Coverage
Coverage
Coverage
Introduction
Code coverage reflects how thorough the HDL code
was exercised. the set of features provided by code
coverage tools usually includes line/block coverage,
arc coverage for state machines, expression
coverage, event coverage and toggle coverage.
There are some limitiation with this approach. they
are,
Overlooking non-implemented features.
The inability to measure the interaction between
multiple modules.
The ability to measure simultaneous events or
sequences of events.
F1 : Functional
F2 : Functional
DUT
F3 : Functional
states
F4 : Functional
DUT
CoverGroup Inside a
Class
As said earlier, covergroup can be embedded inside a
class, interface, or module. When emebedded inside a
class, it allows to generate coverage on subset of class
properties. Important difference between a covergroup in
module and covergroup in class is that, it is optional to
create the instance of covergroup in class. as this is kind
of automatic i.e the coverage group is implicitly declared.
An embedded covergroup can define a coverage model
for protected and local class properties without any
changes to the class data encapsulation. Class members
can become coverage points or can be used in other
coverage constructs, such as conditional guards or option
initialization. A class can have more than one covergroup.
Cross coverage
coverage group can specify cross coverage
between two or more coverage points or
variables. Cross coverage is specified using the
cross construct. When verifying complex
systems it is important that combination of
functional points are verified.
Coverage options
Coverage OptionsLike in Vera, Systemverilog provides ways to control
the behavior of the covergroup, coverpoint and cross. One of the most
common usage of these coverage options is setting weightage of a
covergroup. In a advanced testbench there could be many covergroups,
and from the verification point of view some covergroups have high
priority, and they migh be is less number, on other there hand there
could be covergroups which are of low priority, and they are in large
number. There is no way simulator is going to know this priority
information, so Systemverilog provides options to communicate this to
simulator. This way, even if don't have good coverage on low priority
covegroup, it won't effect overall coverage in big way.
There are two types of options
covergroup instance specific options
All instance specific options