DS3231 Extremely Accurate I2C-Integrated

RTC/TCXO/Crystal

General Description Benefits and Features

The DS3231 is a low-cost, extremely accurate I2C ●● Highly Accurate RTC Completely Manages All
real-time clock (RTC) with an integrated temperature- Timekeeping Functions
compensated crystal oscillator (TCXO) and crystal. • Real-Time Clock Counts Seconds, Minutes, Hours,
The device incorporates a battery input, and maintains Date of the Month, Month, Day of the Week, and
accurate timekeeping when main power to the device Year, with Leap-Year Compensation Valid Up to 2100
is interrupted. The integration of the crystal resonator • Accuracy ±2ppm from 0°C to +40°C
enhances the long-term accuracy of the device as well • Accuracy ±3.5ppm from -40°C to +85°C
as reduces the piece-part count in a manufacturing line. • Digital Temp Sensor Output: ±3°C Accuracy
The DS3231 is available in commercial and industrial • Register for Aging Trim
temperature ranges, and is offered in a 16-pin, 300-mil • RST Output/Pushbutton Reset Debounce Input
SO package. • Two Time-of-Day Alarms
The RTC maintains seconds, minutes, hours, day, date, • Programmable Square-Wave Output Signal
month, and year information. The date at the end of the ●● Simple Serial Interface Connects to Most
month is automatically adjusted for months with fewer Microcontrollers
than 31 days, including corrections for leap year. The • Fast (400kHz) I2C Interface
clock operates in either the 24-hour or 12-hour format ●● Battery-Backup Input for Continuous Timekeeping
with an AM/PM indicator. Two programmable time-of-day • Low Power Operation Extends Battery-Backup
alarms and a programmable square-wave output are Run Time
provided. Address and data are transferred serially • 3.3V Operation
through an I2C bidirectional bus. ●● Operating Temperature Ranges: Commercial
A precision temperature-compensated voltage reference (0°C to +70°C) and Industrial (-40°C to +85°C)
and comparator circuit monitors the status of VCC to ●● Underwriters Laboratories® (UL) Recognized
detect power failures, to provide a reset output, and to
automatically switch to the backup supply when necessary. Applications
Additionally, the RST pin is monitored as a pushbutton ●● Servers ●● Utility Power Meters
input for generating a μP reset. ●● Telematics ●● GPS
Ordering Information and Pin Configuration appear at end of data
sheet.
Typical Operating Circuit
VCC VCC
RPU = tR/CB
VCC

RPU RPU
VCC
SCL SCL INT/SQW
SDA SDA 32kHz
P
RST RST VBAT
DS3231
PUSHBUTTON N.C. N.C.
RESET
N.C. N.C.
N.C. N.C.
N.C. GND N.C.

Underwriters Laboratories is a registered certification mark of

Underwriters Laboratories Inc.

19-5170; Rev 10; 3/15

DS3231 Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal

Absolute Maximum Ratings

Voltage Range on Any Pin Relative to Ground.....-0.3V to +6.0V Junction Temperature.......................................................+125°C
Junction-to-Ambient Thermal Resistance (θJA) (Note 1).73°C/W Storage Temperature Range............................... -40°C to +85°C
Junction-to-Case Thermal Resistance (θJC) (Note 1).....23°C/W Lead Temperature (soldering, 10s).................................. +260°C
Operating Temperature Range Soldering Temperature (reflow, 2 times max).................. +260°C
DS3231S.............................................................0°C to +70°C (see the Handling, PCB Layout, and Assembly section)
DS3231SN....................................................... -40°C to +85°C

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Recommended Operating Conditions

(TA = TMIN to TMAX, unless otherwise noted.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VCC 2.3 3.3 5.5 V
Supply Voltage
VBAT 2.3 3.0 5.5 V
0.7 x VCC +
Logic 1 Input SDA, SCL VIH V
VCC 0.3
0.3 x
Logic 0 Input SDA, SCL VIL -0.3 V
VCC

Electrical Characteristics
(VCC = 2.3V to 5.5V, VCC = Active Supply (see Table 1), TA = TMIN to TMAX, unless otherwise noted.) (Typical values are at VCC =
3.3V, VBAT = 3.0V, and TA = +25°C, unless otherwise noted.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VCC = 3.63V 200
Active Supply Current ICCA (Notes 4, 5) µA
VCC = 5.5V 300

I2C bus inactive, 32kHz VCC = 3.63V 110

Standby Supply Current ICCS output on, SQW output off µA
(Note 5) VCC = 5.5V 170

I2C bus inactive, 32kHz VCC = 3.63V 575

Temperature Conversion Current ICCSCONV µA
output on, SQW output off VCC = 5.5V 650
Power-Fail Voltage VPF 2.45 2.575 2.70 V
Logic 0 Output, 32kHz, INT/SQW,
VOL IOL = 3mA 0.4 V
SDA
Logic 0 Output, RST VOL IOL = 1mA 0.4 V
Output Leakage Current 32kHz,
ILO Output high impedance -1 0 +1 µA
INT/SQW, SDA
Input Leakage SCL ILI -1 +1 µA
RST Pin I/O Leakage IOL RST high impedance (Note 6) -200 +10 µA
VBAT Leakage Current
IBATLKG 25 100 nA
(VCC Active)

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RTC/TCXO/Crystal

Electrical Characteristics (continued)

(VCC = 2.3V to 5.5V, VCC = Active Supply (see Table 1), TA = TMIN to TMAX, unless otherwise noted.) (Typical values are at VCC =
3.3V, VBAT = 3.0V, and TA = +25°C, unless otherwise noted.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Frequency fOUT VCC = 3.3V or VBAT = 3.3V 32.768 kHz

VCC = 3.3V or 0°C to +40°C ±2

Frequency Stability vs.
Δf/fOUT VBAT = 3.3V, ppm
Temperature (Commercial)
aging offset = 00h >40°C to +70°C ±3.5

VCC = 3.3V or -40°C to <0°C ±3.5

Frequency Stability vs.
Δf/fOUT VBAT = 3.3V, 0°C to +40°C ±2 ppm
Temperature (Industrial)
aging offset = 00h >40°C to +85°C ±3.5
Frequency Stability vs. Voltage Δf/V 1 ppm/V
-40°C 0.7
Trim Register Frequency +25°C 0.1
Δf/LSB Specified at: ppm
Sensitivity per LSB +70°C 0.4
+85°C 0.8
Temperature Accuracy Temp VCC = 3.3V or VBAT = 3.3V -3 +3 °C
After reflow, First year ±1.0
Crystal Aging Δf/fO ppm
not production tested 0–10 years ±5.0

Electrical Characteristics
(VCC = 0V, VBAT = 2.3V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

EOSC = 0, BBSQW = 0, VBAT = 3.63V 70
Active Battery Current IBATA µA
SCL = 400kHz (Note 5) VBAT = 5.5V 150
EOSC = 0, BBSQW = 0, VBAT = 3.63V 0.84 3.0
EN32kHz = 1,
Timekeeping Battery Current IBATT µA
SCL = SDA = 0V or
SCL = SDA = VBAT (Note 5) VBAT = 5.5V 1.0 3.5

EOSC = 0, BBSQW = 0, VBAT = 3.63V 575

Temperature Conversion Current IBATTC SCL = SDA = 0V or µA
SCL = SDA = VBAT VBAT = 5.5V 650

Data-Retention Current IBATTDR EOSC = 1, SCL = SDA = 0V, +25°C 100 nA

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RTC/TCXO/Crystal

AC Electrical Characteristics
(VCC = VCC(MIN) to VCC(MAX) or VBAT = VBAT(MIN) to VBAT(MAX), VBAT > VCC, TA = TMIN to TMAX, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Fast mode 100 400
SCL Clock Frequency fSCL kHz
Standard mode 0 100
Bus Free Time Between STOP Fast mode 1.3
tBUF µs
and START Conditions Standard mode 4.7
Hold Time (Repeated) START Fast mode 0.6
tHD:STA µs
Condition (Note 7) Standard mode 4.0
Fast mode 1.3
Low Period of SCL Clock tLOW µs
Standard mode 4.7
Fast mode 0.6
High Period of SCL Clock tHIGH µs
Standard mode 4.0
Fast mode 0 0.9
Data Hold Time (Notes 8, 9) tHD:DAT µs
Standard mode 0 0.9
Fast mode 100
Data Setup Time (Note 10) tSU:DAT ns
Standard mode 250
Fast mode 0.6
START Setup Time tSU:STA µs
Standard mode 4.7
Rise Time of Both SDA and SCL Fast mode 20 + 300
tR ns
Signals (Note 11) Standard mode 0.1CB 1000
Fall Time of Both SDA and SCL Fast mode 20 + 300
tF ns
Signals (Note 11) Standard mode 0.1CB 300
Fast mode 0.6
Setup Time for STOP Condition tSU:STO µs
Standard mode 4.7
Capacitive Load for Each Bus
CB (Note 11) 400 pF
Line
Capacitance for SDA, SCL CI/O 10 pF
Pulse Width of Spikes That Must
tSP 30 ns
Be Suppressed by the Input Filter
Pushbutton Debounce PBDB 250 ms
Reset Active Time tRST 250 ms
Oscillator Stop Flag (OSF) Delay tOSF (Note 12) 100 ms
Temperature Conversion Time tCONV 125 200 ms

Power-Switch Characteristics
(TA = TMIN to TMAX)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VCC Fall Time; VPF(MAX) to
tVCCF 300 µs
VPF(MIN)
VCC Rise Time; VPF(MIN) to
tVCCR 0 µs
VPF(MAX)
Recovery at Power-Up tREC (Note 13) 250 300 ms

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RTC/TCXO/Crystal

Pushbutton Reset Timing

RST

PBDB tRST

Power-Switch Timing

VCC
VPF(MAX)
VPF VPF
VPF(MIN)

tVCCF tVCCR

tREC

RST

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DS3231 Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal

Data Transfer on I2C Serial Bus

SDA

tBUF tSP
tHD:STA
tLOW tF
tR

SCL

tHD:STA tHIGH tSU:STA

tSU:STO
STOP START tSU:DAT REPEATED
START
tHD:DAT

WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
Note 2: Limits at -40°C are guaranteed by design and not production tested.
Note 3: All voltages are referenced to ground.
Note 4: ICCA—SCL clocking at max frequency = 400kHz.
Note 5: Current is the averaged input current, which includes the temperature conversion current.
Note 6: The RST pin has an internal 50kΩ (nominal) pullup resistor to VCC.
Note 7: After this period, the first clock pulse is generated.
Note 8: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL sig-
nal) to bridge the undefined region of the falling edge of SCL.
Note 9: The maximum tHD:DAT needs only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 10: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must then be met. This
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
Note 11: CB—total capacitance of one bus line in pF.
Note 12: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range
of 0.0V ≤ VCC ≤ VCC(MAX) and 2.3V ≤ VBAT ≤ 3.4V.
Note 13: This delay applies only if the oscillator is enabled and running. If the EOSC bit is a 1, tREC is bypassed and RST immedi-
ately goes high. The state of RST does not affect the I2C interface, RTC, or TCXO.

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DS3231 Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal

Typical Operating Characteristics

(VCC = +3.3V, TA = +25°C, unless otherwise noted.)

STANDBY SUPPLY CURRENT SUPPLY CURRENT

vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
150 1.2

DS3231 toc01

DS3231 toc02
BSY = 0, SCL = SDA = VCC VCC = 0V, BSY = 0,
SDA = SCL = VBAT OR VCC
125 1.1
RST ACTIVE

100 1.0
EN32kHz = 1
ICCS (µA)

IBAT (µA)
75 0.9
EN32kHz = 0
50 0.8

25 0.7

0 0.6
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.3 3.3 4.3 5.3
VCC (V) VBAT (V)

SUPPLY CURRENT FREQUENCY DEVIATION

vs. TEMPERATURE vs. TEMPERATURE vs. AGING VALUE
1.0
DS3231 toc03

DS3231 toc04
VCC = 0, EN32kHz = 1, BSY = 0, 60
SDA = SCL = VBAT OR GND 50 -128
FREQUENCY DEVIATION (ppm)

0.9 40 -33
30
IBAT (µA)

20 0
0.8 10
0
-10
0.7
-20 32
127
-30
0.6 -40
-40 -15 10 35 60 85 -40 -15 10 35 60 85
TEMPERATURE (°C) TEMPERATURE (°C)
DELTA TIME AND FREQUENCY
vs. TEMPERATURE
DS3231 toc05
20
0 0
-20 CRYSTAL
DELTA FREQUENCY (ppm)

+20ppm
DELTA TIME (MIN/YEAR)

-40 -20
-60 TYPICAL CRYSTAL,
UNCOMPENSATED
-80 -40
-100 DS3231
CRYSTAL
-120 ACCURACY -60
-20ppm
BAND
-140
-160 -80
-180
-200 -100
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)

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DS3231 Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal

Block Diagram

32kHz
OSCILLATOR AND
X1
CAPACITOR ARRAY N

CONTROL LOGIC/ SQUARE-WAVE BUFFER;

DIVIDER INT/SQW CONTROL INT/SQW
X2
1Hz
N

VCC
VBAT TEMPERATURE ALARM, STATUS, AND
POWER CONTROL
SENSOR CONTROL REGISTERS
GND

1Hz
CLOCK AND CALENDAR
REGISTERS
SCL
I2C INTERFACE AND
ADDRESS REGISTER
DECODE USER BUFFER
SDA
(7 BYTES)
VCC

VOLTAGE REFERENCE; RST

DEBOUNCE CIRCUIT;
DS3231
PUSHBUTTON RESET N

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DS3231 Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal

Pin Description
PIN NAME FUNCTION
32kHz Output. This open-drain pin requires an external pullup resistor. When enabled, the output operates on
1 32kHz
either power supply. It may be left open if not used.
DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1µF to 1.0µF capacitor.
2 VCC
If not used, connect to ground.

Active-Low Interrupt or Square-Wave Output. This open-drain pin requires an external pullup resistor connected
to a supply at 5.5V or less. This multifunction pin is determined by the state of the INTCN bit in the Control
Register (0Eh). When INTCN is set to logic 0, this pin outputs a square wave and its frequency is determined by
3 INT/SQW RS2 and RS1 bits. When INTCN is set to logic 1, then a match between the timekeeping registers and either of
the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the INTCN bit is set to logic 1
when power is first applied, the pin defaults to an interrupt output with alarms disabled. The pullup voltage can
be up to 5.5V, regardless of the voltage on VCC. If not used, this pin can be left unconnected.

Active-Low Reset. This pin is an open-drain input/output. It indicates the status of VCC relative to the
VPF specification. As VCC falls below VPF, the RST pin is driven low. When VCC exceeds VPF, for tRST, the
RST pin is pulled high by the internal pullup resistor. The active-low, open-drain output is combined with a
4 RST
debounced pushbutton input function. This pin can be activated by a pushbutton reset request. It has an internal
50kΩ nominal value pullup resistor to VCC. No external pullup resistors should be connected. If the oscillator is
disabled, tREC is bypassed and RST immediately goes high.

5–12 N.C. No Connection. Must be connected to ground.

13 GND Ground
Backup Power-Supply Input. When using the device with the VBAT input as the primary power source, this pin
should be decoupled using a 0.1µF to 1.0µF low-leakage capacitor. When using the device with the VBAT input
14 VBAT as the backup power source, the capacitor is not required. If VBAT is not used, connect to ground. The device is
UL recognized to ensure against reverse charging when used with a primary lithium battery.
Go to www.maximintegrated.com/qa/info/ul.

Serial Data Input/Output. This pin is the data input/output for the I2C serial interface. This open-drain pin
15 SDA
requires an external pullup resistor. The pullup voltage can be up to 5.5V, regardless of the voltage on VCC.
Serial Clock Input. This pin is the clock input for the I2C serial interface and is used to synchronize data
16 SCL
movement on the serial interface. Up to 5.5V can be used for this pin, regardless of the voltage on VCC.

Detailed Description year. The clock operates in either the 24-hour or 12-hour
The DS3231 is a serial RTC driven by a temperature- format with an AM/PM indicator. The internal registers are
compensated 32kHz crystal oscillator. The TCXO provides accessible though an I2C bus interface.
a stable and accurate reference clock, and maintains the A temperature-compensated voltage reference and com-
RTC to within ±2 minutes per year accuracy from -40°C parator circuit monitors the level of VCC to detect power fail-
to +85°C. The TCXO frequency output is available at the ures and to automatically switch to the backup supply when
32kHz pin. The RTC is a low-power clock/calendar with necessary. The RST pin provides an external pushbutton
two programmable time-of-day alarms and a programma- function and acts as an indicator of a power-fail event.
ble square-wave output. The INT/SQW provides either an
interrupt signal due to alarm conditions or a square-wave
Operation
output. The clock/calendar provides seconds, minutes, The block diagram shows the main elements of the
hours, day, date, month, and year information. The date at DS3231. The eight blocks can be grouped into four func-
the end of the month is automatically adjusted for months tional groups: TCXO, power control, pushbutton function,
with fewer than 31 days, including corrections for leap and RTC. Their operations are described separately in the
following sections.

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DS3231 Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal

32kHz TCXO is powered by VBAT and the serial interface is active,

The temperature sensor, oscillator, and control logic form active battery current, IBATA, is drawn. When the seri-
the TCXO. The controller reads the output of the on-chip al interface is inactive, timekeeping current (IBATT),
temperature sensor and uses a lookup table to determine which includes the averaged temperature conversion
the capacitance required, adds the aging correction in current, IBATTC, is used (refer to Application Note 3644:
AGE register, and then sets the capacitance selection reg- Power Considerations for Accurate Real-Time Clocks
isters. New values, including changes to the AGE register, for details). Temperature conversion current, IBATTC, is
are loaded only when a change in the temperature value specified since the system must be able to support the
occurs, or when a user-initiated temperature conversion periodic higher current pulse and still maintain a valid volt-
is completed. Temperature conversion occurs on initial age level. Data retention current, IBATTDR, is the current
application of VCC and once every 64 seconds afterwards. drawn by the part when the oscillator is stopped (EOSC
= 1). This mode can be used to minimize battery require-
Power Control ments for times when maintaining time and date informa-
This function is provided by a temperature-compensated tion is not necessary, e.g., while the end system is waiting
voltage reference and a comparator circuit that monitors to be shipped to a customer.
the VCC level. When VCC is greater than VPF, the part is
powered by VCC. When VCC is less than VPF but greater
Pushbutton Reset Function
than VBAT, the DS3231 is powered by VCC. If VCC is less The DS3231 provides for a pushbutton switch to be con-
than VPF and is less than VBAT, the device is powered by nected to the RST output pin. When the DS3231 is not in
VBAT. See Table 1. a reset cycle, it continuously monitors the RST signal for
a low going edge. If an edge transition is detected, the
Table 1. Power Control DS3231 debounces the switch by pulling the RST low.
After the internal timer has expired (PBDB), the DS3231
SUPPLY CONDITION ACTIVE SUPPLY continues to monitor the RST line. If the line is still low,
VCC < VPF, VCC < VBAT VBAT the DS3231 continuously monitors the line looking for a
VCC < VPF, VCC > VBAT VCC rising edge. Upon detecting release, the DS3231 forces
the RST pin low and holds it low for tRST.
VCC > VPF, VCC < VBAT VCC
VCC > VPF, VCC > VBAT VCC RST is also used to indicate a power-fail condition. When
VCC is lower than VPF, an internal power-fail signal is
To preserve the battery, the first time VBAT is applied generated, which forces the RST pin low. When VCC
to the device, the oscillator will not start up until VCC returns to a level above VPF, the RST pin is held low for
exceeds VPF, or until a valid I2C address is written to approximately 250ms (tREC) to allow the power supply
the part. Typical oscillator startup time is less than one to stabilize. If the oscillator is not running (see the Power
second. Approximately 2 seconds after VCC is applied, Control section) when VCC is applied, tREC is bypassed
or a valid I2C address is written, the device makes a and RST immediately goes high. Assertion of the RST
temperature measurement and applies the calculated output, whether by pushbutton or power-fail detection,
correction to the oscillator. Once the oscillator is running, does not affect the internal operation of the DS3231.
it continues to run as long as a valid power source is avail- Real-Time Clock
able (VCC or VBAT), and the device continues to measure
With the clock source from the TCXO, the RTC provides
the temperature and correct the oscillator frequency every
seconds, minutes, hours, day, date, month, and year
64 seconds.
information. The date at the end of the month is automati-
On the first application of power (VCC) or when a valid I2C cally adjusted for months with fewer than 31 days, includ-
address is written to the part (VBAT), the time and date ing corrections for leap year. The clock operates in either
registers are reset to 01/01/00 01 00:00:00 (DD/MM/YY the 24-hour or 12-hour format with an AM/PM indicator.
DOW HH:MM:SS).
The clock provides two programmable time-of-day alarms
VBAT Operation and a programmable square-wave output. The INT/SQW
pin either generates an interrupt due to alarm condition
There are several modes of operation that affect the or outputs a square-wave signal and the selection is con-
amount of VBAT current that is drawn. While the device trolled by the bit INTCN.

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BIT 7 BIT 0
ADDRESS BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 FUNCTION RANGE
MSB LSB
00h 0 10 Seconds Seconds Seconds 00–59
01h 0 10 Minutes Minutes Minutes 00–59
AM/PM 1–12 + AM/PM
02h 0 12/24 10 Hour Hour Hours
20 Hour 00–23
03h 0 0 0 0 0 Day Day 1–7
04h 0 0 10 Date Date Date 01–31
Month/
05h Century 0 0 10 Month Month 01–12 + Century
Century
06h 10 Year Year Year 00–99
07h A1M1 10 Seconds Seconds Alarm 1 Seconds 00–59
08h A1M2 10 Minutes Minutes Alarm 1 Minutes 00–59
AM/PM 1–12 + AM/PM
09h A1M3 12/24 10 Hour Hour Alarm 1 Hours
20 Hour 00–23
Day Alarm 1 Day 1–7
0Ah A1M4 DY/DT 10 Date
Date Alarm 1 Date 1–31
0Bh A2M2 10 Minutes Minutes Alarm 2 Minutes 00–59
AM/PM 1–12 + AM/PM
0Ch A2M3 12/24 10 Hour Hour Alarm 2 Hours
20 Hour 00–23
Day Alarm 2 Day 1–7
0Dh A2M4 DY/DT 10 Date
Date Alarm 2 Date 1–31
0Eh EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE Control —
0Fh OSF 0 0 0 EN32kHz BSY A2F A1F Control/Status —
10h SIGN DATA DATA DATA DATA DATA DATA DATA Aging Offset —
11h SIGN DATA DATA DATA DATA DATA DATA DATA MSB of Temp —
12h DATA DATA 0 0 0 0 0 0 LSB of Temp —
Figure 1. Timekeeping Registers
Note: Unless otherwise specified, the registers’ state is not defined when power is first applied.

Address Map to the DS3231 resets because of a loss of VCC or other

Figure 1 shows the address map for the DS3231 time- event, it is possible that the microcontroller and DS3231
keeping registers. During a multibyte access, when the I2C communications could become unsynchronized, e.g.,
address pointer reaches the end of the register space the microcontroller resets while reading data from the
(12h), it wraps around to location 00h. On an I2C START DS3231. When the microcontroller resets, the DS3231
or address pointer incrementing to location 00h, the cur- I2C interface may be placed into a known state by tog-
rent time is transferred to a second set of registers. The gling SCL until SDA is observed to be at a high level. At
time information is read from these secondary registers, that point the microcontroller should pull SDA low while
while the clock may continue to run. This eliminates the SCL is high, generating a START condition.
need to reread the registers in case the main registers
update during a read.
Clock and Calendar
The time and calendar information is obtained by reading
I2C Interface the appropriate register bytes. Figure 1 illustrates the RTC
The I2C interface is accessible whenever either VCC or registers. The time and calendar data are set or initialized
VBAT is at a valid level. If a microcontroller connected by writing the appropriate register bytes. The contents of
the time and calendar registers are in the binary-coded

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DS3231 Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal

decimal (BCD) format. The DS3231 can be run in either Alarms

12-hour or 24-hour mode. Bit 6 of the hours register is The DS3231 contains two time-of-day/date alarms.
defined as the 12- or 24-hour mode select bit. When high, Alarm 1 can be set by writing to registers 07h to 0Ah.
the 12-hour mode is selected. In the 12-hour mode, bit 5 Alarm 2 can be set by writing to registers 0Bh to 0Dh.
is the AM/PM bit with logic-high being PM. In the 24-hour The alarms can be programmed (by the alarm enable
mode, bit 5 is the 20-hour bit (20–23 hours). The century and INTCN bits of the control register) to activate the
bit (bit 7 of the month register) is toggled when the years INT/SQW output on an alarm match condition. Bit 7 of
register overflows from 99 to 00. each of the time-of-day/date alarm registers are mask
The day-of-week register increments at midnight. Values bits (Table 2). When all the mask bits for each alarm
that correspond to the day of week are user-defined but are logic 0, an alarm only occurs when the values in
must be sequential (i.e., if 1 equals Sunday, then 2 equals the timekeeping registers match the corresponding val-
Monday, and so on). Illogical time and date entries result ues stored in the time-of-day/date alarm registers. The
in undefined operation. alarms can also be programmed to repeat every second,
When reading or writing the time and date registers, sec- minute, hour, day, or date. Table 2 shows the possible
ondary (user) buffers are used to prevent errors when the settings. Configurations not listed in the table will result
internal registers update. When reading the time and date in illogical operation.
registers, the user buffers are synchronized to the internal The DY/DT bits (bit 6 of the alarm day/date registers)
registers on any START and when the register pointer control whether the alarm value stored in bits 0 to 5 of
rolls over to zero. The time information is read from these that register reflects the day of the week or the date of
secondary registers, while the clock continues to run. This the month. If DY/DT is written to logic 0, the alarm will be
eliminates the need to reread the registers in case the the result of a match with date of the month. If DY/DT is
main registers update during a read. written to logic 1, the alarm will be the result of a match
The countdown chain is reset whenever the seconds with day of the week.
register is written. Write transfers occur on the acknowl- When the RTC register values match alarm register set-
edge from the DS3231. Once the countdown chain is tings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is
reset, to avoid rollover issues the remaining time and set to logic 1. If the corresponding Alarm Interrupt Enable
date registers must be written within 1 second. The 1Hz ‘A1IE’ or ‘A2IE’ is also set to logic 1 and the INTCN bit
square-wave output, if enabled, transitions high 500ms is set to logic 1, the alarm condition will activate the
after the seconds data transfer, provided the oscillator is INT/SQW signal. The match is tested on the once-per-
already running. second update of the time and date registers.

Table 2. Alarm Mask Bits

ALARM 1 REGISTER MASK BITS (BIT 7)
DY/DT ALARM RATE
A1M4 A1M3 A1M2 A1M1
X 1 1 1 1 Alarm once per second
X 1 1 1 0 Alarm when seconds match
X 1 1 0 0 Alarm when minutes and seconds match
X 1 0 0 0 Alarm when hours, minutes, and seconds match
0 0 0 0 0 Alarm when date, hours, minutes, and seconds match
1 0 0 0 0 Alarm when day, hours, minutes, and seconds match

ALARM 2 REGISTER MASK BITS (BIT 7)

DY/DT ALARM RATE
A2M4 A2M3 A2M2
X 1 1 1 Alarm once per minute (00 seconds of every minute)
X 1 1 0 Alarm when minutes match
X 1 0 0 Alarm when hours and minutes match
0 0 0 0 Alarm when date, hours, and minutes match
1 0 0 0 Alarm when day, hours, and minutes match

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Control Register (0Eh)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NAME: EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE
POR: 0 0 0 1 1 1 0 0

Special-Purpose Registers the square wave has been enabled. The following table
The DS3231 has two additional registers (control and sta- shows the square-wave frequencies that can be selected
tus) that control the real-time clock, alarms, and square- with the RS bits. These bits are both set to logic 1
wave output. (8.192kHz) when power is first applied.

Control Register (0Eh) SQUARE-WAVE OUTPUT FREQUENCY

Bit 7: Enable Oscillator (EOSC). When set to logic 0, SQUARE-WAVE OUTPUT
the oscillator is started. When set to logic 1, the oscillator RS2 RS1
FREQUENCY
is stopped when the DS3231 switches to VBAT. This bit
0 0 1Hz
is clear (logic 0) when power is first applied. When the
DS3231 is powered by VCC, the oscillator is always on 0 1 1.024kHz
regardless of the status of the EOSC bit. When EOSC is 1 0 4.096kHz
disabled, all register data is static. 1 1 8.192kHz
Bit 6: Battery-Backed Square-Wave Enable (BBSQW).
When set to logic 1 with INTCN = 0 and VCC < VPF, this Bit 2: Interrupt Control (INTCN). This bit controls the
bit enables the square wave. When BBSQW is logic 0, INT/SQW signal. When the INTCN bit is set to logic 0,
the INT/SQW pin goes high impedance when VCC < VPF. a square wave is output on the INT/SQW pin. When the
This bit is disabled (logic 0) when power is first applied. INTCN bit is set to logic 1, then a match between the time-
keeping registers and either of the alarm registers acti-
Bit 5: Convert Temperature (CONV). Setting this bit to
vates the INT/SQW output (if the alarm is also enabled).
1 forces the temperature sensor to convert the tempera-
The corresponding alarm flag is always set regardless of
ture into digital code and execute the TCXO algorithm to
the state of the INTCN bit. The INTCN bit is set to logic 1
update the capacitance array to the oscillator. This can
when power is first applied.
only happen when a conversion is not already in prog-
ress. The user should check the status bit BSY before Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to
forcing the controller to start a new TCXO execution. A logic 1, this bit permits the alarm 2 flag (A2F) bit in the
user-initiated temperature conversion does not affect the status register to assert INT/SQW (when INTCN = 1).
internal 64-second update cycle. When the A2IE bit is set to logic 0 or INTCN is set to logic
0, the A2F bit does not initiate an interrupt signal. The
A user-initiated temperature conversion does not affect
A2IE bit is disabled (logic 0) when power is first applied.
the BSY bit for approximately 2ms. The CONV bit remains
at a 1 from the time it is written until the conversion is Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to
finished, at which time both CONV and BSY go to 0. The logic 1, this bit permits the alarm 1 flag (A1F) bit in the
CONV bit should be used when monitoring the status of a status register to assert INT/SQW (when INTCN = 1).
user-initiated conversion. When the A1IE bit is set to logic 0 or INTCN is set to logic
0, the A1F bit does not initiate the INT/SQW signal. The
Bits 4 and 3: Rate Select (RS2 and RS1). These bits
A1IE bit is disabled (logic 0) when power is first applied.
control the frequency of the square-wave output when

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DS3231 Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal

Status Register (0Fh)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NAME: OSF 0 0 0 EN32kHz BSY A2F A1F
POR: 1 0 0 0 1 X X X

Status Register (0Fh) A1IE bit is logic 1 and the INTCN bit is set to logic 1, the
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indi- INT/SQW pin is also asserted. A1F is cleared when written
cates that the oscillator either is stopped or was stopped to logic 0. This bit can only be written to logic 0. Attempting
for some period and may be used to judge the validity of to write to logic 1 leaves the value unchanged.
the timekeeping data. This bit is set to logic 1 any time
that the oscillator stops. The following are examples of Aging Offset
conditions that can cause the OSF bit to be set: The aging offset register takes a user-provided value to
add to or subtract from the codes in the capacitance array
1) The first time power is applied.
registers. The code is encoded in two’s complement, with
2) The voltages present on both VCC and VBAT are insuf- bit 7 representing the sign bit. One LSB represents one
ficient to support oscillation. small capacitor to be switched in or out of the capacitance
3) The EOSC bit is turned off in battery-backed mode. array at the crystal pins. The aging offset register capaci-
tance value is added or subtracted from the capacitance
4) External influences on the crystal (i.e., noise, leakage,
value that the device calculates for each temperature
etc.).
compensation. The offset register is added to the capaci-
This bit remains at logic 1 until written to logic 0. tance array during a normal temperature conversion, if
Bit 3: Enable 32kHz Output (EN32kHz). This bit con- the temperature changes from the previous conversion, or
trols the status of the 32kHz pin. When set to logic 1, the during a manual user conversion (setting the CONV bit).
32kHz pin is enabled and outputs a 32.768kHz square- To see the effects of the aging register on the 32kHz out-
wave signal. When set to logic 0, the 32kHz pin goes to a put frequency immediately, a manual conversion should
high-impedance state. The initial power-up state of this bit be started after each aging register change.
is logic 1, and a 32.768kHz square-wave signal appears Positive aging values add capacitance to the array, slow-
at the 32kHz pin after a power source is applied to the ing the oscillator frequency. Negative values remove
DS3231 (if the oscillator is running). capacitance from the array, increasing the oscillator
Bit 2: Busy (BSY). This bit indicates the device is busy frequency.
executing TCXO functions. It goes to logic 1 when the con- The change in ppm per LSB is different at different tem-
version signal to the temperature sensor is asserted and peratures. The frequency vs. temperature curve is shifted
then is cleared when the device is in the 1-minute idle state. by the values used in this register. At +25°C, one LSB
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag bit typically provides about 0.1ppm change in frequency.
indicates that the time matched the alarm 2 registers. If the Use of the aging register is not needed to achieve the
A2IE bit is logic 1 and the INTCN bit is set to logic 1, the accuracy as defined in the EC tables, but could be used
INT/SQW pin is also asserted. A2F is cleared when written to help compensate for aging at a given temperature.
to logic 0. This bit can only be written to logic 0. Attempting See the Typical Operating Characteristics section for a
to write to logic 1 leaves the value unchanged. graph showing the effect of the register on accuracy over
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag bit temperature.
indicates that the time matched the alarm 1 registers. If the

Aging Offset (10h)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NAME: Sign Data Data Data Data Data Data Data
POR: 0 0 0 0 0 0 0 0

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Temperature Register (Upper Byte) (11h)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NAME: Sign Data Data Data Data Data Data Data
POR: 0 0 0 0 0 0 0 0

Temperature Register (Lower Byte) (12h)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NAME: Data Data 0 0 0 0 0 0
POR: 0 0 0 0 0 0 0 0

Temperature Registers (11h–12h) line while the clock line is high are interpreted as con-
Temperature is represented as a 10-bit code with a trol signals.
resolution of 0.25°C and is accessible at location 11h and Accordingly, the following bus conditions have been
12h. The temperature is encoded in two’s complement defined:
format. The upper 8 bits, the integer portion, are at loca- Bus not busy: Both data and clock lines remain high.
tion 11h and the lower 2 bits, the fractional portion, are in
START data transfer: A change in the state of the
the upper nibble at location 12h. For example, 00011001
data line from high to low, while the clock line is high,
01b = +25.25°C. Upon power reset, the registers are set
defines a START condition.
to a default temperature of 0°C and the controller starts
a temperature conversion. The temperature is read on STOP data transfer: A change in the state of the
initial application of VCC or I2C access on VBAT and once data line from low to high, while the clock line is high,
every 64 seconds afterwards. The temperature registers defines a STOP condition.
are updated after each user-initiated conversion and on Data valid: The state of the data line represents valid
every 64-second conversion. The temperature registers data when, after a START condition, the data line is
are read-only. stable for the duration of the high period of the clock
signal. The data on the line must be changed during
I2C Serial Data Bus the low period of the clock signal. There is one clock
The DS3231 supports a bidirectional I2C bus and data pulse per bit of data.
transmission protocol. A device that sends data onto the Each data transfer is initiated with a START condition
bus is defined as a transmitter and a device receiving data and terminated with a STOP condition. The number
is defined as a receiver. The device that controls the mes- of data bytes transferred between the START and the
sage is called a master. The devices that are controlled STOP conditions is not limited, and is determined by
by the master are slaves. The bus must be controlled by the master device. The information is transferred byte-
a master device that generates the serial clock (SCL), wise and each receiver acknowledges with a ninth bit.
controls the bus access, and generates the START and
STOP conditions. The DS3231 operates as a slave on the Acknowledge: Each receiving device, when
I2C bus. Connections to the bus are made through the addressed, is obliged to generate an acknowledge
SCL input and open-drain SDA I/O lines. Within the bus after the reception of each byte. The master device
specifications, a standard mode (100kHz maximum clock must generate an extra clock pulse, which is associ-
rate) and a fast mode (400kHz maximum clock rate) are ated with this acknowledge bit.
defined. The DS3231 works in both modes. A device that acknowledges must pull down the SDA
The following bus protocol has been defined (Figure 2): line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
● Data transfer may be initiated only when the bus is not the acknowledge-related clock pulse. Of course, setup
busy. and hold times must be taken into account. A master
● During data transfer, the data line must remain stable must signal an end of data to the slave by not generat-
whenever the clock line is high. Changes in the data

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DS3231 Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal

MSB FIRST MSB LSB MSB LSB

SDA

SLAVE R/W ACK DATA ACK DATA ACK/

ADDRESS NACK

SCL 1–7 8 9 1–7 8 9 1–7 8 9

IDLE START REPEATED IF MORE BYTES

CONDITION ARE TRANSFERRED STOP CONDITION
REPEATED START

Figure 2. I2C Data Transfer Overview

ing an acknowledge bit on the last byte that has been is the slave address. Next follows a number of data
clocked out of the slave. In this case, the slave must bytes. The slave returns an acknowledge bit after each
leave the data line high to enable the master to gener- received byte. Data is transferred with the most signifi-
ate the STOP condition. cant bit (MSB) first.
Figures 3 and 4 detail how data transfer is accomplished Data transfer from a slave transmitter to a master
on the I2C bus. Depending upon the state of the R/W bit, receiver. The first byte (the slave address) is transmit-
two types of data transfer are possible: ted by the master. The slave then returns an acknowl-
Data transfer from a master transmitter to a slave edge bit. Next follows a number of data bytes transmit-
receiver. The first byte transmitted by the master ted by the slave to the master. The master returns an
acknowledge bit after all received bytes other than the

<SLAVE
ADDRESS> <R/W> <WORD ADDRESS (n)> <DATA (n)> <DATA (n + 1)> <DATA (n + X)

S 1101000 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A ... XXXXXXXX A P

S - START
SLAVE TO MASTER MASTER TO SLAVE
A - ACKNOWLEDGE (ACK)
P - STOP DATA TRANSFERRED
R/W - READ/WRITE OR DIRECTION BIT ADDRESS (X + 1 BYTES + ACKNOWLEDGE)

Figure 3. Data Write—Slave Receiver Mode

<SLAVE
ADDRESS> <R/W> <DATA (n)> <DATA (n + 1)> <DATA (n + 2)> <DATA (n + X)>

S 1101000 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A ... XXXXXXXX A P

MASTER TO SLAVE SLAVE TO MASTER

S - START
A - ACKNOWLEDGE (ACK) DATA TRANSFERRED
P - STOP (X + 1 BYTES + ACKNOWLEDGE)
A - NOT ACKNOWLEDGE (NACK) NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
R/W - READ/WRITE OR DIRECTION BIT ADDRESS

Figure 4. Data Read—Slave Transmitter Mode

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DS3231 Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal

<SLAVE
ADDRESS><R/W> <WORD ADDRESS (n)> <SLAVE ADDRESS (n)><R/W>

S 1101000 0 A XXXXXXXX A Sr 1101000 1 A

<DATA (n)> <DATA (n + 1)> <DATA (n + 2)> <DATA (n + X)>

XXXXXXXX A XXXXXXXX A XXXXXXXX A ... XXXXXXXX A P

S - START MASTER TO SLAVE SLAVE TO MASTER

Sr - REPEATED START
A - ACKNOWLEDGE (ACK) DATA TRANSFERRED
P - STOP (X + 1 BYTES + ACKNOWLEDGE)
A - NOT ACKNOWLEDGE (NACK) NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
R/W - READ/WRITE OR DIRECTION BIT ADDRESS

Figure 5. Data Write/Read (Write Pointer, Then Read)—Slave Receive and Transmit

last byte. At the end of the last received byte, a not transfer. The master may then transmit zero or more
acknowledge is returned. bytes of data, with the DS3231 acknowledging each
The master device generates all the serial clock pulses byte received. The register pointer increments after
and the START and STOP conditions. A transfer each data byte is transferred. The master generates a
is ended with a STOP condition or with a repeated STOP condition to terminate the data write.
START condition. Since a repeated START condition Slave transmitter mode (DS3231 read mode): The
is also the beginning of the next serial transfer, the bus first byte is received and handled as in the slave
will not be released. Data is transferred with the most receiver mode. However, in this mode, the direction
significant bit (MSB) first. bit indicates that the transfer direction is reversed.
The DS3231 can operate in the following two modes: Serial data is transmitted on SDA by the DS3231 while
the serial clock is input on SCL. START and STOP
Slave receiver mode (DS3231 write mode): Serial conditions are recognized as the beginning and end
data and clock are received through SDA and SCL. of a serial transfer. Address recognition is performed
After each byte is received, an acknowledge bit is by hardware after reception of the slave address and
transmitted. START and STOP conditions are recog- direction bit. The slave address byte is the first byte
nized as the beginning and end of a serial transfer. received after the master generates a START condi-
Address recognition is performed by hardware after tion. The slave address byte contains the 7-bit DS3231
reception of the slave address and direction bit. The address, which is 1101000, followed by the direction
slave address byte is the first byte received after the bit (R/W), which is 1 for a read. After receiving and
master generates the START condition. The slave decoding the slave address byte, the DS3231 outputs
address byte contains the 7-bit DS3231 address, an acknowledge on SDA. The DS3231 then begins to
which is 1101000, followed by the direction bit (R/W), transmit data starting with the register address pointed
which is 0 for a write. After receiving and decoding the to by the register pointer. If the register pointer is not
slave address byte, the DS3231 outputs an acknowl- written to before the initiation of a read mode, the first
edge on SDA. After the DS3231 acknowledges the address that is read is the last one stored in the regis-
slave address + write bit, the master transmits a word ter pointer. The DS3231 must receive a not acknowl-
address to the DS3231. This sets the register pointer edge to end a read.
on the DS3231, with the DS3231 acknowledging the

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DS3231 Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal

Handling, PCB Layout, and Assembly signal line. All N.C. (no connect) pins must be connected
The DS3231 package contains a quartz tuning-fork to ground.
crystal. Pick-and-place equipment can be used, but Moisture-sensitive packages are shipped from the
precautions should be taken to ensure that factory dry packed. Handling instructions listed on the
excessive shocks are avoided. Ultrasonic cleaning should be package label must be followed to prevent damage during
avoided to prevent damage to the crystal. reflow. Refer to the IPC/JEDEC J-STD-020 standard for
Avoid running signal traces under the package, unless moisture-sensitive device (MSD) classifications and reflow
a ground plane is placed between the package and the profiles. Exposure to reflow is limited to 2 times maximum.

Pin Configuration Ordering Information

PART TEMP RANGE PIN-PACKAGE
TOP VIEW
DS3231S# 0°C to +70°C 16 SO
DS3231SN# -40°C to +85°C 16 SO
32kHz 1 16 SCL
#Denotes an RoHS-compliant device that may include lead
VCC 2 15 SDA (Pb) that is exempt under RoHS requirements. The lead finish
INT/SQW 3 14 VBAT
is JESD97 category e3, and is compatible with both lead-based
and lead-free soldering processes. A “#” anywhere on the top
RST 4 DS3231 13 GND mark denotes an RoHS-compliant device.
N.C. 5 12 N.C.

N.C. 6 11 N.C.
N.C. 7 10 N.C.
Package Information
For the latest package outline information and land patterns
N.C. 8 9 N.C.
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
SO
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.

PACKAGE PACKAGE OUTLINE LAND

Chip Information TYPE CODE NO. PATTERN NO.
SUBSTRATE CONNECTED TO GROUND 16 SO W16#H2 21-0042 90-0107
PROCESS: CMOS

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DS3231 Extremely Accurate I2C-Integrated
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Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 1/05 Initial release. —
Changed Digital Temp Sensor Output from ±2°C to ±3°C. 1, 3
Updated Typical Operating Circuit. 1
1 2/05
Changed TA = -40°C to +85°C to TA = TMIN to TMAX. 2, 3, 4
Updated Block Diagram. 8
Added “UL Recognized” to Features; added lead-free packages and removed S from top
mark info in Ordering Information table; added ground connections to the N.C. pin in the 1
Typical Operating Circuit.
Added “noncondensing” to operating temperature range; changed VPF MIN from 2.35V to
2
2.45V.
Added aging offset specification. 3
Relabeled TOC4. 7
Added arrow showing input on X1 in the Block Diagram. 8
Updated pin descriptions for VCC and VBAT. 9
2 6/05
Added the I2C Interface section. 10
Figure 1: Added sign bit to aging and temperature registers; added MSB and LSB. 11
Corrected title for rate select bits frequency table. 13
Added note that frequency stability over temperature spec is with aging offset register =
14
00h; changed bit 7 from Data to Sign (Crystal Aging Offset Register).
Changed bit 7 from Data to Sign (Temperature Register); correct pin definitions in I2C
15
Serial Data Bus section.
Modified the Handing, PC Board Layout, and Assembly section to refer to
17
J-STD-020 for reflow profiles for lead-free and leaded packages.
3 11/05 Changed lead-free packages to RoHS-compliant packages. 1
Changed RST and UL bullets in Features. 1
Changed EC condition “VCC > VBAT” to “VCC = Active Supply (see Table 1).” 2, 3
Modified Note 12 to correct tREC operation. 6
Added various conditions text to TOCs 1, 2, and 3. 7
Added text to pin descriptions for 32kHz, VCC, and RST. 9
4 10/06 Table 1: Changed column heading “Powered By” to “Active Supply”; changed “applied” to
10
“exceeds VPF” in the Power Control section.
Indicated BBSQW applies to both SQW and interrupts; simplified temp convert
13
description (bit 5); added “output” to INT/SQW (bit 2).
Changed the Crystal Aging section to the Aging Offset section; changed “this bit
14
indicates” to “this bit controls” for the enable 32kHz output bit.
Added Warning note to EC table notes; updated Note 12. 6
Updated the Typical Operating Characteristics graphs. 7
5 4/08 In the Power Control section, added information about the POR state of the time and date
10
registers; in the Real-Time Clock section, added to the description of the RST function.
In Figure 1, corrected the months date range for 04h from 00–31 to 01–31. 11

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DS3231 Extremely Accurate I2C-Integrated
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Revision History (continued)

REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
Updated the Typical Operating Circuit. 1
Removed the VPU parameter from the Recommended DC Operating Conditions table
and added verbiage about the pullup to the Pin Description table for INT/SQW, SDA, and 2, 9
SCL.
Added the Delta Time and Frequency vs. Temperature graph in the Typical Operating
7
Characteristics section.
6 10/08
Updated the Block Diagram. 8
Added the VBAT Operation section, improved some sections of text for the 32kHz TCXO
10
and Pushbutton Reset Function sections.
Added the register bit POR values to the register tables. 13, 14, 15
Updated the Aging Offset and Temperature Registers (11h–12h) sections. 14, 15
Updated the I2C timing diagrams (Figures 3, 4, and 5). 16, 17
Removed the “S” from the top mark in the Ordering Information table and the Pin
7 3/10 1, 18
Configuration to match the packaging engineering marking specification.

Updated the Typical Operating Circuit; removed the “Top Mark” column from the Ordering
Information; in the Absolute Maximum Ratings section, added the theta-JA and theta-
JC thermal resistances and Note 1, and changed the soldering temperature to +260°C
1, 2, 3, 4, 6, 9,
8 7/10 (lead(Pb)-free) and +240°C (leaded); updated the functional description of the VBAT pin
11, 12, 13, 18
in the Pin Description; changed the timekeeping registers 02h, 09h, and 0Ch to “20 Hour”
in Bit 5 of Figure 1; updated the BBSQW bit description in the Control Register (0Eh)
section; added the land pattern no. to the Package Information table.

9 1/13 Updated Absolute Maximum Ratings, and last paragraph in Power Control section 2, 10
10 3/15 Revised Benefits and Features section. 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

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