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    Module 4- counters-3 (1)

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    Module 4- counters-3 (1)

    Uploaded by

    nikhilkumar2005.10
    2 views36 pages

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    Copyright:

    © All Rights Reserved
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    2 views36 pages

    Module 4- counters-3 (1)

    Uploaded by

    nikhilkumar2005.10

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 36

    Digital Design(22ECE32)

    MODULE 4 part 1
    Counters
    Asynchronous Counters

    ► An asynchronous counter is one in which the flip-flops (FF)


    within the counter do not change states at exactly the same
    time because they do not have a common clock pulse.
    A 2-Bit Asynchronous Binary Counter
    A 3-Bit Asynchronous Binary Counter
    Propagation delay DISADVANTAGES
    ● limits the rate at
    which counter can be
    clocked and creates
    decoding problems
    ● Maximum cumulative
    delay must be less
    than the clock
    waveform.
    Asynchronous Decade Counters

    ► Modulus
    ► Truncated sequence
    ► Decade counter
    ► Partial Decoding
    An asynchronously
    clocked
    decade counter with
    asynchronous
    recycling
    Show how an asynchronous counter with J-K
    flip-flops can be implemented having a
    modulus of twelve with a straight binary
    sequence from 0000 through 1011
    Synchronous Counter

    ► A synchronous counter is one in which all the


    flip-flops in the counter are clocked at the same
    time by a common clock pulse
    A 2-Bit Synchronous Binary Counter
    Timing details
    A 3-Bit Synchronous Binary Counter
    A 4-Bit Synchronous Binary Counter
    A 4-Bit Synchronous Decade Counter
    Up/Down Synchronous Counters

    ► An up/down counter is one that is capable of progressing in either


    direction through a certain sequence.
    ► An up/down counter, sometimes called a bidirectional counter, can
    have any specified sequence of states.
    ► A 3-bit binary counter that advances upward through its sequence (0,
    1, 2, 3, 4, 5, 6, 7) and then can be reversed so that it goes through
    the sequence in the opposite direction (7, 6, 5, 4, 3, 2, 1, 0) is an
    illustration of up/down sequential operation.
    3-bit binary up/down counter
    Show the timing diagram and determine the
    sequence of a 4-bit synchronous binary
    up/down counter if the clock and UP/DOWN
    control inputs have waveforms as shown. The
    counter starts in the all-0s state and is
    positive edge-triggered.
    Design of Synchronous Counters
    ● Develop a state diagram for a given sequence
    ● Develop a next-state table for a specified counter sequence
    ● Create a flip-flop transition table
    ● Use the Karnaugh map method to derive the logic requirements for a
    synchronous counter
    ● Implement a counter to produce a specified sequence of states

    Consider the example of 3 bit gray code counter


    Step 1: state diagram

    Step 2: State Table


    Step 3: K map for logical
    equations

    FIGURE 9–27 Examples of the mapping procedure for the counter sequence represented in Table 9–8 and Table 9–9
    Step 4: Counter Implementation

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