Final
Final
Final
1. Different parts of this question are independent of each other. kT/q=25mV at 300K. [25]
a. Assume ni=1010/cm3, μn=1600cm2/Vs for Si at room temperature. It is found that a
piece of n-type Si sample has resistivity =100Ω-cm. Find the concentration of electrons
and holes in this material. You may make any reasonable approximation. [6]
b. The excess hole concentration in a n-type material with uniform ND=10 cm and cross-
17 -3
i. Draw a p-n junction and indicate the type and direction of the four conventional
currents across the depletion region of p-n junction under equilibrium. [4]
ii. Draw the charge density function everywhere in the p-n junction and indicate its
magnitude. [2]
iii. Calculate the electric field intensity everywhere in the p-n junction and compute
the maximum value. [4]
iv. Draw the potential function everywhere in the p-n junction. You may take the
potential of the n-region as reference i.e. “0V”. [3]
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Name:____________________ Roll #:_______________
2. For the following circuit, assume kn=1mA/V2, Vt=1V and |VA|=50V, for the MOSFET and VD-
ON=0.7V, rD-ON=1kΩ for the diode D1. The MOSFET is biased in the saturation region through a
constant current source of 1mA connect at the Drain. [25]
a. We will design suitable values of RG1 and RG2 such that the DC-bias voltage at the Drain
VD=0V. Note: We then do not need an output ac coupling capacitor:
i. What should be the DC value of ID? [2]
ii. What is the value of VS? [2]
iii. What should be the value of VG? [2]
iv. What should be the values of RG1 and RG2? [2]
v. Indicate the correct polarity of input coupling capacitor. [2]
vi. At what voltage will clipping occur in the positive and negative half cycles? [2+3]
b. Draw the small signal model of this amplifier. [5]
c. Find the values of input resistance, voltage gain and output resistance [1+2+2]
3. The following circuit is to be used as an amplifier with two outputs. Given that β=100, we would
like to bias the circuit such that VRC=VRE=VCE=VCC/3=1.67V each and IC-Q=1mA. [25]
2
Name:____________________ Roll #:_______________
4. The circuit of Fig 3a has a PMOS transistor MP1 and an NMOS transistor MN1 connected in series.
They both have W/L=1 and |Vt|=1V with μnCox=22.5μA/V2 and μpCox=10μA/V2. Neglecting
channel length modulation: [25]
Fig 3a Fig 3b
a) Find the value of ID and VD for this circuit. [6]
b) The circuit of Fig 4b is extended from the previous circuit to drive a second PMOS transistor
MP2 and a second NMOS transistor MN2. Both these transistors have aspect ratio W/L=2; rest
of the parameters are identical.
i. Find the Drain current ID-P2 in the transistor MP2. [3]
ii. Find the value of VBIAS such that the Drain current ID-N2 is the same as the Drain
current in transistor MP2. [3]
Consider now the channel length modulation in MP2 and MN2 is not negligible for the small signal
analysis. Early voltage |VA|=100V for both MP2 and MN2.
c) Draw the small signal model for the circuit in Fig 3b. [4]
d) Find the value of rin, rout and pole frequency of the output capacitor. [6]
e) Find the expression for the voltage gain if RL=ro. [3]