COLLEGE OF ENGINEERING

PUTRAJAYA CAMPUS
FINAL EXAMINATION

SEMESTER 1 2013 / 2014

PROGRAMME : Bachelor of Electrical & Electronics Engineering (Honours)

Bachelor of Electrical Power Engineering (Honours)

SUBJECT CODE : EEEB273

SUBJECT : ELECTRONIC ANALYSIS AND DESIGN II

DATE : September 2013

TIME : 3 hours

INSTRUCTIONS TO CANDIDATES:

1. This paper contains Six (6) questions in Ten (10) pages.

2. Answer ALL questions.

3. Write all answers in the answer booklet provided.

4. Write answer to different question on a new page.

5. For all calculations, assume that VT = 26 mV.

6. Use at least 4 significant numbers in all calculations.

THIS QUESTION PAPER CONSISTS OF TEN (10) PRINTED PAGES INCLUDING THIS
COVER PAGE.

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 EEEB273, Semester 1 2013/2014

Question 1 [20 marks]

You are required to design a differential amplifier with passive load using NPN bipolar junction
transistors (BJT).
The differential amplifier is biased by a 1.5 mA constant current from a 2-transistor NPN BJT
current source. Power supplies of +10 V and -10 V are used to power the overall circuit.
Output of the differential amplifier is taken as one-sided output at one of its transistor. The
differential-mode voltage gain (Ad) is 150 V/V.
Available components for the design are:
· Matched NPN BJTs with β = 50, VBE(on) = 0.7 V, and VA = ∞.
· Various resistors with precise values.

Design the differential amplifier described above, complete with its biasing circuit, and draw
and label clearly the circuit diagram of your design. Show clearly all calculations related to
the design, with the values as accurate as possible.
[20 marks]

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 EEEB273, Semester 1 2013/2014

Question 2 [15 marks]

As knowledge in electronic design and analysis advances, a differential amplifier circuit can be
improved to increase its gain by using active loads. The BJT differential amplifier shown in
Figure 2 is biased by a 0.18 mA constant current source (i.e. IQ = 0.18 mA). The differential
amplifier uses a BJT Cascode current source made up of PNP transistors as the active load.
The output voltage (vO) of the differential amplifier is taken at vC2. Information related to the
transistor parameters are: β = 150, VBE(on) = VEB(on) = 0.7 V, VAN = 120 V, and VAP = 100 V.

Active load using a BJT Cascode

current source (made up from
PNP transistors) having output
resistance ROAL

Figure 2

(a) Calculate the output resistance of the BJT Cascode current source (ROAL) and then
sketch the differential amplifier circuit incorporating the Cascode current source as the
active load. [5 marks]

(b) Determine the differential-mode voltage gain of the circuit, Ad = vO/vd. [6 marks]

(c) Determine the output voltage of the circuit if a differential input vd = 5 sin (wt) mV is
applied. How will this output different if we use a two-transistor current source (made
up of PNP transistors) as the active load? [4 marks]

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 EEEB273, Semester 1 2013/2014

Question 3 [10 marks]

(a) Briefly describe the advantage of Class-AB output stage as compared to the Class-A and
Class-B output stages. [3 marks]

(b) A Class-A emitter follower biased with a constant-current source is shown in Figure 3.
The transistor parameters are: β = 180, VBE = 0.7 V, and VCE(sat) = 0.2 V. Neglect base
currents.

(i) Find the value of IQ. [3 marks]

(ii) Determine the value of R that will produce the maximum possible output signal
swing. [2 marks]

(iii) Calculate the conversion efficiency, η. [2 marks]

Figure 3

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 EEEB273, Semester 1 2013/2014

Question 4 [20 marks]

The MC14573 CMOS op amp, as shown in Figure 4, is used in a sensor circuit requiring a
very high-degree of accuracy. The open-loop gain of this op amp is required to be 100 dB.
Design the circuit to achieve this.

Given: V+ = +5 V, V- = -5 V, and Iset = 10 mA with VSD5(sat) = 1.5 V.

The transistor parameters are: |VT| = 2 V, (1/2)mnCox = 20 mA/V2, (1/2)mpCox = 10 mA/V2, ln =
0.01 V-1, and lp = 0.02 V-1.
The transistor aspect ratios are (W ) 5, 6,8 = 10. Let the aspect ratios of all other transistors be
L
the same.
[20 marks]

Figure 4

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 EEEB273, Semester 1 2013/2014

Question 5 [15 marks]

Consider the standard 741 operational amplifier circuit as in Figure 5a. The operational
amplifier is supplied by ±5 V DC voltage. The transistors have b n = 200, bp = 50, VAN = VAP =
50 V, VBE(on) = VEB(on) = 0.65 V (EXCEPT for VBE10), and the reverse saturation current IS =
5x10-16 A. Neglect base current in your calculations. Let IC16 = 13.2 µA and IC17 = 0.165 mA.

(a) Study the bias circuit very carefully. If the current IC9 = 10 µA and IREF = 0.22 mA,
determine R4. [5 marks]

(b) Determine the operational amplifier overall differential mode voltage gain if the resistor
values for R1, R2 and R8 are changed to 0 (zero), and the small signal voltage gain of the
gain stage Av2 = -100. You may use the ac equivalent circuits as in Figure 5b and Figure
5c to assist your calculations. [10 marks]

Figure 5a

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 EEEB273, Semester 1 2013/2014

Figure 5b

Figure 5c

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 EEEB273, Semester 1 2013/2014

Question 6 [20 marks]

(a) Using feedback resistor of 30 kΩ, draw the following circuits using inverting op-amp
configuration:
(i) An inverting amplifier with a closed-loop gain of -15. [4 marks]

(ii) A voltage follower. [4 marks]

(b) Consider the non-inverting op-amplifier shown in Figure 6a. Assume the op-amp is ideal.
Design the circuit to produce a closed-loop gain of 20, with the minimum resistor value in
the circuit is to be 15 kΩ. [4 marks]

Figure 6a

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 EEEB273, Semester 1 2013/2014

Figure 6b

(c) A general output equation for a difference amplifier shown in Figure 6b is

vO = Ad vd + Acm vcm
For the difference amplifier in Figure 6b, the circuit parameters are R1 = 15 kW, R2 = 90 kW,
R3 = 15 kW, and R4 = 120 kW and the output voltage (vO) equation is as follows:

æ R öæ R / R ö æR ö
vO = çç1 + 2 ÷÷çç 4 3 ÷÷vI 2 - çç 2 ÷÷vI 1
è R1 øè 1 + R4 / R3 ø è R1 ø

vd
v I 1 = v cm -
where 2
vd
v I 2 = v cm +
and 2

Calculate Ad, Acm, and the CMRR in dB for the circuit. [8 marks]

-END OF QUESTION PAPER-

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 EEEB273, Semester 1 2013/2014

APPENDIX

BASIC FORMULA

BJT MOSFET
iC = I S e vBE / VT ; NPN ; N - MOSFET
vDS (sat) = vGS - VTN
iC = I S e vEB / VT ; PNP
iD = K n [vGS - VTN ]2

iC = biB = aiE mnCoxW kn' W

Kn = = ×
2L 2 L
iE = iB + iC
b
a= ; P - MOSFET
b +1
vSD (sat) = vSG + VTP
iD = K p [vSG + VTP ]2
; Small signal
m pCoxW k p' W
b = g m rp Kp = = ×
2L 2 L
bVT
rp =
I CQ
; Small signal
I CQ
gm = g m = 2 K ? I DQ
VT
1
V ro @
ro = A lI DQ
I CQ

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