ABIT I-N73V [NFORCE MCP73] LGA775 V.0.2

5 4 3 2 1
PAGE CONTENTS
D 1 COVER D
2 BLOCK DIAGRAM
3 RESET MAP
4 CLOCK DISTRIBUTION
5 DEVICE TABLE / VRGES
6-9 SOCKET 775 CPU
10 MCP73 CPU
11 MCP73 PCIE / DAC / HDMI
I-N73V
12 MCP73 MEM
13 MCP73 PCI / LPC
14 MCP73 SATA / IDE
15 MCP73 HDA / MII / USB
16 MCP73 SPI / PS2 / JTAG
C
17
18
MCP73 MEM POWER
MCP73 CORE / VTT POWER
Chipset : MCP73V C
19
20
MCP73 GND
DDR2 DIMM1 (GeForce 7050 / nForce 610i)
21 DDR2 DIMM2
22 DDR TERMINATION
23 DAC ,DVI & HDMI
24 PCI EXPRESS X16 CONNECTOR
25
26
PCI EXPRESS X1 CONNECTOR
PCI 1/2 SLOT
M712 v0.2
27 PCI TERM/DECOUPLING
28 PWR CON/F-PNL/VBAT/SPKR
mATX from factor 244 x 200 mm
29 PWM RT8802 & RT9607
30 CPU DECOUPLING
31 W83304CG & OVP
32 MCP73 CORE & DDRII POWER
B B
33 CPU VTT POWER
34 Ti43AB22A-1394-2 Port
35 RGMII 88E1116 PHY0
36 HD-CODEC_ALC888 (Colay 882/883/885)
37 IDE 1
38 USB+RJ45 & USB+1394 & FP-USB
39 W83627DHF SuperI/O
40 K/M+FLASH+FDC
41 FAN & CPU CHANGE
42 MOUNTING HOLES
A A
Title
COVER
Size Document Number Rev
A3 I-N73V 0.2
Date: Thursday, December 13, 2007 Sheet 1 of 41
5 4 3 2 1
5 4 3 2 1
BLOCK DIAGRAM
INTEL
D D
PENTIUM 4 64-BIT 400/533/667MHZ
PSU VREG DDR2 SDRAM CONN 0
SOCKET 775
DDR2 SDRAM CONN 2
FSB
800/1066M
BACK PANEL CONN

RGB
PCI EXPRESS D-Sub
PCIE X16 CONN
PCI EXPRESS
PCIE X1 CONN
C C
NFORCE
PCI BUS 33MHZ
PCI SLOT 1
ATA 133 MCP73
PRIMARY IDE
PCI SLOT 2
INTEGRATED SATA 1 1048 BGA HDA
SATA1 BACK PANEL CONN
AUDIO CODEC
AUDIO1
SATA2 (x6 PhoneJack)
INTEGRATED SATA 2
SATA3 PANEL HDR
FP-AUDIO1
SATA4
CD1
SPI
SPI FLASH
B RGMII /MII MII / RGMII B
LAN PHY
X10 USB
FLOPPY CONN BACK PANEL CONN
SIO LPC BUS 33MHZ
LPC I/0
USB2
PS2/KBRD CONN
RJ45 CONN (10/100)
8MB FLASH LPC BUS 33MHZ USB1

(Function)
PANEL HDR
FP-USB1
A FP-USB2 A
Title
BLOCK DIAGRAM
A3 I-N73V 0.2
5 4 3 2 1
P4 SKT
RESET MAP
CPU_RST* (V1P2_FSBVTT)
CPU_VTT_PWRGD RST*
VTT_PWRGD
D PWRGOOD D
RST SWTCH
MCP73
FP_RESET* MCP73_CPU_PWRGD
RSTBTN* MCP_PWRGD
CPU_RST*
PS_PWRGD 40-100ms CPU_RESET*
SLP_S3*
SLP S3*
SLP_S5*
SLP S5* PE_RESET* (+2.5V)
PE_RESET*
PEX X16
CPU VCCP
Regulator
CPU_VTT_PWRGD MEM_VLD
C EN PEX X1 C
PWRGD
CPU_VLD PCI_RST_SLOT1* (+3.3V)

AND CPU_VLD PCI RST0*
PCI_RST_SLOT2* (+3.3V) PCI SLOT1
CPU_FSB_VTT PCI RST1*
Regulator
CPU_VTT_PWRGD PCI RST2*
PWRGD CPUVDD_EN PCI_RST_IDE* (+3.3V) PCI SLOT2
EN CPU_ENABLE PCI RST3*
HT_VLD
MCP73 Core
Regulator LPC_RST_SIO* (+3.3V)
HT_ENABLE LPC_RST*
PWRGD IDE
AND
HDA_RESET* HDA_RST* AUDIO_PHY

RESET*
B PWR CONN B
PWRGD_SB
PWRGD_SB
PWRBTN* MII_RESET* RGMII_RESET* LAN_PHY
PWRBTN* RESET*
PWRGD_PS
VCC 300ms PWR GOOD
W83627_PSOUT*
PS ON
W83627_PSOUT* W83627DHF
MEM VDD SLP_S5*
Regulator LRESET*
EN SLP_S3*
PWRBTN*
PSOUT*
PWRGD_SB
PWR SWTCH
PWRGD_PS
A PSON* A
Dual Power
Regulator PSIN*
SLP_S3*
SLP_S3*
PANSWIN*
Title
RESET MAP
A3 I-N73V 0.2
5 4 3 2 1
5 4 3 2 1
CLOCK DISTRIBUTION PCIE

X16 PCIE
X1
DIMM 1
D D
P4
DIMM 2
1/16
MAIN CLOCKS TO CPU
CPU_CLK_IN*
CPU_CLK_IN
MCP73
BCLK_OUT_CPU_P
BCLK_OUT_CPU_N PCIE X16 REF_CLK 100MHZ
PCIE X16 REF_CLK*

200/266/333 MHZ
BCLK_OUT_MCP_P PCIE X1 REF_CLKS 100MHZ
C
BCLK_OUT_MCP_N PCIE X1 REF_CLKS* C
266/333MHZ
3
MEMORY CLOCKS TO DIMMS
MEMORY_0A_CLOCK[2:0]
BCLK_IN_MCP_N 3
MEMORY_0A_CLOCK[2:0]*
BCLK_IN_MCP_P
3
XDP MEMORY_0B_CLOCK[2:0]
3
BCLK_OUT_ITP_P MEMORY_0B_CLOCK[2:0]*
BCLK_OUT_ITP_N
1/16
(Empty)
SIO
PCI SLOT 1
B B
FLASH PCI SLOT 2

BUF_SI0_CLK 24 MHZ
LPC_CLK0 ALL 33MHZ 1/16

LPC_CLK1
PCI_CLK0 ALL 33MHZ
PCI_CLK1
PCI_CLK2
PCI_CLK3
1394
PCI_CLK4
PCI_CLK_FB
LAN INTERFACE
MII_RXCLK 25MHZ, 125MHZ
MII_TXCLK
XTAL_IN LAN
25 MHZ
25.0 MHZ
XTAL_OUT
AC_BITCLK HDA LINK AUDIO
A RTC XTAL_IN A
32.768 KHZ
RTC XTAL_OUT
Title
CLOCK DISTRIBUTION
A3 0.2
I-N73V
5 4 3 2 1
5 4 3 2 1
VREGS
+12V
+5V
5VDUAL
SMBUS ADDRESS MAP +5V_DUAL AC IN
P/S
+3.3V
+5V 5VSB
DUAL V1P2_FSBVTT
+1.2V_VTT PWRGD_PS
5VSB
FET 5VDUAL
DEVICE SMBUS # ADDRESS
D CPU_VTT D
ENABLE HIGH = +5V 1.2V_DUAL
VREG +1.2V_VTT SLP_S3*
ENABLE LOW = 5VSB
DIMM CHANNEL 0 0 1010 000 1/16 +3.3V PS_ON*
SLP_S3*
DIMM CHANNEL 1 0 1010 001
DELAYED
CPUVDD_EN
FROM MCP73 VCC3 VCC5SB
+3.3V +5V_STBY
5VSB XSTR 3.3VSB V1P2_CORE

+1.2V_CORE
VCC12 -12V
SIO 1 0101 101 = 0X2D MCP73 +12V -12V
CTRL FROM CORE
THERM SENSE 1 1001 100 = 0X4C PG PS +5V VREG +1.2V_CORE
PCI SLOT 1 1 ARP VCC5

+5V
PCI SLOT 2 1 ARP 3VDUAL
+3.3V_DUAL V1P2_DUAL
+1.2V_DUAL
3.3VSB V
FET
+3.3V 3VDUAL MCP73
PCIE X1-1 1 ARP CORE AUX
3VDUAL VREG 1.2V_DUAL LAN
PCIE X16 PHYS 1 ARP LAN
1.8V
3VDUAL VREG +1.8V
C PWRGD_PS C
DELAYED
V1P8_DUAL_LAN
VDDMEM
CPU CPU_PWRGD
+1.8V_SUS
OUT
+1.8V_DUAL_LAN0
TO MCP73
+12V VREG
MEM VDDQ
+V_CPU
+5VDUAL VREG +1.8V_SUS
1/16 VCCP
CPU_VTT_PWRGD +V_CPU
VIDS
ENABLE = HIGH
SLP_S5*
VTTMEM AUDIO
+MEM_VTTV +12V
5V +5V_AUD
VREG
CPU_VCC_PLL 1.8V_SUS
+5V CPU_VCC
VREG
VREG CPU_VCC VOLTAGE 3VDUAL +MEM_VTT
FOR PLL
1/16
VTT VOLTAGE
DIMM_VREF FOR TERMINATION
CPU_VCC_PLL 8 VBATCCMOS
B B
CPU_VCC_PLL IN
+3.3V_VBAT
OUT
PCI INTERRUPT/IDSEL MAP

SOT23-5/SC70
SLOT BUS # DEV # IDSEL SLT INTA* SLT INTB* SLT INTC* SLT INTD* REQ/GNT SOT23 SOT23-6 SOT223
SOT89-5
4
1 01 0X06 22 PCI_INTY* PCI_INTZ* PCI_INTW* PCI_INTX* 0 3 5 4 6 5 4
2 01 0X07 23 PCI_INTZ* PCI_INTW* PCI_INTX* PCI_INTY* 1
1394 24 PCI_INTW* 2
1/16
1 2
1 2 3 1 2 3 1 2 3
A A
Title
DEVICE TABLE / VRGES

A3 0.2
I-N73V
5 4 3 2 1
5 4 3 2 1
CRB connect to SIO-P.104 (SYSTIN)
CPU_THERMDC1
CPU_THERMDC1
CPU_THERMDC1R R81 0-LF
CPU_THERMDA1
U6C CPU_THERMDA1 U6A
CPU_THERMDA1R R80 0-LF
SK-C775P SK-C775P
A12 GND
SKT_775P AJ29 SKT_775P
A15 GND 3 OF 5 GND AJ30 95.10.30 1 OF 5 CPU_A*[35..3]
CPU_A*[35..3] 10
A18 GND GND AJ4 0 ˖ˣ˨˲˗ʽ˃ B4 D0* A3* L5 3 ˖ˣ˨˲˔ʽˆ
A2 GND GND AJ7 1 ˖ˣ˨˲˗ʽ˄ C5 D1* A4* P6 4 ˖ˣ˨˲˔ʽˇ
D A21 GND GND AK10 ref. IL9_v0.2 2 ˖ˣ˨˲˗ʽ˅ A4 D2* A5* M5 5 ˖ˣ˨˲˔ʽˈ
D
NC PD_CPU_A24 A24 GND GND AK13 3 ˖ˣ˨˲˗ʽˆ C6 D3* A6* L4 6 ˖ˣ˨˲˔ʽˉ
2
A6 GND GND AK16 4 ˖ˣ˨˲˗ʽˇ A5 D4* A7* M4 7 ˖ˣ˨˲˔ʽˊ
A9 GND GND AK17 5 ˖ˣ˨˲˗ʽˈ B6 D5* A8* R4 8 ˖ˣ˨˲˔ʽˋ

R253
CRB x1K-LF AA23 6 ˖ˣ˨˲˗ʽˉ 9
no this 5%
GND GND AK2 B7 D6* A9* T5 ˖ˣ˨˲˔ʽˌ
R0603 AA24 GND GND AK20 7 ˖ˣ˨˲˗ʽˊ A7 D7* A10* U6 10 ˖ˣ˨˲˔ʽ˄˃
AA25 GND GND AK23 8 ˖ˣ˨˲˗ʽˋ A10 D8* A11* T4 11 ˖ˣ˨˲˔ʽ˄˄

EMPTY 9 ˖ˣ˨˲˗ʽˌ 12 ˖ˣ˨˲˔ʽ˄˅
AA26 GND GND AK24 A11 D9* A12* U5
1
AA27 GND GND AK27 10 ˖ˣ˨˲˗ʽ˄˃

B10 D10* A13* U4 13 ˖ˣ˨˲˔ʽ˄ˆ
AA28 GND GND AK28 11 ˖ˣ˨˲˗ʽ˄˄

C11 D11* A14* V5 14 ˖ˣ˨˲˔ʽ˄ˇ
AA29 GND GND AK29 12 ˖ˣ˨˲˗ʽ˄˅

D8 D12* A15* V4 15 ˖ˣ˨˲˔ʽ˄ˈ
AA3 GND GND AK30 13 ˖ˣ˨˲˗ʽ˄ˆ

B12 D13* A16* W5 16 ˖ˣ˨˲˔ʽ˄ˉ
AA30 GND GND AK5 14 ˖ˣ˨˲˗ʽ˄ˇ

C12 D14* A17* AB6 17 ˖ˣ˨˲˔ʽ˄ˊ
AA6 GND GND AK7 15 ˖ˣ˨˲˗ʽ˄ˈ

D11 D15* A18* W6 18 ˖ˣ˨˲˔ʽ˄ˋ
AA7 GND GND AL10 16 ˖ˣ˨˲˗ʽ˄ˉ

G9 D16* A19* Y6 19 ˖ˣ˨˲˔ʽ˄ˌ
AB1 GND GND AL13 17 ˖ˣ˨˲˗ʽ˄ˊ

F8 D17* A20* Y4 20 ˖ˣ˨˲˔ʽ˅˃
AB23 GND GND AL16 18 ˖ˣ˨˲˗ʽ˄ˋ

F9 D18* A21* AA4 21 ˖ˣ˨˲˔ʽ˅˄
AB24 GND GND AL17 19 ˖ˣ˨˲˗ʽ˄ˌ

E9 D19* A22* AD6 22 ˖ˣ˨˲˔ʽ˅˅
AB25 GND GND AL20 20 ˖ˣ˨˲˗ʽ˅˃

D7 D20* A23* AA5 23 ˖ˣ˨˲˔ʽ˅ˆ
AB26 GND GND AL23 21 ˖ˣ˨˲˗ʽ˅˄

E10 D21* A24* AB5 24 ˖ˣ˨˲˔ʽ˅ˇ
AB27 GND GND AL24 22 ˖ˣ˨˲˗ʽ˅˅

D10 D22* A25* AC5 25 ˖ˣ˨˲˔ʽ˅ˈ
AB28 GND GND AL27 23 ˖ˣ˨˲˗ʽ˅ˆ

F11 D23* A26* AB4 26 ˖ˣ˨˲˔ʽ˅ˉ
AB29 GND GND AL28 24 ˖ˣ˨˲˗ʽ˅ˇ

F12 D24* A27* AF5 27 ˖ˣ˨˲˔ʽ˅ˊ
AB30 GND GND AL3 CPU_AL3_PD NC 25 ˖ˣ˨˲˗ʽ˅ˈ

D13 D25* A28* AF4 28 ˖ˣ˨˲˔ʽ˅ˋ
2
AB7 GND GND AL7 26 ˖ˣ˨˲˗ʽ˅ˉ
E13 D26* A29* AG6 29 ˖ˣ˨˲˔ʽ˅ˌ
AC3 GND GND AM1 27 ˖ˣ˨˲˗ʽ˅ˊ

G13 D27* A30* AG4 30 ˖ˣ˨˲˔ʽˆ˃
R104
AC6 GND GND AM10 x0-LF
5%
28 ˖ˣ˨˲˗ʽ˅ˋ
F14 D28* A31* AG5 31 ˖ˣ˨˲˔ʽˆ˄
AC7 GND GND AM13 R0603 29 ˖ˣ˨˲˗ʽ˅ˌ

G14 D29* A32* AH4 32 ˖ˣ˨˲˔ʽˆ˅
CRB 30 33 ˖ˣ˨˲˔ʽˆˆ
AD4 GND GND AM16 no this
˖ˣ˨˲˗ʽˆ˃
F15 D30* A33* AH5
C AD7 GND GND AM17 31 ˖ˣ˨˲˗ʽˆ˄
G15 D31* A34* AJ5 34 ˖ˣ˨˲˔ʽˆˇ C
1
AE10 GND GND AM20 32 ˖ˣ˨˲˗ʽˆ˅

G16 D32* A35* AJ6 35 ˖ˣ˨˲˔ʽˆˈ
AE13 GND GND AM23 33 ˖ˣ˨˲˗ʽˆˆ

E15 D33*
AE16 GND GND AM24 34 ˖ˣ˨˲˗ʽˆˇ
E16 D34* AP0* U2 NC
AE17 GND GND AM27 35 ˖ˣ˨˲˗ʽˆˈ
G18 D35* AP1* U3 NC
AE2 GND GND AM28 36 ˖ˣ˨˲˗ʽˆˉ
G17 D36*
AE20 GND GND AM4 37 ˖ˣ˨˲˗ʽˆˊ
F17 D37* ADSTB0* R6 CPU_ADSTB0*
CPU_ADSTB0* 10
AE24 GND GND F22 38 ˖ˣ˨˲˗ʽˆˋ
F18 D38* ADSTB1* AD5 CPU_ADSTB1*
CPU_ADSTB1* 10
AE25 GND GND AN1 39 ˖ˣ˨˲˗ʽˆˌ
E18 D39*
AE26 GND GND AN10 40 ˖ˣ˨˲˗ʽˇ˃
E19 D40*
AE27 GND GND AN13 41 ˖ˣ˨˲˗ʽˇ˄
F20 D41* DSTBP0* B9 CPU_DSTBP0*
CPU_DSTBP0* 10
AE28 GND GND AN16 42 ˖ˣ˨˲˗ʽˇ˅
E21 D42* DSTBN0* C8 CPU_DSTBN0*
CPU_DSTBN0* 10
AE29 GND GND AN17 43 ˖ˣ˨˲˗ʽˇˆ
F21 D43* DBI0* A8 CPU_DBI0*
CPU_DBI0* 10
AE30 GND GND AN2 44 ˖ˣ˨˲˗ʽˇˇ
G21 D44*
AE5 GND GND AN20 45 ˖ˣ˨˲˗ʽˇˈ
E22 D45* DSTBP1* E12 CPU_DSTBP1*
CPU_DSTBP1* 10
AE7 GND GND AN23 46 ˖ˣ˨˲˗ʽˇˉ
D22 D46* DSTBN1* G12 CPU_DSTBN1*
CPU_DSTBN1* 10
AF10 GND GND AN24 47 ˖ˣ˨˲˗ʽˇˊ
G22 D47* DBI1* G11 CPU_DBI1*
CPU_DBI1* 10
AF13 GND GND AN27 48 ˖ˣ˨˲˗ʽˇˋ
D20 D48*
AF16 GND GND AN28 49 ˖ˣ˨˲˗ʽˇˌ
D17 D49* DSTBP2* G19 CPU_DSTBP2* VTT_OUT_LEFT
CPU_DSTBP2* 10
AF17 GND GND F4 50 ˖ˣ˨˲˗ʽˈ˃
A14 D50* DSTBN2* G20 CPU_DSTBN2*
CPU_DSTBN2* 10
AF20 GND GND B1 51 ˖ˣ˨˲˗ʽˈ˄
C15 D51* DBI2* D19 CPU_DBI2*
CPU_DBI2* 10
AF23 GND GND B11 52 ˖ˣ˨˲˗ʽˈ˅
C14 D52*
2
AF24 GND GND B14 53 ˖ˣ˨˲˗ʽˈˆ
B15 D53* DSTBP3* C17 CPU_DSTBP3*
CPU_DSTBP3* 10
AF25 GND GND B17 54 ˖ˣ˨˲˗ʽˈˇ
C18 D54* DSTBN3* A16 CPU_DSTBN3* R213
CPU_DSTBN3* 10
AF26 GND GND B20 55 ˖ˣ˨˲˗ʽˈˈ
B16 D55* DBI3* C20 CPU_DBI3*
CPU_DBI3* 10 60.4-1%-0402-LF
5%
AF27 GND GND B24 56 ˖ˣ˨˲˗ʽˈˉ
A17 D56* R0402 62 -> 60.4-1%-0402
AF28 GND GND B5 57 ˖ˣ˨˲˗ʽˈˊ
B18 D57* ADS* D2 CPU_ADS*
CPU_ADS* 10
AF29 GND GND B8 58 ˖ˣ˨˲˗ʽˈˋ
C21 D58* BPRI* G8 CPU_BPRI*
CPU_BPRI* 10
1
AF3 GND GND C10 59 ˖ˣ˨˲˗ʽˈˌ
B21 D59* BR0* F3 CPU_BR0*
B CPU_BR0* 10 B
AF30 GND GND C13 60 ˖ˣ˨˲˗ʽˉ˃
B19 D60*
AF6 GND GND C16 61 ˖ˣ˨˲˗ʽˉ˄
A19 D61*
AF7 GND GND C19 62 ˖ˣ˨˲˗ʽˉ˅
A22 D62* DBSY* B2 CPU_DBSY*
CPU_D*[63..0]
CPU_DBSY* 10
AG10 GND GND C22 63 ˖ˣ˨˲˗ʽˉˆ
B22 D63* DEFER* G7 CPU_DEFER*
10 CPU_D*[63..0] CPU_DEFER* 10
AG13 GND GND C24 VTT_OUT_RIGHT
AG16 GND GND C4 CPU_DP0* NC J16 DP0* DRDY* C1 CPU_DRDY*
CPU_DP0* CPU_DRDY* 10
AG17 GND GND C7 CPU_DP1* MCP73 NC H15 DP1* TRDY* E3 CPU_TRDY*
CPU_DP1* CPU_TRDY* 10
AG20 GND GND D12 CPU_DP2* be NC NC H16 DP2* BNR* C2 CPU_BNR* 62 -> 60.4-1%-0402
CPU_DP2* CPU_BNR* 10
2
AG23 GND GND D15 CPU_DP3* NC J17 DP3*
CPU_DP3* CPU_REQ*[4..0]
AG24 GND GND D18 HIT* D4 CPU_HIT*
10 CPU_REQ*[4..0] CPU_HIT* 10
AG7 GND GND D21 0 ˖ˣ˨˲˥˘ˤʽ˃ K4 REQ0* HITM* E4 CPU_HITM*
CPU_HITM* 10
AH1 GND GND D24 1 ˖ˣ˨˲˥˘ˤʽ˄ J5 REQ1* R144 V1P2_FSBVTT
AH10 GND GND D3 2 ˖ˣ˨˲˥˘ˤʽ˅ M6 REQ2* LOCK* C3 CPU_LOCK* 60.4-1%-0402-LF
CPU_LOCK* 10
2
AH13 GND GND D5 3 ˖ˣ˨˲˥˘ˤʽˆ K6 REQ3* BINIT* AD3 NC
1
AH16 GND GND D6 4 ˖ˣ˨˲˥˘ˤʽˇ J6 REQ4*
AH17 GND GND D9 CPU_RS*[2..0] IERR* AB2 CPU_IERR*
10 CPU_RS*[2..0]
AH20 GND GND E11 0 ˖ˣ˨˲˥˦ʽ˃ B3 RS0* MCERR* AB3 NC MCP73 CPU_MCERR* R273
CPU_MCERR*
AH23 GND GND E14 1 ˖ˣ˨˲˥˦ʽ˄ F5 RS1* be NC 221-1%-0402-LF
AH24 GND GND E17 2 ˖ˣ˨˲˥˦ʽ˅ A3 RS2*
1
AH3 GND GND E2 NC H4 RSP* RESET* G23 CPU_RST*
CPU_RST* 10
AH6 GND GND E20
AH7 GND GND E25 I229
AJ10 GND GND E26 MCP73 Design Guide_v0.1:
AJ13 GND GND E27 Changed CPU_RESET# pull up
AJ16 GND GND E28 from 62 ohms to 200 ohms
AJ17 GND GND E29 PD_CPU_E29 NC 2007.6.22
2
AJ20 GND GND E8

AJ23 GND GND F10 R252
A AJ24 GND GND F13 x1K-LF A
CRB
AJ27 GND GND F16 no this
AJ28 GND GND F19 5%
R0603
1
EMPTY
I230
Title
SOCKET 775 PART 1

A3 I-N73V 0.2
5 4 3 2 1
5 4 3 2 1
VTT_OUT_LEFT
CPU TERMINATION
VTT_OUT_RIGHT
VTT_OUT_RIGHT
to SIO v0.2 BOM CRB
1 2 SIO_PECI_MCP 38 MCP73 internal Pull Hi no this circuit
U6B
2
R441 33-LF
SK-C775P
2
R140 R206 VCCP
x100-1%-0402-LF SKT_775P
R173 R178 R174 1% 1%
from MCP 20 -> 33 ohm R0402 R0402 x100-1%-0402-LF 2 OF 5
CPU_PECI_O x150-1%-0402-LF EMPTY EMPTY CPU_CLK
10 CPU_PECI_MCP 1 2 10 CPU_CLK F28 BCLK0 VCCP AA8
R95 x33-LF 60.4-1%-0402-LF x150-1%-0402-LF CPU_CLK* G28 BCLK1 VCCP AB8
10 CPU_CLK*
1
D 1 2 to CPU VCCP AC23 D
38 CPU_PECI_SIO
1
R96 33-LF CPU_A20M* K3 A20M* VCCP AC24
10 CPU_A20M*
from SIO Em pty CPU_FERR* R3 FERR*/PBE* VCCP AC25
10 CPU_FERR*
CPU_IGNNE* N2 IGNNE* VCCP AC26
10 CPU_IGNNE*
CPU_SMI* P2 SMI* VCCP AC27
10 CPU_SMI*
MCP CPU_STPCLK* M3 STPCLK* VCCP AC28
10 CPU_STPCLK*
CPU_INTR K1 INTR VCCP AC29
10 CPU_INTR
CPU CPU_NMI L1 NMI VCCP AC30
10 CPU_NMI
CPU_INIT* P3 INIT* VCCP AC8
10 CPU_INIT*
SIO VCCP AD23
VTT_OUT_LEFT VTT_OUT_RIGHT VCCP AD24
2
PECI CPU_COMP2 G2 FC1 VCCP AD25
R155 R210 CPU_COMP3 R1 FC2 VCCP AD26
2
CPU_GTLREF3 F2 FC5 VCCP AD27
8,9 CPU_GTLREF3
R166 R170 49.9-1%-0402-LF CPU_PECI_O G5 FC7 VCCP AD28
200-1%-LF R141 R89 49.9-1%-0402-LF VCCP AD29
x150-1%-LF 51.1-1%-LF CPU_THERMDA AL1 THERMDA VCCP AD30
38 CPU_THERMDA
1
60.4-1%-0402-LF CPU_THERMDC AK1 THERMDC VCCP AD8
38 CPU_THERMDC
CPU_THERMTRIP* M2 THERMTRIP* VCCP AE11
10 CPU_THERMTRIP*
1
CPU_PROCHOT* AL2 PROCHOT* VCCP AE12
10,40 CPU_PROCHOT*
VCCP AE14
MCP73_CPU_PWRGD N1 PWRGOOD VCCP AE15
10 MCP73_CPU_PWRGD
CPU_VTT_PW RGD AM6 VTT_PWRGD VCCP AE18
29,33 CPU_VTT_PWRGD
VCCP AE19
BSEL0 G29 BSEL0 VCCP AE21
10 BSEL0
BSEL1 H30 BSEL1 VCCP AE22
10 BSEL1
BSEL2 G30 BSEL2 VCCP AE23
VTT_OUT_RIGHT 10 BSEL2
2
2
VCCP AE9
R116 R130 R124 R138 R118 R112 0 ˖ˣ˨˲˕ˣˠʽ˃ AJ2 BPM0* VCCP AF11
C 49.9-1%-LF VTT_OUT_RIGHT 1 ˖ˣ˨˲˕ˣˠʽ˄ AJ1 BPM1* VCCP AF12 C
1% 1% 1% 1% 1% 1%
49.9-1%-LF R0603 R0603 R0603 R0603 R0603 R0603 2 ˖ˣ˨˲˕ˣˠʽ˅ AD2 BPM2* VCCP AF14
49.9-1%-LF
˖ˣ˨˲˕ˣˠʽ˃
3 ˖ˣ˨˲˕ˣˠʽˆ AG2 BPM3* VCCP AF15

49.9-1%-LF R137 60.4-1%-0402-LF
˖ˣ˨˲˕ˣˠʽ˄
0 ˖ˣ˨˲˕ˣˠʽ˃
1 2 4 ˖ˣ˨˲˕ˣˠʽˇ
AF2 BPM4* VCCP AF18
1
49.9-1%-LF R145 60.4-1%-0402-LF

˖ˣ˨˲˕ˣˠʽ˅
˖ˣ˨˲˕ˣˠʽ˄
1 1 2 5 ˖ˣ˨˲˕ˣˠʽˈ AG3 BPM5* VCCP AF19
49.9-1%-LF R129 60.4-1%-0402-LF
˖ˣ˨˲˕ˣˠʽˆ
˖ˣ˨˲˕ˣˠʽ˅
2 1 2 VCCP AF21
R122 60.4-1%-0402-LF XDP_TDI
˖ˣ˨˲˕ˣˠʽˇ
˖ˣ˨˲˕ˣˠʽˆ
3 1 2 AD1 TDI VCCP AF22
ITP TERMINATION N C AF1
˖ˣ˨˲˕ˣˠʽˈ
˖ˣ˨˲˕ˣˠʽˇ
4 TDO VCCP AF8
˖ˣ˨˲˕ˣˠʽˈ
5 R123 1 2 x220-LF XDP_TMS AC1 TMS VCCP AF9
PLACE CLOSE TO CPU XDP_TCK AE1 TCK VCCP AG11
XDP_TRST* AG1 TRST* VCCP AG12
XDP_FNTPNL_RST* AC2 DBR* VCCP AG14
28 XDP_FNTPNL_RST*
INTERPOSER_BCLK AK3 ITP_CLK0 VCCP AG15
8 CPU_BPM*[5..0]
INTERPOSER_BCLK* AJ3 ITP_CLK1 VCCP AG18
10 INTERPOSER_BCLK
10 INTERPOSER_BCLK* VCCP AG19
9 MIL TRACE VCCP AG21
CPU_GTLREF H1 GTLREF VCCP AG22
8,9 CPU_GTLREF
IP35 be NC VCCP AG25
CPU_COMP0 A13 COMP0 VCCP AG26 VTT_OUT_RIGHT
CPU_COMP1 T1 COMP1 VCCP AG27
2
VCCP AG28
R260 R156 TP3 LOAD_LN_ID0 V2 LL_ID0 VCCP AG29
2
TP1 LOAD_LN_ID1 AA2 LL_ID1 VCCP AG30
1% 1%
R0603 R0603 VCCP AG8 R164 R161
49.9-1%-LF 0 ˖ˣ˨˲˩˜˗˃ AM2 VID0 VCCP AG9 x51.1-1%-LF x51.1-1%-LF
1% 1%
49.9-1%-LF 1 ˖ˣ˨˲˩˜˗˄ AL5 VID1 VCCP AH11 R0603 R0603
1
CPU_VID[7..0] 2 ˖ˣ˨˲˩˜˗˅
AM3 VID2 VCCP AH12 EMPTY EMPTY
8,38 CPU_VID[7..0]
V1P2_FSBVTT 3 ˖ˣ˨˲˩˜˗ˆ AL6 VID3 VCCP AH14
1
4 ˖ˣ˨˲˩˜˗ˇ AK4 VID4 VCCP AH15 CPU_MSID1
B 5 ˖ˣ˨˲˩˜˗ˈ B
1 2 AL4 VID5 VCCP AH18
FB6 10UH/125MA/0805-LF 12 MIL TRACE VCCP AH19 CPU_MSID0
2
1 2 VCCA A23 VCCA VCCP AH21
FB7 10UH/125MA/0805-LF VCCIOPLL C23 VCCIOPLL VCCP AH22 R165 R162
1
PLL ANALOG FILTER CT45 C126 C131 VSSA B23 VSSA VCCP AH25 51.1-1%-LF 51.1-1%-LF
1% 1%
CT47 CT49 CPU_MSID1 V1 MSID1 VCCP AH26 R0603 R0603
PLL 33UF CAP MUST BE: EMPTY CPU_MSID0 W1 MSID0 VCCP AH27
ESL <= 9NH
VCCP AH28 LAYOUT:
2
1
ESR <= 0.3 OHMS TP2 Y1 BOOTSELECT VCCP AH29 Close to CPU
TRACE FROM 33UF CAP MUST 10UF/Y5V/10V/0805-LF x10UF/X5R/16V/0805-LF VTT_OUT_LEFT 40 SKTOCC# AE8 SKTOCC* VCCP AH30
BE WITHIN 750 MILS OF PIN x10UF/X5R/6.3V/0805-LF 1UF/16V-LF V1P2_FSBVTT VCCP AH8
PLACE INDUCTOR CLOSE TO CAP 0.1UF/X7R/16V/0402-LF F26 TESTHI0 VCCP AH9
W3 TESTHI1 VCCP AJ11
2
TRACE WIDTH TO CAPS MUST BE NO SMALLER THAN 12MIL F25 TESTHI2 VCCP AJ12
2
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET R281 R282 G25 TESTHI3 VCCP AJ14 VTT_OUT_RIGHT VTT_OUT_LEFT
R177 R158 R167 R163 R133 R119 R139 1% 1%
G27 TESTHI4 VCCP AJ15
1% 1% 1% 1% 1% 1% 1%
R0603 R0603 G26 TESTHI5 VCCP AJ18
R0603 R0603 R0603 R0603 R0603 R0603 R0603 51.1-1%-LF G24 TESTHI6 VCCP AJ19
51.1-1%-LF 51.1-1%-LF 51.1-1%-LF 51.1-1%-LF 51.1-1%-LF F24 TESTHI7 VCCP AJ21
1
1
51.1-1%-LF 51.1-1%-LF 51.1-1%-LF TE STHI_0 G3 TESTHI8 VCCP AJ22 C62 C56 C58 C71
1
TE STHI_1 G4 TESTHI9 VCCP AJ25

TESTHI_2-7 H5 TESTHI10 VCCP AJ26 C0603
X5R
C0603
X5R
C0603
X5R
C0603
X5R
6.3V 6.3V 6.3V 6.3V
TE STHI_8 P1 TESTHI11 VCCP AJ8 10% 10% 10% 10%
8 TESTHI_8
2
TE STHI_9 W2 TESTHI12 VCCP AJ9 1UF/16V-LF 1UF/16V-LF
8 TESTHI_9
T ESTHI_10 L2 TESTHI13 VCCP AK11 1UF/16V-LF 1UF/16V-LF
T ESTHI_11
T ESTHI_12 I126
8 TESTHI_12
CPU_SLP* CPU_SLP_R*
A CPU_SLP* A
a.from C55
b.MCP73 CRB no this
Title
SOCKET 775 PART 2

A3 0.2
I-N73V
5 4 3 2 1
5 4 3 2 1
VTT_OUT_LEFT
V1P2_FSBVTT
U6D
SK-C775P
2
62 -> 60.4-1%-0402
SKT_775P
R171
60.4-1%-0402-LF
Y7 GND 4 OF 5 VTT A25
Y2 GND VTT A26
F7 GND VTT A27
D CPU_G1 G1 GND VTT A28 D
CPU_G1
21
VCCP U6E
SK-C775P H10 GND VTT A29
VCCP H11 GND VTT A30
R146
SKT_775P x0-LF H12 GND VTT B25
5%
AK12 VCCP 5 OF 5 VCCP J30 R0603 H13 GND VTT B26
AK14 VCCP VCCP J8 H14 GND VTT B27
AK15 VCCP VCCP J9 EMPTY H17 GND VTT B28
1
AK18 VCCP VCCP K23 H18 GND VTT B29
AK19 VCCP VCCP K24 H19 GND VTT B30
AK21 VCCP VCCP K25 H20 GND VTT C25
AL11 VCCP VCCP K8 H26 GND VTT D25 V1P2_FSBVTT
AL12 VCCP VCCP L8 H27 GND VTT D26 VTT_OUT_LEFT
AL14 VCCP VCCP M23 H28 GND VTT D27
AL15 VCCP VCCP M24 Y5 GND VTT D28 VTT_OUT_RIGHT
2
AL18 VCCP VCCP M25 H3 GND VTT D29 KENTSFIELD SUPPORT
AL19 VCCP VCCP M26 H6 GND VTT D30 R283
AL21 VCCP VCCP M27 H7 GND IF CPU_VTT_SEL USED,
5%
AL22 VCCP VCCP M28 H8 GND VTT_OUT_LEFT J1 R0603 EMPTY VTT_SEL= 1, VTT= 1.2V
AL25 VCCP VCCP M29 H9 GND VTT_OUT_RIGHT AA1 150-1%-LF VTT_SEL= 0, VTT= 1.1V
AL26 VCCP VCCP M30 J4 GND VTT_OUT_RIGHT VTT_OUT_RIGHT VTT_OUT_LEFT
1
AL29 VCCP VCCP M8 J7 GND VTT_SEL F27 CPU_VTT_SEL VTT_OUT_LEFT
CPU_VTT_SEL 16,33
AL30 VCCP VCCP N23 K2 GND GTLREF_SEL H29 N C TP_GTLREF_SEL
2
AL8 VCCP VCCP N24 K5 GND
2
AL9 VCCP VCCP N25 K7 GND FC3 J2 CPU_COMP4 R88
C AM11 VCCP VCCP N26 L23 GND FC4 T2 CPU_COMP5 R115 R135 R157 R160 R184 C
5%
AM12 VCCP VCCP N27 L24 GND FC6 H2 CPU_GTLREF1 R0603 CPU_VIDSEL:
CPU_GTLREF1 7,9 1% 1% 1% 1% 1%
AM14 VCCP VCCP N28 L25 GND FC11 AM5 6 ˖ˣ˨˲˩˜˗ˉ CPU_VID[7..0] 680-LF High: VRD11 R0603 R0603 R0603 R0603 R0402
CPU_VID[7..0] 7,38
AM15 VCCP VCCP N29 L26 GND FC12 AM7 7 ˖ˣ˨˲˩˜˗ˊ
Low: VRD 10.X 49.9-1%-LF 49.9-1%-LF 49.9-1%-0402-LF
2 1
AM18 VCCP VCCP N30 L27 GND FC16 AN7 CPU_VIDSEL 49.9-1%-LF 49.9-1%-LF
CPU_VIDSEL 29,38
1
AM19 VCCP VCCP N8 L28 GND CPU_COMP4
AM21 VCCP VCCP P8 L29 GND VCC_MB_REG AN5 VCC_MB_REG R92 1 2 0-LF R87 CPU_COMP5
AM22 VCCP VCCP R8 L3 GND VSS_MB_REG AN6 VSS_MB_REG 1 2 CPU_COMP6
1%
AM25 VCCP VCCP T23 L30 GND R91 0-LF DIFF PAIR R0603 EMPTY CPU_COMP7
AM26 VCCP VCCP T24 L6 GND VCCSENSE AN3 VCC_SENSE CPU_CORE_FB+ x51.1-1%-LF CPU_C9
CPU_CORE_FB+ 29
AM29 VCCP VCCP T25 L7 GND VSSSENSE AN4 VSS_SENSE CPU_CORE_FB- 1 2 CPU_COMP8
CPU_CORE_FB- 29
1
AM30 VCCP VCCP T26 M1 GND 1 EMPTY 2 R261
AM8 VCCP VCCP T27 M7 GND RSVD A20 NC R94 x0-LF 24.9-1%-LF
AM9 VCCP VCCP T28 N3 GND RSVD AC4 NC 1 EMPTY 2
AN11 VCCP VCCP T29 N6 GND RSVD AE3 CPU_COMP7 R93 x0-LF
AN12 VCCP VCCP T30 N7 GND RSVD AE4 NC
AN14 VCCP VCCP T8 P23 GND RSVD AE6
AN15 VCCP VCCP U23 P24 GND RSVD AH2
AN18 VCCP VCCP U24 P25 GND RSVD C9 CPU_C9
C55_GTLREF
AN19 VCCP VCCP U25 P26 GND RSVD D1 NC VCC5
AN21 U26 P27 D14 NC P_GTLREF
AN22
VCCP
VCCP
VCCP
VCCP U27 P28
GND
GND
RSVD
RSVD D16
P_GTLREF 9
VCC3 CPU VCC for PLL
AN25 VCCP VCCP U28 P29 GND RSVD E23 NC
AN26 VCCP VCCP U29 P30 GND RSVD E24 CRB no this FB8
AN29 VCCP VCCP U30 P4 GND RSVD E5 CPU_E5_PD 1EMPTY 2 30OHM/3A/40mOHM-LF U10
AN30 VCCP VCCP U8 P7 GND RSVD E6 NC R107 x1K-LF 1 5
VIN VOUT CPU_VCC_PLL
AN8 VCCP VCCP V8 R2 GND RSVD E7 NC
1
AN9 VCCP VCCP W23 R23 GND RSVD F23 NC 2 1 R1 R264
J10 VCCP VCCP W24 R24 GND RSVD F29 NC R209 49.9-1%-0402-LF 0603 3 3.01K-1%-LF C132
B SEL_50_60_OHM CT50 C153 EN 06031UF/X7R/16V-LF B
J11 VCCP VCCP W25 R25 GND RSVD F6
J12 VCCP VCCP W26 R26 GND RSVD G10 CPU_GTLREF2 1UF/X7R/16V-LF
CPU_GTLREF2 7,9
2
J13 VCCP VCCP W27 R27 GND RSVD B13 CPU_COMP8 VTT_OUT_RIGHT VTT_OUT_LEFT 10UF/X5R/6.3V/0805-LF 2 GND 4 Layout
ADJ Near RT9179
J14 VCCP VCCP W28 R28 GND RSVD J3 CPU_J3_PD 1EMPTY 2
2
J15 VCCP VCCP W29 R29 GND RSVD N4 NC R172 x1K-LF RT9179-LF R2 R268
2
J18 VCCP VCCP W30 R30 GND RSVD N5 NC CRB no this 10K-1%-LF
J19 VCCP VCCP W8 R5 GND RSVD P5 NC R90 R113 Vout = 1.175*(1+R1/R2)
J20 VCCP VCCP Y23 R7 GND RSVD Y3 CPU_COMP6 150-1%-LF = 1.175 (1+3.01K/10K) Ext. FB resistor
1%
J21 VCCP VCCP Y24 T3 GND RSVD D23 CPU_VCC_PLL R0603 = 1.529V must be 1xx -9xxK \ohm
J22 VCCP VCCP Y25 T6 GND RSVD AK6 CPU_FORCE* 51.1-1%-LF
1
J23 VCCP VCCP Y26 T7 GND RSVD G6 CPU_RSVD_G6
1
J24 VCCP VCCP Y27 U1 GND
J25 VCCP VCCP Y28 U7 GND GND V29 CPU_VCC_PLL
J26 VCCP VCCP Y29 V23 GND GND V3
1
J27 VCCP VCCP Y30 V24 GND GND V30 C127 CT48 CT46 VTT_OUT_LEFT VTT_OUT_RIGHT
J28 VCCP VCCP Y8 V25 GND GND V6 x10UF/X5R/6.3V/0805-LF KENTSFIELD SUPPORT (CRB no this)
J29 VCCP V26 GND GND V7 961213 ECR
V27 GND GND W4 Cost down (ref. from IL9_v0.2)
2
I128 V28 GND GND W7

10UF/X5R/6.3V/0805-LF + CT12 + CT9 CPU_BPM*[5..0]
I129 7 CPU_BPM*[5..0]
CPU_FORCE* 40
0.01UF/16V/0402-LF 10UF/Y5V/10V/0805-LF
10UF/Y5V/10V/0805-LF CPU_G1 R176 1 EMPTY 2 x0-LF 0
˖ˣ˨˲˕ˣˠʽ˃
CPU_C9 R117 1 EMPTY 2 x0-LF 1

˖ˣ˨˲˕ˣˠʽ˄
R169 T ESTHI_12 TE STHI_9 R134 EMPTY x0-LF 2
1 2 TESTHI_12 7 7 TESTHI_9 1 2 ˖ˣ˨˲˕ˣˠʽ˅
R0603 5% VCC3 TE STHI_8 R125 1 EMPTY 2 x0-LF 3

˖ˣ˨˲˕ˣˠʽˆ
7 TESTHI_8
0-LF 1.CRB from PWM's VRHOT
2
2.IL9_v0.2 only pull-hi VCC3 VTT_OUT_LEFT VTT_OUT_RIGHT

A R168 USE RTOP = 3.83K, RBOT = 10K, RFET = 32.4K A
x0-LF 95.10.30
5%
CRB R0603
no this EMPTY
1
C84 C90 C61
1
from SIO-GPIO
C0402 C0402 C0402
38 CPU_FORCE_PR_SIO* X7R
16V
X7R
16V
X7R
16V
10% 10% 10%
2
2
Title
0.1UF/16V/0402-LF
0.1UF/16V/0402-LF SOCKET 775 PART 3
0.1UF/16V/0402-LF Size Document Number Rev
A3 I-N73V 0.2
5 4 3 2 1
5 4 3 2 1
D D
VTT_OUT_RIGHT
GTLREF voltage should be
0.63 x VTT = 0.75V
CRB: 63.4-1%
R196 LAYOUT:
49.9-1%-LF
Close to CPU
0.667*VTT
( Reference from IP35 ) CPU_GTLREF02_R 1R195 2 CPU_GTLREF
CPU_GTLREF 7,8
10-1%-0402-LF
1
CPU_GTLREF2 7,8
KENTSFIELD SUPPORT: R197 C77 C76 C75
100-1%-LF 1UF/16V-LF
SEL1 SEL0 GTLREF
2
3VDUAL VCC12
0 0 64% (0.76815V) 0.1UF/16V/0402-LF
0 1 65% (0.77770V) 220PF/X7R/0402-LF
1 0 66% (0.79044V) 3VDUAL
1 1 * 67% (0.80052V)
* default 3VDUAL VCC12
C C
CPU_GTLREF_SEL0 VTT_OUT_RIGHT
GTLREF voltage should be
0.63 x VTT = 0.75V
CRB: 63.4-1%
CPU_GTLREF_SEL1 R188 LAYOUT:

49.9-1%-LF
Close to CPU
0.667*VTT
CPU_GTLREF13_R 2R187 1 CPU_GTLREF1
CPU_GTLREF1 7,8
IN
CPU_GTLREF1_SEL 10-1%-0402-LF
1
CPU_GTLREF3 7,8
MCP73 CRB: R180 C70 C81 C73
IF CPU_GTLREF1_SEL USED, 100-1%-LF 1UF/16V-LF
CPU_GTLREF1_SEL= 1, CPU_GTLREF1=0.684*VTT
2
CPU_GTLREF1_SEL= 0, CPU_GTLREF1=0.609*VTT
0.1UF/16V/0402-LF
220PF/X7R/0402-LF
B B
VTT_OUT_RIGHT VTT_OUT_LEFT
2
CRB: 88.7-1%
R131
100-1%-LF R114
84.5-1%-LF
IF 100//84.5=45.8ohm
=> GTLREF= 0.772V
1
C55_GTLREF
IF 100//88.7=47.0ohm R110
=> GTLREF=0.764V P_GTLREF_R 1 2 P_GTLREF 8
35.7-1%-LF
1
1
R109 C44 C49
82.5-1%-LF C45
1UF/16V-LF
2
2
0.1UF/16V/0402-LF
1
220PF/X7R/0402-LF
A A
Title
SOCKET 775 GTLREF

A3 I-N73V 0.2
5 4 3 2 1
U16A
BGA1048 MCP73 CPU_D*[63..0]
CPU_D*[63..0] 6
SEC 1 OF 10
CPU_DSTBP0* V36 CPU_DSTBP0# CPU_D0# AB36 0 ˖ˣ˨˲˗ʽ˃
6 CPU_DSTBP0*
CPU_DSTBN0* W36 CPU_DSTBN0# CPU_D1# AA36 1 ˖ˣ˨˲˗ʽ˄
6 CPU_DSTBN0*
CPU_DBI0* W37 CPU_DBI0# CPU_D2# AB37 2 ˖ˣ˨˲˗ʽ˅
6 CPU_DBI0*
CPU_D3# Y36 3 ˖ˣ˨˲˗ʽˆ
CPU_DSTBP1* N31 CPU_DSTBP1# CPU_D4# AA35 4 ˖ˣ˨˲˗ʽˇ
6 CPU_DSTBP1*
CPU_DSTBN1* P30 CPU_DSTBN1# CPU_D5# Y35 5 ˖ˣ˨˲˗ʽˈ
6 CPU_DSTBN1*
CPU_DBI1* R34 CPU_DBI1# CPU_D6# Y37 6 ˖ˣ˨˲˗ʽˉ
6 CPU_DBI1*
CPU_D7# Y38 7 ˖ˣ˨˲˗ʽˊ
CPU_DSTBP2* G33 CPU_DSTBP2# CPU_D8# U35 8 ˖ˣ˨˲˗ʽˋ
6 CPU_DSTBP2*
CPU_DSTBN2* G35 CPU_DSTBN2# CPU_D9# T35 9 ˖ˣ˨˲˗ʽˌ
6 CPU_DSTBN2*
CPU_DBI2* H31 CPU_DBI2# CPU_D10# U36 10 ˖ˣ˨˲˗ʽ˄˃
6 CPU_DBI2*
CPU_D11# T36 11 ˖ˣ˨˲˗ʽ˄˄
CPU_DSTBP3* M38 CPU_DSTBP3# CPU_D12# V37 12 ˖ˣ˨˲˗ʽ˄˅
6 CPU_DSTBP3*
CPU_DSTBN3* N36 CPU_DSTBN3# CPU_D13# T37 13 ˖ˣ˨˲˗ʽ˄ˆ
6 CPU_DSTBN3*
CPU_DBI3* J35 CPU_DBI3# CPU_D14# R37 14 ˖ˣ˨˲˗ʽ˄ˇ
6 CPU_DBI3*
CPU_D15# T38 15 ˖ˣ˨˲˗ʽ˄ˈ
CPU_D16# R31 16 ˖ˣ˨˲˗ʽ˄ˉ
CPU_D17# U33 17 ˖ˣ˨˲˗ʽ˄ˊ

3 ˖ˣ˨˲˔ʽˆ W34 CPU_A3# CPU_D18# U34 18 ˖ˣ˨˲˗ʽ˄ˋ
4 ˖ˣ˨˲˔ʽˇ AA34 CPU_A4# CPU_D19# R30 19 ˖ˣ˨˲˗ʽ˄ˌ
5 ˖ˣ˨˲˔ʽˈ W31 CPU_A5# CPU_D20# U32 20 ˖ˣ˨˲˗ʽ˅˃
6 ˖ˣ˨˲˔ʽˉ W33 CPU_A6# CPU_D21# R32 21 ˖ˣ˨˲˗ʽ˅˄
7 ˖ˣ˨˲˔ʽˊ
W32 CPU_A7# CPU_D22# R33 22 ˖ˣ˨˲˗ʽ˅˅
8 ˖ˣ˨˲˔ʽˋ AA32 CPU_A8# CPU_D23# R35 23 ˖ˣ˨˲˗ʽ˅ˆ
9 ˖ˣ˨˲˔ʽˌ AA31 CPU_A9# CPU_D24# N30 24 ˖ˣ˨˲˗ʽ˅ˇ
10 ˖ˣ˨˲˔ʽ˄˃
AB30 CPU_A10# CPU_D25# N32 25 ˖ˣ˨˲˗ʽ˅ˈ MCP73 Design Guide_v0.1:
11 ˖ˣ˨˲˔ʽ˄˄
AA30 CPU_A11# CPU_D26# N33 26 ˖ˣ˨˲˗ʽ˅ˉ Removed termination on BCLK
12 ˖ˣ˨˲˔ʽ˄˅
AC35 CPU_A12# CPU_D27# N34 27 ˖ˣ˨˲˗ʽ˅ˊ output to CPU, ITP/XDP, and BCLK_IN
13 ˖ˣ˨˲˔ʽ˄ˆ
AC34 CPU_A13# CPU_D28# L30 28 ˖ˣ˨˲˗ʽ˅ˋ 2007.6.22
14 ˖ˣ˨˲˔ʽ˄ˇ
AC33 CPU_A14# CPU_D29# L31 29 ˖ˣ˨˲˗ʽ˅ˌ
15 ˖ˣ˨˲˔ʽ˄ˈ
AC32 CPU_A15# CPU_D30# L33 30 ˖ˣ˨˲˗ʽˆ˃
16 ˖ˣ˨˲˔ʽ˄ˉ
AC31 CPU_A16# CPU_D31# L32 31 ˖ˣ˨˲˗ʽˆ˄
17 ˖ˣ˨˲˔ʽ˄ˊ
AE30 CPU_A17# CPU_D32# L35 32 ˖ˣ˨˲˗ʽˆ˅ 33ohm -> 0ohm
18 ˖ˣ˨˲˔ʽ˄ˋ
AC30 CPU_A18# CPU_D33# L34 33 ˖ˣ˨˲˗ʽˆˆ CPU_CLK
CPU_CLK 7
19 ˖ˣ˨˲˔ʽ˄ˌ
AE34 CPU_A19# CPU_D34# K30 34 ˖ˣ˨˲˗ʽˆˇ R304 0-LF CPU_CLK*
CPU_CLK* 7
20 ˖ˣ˨˲˔ʽ˅˃
AE33 CPU_A20# CPU_D35# J34 35 ˖ˣ˨˲˗ʽˆˈ R303 0-LF
2
21 ˖ˣ˨˲˔ʽ˅˄
AE31 CPU_A21# CPU_D36# J31 36 ˖ˣ˨˲˗ʽˆˉ
1
22 ˖ˣ˨˲˔ʽ˅˅
AG33 CPU_A22# CPU_D37# J30 37 ˖ˣ˨˲˗ʽˆˊ
R296 R297 C173 C171
23 ˖ˣ˨˲˔ʽ˅ˆ
AE32 CPU_A23# CPU_D38# J33 38 ˖ˣ˨˲˗ʽˆˋ
24 39 ˖ˣ˨˲˗ʽˆˌ EMPTY EMPTY
˖ˣ˨˲˔ʽ˅ˇ
AG35 CPU_A24# CPU_D39# J32
25 ˖ˣ˨˲˔ʽ˅ˈ
AG34 CPU_A25# CPU_D40# G31 40 ˖ˣ˨˲˗ʽˇ˃
2
26 ˖ˣ˨˲˔ʽ˅ˉ
AF30 CPU_A26# CPU_D41# G34 41 ˖ˣ˨˲˗ʽˇ˄
1
27 ˖ˣ˨˲˔ʽ˅ˊ
AG31 CPU_A27# CPU_D42# G36 42 ˖ˣ˨˲˗ʽˇ˅
28 ˖ˣ˨˲˔ʽ˅ˋ
AG30 CPU_A28# CPU_D43# F33 43 ˖ˣ˨˲˗ʽˇˆ x49.9-1%-LF x15PF/NPO/50V/0402-LF
29 ˖ˣ˨˲˔ʽ˅ˌ
AJ32 CPU_A29# CPU_D44# E33 44 ˖ˣ˨˲˗ʽˇˇ x49.9-1%-LF x15PF/NPO/50V/0402-LF
30 ˖ˣ˨˲˔ʽˆ˃
AJ34 CPU_A30# CPU_D45# E35 45 ˖ˣ˨˲˗ʽˇˈ
31 ˖ˣ˨˲˔ʽˆ˄
AJ33 CPU_A31# CPU_D46# D35 46 ˖ˣ˨˲˗ʽˇˉ XDP_CLK
XDP_CLK
32 ˖ˣ˨˲˔ʽˆ˅
AJ30 CPU_A32# CPU_D47# D36 47 ˖ˣ˨˲˗ʽˇˊ XDP_CLK*
XDP_CLK*
33 ˖ˣ˨˲˔ʽˆˆ
AJ31 CPU_A33# CPU_D48# J36 48 ˖ˣ˨˲˗ʽˇˋ
34 ˖ˣ˨˲˔ʽˆˇ
AL35 CPU_A34# CPU_D49# M37 49 ˖ˣ˨˲˗ʽˇˌ
33ohm -> 0ohm
CPU_A*[35..3] 35 50 ˖ˣ˨˲˗ʽˈ˃ CPU_ITP_CLK EMPTY
6 CPU_A*[35..3]
˖ˣ˨˲˔ʽˆˈ
AK30 CPU_A35# CPU_D50# R36 1 2 INTERPOSER_BCLK 7
CPU_D51# N35 51 ˖ˣ˨˲˗ʽˈ˄ R290 x0-LF R223 x0-LF
CPU_ADSTB0* 52 ˖ˣ˨˲˗ʽˈ˅ CPU_ITP_CLK* EMPTY
6 CPU_ADSTB0* AA33 CPU_ADSTB0# CPU_D52# P37 1 2 INTERPOSER_BCLK* 7
CPU_ADSTB1* AG32 CPU_ADSTB1# CPU_D53# P36 53 ˖ˣ˨˲˗ʽˈˆ
R288 x0-LF R222 x0-LF
6 CPU_ADSTB1*
2
CPU_REQ*[4..0] CPU_D54# L36 54 ˖ˣ˨˲˗ʽˈˇ R280 R284 to CPU
6 CPU_REQ*[4..0]
1
0 ˖ˣ˨˲˥˘ˤʽ˃ V30 CPU_REQ0# CPU_D55# M35 55 ˖ˣ˨˲˗ʽˈˈ C157 C159 (CPU Test Bus Clock)
1 ˖ˣ˨˲˥˘ˤʽ˄ U31 CPU_REQ1# CPU_D56# M36 56 ˖ˣ˨˲˗ʽˈˉ Layout near CPU
2 ˖ˣ˨˲˥˘ˤʽ˅ 57 ˖ˣ˨˲˗ʽˈˊ EMPTY EMPTY
W30 CPU_REQ2# CPU_D57# L37
3 ˖ˣ˨˲˥˘ˤʽˆ W35 CPU_REQ3# CPU_D58# H36 58 ˖ˣ˨˲˗ʽˈˋ
2
4 ˖ˣ˨˲˥˘ˤʽˇ U30 CPU_REQ4# CPU_D59# H35 59 ˖ˣ˨˲˗ʽˈˌ
1
CPU_D60# K36 60 ˖ˣ˨˲˗ʽˉ˃
CPU_D61# K37 61 ˖ˣ˨˲˗ʽˉ˄ x49.9-1%-LF x15PF/NPO/50V/0402-LF

CPU_D62# H38 62 ˖ˣ˨˲˗ʽˉ˅ x49.9-1%-LF x15PF/NPO/50V/0402-LF
CPU_ADS* AF37 CPU_ADS# CPU_D63# H37 63 ˖ˣ˨˲˗ʽˉˆ
6 CPU_ADS*
CPU_BNR* AF36 CPU_BNR#
6 CPU_BNR*
CPU_BR0* AH37 CPU_BR0# CPU_RESET# C36 CPU_RST* MCP73 Design Guide_v0.1:
6 CPU_BR0* CPU_RST* 6
CPU_BPRI* AC36 CPU_BPRI# Removed termination on BCLK
6 CPU_BPRI* CPU_RST*
CPU_DBSY* AE35 CPU_DBSY# OUT output to CPU, ITP/XDP, and BCLK_IN
6 CPU_DBSY*
CPU_DEFER* AC37 CPU_DEFER# 2007.6.22
6 CPU_DEFER*
CPU_DRDY* AG36 CPU_DRDY# BCLK_OUT_CPU_P G38 CPU_CLKR
6 CPU_DRDY*
CPU_HIT* AD38 CPU_HIT# BCLK_OUT_CPU_N G37 CPU_CLKR*
6 CPU_HIT*
CPU_HITM* AG37 CPU_HITM# V1P2_FSBVTT
6 CPU_HITM*
CPU_LOCK* AE36 CPU_LOCK# BCLK_OUT_ITP_P AN36 CPU_ITP_CLKR
CPU_RS*[2..0]
6 CPU_LOCK*
CPU_TRDY* AG38 CPU_TRDY# BCLK_OUT_ITP_N AM35 CPU_ITP_CLKR*
6 CPU_RS*[2..0] 6 CPU_TRDY*
0 ˖ˣ˨˲˥˦ʽ˃ AD36 CPU_RS0#
2
1 ˖ˣ˨˲˥˦ʽ˄ AD37 CPU_RS1# BCLK_OUT_MCP_P D37 33ohm -> 0ohm 1 R294 2
2 ˖ˣ˨˲˥˦ʽ˅ AD35 CPU_RS2# BCLK_OUT_MCP_N D38 R300 0-LF x49.9-1%-0402-LF R275 R274 R276
R301 0-LF 470-LF 470-LF 470-LF
5% 5% 5%
7 CPU_FERR*
CPU_FERR* AL38 FERR# BCLK_IN_N C37 BCLK_IN* 1 R295 2 R0603 R0603 R0603
CPU_A20M* AH38 A20M# BCLK_IN_P C38 BCLK_IN x49.9-1%-0402-LF

7 CPU_A20M*
CPU_IGNNE* AK36 IGNNE# from CPU
7 CPU_IGNNE*
1
CPU_INIT* AL36 INIT# BSEL0 F36 BSEL0
7 CPU_INIT* BSEL0 7
CPU_SMI* AL37 SMI# BSEL1 E36 BSEL1
7 CPU_SMI* BSEL1 7
CPU_INTR AH36 LINT0_INTR BSEL2 F37 BSEL2_MCP BSEL2
7 CPU_INTR BSEL2 7
CPU_NMI AH35 LINT1_NMI R741 0-LF
7 CPU_NMI
CPU_STPCLK* AJ36 STPCLK# PECI B37 CPU_PECI_MCP
7 CPU_STPCLK* CPU_PECI_MCP 7
MCP73_CPU_PWRGD AK37 CPU_PWRGD PROCHOT# AM36 CPU_PROCHOT* 3VDUAL R742 FSB Frequency Bus Select :
7 MCP73_CPU_PWRGD CPU_PROCHOT* 7,40
THERMTRIP# AJ35 CPU_THERMTRIP* v0.2 BOM x470-LF
CPU_THERMTRIP* 7
VTT_OUT_RIGHT latched at the rising edge of CPU_PWRGD.
1 2 AM38 CPU_COMP_VCC
1/16 R743
D
R285 40.2-1%-LF BCLK_COMP B38 CPU_CLK_COMP 1 2 x10K-0402-LF
1 2 AM37 CPU_COMP_GND R299 Q100
R286 40.2-1%-LF x2.37K-1%-LF G x2N7002-LF
I3463 38 BSEL2_LOW_EN
EMPTY
S
v0.2 BOM
49.9 -> 40.2ohm
Title
MCP73 CPU
A3 I-N73V 0.2
U16B
BGA1048 MCP73 PE_X16-1_TXC[15..0]
PE_X16-1_TXC[15..0] 24
SEC 3 OF 10
P E1_TXC H9 PE1_TX0_P PE0_TX15_P V4 15 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˄ˈ
25 PE1_TXC
PE1_TXC* H8 PE1_TX0_N PE0_TX14_P U2 14 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˄ˇ
25 PE1_TXC*
Level shift PE0_TX13_P T2 13 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˄ˆ
PE1_RX H7 PE1_RX0_P PE0_TX12_P R1 12 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˄˅
25 PE1_RX
3VDUAL PE1_RX* H6 PE1_RX0_N PE0_TX11_P R4 11 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˄˄
25 PE1_RX*
PE0_TX10_P P4 10 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˄˃
PE1_REFCLK B1 PE1_REFCLK_P PE0_TX9_P N2 9 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˌ
25 PE1_REFCLK
PE1_REFCLK* C1 PE1_REFCLK_N PE0_TX8_P M2 8 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˋ
25 PE1_REFCLK*
1
C401 PE0_TX7_P L1 7 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˊ
R562 R561 PE1_PRESENT* F6 PEA_PRSNT# PE0_TX6_P L4 6 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˉ
25 PE1_PRESENT*
10K-0402-LF F5 PEA_CLKREQ# PE0_TX5_P K4 5 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˈ
3VDUAL 0.1UF/16V/0402-LF10K-0402-LF to Slot PE0_TX4_P J2 4 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˇ
2
PE_RESET* PE0_TX3_P H2 3 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˆ
PE_RESET* 24,25
Prevnt Glitch CRB: PE0_TX2_P G1 2 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˅
D
74LVC08 -> BAT54A NC TP_P E2_TXC D2 PE2_TX0_P PE0_TX1_P G4 1 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˄
R559 NC T P_PE2_TXC* D3 PE2_TX0_N PE0_TX0_P F4 0 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˃ PE_X16-1_TXC*[15..0]

PE_X16-1_TXC*[15..0] 24
D26 10K-0402-LF G Q69 PE0_TX15_N V3 15 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˄ˈ
BAT54A-LF 2N7002-LF NC T P_PE2_RX E2 PE2_RX0_P PE0_TX14_N U3 14 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˄ˇ
S
MCP_PWRGD K1 NC TP_PE2_RX* E3 PE2_RX0_N PE0_TX13_N T3 13 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˄ˆ
16,31 MCP_PWRGD 1
A R554 B Q68 PE0_TX12_N R2 12 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˄˅
K2 2 2.2K-LF PMBS3904-LF 3VDUAL NC TP_PE2_REFCLK A2 PE2_REFCLK_P PE0_TX11_N R3 11 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˄˄

NC TP_PE2_REFCLK* B2 PE2_REFCLK_N PE0_TX10_N P3 10 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˄˃
E
PE0_TX9_N N3 9 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽˌ
NC TP_PE2_PRESENT* F7 PEB_PRSNT# PE0_TX8_N M3 8 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽˋ
10k PE0_TX7_N L2 7 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽˊ
PE0_TX6_N L3 6 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽˉ
R623 x0-0402-LF PE0_TX5_N K3 5 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽˈ
PE_RESET_GATE* E7 PEX_RST0# PE0_TX4_N J3 4 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽˇ
PE_WAKE* E13 PE_WAKE#/GPIO_21 PE0_TX3_N H3 3 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽˆ
24,25 PE_WAKE*
1 2 PE_CLK_COMP A3 PEX_CLK_COMP PE0_TX2_N G2 2 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˅
R415 x2.37K-1%-LF PE0_TX1_N G3 1 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˄
EMPTY PE0_TX0_N F3 0 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˃
PE_X16-1_RX[15..0]
PE_X16-1_RX[15..0] 24
1/16 PE0_RX15_P V6 15 ˣ˘˲˫˄ˉˀ˄˲˥˫˄ˈ
PE0_RX14_P V8 14 ˣ˘˲˫˄ˉˀ˄˲˥˫˄ˇ
HDMI_TXD0P NC A35 HDMI_TXD0_P PE0_RX13_P U9 13 ˣ˘˲˫˄ˉˀ˄˲˥˫˄ˆ
HDMI_TXD0P
HDMI_TXD0N NC A36 HDMI_TXD0_N PE0_RX12_P T5 12 ˣ˘˲˫˄ˉˀ˄˲˥˫˄˅
HDMI_TXD0N
HDMI_TXD1P NC C35 HDMI_TXD1_P PE0_RX11_P T7 11 ˣ˘˲˫˄ˉˀ˄˲˥˫˄˄
HDMI_TXD1P
BACKDRIVE HDMI_TXD1N NC B35 HDMI_TXD1_N PE0_RX10_P T9 10 ˣ˘˲˫˄ˉˀ˄˲˥˫˄˃
HDMI_TXD1N
PREVENTION CIRCUIT VCC3 HDMI_TXD2P NC C34 HDMI_TXD2_P PE0_RX9_P P6 9 ˣ˘˲˫˄ˉˀ˄˲˥˫ˌ
HDMI_TXD2P
HDMI_TXD2N NC B34 HDMI_TXD2_N PE0_RX8_P P8 8 ˣ˘˲˫˄ˉˀ˄˲˥˫ˋ
HDMI_TXD2N
PE0_RX7_P N9 7 ˣ˘˲˫˄ˉˀ˄˲˥˫ˊ
APM4500KCTRL HDMI_TXC0P NC B36 HDMI_TXC_P PE0_RX6_P M5 6 ˣ˘˲˫˄ˉˀ˄˲˥˫ˉ
HDMI_TXC0P
NPN+PNP HDMI_TXC0N NC A37 HDMI_TXC_N PE0_RX5_P M7 5 ˣ˘˲˫˄ˉˀ˄˲˥˫ˈ
16,31 MCP_PWRGD HDMI_TXC0N

PE0_RX4_P M9 4 ˣ˘˲˫˄ˉˀ˄˲˥˫ˇ
PE0_RX3_P K6 3 ˣ˘˲˫˄ˉˀ˄˲˥˫ˆ
PE0_RX2_P K8 2 ˣ˘˲˫˄ˉˀ˄˲˥˫˅
BR29 x1K-LF HDMI_RSET D34 HDMI_RSET PE0_RX1_P J9 1 ˣ˘˲˫˄ˉˀ˄˲˥˫˄
EMPTY PE0_RX0_P H5 0 ˣ˘˲˫˄ˉˀ˄˲˥˫˃ PE_X16-1_RX*[15..0]

PE_X16-1_RX*[15..0] 24
PE0_RX15_N V5 15 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˄ˈ
VCC3 1/16 PE0_RX14_N V7 14 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˄ˇ
FB11 +3.3V_HDMI_IO C30 V3P3_HDMI_IO PE0_RX13_N V9 13 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˄ˆ
30OHM/3A/40mOHM-LF PE0_RX12_N T4 12 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˄˅
PE0_RX11_N T6 11 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˄˄
1
PE0_RX10_N T8 10 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˄˃
C196 +3.3V_HDMI_PLL_HVDD B30 V3P3_HDMI_PLL PE0_RX9_N P5 9 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽˌ
0.1UF/16V/0402-LF 8
PE0_RX8_N P7 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽˋ
PE0_RX7_N P9 7 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽˊ
2
PE0_RX6_N M4 6 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽˉ
PE0_RX5_N M6 5 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽˈ
PE0_RX4_N M8 4 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽˇ
DAC_BLUE A27 DAC_BLUE PE0_RX3_N K5 3 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽˆ
23 DAC_BLUE
DAC_GREEN B27 DAC_GREEN PE0_RX2_N K7 2 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˅
23 DAC_GREEN
DAC_RED C27 DAC_RED PE0_RX1_N K9 1 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˄
23 DAC_RED
PE0_RX0_N H4 0 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˃
2
DAC _HSYNC B28 DAC_HSYNC

23 DAC_HSYNC
BR26 BR27 BR28 DAC_VSYNC C28 DAC_VSYNC PE0_REFCLK_P C2 PE_X16-1_REFCLK
150-1%-LF 150-1%-LF 150-1%-LF
23 DAC_VSYNC PE_X16-1_REFCLK 24
PE0_REFCLK_N D1 PE_X16-1_REFCLK*
1% 1% 1% PE_X16-1_REFCLK* 24
0402_R 0402_R 0402_R 1 2 DAC_RSET C26 DAC_RSET
R330 2 1 DAC_VREF D28 DAC_VREF PE0_PRSNTX1#/DDC_CLK1 B3 PE_X16_PRESENTX1*
PE_X16_PRESENTX1* 24
124-1%-LF C199 0.01UF/16V/0402-LF PE0_PRSNTX4#/DDC_DATA1 B4 PE_X16_PRESENTX4*
1
PE0_PRSNTX8#/EXP_EN A4 PE_X16_PRESENTX8*
PE0_PRSNTX16# C4 PE_X16_PRESENTX16*
PLACE NEAR MCP73
V1P2_CORE
DDC_DATA D30 DDC_DATA0
23 DDC_DATA
DDC_CLK E29 DDC_CLK0 V1P2_PEX0_PLL M14 V1.2V_PEX_PLL BFB5
23 DDC_CLK
V1P2_PEX1_PLL N14 30OHM/3A/40mOHM-LF
1
BC22
BC16
HDMI_DDC_DATA F27 DDC_DATA3 0.1uF 1UF/16V-LF
HDMI_DDC_DATA
HDMI_DDC_CLK E27 DDC_CLK3 V1P2_PLL_XREF_XS0 M12 4.7uF/0805 -> 1uF
HDMI_DDC_CLK
2
HPLUG_DET3 G27 HPLUG_DET3 V1P2_PLL_XREF_XS1 M13
HPLUG_DET3
0.1UF/16V/0402-LF
VCC3
HDCP Key Stroge for HDMI V3P3_PLL_XREF_XS0 L8 V3.3V_PLL_IN BFB3
BOM 3: External I2C EEPROM V3P3_PLL_XREF_XS1 L9 30OHM/3A/40mOHM-LF
1
HDCP_ROM_SCLK D29 HDCP_ROM_SCLK BC42 BC11
HDCP_ROM_SDATA C29 HDCP_ROM_SDATA BC13
VCC3 VCC3 1UF/16V-LF
V3.3V_PLL_IN 12
Unused Interface V3P3_PLL_COREPLL H26 4.7uF/0805 -> 1uF
2
V3P3_VPLL F26
0.1UF/16V/0402-LF
R644 10K-0402-LF HPLUG_DET3 I552 0.1UF/16V/0402-LF
VCC3
EMPTY VCC3 R645 10K-0402-LF HDMI_DDC_DATA
SMB_SDA 16,24,25,26
AT24C16A R646 10K-0402-LF HDMI_DDC_CLK
SMB_SCL 16,24,25,26
R322 10K-0402-LF HDCP_ROM_SCLK
R328 10K-0402-LF HDCP_ROM_SDATA Title

VCC3
MCP73 PCIE/DAC/HDMI
A3 I-N73V 0.2
MEM_0_DQS[7..0]
20,21 MEM_0_DQS[7..0] U16C
BGA1048 MCP73
MEM_0_DQS*[7..0] SEC 2 OF 10 MEM_0_DATA[63..0]
20,21 MEM_0_DQS*[7..0] MEM_0_DATA[63..0] 20,21
0 ˠ˘ˠ˲˃˲˗ˤ˦˃ AU37 MDQS0_0 MDQ0_0 AT37 0 ˠ˘ˠ˲˃˲˗˔˧˔˃
0 ˠ˘ˠ˲˃˲˗ˤ˦ʽ˃ AU38 MDQS0_0# MDQ0_1 AT38 1 ˠ˘ˠ˲˃˲˗˔˧˔˄
1 ˠ˘ˠ˲˃˲˗ˤ˦˄
AN33 MDQS0_1 MDQ0_2 AU35 2 ˠ˘ˠ˲˃˲˗˔˧˔˅
1 ˠ˘ˠ˲˃˲˗ˤ˦ʽ˄ AN34 MDQS0_1# MDQ0_3 AV35 3 ˠ˘ˠ˲˃˲˗˔˧˔ˆ
2 ˠ˘ˠ˲˃˲˗ˤ˦˅ AU31 MDQS0_2 MDQ0_4 AR36 4 ˠ˘ˠ˲˃˲˗˔˧˔ˇ
2 ˠ˘ˠ˲˃˲˗ˤ˦ʽ˅ AV31 MDQS0_2# MDQ0_5 AR37 5 ˠ˘ˠ˲˃˲˗˔˧˔ˈ
3 ˠ˘ˠ˲˃˲˗ˤ˦ˆ
AP28 MDQS0_3 MDQ0_6 AV37 6 ˠ˘ˠ˲˃˲˗˔˧˔ˉ
3 ˠ˘ˠ˲˃˲˗ˤ˦ʽˆ AR28 MDQS0_3# MDQ0_7 AU36 7 ˠ˘ˠ˲˃˲˗˔˧˔ˊ
4 ˠ˘ˠ˲˃˲˗ˤ˦ˇ AK18 MDQS0_4 MDQ0_8 AL32 8 ˠ˘ˠ˲˃˲˗˔˧˔ˋ
4 ˠ˘ˠ˲˃˲˗ˤ˦ʽˇ AL18 MDQS0_4# MDQ0_9 AL31 9 ˠ˘ˠ˲˃˲˗˔˧˔ˌ
5 ˠ˘ˠ˲˃˲˗ˤ˦ˈ AU20 MDQS0_5 MDQ0_10 AR32 10 ˠ˘ˠ˲˃˲˗˔˧˔˄˃

5 ˠ˘ˠ˲˃˲˗ˤ˦ʽˈ AT20 MDQS0_5# MDQ0_11 AP30 11 ˠ˘ˠ˲˃˲˗˔˧˔˄˄
6 ˠ˘ˠ˲˃˲˗ˤ˦ˉ AL14 MDQS0_6 MDQ0_12 AL34 12 ˠ˘ˠ˲˃˲˗˔˧˔˄˅
6 ˠ˘ˠ˲˃˲˗ˤ˦ʽˉ AM14 MDQS0_6# MDQ0_13 AL33 13 ˠ˘ˠ˲˃˲˗˔˧˔˄ˆ
7 ˠ˘ˠ˲˃˲˗ˤ˦ˊ AT14 MDQS0_7 MDQ0_14 AN32 14 ˠ˘ˠ˲˃˲˗˔˧˔˄ˇ
7 ˠ˘ˠ˲˃˲˗ˤ˦ʽˊ AR15 MDQS0_7# MDQ0_15 AP32 15 ˠ˘ˠ˲˃˲˗˔˧˔˄ˈ
MEM_0_DQM[7..0] MDQ0_16 AT32 16 ˠ˘ˠ˲˃˲˗˔˧˔˄ˉ
20,21 MEM_0_DQM[7..0]
0 ˠ˘ˠ˲˃˲˗ˤˠ˃
AT36 MDQM0_0 MDQ0_17 AU32 17 ˠ˘ˠ˲˃˲˗˔˧˔˄ˊ
1 ˠ˘ˠ˲˃˲˗ˤˠ˄ AN35 MDQM0_1 MDQ0_18 AR30 18 ˠ˘ˠ˲˃˲˗˔˧˔˄ˋ
2 ˠ˘ˠ˲˃˲˗ˤˠ˅ AT31 MDQM0_2 MDQ0_19 AT29 19 ˠ˘ˠ˲˃˲˗˔˧˔˄ˌ
3 ˠ˘ˠ˲˃˲˗ˤˠˆ AJ29 MDQM0_3 MDQ0_20 AT33 20 ˠ˘ˠ˲˃˲˗˔˧˔˅˃
4 ˠ˘ˠ˲˃˲˗ˤˠˇ
AM18 MDQM0_4 MDQ0_21 AU33 21 ˠ˘ˠ˲˃˲˗˔˧˔˅˄
5 ˠ˘ˠ˲˃˲˗ˤˠˈ AU21 MDQM0_5 MDQ0_22 AR31 22 ˠ˘ˠ˲˃˲˗˔˧˔˅˅
6 ˠ˘ˠ˲˃˲˗ˤˠˉ AN14 MDQM0_6 MDQ0_23 AT30 23 ˠ˘ˠ˲˃˲˗˔˧˔˅ˆ
7 ˠ˘ˠ˲˃˲˗ˤˠˊ AT15 MDQM0_7 MDQ0_24 AL30 24 ˠ˘ˠ˲˃˲˗˔˧˔˅ˇ
MDQ0_25 AK29 25 ˠ˘ˠ˲˃˲˗˔˧˔˅ˈ
MDQ0_26 AL28 26 ˠ˘ˠ˲˃˲˗˔˧˔˅ˉ

MEM_0A_ADD[15..0] 27 ˠ˘ˠ˲˃˲˗˔˧˔˅ˊ
20,21,22 MEM_0A_ADD[15..0] MDQ0_27 AK28
0 ˠ˘ˠ˲˃˔˲˔˗˗˃ AU29 MA0A_0 MDQ0_28 AN30 28 ˠ˘ˠ˲˃˲˗˔˧˔˅ˋ
1 ˠ˘ˠ˲˃˔˲˔˗˗˄ AK21 MA0A_1 MDQ0_29 AM30 29 ˠ˘ˠ˲˃˲˗˔˧˔˅ˌ
2 ˠ˘ˠ˲˃˔˲˔˗˗˅ AK22 MA0A_2 MDQ0_30 AN28 30 ˠ˘ˠ˲˃˲˗˔˧˔ˆ˃
3 ˠ˘ˠ˲˃˔˲˔˗˗ˆ AL22 MA0A_3 MDQ0_31 AM28 31 ˠ˘ˠ˲˃˲˗˔˧˔ˆ˄
4 ˠ˘ˠ˲˃˔˲˔˗˗ˇ AM22 MA0A_4 MDQ0_32 AP18 32 ˠ˘ˠ˲˃˲˗˔˧˔ˆ˅
5 ˠ˘ˠ˲˃˔˲˔˗˗ˈ AP22 MA0A_5 MDQ0_33 AN18 33 ˠ˘ˠ˲˃˲˗˔˧˔ˆˆ
6 ˠ˘ˠ˲˃˔˲˔˗˗ˉ AN22 MA0A_6 MDQ0_34 AP16 34 ˠ˘ˠ˲˃˲˗˔˧˔ˆˇ
7 ˠ˘ˠ˲˃˔˲˔˗˗ˊ AL24 MA0A_7 MDQ0_35 AN16 35 ˠ˘ˠ˲˃˲˗˔˧˔ˆˈ
8 ˠ˘ˠ˲˃˔˲˔˗˗ˋ AK24 MA0A_8 MDQ0_36 AL20 36 ˠ˘ˠ˲˃˲˗˔˧˔ˆˉ
9 ˠ˘ˠ˲˃˔˲˔˗˗ˌ AM24 MA0A_9 MDQ0_37 AK20 37 ˠ˘ˠ˲˃˲˗˔˧˔ˆˊ
10 ˠ˘ˠ˲˃˔˲˔˗˗˄˃ AT28 MA0A_10 MDQ0_38 AK17 38 ˠ˘ˠ˲˃˲˗˔˧˔ˆˋ
11 ˠ˘ˠ˲˃˔˲˔˗˗˄˄ AN24 MA0A_11 MDQ0_39 AR16 39 ˠ˘ˠ˲˃˲˗˔˧˔ˆˌ
12 ˠ˘ˠ˲˃˔˲˔˗˗˄˅ AP24 MA0A_12 MDQ0_40 AR22 40 ˠ˘ˠ˲˃˲˗˔˧˔ˇ˃
13 ˠ˘ˠ˲˃˔˲˔˗˗˄ˆ AT24 MA0A_13 MDQ0_41 AT21 41 ˠ˘ˠ˲˃˲˗˔˧˔ˇ˄
14 ˠ˘ˠ˲˃˔˲˔˗˗˄ˇ AK25 MA0A_14 MDQ0_42 AT19 42 ˠ˘ˠ˲˃˲˗˔˧˔ˇ˅
15 ˠ˘ˠ˲˃˔˲˔˗˗˄ˈ
AK26 MA0A_15 MDQ0_43 AR19 43 ˠ˘ˠ˲˃˲˗˔˧˔ˇˆ
MEM_0A_BA[2..0] MDQ0_44 AR23 44 ˠ˘ˠ˲˃˲˗˔˧˔ˇˇ
20,21,22 MEM_0A_BA[2..0] 0 ˠ˘ˠ˲˃˔˲˕˔˃
AU27 MBA0A_0 MDQ0_45 AT22 45 ˠ˘ˠ˲˃˲˗˔˧˔ˇˈ
1 ˠ˘ˠ˲˃˔˲˕˔˄
AU28 MBA0A_1 MDQ0_46 AU19 46 ˠ˘ˠ˲˃˲˗˔˧˔ˇˉ
2 ˠ˘ˠ˲˃˔˲˕˔˅
AR24 MBA0A_2 MDQ0_47 AV19 47 ˠ˘ˠ˲˃˲˗˔˧˔ˇˊ
MDQ0_48 AK16 48 ˠ˘ˠ˲˃˲˗˔˧˔ˇˋ
MDQ0_49 AP14 49 ˠ˘ˠ˲˃˲˗˔˧˔ˇˌ

MEM_0A_CS*[1..0] MDQ0_50 AR12 50 ˠ˘ˠ˲˃˲˗˔˧˔ˈ˃
20,22 MEM_0A_CS*[1..0]
0 ˠ˘ˠ˲˃˔˲˖˦ʽ˃ AR27 MCS0A_0# MDQ0_51 AP12 51 ˠ˘ˠ˲˃˲˗˔˧˔ˈ˄
MEM_0A_CKE[1..0] 1 ˠ˘ˠ˲˃˔˲˖˦ʽ˄
AU24 MCS0A_1# MDQ0_52 AM16 52 ˠ˘ˠ˲˃˲˗˔˧˔ˈ˅
20,22 MEM_0A_CKE[1..0]
0 ˠ˘ˠ˲˃˔˲˖˞˘˃ AL26 MCKE0A_0 MDQ0_53 AL16 53 ˠ˘ˠ˲˃˲˗˔˧˔ˈˆ
MEM_0A_ODT[1..0] 1 ˠ˘ˠ˲˃˔˲˖˞˘˄ AN26 MCKE0A_1 MDQ0_54 AK14 54 ˠ˘ˠ˲˃˲˗˔˧˔ˈˇ
20,22 MEM_0A_ODT[1..0]
0 ˠ˘ˠ˲˃˔˲ˢ˗˧˃ AT25 MODT0A_0 MDQ0_55 AT12 55 ˠ˘ˠ˲˃˲˗˔˧˔ˈˈ
1 ˠ˘ˠ˲˃˔˲ˢ˗˧˄
AT23 MODT0A_1 MDQ0_56 AU15 56 ˠ˘ˠ˲˃˲˗˔˧˔ˈˉ
MDQ0_57 AV15 57 ˠ˘ˠ˲˃˲˗˔˧˔ˈˊ
MDQ0_58 AU13 58 ˠ˘ˠ˲˃˲˗˔˧˔ˈˋ
MDQ0_59 AU12 59 ˠ˘ˠ˲˃˲˗˔˧˔ˈˌ

MEM_0A_CLK0 AN20 MCLK0A_0 MDQ0_60 AT16 60 ˠ˘ˠ˲˃˲˗˔˧˔ˉ˃
20 MEM_0A_CLK0
MEM_0A_CLK0* AM20 MCLK0A_0# MDQ0_61 AU16 61 ˠ˘ˠ˲˃˲˗˔˧˔ˉ˄
20 MEM_0A_CLK0*
MEM_0A_CLK1 AT35 MCLK0A_1 MDQ0_62 AR14 62 ˠ˘ˠ˲˃˲˗˔˧˔ˉ˅
20 MEM_0A_CLK1
MEM_0A_CLK1* AR35 MCLK0A_1# MDQ0_63 AT13 63 ˠ˘ˠ˲˃˲˗˔˧˔ˉˆ
20 MEM_0A_CLK1*
MEM_0A_CLK2 AT18 MCLK0A_2
20 MEM_0A_CLK2
MEM_0A_CLK2* AR18 MCLK0A_2#
20 MEM_0A_CLK2*
MRAS0A# AV27 MEM_0A_RAS*
MEM_0B_CS*[1..0]
MEM_0A_RAS* 20,21,22
MCAS0A# AR26 MEM_0A_CAS*
21,22 MEM_0B_CS*[1..0] MEM_0A_CAS* 20,21,22
0 ˠ˘ˠ˲˃˕˲˖˦ʽ˃ AT26 MCS0B_0# MWE0A# AT27 MEM_0A_WE*
MEM_0B_CKE[1..0]
MEM_0A_WE* 20,21,22
1 ˠ˘ˠ˲˃˕˲˖˦ʽ˄ AU23 MCS0B_1#
21,22 MEM_0B_CKE[1..0]
0 ˠ˘ˠ˲˃˕˲˖˞˘˃ AM26 MCKE0B_0 VDDMEM
MEM_0B_ODT[1..0] 1 ˠ˘ˠ˲˃˕˲˖˞˘˄ AP26 MCKE0B_1
21,22 MEM_0B_ODT[1..0]
0 ˠ˘ˠ˲˃˕˲ˢ˗˧˃ AU25 MODT0B_0 MEM_COMP_1P8V AP37 MEM_COMP_1P8V 1 2
1 ˠ˘ˠ˲˃˕˲ˢ˗˧˄ AV23 MODT0B_1 R289 30.1-1%-LF
MEM_COMP_GND AP36 MEM_COMP_GND 1 2
R287 30.1-1%-LF V1P2_CORE
v0.2 BOM
MEM_0B_CLK0 AR20 MCLK0B_0 40.2 -> 30.1ohm
21 MEM_0B_CLK0
MEM_0B_CLK0* AP20 MCLK0B_0# V1P2_PLL_MEM_CPU M26
21 MEM_0B_CLK0*
MEM_0B_CLK1 AT34 MCLK0B_1 V3P3_PLL D26 V3.3V_PLL_IN BR25 0-LF
21 MEM_0B_CLK1 V3.3V_PLL_IN 11
1
MEM_0B_CLK1* AR34 MCLK0B_1#
21 MEM_0B_CLK1* 1/16
MEM_0B_CLK2 AT17 MCLK0B_2
21 MEM_0B_CLK2
MEM_0B_CLK2* AU17 MCLK0B_2# BC32
21 MEM_0B_CLK2*
0.1UF/16V/0402-LF
2
I992
Title
MCP73 MEM
A3 I-N73V 0.2
U16D
BGA1048 MCP73 PCI_REQ*[4..0]
PCI_AD[31..0] PCI_REQ*[4..0] 26,27
26 PCI_AD[31..0] SEC 4 OF 10
0 ˣ˖˜˲˔˗˃ AM3 PCI_AD0 PCI_REQ0# AE2 PCI_REQ*0 0
1 ˣ˖˜˲˔˗˄ AK5 PCI_AD1 PCI_REQ1# Y5 PCI_REQ*1 1
2 ˣ˖˜˲˔˗˅ AM2 PCI_AD2 PCI_REQ2#/GPIO_40/RS232_DSR# AD3 PCI_REQ*2 2
3 ˣ˖˜˲˔˗ˆ AH4 PCI_AD3 PCI_REQ3#/GPIO_38/RS232_CTS# Y6 PCI_REQ*3 3
4 ˣ˖˜˲˔˗ˇ AM1 PCI_AD4 PCI_REQ4#/GPIO_52/RS232_SIN# AD2 PCI_REQ*4 4
5 ˣ˖˜˲˔˗ˈ AH5 PCI_AD5
6 ˣ˖˜˲˔˗ˉ AL2 PCI_AD6 PCI_GNT*[4..0]
7 ˣ˖˜˲˔˗ˊ
PCI_GNT*[4..0] 26 1/16
AH6 PCI_AD7
8 ˣ˖˜˲˔˗ˋ AH7 PCI_AD8 PCI_GNT0# AD1 PCI_GNT*0 0
9 ˣ˖˜˲˔˗ˌ AL3 PCI_AD9 PCI_GNT1# Y7 PCI_GNT*1 1 PCI_CLKSLOT1 OUT
10 ˣ˖˜˲˔˗˄˃ AF5 PCI_AD10 PCI_GNT2#/GPIO_41/RS232_DTR# AC2 N C
11 ˣ˖˜˲˔˗˄˄ AF6 PCI_AD11 PCI_GNT3#/GPIO_39/RS232_RTS# Y8 N C PCI_CLKSLOT2 OUT
12 ˣ˖˜˲˔˗˄˅ AF7 PCI_AD12 PCI_GNT4#/GPIO_53/RS232_SOUT# AC1 N C
13 ˣ˖˜˲˔˗˄ˆ AL4 PCI_AD13 LPC_CLK_TPM OUT
14 ˣ˖˜˲˔˗˄ˇ AF8 PCI_AD14
15 ˣ˖˜˲˔˗˄ˈ AK3 PCI_AD15
16 ˣ˖˜˲˔˗˄ˉ AH2 PCI_AD16 PCI_CLK0 AC3 PCI_CLK0 1 2 PCI_CLKSLOT1
17 ˣ˖˜˲˔˗˄ˊ R427 22-LF
PCI_CLKSLOT1 26
AD8 PCI_AD17
18 ˣ˖˜˲˔˗˄ˋ AH1 PCI_AD18 PCI_CLK1 AC4 PCI_CLK1 1 2 PCI_CLKSLOT2
19 ˣ˖˜˲˔˗˄ˌ R421 22-LF
PCI_CLKSLOT2 26
AD9 PCI_AD19
20 ˣ˖˜˲˔˗˅˃ AG2 PCI_AD20 PCI_CLK2 AB3 PCI_CLK2 NC PCI_CLK_1394
21 ˣ˖˜˲˔˗˅˄
PCI_CLK_1394
AB5 PCI_AD21
22 ˣ˖˜˲˔˗˅˅ AG1 PCI_AD22 PCI_CLK3 AB4 TP_PCI_CLK3 NC
23 ˣ˖˜˲˔˗˅ˆ AB6 PCI_AD23 10pF 10pF 10pF
24 ˣ˖˜˲˔˗˅ˇ AG3 PCI_AD24 PCI_CLK4 AA3 PCI_CLK4 1 2
25 ˣ˖˜˲˔˗˅ˈ AB8 PCI_AD25 R419 22-LF EMPTY EMPTY EMPTY
26 ˣ˖˜˲˔˗˅ˉ AG4 PCI_AD26 PCI_CLKIN AA2 PCI_CLKIN
27 ˣ˖˜˲˔˗˅ˊ AB9 PCI_AD27
28 ˣ˖˜˲˔˗˅ˋ AF3 PCI_AD28 LAYOUT: INTERNAL TO MCP73 VCC3
29 ˣ˖˜˲˔˗˅ˌ AA9 PCI_AD29 trace matching as other PCI clocks BACKUP ONLY
30 ˣ˖˜˲˔˗ˆ˃ AF4 PCI_AD30 PCI_INTW# Y9 PCI_INTW*
PCI_INTW* 26,27
1
31 ˣ˖˜˲˔˗ˆ˄ Y4 PCI_AD31 PCI_INTX# W1 PCI_INTX*
PCI_INTX* 26,27
PCI_INTY# W3 PCI_INTY* C242 R406 R411
PCI_INTY* 26,27
PCI_INTZ# W4 PCI_INTZ* 10PF/NPO/50V/0402-LF x10K-0402-LF
PCI_C/BE*[3..0] PCI_INTZ* 26,27
EMPTY x10K-0402-LF
26 PCI_C/BE*[3..0]
2
0 ˣ˖˜˲˖˂˕˘ʽ˃
AL1 PCI_CBE0#
1 ˣ˖˜˲˖˂˕˘ʽ˄
AF9 PCI_CBE1# LPC_DRQ0* EMPTY EMPTY EMPTY
2 ˣ˖˜˲˖˂˕˘ʽ˅
AD7 PCI_CBE2# LPC_AD[3..0] LPC_DRQ1*
LPC_AD[3..0] 38,39
3 ˣ˖˜˲˖˂˕˘ʽˆ
AB7 PCI_CBE3# LPC_SERIRQ
PCI_FRAME* AH3 PCI_FRAME# MCP51 no this

26,27 PCI_FRAME* 0
26,27 PCI_IRDY*
PCI_IRDY* AD6 PCI_IRDY# LPC_AD0 A8 LPC_AD_R<0> 1 2 ˟ˣ˖˲˔˗˃
26,27 PCI_TRDY*
PCI_TRDY* AJ2 PCI_TRDY# LPC_AD1 B8 LPC_AD_R<1> 1R401 22-LF2 1
˟ˣ˖˲˔˗˄
26,27 PCI_STOP*
PCI_STOP* AJ3 PCI_STOP# LPC_AD2 A7 LPC_AD_R<2> 1R402 22-LF2 2
˟ˣ˖˲˔˗˅
VCC3
26,27 PCI_DEVSEL*
PCI_DEVSEL* AD5 PCI_DEVSEL# LPC_AD3 B7 LPC_AD_R<3> 1R403 22-LF2 3
˟ˣ˖˲˔˗ˆ
PCI_PAR AK4 PCI_PAR R405 22-LF

26 PCI_PAR
PCI_PERR* AD4 PCI_PERR#/GPIO_43/RS232_DCD#
26,27 PCI_PERR*
PCI_SERR* AE9 PCI_SERR# R456
26,27 PCI_SERR*
1394 PCI_PME* AE3 PCI_PME#/GPIO_30 LPC_DRQ0#/GPIO_50 B6 LPC_DRQ0* x10K-0402-LF
26,27 PCI_PME* LPC_DRQ0* 38
LPC_DRQ1/GPIO_19/FANRPM1 C6 LPC_DRQ1* EMPTY
PCI Slot 1 LPC_FRAME# C8 LPC_FRAME_R* 1 R399 2 LPC_FRAME*
LPC_FRAME* 38
PCI Slot 2 R0603 5%
LPC_SERIRQ 22-LF
IDE LPC_SERIRQ C7 LPC_SERIRQ 38
PCI_RST_1394* PCI_RESET0* N C Y3 PCI_RESET0#
PCI_RST_1394*
R494
PCI_RST_SLOT1* 1 2 PCI_RESET1* Y2 PCI_RESET1# LPC_RESET# D8 LPC_RESET* LPC_RST_FLASH* R451 STRAP
26 PCI_RST_SLOT1* LPC_RST_FLASH*
R0603 5%
R493 R390
10K-0402-LF
PCI_RST_SLOT2* 33-LF
1 2 PCI_RESET2* Y1 PCI_RESET2# 1 2 LPC_RST_SIO* HDA_SDOUT
26 PCI_RST_SLOT2* LPC_RST_SIO* 38 LPC_FRAME
R0603 5% R0603 5%
R409
PCI_RST_IDE* 33-LF 33-LF
36 PCI_RST_IDE* 1 2 PCI_RESET3* W2 PCI_RESET3# LPC_CLK0 D5 LPC_Flash DEFAULT*
R0603 5%
LPC_CLK1 C5 LPC_SIO
33-LF
1/16 I463 00 = LPC BIOS*
01 = PCI BIOS
10 = SPI BIOS
CRB 11 = RESERVED
R412
OUT
LPC_RST_TPM* LPC_CLK0 1 2 LPC_CLK_SIO
LPC_CLK_SIO 38
R0603 5%
PCI_RST_SLOTS_1* 33-LF
OUT
LPC_CLK1 LPC_CLK_FLASH
LPC_CLK_FLASH
OUT
PCI_RST_SLOTS_2*
LPC_SIO
PCI_RST_IDE* MCP51: 22ohm
OUT
1
LPC_Flash
1
C243 C244
EMPTY EMPTY
2
x10PF/NPO/50V/0402-LF
Title
MCP73 PCI/LPC
A3 I-N73V 0.2
VCC3 All IDE traces should be referenced to GND.
Implement stitching 0.1 mF capacitors around

the area that the signals transfer routing layers.
C454 C455 C456 C457 C458 C459 C460
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF
0.1UF/16V/0402-LF v0 .2
PLACE CAPS AT CONN

U16E
BGA1048 MCP73
1 SEC 5 OF 10 IDE_DATA_P[15..0]
1
SATA_A0_TX_P_C
C395 IDE_DATA_P[15..0] 36
2 2 1 C394
SATA_A0_TX_P AR4 SATA_A0_TX_P IDE_DATA_P0/WUSB_DATA0 AV7 0 ˜˗˘˲˗˔˧˔˲ˣ˃
SATA1 3 SATA_A0_TX_N_C C0402

X7R 2 1 SATA_A0_TX_N AR5 SATA_A0_TX_N IDE_DATA_P1/WUSB_DATA1 AR7 1 ˜˗˘˲˗˔˧˔˲ˣ˄
0.01UF/16V/0402-LF
<VOLTAGE> C0402
SATA-BLACK-Box-LF 4 C393 10% X7R
0.01UF/16V/0402-LF IDE_DATA_P2/WUSB_DATA2 AR6 2 ˜˗˘˲˗˔˧˔˲ˣ˅
5 SATA_A0_RX_N_C 2 1
<VOLTAGE>
10% SATA_A0_RX_N AP6 SATA_A0_RX_N IDE_DATA_P3/WUSB_DATA3 AU5 3 ˜˗˘˲˗˔˧˔˲ˣˆ
C392
6 SATA_A0_RX_P_C C0402
X7R 2 1 SATA_A0_RX_P AN6 SATA_A0_RX_P IDE_DATA_P4/WUSB_DATA4 AU4 4 ˜˗˘˲˗˔˧˔˲ˣˇ
0.01UF/16V/0402-LF
<VOLTAGE> C0402
7 10% X7R IDE_DATA_P5/WUSB_DATA5 AT3 5 ˜˗˘˲˗˔˧˔˲ˣˈ
0.01UF/16V/0402-LF
<VOLTAGE>
10% IDE_DATA_P6/WUSB_DATA6 AU3 6 ˜˗˘˲˗˔˧˔˲ˣˉ
IDE_DATA_P7/WUSB_DATA7 AU2 7 ˜˗˘˲˗˔˧˔˲ˣˊ
IDE_DATA_P8 AV2 8 ˜˗˘˲˗˔˧˔˲ˣˋ
1 IDE_DATA_P9 AV3 9 ˜˗˘˲˗˔˧˔˲ˣˌ

1 C418
2 SATA_A1_TX_P_C 2 1 SATA_A1_TX_P AR8 SATA_A1_TX_P IDE_DATA_P10 AV4 10 ˜˗˘˲˗˔˧˔˲ˣ˄˃
C417
SATA3 3 SATA_A1_TX_N_C C0402
X7R 2 1 SATA_A1_TX_N AP8 SATA_A1_TX_N IDE_DATA_P11 AT4 11 ˜˗˘˲˗˔˧˔˲ˣ˄˄
0.01UF/16V/0402-LF
<VOLTAGE> C0402
0.01UF/16V/0402-LF IDE_DATA_P12 AT5 12 ˜˗˘˲˗˔˧˔˲ˣ˄˅
5 SATA_A1_RX_N_C 2 1
<VOLTAGE>
10% SATA_A1_RX_N AN8 SATA_A1_RX_N IDE_DATA_P13 AT6 13 ˜˗˘˲˗˔˧˔˲ˣ˄ˆ
C415
SATA2 -> SATA3 6 SATA_A1_RX_P_C C0402
X7R 2 1 SATA_A1_RX_P AM8 SATA_A1_RX_P IDE_DATA_P14 AT7 14 ˜˗˘˲˗˔˧˔˲ˣ˄ˇ
0.01UF/16V/0402-LF
<VOLTAGE> C0402
7 10% X7R IDE_DATA_P15 AU7 15 ˜˗˘˲˗˔˧˔˲ˣ˄ˈ
0.01UF/16V/0402-LF
<VOLTAGE>
10%
IDE_ADDR_P[2..0]
0
IDE_ADDR_P[2..0] 36
1 1 C399 IDE_ADDR_P0/WUSB_STOPC AR11 ˜˗˘˲˔˗˗˥˲ˣ˃
2 SATA_B0_TX_P_C 2 1 SATA_B0_TX_P AP10 SATA_B0_TX_P IDE_ADDR_P1/WUSB_RX_EN AT10 1 ˜˗˘˲˔˗˗˥˲ˣ˄

C398
SATA2 3 SATA_B0_TX_N_C C0402
X7R 2 1 SATA_B0_TX_N AN10 SATA_B0_TX_N IDE_ADDR_P2/WUSB_TX_EN AT11 2 ˜˗˘˲˔˗˗˥˲ˣ˅
0.01UF/16V/0402-LF
<VOLTAGE> C0402
0.01UF/16V/0402-LF
5 SATA_B0_RX_N_C 2 1
<VOLTAGE>
10% SATA_B0_RX_N AM10 SATA_B0_RX_N
C396
SATA3 -> SATA2 6 SATA_B0_RX_P_C C0402
X7R 2 1 SATA_B0_RX_P AL10 SATA_B0_RX_P
0.01UF/16V/0402-LF
<VOLTAGE> C0402
7 10% X7R
0.01UF/16V/0402-LF IDE_CS1_P#/WUSB_PHY_RESET# AV11 IDE_CS1_P*
<VOLTAGE>
IDE_CS3_P* IDE_CS1_P* 36
10% IDE_CS3_P# AU11 IDE_CS3_P* 36
IDE_DACK_P# AT9 IDE_DACK_P*
IDE_IOW_P* IDE_DACK_P* 36
IDE_IOW_P#/WUSB_CCA_STATUS AU8 IDE_IOW_P* 36
1 C422 IDE_IOR_P#/WUSB_SERIAL_DATA AT8 IDE_IOR_R_P* 1 2 IDE_IOR_P*
1
SATA_B1_TX_P_C SATA_B1_TX_P IDE_INTR_P R394 0-LF IDE_IOR_P* 36
2 2 1 C421 AN12 SATA_B1_TX_P IDE_INTR_P/WUSB_PHY_ACTIVE AR10 IDE_INTR_P 36
SATA4 3 SATA_B1_TX_N_C C0402
X7R 2 1 SATA_B1_TX_N AM12 SATA_B1_TX_N IDE_DREQ_P/WUSB_PCLK AV8 IDE_DREQ_P
0.01UF/16V/0402-LF
<VOLTAGE> C0402 IDE_DREQ_P 36
SATA-BLACK-Box-LF 4 10% X7R IDE_RDY_P/WUSB_DATA_EN AU9 IDE_RDY_P
SATA_B1_RX_N_C
C420 0.01UF/16V/0402-LF
<VOLTAGE> IDE_RDY_P 36
5 2 1 10% SATA_B1_RX_N AL12 SATA_B1_RX_N CABLE_DET_P/GPIO_63 AK13 CABLE_DET_P
SATA_B1_RX_P_C C0402
C419 CABLE_DET_P 36
6 X7R
0.01UF/16V/0402-LF 2 1 SATA_B1_RX_P AK12 SATA_B1_RX_P
<VOLTAGE> C0402
7 10% X7R
0.01UF/16V/0402-LF
<VOLTAGE>
10%
VCC3
28 SATA_HDLED* SATA_HDLED* D27 SATA_LED#/GPIO_57
1 2 SATA_TERMP AT1 SATA_TERMP IDE_COMP_3P3 AT2 IDE_COMP_3P3V
2
R407
1
V1P2_CORE BFB2 2.49K-1%-LF IDE_COMP_GND AU1 IDE_COMP_GND
30OHM/3A/40mOHM-LF R410 C448
V1.2V_SATA_PLL AF12 V1P2_SATA_PLL 121-1%-LF 0.1UF/16V/0402-LF
2
1
BC14 BC15 v0 .2
2 1
01.uF MCP73 DG_v0.3 update
C0402
X7R
C0402
X7R AG12 V1P2_PLL_SREF_SP =>Add 0.1uF
v0 .2 16V
10%
16V
10%
2
4.7uF -> 0.1uF 1/16 R408

0.1UF/16V/0402-LF 0.1UF/16V/0402-LF 121-1%-LF
AG9 V3P3_PLL_SREF_SP
1
I245
VCC3 BFB1
30OHM/3A/40mOHM-LF
V3.3V_PLL_SREF_SP
1
BC7 BC9
1/16
C0402
X7R
16V
10%
2
0.1UF/16V/0402-LF
10UF/Y5V/10V/0805-LF
Title
MCP73 SATA/IDE
A3 I-N73V 0.2
VCC3
STRAP
EMPTY
HDA_SDOUT
LPC_FRAME BR7
DEFAULT* 10K-0402-LF
00 = LPC BIOS*
01 = PCI BIOS HDA_SDOUT 1 2 HDASDOUT
10 = SPI BIOS 35 HDA_SDOUT
BR8 22-LF
11 = RESERVED BR3 U16F
2 1 BGA1048
x10K-0402-LF BC1 MCP73
10PF/NPO/50V/0402-LF SEC 6 OF 10
E11 HDA_SDATA_OUT/GPIO_45 USB0_P C25 USB_0
USB_0 37
HDA_SDIN_0 H11 HDA_SDATA_IN0/GPIO_22 USB0_N D25 USB_0*
35 HDA_SDIN_0 R342 R345 USB_0* 37
OUT
CPU_GTLREF1_SEL BR1 0-0402-LF G11 HDA_SDATA_IN1/GPIO_23/MGPIO_0 1 21 2
28,38,39 ROM_WP_EN
R0603 5% R0603 5%
HDASYNC 15K-LF 15K-LF

1 2 D11 HDA_SYNC/GPIO_44
BR11 22-LF USB1_P C24 USB_1
USB_1 37
1 2 HDABCLK USB1_N D24 USB_1*
R348 R355 USB_1* 37
delect MII or RGMII: BR13 22-LF 1 21 2
1 2 HDARST* F11 HDA_BITCLK R0603 5% R0603 5%
HDA_RESET# BR16 22-LF 15K-LF 15K-LF
-0 = MII USB2_P J25 USB_2

USB_2 37
-1 = RGMII BC5 USB2_N J26 USB_2*
R356 R359 USB_2* 37
1
BC2 BC8 J11 HDA_RESET# 1 21 2
SPEAKER F9 SPKR R0603 5% R0603 5%
28,35 SPEAKER 15K-LF 15K-LF
3VDUAL VCC3 10PF/NPO/50V/0402-LF
10PF/NPO/50V/0402-LF USB3_P G25 USB_3
USB_3 37
2
10PF/NPO/50V/0402-LF USB3_N H25 USB_3*
R364 R369 USB_3* 37
1 21 2
R0603 5% R0603 5%
BR4 BR10 0 R347 0-0402-LF 15K-LF 15K-LF

˥˚ˠ˜˜˃˲˧˫˗˃
RGMII0_TXD0_R
C21 MII0_TXD0
x10K-0402-LF 10K-0402-LF RGMII0_TXD[3..0] 1 ˥˚ˠ˜˜˃˲˧˫˗˄
R346 0-0402-LF RGMII0_TXD1_R
D21 MII0_TXD1 USB4_P E25 USB_4
OUT USB_4 37
2 ˥˚ˠ˜˜˃˲˧˫˗˅
B22 MII0_TXD2 USB4_N F25 USB_4*
R599 R598 USB_4* 37
3 ˥˚ˠ˜˜˃˲˧˫˗ˆ
C23 MII0_TXD3 1 21 2
HD A_SYNC R0603 5% R0603 5%
35 HDA_SYNC
OUT
RGMII0_TXC R344 0-0402-LF RGMII0_TXC_R C22 MII0_TXCLK
15K-LF 15K-LF
HDA_BITCLK USB5_P H23 USB_5

35 HDA_BITCLK USB_5 37
OUT
RGMII0_TXCTL R338 0-0402-LF RGMII0_TXCTL_R B23 MII0_TXEN USB5_N J23 USB_5*
R597 R596 USB_5* 37
HDA_RST* 1 21 2
35 HDA_RST*
R0603 5% R0603 5%
SIO clock select: RGMII0_RXD[3..0] 15K-LF 15K-LF

IN
0 ˥˚ˠ˜˜˃˲˥˫˗˃
A19 MII0_RXD0 USB6_P G23 USB_6
USB_6 37
BR31 HDA_SYNC 1 ˥˚ˠ˜˜˃˲˥˫˗˄
B20 MII0_RXD1 USB6_N F23 USB_6*
R601 R600 USB_6* 37
10K-0402-LF -0 = 14.31818 MHz RGMII0_RXC 2 ˥˚ˠ˜˜˃˲˥˫˗˅
C20 MII0_RXD2 1 21 2
34 RGMII0_RXC
-1 = 24 MHz RGMII0_RXCTL 3 ˥˚ˠ˜˜˃˲˥˫˗ˆ
D20 MII0_RXD3 R0603 5% R0603 5%
34 RGMII0_RXCTL 15K-LF 15K-LF
BR727 x0-0402-LF A20 MII0_RXCLK USB7_P E23 USB_7

USB_7 37
BR738 x0-0402-LF USB7_N D23 USB_7*
R603 R602 USB_7* 37
BR737 x0-0402-LF D19 MII0_RXDV 1 21 2
34 MII_RX_ER MII_RX_ER E19 MII0_RXER/GPIO_36 R0603 5% R0603 5%
3VDUAL MII_COL 15K-LF 15K-LF

34 MII_COL
MII_CRS
G19 MII0_COL/MI2C_DATA
USB_8
Unused Interface
34 MII_CRS F19 MII0_CRS/MI2C_CLK USB8_P J22 USB_8
1
USB8_N J21 USB_8*

BR605 BR604 USB_8*
1 21 2
R341 R0603 5% R0603 5%
RGMII0_INTR* 10K-0402-LF RGMII0_MDC 15K-LF 15K-LF

IN OUT
RGMII0_MDIO
B19 MII0_MDC
USB_9
Unused Interface
OUT C19 MII0_MDIO USB9_P H21 USB_9
RGMII0_INTR* E21 MII0_INTR/GPIO_35 USB9_N G21 USB_9*
34 RGMII0_INTR* USB_9*
2
BR607 BR606
OUT
RGMII0_PWRDWN* 1 2 RGMII0_PWRDWNR* H19 MII0_PWRDWN/GPIO_37 1 21 2
R352 22-LF R0603 5% R0603 5%
RGMII_RESET* 15K-LF 15K-LF

OUT F21 MII0_RESET#
USB_OC0#/GPIO_25 B14 USB_OC01* 37
3VDUAL MII_VREF A23 MII_VREF USB_OC1#/GPIO_26 C14 Unused Interface
USB_OC23* 37 3VDUAL
USB_OC2#/GPIO_27 D13 USB_OC45* 37
2
3VDUAL USB_OC3#/GPIO_28/MGPIO_1 C13 USB_OC67* 37

R334 USB_OC4#/GPIO_29/MGPIO_3 D12 USB_OC89* R647
1.47K-1%-LF 1 2 MII_COMP_3P3V A24 MII_COMP_VDD 10K-0402-LF
1% USB_OC89*
R0603 R329 49.9-1%-LF
1 2 MII_COMP_GND B24 MII_COMP_GND
R332 49.9-1%-LF USB_RBIAS_GND B26 USB_RBIAS_GND 1 2
21
R327 909-1%-LF
1
R335 1/16
1.47K-1%-LF C203 J19 V3P3_DUAL_PLL_MAC
1%
R0603 0.1UF/16V/0402-LF 1.1K->909ohm
3VDUAL I602
2
1
BFB7
30OHM/3A/40mOHM-LF
V3.3V_PLL_MAC_DUAL
1
BC28
C204 4.7uF
10UF/Y5V/10V/0805-LF
0.1UF/16V/0402-LF
2
Title
MCP73 HDA/MII/USB
A3 I-N73V 0.2
VCC3 3VDUAL REMOVE FOR PRODUCTION
JTAG CONNECTOR 3VDUAL
LAYOUT: PLACE HEADERS CLOSE TOGETHER
CRB 2.7k->2.2k
2
BR19 BR17 BR21 BR23 BR5
BR2 BR30 x10K-0402-LF
x10K-0402-LF x10K-0402-LF
2.2K-LF 2.2K-LF 2.2K-LF 2.2K-LF U16G EMPTY EMPTY
BGA1048 MCP73 JTAG_TRST_MCP*
1
SEC 7 OF 10 JTAG_TDO_MCP
SMB_MEM_DA 1 2 SMB_MEM_DA_R F15 SMB_DATA0 JTAG_TDI F13 JTAG_TDI_MCP JTAG_TDI_MCP
20,21 SMB_MEM_DA
20,21 SMB_MEM_CL
SMB_MEM_CL 1BR20 0-0402-LF
2 SMB_MEM_CL_R E15 SMB_CLK0 JTAG_TDO J13 N C JTAG_TDO_MCP JTAG_TMS_MCP
BR18 0-0402-LF JTAG_TCK_MCP
SMB_SDA 1 2 SMB_SDA_R G15 SMB_DATA1/MSMB_DATA JTAG_TCK G13 JTAG_TCK_MCP
24,25,26 SMB_SDA
24,25,26 SMB_SCL
SMB_SCL 1BR22 0-0402-LF
2 SMB_SCL_R H15 SMB_CLK1/MSMB_CLK
BR24 0-0402-LF JTAG_TMS J14 JTAG_TMS_MCP BR9 BR6
x10K-0402-LF 10K-0402-LF
JTAG_TRST# H13 JTAG_TRST_MCP* EMPTY
3VDUAL
MCP73 A20GATE
38 A20GATE D7 A20GATE/GPIO_55
GPIO34 38 EXT_SMI*
EXT_SMI* C15 EXT_SMI#/GPIO_32
R367
x10K-0402-LF 38 PWRBTN* PWRBTN* E17 PWRBTN# SPI_DI/GPIO_8 B10 SPI_DI
SPI_DI 39
FP_RESET* F17 RSTBTN# SPI_DO/GPIO_9 C10 SPI_DO
28 FP_RESET* SPI_DO 39
SUS_CLK_R IO_PME* D15 SIO_PME#/GPIO_31/SPI_CS2 3VDUAL
38 IO_PME*
SIO_KBRST* E9 KBRDRSTIN#/GPIO_56 SPI_CS0/GPIO_10 D9 SPI_CS*
38 SIO_KBRST* SPI_CS* 39
R365
10K-0402-LF SPI_CLK/GPIO_11 C9 SPI_CLK
SPI_CLK 39
BUF0_25MHZ 1 2 BUF0_25MHZ_R B18 BUF0_25MHZ R575 R572
34 BUF0_25MHZ R362 22-LF
BUF_SIO_CLK 1 2 BUF_SIO_CLK_R D4 BUF_SIO_CLK x10K-0402-LF x10K-0402-LF
38 BUF_SIO_CLK R416 22-LF SUS_CLK_R C18 SUS_CLK/GPIO_34 EMPTY EMPTY
OUT
SUS_CLK_TPM 1/16 MCP73 SPI CLK STRAP
1
C245 C213 GPIO_2/NMI/PS2_KB_CLK C12 N C

GPIO_3/SMI#/PS2_KB_DATA A12 N C SPI_DO | SPI_CLK
32 SLP_S5*
SLP_S5* J17 SLP_S5# GPIO_4/SCI/INTR/PS2_MS_CLK B12 N C *0 0 = 31MHz
EMPTY EMPTY SLP_S3* J18 SLP_S3# GPIO_5/INIT#/PS2_MS_DATA A11 CPU_VTT_SEL_V1P1 R576 R573 0 1 = 42MHz
31,32,38 SLP_S3*
2
PWRGD_SB D16 PWRGD_SB GPIO_6/FERR#/IGPU_GPIO_6 B11 10K-0402-LF 10K-0402-LF 1 0 = 25MHz

28,38 PWRGD_SB
IN
PS_PWRGD MCP_PWRGD J15 PS_PWRGD GPIO_7/NFERR#/IGPU_GPIO_7 C11 ACZ_DET
ACZ_DET 35 1 1 = 1MHz
11,31 MCP_PWRGD
IN
CPU_PWRGD
31 CPU_VLD_MCP
CPU_VLD_MCP H17 CPU_VLD ( *DEFAULT )
x10PF/NPO/50V/0402-LF CPUVDD_EN G17 CPUVDD_EN from FP-AUDIO
33 CPUVDD_EN
XTALIN A15 XTALIN FANRPM0/GPIO_60 K10 N C VCC3

XTALOUT B15 XTALOUT MCP73
Y2 FANCTL0/GPIO_61 J10 N C
25.000MHZ FANCTL1/GPIO_62 G9 MCP_GPIO62 GPIO62
1 2
XTALIN_RTC C17 XTALIN_RTC R417
1
Y1 XTALOUT_RTC D17 XTALOUT_RTC x10K-0402-LF

CPU_VTT_SEL_V1P1
C227 C230 32.768KHZ
1 2 CPU_VTT State:
18PF/NPO/50V/0402-LF 4 3 TEST_MODE_EN H12 TESTMODE R418 - 0, VTT= 1.2V
2
18PF/NPO/50V/0402-LF RTC_RST* C16 RTC_RST# PKG_TEST J12 10K-0402-LF - 1, VTT= 1.1V

v0 .2
INTRUDER* B16 INTRUDER# BR14
2R371 x1M-LF
1 1K-LF
1
C217 C216 VBATCCMOS VBATCCMOS A16 V3P3_VBAT
18PF/NPO/50V/0402-LF I541
2
18PF/NPO/50V/0402-LF BC20
0.1UF/16V/0402-LF
CRB = 15pF 0402_R
X5R
16V
10%
2
VCC3
VBATCCMOS
Unused Interface
R648
2
10K-0402-LF
R379 R380 HDMI_CEC

49.9K-1%-LF 49.9K-1%-LF
HDMI_CEC
1
28 RTC_RST*
INTRUDER*
Title
MCP73 SPI/PS2/JTAG
A3 I-N73V 0.2
VDDMEM
VDDMEM
U16H
BGA1048 MCP73 V1P2_DUAL
SEC 9 OF 10
1
1
BC45 BC39 BC34 BC30 BC27 BC37 C67 C129 C160 C149 AF17 V1P8_MEM_VDDP V1P2_VDD_AUXC M16
AF18 V1P8_MEM_VDDP V1P2_VDD_AUXC M18
1
C0402
X7R
C0402
X7R
C0402
X7R
C0402
X7R
C0402
X7R
C0402
X7R
C0402
X7R
C0402
X7R
C0402
X7R
C0402
X7R AF19 V1P8_MEM_VDDP V1P2_VDD_AUXC M20 BC41 BC35
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% AF20 V1P8_MEM_VDDP V1P2_VDD_AUXC M22
2
2
AF21 V1P8_MEM_VDDP V1P2_VDD_AUXC N16 C0402
X7R
C0402
X7R
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF AF22 V1P8_MEM_VDDP V1P2_VDD_AUXC N18
16V
10%
16V
10%
2
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF AF23 V1P8_MEM_VDDP V1P2_VDD_AUXC N20
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF AF24 V1P8_MEM_VDDP V1P2_VDD_AUXC N22 0.1UF/16V/0402-LF
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF AF25 V1P8_MEM_VDDP 0.1UF/16V/0402-LF
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF AF26 V1P8_MEM_VDDP
AF27 V1P8_MEM_VDDP
AG17 V1P8_MEM_VDDP 3VDUAL
VDDMEM VDDMEM AG19 V1P8_MEM_VDDP
1/16 AG21 V1P8_MEM_VDDP V3P3_DUAL F16
AG23 V1P8_MEM_VDDP V3P3_DUAL H16 1/16
1
AG25 V1P8_MEM_VDDP V3P3_DUAL J16
1
1
C443 C444 BCT12 CT42 AG27 V1P8_MEM_VDDP C377
AK23 V1P8_MEM_VDDP 3VDUAL C0402
X7R
0.1UF/16V/0402-LF
16V
C0402 C0402 C0805 C0805
AK27 V1P8_MEM_VDDP 10%
2
X7R X7R X5R X5R
16V 16V 10V 10V
10% 10% 10% 10% AL23 V1P8_MEM_VDDP V3P3_DUAL_USB F24
2
2
AL25 V1P8_MEM_VDDP V3P3_DUAL_USB H24 1/16
1
10UF/Y5V/10V/0805-LF AL27 V1P8_MEM_VDDP V3P3_DUAL_USB J24
0.1UF/16V/0402-LF 10UF/Y5V/10V/0805-LF AN23 V1P8_MEM_VDDP BC38
0.1UF/16V/0402-LF AN25 V1P8_MEM_VDDP 3VDUAL C0402
X7R
0.1UF/16V/0402-LF
AN27 V1P8_MEM_VDDP 1/16 16V
10%
2
AR25 V1P8_MEM_VDDP V3P3_DUAL_RMGT F20
AV24 V1P8_MEM_VDDP V3P3_DUAL_RMGT H20
1
AV28 V1P8_MEM_VDDP V3P3_DUAL_RMGT J20 BC33 CT83
I435 C0402
X7R
16V
10%
2
0.1UF/16V/0402-LF
10UF/Y5V/10V/0805-LF
Title
MCP73 MEM POWER

A3 I-N73V 0.2
V1P2_FSBVTT
V1P2_CORE U16I
BGA1048 MCP73
SEC 8 OF 10
AA12 V1P2_VDD_CORE V1P2_CPU_VTT A31 V1P2_FSBVTT
AA13 V1P2_VDD_CORE V1P2_CPU_VTT A32 1/16
AA19 V1P2_VDD_CORE V1P2_CPU_VTT AB27
AA21 V1P2_VDD_CORE V1P2_CPU_VTT AD27
AA22 V1P2_VDD_CORE V1P2_CPU_VTT B31
1
AA23 V1P2_VDD_CORE V1P2_CPU_VTT B32 BC49 BC48 BC50 BC53 BC52 C194 C112 CT61
AA24 V1P2_VDD_CORE V1P2_CPU_VTT C31
V1P2_CORE V1P2_CORE AA26 V1P2_VDD_CORE V1P2_CPU_VTT C32 C0402
X7R
C0402
X7R
C0402
X7R
C0402
X7R
C0402
X7R
C0402
X7R
C0402
X7R
C0805
X5R
16V 16V 16V 16V 16V 16V 16V 10V
AB12 V1P2_VDD_CORE V1P2_CPU_VTT C33 10% 10% 10% 10% 10% 10% 10% 10%
2
AB13 V1P2_VDD_CORE V1P2_CPU_VTT D31
AB15 V1P2_VDD_CORE V1P2_CPU_VTT D32 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF 10UF/Y5V/10V/0805-LF
1
1
CT74 BCT1 BCT2 AB16 V1P2_VDD_CORE V1P2_CPU_VTT D33 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF
4.7uF -> 10uF AB17 V1P2_VDD_CORE V1P2_CPU_VTT E31 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF
C0805
X5R
C0805
X5R
C0805
X5R AB19 V1P2_VDD_CORE V1P2_CPU_VTT F29 0.1UF/16V/0402-LF
10V 10V 10V
10% 10% 10% AB21 V1P2_VDD_CORE V1P2_CPU_VTT F30
2
2
10UF/Y5V/10V/0805-LF AB26 V1P2_VDD_CORE V1P2_CPU_VTT F31
10UF/Y5V/10V/0805-LF AC12 V1P2_VDD_CORE V1P2_CPU_VTT G29
10UF/Y5V/10V/0805-LF AC13 V1P2_VDD_CORE V1P2_CPU_VTT H27
AC17 V1P2_VDD_CORE V1P2_CPU_VTT H28
AC19 V1P2_VDD_CORE V1P2_CPU_VTT H29
AC21 V1P2_VDD_CORE V1P2_CPU_VTT J27 V1P2_FSBVTT
AC23 V1P2_VDD_CORE V1P2_CPU_VTT J28 NEAR CPU SIDE
V1P2_CORE AC24 V1P2_VDD_CORE V1P2_CPU_VTT J29
AC26 V1P2_VDD_CORE V1P2_CPU_VTT K29
AD12 V1P2_VDD_CORE V1P2_CPU_VTT M27
1
AD13 V1P2_VDD_CORE V1P2_CPU_VTT N27 C114 C116 C119 CT44
1
BC46 BC44 BC43 BC40 BC47 AD17 V1P2_VDD_CORE V1P2_CPU_VTT P27 1/16
AD19 V1P2_VDD_CORE V1P2_CPU_VTT T27 C0402
X7R
C0402
X7R
C0402
X7R
C0805
X5R
16V 16V 16V 10V
C0402 C0402 C0402 C0402 C0402
AD21 V1P2_VDD_CORE V1P2_CPU_VTT V27 10% 10% 10% 10%
2
X7R X7R X7R X7R X7R
16V 16V 16V 16V 16V
10% 10% 10% 10% 10% AD23 V1P2_VDD_CORE V1P2_CPU_VTT Y27
2
AD26 V1P2_VDD_CORE 0.1UF/16V/0402-LF 10UF/Y5V/10V/0805-LF

0.1UF/16V/0402-LF 0.1UF/16V/0402-LF AE12 V1P2_VDD_CORE 0.1UF/16V/0402-LF
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF AE26 V1P2_VDD_CORE 0.1UF/16V/0402-LF
0.1UF/16V/0402-LF AH8 V1P2_VDD_CORE V1P2_CORE
AH9 V1P2_VDD_CORE
AJ10 V1P2_VDD_CORE V1P2_PEX_DVDD N13
V1P2_CORE AJ6 V1P2_VDD_CORE V1P2_PEX_DVDD R15
AJ8 V1P2_VDD_CORE V1P2_PEX_DVDD R16
AJ9 V1P2_VDD_CORE V1P2_PEX_DVDD T15
AK10 V1P2_VDD_CORE V1P2_PEX_DVDD T16
1
BC29 AK6 V1P2_VDD_CORE V1P2_CORE

AK7 V1P2_VDD_CORE
C0402
X7R
0.1uF 0.1uF 0.1uF 0.1uF AK8 V1P2_VDD_CORE
16V
10% AK9 V1P2_VDD_CORE V1P2_PEX_AVDD N12 BFB6
2
AL6 V1P2_VDD_CORE V1P2_PEX_AVDD P12 30OHM/3A/40mOHM-LF
1
0.1UF/16V/0402-LF AL8 V1P2_VDD_CORE V1P2_PEX_AVDD P13 BC21 BC18 BC19 BC12 BCT5
AM4 V1P2_VDD_CORE V1P2_PEX_AVDD T12 0.1uF
AM5 V1P2_VDD_CORE V1P2_PEX_AVDD T13 C0805
X5R
10V
AM6 V1P2_VDD_CORE V1P2_PEX_AVDD U12 10%
2
AN2 V1P2_VDD_CORE V1P2_PEX_AVDD U13
0.1UF/16V/0402-LF 10UF/Y5V/10V/0805-LF
AN3 V1P2_VDD_CORE V1P2_PEX_AVDD W12
V1P2_CORE V1P2_CORE 0.1UF/16V/0402-LF
AN4 V1P2_VDD_CORE V1P2_PEX_AVDD W13
V1P2_CORE 0.1UF/16V/0402-LF
AP3 V1P2_VDD_CORE
0.1UF/16V/0402-LF
AP4 V1P2_VDD_CORE
AR1 V1P2_VDD_CORE
1/16
1
BC31 BC36 BC25 AR2 V1P2_VDD_CORE

AR3 V1P2_VDD_CORE
1
0.1uF 0.1uF M23 V1P2_VDD_CORE V1P2_SATA_DVDD AD15
M24 V1P2_VDD_CORE V1P2_SATA_DVDD AF15 BC26
2
M25 V1P2_VDD_CORE V1P2_SATA_DVDD AF16 0.1UF/16V/0402-LF

N23 V1P2_VDD_CORE V1P2_SATA_DVDD AG16
2
0.1UF/16V/0402-LF N24 V1P2_VDD_CORE
0.1UF/16V/0402-LF N25 V1P2_VDD_CORE V1P2_CORE
0.1UF/16V/0402-LF N26 V1P2_VDD_CORE
P26 V1P2_VDD_CORE V1P2_SATA_AVDD AE13 BFB4
R18 V1P2_VDD_CORE V1P2_SATA_AVDD AF13 30OHM/3A/40mOHM-LF
1
V1P2_CORE R20 V1P2_VDD_CORE V1P2_SATA_AVDD AF14 BCT8
R22 V1P2_VDD_CORE V1P2_SATA_AVDD AG13 BC23 BC24
R24 V1P2_VDD_CORE V1P2_SATA_AVDD AG14 C0805
X5R
10V
R26 V1P2_VDD_CORE V1P2_SATA_AVDD AG15 10%
2
1
BC3 T18 V1P2_VDD_CORE

0.1UF/16V/0402-LF 10UF/Y5V/10V/0805-LF
T20 V1P2_VDD_CORE
0.1uF 0.1UF/16V/0402-LF
C0402
X7R T22 V1P2_VDD_CORE
16V
10% T26 V1P2_VDD_CORE VCC3
2
U18 V1P2_VDD_CORE
1/16
U20 V1P2_VDD_CORE V3P3 AC6
0.1UF/16V/0402-LF U22 V1P2_VDD_CORE V3P3 AC8
1
U23 V1P2_VDD_CORE V3P3 AC9 C240 BC4 BC6 C241
U24 V1P2_VDD_CORE V3P3 AG6
U26 V1P2_VDD_CORE V3P3 AG8 C0402
X7R
C0402
X7R
C0402
X7R
C0402
X7R
16V 16V 16V 16V
V15 V1P2_VDD_CORE V3P3 W6 10% 10% 10% 10%
2
V16 V1P2_VDD_CORE V3P3 W8
V17 V1P2_VDD_CORE V3P3 W9 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF
V18 V1P2_VDD_CORE 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF
V20 V1P2_VDD_CORE
V26 V1P2_VDD_CORE VCC3
W20 V1P2_VDD_CORE V3P3_DAC F28 BFB8
W21 V1P2_VDD_CORE V3.3V_DAC 30OHM/3A/40mOHM-LF
W22 V1P2_VDD_CORE
W23 V1P2_VDD_CORE
1
W24 V1P2_VDD_CORE BC51 BCT14

W26 V1P2_VDD_CORE 4.7uF -> 10uF
Y12 V1P2_VDD_CORE C0402
X7R
C0805
X5R
16V 10V
Y13 V1P2_VDD_CORE 10% 10%
2
Y15 V1P2_VDD_CORE 10UF/Y5V/10V/0805-LF

Y16 V1P2_VDD_CORE
Y17 V1P2_VDD_CORE
Y18 V1P2_VDD_CORE 0.1UF/16V/0402-LF
Y19 V1P2_VDD_CORE
Y26 V1P2_VDD_CORE Title
I378 MCP73 CORE/VTT POWER

A3 I-N73V 0.2
U16J
BGA1048 MCP73
SEC 10 OF 10
A28 GND GND F12
AA15 GND GND F14
AA16 GND GND F18
AA17 GND GND F22
AA18 GND GND F32
AA20 GND GND F35
AA27 GND GND F8
AA4 GND GND G6
AA6 GND GND H1
AA8 GND GND H10
AB18 GND GND H14
AB20 GND GND H18
AB22 GND GND H22
AB23 GND GND H30
AB24 GND GND H33
AB31 GND GND J4
AB33 GND GND J6
AB35 GND GND J8
AC15 GND GND K31
AC16 GND GND K33
AC18 GND GND K35
AC20 GND GND L38
AC22 GND GND L6
AC27 GND GND M1
AC38 GND GND M15
AD16 GND GND M17
AD18 GND GND M19
AD20 GND GND M21
AD22 GND GND M30
AD24 GND GND M31
AD30 GND GND M33
AD31 GND GND N15
AD33 GND GND N17
AE27 GND GND N19
AE4 GND GND N21
AE6 GND GND N4
AE8 GND GND N6
AF31 GND GND N8
AF33 GND GND P31
AF35 GND GND P33
AG18 GND GND P35
AG20 GND GND R12
AG22 GND GND R13
AG24 GND GND R17
AG26 GND GND R19
AH30 GND GND R21
AH31 GND GND R23
AH33 GND GND R27
AJ4 GND GND R38
AK11 GND GND R6
AK15 GND GND R8
AK19 GND GND R9
AK31 GND GND T1
AK33 GND GND T17
AK35 GND GND T19
AL11 GND GND T21
AL13 GND GND T23
AL15 GND GND T24
AL17 GND GND T30
AL19 GND GND T31
AL21 GND GND T33
AL29 GND GND U15
AL9 GND GND U16
AM33 GND GND U17
AN11 GND GND U19
AN13 GND GND U21
AN15 GND GND U27
AN17 GND GND U4
AN19 GND GND U6
AN21 GND GND U8
AN29 GND GND V12
AN31 GND GND V13
AN7 GND GND V19
AN9 GND GND V21
AP35 GND GND V22
AR13 GND GND V23
AR17 GND GND V24
AR21 GND GND V31
AR29 GND GND V33
AR33 GND GND V35
AR38 GND GND W15
AR9 GND GND W16
AV12 GND GND W17
AV16 GND GND W18
AV20 GND GND W19
AV32 GND GND W27
AV36 GND GND W38
C3 GND GND Y20
D10 GND GND Y21
D14 GND GND Y22
D18 GND GND Y23
D22 GND GND Y24
D6 GND GND Y30
E4 GND GND Y31
F10 GND GND Y33
I275
Title
MCP73 GND & JTAG HDR

A3 I-N73V 0.2
SM_MEM BUS ADDRESS
DIMM 0 1010 000
CPU SKT
DIMM 0 DIMM 1 1010 001
IN
SMB_MEM_CL
BI
SMB_MEM_DA
MCP73
MEM_0A_ODT[1..0]
IN
MEM_0A_BA[2..0] ˠ˘ˠ˲˃˔˲ˢ˗˧˃
ˠ˘ˠ˲˃˔˲ˢ˗˧˄
VDDMEM
IN
0
1
MEM_0A_CKE[1..0] ˠ˘ˠ˲˃˔˲˕˔˃
ˠ˘ˠ˲˃˔˲˕˔˄
ˠ˘ˠ˲˃˔˲˕˔˅
IN
MEM_0A_CS*[1..0]
0
1
2
IN
2
ˠ˘ˠ˲˃˔˲˖˞˘˄
ˠ˘ˠ˲˃˔˲˖˞˘˃
DIMM 0 ADDR 0A/CNTL 0A
0
1
ˠ˘ˠ˲˃˔˲˖˦ʽ˃
ˠ˘ˠ˲˃˔˲˖˦ʽ˄
DATA 0
0
1
DIMM 1 ADDR 0A/CNTL 0B IN
MEM_0A_CAS* C54 R132
IN
MEM_0A_RAS* 0.1UF/16V/0402-LF 200-1%-LF
IN
MEM_0A_WE*
IN
MEM_0A_CLK2*
1
IN
MEM_0A_CLK2 DIMM_VREF_CH0
DIMM_VREF_CH0 21
IN
MEM_0A_CLK1*
2
IN
MEM_0A_CLK1
IN
MEM_0A_CLK0* C51
IN
MEM_0A_CLK0 0.1UF/16V/0402-LF R121
200-1%-LF
1
MEM_0_DQS*[7..0]
BI
1
ˠ˘ˠ˲˃˲˗ˤ˦ʽ˃
ˠ˘ˠ˲˃˲˗ˤ˦ʽ˄
ˠ˘ˠ˲˃˲˗ˤ˦ʽ˅
ˠ˘ˠ˲˃˲˗ˤ˦ʽˆ
ˠ˘ˠ˲˃˲˗ˤ˦ʽˇ
ˠ˘ˠ˲˃˲˗ˤ˦ʽˈ
ˠ˘ˠ˲˃˲˗ˤ˦ʽˉ
ˠ˘ˠ˲˃˲˗ˤ˦ʽˊ
0
1
2
3
4
5
6
7
C0402 C0402
X7R X5R
MEM_0_DQS[7..0] 25V
10%
16V
10%
BI
2
C50 C53
ˠ˘ˠ˲˃˲˗ˤ˦˃
ˠ˘ˠ˲˃˲˗ˤ˦˄
ˠ˘ˠ˲˃˲˗ˤ˦˅
ˠ˘ˠ˲˃˲˗ˤ˦ˆ
ˠ˘ˠ˲˃˲˗ˤ˦ˇ
ˠ˘ˠ˲˃˲˗ˤ˦ˈ
ˠ˘ˠ˲˃˲˗ˤ˦ˉ
ˠ˘ˠ˲˃˲˗ˤ˦ˊ
0
1
2
3
4
5
6
7
MEM_0_DQM[7..0]
IN
1000PF/X7R/50V/0402-LF
ˠ˘ˠ˲˃˲˗ˤˠ˃
ˠ˘ˠ˲˃˲˗ˤˠ˄
ˠ˘ˠ˲˃˲˗ˤˠ˅
ˠ˘ˠ˲˃˲˗ˤˠˆ
ˠ˘ˠ˲˃˲˗ˤˠˇ
ˠ˘ˠ˲˃˲˗ˤˠˈ
ˠ˘ˠ˲˃˲˗ˤˠˉ
ˠ˘ˠ˲˃˲˗ˤˠˊ
VDDMEM 0.1UF/16V/0402-LF
MEM_0A_ADD[15..0]
0
1
2
3
4
5
6
7
IN
VCC3
10
11
12
13
14
ˠ˘ˠ˲˃˔˲˔˗˗˃
ˠ˘ˠ˲˃˔˲˔˗˗˄
ˠ˘ˠ˲˃˔˲˔˗˗˅
ˠ˘ˠ˲˃˔˲˔˗˗ˆ
ˠ˘ˠ˲˃˔˲˔˗˗ˇ
ˠ˘ˠ˲˃˔˲˔˗˗ˈ
ˠ˘ˠ˲˃˔˲˔˗˗ˉ
ˠ˘ˠ˲˃˔˲˔˗˗ˊ
ˠ˘ˠ˲˃˔˲˔˗˗ˋ
ˠ˘ˠ˲˃˔˲˔˗˗ˌ
ˠ˘ˠ˲˃˔˲˔˗˗˄˃
ˠ˘ˠ˲˃˔˲˔˗˗˄˄
ˠ˘ˠ˲˃˔˲˔˗˗˄˅
ˠ˘ˠ˲˃˔˲˔˗˗˄ˆ
ˠ˘ˠ˲˃˔˲˔˗˗˄ˇ
ˠ˘ˠ˲˃˔˲˔˗˗˄ˈ
15
NC
NC
NC
NC
0
1
2
3
4
5
6
7
8
9
188
183
182
180
179
177
176
196
174
173
125
134
146
155
202
211
223
232
164
105
114
104
113
161
162
167
168
126
135
147
156
203
212
224
233
165
185
137
220
186
138
221
192
193
171
190
195
102
239
240
101
119
120
238
172
178
184
187
189
197
170
175
181
191
194
63
61
60
58
70
57
16
28
37
84
93
46
15
27
36
83
92
45
42
43
48
49
19
73
74
76
52
71
54
77
68
55
18
53
59
64
67
69
51
56
62
72
75
78
7
1
VREF
ODT0
ODT1
VDDSPD
NC/CB0
NC/CB1
NC/CB2
NC/CB3
NC/CB4
NC/CB5
NC/CB6
NC/CB7
PAR_IN
DM0/DQS9
DM1/DQS10
DM2/DQS11
DM3/DQS12
DM4/DQS13
DM5/DQS14
DM6/DQS15
DM7/DQS16
DM8/DQS17
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
NC/DQS8
DQS0*
DQS1*
DQS2*
DQS3*
DQS4*
DQS5*
DQS6*
DQS7*
NC/DQS8*
NC/DQS9*
NC/DQS10*
NC/DQS11*
NC/DQS12*
NC/DQS13*
NC/DQS14*
NC/DQS15*
NC/DQS16*
NC/DQS17*
CK0*
CK1*
CK2*
RAS*
CAS*
TEST
ERR_OUT*
RESET*
SDA
CK0
CK1
CK2
S0*
S1*
CKE0
CKE1
A16/BA2
SCL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A10/AP
A11
A12
A13
A14
A15
WE*
BA0
BA1
SA0
SA1
SA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
NC
DIMM240
DIMM1
1.8V
DIMM240-GREEN-LF
SK-D240P
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
I545
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
4
9
10
122
123
128
129
12
13
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
100
103
106
109
112
115
118
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
169
198
201
204
207
210
213
216
219
222
225
228
231
234
237
ˠ˘ˠ˲˃˲˗˔˧˔˃
ˠ˘ˠ˲˃˲˗˔˧˔˄
ˠ˘ˠ˲˃˲˗˔˧˔˅
ˠ˘ˠ˲˃˲˗˔˧˔ˆ
ˠ˘ˠ˲˃˲˗˔˧˔ˇ
ˠ˘ˠ˲˃˲˗˔˧˔ˈ
ˠ˘ˠ˲˃˲˗˔˧˔ˉ
ˠ˘ˠ˲˃˲˗˔˧˔ˊ
ˠ˘ˠ˲˃˲˗˔˧˔ˋ
ˠ˘ˠ˲˃˲˗˔˧˔ˌ
ˠ˘ˠ˲˃˲˗˔˧˔˄˃
ˠ˘ˠ˲˃˲˗˔˧˔˄˄
ˠ˘ˠ˲˃˲˗˔˧˔˄˅
ˠ˘ˠ˲˃˲˗˔˧˔˄ˆ
ˠ˘ˠ˲˃˲˗˔˧˔˄ˇ
ˠ˘ˠ˲˃˲˗˔˧˔˄ˈ
ˠ˘ˠ˲˃˲˗˔˧˔˄ˉ
ˠ˘ˠ˲˃˲˗˔˧˔˄ˊ
ˠ˘ˠ˲˃˲˗˔˧˔˄ˋ
ˠ˘ˠ˲˃˲˗˔˧˔˄ˌ
ˠ˘ˠ˲˃˲˗˔˧˔˅˃
ˠ˘ˠ˲˃˲˗˔˧˔˅˄
ˠ˘ˠ˲˃˲˗˔˧˔˅˅
ˠ˘ˠ˲˃˲˗˔˧˔˅ˆ
ˠ˘ˠ˲˃˲˗˔˧˔˅ˇ
ˠ˘ˠ˲˃˲˗˔˧˔˅ˈ
ˠ˘ˠ˲˃˲˗˔˧˔˅ˉ
ˠ˘ˠ˲˃˲˗˔˧˔˅ˊ
ˠ˘ˠ˲˃˲˗˔˧˔˅ˋ
ˠ˘ˠ˲˃˲˗˔˧˔˅ˌ
ˠ˘ˠ˲˃˲˗˔˧˔ˆ˃
ˠ˘ˠ˲˃˲˗˔˧˔ˆ˄
ˠ˘ˠ˲˃˲˗˔˧˔ˆ˅
ˠ˘ˠ˲˃˲˗˔˧˔ˆˆ
ˠ˘ˠ˲˃˲˗˔˧˔ˆˇ
ˠ˘ˠ˲˃˲˗˔˧˔ˆˈ
ˠ˘ˠ˲˃˲˗˔˧˔ˆˉ
ˠ˘ˠ˲˃˲˗˔˧˔ˆˊ
ˠ˘ˠ˲˃˲˗˔˧˔ˆˋ
ˠ˘ˠ˲˃˲˗˔˧˔ˆˌ
ˠ˘ˠ˲˃˲˗˔˧˔ˇ˃
ˠ˘ˠ˲˃˲˗˔˧˔ˇ˄
ˠ˘ˠ˲˃˲˗˔˧˔ˇ˅
ˠ˘ˠ˲˃˲˗˔˧˔ˇˆ
ˠ˘ˠ˲˃˲˗˔˧˔ˇˇ
ˠ˘ˠ˲˃˲˗˔˧˔ˇˈ
ˠ˘ˠ˲˃˲˗˔˧˔ˇˉ
ˠ˘ˠ˲˃˲˗˔˧˔ˇˊ
ˠ˘ˠ˲˃˲˗˔˧˔ˇˋ
ˠ˘ˠ˲˃˲˗˔˧˔ˇˌ
ˠ˘ˠ˲˃˲˗˔˧˔ˈ˃
ˠ˘ˠ˲˃˲˗˔˧˔ˈ˄
ˠ˘ˠ˲˃˲˗˔˧˔ˈ˅
ˠ˘ˠ˲˃˲˗˔˧˔ˈˆ
ˠ˘ˠ˲˃˲˗˔˧˔ˈˇ
ˠ˘ˠ˲˃˲˗˔˧˔ˈˈ
ˠ˘ˠ˲˃˲˗˔˧˔ˈˉ
ˠ˘ˠ˲˃˲˗˔˧˔ˈˊ
ˠ˘ˠ˲˃˲˗˔˧˔ˈˋ
ˠ˘ˠ˲˃˲˗˔˧˔ˈˌ
ˠ˘ˠ˲˃˲˗˔˧˔ˉ˃
ˠ˘ˠ˲˃˲˗˔˧˔ˉ˄
ˠ˘ˠ˲˃˲˗˔˧˔ˉ˅
ˠ˘ˠ˲˃˲˗˔˧˔ˉˆ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
8
9
MEM_0_DATA[63..0]
BI
VDDMEM
3VDUAL 3VDUAL
Prevent ESD issue K K
1
CT58 CT64 CT38 C158 C156 C133 C82 C177 C161 C165
SMB_MEM_DA KA KA
C0805 C0805 C0805 0603_R 0603_R 0603_R C0402 C0402 C0402 C0402
16,21 SMB_MEM_DA
X5R X5R X5R X5R X5R X5R X7R X7R X7R X7R
10V
10%
10V
10%
10V
10%
16V
10%
16V
10%
16V
10%
16V
10%
16V
10%
16V
10%
16V
10% SMB_MEM_CL D14 D12
16,21 SMB_MEM_CL
2
BAV99-LF BAV99-LF
10UF/Y5V/10V/0805-LF 1UF/16V-LF 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF A A

10UF/Y5V/10V/0805-LF 1UF/16V-LF 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF
x10UF/X5R/6.3V/0805-LF 1UF/16V-LF
Title
961213 ECR
Cost down DDR2 DIMM 0
A3 I-N73V 0.2
SM_MEM BUS ADDRESS
DIMM 1 IN
SMB_MEM_CL
DIMM 0
DIMM 1
1010 000
1010 001
BI
SMB_MEM_DA
MEM_0B_ODT[1..0]
IN
CPU SKT MEM_0A_BA[2..0] ˠ˘ˠ˲˃˕˲ˢ˗˧˃

ˠ˘ˠ˲˃˕˲ˢ˗˧˄
IN
0
1
MEM_0B_CKE[1..0] ˠ˘ˠ˲˃˔˲˕˔˃
ˠ˘ˠ˲˃˔˲˕˔˄
ˠ˘ˠ˲˃˔˲˕˔˅
IN
MEM_0B_CS*[1..0]
0
1
2
IN ˠ˘ˠ˲˃˕˲˖˞˘˃
ˠ˘ˠ˲˃˕˲˖˞˘˄
MCP73
0
1
ˠ˘ˠ˲˃˕˲˖˦ʽ˃
ˠ˘ˠ˲˃˕˲˖˦ʽ˄
0
1
IN
MEM_0A_CAS*
IN
MEM_0A_RAS*
IN
MEM_0A_WE*
DIMM 0 ADDR 0A/CNTL 0A MEM_0B_CLK2*
DATA 1 DIMM 1 ADDR 0A/CNTL 0B
IN
MEM_0B_CLK2
IN
IN
MEM_0B_CLK1*
IN
MEM_0B_CLK1
IN
MEM_0B_CLK0*
IN
MEM_0B_CLK0
DIMM_VREF_CH0
IN
MEM_0_DQS*[7..0]
BI
1
MEM_0_DQS[7..0] ˠ˘ˠ˲˃˲˗ˤ˦ʽ˃
ˠ˘ˠ˲˃˲˗ˤ˦ʽ˄
ˠ˘ˠ˲˃˲˗ˤ˦ʽ˅
ˠ˘ˠ˲˃˲˗ˤ˦ʽˆ
ˠ˘ˠ˲˃˲˗ˤ˦ʽˇ
ˠ˘ˠ˲˃˲˗ˤ˦ʽˈ
ˠ˘ˠ˲˃˲˗ˤ˦ʽˉ
ˠ˘ˠ˲˃˲˗ˤ˦ʽˊ
BI
0
1
2
3
4
5
6
7
C52
MEM_0_DQM[7..0] ˠ˘ˠ˲˃˲˗ˤ˦˃
ˠ˘ˠ˲˃˲˗ˤ˦˄
ˠ˘ˠ˲˃˲˗ˤ˦˅
ˠ˘ˠ˲˃˲˗ˤ˦ˆ
ˠ˘ˠ˲˃˲˗ˤ˦ˇ
ˠ˘ˠ˲˃˲˗ˤ˦ˈ
ˠ˘ˠ˲˃˲˗ˤ˦ˉ
ˠ˘ˠ˲˃˲˗ˤ˦ˊ
VCC3 C0402 0.1UF/16V/0402-LF
IN X5R
0
1
2
3
4
5
6
7
VDDMEM 16V
10%
2
ˠ˘ˠ˲˃˲˗ˤˠ˃
ˠ˘ˠ˲˃˲˗ˤˠ˄
ˠ˘ˠ˲˃˲˗ˤˠ˅
ˠ˘ˠ˲˃˲˗ˤˠˆ
ˠ˘ˠ˲˃˲˗ˤˠˇ
ˠ˘ˠ˲˃˲˗ˤˠˈ
ˠ˘ˠ˲˃˲˗ˤˠˉ
ˠ˘ˠ˲˃˲˗ˤˠˊ
0
1
2
3
4
5
6
7
MEM_0A_ADD[15..0]
IN
10
11
12
13
14
15
ˠ˘ˠ˲˃˔˲˔˗˗˃
ˠ˘ˠ˲˃˔˲˔˗˗˄
ˠ˘ˠ˲˃˔˲˔˗˗˅
ˠ˘ˠ˲˃˔˲˔˗˗ˆ
ˠ˘ˠ˲˃˔˲˔˗˗ˇ
ˠ˘ˠ˲˃˔˲˔˗˗ˈ
ˠ˘ˠ˲˃˔˲˔˗˗ˉ
ˠ˘ˠ˲˃˔˲˔˗˗ˊ
ˠ˘ˠ˲˃˔˲˔˗˗ˋ
ˠ˘ˠ˲˃˔˲˔˗˗ˌ
ˠ˘ˠ˲˃˔˲˔˗˗˄˃
ˠ˘ˠ˲˃˔˲˔˗˗˄˄
ˠ˘ˠ˲˃˔˲˔˗˗˄˅
ˠ˘ˠ˲˃˔˲˔˗˗˄ˆ
ˠ˘ˠ˲˃˔˲˔˗˗˄ˇ
ˠ˘ˠ˲˃˔˲˔˗˗˄ˈ
0
1
2
3
4
5
6
7
8
9
NC
NC
NC
NC
188
183
182
180
179
177
176
196
174
173
125
134
146
155
202
211
223
232
164
105
114
104
113
161
162
167
168
126
135
147
156
203
212
224
233
165
185
137
220
186
138
221
192
193
171
190
195
102
239
240
101
119
120
238
172
178
184
187
189
197
170
175
181
191
194
63
61
60
58
70
57
16
28
37
84
93
46
15
27
36
83
92
45
42
43
48
49
19
73
74
76
52
71
54
77
68
55
18
53
59
64
67
69
51
56
62
72
75
78
7
1
VREF
ODT0
ODT1
NC/CB0
NC/CB1
NC/CB2
NC/CB3
NC/CB4
NC/CB5
NC/CB6
NC/CB7
VDDSPD
PAR_IN
DM0/DQS9
DM1/DQS10
DM2/DQS11
DM3/DQS12
DM4/DQS13
DM5/DQS14
DM6/DQS15
DM7/DQS16
DM8/DQS17
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
NC/DQS8
DQS0*
DQS1*
DQS2*
DQS3*
DQS4*
DQS5*
DQS6*
DQS7*
NC/DQS8*
NC/DQS9*
NC/DQS10*
NC/DQS11*
NC/DQS12*
NC/DQS13*
NC/DQS14*
NC/DQS15*
NC/DQS16*
NC/DQS17*
CK0*
CK1*
CK2*
RAS*
CAS*
TEST
ERR_OUT*
RESET*
SDA
CK0
CK1
CK2
S0*
S1*
CKE0
CKE1
A16/BA2
SCL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A10/AP
A11
A12
A13
A14
A15
BA0
BA1
SA0
SA1
SA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
WE*
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
NC
DIMM240
1.8V
DIMM2
DIMM240-GREEN-LF
SK-D240P
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
I545
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
4
9
10
122
123
128
129
12
13
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
100
103
106
109
112
115
118
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
169
198
201
204
207
210
213
216
219
222
225
228
231
234
237
ˠ˘ˠ˲˃˲˗˔˧˔˃
ˠ˘ˠ˲˃˲˗˔˧˔˄
ˠ˘ˠ˲˃˲˗˔˧˔˅
ˠ˘ˠ˲˃˲˗˔˧˔ˆ
ˠ˘ˠ˲˃˲˗˔˧˔ˇ
ˠ˘ˠ˲˃˲˗˔˧˔ˈ
ˠ˘ˠ˲˃˲˗˔˧˔ˉ
ˠ˘ˠ˲˃˲˗˔˧˔ˊ
ˠ˘ˠ˲˃˲˗˔˧˔ˋ
ˠ˘ˠ˲˃˲˗˔˧˔ˌ
ˠ˘ˠ˲˃˲˗˔˧˔˄˃
ˠ˘ˠ˲˃˲˗˔˧˔˄˄
ˠ˘ˠ˲˃˲˗˔˧˔˄˅
ˠ˘ˠ˲˃˲˗˔˧˔˄ˆ
ˠ˘ˠ˲˃˲˗˔˧˔˄ˇ
ˠ˘ˠ˲˃˲˗˔˧˔˄ˈ
ˠ˘ˠ˲˃˲˗˔˧˔˄ˉ
ˠ˘ˠ˲˃˲˗˔˧˔˄ˊ
ˠ˘ˠ˲˃˲˗˔˧˔˄ˋ
ˠ˘ˠ˲˃˲˗˔˧˔˄ˌ
ˠ˘ˠ˲˃˲˗˔˧˔˅˃
ˠ˘ˠ˲˃˲˗˔˧˔˅˄
ˠ˘ˠ˲˃˲˗˔˧˔˅˅
ˠ˘ˠ˲˃˲˗˔˧˔˅ˆ
ˠ˘ˠ˲˃˲˗˔˧˔˅ˇ
ˠ˘ˠ˲˃˲˗˔˧˔˅ˈ
ˠ˘ˠ˲˃˲˗˔˧˔˅ˉ
ˠ˘ˠ˲˃˲˗˔˧˔˅ˊ
ˠ˘ˠ˲˃˲˗˔˧˔˅ˋ
ˠ˘ˠ˲˃˲˗˔˧˔˅ˌ
ˠ˘ˠ˲˃˲˗˔˧˔ˆ˃
ˠ˘ˠ˲˃˲˗˔˧˔ˆ˄
ˠ˘ˠ˲˃˲˗˔˧˔ˆ˅
ˠ˘ˠ˲˃˲˗˔˧˔ˆˆ
ˠ˘ˠ˲˃˲˗˔˧˔ˆˇ
ˠ˘ˠ˲˃˲˗˔˧˔ˆˈ
ˠ˘ˠ˲˃˲˗˔˧˔ˆˉ
ˠ˘ˠ˲˃˲˗˔˧˔ˆˊ
ˠ˘ˠ˲˃˲˗˔˧˔ˆˋ
ˠ˘ˠ˲˃˲˗˔˧˔ˆˌ
ˠ˘ˠ˲˃˲˗˔˧˔ˇ˃
ˠ˘ˠ˲˃˲˗˔˧˔ˇ˄
ˠ˘ˠ˲˃˲˗˔˧˔ˇ˅
ˠ˘ˠ˲˃˲˗˔˧˔ˇˆ
ˠ˘ˠ˲˃˲˗˔˧˔ˇˇ
ˠ˘ˠ˲˃˲˗˔˧˔ˇˈ
ˠ˘ˠ˲˃˲˗˔˧˔ˇˉ
ˠ˘ˠ˲˃˲˗˔˧˔ˇˊ
ˠ˘ˠ˲˃˲˗˔˧˔ˇˋ
ˠ˘ˠ˲˃˲˗˔˧˔ˇˌ
ˠ˘ˠ˲˃˲˗˔˧˔ˈ˃
ˠ˘ˠ˲˃˲˗˔˧˔ˈ˄
ˠ˘ˠ˲˃˲˗˔˧˔ˈ˅
ˠ˘ˠ˲˃˲˗˔˧˔ˈˆ
ˠ˘ˠ˲˃˲˗˔˧˔ˈˇ
ˠ˘ˠ˲˃˲˗˔˧˔ˈˈ
ˠ˘ˠ˲˃˲˗˔˧˔ˈˉ
ˠ˘ˠ˲˃˲˗˔˧˔ˈˊ
ˠ˘ˠ˲˃˲˗˔˧˔ˈˋ
ˠ˘ˠ˲˃˲˗˔˧˔ˈˌ
ˠ˘ˠ˲˃˲˗˔˧˔ˉ˃
ˠ˘ˠ˲˃˲˗˔˧˔ˉ˄
ˠ˘ˠ˲˃˲˗˔˧˔ˉ˅
ˠ˘ˠ˲˃˲˗˔˧˔ˉˆ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
8
9
MEM_0_DATA[63..0]
BI
VDDMEM
1
CT59 C128 C170 C111 C172 C445 C167 C143 C148 C104 C113
C0805 C0603 C0603 C0603 C0603 0603_R C0402 C0402 C0402 C0402 C0402
X5R X5R X5R X5R X5R X5R X7R X7R X7R X7R X7R
10V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2
10UF/Y5V/10V/0805-LF 1UF/16V-LF 1UF/16V-LF 0.01UF/16V/0402-LF

1UF/16V-LF 1UF/16V-LF 0.1UF/16V/0402-LF 0.01UF/16V/0402-LF
1UF/16V-LF 0.1UF/16V/0402-LF
0.1UF/16V/0402-LF
Title
DDR2 DIMM 1
A3 I-N73V 0.2
5 4 3 2 1
VTTMEM
VTTMEM VDDMEM RN13A

0 ˠ˘ˠ˲˃˔˲˔˗˗˃
1 8
47-8P4R-0402-LF
C174
RN12C 2 1
1
C0402
D C107 C108 C193 C188 1 ˠ˘ˠ˲˃˔˲˔˗˗˄
3 6 X7R
0.1UF/16V/0402-LF D
0.1UF/16V/0402-LF
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF
0.1UF/16V/0402-LF C164 16V
47-8P4R-0402-LF 2 1
C0402 C140
10%
C0402 C0402 C0402 C0402 RN12D X7R

0.1UF/16V/0402-LF
16V
2 1
C0402
10% 10% 10% 10% 2 ˠ˘ˠ˲˃˔˲˔˗˗˅
4 5 10% X7R
2
16V 16V 16V 16V
0.1UF/16V/0402-LF
16V
X7R X7R X7R X7R 47-8P4R-0402-LF 10%
C144
RN12B 2 1
C0402 C142
PLACE NEAR ADDR/CTRL TRACES 3 ˠ˘ˠ˲˃˔˲˔˗˗ˆ
2 7 X7R 2 1
0.1UF/16V/0402-LF
16V C0402
47-8P4R-0402-LF 10% X7R
0.1UF/16V/0402-LF
16V
10%
VTTMEM VDDMEM
RN12A
4 ˠ˘ˠ˲˃˔˲˔˗˗ˇ
1 8 C152
47-8P4R-0402-LF 2 1
C0402 C147
RN11C X7R
0.1UF/16V/0402-LF 2 1
1
16V C0402
C162 C151 C150 C109 5 ˠ˘ˠ˲˃˔˲˔˗˗ˈ
3 6 10% X7R
0.1UF/16V/0402-LF
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF 16V
47-8P4R-0402-LF 10%
C185
C0402 C0402 C0402 C0402 RN11D 2 1
C0402 C182
210% 10% 10% 10% 6 ˠ˘ˠ˲˃˔˲˔˗˗ˉ
4 5 X7R 2 1
2
16V 16V 16V 16V
0.1UF/16V/0402-LF
16V C0402
X7R X7R X7R X7R 47-8P4R-0402-LF 10% X7R
0.1UF/16V/0402-LF
16V
10%
PLACE NEAR ADDR/CTRL TRACES

RN11A
7 ˠ˘ˠ˲˃˔˲˔˗˗ˊ
1 8 C183
47-8P4R-0402-LF 2 1
C0402 C176
X7R
0.1UF/16V/0402-LF
16V
2 1
C0402
10% X7R
RN11B 0.1UF/16V/0402-LF
16V
8 ˠ˘ˠ˲˃˔˲˔˗˗ˋ
2 7 10%
C125
47-8P4R-0402-LF 2 1
C0402 C187
RN10C X7R
0.1UF/16V/0402-LF
16V
2 1
C0402
9 ˠ˘ˠ˲˃˔˲˔˗˗ˌ
3 6 10% X7R
0.1UF/16V/0402-LF
16V
47-8P4R-0402-LF 10%
C
RN13C C
10 ˠ˘ˠ˲˃˔˲˔˗˗˄˃
3 6
RN8A C118
1 8 47-8P4R-0402-LF 2 1
C0402 C166
47-8P4R-0402-LF
RN10D X7R
0.1UF/16V/0402-LF
16V
2 1
C0402
11 ˠ˘ˠ˲˃˔˲˔˗˗˄˄
4 5 10% X7R
RN8B 0.1UF/16V/0402-LF
16V
2 7 47-8P4R-0402-LF
C163
10%
47-8P4R-0402-LF
RN10B 2 1
C0402
12 ˠ˘ˠ˲˃˔˲˔˗˗˄˅
2 7 X7R
0.1UF/16V/0402-LF
16V
47-8P4R-0402-LF 10%
C136
RN16A 2 1
C0402
13 ˠ˘ˠ˲˃˔˲˔˗˗˄ˆ
1 8 X7R
0.1UF/16V/0402-LF
16V
47-8P4R-0402-LF 10%
C134
RN9D 2 1
C0402
14 ˠ˘ˠ˲˃˔˲˔˗˗˄ˇ
4 5 X7R
0.1UF/16V/0402-LF
16V
47-8P4R-0402-LF 10%
RN9C
15 ˠ˘ˠ˲˃˔˲˔˗˗˄ˈ
3 6
MEM_0A_ADD[15..0] 47-8P4R-0402-LF
12,20,21 MEM_0A_ADD[15..0]
RN15C
0 ˠ˘ˠ˲˃˔˲ˢ˗˧˃
3 6 RN15B
47-8P4R-0402-LF 0 ˠ˘ˠ˲˃˕˲ˢ˗˧˃
2 7
47-8P4R-0402-LF
RN16D
1 ˠ˘ˠ˲˃˔˲ˢ˗˧˄
4 5 RN16B
47-8P4R-0402-LF 1 ˠ˘ˠ˲˃˕˲ˢ˗˧˄
2 7
MEM_0A_ODT[1..0] 47-8P4R-0402-LF
12,20 MEM_0A_ODT[1..0] MEM_0B_ODT[1..0]
12,21 MEM_0B_ODT[1..0]
RN10A
2 ˠ˘ˠ˲˃˔˲˕˔˅
1 8
47-8P4R-0402-LF
RN13D
B 0 B
ˠ˘ˠ˲˃˔˲˕˔˃
4 5
47-8P4R-0402-LF
RN13B
1 ˠ˘ˠ˲˃˔˲˕˔˄
2 7
47-8P4R-0402-LF
MEM_0A_BA[2..0]
12,20,21 MEM_0A_BA[2..0]
RN8C
0 ˠ˘ˠ˲˃˔˲˖˞˘˃
3 6 RN9A
47-8P4R-0402-LF 0 ˠ˘ˠ˲˃˕˲˖˞˘˃
1 8
47-8P4R-0402-LF
RN8D
1 ˠ˘ˠ˲˃˔˲˖˞˘˄
4 5 RN9B
47-8P4R-0402-LF 1 ˠ˘ˠ˲˃˕˲˖˞˘˄
2 7
MEM_0A_CKE[1..0] 47-8P4R-0402-LF
12,20 MEM_0A_CKE[1..0] RN14C MEM_0B_CKE[1..0]
0 ˠ˘ˠ˲˃˔˲˖˦ʽ˃
3 6 12,21 MEM_0B_CKE[1..0] RN14D
47-8P4R-0402-LF 0 ˠ˘ˠ˲˃˕˲˖˦ʽ˃
4 5
47-8P4R-0402-LF
RN15D
1 ˠ˘ˠ˲˃˔˲˖˦ʽ˄
4 5
MEM_0A_CS*[1..0] RN16C
47-8P4R-0402-LF 1 ˠ˘ˠ˲˃˕˲˖˦ʽ˄
3 6
12,20 MEM_0A_CS*[1..0] MEM_0B_CS*[1..0] 47-8P4R-0402-LF
12,21 MEM_0B_CS*[1..0]
RN15A
MEM_0A_CAS* 1 8
12,20,21 MEM_0A_CAS*
47-8P4R-0402-LF
RN14A
MEM_0A_RAS* 1 8
12,20,21 MEM_0A_RAS*
47-8P4R-0402-LF
RN14B
MEM_0A_WE* 2 7
A 12,20,21 MEM_0A_WE* A
47-8P4R-0402-LF
MEM0_RESET*
Title
DDR TERMINATION
A3 0.2
I-N73V
5 4 3 2 1
5 4 3 2 1
v0.2 BOM
for EMI
PLACE NEAR Connector GND GND_VGA

wuthin 600 mils of VGAPWR_FB
Connector L8 RED_A
11 DAC_RED 60OHM/400mA/150mOHM-LF
K
1
VCC3 0.068nH->60OHM-Bead VGA1
1
R270 9
C137 C120 VCC5 VCC
D D
D18 0603 33PF/NPO/50V/0402-LF 0603 33PF/NPO/50V/0402-LF RED_A RED_A
KA NPO
25V
NPO
25V GREEN_A 1 R
BAV99-LF 150-1%-LF 5% NC->33pF 5% 10pF->33pF GREEN_A 2
2
BLUE_A G
1
EMPTY EMPTY C146 BLUE_A 3
2
0.1UF/16V/0402-LF B 16
C0402
BUF_HSYNC_A 13
A X5R
16V
U11A BUF_HSYNC_A BUF_VSYNC_A HS
14
10% 14 1 6 11
2
L9 GREEN_A 74ACT08-LF BUF_VSYNC_A VS VCC5_FUSE
11 DAC_GREEN 60OHM/400mA/150mOHM-LF
K 1 DDC_SDA 12 DDCDA 2 7 12
1
VCC3 0.068nH->60OHM-Bead 3 HS YNC_R11R277 2HS YNC_R2 L11
1
R271 2 33-LF K 0.068uH/300mA/850mOHM-LF DDC_SCL 15 v0 .2
11 DAC_HSYNC DDCCL 3 8 13
C138 C121 VCC5 27nH->68nH C499 for EMI
1
KA D19 0603 33PF/NPO/50V/0402-LF 0603 33PF/NPO/50V/0402-LF EMICAP2 4
NPO NPO
4 9 14
7
NC1
1
25V 25V
BAV99-LF 150-1%-LF NC->33pF 10pF->33pF C123 EMICAP1 1000PF/X7R/50V/0402-LF
5% 5%
11
2
EMPTY EMPTY D15 47PF/NPO/50V/0402-LF NC2 C66
KA 5 10 15
2
BAV99-LF 0603
5 0.1UF/16V/0402-LF
2
EMPTY
NPO
50V
EMPTY EMPTY EMPTY GND1
10% 6
2
A GND2 17
7 GND3
1
L10 BLUE_A U11B C102 C96
11 DAC_BLUE 8 GND4
60OHM/400mA/150mOHM-LF 74ACT08-LF A x470PF/X7R/16V/0402-LF
K 10 GND5 2.0mm
1
0.068nH->60OHM-Bead 27nH->68nH 0603 x470PF/X7R/16V/0402-LF
0603
VCC3 4 NPO NPO
1
25V 25V
R272 6 VSYNC_R1 1R278 2VSYNC_R2 L12 5% 5%
16 D-Sub footprint
2
C139 C122 33-LF K 0.068uH/300mA/850mOHM-LF H1 -Hi-pin: COD15P-3R-H-2_29
11 DAC_VSYNC 5 17 H2
KA D17 0603 33PF/NPO/50V/0402-LF 0603 33PF/NPO/50V/0402-LF GND GND_VGA -Normal: COD15P-3R
NPO NPO
VCC5
1
25V 25V
BAV99-LF 150-1%-LF 2 5% NC->33pF 5% 10pF->33pF C124 VGACONN-15PIN-LF
2
47PF/NPO/50V/0402-LF
EMPTY EMPTY COD15P-3R
2
D13 KA 0603
NPO
BAV99-LF 50V
10%EMPTY
2
A EMPTY
C for EMI: C
VCC5 2 1 v0.2 BOM

2.2K-LF R221 A
DDC_DATA 1 2 DDC_SDA R752 0-LF
11 DDC_DATA R234 33-LF
K
VCC5
1
C93 GND R258 0-LF GND_VGA

x470PF/X7R/16V/0402-LF
KA D9 0603
NPO
25V
BAV99-LF 5% U11C U11D
2
EMPTY
10 13
VCC5 2 1 8 11
2.2K-LF R237 A
9 12
DDC_CLK 1 2 DDC_SCL I5 I5
11 DDC_CLK R247 33-LF K
VCC5 74ACT08-LF 74ACT08-LF VCC5 D7 FB4 VCC5_FUSE
1
C100 SS12/1A/20V-LF 30OHM/3A/40mOHM-LF

x470PF/X7R/16V/0402-LF 1 2 A K 0805
KA D10 0603
NPO
1
25V
BAV99-LF 5% F2 DO214AC
2
EMPTY C94 0.5A/15V/POLYSWITCH-LF

0.01UF/16V/0402-LF C39
470PF/X7R/16V/0402-LF
2
A
B B
A A
Title
DAC
A3 I-N73V 0.2
5 4 3 2 1
PCIEXP1 VCC12
VCC12 PCIE164-R-ORANGE-LF
3VDUAL VCC3 VCC3 VCC3 VCC3 IN9-SLI del this
PCI_EXPRESS_X16
2
Default
B1 +12V
RIGHT PRSNT1* A1
B2 +12V +12V A2 R438 R439 1/16
10K-0402-LF10K-0402-LF
B3 +12V +12V A3
R474
B4 GND GND A4
SMB_SCL PE _TCK 10K-0402-LF
IN B5 SMCLK TCK A5 1 2
1
SMB_SDA B6 SMDAT TDI A6 PE_TDI
BI
B7 GND TDO A7 TP_PE_TDO NC
1/16 B8 +3.3V TMS A8 PE_TMS
1 R471 2 P R_TRST* B9 TRST* +3.3V A9
10K-0402-LF B10 +3.3V_AUX +3.3V A10
PE_WAKE* B11 WAKE* PERST* A11 PE_RESET*
OUT IN
B12 RSVD GND A12

B13 GND X1 CONNECTOR REFCLK+ A13 PE_X16-1_REFCLK
IN
0 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˃
1 2 PE0_TX0
B14 PETP0 REFCLK- A14 PE_X16-1_REFCLK*
IN
0 C277
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˃ 0.1UF/16V/0402-LF
1 2 PE 0_TX0*
B15 PETN0 GND A15 PE_X16-1_RX[15..0]
OUT
C278 0.1UF/16V/0402-LF
B16 GND PERP0 A16 0 ˣ˘˲˫˄ˉˀ˄˲˥˫˃ PE_X16-1_RX*[15..0]
OUT
PE_X16_PRESENTX1* B17 PRSNT2* PERN0 A17 0 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˃
OUT
B18 GND GND A18
1 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˄
1 2 PE0_TX1
B19 PETP1 RSVD A19
1 C279 0.1UF/16V/0402-LF X4 CONNECTOR
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˄
1 2 PE 0_TX1*
B20 PETN1 GND A20
C280 0.1UF/16V/0402-LF 1
B21 GND PERP1 A21 ˣ˘˲˫˄ˉˀ˄˲˥˫˄
B22 GND PERN1 A22 1 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˄
2 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˅
1 2 PE0_TX2
B23 PETP2 GND A23
2 C281 0.1UF/16V/0402-LF
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˅
1 2 PE 0_TX2*
B24 PETN2 GND A24
C282 0.1UF/16V/0402-LF 2
B25 GND PERP2 A25 ˣ˘˲˫˄ˉˀ˄˲˥˫˅
B26 GND PERN2 A26 2 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˅
3 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˆ
1 2 PE0_TX3
B27 PETP3 GND A27
3 C283 0.1UF/16V/0402-LF
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽˆ
1 2 PE 0_TX3*
B28 PETN3 GND A28
C284 0.1UF/16V/0402-LF 3
B29 GND PERP3 A29 ˣ˘˲˫˄ˉˀ˄˲˥˫ˆ
B30 RSVD PERN3 A30 3

ˣ˘˲˫˄ˉˀ˄˲˥˫ʽˆ
OUT
PE_X16_PRESENTX4* B31 PRSNT2* GND A31 X16 SLOT DECOUPLING
B32 GND RSVD A32
4 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˇ
1 2 PE0_TX4
B33 PETP4 RSVD A33
4 C285 0.1UF/16V/0402-LF X8 CONNECTOR VCC12
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽˇ
1 2 PE 0_TX4*
B34 PETN4 GND A34
C286 0.1UF/16V/0402-LF 4
B35 GND PERP4 A35 ˣ˘˲˫˄ˉˀ˄˲˥˫ˇ
B36 GND PERN4 A36 4 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽˇ
5 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˈ
1 2 PE0_TX5
B37 PETP5 GND A37
PE_X16-1_TXC[15..0] 5 C287
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽˈ 0.1UF/16V/0402-LF
1 2 PE 0_TX5*
B38 PETN5 GND A38
IN
1
C288 0.1UF/16V/0402-LF
B39 GND PERP5 A39 5 ˣ˘˲˫˄ˉˀ˄˲˥˫ˈ
+ CE29 C341 C349 C370
B40 GND PERN5 A40 5 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽˈ
0603 0603 0.1uF 0603 0.1uF
6 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˉ
1 2 PE0_TX6
B41 PETP6 GND A41 470UF/MBZ/16V/DIP-LF
2
6 C289 0.1UF/16V/0402-LF
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽˉ
1 2 PE 0_TX6*
B42 PETN6 GND A42
PE_X16-1_TXC*[15..0] C290 0.1UF/16V/0402-LF
B43 GND PERP6 A43 6 ˣ˘˲˫˄ˉˀ˄˲˥˫ˉ
0.1UF/16V/0402-LF
IN
B44 GND PERN6 A44 6 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽˉ
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF
7 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˊ
1 2 PE0_TX7
B45 PETP7 GND A45
7 C291 0.1UF/16V/0402-LF 3VDUAL
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽˊ
1 2 PE 0_TX7*
B46 PETN7 GND A46
C292 0.1UF/16V/0402-LF 7
B47 GND PERP7 A47 ˣ˘˲˫˄ˉˀ˄˲˥˫ˊ
PE_X16_PRESENTX8* B48 PRSNT2* PERN7 A48 7 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽˊ
OUT
B49 GND GND A49
1
CT78 CT72 CT75
8 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˋ
1 2 PE0_TX8
B50 PETP8 RSVD A50 C350
8 C293 0.1UF/16V/0402-LF X16 CONNECTOR 0603
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽˋ
1 2 PE 0_TX8*
B51 PETN8 GND A51
C294 0.1UF/16V/0402-LF
B52 GND PERP8 A52 8 ˣ˘˲˫˄ˉˀ˄˲˥˫ˋ 1/16
2
8 0.1UF/16V/0402-LF
B53 GND PERN8 A53 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽˋ
9 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˌ
1 2 PE0_TX9
B54 PETP9 GND A54 10UF/Y5V/10V/0805-LF
9 C295 0.1UF/16V/0402-LF 10UF/Y5V/10V/0805-LF
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽˌ
1 2 PE 0_TX9*
B55 PETN9 GND A55
C296 0.1UF/16V/0402-LF 9 10UF/Y5V/10V/0805-LF
B56 GND PERP9 A56 ˣ˘˲˫˄ˉˀ˄˲˥˫ˌ
B57 GND PERN9 A57 9 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽˌ
10 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˄˃
1 2 PE0_TX 10
B58 PETP10 GND A58 VCC3
10 C297 0.1UF/16V/0402-LF
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˄˃
1 2 PE0_ TX10*
B59 PETN10 GND A59
C298 0.1UF/16V/0402-LF 10 ˣ˘˲˫˄ˉˀ˄˲˥˫˄˃
B60 GND PERP10 A60
B61 GND PERN10 A61 10 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˄˃
11 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˄˄
1 2 PE0_TX 11
B62 PETP11 GND A62 1
11 C299 0.1UF/16V/0402-LF CE34 C259
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˄˄
1 2 PE0_ TX11*
B63 PETN11 GND A63
C300 0.1UF/16V/0402-LF 11 ˣ˘˲˫˄ˉˀ˄˲˥˫˄˄ 0603 0.1UF/16V/0402-LF
B64 GND PERP11 A64
B65 GND PERN11 A65 11 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˄˄
12 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˄˅
1 2 PE0_TX 12
B66 PETP12 GND A66 2 1000UF/6.3V/DIP-LF
12 C301 0.1UF/16V/0402-LF
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˄˅
1 2 PE0_ TX12*
B67 PETN12 GND A67
C302 0.1UF/16V/0402-LF 12 ˣ˘˲˫˄ˉˀ˄˲˥˫˄˅
B68 GND PERP12 A68
B69 GND PERN12 A69 12 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˄˅
13 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˄ˆ
1 2 PE0_TX 13
B70 PETP13 GND A70
13 C303 0.1UF/16V/0402-LF
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˄ˆ
1 2 PE0_ TX13*
B71 PETN13 GND A71
C304 0.1UF/16V/0402-LF 13 ˣ˘˲˫˄ˉˀ˄˲˥˫˄ˆ
B72 GND PERP13 A72
B73 GND PERN13 A73 13 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˄ˆ
14 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˄ˇ
1 2 PE0_TX 14
B74 PETP14 GND A74
14 C305 0.1UF/16V/0402-LF
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˄ˇ
1 2 PE0_ TX14*
B75 PETN14 GND A75
C306 0.1UF/16V/0402-LF 14 ˣ˘˲˫˄ˉˀ˄˲˥˫˄ˇ
B76 GND PERP14 A76
B77 GND PERN14 A77 14 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˄ˇ
15 ˣ˘˲˫˄ˉˀ˄˲˧˫˖˄ˈ
1 2 PE0_TX 15
B78 PETP15 GND A78
15 C307 0.1UF/16V/0402-LF
ˣ˘˲˫˄ˉˀ˄˲˧˫˖ʽ˄ˈ
1 2 PE0_ TX15*
B79 PETN15 GND A79
C308 0.1UF/16V/0402-LF 15 ˣ˘˲˫˄ˉˀ˄˲˥˫˄ˈ
B80 GND PERP15 A80
PE_X16_PRESENTX16* B81 PRSNT2* PERN15 A81 15 ˣ˘˲˫˄ˉˀ˄˲˥˫ʽ˄ˈ
OUT
B82 RSVD GND A82
I173 FLASH
PLACE CAPS NEAR CONNECTOR
Title
PCI-E X16 CONN

A3 0.2
I-N73V
PCIE1 VCC12
3VDUAL VCC3 VCC12 CONN_R VCC3 VCC3 VCC3 IN9-SLI del this SLOT DECOUPLING
PCI_EXPRESS_X1
2
B1 +12V PRSNT1* A1 VCC12
B2 +12V +12V A2 R434 R430 1/16
10K-0402-LF10K-0402-LF
B3 +12V +12V A3
R429
B4 GND GND A4
SMB_SCL PE1_TCK 10K-0402-LF
IN B5 SMCLK TCK A5 1 2
1
SMB_SDA B6 SMDAT TDI A6 PE1_TDI
BI
B7 GND TDO A7 TP_PE1_TDO NC
1/16 B8 +3.3V TMS A8 PE1_TMS
1 2 PE 2_TRST* B9 TRST* +3.3V A9
R431 10K-0402-LF B10 +3.3V_AUX +3.3V A10
PE_WAKE* B11 WAKE* PERST* A11 PE_RESET*
OUT IN
B12 RSVD GND A12

B13 GND X1 CONNECTOR REFCLK+ A13 PE1_REFCLK
IN
0402
IN
PE1_TXC C260 0.1UF/16V/0402-LF PE1 _TX
B14 PETP0 REFCLK- A14 PE1_REFCLK*
IN
0402
PE1_TXC* PE1_TX*
B15 PETN0 GND A15
IN
C257 0.1UF/16V/0402-LF B16 GND PERP0 A16 PE1_RX
OUT
VCC3
PE1_PRESENT* B17 PRSNT2* PERN0 A17 PE1_RX*
OUT OUT 1/16
B18 GND GND A18
I473 15U
Title
PCI-E X1 CONN
A3 0.2
I-N73V
5 4 3 2 1
D SLOT 1 D
PCI1 SLOT 2
SL-PCI120P PCI2
PCI124 3VDUAL SL-PCI120P
PCI_AD[31..0] V2.2 PCI124 3VDUAL
13 PCI_AD[31..0] 0 PCI_AD[31..0]
ˣ˖˜˲˔˗˃
A58 AD0 5V 32BIT 3.3VAUX A14 V2.2
1 13 PCI_AD[31..0] 0
ˣ˖˜˲˔˗˄
B58 AD1 TDO B4 ˣ˖˜˲˔˗˃
A58 AD0 5V 32BIT 3.3VAUX A14
2 1
ˣ˖˜˲˔˗˅
A57 AD2 PRSNT1* B9 ˣ˖˜˲˔˗˄
B58 AD1 TDO B4
3 2
ˣ˖˜˲˔˗ˆ
B56 AD3 PRSNT2* B11 ˣ˖˜˲˔˗˅
A57 AD2 PRSNT1* B9
4 3
ˣ˖˜˲˔˗ˇ
A55 AD4 RSVD1 A9 ˣ˖˜˲˔˗ˆ
B56 AD3 PRSNT2* B11
5 4
ˣ˖˜˲˔˗ˈ
B55 AD5 RSVD2 B10 ˣ˖˜˲˔˗ˇ
A55 AD4 RSVD1 A9
6 5
ˣ˖˜˲˔˗ˉ
A54 AD6 RSVD3 A11 ˣ˖˜˲˔˗ˈ
B55 AD5 RSVD2 B10
7 6
ˣ˖˜˲˔˗ˊ
B53 AD7 RSVD5 B14 ˣ˖˜˲˔˗ˉ
A54 AD6 RSVD3 A11
8 7
ˣ˖˜˲˔˗ˋ
B52 AD8 T CK B2 ˣ˖˜˲˔˗ˊ
B53 AD7 RSVD5 B14
9 8
ˣ˖˜˲˔˗ˌ
A49 AD9 T RST* A1 ˣ˖˜˲˔˗ˋ
B52 AD8 T CK B2
10 9
ˣ˖˜˲˔˗˄˃
B48 AD10 TMS A3 ˣ˖˜˲˔˗ˌ
A49 AD9 T RST* A1
11 10
ˣ˖˜˲˔˗˄˄
A47 AD11 TDI A4 ˣ˖˜˲˔˗˄˃
B48 AD10 TMS A3
12 11
ˣ˖˜˲˔˗˄˅
B47 AD12
ˣ˖˜˲˔˗˄˄
A47 AD11 TDI A4
13 12
ˣ˖˜˲˔˗˄ˆ
A46 AD13
ˣ˖˜˲˔˗˄˅
B47 AD12
14 13
ˣ˖˜˲˔˗˄ˇ
B45 AD14
ˣ˖˜˲˔˗˄ˆ
A46 AD13
15 VCC12 14
ˣ˖˜˲˔˗˄ˈ
A44 AD15
ˣ˖˜˲˔˗˄ˇ
B45 AD14
16 15 VCC12
ˣ˖˜˲˔˗˄ˉ
A32 AD16
-12V ˣ˖˜˲˔˗˄ˈ
A44 AD15
17 16
ˣ˖˜˲˔˗˄ˊ
B32 AD17 +12V A2 ˣ˖˜˲˔˗˄ˉ
A32 AD16
-12V
18 17
ˣ˖˜˲˔˗˄ˋ
A31 AD18 -12V B1 ˣ˖˜˲˔˗˄ˊ
B32 AD17 +12V A2
19 18
ˣ˖˜˲˔˗˄ˌ
B30 AD19
ˣ˖˜˲˔˗˄ˋ
A31 AD18 -12V B1
20 19
ˣ˖˜˲˔˗˅˃
A29 AD20 +5V B5 ˣ˖˜˲˔˗˄ˌ
B30 AD19
21 20
ˣ˖˜˲˔˗˅˄
B29 AD21 +5V B6 ˣ˖˜˲˔˗˅˃
A29 AD20 +5V B5
22 21
ˣ˖˜˲˔˗˅˅
A28 AD22 +5V A5 ˣ˖˜˲˔˗˅˄
B29 AD21 +5V B6
C 23 22 C
ˣ˖˜˲˔˗˅ˆ
B27 AD23 +5V A8 ˣ˖˜˲˔˗˅˅
A28 AD22 +5V A5
24 23
ˣ˖˜˲˔˗˅ˇ
A25 AD24 +5V A10 ˣ˖˜˲˔˗˅ˆ
B27 AD23 +5V A8
25 24
ˣ˖˜˲˔˗˅ˈ
B24 AD25 +5V B61 ˣ˖˜˲˔˗˅ˇ
A25 AD24 +5V A10
26 25
ˣ˖˜˲˔˗˅ˉ
A23 AD26 +5V A16 ˣ˖˜˲˔˗˅ˈ
B24 AD25 +5V B61
PCI_AD26 27 26
ˣ˖˜˲˔˗˅ˊ
B23 AD27 +5V B62 ˣ˖˜˲˔˗˅ˉ
A23 AD26 +5V A16
28 PCI_AD25 27
ˣ˖˜˲˔˗˅ˋ
A22 AD28 +5V A59 ˣ˖˜˲˔˗˅ˊ
B23 AD27 +5V B62
29 28
ˣ˖˜˲˔˗˅ˌ
B21 AD29 +5V B59 ˣ˖˜˲˔˗˅ˋ
A22 AD28 +5V A59
PCI_AD22 30 VCC5 29
ˣ˖˜˲˔˗ˆ˃
A20 AD30 +5V A61 ˣ˖˜˲˔˗˅ˌ
B21 AD29 +5V B59
31 PCI_AD23 30 VCC5
ˣ˖˜˲˔˗ˆ˄
B20 AD31 +5V B19 ˣ˖˜˲˔˗ˆ˃
A20 AD30 +5V A61
31
A26 IDSEL +5V A62 ˣ˖˜˲˔˗ˆ˄
B20 AD31 +5V B19
PCI_C/BE*[3..0] 25
13 PCI_C/BE*[3..0] A26 IDSEL +5V A62
0 PCI_C/BE*[3..0]
ˣ˖˜˲˖˂˕˘ʽ˃
A52 CBE0* +3.3V A21 13 PCI_C/BE*[3..0]
1 0
ˣ˖˜˲˖˂˕˘ʽ˄
B44 CBE1* +3.3V A27 ˣ˖˜˲˖˂˕˘ʽ˃
A52 CBE0* +3.3V A21
2 1
ˣ˖˜˲˖˂˕˘ʽ˅
B33 CBE2* +3.3V A33 ˣ˖˜˲˖˂˕˘ʽ˄
B44 CBE1* +3.3V A27
3 2
ˣ˖˜˲˖˂˕˘ʽˆ
B26 CBE3* +3.3V A39 ˣ˖˜˲˖˂˕˘ʽ˅
B33 CBE2* +3.3V A33
3
+3.3V A45 ˣ˖˜˲˖˂˕˘ʽˆ
B26 CBE3* +3.3V A39
PCI_INTY* A6 INTA* +3.3V B43 +3.3V A45
13,27 PCI_INTY* PCI_INTZ* PCI_INTZ*
13,27 PCI_INTZ* B7 INTB* +3.3V B41 13,27 PCI_INTX* 13,27 PCI_INTZ* A6 INTA* +3.3V B43
PCI_INTW* A7 INTC* +3.3V B36 PCI_INTW* B7 INTB* +3.3V B41
13,27 PCI_INTW* PCI_INTX* 13,27 PCI_INTY* 13,27 PCI_INTW* PCI_INTX*
13,27 PCI_INTX* B8 INTD* +3.3V B31 13,27 PCI_INTZ* 13,27 PCI_INTX* A7 INTC* +3.3V B36
+3.3V B25 VCC3 PCI_INTY* B8 INTD* +3.3V B31
PCI_REQ*0 13,27 PCI_INTW* 13,27 PCI_INTY* VCC3
13,27 PCI_REQ*0 B18 REQ* +3.3V B54 +3.3V B25
PCI_GNT*0 A17 GNT* +3.3V A53 PCI_REQ*1 B18 REQ* +3.3V B54
13 PCI_GNT*0 13,27 PCI_REQ*3 13,27 PCI_REQ*1 PCI_GNT*1
PCI_GNT*3 13 PCI_GNT*1 A17 GNT* +3.3V A53
PCI_PME* A19 PME*
13,27 PCI_PME* PCI_FRAME* PCI_PME*
13,27 PCI_FRAME* A34 FRAME* GND A12 13,27 PCI_PME* A19 PME*
PCI_TRDY* A36 TRDY* GND A13 PCI_FRAME* A34 FRAME* GND A12
13,27 PCI_TRDY* PCI_STOP* 13,27 PCI_FRAME* PCI_TRDY*
13,27 PCI_STOP* A38 STOP* GND A18 13,27 PCI_TRDY* A36 TRDY* GND A13
PCI_IR DY* B35 IRDY* GND A24 PCI_STOP* A38 STOP* GND A18
B 13,27 PCI_IRDY* PCI_DEVSEL* 13,27 PCI_STOP* PCI_IR DY* B
13,27 PCI_DEVSEL* B37 DEVSEL* GND A30 13,27 PCI_IRDY* B35 IRDY* GND A24
PCI_LOCK* B39 A35 PCI_DEVSEL* B37 A30
27 PCI_LOCK* LOCK* GND 13,27 PCI_DEVSEL* DEVSEL* GND
PCI_PERR* B40 A37 PCI_LOCK* B39 A35
13,27 PCI_PERR* PERR* GND 27 PCI_LOCK* LOCK* GND
PCI_SERR* B42 A42 PCI_PERR* B40 A37
13,27 PCI_SERR* SERR* GND 13,27 PCI_PERR* PERR* GND
PCI_PAR A43 A48 PCI_SERR* B42 A42
13 PCI_PAR PAR GND 13,27 PCI_SERR* SERR* GND
SMB_SDA A41 A56 PCI_PAR A43 A48
16,24,25 SMB_SDA SBO* GND 13 PCI_PAR PAR GND
PCI_RST_SLOT1* A15 B3 SMB_SDA A41 A56
13 PCI_RST_SLOT1* RESET* GND 16,24,25 SMB_SDA SBO* GND
SMB_SCL A40 B12 PCI_RST_SLOT2* A15 B3
16,24,25 SMB_SCL SDONE GND 13 PCI_RST_SLOT2* RESET* GND
B13 SMB_SCL A40 B12
GND 16,24,25 SMB_SCL SDONE GND
PCI_REQ64B* A60 B15 B13
27 PCI_REQ64B* REQ64* GND GND
PCI_ACK64* B60 B17 PCI_REQ64B* A60 B15
27 PCI_ACK64* ACK64* GND 27 PCI_REQ64B* REQ64* GND
PCI_CLKSLOT1 B16 B22 PCI_ACK64* B60 B17
13 PCI_CLKSLOT1 CLOCK GND 27 PCI_ACK64* ACK64* GND
B28 PCI_CLKSLOT2 B16 B22
GND 13 PCI_CLKSLOT2 CLOCK GND
KEY<A50> GND B34 GND B28
KEY<A51> GND B38 KEY<A50> GND B34
KEY<B50> GND B46 KEY<A51> GND B38
KEY<B51> GND B49 KEY<B50> GND B46
GND B57 KEY<B51> GND B49
GND B57
I136
I136
3VDUAL 3VDUAL
Prevent ESD issue K K
A A
SMB_SDA KA KA
16,24,25 SMB_SDA
SMB_SCL D22 D21
16,24,25 SMB_SCL
BAV99-LF BAV99-LF
A A
MCP73 CRB no this Title
PCI 1 & 2 SLOT

A3 0.2
I-N73V
5 4 3 2 1
5 4 3 2 1
D
PCI SLOT DECOUPLING D
VCC3 VCC5
CT82
C348
2 1
C0402
+
X5R
0.1UF/16V/0402-LF
16V
10% 10UF/Y5V/10V/0805-LF
C366 C387
2 1
C0402
2 1
C0402
X5R X5R
0.1UF/16V/0402-LF
16V
0.1UF/16V/0402-LF
16V
VCC3 8.2K 10% 10%
RN19A -> 10K VCC3 C347 C368

PCI_STOP* 1 8 PCI_REQ*[4..0] R495 2 1 2 1
13,26 PCI_STOP* 13,26 PCI_REQ*[4..0] 0
C0402 C0402
8.2K-8P4R-LF 1
ˣ˖˜˲˥˘ˤʽ˃
2 X5R
0.1UF/16V/0402-LF
16V
X5R
0.1UF/16V/0402-LF
16V
R0402 5% 10% 10%
10K-0402-LF
RN19B C384
PCI_LOCK* 2 7 R458 2 1
26 PCI_LOCK* 1
C0402
8.2K-8P4R-LF 1
ˣ˖˜˲˥˘ˤʽ˄
2 X5R
0.1UF/16V/0402-LF
16V
R0402 5% 10%
10K-0402-LF
RN19C C389 C406
PCI_PERR* 3 6 R469 2 1 2 1
13,26 PCI_PERR* 2
C0603 C0402
8.2K-8P4R-LF 1
ˣ˖˜˲˥˘ˤʽ˅
2 X5R
1UF/16V-LF
16V
X5R
0.1UF/16V/0402-LF
16V
R0402 5% 10% 10%
10K-0402-LF
RN19D
PCI_SERR* 4 5 R496
13,26 PCI_SERR* 3
8.2K-8P4R-LF 1
ˣ˖˜˲˥˘ˤʽˆ
2
R0402 5%
10K-0402-LF
RN18D
C PCI_DEVSEL* 4 5 R468
C
13,26 PCI_DEVSEL* 4 VCC3
8.2K-8P4R-LF 1
ˣ˖˜˲˥˘ˤʽˇ
2
R0402 5%
10K-0402-LF VCC5
RN18C
PCI_TRDY* 3 6 RN18B
13,26 PCI_TRDY* PCI_IR DY*
8.2K-8P4R-LF
13,26 PCI_IRDY* 2 7
8.2K-8P4R-LF
RN18A
100uF
PCI_FRAME* CT77
13,26 PCI_FRAME* 1 8 RN20A
8.2K-8P4R-LF PCI_INTY* 1 8 VCC5
13,26 PCI_INTY*
+
8.2K-8P4R-LF
RN20B 10UF/Y5V/10V/0805-LF
PCI_INTW* 2 7 RN20C
13,26 PCI_INTW* PCI_INTZ*
8.2K-8P4R-LF
13,26 PCI_INTZ* 3 6 C371
8.2K-8P4R-LF 2 1
C0402
RN20D
0.1uF X5R
0.1UF/16V/0402-LF
16V
PCI_INTX* 4 5 R528 10%
13,26 PCI_INTX* PCI_ACK64* VCC3
8.2K-8P4R-LF
26 PCI_ACK64* 1 2
C386
100uF->1000uF
10K-0402-LF CE36
R550 2 1
C0402
PCI_REQ64B* 1 2 8.2K(8P4R) -> 10K X5R
1000UF/6.3V/DIP-LF
26 PCI_REQ64B* 0.1UF/16V/0402-LF
16V
10%
C367
10K-0402-LF
C388 2 1
C0402
2 1 X5R
0.1UF/16V/0402-LF
OUT
PCI_CLKRUN* C0402
X5R
0.1UF/16V/0402-LF
16V
10% 100uF
16V
10%
MCP51 C346
added 8.2K(8P4R) -> 10K 2 1
C0402
X5R
0.1UF/16V/0402-LF
B 16V
3VDUAL B
10%
0.1uF
0.1uF
100uF
C365
2 1
C0402
X5R
0.1UF/16V/0402-LF
16V
3VDUAL 10%
PCI_PME* R549
13,26 PCI_PME* 1 2
R0402 5%
10K-0402-LF
8.2K(8P4R) -> 10K
A A
Title
PCI TERM/DECOUPLING
A3 0.2
I-N73V
5 4 3 2 1
5 4 3 2 1
ATXPWR1
VCC5SB VCC3 -12V VCC5 VCC12 VCC5SB VCC5SB
VCC5SB
2
3.3V 1
3.3V
R263 13
-12V 2
3.3V
14
SMB_SCL x22K-LF GND 3
GND
16,24,25,26 SMB_SCL
2
R266 15
1
R681 2K-1%-LF ATX_PS_ON* 16
PS_ON* 5V
4
C
D SMB_SDA SMB1 x10K-0402-LF R293 D
16,24,25,26 SMB_SDA GND 22K-LF
5VDUAL 16,38 PWRGD_SB 2 1 B 5
GND
13,26,27 PCI_PME* PCI_PME* Q42 17

PMBS3904-LF GND 5V
6
1
E
C476 0603 R265 470pF 18
1UF/16V-LF 1K-LF 7
GND
GND
VCC5SB 19
1 Reserve NC 8
PW R_OK PWRGD_PS PWRGD_PS 31
20
5V 9
5VSB
R267 21
1
4.7K-0402-LF 5V 10
12V C168
1
W83627_PSON# C178 100uF->10uFx2 470PF/X7R/16V/0402-LF
32,33,38 W83627_PSON# 22
2
5V 11
12V
W83303D_PSOUT* 23 CT56 CT55
2
GND 12
3.3V
2
24
0.1UF/16V/0402-LF W83303D_PSOUT* 2N7002
5VDUAL W83627DHF/ AN2(Pin70):
- Test mode: pull-high 5V_dual
- *User mode: pull-down COP2X12P-ATXS 10UF/Y5V/10V/0805-LF
ATX_PWR_24 10UF/Y5V/10V/0805-LF
R594 I272
x10K-LF SUSLED1
C
IDE_HDLED_P* K2 R579 B Q75
36 IDE_HDLED_P* 2
38 SUSLED
A HDDLED* VCC5 2.2K-LF PMBS3904-LF
SATA_HDLED* K1
14 SATA_HDLED*
E
1
C D28 R574 2.2K-LF 5VDUAL C

BAT54A-LF 3VDUAL VCC5SB KN9-SLI issue:
1
(issue): LOW power supply supportability.
ROM_WP_EN: R620 (Sol): Add loading to 5VSB
- 0 : ROM Write-able Q66
D
- 1 : ROM Write protect (default) 2N7002-LF 220-LF R616 W83627DHG ref._v0.5: VCC5SB
330-LF PSIN# serier resistance might need to
15,38,39 ROM_WP_EN G FPIO1 R578 be tuned for EOS and compatibility
4.7K-0402-LF
2
S
2
HDDLEDV 1 2 SUSLEDV R308 R313
HDD_LED+ 1 2 SP_LED+
2
R592 x1K-LF HDDLED* 3 4 220-0805-LF x475-0805-LF
3VDUAL HDD_LED- SP_LED-
REST_SW 5 6 FP_PWRSW R570 100-1%-LF PANSWIN* 38
FP_RESET*R RESET SW- PWR_ON+ FP_PWRSW_N
16 FP_RESET* 1 2 7 RESET SW+ PWR_ON- 8 PANSWIN
R593 22-LF 9 475//475 ->220
to MCP73 5VDUAL NC VCC5 Winbond SIO- PSIN define:
1
R618 68-0805-LF BUZZER_5V 13 C428 - DHG: PSIN is ative LOW
1
D32 C427 R622 68-0805-LF SPEAKER+5V PWRLEDV R615 R577 Q74 - EHG: PSIN is ative HIGH
15 16
D
SPEAKER GND1 PWR LED+ 147-1%-LF x10K-LF
x0.1UF/16V/0402-LF 2N7002-LF
38 WDTORST* K A 17
K
0.1UF/16V/0402-LF SPEAKER GND2

19 SPEAKER DRIVER19 PWR LED- 20
from SIO LL4148/150MA-LF D31 20 G ROM_WP_EN 15,38,39
LL4148/150MA-LF
S
10*2PIN-LF CH2X10P-CUT5P ROM_WP_EN:
A
R595 0-0402-LF BUZZER_DRV - 0 : ROM Write-able

7 XDP_FNTPNL_RST*
- 1 : ROM Write protect (default) VCC12
from CPU IP35 stuffed PCIEX AUX PWR
W83627DHG ref.
5VDUAL used NPN ,not PNP 5VDUAL
B R538 x0-LF BUZZER_DRV 3VDUAL B
BEEP pin (OD) state after system reset
W83627DHG = Low
10K-LF 5VDUAL VCC5 FPIO1
R537
W83627EHF = high
C381 Lighter
C
W83627HF = Low
38 W_BEEP B Q63 0.1UF/16V/0402-LF R106 R354 Layout please

PMBS3904-LF 3VDUAL
220-LF R535 220-LF 220-LF NEAR FPIO1
E
SPEAKER STRAPS VCC3

ROM Table Select 2 1
C
A
R539 1K-0402-LF
0= USER SPEAKER R536 SPKR2 B Q62 LED1 LED2
15,35 SPEAKER PMBS3904-LF
1= SAFE(Default) 2.2K-LF
Buzzer Driver from chipset
1 2 C375 LED-Red-LF LED-Green-LF
E
R544 x1K-LF
K
K
0.1UF/16V/0402-LF
VBATCCMOS Layout please

3VDUAL VBATCCMOS
Quick Button NEAR FPIO1
ATX4P_DETECT
to MCP51 GPIO
D29 CT84 CT85
1
BAT54C-LF CCMOS1 C434 C425 FP_PWRSW_N FP_PWRSW

+ + 0.1UF/16V/0402-LF0.1UF/16V/0402-LF
A
3V_BATTERY-HOLDER-LF A2 2
HEADER3X1-Black-LF A
K VBATS 1
BA TT_PW R 1 2BATT_PWR_R A1 2
2
1
3 10UF/Y5V/10V/0805-LF
BAT1 R610 1K-LF 10UF/Y5V/10V/0805-LF
D27
BATTERY=VBAT BAT54C-LF R571
A1 1 100-1%-LF REST_SW FP_RESET*R
GND
K Title
16 RTC_RST*
A2 2
CMOS CLEAR JUMPER PWR CON/F-PNL/VBAT/SPKR

A3 I-N73V 0.2
5 4 3 2 1
5 4 3 2 1
3VDUAL 0.5V~1.6V/100A
CPU VCCP VCC12A L2 VIN Layout VCCP
ATX12V1 1.2uH/DIP/10A-LF Place on solder side
ADJ max= 375mV
Protect Circuit
2
CPU VCCP VCCP 1
GND
RT8802_DVDEN 5
+12V
Protect Circuit 2
GND + + + + + + + + + +
OVP_EN 6
+12V C25 + 220uF 220uF 220uF 220uF 820uF 820uF
FDD8780-8.5mOHM 3
GND 0603 CE5 CE9 CE19 CE40 CE3 CE14 CE17 CE4 CE15 CE8
2N7002 7
+12V CE41
ATX Power 4
GND 680UF/4V/LR/DIP-LF
W83303D_PSOUT*
8
+12V 1000UF/16V/LR/DIP-LF Reserve for Lab. test 820UF/SOLID/2.5V/DIP-LF 680UF/4V/LR/DIP-LF
28,31 PWRGD_PS
D 2N7002 COP2X4P-ATXS 1UF/X7R/16V-LF 1000UF/16V/LR/DIP-LF 820UF/SOLID/2.5V/DIP-LF 680UF/4V/LR/DIP-LF D
I178 1000UF/16V/LR/DIP-LF 1000UF/16V/LR/DIP-LF 680UF/4V/LR/DIP-LF
1000UF/16V/LR/DIP-LF
VIN
OVP_EN 2N7002
U44 VCC12A 1 2
RT9605BPQ-LF R269 Q36 C79 1UF/X7R/16V-LF
1206
22 4.7-0805-LF
from OVP Circuit VCC5 PVCC1 CT30 10UF/16V/X5R/1206-LF
G
A
40 RT8802_DVDEN RT8802_DVDEN D11 C145 L7
0603 10uF FDD8780-8.5mOHM-TO-252-LF 0.47uH/38A/0.87mOHM/DIP-LF
S
LL4148/150MA-LF PHASE1 1 2
K
VCC12A R649 2
D
BOOT1
2
4.7-0805-LF 1UF/X7R/16V-LF Q38 Q37
RT8802-Pin.40,32: V1P2_FSBVTT VCC5 C130 G G R251 XTR3 XTR4
R17 8 0603 2.2-0805-LF xTRACE10 xTRACE10
VIDSEL VID[7] Table 9.09K-1%-LF 5V 1UF/X7R/16V-LF
1
S
S
VTT x VR11 7,33 CPU_VTT_PWRGD R67 LF C462 C115
GND x VR10.x 0-LF R63 R76 0603 1UF/X7R/16V-LF 1 R737 1000PF/X7R/50V/0402-LF
UG1
0603
VDD NC K8 x1K-LF 4.7-0805-LF 0-0805-LF 0603 R54 C21
VDD GND K8_M2 24 FDD8796-5.7mOHM-TO-252-LF 680-LF 1UF/X7R/16V-LF
PHASE1
1
C496 C464 R16 VCC3 VCCP FDD8796-5.7mOHM-TO-252-LF ISP1 R55 x0-LF

1K-1%-LF 23
LG1
1
0402 PWM3 7 ISN1 ISN1_R
C35 PWM2 PWMIN3 VCC12A R9 680-LF
5
2
VCCP PWMIN2 VIN
0603
BAT54C PWM1 4 R105
4.7K 0.1UF/X7R/16V/0402-LF PWMIN1 4.7-0805-LF C451 0.1UF/X7R/16V/0402-LF
21
2
Layout near choke x1UF/X7R/16V-LF PVCC2
1 2 Near RT8802
A
C x0.1UF/X7R/16V/0402-LF D16 C42 Q31 C98 1UF/X7R/16V-LF C
31
D
1
1206
U2 0603 10uF
1
CT11 C450 BC497 12 26 PWM1 LL4148/150MA-LF G CT39 10UF/16V/X5R/1206-LF
VR_Enable/VTT
VDD
K
XTR2 XTR1 DVD PWM1 ISN1 L6
31 CPU_VLD 2 VR_Ready ISN1 18 BOOT2 16
0402 xTRACE10 xTRACE10 8,38 CPU_VIDSEL 40 25 ISP1 1UF/X7R/16V-LF FDD8780-8.5mOHM-TO-252-LF 0.47uH/38A/0.87mOHM/DIP-LF
S
VID_SEL ISP1 C141 PHASE2
SIO_VID7 32 1 2
2
VID7 0603
SIO_VID6 33
D
VID6
2
10UF/X5R/6.3V/0805-LF form SIO SIO_VID5 34 27 PWM2 1UF/X7R/16V-LF Q33 Q34
x1UF/X7R/16V-LF VID5 PWM2 R199 XTR5 XTR6
38 SIO_VID[7..0] SIO_VID4 35 VID4 PWM4 29 VCC5 G G
0.1UF/X7R/16V/0402-LF SIO_VID3 36 19 ISN24 2.2-0805-LF xTRACE10 xTRACE10
VID3 ISN24 ISP2 R738
7,8,38 CPU_VID[7..0] SIO_VID2 37 24 17
1
S
S
VID2 ISP2 ISP4 R651 ISN24_R UG2 0-0805-LF C78
SIO_VID1 38 VID1 ISP4 22
R51 R46 SIO_VID0 39 0-0402-LF 19 1000PF/X7R/50V/0402-LF
VID0 PHASE2
0603
100-1%-LF x100-1%-LF 0603 R48 C19
1000PF/X7R/50V/0402-LF 20 FDD8796-5.7mOHM-TO-252-LF 680-LF 1UF/X7R/16V-LF
LG2
0603
0603
C18 R36 15K-1%-LF 5 28 PWM3 FDD8796-5.7mOHM-TO-252-LF ISP2 R49 x0-LF

C17 2200PF/X7R/16V/0402-LF COMP PWM3 VCC12A
PWM5 30 VCC5
0603
20 ISN35 R650 ISN24 ISN24_R

C16 47PF/NPO/50V/0402-LF ISN35 ISP3 4.7-0805-LF R8 680-LF
ISP3 23 PVCC3 15
VIN
0603
8 CPU_CORE_FB+ R78 VCCP_FB_P_R 4 FB 21 ISP5 R6 ISN35_R
A
20-1%-LF R37 1.47K-1%-LF ISP5 0-0402-LF D4 C463 C452 0.1UF/X7R/16V/0402-LF
1 2
C27 3 0603 10uF Q18 C48 1UF/X7R/16V-LF Near RT8802
D
FBRTN
1206
961213 ECR 0402 VCC5 7 HOT_SET LL4148/150MA-LF
K
2.2 -> 20ohm 0.1UF/X7R/16V/0402-LF R24 VOSS HOT_SET VR_FAN CT8 10UF/16V/X5R/1206-LF
14 VOSS VR_FAN 8 BOOT3 9 G
x10K-LF 9 VR_HOT 1UF/X7R/16V-LF L3
VR_HOT
GND_PAD
8 CPU_CORE_FB- R77 VCCP_FB_N_R VADJ = [(DCR*(Radj/Rcsn)]*Iout-total 10 TSEN C30 FDD8780-8.5mOHM-TO-252-LF 0.47uH/38A/0.87mOHM/DIP-LF
S
20-1%-LF R751 0-LF R14 TSEN PWM_FAN_SET 0603 PHASE3
15 ADJ FAN_SET 11 1 2
0603
C26 18.7K-1%-LF 13 RT 16 IOUT 1UF/X7R/16V-LF
D
IOUT
2
0402 C22 961213 ECR 6 SS 17 IMAX Q19 Q20
B 0.1UF/X7R/16V/0402-LF x1UF/X7R/16V-LF 22K -> 18.7K IMAX R108 XTR9 XTR8 B
3 NC G G
RT8802APQV-LF 6 10 R739 2.2-0805-LF xTRACE10 xTRACE10
41
RT8802A 0603C13 GND1 UG3 0-0805-LF

12
1
S
S
Ref. circuit R58 0.047UF/16V/0402-LF GND2 C40
13 GND3 PHASE3 11
update x169-1%-LF 18 1000PF/X7R/50V/0402-LF
2007.1.30 GND4
0603
25 14 0603 R38 C14
GND5 LG3 FDD8796-5.7mOHM-TO-252-LF 680-LF 1UF/X7R/16V-LF
C498 0402 R15 15K->20K FDD8796-5.7mOHM-TO-252-LF ISP3 R39 x0-LF
x0.1UF/X7R/16V/0402-LF 18.7K-1%-LF PWM Freq.
=205kHz ISN35 R7 ISN35_R
680-LF
0603
R13
453-1%-LF C453 0.1UF/X7R/16V/0402-LF
961213 ECR Non-Used Near RT8802 0 ohm VCCP Near RT8802
402 -> 453 ohm
Temperature detect Over Current Protection 0 ohm ISN1_R
VCC5 for VR_HOT/VR_FAN D1
A2
A1
0ohm R12 1) Total current OCP , BAT54C-LF
453-1%-LF 10K-LF R22 VR_FAN Triggered when VADJ > VTCOC. CRB be NC
0.1uF 10K-LF R23 VR_HOT => Iout(max)={Vtcoc / [DCR*(Radj/Rcsn) ]} 0 ISP2
K
=> Iout(max)= ______
120.8 A * 0.8= ____
97 A ISN1 R3 LF 147K-1%-LF 0 ISP4
0 ohm
PWM_FAN_SET R5 28K-1%-LF 2) Phase current OCP. ISN24 R20 LF 147K-1%-LF
TSEN =>Iphase(max)=(3/2)*(1/Ri-max)*(Rcsn/DCR) R30
LF
0603
(Pin-11) IOUT C1 R27 10K-LF =>Iphase(max)=____

64.5 A/Phase ISN35 R25 LF 147K-1%-LF 100-1%-LF
0.1UF/X7R/16V/0402-LF Near
RT-10ohm Hi-side
A MOSFET Rb Ra A
R35 0603C11 R18 R19 IMAX
(Pin-7) Quick response select: 0 ohm 10K-LF 1UF/X7R/16V-LF 12.1K-1%-LF 4.99K-1%-LF VIMAX = 1V
-GND :during Heavy to Light load transient 3.83K -> 4.99K ohm
-NC :Quick response selected. R2 0-LF IOUT
"VTCOC"
HOT_SET R26 x22K-LF Rc C9
RT-10ohm R1 0603x0.1UF/16V/0402-LF
0603
C10 2.37K-1%-LF Ri-max = Ra+Rb+Rc Title

x0.1UF/X7R/16V/0402-LF Near Hi-side MOSFET 2.26K -> 2.37K ohm Vtcoc = Rc/(Ra+Rb+Rc)
PWM RT8802 + RT9605
961213 ECR A3 I-N73V 0.2
5 4 3 2 1
5 4 3 2 1
CPU DECOUPLING
D
10uF/X5R/1206 D
Inside of CPU Socket VCCP CPU ADJ BUFFER

CT17 CT18 CT19 CT20 CT21 CT22
0805 0805 0805 0805 0805 0805
10UF/6.3V/X5R/1206-LF 10UF/6.3V/X5R/1206-LF
10UF/6.3V/X5R/1206-LF 10UF/6.3V/X5R/1206-LF
10UF/6.3V/X5R/1206-LF 10UF/6.3V/X5R/1206-LF
5VDUAL 3VDUAL
74LVC14 : VCC= 1.65 - 3.6V
VCCP 74HCT14: VCC= 4.5 - 5.5V
CT24 CT31 10uF/X5R/1206 10uF/X5R/1206

0805 0805 10uF/X5R/1206 10uF/X5R/1206
0.1uF
10UF/6.3V/X5R/1206-LF
10UF/6.3V/X5R/1206-LF
SN74LVC14
from SIO GPIO to CPU PWM
C VCCP C
VCORE_ADJ0 VCCP_ADJ0#
10uF/X5R/1206 10uF/X5R/1206 10uF/X5R/1206

10uF/X5R/1206 10uF/X5R/1206 10uF/X5R/1206 VCORE_ADJ1 VCCP_ADJ1#
SN74LVC14
SN74LVC14
SN74LVC14
10uF/X5R/1206
Outside of CPU Socket
VCCP
B B
10uF/X5R/1206 10uF/X5R/1206 10uF/X5R/1206

10uF/X5R/1206 10uF/X5R/1206 10uF/X5R/1206
VCCP
10uF/X5R/1206 10uF/X5R/1206 10uF/X5R/1206

10uF/X5R/1206 10uF/X5R/1206 10uF/X5R/1206
VCCP
A
10uF/X5R/1206 10uF/X5R/1206 10uF/X5R/1206 A
10uF/X5R/1206 10uF/X5R/1206 10uF/X5R/1206
Title
CPU DECOUPLING & ADJ BUFFER

A3 I-N73V 0.2
5 4 3 2 1
5 4 3 2 1
VCC5SB
3VDUAL VCC5SB
VCC12
near VDDMEM 5V_DUAL
U46 + CE43 # of E/C at 5V_DUAL
R683 APM4500K-N_8A-N_22m-LF 8X11.5
1000UF/6.3V/DIP-LF limit in 3pcs
LF
2.2K-LF
R740 P-ch S2 3 5VDUAL
LF
D 1K-LF 5VDUAL_FET_GATE R685 LF 330-LF 4 G2 D
C478 C479 4.3A D2 5

D2 6
D
80mOHM
ATX_PWROK
R686 0603 0805 7 + CE42
N-ch D1 8
LF
10K-LF VCC5 8X11.5
1000uF
Q97 Q85 EMPTY D1
28 PWRGD_PS G G 2 G1
2N7002-LF 2N7002-LF 1UF/16V-LF
S
from ATX x4.7UF/10V/0805-LF 8A 1000UF/6.3V/DIP-LF
22mOHM S1 1
VCC5SB VCC5
D
3VDUAL
VCC5 + CE44
R687 G
8X11.5
LF
1K-LF RN21-1 8 1 10K-8P4R-LF 1000UF/6.3V/DIP-LF
S
Q86 RN21-2 7 2 10K-8P4R-LF
FDD8780-8.5mOHM-TO-252-LF RN21-3 6 3 10K-8P4R-LF
D
S3# RN21-4 5 4 10K-8P4R-LF
near USB1/2
16,32,38 SLP_S3* G Q98 G Q99
2N7002-LF 2N7002-LF
S
from MCP73
C
3V_DUAL C
Q87
5VDUAL RC1117ST/SOT223-LF 3VDUAL
SOT223
I IN(I) OUT(O) O
ADJ(I)
Fix SevenTeam 750W Bug CT91 R1 CT92 CT93
0805 R692 0805 0805
10UF/Y5V/10V/0805-LF 1A 100-1%-LF
ALL_PWROK
G
ATX_PWROK SOT23
A1 LF 10UF/Y5V/10V/0805-LF
MCP_PWRGD 11,16
28 PWRGD_PS K x0 R694 10UF/Y5V/10V/0805-LF
A2 LF
CPU_VLD 29
D33 x0 R695 R2
xBAT54C VCCP_PWROK improves C482 R693 VOUT= [(R2/R1)+1]*1.25
ripple rejection x1UF/16V-LF 169-1%-LF = [(169/100)+1]*1.25
= 3.3625 V
R1,R2= 10 - 1Kohm
CPU_VLD_MCP
CPU_VLD_MCP 16 MCP_PWRGD 11,16
R534 x0-LF R513 0-LF
MCP55_PWRGD
VCC3
B VCC3 B
R524
4.7K-0402-LF R512
R510 R527 x4.7K-0402-LF VCC5SB V2P5_SB
VCC3 4.7K-0402-LF VCC3 x4.7K-0402-LF V2P5_VREF v0.2 BOM
D
Q58 C467 R660

R542 G 2N7002-LF R543 Q57 06031UF/16V-LF 200-1%-LF
4.7K-0402-LF 4.7K-0402-LF G x2N7002-LF 100->200 V2P5_VREF
S
D
R662
from CPU PWM PWRGD(VCC3) Q60 from MCP CORE PWRGD(VCC3) Q61 22-LF R663 0-LF
G 2N7002-LF G x2N7002-LF Q79 10->22
29 CPU_VLD 33 V1P2_CORE_PWRGD
2 SOP8 1 CT90 0603 C468
S
A1 K 10UF/Y5V/10V/0805-LF
3 A2 NC1 4 1UF/16V-LF
6 A3 NC2 5
7 A4 REF 8
TL431ACD-100mA-LF
100mA
D
SOP8-1_27
from ATX PWRGD(5VSB)
G Q65
28 PWRGD_PS
2N7002-LF
S
A A
Title
5V/3V_DUAL
A3 I-N73V 0.2
5 4 3 2 1
5 4 3 2 1
5VDUAL
DDRII MEMVDD
Q14
22AMP @1.8V DDRII VTT
S
5VDUAL DRVLO1 R136 GATE_L1 G FDD8780-8.5mOHM-TO-252-LF
2
D 1 0-0805-LF D
R4
C7 I_lim = (72uA * RISEN)/RDSON L4 VDDMEM 7AMP @ 1/2MEMVDD
D
= (72uA*3.01K)/8.5mohm = 25.49A 2.0UH/25A/3.3mOHM/Square-LF
4.7-0805-LF 1UF/16V-LF PH1 1 2
U1
1
1
2 W83320G-LF R73 CT51 BCT13 1 1 VDDMEM VDDMEM
1
1 14 ISEN1 3.01K-1%-LF ISEN1R C135 CE13 CE16
LDRV ISEN 1000uF/6.3V 3VDUAL
2 13
S
C6 VDDA1 VDD PGND DRVHI1 R64 GATE_H1 R103 0.1UF/16V/0402-LF
3 12 G
2
VDDA HDRV
0603
1UF/16V-LF 4 11 BOOTCORE1 0-0805-LF 2.2-0805-LF 2 2 C99
PWROK BOOT
1
5 10 Q10 10UF/Y5V/10V/0805-LF 1000UF/MBZ/6.3V/DIP-LF R236 C97
2 GND ISET REFINCORE1 C29 FDD8780-8.5mOHM-TO-252-LF 10UF/Y5V/10V/0805-LF 1000UF/MBZ/6.3V/DIP-LF 0603 1K-1%-LF 0.1UF/16V/0402-LF C101
6 9
D
SS REFIN U8
1
7 8 FB1 0.22UF/16V/0402-LF 06030.1UF/16V/0402-LF
COMP FB
1
C28 C41 0.1UF/16V/0402-LF 8
VIN
2
5VDUAL 5VDUAL 1000PF/X7R/50V/0402-LF 5VDUAL VREF2
VCTRL 6
1 COMP1 R10 100K-1%-LF A1 83310_VREF1 3 VREF1
1
C3 2200PF/X7R/16V/0402-LF 1UF/16V-LF K 5VDUAL_IN1 L1 1 VTTMEM
2
D2 2 A2 1 1 1.2uH/6A-SDIP3026LF CE39 3VDUAL
R682 C4 x2200PF/X7R/16V/0402-LF BAT54C CT10 CT2 1000UF/MBZ/6.3V/DIP-LF C103 5 BOOT_SEL VOUT 4
4.7K-0402-LF C5 R72 0805 0805 CE1 CE2 R246 1
0.1UF/16V/0402-LF 39.2K-1%-LF 961213 ECR 1000uF 2 0603 1K-1%-LF CE18
Layout 7
GND
GND
2 Cost down 2 2 ENABLE 1000UF/6.3V/DIP-LF
Freq.=200KHz*(1.19V/Rset)/24uA 10UF/Y5V/10V/0805-LF 1000UF/MBZ/6.3V/DIP-LF NEAR MCP73 0.1UF/16V/0402-LF
1
1.Rset=49.9K -> 200KHz x10UF/X5R/6.3V/0805-LF 1000UF/MBZ/6.3V/DIP-LF W83310DG-LF 2 1000uF/MBZ/10V
2
9
2.Rset=39.2K -> 252.98KHz
R71 4.7K-LF
VDDMEM_VREF
C C
2
1R59 21C20 2
x10K-LF x1UF/16V-LF
2 1
R69 R31 4.99K-1%-LF
x4.99K-1%-LF
1
V2P5_VREF
VCC5SB
DDRII VREF MCP73
VDDMEM R654 Power Sequence
_SEL[1:0] 715-1%-LF
3VDUAL to W83320G U49C U49D
0 0 2.10V (2.10671V) VDDMEM_VREF 3VDUAL C490 SN74HCT00-LF SN74HCT00-LF
VDDMEM_VREF 0.1UF/16V/0402-LF
0 1 2.00V (2.00678V) 9 12
28,33,38 W83627_PSON#
1 0 1.90V (1.88451V) 8 11
SOP14 SOP14
1 1 * 1.80V (1.80415V) R655 R656 R657 10 13
R658 R659 12.1K-1%-LF 5.11K-1%-LF 3.83K-1%-LF R706 U49A
14
4.7K-0402-LF SN74HCT00-LF U49B
4.7K-0402-LF Q76 1 SN74HCT00-LF
D
B S3# B
4.7K-0402-LF 2N7002-LF 3 4
SOP14
from SIO Q77 16,31,38 SLP_S3* 2 6
SOP14
G G 2N7002-LF 5
38 VDDMEM_SEL0
from MCP73
DDRII Enable
7
S
38 VDDMEM_SEL1 VCC5SB
3VDUAL
to VDDMEM Regulator
VDDMEM_VREF
R232 R707
D
4.7K-0402-LF x4.7K-0402-LF
S5#
Q90
G 2N7002-LF
16 SLP_S5*
R708 0-LF
S
from MCP73
0603 G
C491 Q91
S
x1UF/X7R/16V-LF x2N7002-LF
Reserved
S3 S5 PS_ON DDRREF_IN
A AC_ON H H H L A
S0 H H L H
S3 L H H H
S5 L L H L
Title
DDRII Power
A3 0.2
I-N73V
5 4 3 2 1
5 4 3 2 1
V1P2_CORE_SEL[1:0]
0 0 1.50V (1.488V) V2P5_VREF 5VDUAL 3VDUAL
0 1 1.45V (1.445V) VTT Regulator
1 0 1.40V (1.387V)
1 1 * 1.35V (1.350V) R665 MCP73 CORE VREF
1K-1%-LF
U45A R744 C181
MCP73 CORE AUX
D
8
LM358DR-LF 4.7K-LF
V1P2_AUX_VREF 3 0.1UF/16V/0402-LF V1P2_DUAL
+
V1P2_DUAL_DRV
D 3VDUAL 2
1 G
1.35V @ 25mA MAX D
S
-
Q46 VTT
R666 R667 R668 C471 C472 2N7002-LF
4
20K-1%-LF 8.25K-1%-LF 1.47K-1%-LF 0.1UF/16V/0402-LF 1000PF/X7R/50V/0402-LF V1P2_DUAL V1P2
R669 R670
4.7K-0402-LF 4.7K-0402-LF V1P2_DUAL_SEN R671
2K-1%-LF
1
Q80 Q81 VDDMEM
from SIO 2N7002-LF 2N7002-LF C74 CT88 BCT57 BCT58 BC179
38 V1P2_CORE_SEL0 G G
MCP73
2
S
S
V1P2_DUAL
10UF/Y5V/10V/0805-LF Regulator
Layout Near MCP73 1UF/16V-LF 10UF/Y5V/10V/0805-LF
38 V1P2_CORE_SEL1
10UF/Y5V/10V/0805-LF 0.1UF/16V/0402-LF VDDMEM
V1P2 Regulator Regulator
VDDMEM
V1P2_DUAL 5VDUAL
R661
1.8 - 2.1V MCP73 CORE
1K-1%-LF C475 CT76
U45B R745 0805
1.35V @16AMP
D
C 8 LM358DR-LF 4.7K-LF VCC5SB C
5 + C1P2_CORE PWRGD
2
7 V1P2_CORE_DRV G 0.1UF/16V/0402-LF V1P2_VDD_CORE @ 5.7A
6 10UF/Y5V/10V/0805-LF V1P2_PEX_VDD @ 2.25A
S
-
C469 Q78 V1P2_SATA_VDD @ 475 MA V1P2_CORE R673
0.1UF/16V/0402-LF C470 FDD8780-8.5mOHM-TO-252-LF V1P2_PLL @ 360MA 10K-0402-LF
4
1000PF/X7R/50V/0402-LF to MCP73
V1P2_CORE CPU_VTT @ 6A R675 V1P2_VLD_5V
V1P2_CORE_PWRGD 31
C 1
1.35 - 1.5V 4.7K-LF
D
V1P2_CORE_SEN R664
1
2K-1%-LF V1P2_VLD_RC B Q84 Q93
1 1 PMBS3904-LF G 2N7002-LF C473
D
1
C324 CT68 CE30 CE31 x0.1UF/16V/0402-LF
S
from SIO Q101 R676 0603
2
28,32,38 W83627_PSON# G 2N7002-LF x4.7K-LF C474
2 2 2
2
S
Layout Near MCP73 1000UF/6.3V/DIP-LF 1UF/16V-LF

10UF/Y5V/10V/0805-LF 1000UF/6.3V/DIP-LF
0.1UF/16V/0402-LF
V1P2_CORE
V2P5_VREF 5VDUAL
R652
1.35 - 1.5V CPU FSB VTT
B 3VDUAL 1K-1%-LF C154 CT52 10 AMPS @ 1.2V B
U50A R748
D
8
LM358DR-LF 4.7K-LF CPU.VTT @ 5.2A

CPUVTT_VREF 3 MCP73.V1P2_CPU_VTT @ 800mA
+
1
1 V1P2_FSBVTT_DRV G 0.1UF/16V/0402-LF
C200 R324 2 10UF/Y5V/10V/0805-LF
S
-
1
0.1UF/16V/0402-LF 10K-0402-LF Q43

R190 R653 C465 C466 FDD8780-8.5mOHM-TO-252-LF V1P2_FSBVTT
2
5.11K-1%-LF 931-1%-LF 1UF/16V-LF 1000PF/X7R/50V/0402-LF 1.2V

If CPU_VTT_SEL used,
2
- VTT_SEL= 1, VTT= 1.2V v0 .2

1
- VTT_SEL= 0, VTT= 1.1V 0.1uF->1uF V1P2_FSBVTT_SEN R193 C68 CT54 BCT15 1

C
2K-1%-LF C69 0603C155 CE21

CPU_VTT_SEL R279
LF B Q102 1UF/16V-LF 961213 ECR 1000UF/6.3V/DIP-LF
1K-LF G 2N7002-LF Cost down
2
from CPU Q49 Layout Near CPU 2

E
PMBS3904-LF v0 .2 0.01UF/16V/0402-LF x10UF/Y5V/10V/0805-LF

0.1UF/16V/0402-LF x10UF/X5R/6.3V/0805-LF
CPU_VTT_SEL_V1P1
to MCP73
VCC5SB
3VDUAL CPUVTT PWRGD

MCP73
Power Sequence R98
R66 10K-0402-LF to CPU
A
3VDUAL R672 1K-LF to PWM (VR_Enable) A
4.7K-0402-LF
CPU_VTT_PWRGD 7,29
C
R696 B Q12
D
from MCP73 x4.7K-0402-LF R61 0603 G 2N7002-LF C34

(3V_DUAL) Q82 10K-LF C31 Q9 x0.1UF/16V/0402-LF
E
G G 2N7002-LF 1UF/16V-LF PMBS3904-LF

16 CPUVDD_EN
2
Q48 Title
S
2N7002-LF
MCP73 Core & CPU_VTT
A3 0.2
I-N73V
5 4 3 2 1
5 4 3 2 1
88E3018 LAN PHY

88E1116: 1.8V_DUAL / 500mA max
1.8V @ 500mA MAX 88E3018: 2.5V_DUAL / ?
LAYOUT
please near LAN PHY 2.5V @ 500mA MAX
5VDUAL Q92 V2P5_DUAL_LAN
BUF0_25MHZ 0 ohm RC1117ST/SOT223-LF V1P8_DUAL_LAN
16 BUF0_25MHZ
D 3VDUAL SOT223 D
LAN_XTAL2_1 I O
IN(I) OUT(O)
ADJ(I)
C449 RSET Pin33(RSET): R1
1
10PF/NPO/50V/0402-LF XTAL -88E1116: 4.99K R326 BC10 BCT11 BCT10
for EMI 25MHz -88E3018: 2K CT60 1A 0805
G
10UF/Y5V/10V/0805-LF 121-1%-LF stuffed for
3VDUAL 33pF R395 88E1116 only
2
C235 2K-1%-LF
x33PF/NPO/50V-LF 1UF/16V-LF
R2 x4.7UF/10V/0805-LF
R396 improves C202 R333 x10UF/X5R/6.3V/0805-LF
4.7K-LF Reserve ripple rejection x1UF/16V-LF
1.5K->4.7K 121-1%-LF
v0.2 BOM VOUT= [(R2/R1)+1]*1.25
RGMII0_MDIO deleted a).R1=121,R2=56.2 -> Vout=1.83V
15 RGMII0_MDIO
1116_V1P2_1 RGMII0_MDC FB51 R1= 121ohm fixed b).R1=121,R2=121 -> Vout=2.50V
15 RGMII0_MDC
x30OHM/3A/40mOHM-LF R2= 10 - 1Kohm
3VDUAL
1
1
BCT6 C208 C210 BCT7 BCT4
stuffed for Pin16
88E1116 only -88E1116: stuffed
R728 x0-LF -88E3018: non-stuff FB14 V2P5_DUAL_LAN
2
2
30OHM/3A/40mOHM-LF
4.7UF/10V/0805-LF 0.1UF/16V/0402-LF x10UF/X5R/6.3V/0805-LF
3VDUAL 0.1UF/16V/0402-LF x10UF/X5R/6.3V/0805-LF
1
C234 C233 C205 CT65
C CT67 0805 C
1
C236C0402 C224 C221 C209 x4.7UF/10V/0805-LF 0.1UF/16V/0402-LF 4.7UF/10V/0805-LF
2
X5R
10% VREF=VDDO / 2 961213 ECR 0.1UF/16V/0402-LF
2
C0402
X5R
C0402
X5R
C0402
X5R 3VDUAL R361 1K-1%-LF Cost down 0.01UF/16V/0402-LF
16V 16V 16V
R366 1K-1%-LF
13
47
40
48
45
44
43
42
41
39
38
36
35
33
37
34
16
10% 10% 10%
2
5
U17 FB12
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF 1 2 7 30OHM/3A/40mOHM-LF
RSET
MDIO
TDO
TDI
XTAL2
XTAL1
DVDD
DVDD
DVDD
DVDD
MDC
TCK
TMS
TS_HSDACN
TS_HSDACP
AVDDC
AVDDC
AVDDX
0.1UF/16V/0402-LF 0.1UF/16V/0402-LF BC493 0.1UF/16V/0402-LF VDDO
46 VDDO
1
52 CT63 C215 C226
MCP73 CRB no this VDDOR
56 VDDOR TS_PT 32
PLACE NEAR PHY 57 29
RGMII0_RXCTL R389 0-0402-LF VREF AVDD 4.7UF/10V/0805-LF
28
2
15 RGMII0_RXCTL AVDD BR729 0-LF 0.1UF/16V/0402-LF
RGMII0_RXCTL_R 49 RX_CTRL EPAD-VSS AVDD 27
RGMII0_RXD0 R388 0-0402-LF RGMII0_RXD0_R 50 22 0.01UF/16V/0402-LF
RGMII0_RXD[3..0] RGMII0_RXD1 R386 0-0402-LF RXD[0] AVDD
15 RGMII0_RXD[3..0]
RGMII0_RXD1_R 51 RXD[1] AVDD 21
RGMII0_RXD2 R376 0-0402-LF to transformer
RGMII0_RXD3 R374 0-0402-LF
RGMII0_RXD2_R
RGMII0_RXD3_R
54
55
RXD[2] MARVELL 31 LAN0_MDI0+
RXD[3] MDIP[0] LAN0_MDI0+ 37
RGMII0_RXC R377 0-0402-LF RGMII0_RXC_R 53 30 LAN0_MDI0-
15 RGMII0_RXC RX_CLK MDIN[0] LAN0_MDI0- 37
88E1116(RGMII) 26 LAN0_MDI1+
15 RGMII0_TXC MDIP[1] LAN0_MDI1+ 37
RGMII0_TXC 60 25 LAN0_MDI1-
RGMII0_TXD0 TX_CLK 88E3018(MII+RGMII) MDIN[1] LAN0_MDI2+
LAN0_MDI1- 37
58 TXD[0] MDIP[2] 24 LAN0_MDI2+ 37
RGMII0_TXD[3..0] RGMII0_TXD1 59 23 LAN0_MDI2-
15 RGMII0_TXD[3..0] TXD[1] MDIN[2]/MII_COL LAN0_MDI2- 37
RGMII0_TXD2 61 88E3018-10/100PHY-LF 20 LAN0_MDI3+
TXD[2] MDIP[3]/MII_CRS LAN0_MDI3+ 37
RGMII0_TXD3 62 19 LAN0_MDI3-
TXD[3] MDIN[3]/MII_RXER LAN0_MDI3- 37
RGMII0_TXCTL 63 18
15 RGMII0_TXCTL TX_CTRL NC
CTRL_REG18 17
RX RGMII signals R730 0-0402-LF
DIS_REG12
EPAD-VSS
CONFIG[0]
CONFIG[1]
CONFIG[2]
CONFIG[3]
CONFIG[4]
R357 R360 R370 R372 R375 R378 R387 R393
B must be used 50 ohm B
RESET#
Hardware configuration: Pin18
AVDDR
AVDDR
TRSTn
LED[0]
LED[1]
LED[2]
impedance trace in -88E1116: floating x49.9-1%-0402-LF x49.9-1%-0402-LF 49.9-1%-0402-LF 49.9-1%-0402-LF
Two bits mapping: Configuration mapping: pcb layout. -88E3018: stuffed x49.9-1%-0402-LF x49.9-1%-0402-LF 49.9-1%-0402-LF 49.9-1%-0402-LF
Pin Bit 1,0 Pin Bit 1 Bit 0 LAN0_MDI3_C LAN0_MDI2_C LAN0_MDI1_C LAN0_MDI0_C
65
64
1
2
3
4
6
8
9
10
11
12
14
15
VSS 00 CONFIG[0] PHYAD[1] PHYAD[0] 01 Pin17 (CTRL_REG18/25)
LED[0] 01 CONFIG[1] PHYAD[3] PHYAD[2] 00 -Float: 18/25 regulator isn't used C211 C214 C225 C238
2 1 2 1 2 1 2 1
LED[1] 10 CONFIG[2] ENA_XC PHYAD[4] 10
x0.01UF/X7R/16V/0402-LF 0.01UF/16V/0402-LF
1
LED[2] Unused CONFIG[3] RGMII_TX RGMII_RX 00

VDDO 11 CONFIG[4] ANEG[1] ANEG[0] 11 LAN0_LED_0 R353 0-0402-LF R349 Pin12 DIS_REG12: PLACE RC NETWORKS x0.01UF/X7R/16V/0402-LF 0.01UF/16V/0402-LF
-GNDΚ disable CLOSE TO PHY
LAN0_LED_1 4.7K-0402-LF -VDDO Genable
Configuration definition:
LAN0_LED_2 R731 0-0402-LF stuffed for 88E1116 (RGMII) only.
2
Bits Definition R732 x0-0402-LF V2P5_DUAL_LAN

PHYAD[4:0] PHY Address
RGMII_TX *0 = TX clock not delayed 88E1116: connect to GND
1 = TX clock delayed 3VDUAL 88E3108: connect to LED2 form MCP73
RGMII_RX *0 = RX clock when data transtions C207 C206 CT66 BR733 0-0402-LF MII_RX_ER 15
1
1 = RX clock when data stable 1 BR734 0-0402-LF MII_CRS 15

ENA_XC 0 = Disable Auto-Crossover CRB add this BR735 0-0402-LF MII_COL 15
37 LAN0_LED_0
*1 = Enable Auto-Crossover 10K 0.1UF/16V/0402-LF BR736 0-0402-LF 3VDUAL
37 LAN0_LED_1
ANEG[1:0] 00 = 1000BASE-T full-duplex only 3VDUAL 0.01UF/16V/0402-LF
37 LAN0_LED_2
2
01 = 1000BASE-T full-duplex and Half-duplex only 4.7UF/10V/0805-LF stuffed for 88E3018 (MII) only
1
10 = all capabilities except 1000BASE-T half-duplex 15 RGMII0_INTR* 1 2

*11 = all capabilities R340 x22-LF
2
RGMII_RESET* R351
A
15 RGMII_RESET*
R350
10K-0402-LF Colay with 88E1116 and 88E3018 A
2
4.7K-0402-LF
RGMII0_PWRDWN* 15
PHY HW DEFALT CONFIG
1
CONFIG 0-1 PHY ADDRESS = 00001
CONFIG 2 ENABLE AUTO-CROSSOVER

BIOS Title
CONFIG 3 RXCLK TRANSMITS W/DATA PROGRAM LED TO MODE 3
TXCLK DELAY = DISABLED COMA* MUST BE PROGRAMMED BEFORE RESET 88E3108_10/100 LAN PHY
A3 0.2
I-N73V
5 4 3 2 1
5 4 3 2 1
FB
VCC5A NORMAL VOLTAGE = 4.7V (2%) GND GND_AUDIO
PIN 47 AUDIO1 AUDIO2
RT9179 (Vout Adjustable) : Vout = 1.75 x (1+R1/R2) = 1.75 x (1+3k/1k) = 4.7V
RT9167 (Vout Fixed) VCC5A VCC3 50 mils gap
Q54
VCC5 FB35 1 5 FB32 30OHM/3A/40mOHM-LF pin 12 GND_EMI_AUDIO

x30OHM/3A/40mOHM-LF VIN VOUT L0603
ALC88X CODEC
C318 C271 C321
VCC5SB FB34 C353 2 R1 R497 C263 CT95 C328 CT96 0402 0402 0805 GND
30OHM/3A/40mOHM-LF 06031UF/16V-LF GND
Y5V
0402 0805 0402 0805 For PCB Layout copper
5VDUAL 3.01K-1%-LF GND_AUDIO CGND
16V 3 4 C1 0.1UF/16V/0402-LF area and placement
SHDN# BYPASS 1
D 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF D
RT9179-LF R2 R503 10UF/Y5V/10V/0805-LF 10UF/Y5V/10V/0805-LF 4.7UF/10V/0805-LF
BR12
1 22-LF
2
15 HDA_SDIN_0 xFB
R0603 5% 1K-1%-LF
Layout close ALC88X-Pin25 Layout close ALC88X-Pin25
15 HDA_RST* 2
BR15 10K-0402-LF 15 HDA_SYNC FRONT_OUT_L
CE32 100UF/25V/DIP-LF ALC880/882/883 use the same VREF (VREF_MIC2_L)
+ +
15 HDA_SDOUT ALC885 use the independent VREF(VREF_MIC2_L and R)
nVidia CRB EMPTY FRONT_OUT_R
HDA_SDIN_0_R CE33 100UF/25V/DIP-LF
FRONT PANEL AUDIO
08050805080508050805080508050805
RT9167 => R1:NC; R2:NC; C1:0.1uF LINE_IN_L 4.7K
R440 0-0402-LF HDA_BITCLK_R RT9179 => R1:3.01K_1%; R2:1K_1%; C1:0.1uF CT97 10UF/Y5V/10V/0805-LF
15 HDA_BITCLK VCC3
LINE_IN_R 2 K2 R483
C274 FP_OUT_L CE28 100UF/25V/DIP-LF CT98 10UF/Y5V/10V/0805-LF VREF_MIC2_L A 4.7K-0402-LF
+ +
CRB 0402 25V MIC1_L K1 R484
1
no this 22PF/NPO/50V/0402-LF FP_OUT_R CE27 100UF/25V/DIP-LF U18 CT99 10UF/Y5V/10V/0805-LF D23 4.7K-0402-LF R462
25V MIC1_R VREF_MIC2_R BAT54A 4.7K-0402-LF
FP-AUDIO1
11 RESET# (I) FRONT_OUT_L (B) 35
060306030603
CD_L C250 1UF/16V-LF 10 36 CT100 10UF/Y5V/10V/0805-LF 4.7K
Y5V 16V SYNC (I) FRONT_OUT_R (B) CENTER_OUT
5 SDOUT (I) LINE_IN1_L (B) 23 16 ACZ_DET 4 AVCC
CD_REF C249 1UF/16V-LF 8 24 CT101 x10UF/Y5V/10V/0805-LF ALC88x
Y5V 16V SDIN (O) LINE_IN1_R (B) LFE_OUT stuffed only MIC2_L
6 BITCLK (I) MIC1_L (B) 21 1 MIC2_L
CD _R C253 1UF/16V-LF 14 22 CT102 x10UF/Y5V/10V/0805-LF MIC2_R 3
Y5V 16V LINE_IN2_L (B) MIC1_R (B) REARSURR_OUT_L MIC2_R 1 2
15 LINE_IN2_R (B) CENTER_OUT (O) 43
06030603
MIC2_L C252 1UF/16V-LF 18 44 CT103 x10UF/Y5V/10V/0805-LF C340 C345 FP_OUT_R 5

Y5V 16V CD_L (I) LFE_OUT (O) REARSURR_OUT_R 0402 0402 JD_MIC2 FRO_R
19 CD_GND (I) SURR_L (B) 39 6 MIC2_JD
MIC2_R C251 1UF/16V-LF 20 41 CT104 x10UF/Y5V/10V/0805-LF
Y5V 16V CD_R (I) SURR_R (B) SENSE_B FP_OUT_L 9 10
16 MIC2_L (B) SENSE_B (I) 34 9 FRO_L
SENSE_A CRB stuff 100uF EXT_VOL_CTRL R449 JD_LINEIN2
17 MIC2_R (B) DCVOL (I) 33 VCC5A 10 LINE2_JD
13 40 JD REF R459 L F 1% 20K-1%-0402-LF 10K-0402-LF x4700PF/X7R/16V/0402-LF
SENSE_A (I) JDREF
08050805
SURR_OUT_L CT105 x10UF/Y5V/10V/0805-LF 37 48 SPDIFO ALC888 :NC x4700PF/X7R/16V/0402-LF 7

C ALC88x stuffed only DACREF (O) SPDIFO (O) SPDIFI F_IO_SEN C
45 SIDESURR_L (O) SPDIFI/EAPD (B) 47 2 AGND
0805
SURR_OUT_R CT106 x10UF/Y5V/10V/0805-LF 46 27 CT107 10UF/Y5V/10V/0805-LF
SIDESURR_R (O) VREF (O) VREF_MIC1_L NC
12 PC_BEEP (I) MIC1_VREFO_L (O) 28
0603
15,28 SPEAKER R432 PC_BEEP C267 1UF/16V-LF 2 29 VREF_MIC2_R NC HEADER-5*2 PIN-LF

10K-0402-LF Y5V 16V GPIO0 (B) LINE_IN1_VREFO (O) VREF_MIC2_L NC Don't stuff this bead. COH2X5P-2_54-CP8
3 GPIO1 (B) MIC2_VREFO (O) 30
4 31 NC VREF Decouple Caps. Or it will degrade audio quality.
0402 R435 GND1 (P) LINE_IN2_VREFO (O) VREF_MIC1_R NC 1) Place close to codec
7 GND2 (P) MIC1_VREFO_R (O) 32
C265 1K-0402-LFVCC3 R447 x1K-0402-LF 1 2) Signal trace routed through if EMI issue happened,
0.1UF/16V/0402-LF VCC3_1 (P) or beneath is forbidden. change be a Cap.
VCC3_2 (P) 9 VCC3
R442 x1K-0402-LF 26 25
AGND1 (P) AVCC_1 (P) Bead/3A
42 AGND2 (P) AVCC_2 (P) 38 VCC5A
If GPIO no used,
PhoneJack Sense leave them floating
LQFP48-0_5
ALC662-LF EMI del
C325
JD_FRONT R463 5.11K-1%-0402-LF SENSE_A ALC888 / 888DD / 888H-GR 0402 v0 .2
CT73 -GR: for Green (leadfree) 0.1UF/16V/0402-LF
JD_LINEIN1 R461 10K-1%-0402-LF 0805 -DD: Dolby Digital Live+DTS Connect Bead/3A
10UF/Y5V/10V/0805-LF (real-time encoding) VCC5 SPDIFO1 CD1
JD_MIC1 R470 20K-1%-0402-LF -H: Dolby Home Theater If not used, FB19
Please stuff 0.1uF 30OHM/3A/40mOHM-LF 1 1 CD_L
1 1 L(O)
JD_REARSURR R472 39.2K-1%-0402-LF 2 CD_REF
SPDIFO GND1(P)
3 3 GND2(P) 3
JD_SURR R478 5.11K-1%-0402-LF SENSE_B 4 4 CD _R
4 4 R(O)
JD_CENTER R477 10K-1%-0402-LF HDR-4*1-BLACK CD-WAFER-4*1PIN-LF
COH1X4P-2_54-CP2 COB1X4P-2_54-CD
JD_LINEIN2 R725 39.2K-1%-0402-LF
Phone Jack:
JD_MIC2 R726 20K-1%-0402-LF -ALC88X(6 Jacks) :stuffed
B VCC5 B
-ALC662 (3 Jacks): non-stuffed
v0.2 BOM
GND_AUDIO GND_EMI_AUDIO GND_AUDIO GND_EMI_AUDIO
AUDIO1B AUDIO1A SPDIFO
LINE_IN_L FB20 150OHM/400MA/150mOHM-LF A1 CENTER_OUT FB27 150OHM/400MA/150mOHM-LF D1 OPT-OUT1
LINEIN_L (B) CENTER (I)
A2 NC1 D2 NC1
JD_LINEIN1 A3 JD_CENTER D3
LINE_IN_R FB21 150OHM/400MA/150mOHM-LF NC2 LFE_OUT FB30 150OHM/400MA/150mOHM-LF NC2
A4 LINEIN_R (B) BLUE D4 BASS (I) ORANGE
C264 C262 C323 C316
G R E EN BLA CK
0402 0402 0402 0402 7
1000PF/X7R/50V/0402-LF 1000PF/X7R/50V/0402-LF HOLE7
P INK 8 HOLE8 GR AY
1000PF/X7R/50V/0402-LF 1000PF/X7R/50V/0402-LF VCC5
FRONT_OUT_L FB31 150OHM/400MA/150mOHM-LF B1 REARSURR_OUT_L FB26 150OHM/400MA/150mOHM-LF E1

FRONT_L (I) C1 RSR_L (I) F1 SPDIFI
B2 NC3 A1 B1 E2 NC3 D1 E1
JD_FRONT B3 C2 JD_REARSURR E3 F2
NC4 A2 B2 NC4 D2 E2
FRONT_OUT_R FB22 150OHM/400MA/150mOHM-LF B4 C0 REARSURR_OUT_RFB28 150OHM/400MA/150mOHM-LF E4 F0
FRONT_R (I) A3 B3 RSR_R (I) D3 E3
C3 F3 OPT-IN1
A4 B4 D4 E4
C268 C326 C4 C317 C310 F4
0402 0402 4 0402 0402 1
VREF_MIC1_L R423 4.7K-0402-LF 1000PF/X7R/50V/0402-LF HOLE4 1000PF/X7R/50V/0402-LF HOLE1
5 HOLE5 2 HOLE2
1000PF/X7R/50V/0402-LF 6 1000PF/X7R/50V/0402-LF 3
HOLE6 A1,B1,C1 HOLE3 D1,E1,F1
VREF_MIC1_R R448 4.7K-0402-LF
A2,B2,C2 D2,E2,F2
MIC1_L R422 FB23 150OHM/400MA/150mOHM-LF C1 SURR_OUT_L FB25 150OHM/400MA/150mOHM-LF F1
MIC_REF (B) A3,B3,C3 SR_L (I) D3,E3,F3
1K-0402-LF C2 F2
A NC5 A4,B4,C4 NC5 D4,E4,F4 A
JD_MIC1 C3 JD_SURR F3 refer to "abit-ALC88X REF DESIGN_Rev 0.13"
NC6 C0 NC6 F0
MIC1_R R437 FB24 150OHM/400MA/150mOHM-LF C4 SURR_OUT_R FB29 150OHM/400MA/150mOHM-LF F4
1K-0402-LF MIC_IN (I) SR_R (I)
C258 C246 C273 C270 C0 GND C320 C276 F0 GND
0402 0402 0402 0402 0402 0402
1000PF/X7R/50V/0402-LF CONN-AUDIO-LF x1000PF/X7R/50V/0402-LF CONN-AUDIO-LF
1000PF/X7R/50V/0402-LF CON26P-PHONEX6_P8 x1000PF/X7R/50V/0402-LF CON26P-PHONEX6_P8
footprint be 3-Jacks x2pcs footprint be 3-Jacks x2pcs Title
x4700PF/X7R/16V/0402-LF colay with 6-Jacks colay with 6-Jacks
x4700PF/X7R/16V/0402-LF HD CODEC (ALC662,88x)
A3 0.2
I-N73V
5 4 3 2 1
5 4 3 2 1
IDE1
IDE_DATA_P[15..0]
14 IDE_DATA_P[15..0]
IDE1
COB2X20P-2_54-CP20
D D
IDE_HDR
R433
7 7 8
1 2 ˜˗˘˲˗˔˧˔˲ˣˊ ˜˗˘˲˗˔˧˔˲ˣˊ
3 DD7 DD8 4 ˜˗˘˲˗˔˧˔˲ˣˋ
6 9
R0402 5% ˜˗˘˲˗˔˧˔˲ˣˉ
5 DD6 DD9 6 ˜˗˘˲˗˔˧˔˲ˣˌ
VCC3 VCC3 10K-0402-LF 5 10

˜˗˘˲˗˔˧˔˲ˣˈ
7 DD5 DD10 8 ˜˗˘˲˗˔˧˔˲ˣ˄˃
EMPTY 4 11
˜˗˘˲˗˔˧˔˲ˣˇ
9 DD4 DD11 10 ˜˗˘˲˗˔˧˔˲ˣ˄˄
3 12
R373
˜˗˘˲˗˔˧˔˲ˣˆ
11 DD3 DD12 12 ˜˗˘˲˗˔˧˔˲ˣ˄˅
2 13
R383 1 2 ˜˗˘˲˗˔˧˔˲ˣ˅
13 DD2 DD13 14 ˜˗˘˲˗˔˧˔˲ˣ˄ˆ
1 14
1 2 R0603 5% ˜˗˘˲˗˔˧˔˲ˣ˄
15 DD1 DD14 16 ˜˗˘˲˗˔˧˔˲ˣ˄ˇ
x10K-LF 0 15
R0402 5% ˜˗˘˲˗˔˧˔˲ˣ˃
17 DD0 DD15 18 ˜˗˘˲˗˔˧˔˲ˣ˄ˈ
13 PCI_RST_IDE*
PCI_RST_IDE* 4.7K-0402-LF 1 RESET*
CSEL 28
IDE_DREQ_P 21 DMARQ
14 IDE_DREQ_P IDE_IOW_P*
14 IDE_IOW_P* 23 DIOW*
14 IDE_IOR_P*
IDE_IOR_P* 25 DIOR* PDIAG* 34 CABLE_DET_P
CABLE_DET_P 14
IDE_RDY_P 27 IORDY DA2 36
14 IDE_RDY_P IDE_DACK_P*
14 IDE_DACK_P* 29 DMACK* CS1* 38
2
IDE_INTR_P 31 INTRQ
14 IDE_INTR_P IDE_ADDR_P1
14 IDE_ADDR_P1 33 DA1 GND 2 R358
14 IDE_ADDR_P0
IDE_ADDR_P0 35 DA0 GND 19 15K-LF
5%
14 IDE_CS1_P*
IDE_CS1_P* 37 CS0* GND 22 R0603
IDE_HDLED_P* 39 DASP* GND 24

28 IDE_HDLED_P*
26
1
GND
R404 R368 GND 30
1 2 1 2 32 NC GND 40
R0402 5% R0402 5%
4.7K-0402-LF 10K-0402-LF I267

5.6k ohm -> 4.7k ohm IDE_HDR-Black-LF
C
14 IDE_CS3_P*
IDE_CS3_P* C
14 IDE_ADDR_P2
IDE_ADDR_P2
B B
A A
Title
IDE 1
A3 I-N73V 0.2
5 4 3 2 1
5 4 3 2 1
FP_USB1
USB1 (USB+1394) F8 1 R608 1K-LF
2 USB_OC45*
USB_OC45* 15
2
1.6A/9V/POLYSWITCH-LF
2 1 FB42 R611
2.2K-LF
1
30OHM/3A/40mOHM-LF C437 C438
C426 470PF/X7R/16V/0402-LF
1000PF/X7R/50V/0402-LF 0.1UF/16V/0402-LF
1
C440
FP-USB
2
0.1UF/16V/0402-LF
TPA0- TPA0+
D TPB0- TPB0+ D
L14 USB1VCC
1394VCC1
1
USB1
5
Header USBV0 1
3
FP-USB1
VREG_USBn VREG_USBn+1 2
4
USBV0
VCC0 VCC1 15 USB_4* USBPnN USBPn+1N USB_5* 15
1 2 USB_1N_C 2 6 USB_0N_C 5 6
15 USB_1* DATA0- DATA1- 15 USB_4 USBPnP USBPn+1P USB_5 15
USB_1P_C 3 7 USB_0P_C USBG0 7 8
DATA0+ DATA1+ GNDn GNDn+1
15 USB_1 4 3 4 GND0 GND1 8 9 NO PIN9 USB_OC 10
9 GND2 GND4 11
xChoke-USB 10 12 USB2P_HEADER5X2-LF
GND3 GND5
L13 USBCON-LF
15 USB_0* 1 2
USB_0N_C FP_USB2 1 R609 1K-LF
2 USB_OC67*
USB_OC67* 15
2
4 3 USB_0P_C USB1GND F9
15 USB_0
2 1 FB43 R614
xChoke-USB FB9 2.2K-LF
1
30OHM/3A/40mOHM-LF 1.6A/9V/POLYSWITCH-LF 30OHM/3A/40mOHM-LF C436 C435
FB47 C431 470PF/X7R/16V/0402-LF
USBPWR1 x30OHM/3A/40mOHM-LF 1000PF/X7R/50V/0402-LF 0.1UF/16V/0402-LF
1
F4 C441
2
2 1 VCCUSB1 C191 0.1UF/16V/0402-LF
0.1UF/16V/0402-LF
1.6A/9V/POLYSWITCH-LF 5VDUAL R621 FP_USB1
0-1206-LF FP_USB2 FP-USB2
R317 FB10 R619 USBV2 USBV2
15 USB_OC01* 1 2 VCC5 FP_USB3 1 VREG_USBn VREG_USBn+1 2
30OHM/3A/40mOHM-LF x0-1206-LF 3 4
15 USB_7* USBPnN USBPn+1N USB_6* 15
2
1
1K-LF C195
15 USB_7 5 USBPnP USBPn+1P 6 USB_6 15
C192 470PF/X7R/16V/0402-LF CE37 USBG2 7 8
R318 1000uF 1000UF/6.3V/DIP-LF GNDn GNDn+1
9 NO PIN9 USB_OC 10
C 1000PF/X7R/50V/0402-LF 2.2K-LF C198 2 C
0.1UF/16V/0402-LF USB2P_HEADER5X2-LF
1
FP_USB3 USB_OC89*
USB_OC89* 15
5VDUAL R749 USBPWR1

0-1206-LF
VCC5 R750 USBPWR2
x0-1206-LF
CE22
1000UF/6.3V/DIP-LF
USBV3 USBV3
15 USB_9* USB_8* 15
USB Header
USB2 (USB+RJ45) 15 USB_9
USBG3
USB_8 15
B B
LAN1_1000- 1R339 22-LF
2 LAN0_LED_0 34
USB2 RJ45USB-10/100-LF LAN1_100- 1R336 22-LF
2 LAN0_LED_1 34
L14
ORANGE
FB17 USB2.L10:
L13 30OHM/3A/40mOHM-LF V2P5_DUAL_LAN -RGMII :GND USB2.L6,7,8,9:
CG7 CG1 GLEDP14 GREEN -MII: LAN_PHY_VDDIO -RGMII : stuffed 6.8pF
L15 USB2VCC U5 L10 R381 x0-LF -MII: non-stuffed
VCCP0 CG5 CG3 GLEDN13 GND DATA LOSS SOLUTION
15 USB_2* 1 2 U6 USBP0N
U7 L9 LAN0_MDI3-
USBP0P VCCP0 VCCP1 GND TRD3- LAN0_MDI3- 34
4 3 U8 L8 LAN0_MDI3+
15 USB_2 GNDP0 TRD3- TRD3+ LAN0_MDI3+ 34
1 2 C212
xChoke-USB USBP0N USBP1N TRD3+ L7 x6.8PF/NPO/50V/0402-LF LAN0_MDI2-
TRD2- TRD2- LAN0_MDI2- 34
L6 LAN0_MDI2+
USBP0P USBP1P TRD2+ TRD2+ LAN0_MDI2+ 34
L16 USB2VCC U1 1 2 C220 GBit
VCCP1 TRD1- x6.8PF/NPO/50V/0402-LF LAN0_MDI1-
15 USB_3* 1 2 U2 USBP1N GNDP0 TRD1- L5 LAN0_MDI1- 34
U3 GNDP1 TRD1+ L4 LAN0_MDI1+
USBP1P TRD0- TRD1+ LAN0_MDI1+ 34
4 3 U4 1 2 C222 10/100
15 USB_3 GNDP1 TRD0+ L3 6.8PF/NPO/50V/0402-LF LAN0_MDI0-
VCT TRD0- LAN0_MDI0- 34
xChoke-USB L2 LAN0_MDI0+
OLEDP12 TRD0+ LAN0_MDI0+ 34
1 2 C229
CG6 CG4 L1 FB16 6.8PF/NPO/50V/0402-LF
VCT V2P5_DUAL_LAN
USBPWR2 CG8 CG2 OLEDN11 30OHM/3A/40mOHM-LF
F3 R398
L12 3VDUAL
2 1 VCCUSB2 C223 0.1UF/16V/0402-LF 220-LF LAN trace : 50:5:7:5:50
YELLOW
CG1
CG2
CG3
CG4
CG5
CG6
CG7
CG8
1.6A/9V/POLYSWITCH-LF L11 LAN0_LED_2 34

A A
1K-LF
15 USB_OC23* 1 R382 2 FB15
H1
H2
H3
H4
H5
H6
H7
H8
30OHM/3A/40mOHM-LF C218
2
470PF/X7R/16V/0402-LF C494 0402 0402 C239

C231 R391 USB2GND 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF
2.2K-LF 1000uF
1000PF/X7R/50V/0402-LF C219
2
0.1UF/16V/0402-LF FB18
30OHM/3A/40mOHM-LF Title
1
FB48
x30OHM/3A/40mOHM-LF USB1 / USB2 / FP-USB
A3 I-N73V 0.2
5 4 3 2 1
5 4 3 2 1
CPU_VID7 RN2-4 4 5 1K-8P4R-LF

CPU_VTT CPU_VID6 RN2-3 1K-8P4R-LF
3 6
CPU VID Change CPU_VID5 RN2-2 2 7 1K-8P4R-LF U20 Board ID: Version ID: Temperature Sensing (2.048V)
by W83627DHG CPU_VID4 RN2-1 1 8 1K-8P4R-LF VTT_OUT_RIGHT 102 65 SEL2 / 1 / 0 SEL1 / 0
1K CPU_VID3 RN3-4 1K-8P4R-LF 0 0 0 I-N73HD 0 0 (Reserve)
4 5 HM_VREF=2.048V
CPU_VID2 RN3-3 3 6 1K-8P4R-LF 103 64 0 0 1 I-N73V "CPU Back / PWM use"
SIO CPU CPU_VID1 RN3-2 2 7 1K-8P4R-LF QFP128 0 1 0 I-N73H HM_VREF HM_VREF RS6 2 1
t
4.7K CPU_VID0 RN3-1 1K-8P4R-LF 39 10K-1%-LF RT1 10K-1%THRM_0603-LF
1 8 128
0603
SIO_GP63 R638 10K-0402-LF VCC3 40 VPWMTIN VPWMTIN
1 38 LPT BOARD_ID_SEL0 R639 x10K-0402-LF C364 0.1UF/16V/0402-LF
PWM CPU_VID0 RN22-4 4 5 4.7K-8P4R-LF SIO_VID0 128 47 NC 1
CPU_VID1 RN22-3 4.7K-8P4R-LF SIO_VID1 VID0/GPSA1/GP10 (BD) STB# (OD) NC SIO_GP66 R640 x10K-0402-LF
3 6 127 VID1/GPSB1/GP11 (BD) AFD# (OD) 46 VCC3 "system use" IOAGND 7
D CPU_VID2 RN22-2 2 7 4.7K-8P4R-LF SIO_VID2 126 45 NC BOARD_ID_SEL1 R641 10K-0402-LF C374 RS1 2 1 D
CPU_VID3 RN22-1 4.7K-8P4R-LF SIO_VID3 VID2/GPX1/GP12 (BD) ERR# (I) NC 10K-1%-LF RT3 10K-1%THRM_0603-LF
t
1 8 125 VID3/GPX2/GP13 (BD) INIT# (OD) 44
0603
to CPU CPU_VID4 RN23-4 4 5 4.7K-8P4R-LF SIO_VID4 124 43 NC SIO_GP67 R642 x10K-0402-LF VCC3 1UF/16V-LF VSYSTIN
CPU_VID[7..0] CPU_VID5 RN23-3 4.7K-8P4R-LF SIO_VID5 VID4/GPY2/GP14 (BD) SLIN# (OD) NC BOARD_ID_SEL2 R643 10K-0402-LF C358 0.1UF/16V/0402-LF
7,8 CPU_VID[7..0] 3 6 123 VID5/GPY1/GP15 (BD) PD0 (B) 42
CPU_VID6 RN23-2 4.7K-8P4R-LF SIO_VID6 NC 2
2 7 122 VID6/GPSB2 (I)/GP16(BD) PD1 (B) 41
1
CPU_VID7 RN23-1 1 8 4.7K-8P4R-LF SIO_VID7 121 40 NC "CPU use"
VID7/GPSA2 (I)/GP17(BD) PD2 (B) NC CT79 RS7
PD3 (B) 39 CPU_THERMDA 7
Layout near CPU PWM to PWM controller 38 NC SIO_GP41 R677 x10K-0402-LF VCC3 15K-1%-LF
SIO_VID[7..0] PD4 (B) NC VER_ID_SEL0 R678 10K-0402-LF 4.7UF/10V/0805-LF C43
29 SIO_VID[7..0] 37
2
PD5 (B) NC VCPUTIN 2200PF/X7R/16V/0402-LF
PD6 (B) 36
FAN Controller 35 NC SIO_GP43 R679 x10K-0402-LF VCC3 C447
PD7 (B) NC VER_ID_SEL1 R680 10K-0402-LF 2200PF/X7R/16V/0402-LF
FANPWM_CPU1 120 CPUFANOUT1/MSO/GP20 (BD) ACK# (I) 34
W83627DHG ref._v0.5 no this, VCC3 2 1 AUXFAN1 119 33 NC
FAN4_AUX2 CPUFANIN1/MSI/GP21 (BD) BUSY (I) 7 IOAGND CPU_THERMDC 7
that reserve from W83627EHF. 3VDUAL FANPWM_SYS R479 1K-1%-LF 116 32 NC
SYSFANOUT (O) PE (I) NC Layout near CPU
40 FANPWM_CPU0 115 CPUFANOUT0 (O) SLCT (I) 31
80 VREF_P* 10K NC 7
81 VREF_N 10K SYSFAN AUXFANOUT C OM1 CPUFAN_4P_EN
40 FAN3_SYS 2 1 113 SYSFANIN (B) CPUFAN_4P_EN 40
87 PASS_CPURST R520 x10K-0402-LF 2R492 1K-1%-LF
1 CPUFAN 112 57
40 FAN1_CPU CPUFANIN0 GP60/RIA#
91 VCORE_RST* R101 x10K-0402-LF 2R499 1K-1%-LF
1 AUXFAN0 111 56 CPU_VIDSEL_SIO* R717 VCC3
40 FAN2_AUX1 AUXFANIN0 GP61/DCDA#
92 TURBO R100 x10K-0402-LF 2R501 1K-1%-LF
1 58 54 SOUTA 10K-0402-LF
R500 1K-1%-LF AUXFANIN1/SO GP62/SOUTA/PENKB BOARD_ID_SEL0 CPU_VIDSEL_SIO:
53
C
GP63/SINA DTRA# -0 : VRD 11
VCC3 GP64/DTRA#(PENROM) 52
51 RTSA# -1 : VRD 10.X B R718
GP65/RTSA#(HEFRAS) CPU_VIDSEL 8,29
50 BOARD_ID_SEL1 1K-LF
H W M onitor GP66/DSRA# BOARD_ID_SEL2 Q94 form CPU(1.2V)
49
E
SYSFAN VCC3 VSYSTIN GP67/CTSA# PMBS3904-LF
A1 104
K Q52 VCPUTIN 103
SYSTIN/VTIN1 (I)
CPUTIN/VTIN2 (I) 1 2 ROM_WP_EN 15,28,39
Voltage Sensing (2.048V)
CPUFAN A2 BAT54C-LF VPWMTIN 102 C OM2 R525 x0-0402-LF
3VDUAL AUXTIN0/VTIN3 (I) RS5 10K-1%-LF VCCP_R
GP40/RIB# 85 VCCP
C AUXFAN0 A1 HM_VREF HM_VREF 101 84 VER_ID_SEL0 C
VREF (P) GP41/DCDB#
K Q51 VCCP_R 100 CPUVCORE (I) GP42/IRTX/SOUTB 83 SIO_FAN_SET2
VDDMEM
RS10 10K-1%-LF V_DDR
AUXFAN1 A2 BAT54C-LF V_DDR 99 82 VER_ID_SEL1 RS9 10K-1%-LF
VIN0 (I) GP43/IRRX/SINB 7 IOAGND
V_VTT 98 81
R219 V_PCIE VIN1 (I) GP44/DTRB# RS4 10K-1%-LF V_VTT
97 VIN2 (I) GP45/RTSB# 80 V1P2_CORE_SEL0 33 VTT_P V1P2_FSBVTT
1K-0402-LF +12VIN 96 79
to MCP VIN3 (I) GP46/DSRB# V1P2_CORE_SEL1 33 VTT_N
78 V1P2_CORE RS8 10K-1%-LF V_PCIE
R515 0-LF GP47/CTSB#
16,28 PWRGD_SB 2 VCORE_ADJ0 VDDMEM_SEL0 32 CPU_GTLREF_SEL0
VCORE_ADJ1 RS3 20K-1%-LF +12VIN
VDDMEM_SEL1 32 CPU_GTLREF_SEL1 VCC12
Layout RS2 3.01K-1%-LF
near Chipset R626 C91
VCORE_ADJ2
VCORE_ADJ3
W83627DHG 7 IOAGND
x10K-LF x1UF/16V-LF
1 RSMRST_SIO* RSTOUT0* R523 10K-0402-LF
75 GP51/RSRMRST# (B) RSTOUT0# (O) 94 VCC3
NC TURBO 92 93 N C H/W Straping
NC VCORE_RST* GP30(BD) RSTOUT1# (O) SIO_SCL R521 10K-0402-LF
91 GP31(BD) RSTOUT2#/SCL/GP32 90 VCC3
3VDUAL 10 BSEL2_LOW_EN 69 89 SIO_SDA R532 10K-0402-LF
C55/MCP51 CRB: GP36 RSTOUT3#/SDA/GP33
64 GP37 RSTOUT4#/GP34 88 N C R533 x1K-0402-LF HEFRAS 51 RTSA# R481 x1K-0402-LF VCC3
SIO THERM OUTPUT MCP73 NC PASS_CPURST 87 R522 x1K-0402-LF R487 1K-0402-LF
USED FOR EXT_SMI* Internal Pull-Hi GP35 PENROM 52 DTRA# R491 1K-0402-LF
SID 110N C W83627DHG ref.
R452 VBATCCMOS 2R516 1M-LF
1 109N C SCL/SDA Pull-Hi VCC3 PENKBC 54 SOUTA R498 1K-0402-LF VCC3
to MCP73 x10K-0402-LF SIC
118 P E CI CPU_PECI EN_GTL 77 WDTORST* R517 1K-0402-LF 3VDUAL
16 EXT_SMI* 28 W_BEEP BEEP/SI (OD)
77 108 CPU_PECI_SIO 7 R529 x1K-0402-LF
28 WDTORST* WDTO#/GP50(EN_VRM10) PECI
40 CASEOPEN* 76 CASEOPEN# (I) VTT 107 V1P2_FSBVTT
EXT_SMI* 5 106N C SIO_PECI_MCP 7 FAN_SET2 83 SIO_FAN_SET2 R519 1K-0402-LF
OVT#/HM_SMI# PECISB R506 x10K-0402-LF C352 FAN_SET 117 SIO_FAN_SET R482 1K-0402-LF
72 PSON#/GP53 VCC3
VCC5SB D34 PWRBTN* 67
B LL4148/150mA-LF PSOUT#/GP57 0.1UF/16V/0402-LF B
28 PANSWIN* 68 PSIN#/GP56 SCE#/GP22 19 CPU_FORCE_PR_SIO*
5VDUAL K A N C 71 2 NC W83627DHG POWER ON STRAPPING PIN
SUSLED PWROK/GP54 SCK/GP23
28 SUSLED 70 SUSLED/GP55
73 Low Hi
28,32,33 W83627_PSON# GP52/SUSB# RTSA# (51) 2E 4E I/O CONFIGURATION ADDRESS
R747 33-LF KB
16,31,32 SLP_S3* DTRA#(52) DISABLE ENABLE ENABLE SPI
L PC 63
PWRCTL* GP26/KDAT SIO_KBDATA 39 SOUTA (54) DISABLE ENABLE KBC FUNCTION ENABLE
13 LPC_RST_SIO* 30 LRESET# (I) GP27/KCLK 62 SIO_KBCLK 39
LPC_FRAME* 29 GP50 (77) TTL GTL VID LEVEL SELECTION
3VDUAL 13 LPC_FRAME* LFRAME# (I) SOUTB (83) PWMOUT 50% PWMOUT 100% FOR CPUFANOUT1(120) ONLY
13,39 LPC_AD0 27 LAD0 (B) KBRST (O) 60 SIO_KBRST* 16
MCP73 26 59 PLED (117) PWMOUT 50% PWMOUT 100% FOR CPUFANOUT0(115) ONLY
13,39 LPC_AD1 LAD1 (B) GA20M (O) A20GATE 16
Internal Pull-Hi 25
13,39 LPC_AD2 LAD2 (B)
24 MS
13,39 LPC_AD3 LAD3 (B)
R514 22 66 VCC3
13 LPC_DRQ0* LDRQ# (O) GP24/MDAT SIO_MSDATA 39
x10K-0402-LF 21 65 FB38
13 LPC_CLK_SIO PCICLK (I) GP25/MCLK SIO_MSCLK 39
LPC_SERIRQ 23 150OHM/400MA/150mOHM-LF H/W Straping
16 PWRBTN* 13 LPC_SERIRQ SERIRQ (B)
16 IO_PME* IO_PME* 86 1
to MCP73 C362 PME# (OD) SIO_FAN_SET W83627EHG- App. Notice 01 (Pin70):
16 BUF_SIO_CLK 18 CLKIN_48/24 (I) PLED/FAN_SET 117
1
06031000PF/X7R/50V/0402-LF C461 C373 BC379 BCT81 Test mode: pull-high 5V_dual
X7R 114 SIO_SST R489 10K-0402-LF *User mode: pull-low
16V SST 1UF/16V-LF 0.1UF/16V/0402-LF
FDC 95 IOAVCC 2200PF/X7R/16V/0402-LF 10UF/Y5V/10V/0805-LF 10k
5VDUAL
2
W83627DHG AVCC IOAGND 2 FB37 SUSLED 2.2k
39 FD_DENSEL 1 DRVDEN0 (OD) AGND 105
-Application Note 2: 39 FD_INDEX- 3 150OHM/400MA/150mOHM-LF
INDEX# (I) IOAGND 7
Pin70 (GP55/SUSLED) 4 74 VBATCCMOS
3VDUAL 39 FD_MTR0- MOA# (OD) VBAT (P)
4.7K RSMRST_SIO* should be pulled low, 6
39 FD_DR0- DSA# (OD)
If pulled high, 8 61 3VDUAL
39 FD_DIR- DIR# (OD) 3VSB (P)
R531 IO_PME* it enables Winbond test mode. 9
39 FD_STEP- STEP# (OD)
x10K-0402-LF 10 12 VCC3
39 FD_WDATA- WD# (OD) VCC3_1 (P)
MCP73 11 28
A 39 FD_WGATE- WE# (OD) VCC3_2 (P) A
Internal Pull-Hi 4.7K LPC_FRAME* 39 FD_TRK0- 13 48 C363
TRAK0# (I) VCC3_3 (P) C338C319 C351
39 FD_WP- 14 WP# (I)
R453 LPC_SERIRQ 39 FD_RDATA- 15 20 0.1UF/16V/0402-LF 3VDUAL
x10K-0402-LF RDATA# (I) VSS_1 (P) 0.1UF/16V/0402-LF
39 FD_HDSEL- 16 HEAD# (OD) VSS_2 (P) 55
4.7K LPC_DRQ0* 39 FD_DSKCHG- 17 DSKCHG# (I)
4.7K LPC_AD0 W83627DHG-LF
VCC3 4.7K LPC_AD1 PQFP128-0_5-A 0.1UF/16V/0402-LF Title
4.7K LPC_AD2 0.1UF/16V/0402-LF to MCP51
4.7K LPC_AD3 SER_RI*
SER_RI*
W83627DHG SuperI/O
A3 I-N73V 0.2
5 4 3 2 1
5 4 3 2 1
LPC SPI
FLASH ROM FLASH ROM
Layout SIO
MCP73 VCC3
D Internal Pull-Hi D
LPC_AD[3..0]
13,38 LPC_AD[3..0]
LPC_AD0 R467 x10K-0402-LF
LPC_AD1 R466 x10K-0402-LF U43
LPC_AD2 R465 x10K-0402-LF SKT-SPI-LF 3VDUAL 3VDUAL
LPC_AD3 R464 x10K-0402-LF
1 CS*(I) 8 VCC3 8
2 SO(I) 1 HOLD* 7
1
3 6 C403 C442
VCC3 WP* SCK(I) 0603 R563
4 GND SI(I/O) 5
3VDUAL 5 10K-0402-LF
LPC_AD[3..0] 4
13,38 LPC_AD[3..0]
2
SPI SKT
LPC_AD0 Place < 100 MILS 1UF/16V-LF
LPC_AD1 FROM SERIAL FLASH DEVICE R560 U23 0.1UF/16V/0402-LF
LPC_AD2 10K-0402-LF xSPI-ROM
LPC_AD3 from MCP73 Place < 100MILS FROM NB
16 SPI_CS* SPI_CS* 1 SPI 8
LPC_FRAME* FLASH4MBIT_INIT R635 0-0402-LF SPI_DI_R CS*(I) VCC3 SPI_HOLD*
13,38 LPC_FRAME* 16 SPI_DI 2 SO(I) HOLD* 7
SPI_WP* 3 6 SPI_CLK_R R636 0-0402-LF
LPC_CLK_FLASH WP* SCK(I) SPI_CLK 16
4 5 SPI_DO_R R637 0-0402-LF
LPC_CLK_FLASH GND SI(I/O) SPI_DO 16
VCC3
LPC_RST_FLASH* ROM_WP_EN*
LPC_RST_FLASH*
LPC
FLASH
VCC3 FWH_WP*
FWH_TBL*
C C
ROM_WP_EN* 3VDUAL
ROM_WP_EN*
ROM_WP_EN:
- 0 : ROM Write-able R526
D
- 1 : ROM Write protect (default) 4.7K-LF
15,28,38 ROM_WP_EN G Q56

2N7002-LF
S
5V_PS2
0805 -> 0603
FB2 30OHM/3A/40mOHM-LF
FLOPPY CONNECTOR
5VDUAL
VCC5 FB1 x30OHM/3A/40mOHM-LF

PS/2 KM
W83627DHG Ref. circuit_v0.5 :
Index# of W83627DHG must pull high VCC
B B
no matter use FDC or not.
F1 VCC5
1812 1.6A/9V/POLYSWITCH-LF R331 1K-0402-LF
1 2
C2 6 3
2.7K-8P4R-LF
2.7K-8P4R-LF
2.7K-8P4R-LF
2.7K-8P4R-LF
06030.1UF/16V/0402-LF RN17-3 7 2 x1K-8P4R

6
5
7
8
0 ohm Y5V RN17-2 8 1 x1K-8P4R

16V
VCC5
RN17-1 5 4 x1K-8P4R
KM1 RN17-4 x1K-8P4R
4 FDC1
3
4
2
1
5VPS2 VCC1 (P)

10 VCC2 (P) 38 FD_DENSEL 2 DR0 (I) 2 1 GND1 (P) 1
RN1-3
RN1-4
RN1-2
RN1-1
4 NC1 GND2 (P) 3

6 DR1 (I)
38 FD_INDEX- 8 INDEX# (O) GND4 (P) 7
4 5 LN1-4 SIOKBDATA 1 38 FD_MTR0- 10 9
38 SIO_KBDATA KDAT (B) MORA# (I) GND5 (P)
3 6 LN1-3 SIOKBCLK 5 12 11
38 SIO_KBCLK KCLK (B) DSB# (I) GND6 (P)
2 7 LN1-2 2 38 FD_DR0- 14 13
38 SIO_MSDATA NC1 DSA# (I) GND7 (P)
1 8 LN1-1 6 16 15
38 SIO_MSCLK NC2 MORB# (I) GND8 (P)
38 FD_DIR- 18 DIR# (I) GND9 (P) 17
120-8P4B-LF SIOMSDATA 7 38 FD_STEP- 20 19
SIOMSCLK MDAT (B) STEP# (I) GND10 (P)
11 MCLK (B) 38 FD_WDATA- 22 WD# (I) GND11 (P) 21
8 NC3 38 FD_WGATE- 24 WE# (I) GND12 (P) 23
150OHM/400mA/0603 12 26 25
NC4 38 FD_TRK0- TRK0# (O) GND13 (P)
-> 120ohm/150mA/8P4R 28 27
38 FD_WP- WP# (O) GND14 (P)
47PF/NPO/8P4C-LF
47PF/NPO/8P4C-LF
47PF/NPO/8P4C-LF
47PF/NPO/8P4C-LF
3 GND1 (P) 16 14 38 FD_RDATA- 30 RD# (O) NC2 29

5
6
7
8
9 GND2 (P) 38 FD_HDSEL- 32 HEAD# (I) GND15 (P) 31

A 11 9 5 3 38 FD_DSKCHG- 34 DSKCH# (O)34 33 NC3 33 A
13 7 1
4
3
2
1
H1 Header-BOX-17X2P-LF
14 H2 8 2
COB2X17P-2_54
15 H3 12 10 6 413
CN1-4
CN1-3
CN1-2
CN1-1
16 H4
17 H5 17 15
KB/MS-LF
CON2X6P-DIN Title
K/M + FLASH + FDC

A3 I-N73V 0.2
5 4 3 2 1
5 4 3 2 1
VCC3 VCC3
VCC3 VCC5 VCC5 Value of the serier resistance
might need to be tuned for EOS
2
VCC12
K
R428 R34
1
4.7K-0402-LF VCC12 R617 W83627EHF (AN05): 2.2K-LF D3
4.7K-0402-LF Pin115/116 could select output type by Register: R62 LL4148/150MA-LF
OD => stuff 0 ohm
D 4 4 Push-pull => stuff NPN,pull-high 2.2K-LF D
B 1
3 FAN3_SYS 38 3 FAN2_AUX1 38
A
2 2 Register default:OD (for H ver.)
2
1 1 Q2
E C R79
38 FANPWM_CPU0
PMBS3904-LF 220-0805-LF
SYSFAN1 AUXFAN1
FAN-WAFER3X1-BROWN-LF FAN-WAFER3X1-BROWN-LF
VCC12
VCC12
R82
4.02K-1%-LF
E
C38
06030.1UF/16V/0402-LF B Q15 VCC3
OVP R84
Y5V
16V 2SB1202/3A_TO252-LF
C
Layout Near CPU PWM 10K-LF
R83 R99
8
1K-1%-LF 4.7K-0402-LF
4 3 2 1
5 + 4 Control
7
VCCP 5VDUAL 6 3
- 38 FAN1_CPU SENSE
C U3B C
R702 1K-1%-LF 1UF/16V-LF LM358DR-LF 2
4
C36 +12V
C488 to CPU PWM 0603 1
0.1UF/16V/0402-LF RT8802_DVDEN GND
RT8802_DVDEN 29
R703 VCC3 R86 10K-1%-LF
8
U48B 4.7K-LF
D
V2P5_VREF OVP_EN#
5
+ V+ 7 OV_EN G Q7
R40
R85 CT108 CPUFAN1
R704 1K-1%-LF V2P0_REF 6 V- 2N7002-LF 4.02K-1%-LF 1206 FAN-WAFER4X1-Black-LF
2V - 4.7K-0402-LF 10UF/16V/X5R/1206-LF
D
S
LM358DR-LF
4
R705 C489 SOP8-1_27 SIO GPIO Q3

4.02K-1%-LF 0.1UF/16V/0402-LF G
38 CPUFAN_4P_EN
2N7002-LF
S
-Hi: 4Pin Fan
-Lo: 3Pin Fan
B
CPU PROCHOT# & FORCE# B
Layout Near CPU PWM CPU Change & Clear CMOS: High
R719 0603-1% 39.2K-1%-LF
TO SIO CASE OPEN* VBATCCMOS
38 CASEOPEN* CASEOPEN* 0 ohm 2

5VDUAL VCC5
V2P5_VREF
INTRUDER* INTRUDER* 0 ohm R385
10M-LF
D
TO MCP73
PROCHOT# 1 CPU_GND
C492
0603-1%
C495 R720 06030.1UF/X7R/16V/0402-LF CPU_PROCHOT* 7,10 Q50 G SKTOCC# SKTOCC# 7

0.1UF/16V/0402-LF 7.5K-1%-LF R721 2N7002-LF
D
S
8
U48A 10K-LF to CPU 1 form CPU

3 Q95
+ V+ 1 R722 0-LF G 2N7002-LF C228
2 V- 0.1UF/16V/0402-LF LGA775-SKTOC#(Pin.AE8)
-
0603-1%
R723 -Low: CPU stuffed

499-1%-LF LM358DR-LF FORCEPR# -NA: no CPU
4
SOP8-1_27 2
CPU_FORCE* 8
D
A
from RT of PWM to CPU A
38 VPWMTIN Q96
R724 0-LF G 2N7002-LF
PWMTEMP
S
Title
CPU CHANGE ,PROCHOT# & FAN

A3 I-N73V 0.2
5 4 3 2 1
5 4 3 2 1
Other BOM (NO Foot-Print)

BIOS Guru CPU CCMOS JUMPER Battery CUPON CUPON
( ref. the same
with CCMOS1 ) BAT
(differential) (single)
1.ROM 1.Firmware 1.Label
D U21ROM UxFW U6LAB CCMOS1(1-2) VCC5 VCC5 D
CUPON1
LGA775 CUPON3 NC 1
8MB CPU Socket CUPON3N NC NC CUPON1 2
CAUTION
FLASH 1394 Firmware xHeader-2X1P
Data File
xLPC_FLASH_8M-LF LGA775-CAUTION-LF CUPON2
xAC2005_FIRMWARE1 4301-0000-17 1
CUPON4 NC NC CUPON2 2
U43ROM JUMPER-2PIN-Black-LF CUPON4N NC
3V_BATTERY-LF
xHeader-2X1P
8MB 1394
FLASH
1.Firmware PCB 14.318MHz
SPI_FLASH_8M-LF U24FW (no ref.) XTAL WIRE
PCB (ref. the same #
with X'TAL(32.768KHZ))
1394 Firmware
2.Label 3.Firmware Data File PCB
U43LAB U43FW
x1394_FIRMWARE1 1Cm Layout Note
LABEL PCB_M712_v02_244x200_Orange Y1W
PhoenixBIOS NC
D686 BIOS JUMP_WIRE-LF
C PHOENIX 1998 BIOS Firmware C
PCI
PCI
Data File
PCIEx1
BIOS_LABEL-LF
PCIEXP
4301-0000-15 BIOS_FIRMWARE1
4Cm 4.5Cm
G-CARD
M/B
PWM Heat-Sink NB Heat-Sink SB Heat-Sink
NB_HSINK1
B B
Heat_Sink/68.4*48*35mm-BLUE-LF
HSINK-C40X40
3247-0000-56
RL10 RL14
1 1 1 1
M9
xMarkin-R xMarkin-R M8 M6 1 4
v0.2 1 5 1 5 2 1 7
RL23 RL6 Place on 2 6 2 6
solder side 3 1 7 3 1 7
4 8 4 8 xM8_3X4G
1 1 1 1
xM8_3X4G xM8_3X4G
A xMarkin-R xMarkin-R RL27 M2 M1 M5 A

1 5 1 5 1 5
RL9 RL24 2 6 2 6 2 6
1 1 3 1 7 3 1 7 3 1 7
4 8 4 8 4 8
1 1 1 1
xM8_3X4G xM8_3X4G xM8_3X4G USBGND
xMarkin-R
Title
xMarkin-R xMarkin-R
MOUNTING HOLES
A3 I-N73V 0.2
5 4 3 2 1

ABIT I-N73V [NFORCE MCP73] LGA775 V.0.2

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ABIT I-N73V [NFORCE MCP73] LGA775 V.0.2

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5 4 3 2 1

BACK PANEL CONN

8MB FLASH LPC BUS 33MHZ USB1

CPU_VLD PCI_RST_SLOT1* (+3.3V)

HDA_RESET* HDA_RST* AUDIO_PHY

CLOCK DISTRIBUTION PCIE

BCLK_OUT_CPU_N PCIE X16 REF_CLK 100MHZ

PCIE X16 REF_CLK*

FLASH PCI SLOT 2

LPC_CLK0 ALL 33MHZ 1/16

5VSB XSTR 3.3VSB V1P2_CORE

PCI SLOT 1 1 ARP VCC5

PCI INTERRUPT/IDSEL MAP

DEVICE TABLE / VRGES

CRB connect to SIO-P.104 (SYSTIN)

A2 GND GND AJ7 1 ˖ˣ˨˲˗ʽ˄ C5 D1* A4* P6 4 ˖ˣ˨˲˔ʽˇ

A6 GND GND AK16 4 ˖ˣ˨˲˗ʽˇ A5 D4* A7* M4 7 ˖ˣ˨˲˔ʽˊ

A9 GND GND AK17 5 ˖ˣ˨˲˗ʽˈ B6 D5* A8* R4 8 ˖ˣ˨˲˔ʽˋ

R0603 AA24 GND GND AK20 7 ˖ˣ˨˲˗ʽˊ A7 D7* A10* U6 10 ˖ˣ˨˲˔ʽ˄˃

AA25 GND GND AK23 8 ˖ˣ˨˲˗ʽˋ A10 D8* A11* T4 11 ˖ˣ˨˲˔ʽ˄˄

AA27 GND GND AK27 10 ˖ˣ˨˲˗ʽ˄˃

AA28 GND GND AK28 11 ˖ˣ˨˲˗ʽ˄˄

AA29 GND GND AK29 12 ˖ˣ˨˲˗ʽ˄˅

AA3 GND GND AK30 13 ˖ˣ˨˲˗ʽ˄ˆ

AA30 GND GND AK5 14 ˖ˣ˨˲˗ʽ˄ˇ

AA6 GND GND AK7 15 ˖ˣ˨˲˗ʽ˄ˈ

AA7 GND GND AL10 16 ˖ˣ˨˲˗ʽ˄ˉ

AB1 GND GND AL13 17 ˖ˣ˨˲˗ʽ˄ˊ

AB23 GND GND AL16 18 ˖ˣ˨˲˗ʽ˄ˋ

AB24 GND GND AL17 19 ˖ˣ˨˲˗ʽ˄ˌ

AB25 GND GND AL20 20 ˖ˣ˨˲˗ʽ˅˃

AB26 GND GND AL23 21 ˖ˣ˨˲˗ʽ˅˄

AB27 GND GND AL24 22 ˖ˣ˨˲˗ʽ˅˅

AB28 GND GND AL27 23 ˖ˣ˨˲˗ʽ˅ˆ

AB29 GND GND AL28 24 ˖ˣ˨˲˗ʽ˅ˇ

AB30 GND GND AL3 CPU_AL3_PD NC 25 ˖ˣ˨˲˗ʽ˅ˈ

AC3 GND GND AM1 27 ˖ˣ˨˲˗ʽ˅ˊ

AC7 GND GND AM13 R0603 29 ˖ˣ˨˲˗ʽ˅ˌ

AE10 GND GND AM20 32 ˖ˣ˨˲˗ʽˆ˅

AE13 GND GND AM23 33 ˖ˣ˨˲˗ʽˆˆ

AJ20 GND GND E8

SOCKET 775 PART 1

3 ˖ˣ˨˲˕ˣˠʽˆ AG2 BPM3* VCCP AF15

49.9-1%-LF R145 60.4-1%-0402-LF

TE STHI_1 G4 TESTHI9 VCCP AJ25

SOCKET 775 PART 2

I128 V28 GND GND W7

CPU_C9 R117 1 EMPTY 2 x0-LF 1

R0603 5% VCC3 TE STHI_8 R125 1 EMPTY 2 x0-LF 3

2.IL9_v0.2 only pull-hi VCC3 VTT_OUT_LEFT VTT_OUT_RIGHT

CPU_GTLREF_SEL1 R188 LAYOUT:

SOCKET 775 GTLREF

CPU_DSTBP1* N31 CPU_DSTBP1# CPU_D4# AA35 4 ˖ˣ˨˲˗ʽˇ

CPU_DSTBP2* G33 CPU_DSTBP2# CPU_D8# U35 8 ˖ˣ˨˲˗ʽˋ

CPU_D16# R31 16 ˖ˣ˨˲˗ʽ˄ˉ

CPU_D17# U33 17 ˖ˣ˨˲˗ʽ˄ˊ

CPU_D61# K37 61 ˖ˣ˨˲˗ʽˉ˄ x49.9-1%-LF x15PF/NPO/50V/0402-LF

CPU_A20M* AH38 A20M# BCLK_IN_P C38 BCLK_IN x49.9-1%-0402-LF

R562 R561 PE1_PRESENT* F6 PEA_PRSNT# PE0_TX6_P L4 6 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˉ

3VDUAL 0.1UF/16V/0402-LF10K-0402-LF to Slot PE0_TX4_P J2 4 ˣ˘˲˫˄ˉˀ˄˲˧˫˖ˇ