aic

Advanced Integrated
Circuits
Lecture Notes 2025
Carsten Wulff
Built on Fri Dec 6 14:28:19 UTC 2024

from 791ec535026d56ee6e595c681f67241210de3ae2
©Carsten Wulff 2025

Contents
Contents 3
1 Background 1
2 Introduction 3
2.1 Who . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 How I see our roles . . . . . . . . . . . . . . . . . 3
2.3 I want you to learn the skills necessary to make your
own ICs . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 There will always be analog circuits, because the
real world is analog . . . . . . . . . . . . . . . . . 5
2.4.1 Will you tape-out an IC? . . . . . . . . . . 9
2.4.2 What the team needs to know to design ICs 9
2.4.3 Zen of IC design (stolen from Zen of Python) 10
2.4.4 IC design mantra . . . . . . . . . . . . . . 10
2.4.5 Analog Design Process . . . . . . . . . . . 11
2.5 My Goal . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6 Syllabus . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7 JNW (2025) . . . . . . . . . . . . . . . . . . . . . . 13
2.7.1 Grading . . . . . . . . . . . . . . . . . . . . 15
2.7.2 Group dynamics . . . . . . . . . . . . . . . 15
2.8 Software . . . . . . . . . . . . . . . . . . . . . . . 16
3 A refresher 17
3.1 There are standard units of measurement . . . . . 17
3.2 Electrons . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Probability . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Uncertainty principle . . . . . . . . . . . . . . . . 20
3.5 States as a function of time and space . . . . . . . 20
3.6 Allowed energy levels in atoms . . . . . . . . . . 21
3.7 Allowed energy levels in solids . . . . . . . . . . . 21
3.8 Silicon Unit Cell . . . . . . . . . . . . . . . . . . . 22
3.9 Band structure . . . . . . . . . . . . . . . . . . . . 23
3.10 Valence band and Conduction band . . . . . . . . 24
3.11 Fermi level . . . . . . . . . . . . . . . . . . . . . . 24
3.12 Metals . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.13 Insulators . . . . . . . . . . . . . . . . . . . . . . . 26
3.14 Semiconductors . . . . . . . . . . . . . . . . . . . 26
3.15 Band diagrams . . . . . . . . . . . . . . . . . . . . 27
3.16 Density of electrons/holes . . . . . . . . . . . . . 27
3.17 Fields . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18 Permittivity and Permeability . . . . . . . . . . . 28
3.19 Quantum electrodynamics . . . . . . . . . . . . . 29
3.20 Voltage . . . . . . . . . . . . . . . . . . . . . . . . 29
3.21 Current . . . . . . . . . . . . . . . . . . . . . . . . 29
3.22 Drift current . . . . . . . . . . . . . . . . . . . . . 30
3.23 Diffusion current . . . . . . . . . . . . . . . . . . . 31
3.24 Why are there two currents? . . . . . . . . . . . . 31
3.25 Currents in a semiconductor . . . . . . . . . . . . 31
3.26 Resistors . . . . . . . . . . . . . . . . . . . . . . . 32
3.27 Capacitors . . . . . . . . . . . . . . . . . . . . . . 32
3.28 Inductors . . . . . . . . . . . . . . . . . . . . . . . 32
4 Diodes 33
4.1 Why . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2 Silicon . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3 Intrinsic carrier concentration . . . . . . . . . . . 35
4.4 It’s all quantum . . . . . . . . . . . . . . . . . . . 37
4.4.1 Density of states . . . . . . . . . . . . . . . 38
4.4.2 How to think about electrons (and holes) . 40
4.5 Doping . . . . . . . . . . . . . . . . . . . . . . . . 41
4.6 PN junctions . . . . . . . . . . . . . . . . . . . . . 42
4.6.1 Built-in voltage . . . . . . . . . . . . . . . 43
4.6.2 Current . . . . . . . . . . . . . . . . . . . . 44
4.6.3 Forward voltage temperature dependence 45
4.6.4 Current proportional to temperature . . . 47
4.7 Equations aren’t real . . . . . . . . . . . . . . . . . 48
References . . . . . . . . . . . . . . . . . . . . . . 49
5 MOSFETs 51
5.0.1 Metal Oxide Semiconductor . . . . . . . . 51
5.0.2 Field Effect . . . . . . . . . . . . . . . . . . 53
5.1 Analog transistors in the books . . . . . . . . . . . 58
5.2 Transistors in weak inversion . . . . . . . . . . . . 61
5.3 The Field Effect . . . . . . . . . . . . . . . . . . . . 64
5.4 Transistors in strong inversion . . . . . . . . . . . 66
5.5 How should I size my transistor? . . . . . . . . . . 67
6 SPICE 69
6.1 SPICE . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.2 Simulation Program with Integrated Circuit Em-
phasis . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.2.1 Today . . . . . . . . . . . . . . . . . . . . . 69
6.2.2 But . . . . . . . . . . . . . . . . . . . . . . 70
6.2.3 Sources . . . . . . . . . . . . . . . . . . . . 71
6.2.4 Passives . . . . . . . . . . . . . . . . . . . . 72
6.2.5 Transistor Models . . . . . . . . . . . . . . 72
6.2.6 Transistors . . . . . . . . . . . . . . . . . . 73
6.2.7 Foundries . . . . . . . . . . . . . . . . . . . 74
6.3 Find right transistor sizes . . . . . . . . . . . . . . 74
6.3.1 Use unit size transistors for analog design 75
6.3.2 What about gm/Id ? . . . . . . . . . . . . 76
6.3.3 Characterize the transistors . . . . . . . . . 76
6.4 More information . . . . . . . . . . . . . . . . . . 76
6.5 Analog Design . . . . . . . . . . . . . . . . . . . . 76
6.6 Demo . . . . . . . . . . . . . . . . . . . . . . . . . 77
7 Mixed Signal Simulation in NGSPICE 79

7.1 Mixed Signal Simulation in ngspice . . . . . . . . 79
7.2 Digital simulation . . . . . . . . . . . . . . . . . . 79
7.3 Transient analog simulation . . . . . . . . . . . . 80
7.4 Demo . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.5 The circuit . . . . . . . . . . . . . . . . . . . . . . 82
7.6 The digital code . . . . . . . . . . . . . . . . . . . 83
7.7 Compile RTL . . . . . . . . . . . . . . . . . . . . . 84
7.8 Import object into SPICE file . . . . . . . . . . . . 84
7.9 Import in testbench . . . . . . . . . . . . . . . . . 85
7.10 Override default digital output voltage . . . . . . 85
7.11 Running . . . . . . . . . . . . . . . . . . . . . . . . 86
8 Sky130nm tutorial 87
8.1 Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.1.1 Setup WSL (Applicable for Windows users) 87
8.1.2 Setup public key towards github . . . . . . 87
8.1.3 Get AICEX and setup your shell . . . . . . 88
8.1.4 On systems with python3 > 3.12 . . . . . . 88
8.1.5 Install Tools . . . . . . . . . . . . . . . . . 88
8.1.6 Install cicconf . . . . . . . . . . . . . . . . 89
8.1.7 Install cicsim . . . . . . . . . . . . . . . . . 89
8.1.8 Setup your ngspice settings . . . . . . . . . 89
8.2 Check that magic and xschem works . . . . . . . 90
8.3 Design tutorial . . . . . . . . . . . . . . . . . . . . 90
8.3.1 Create the IP . . . . . . . . . . . . . . . . . 90
8.3.2 The file structure . . . . . . . . . . . . . . . 90
8.3.3 Github setup . . . . . . . . . . . . . . . . . 92
8.3.4 Start working . . . . . . . . . . . . . . . . . 93
8.3.5 Draw Schematic . . . . . . . . . . . . . . . 93
8.3.6 Typical corner SPICE simulation . . . . . 95
8.3.7 All corners SPICE simulations . . . . . . . 98
8.3.8 Draw Layout . . . . . . . . . . . . . . . . 100
8.3.9 Layout verification . . . . . . . . . . . . . 107
8.3.10 Extract layout parasitics . . . . . . . . . . 109
8.3.11 Simulate with layout parasitics . . . . . . 109
8.3.12 Make documentation . . . . . . . . . . . . 110
8.3.13 Edit info.yaml . . . . . . . . . . . . . . . . 110
8.3.14 Setup github pages . . . . . . . . . . . . . 111
8.3.15 Frequency asked questions . . . . . . . . . 111
9 IC and ESD 113

9.0.1 What blocks must our IC include? . . . . . 113
9.1 Electrostatic Discharge . . . . . . . . . . . . . . . 116
9.1.1 When do ESD events occur? . . . . . . . . 117
9.1.2 Before/during PCB . . . . . . . . . . . . . 117
9.1.3 After PCB . . . . . . . . . . . . . . . . . . 118
9.1.4 Human body model (HBM) . . . . . . . . 118
9.1.5 Charged device model (CDM) . . . . . . . 119
9.2 An HBM ESD zap example . . . . . . . . . . . . . 121
9.3 Permutations . . . . . . . . . . . . . . . . . . . . . 122
9.3.1 Why does this work? . . . . . . . . . . . . 124
9.3.2 How can current in one place lead to a cur-
rent somewhere else? . . . . . . . . . . . . 127
9.4 Want to learn more? . . . . . . . . . . . . . . . . . 130
10 References and bias 131

10.1 Routing . . . . . . . . . . . . . . . . . . . . . . . . 131
10.2 Bandgap voltage reference . . . . . . . . . . . . . 133
10.2.1 A voltage complementary to temperature
(CTAT) . . . . . . . . . . . . . . . . . . . . 133
10.2.2 A current proportional to temperature (PTAT) 135
10.2.3 How to combine a CTAT with a PTAT ? . . 136
10.2.4 Brokaw reference . . . . . . . . . . . . . . 138
10.2.5 Low voltage bandgap . . . . . . . . . . . . 140
10.3 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . 143
10.3.1 How does a VI converter circuit work? . . 143
10.3.2 GmCell: Why is 1/Z proportional to transis-
tor transconductance? . . . . . . . . . . . . 144
11 Analog frontend and filters 147

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . 147
11.2 Filters . . . . . . . . . . . . . . . . . . . . . . . . . 149
11.2.1 First order filter . . . . . . . . . . . . . . . 150
11.2.2 Second order filter . . . . . . . . . . . . . . 151
11.2.3 How do we implement the filter sections? 152
11.3 Gm-C . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.3.1 Differential Gm-C . . . . . . . . . . . . . . 153
11.3.2 Finding a transconductor . . . . . . . . . . 155
11.4 Active-RC . . . . . . . . . . . . . . . . . . . . . . . 156
11.4.1 General purpose first order filter . . . . . . 156
11.4.2 General purpose biquad . . . . . . . . . . 159
11.5 The OTA is not ideal . . . . . . . . . . . . . . . . . 160
11.6 Example circuit . . . . . . . . . . . . . . . . . . . . 160
11.7 My favorite OTA . . . . . . . . . . . . . . . . . . . 161
12 Switched-Capacitor Circuits 165

12.1 Active-RC . . . . . . . . . . . . . . . . . . . . . . . 165
12.2 Gm-C . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.3 Switched capacitor . . . . . . . . . . . . . . . . . . 167
12.3.1 An example SC circuit . . . . . . . . . . . 170
12.4 Discrete-Time Signals . . . . . . . . . . . . . . . . 172
12.4.1 The mathematics . . . . . . . . . . . . . . 173
12.4.2 Python discrete time example . . . . . . . 174
12.4.3 Aliasing, bandwidth and sample rate theory 176
12.4.4 Z-transform . . . . . . . . . . . . . . . . . 178
12.4.5 Pole-Zero plots . . . . . . . . . . . . . . . . 179
12.4.6 Z-domain . . . . . . . . . . . . . . . . . . . 179
12.4.7 First order filter . . . . . . . . . . . . . . . 180
12.4.8 Finite-impulse response(FIR) . . . . . . . . 182
12.5 Switched-Capacitor . . . . . . . . . . . . . . . . . 183
12.5.1 Switched capacitor gain circuit . . . . . . . 185
12.5.2 Switched capacitor integrator . . . . . . . 186
12.5.3 Noise . . . . . . . . . . . . . . . . . . . . . 188
12.5.4 Sub-circuits for SC-circuits . . . . . . . . . 189
12.5.5 Example . . . . . . . . . . . . . . . . . . . 193
13 Oversampling and Sigma-Delta ADCs 195

13.1 ADC state-of-the-art . . . . . . . . . . . . . . . . . 195
13.1.1 What makes a state-of-the-art ADC . . . . 196
13.1.2 High resolution FOM . . . . . . . . . . . . 203
13.2 Quantization . . . . . . . . . . . . . . . . . . . . . 204
13.2.1 Signal to Quantization noise ratio . . . . . 208
13.2.2 Understanding quantization . . . . . . . . 208
13.2.3 Why you should care about quantization
noise . . . . . . . . . . . . . . . . . . . . . 211
13.3 Oversampling . . . . . . . . . . . . . . . . . . . . 211
13.3.1 Noise power . . . . . . . . . . . . . . . . . 212
13.3.2 Signal power . . . . . . . . . . . . . . . . . 213
13.3.3 Signal to Noise Ratio . . . . . . . . . . . . 213
13.3.4 Signal to Quantization Noise Ratio . . . . 213
13.3.5 Python oversample . . . . . . . . . . . . . 214
13.4 Noise Shaping . . . . . . . . . . . . . . . . . . . . 215
13.4.1 The magic of feedback . . . . . . . . . . . 215
13.4.2 Sigma-delta principle . . . . . . . . . . . . 216
13.4.3 Signal transfer function . . . . . . . . . . . 218
13.4.4 Noise transfer function . . . . . . . . . . . 219
13.4.5 Combined transfer function . . . . . . . . 219
13.5 First-Order Noise-Shaping . . . . . . . . . . . . . 219
13.5.1 SQNR and ENOB . . . . . . . . . . . . . . 221
13.6 Examples . . . . . . . . . . . . . . . . . . . . . . . 222
13.6.1 Python noise-shaping . . . . . . . . . . . . 222
13.6.2 The wonderful world of SD modulators . . 224
14 Voltage regulation 231
14.1 Voltage source . . . . . . . . . . . . . . . . . . . . 231
14.1.1 Core voltage . . . . . . . . . . . . . . . . . 235
14.1.2 IO voltage . . . . . . . . . . . . . . . . . . 236
14.1.3 Supply planning . . . . . . . . . . . . . . . 236
14.2 Linear Regulators . . . . . . . . . . . . . . . . . . 237
14.2.1 PMOS pass-fet . . . . . . . . . . . . . . . . 237
14.2.2 NMOS pass-fet . . . . . . . . . . . . . . . . 239
14.2.3 Control of pass-fet . . . . . . . . . . . . . . 239
14.3 Switched Regulators . . . . . . . . . . . . . . . . . 241
14.3.1 Principles of switched regulators . . . . . 242
14.3.2 Inductive DC/DC converter details . . . . 245
14.3.3 Pulse width modulation (PWM) . . . . . . 246
14.3.4 Real world use . . . . . . . . . . . . . . . . 248
14.3.5 Pulsed Frequency Mode (PFM) . . . . . . 249
14.4.1 Linear regulators . . . . . . . . . . . . . . 252
14.4.2 DC-DC converters . . . . . . . . . . . . . . 252
15 Clocks and PLLs 253

15.1 Why clocks? . . . . . . . . . . . . . . . . . . . . . 253
15.1.1 A customer story . . . . . . . . . . . . . . 253
15.1.2 Frequency . . . . . . . . . . . . . . . . . . 255
15.1.3 Noise . . . . . . . . . . . . . . . . . . . . . 255
15.1.4 Stability . . . . . . . . . . . . . . . . . . . . 255
15.1.5 Conclusion . . . . . . . . . . . . . . . . . . 255
15.2 A typical System-On-Chip clock system . . . . . . 256
15.2.1 32 MHz crystal . . . . . . . . . . . . . . . . 256
15.2.2 32 KiHz crystal . . . . . . . . . . . . . . . 257
15.2.3 PCB antenna . . . . . . . . . . . . . . . . . 257
15.2.4 DC/DC inductor . . . . . . . . . . . . . . 257
15.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 259
15.3.1 Integer PLL . . . . . . . . . . . . . . . . . . 260
15.3.2 Fractional PLL . . . . . . . . . . . . . . . . 261
15.3.3 Modulation in PLLs . . . . . . . . . . . . . 261
15.4 PLL Example . . . . . . . . . . . . . . . . . . . . . 262
15.4.1 Loop gain . . . . . . . . . . . . . . . . . . . 264
15.4.2 Controlled oscillator . . . . . . . . . . . . . 264
15.4.3 Phase detector and charge pump . . . . . 266
15.4.4 Loop filter . . . . . . . . . . . . . . . . . . 267
15.4.5 Divider . . . . . . . . . . . . . . . . . . . . 267
15.4.6 Loop transfer function . . . . . . . . . . . 268
16 Oscillators 273
16.1 Atomic clocks . . . . . . . . . . . . . . . . . . . . 273
16.1.1 Microchip 5071B Cesium Primary Time and
Frequency Standard . . . . . . . . . . . . . 273
16.1.2 Rubidium standard . . . . . . . . . . . . . 274
16.2 Crystal oscillators . . . . . . . . . . . . . . . . . . 276
16.2.1 Impedance . . . . . . . . . . . . . . . . . . 279
16.2.2 Circuit . . . . . . . . . . . . . . . . . . . . 280
16.2.3 Temperature behavior . . . . . . . . . . . . 282
16.3 Controlled Oscillators . . . . . . . . . . . . . . . . 283
16.3.1 Ring oscillator . . . . . . . . . . . . . . . . 283
16.3.2 Capacitive load . . . . . . . . . . . . . . . 285
16.3.3 Realistic . . . . . . . . . . . . . . . . . . . . 285
16.3.4 Digitally controlled oscillator . . . . . . . 288
16.3.5 Differential . . . . . . . . . . . . . . . . . . 288
16.3.6 LC oscillator . . . . . . . . . . . . . . . . . 289
16.4 Relaxation oscillators . . . . . . . . . . . . . . . . 291
16.5.1 Crystal oscillators . . . . . . . . . . . . . . 292
16.5.2 CMOS oscillators . . . . . . . . . . . . . . 292
17 Low Power Radio 293

17.1 Data Rate . . . . . . . . . . . . . . . . . . . . . . . 293
17.1.1 Data . . . . . . . . . . . . . . . . . . . . . . 293
17.1.2 Rate . . . . . . . . . . . . . . . . . . . . . . 294
17.1.3 Data Rate . . . . . . . . . . . . . . . . . . . 294
17.2 Carrier Frequency & Range . . . . . . . . . . . . . 294
17.2.1 ISM (industrial, scientific and medical) bands 294
17.2.2 Antenna . . . . . . . . . . . . . . . . . . . 295
17.2.3 Range (Friis) . . . . . . . . . . . . . . . . . 296
17.2.4 Range (Free space) . . . . . . . . . . . . . . 297
17.2.5 Range (Real world) . . . . . . . . . . . . . 297
17.3 Power supply . . . . . . . . . . . . . . . . . . . . . 298
17.3.1 Battery . . . . . . . . . . . . . . . . . . . . 298
17.4 Decisions . . . . . . . . . . . . . . . . . . . . . . . 299
17.4.1 Modulation . . . . . . . . . . . . . . . . . . 299
17.4.2 BPSK . . . . . . . . . . . . . . . . . . . . . 300
17.4.3 Single carrier, or multi carrier? . . . . . . . 307
17.4.4 Use a Software Defined Radio . . . . . . . 308
17.5 Bluetooth . . . . . . . . . . . . . . . . . . . . . . . 309
17.5.1 Bluetooth Basic Rate/Extended Data rate . 310
17.5.2 Bluetooth Low Energy . . . . . . . . . . . 310
17.6 Algorithm to design state-of-the-art LE radio . . . 312
17.6.1 LNTA . . . . . . . . . . . . . . . . . . . . . 313
17.6.2 MIXER . . . . . . . . . . . . . . . . . . . . 314
17.6.3 AAF . . . . . . . . . . . . . . . . . . . . . . 316
17.6.4 ADC . . . . . . . . . . . . . . . . . . . . . 316
17.6.5 AD-PLL . . . . . . . . . . . . . . . . . . . . 318
17.6.6 Baseband . . . . . . . . . . . . . . . . . . . 319
17.7 What do we really want, in the end? . . . . . . . . 319
18 Energy Sources 323
18.1 Thermoelectric . . . . . . . . . . . . . . . . . . . . 325
18.1.1 Radioisotope Thermoelectric generator . . 329
18.1.2 Thermoelectric generators . . . . . . . . . 330
18.2 Photovoltaic . . . . . . . . . . . . . . . . . . . . . 331
18.3 Piezoelectric . . . . . . . . . . . . . . . . . . . . . 333
18.4 Electromagnetic . . . . . . . . . . . . . . . . . . . 335
18.4.1 “Near field” harvesting . . . . . . . . . . . 335
18.4.2 Ambient RF Harvesting . . . . . . . . . . . 336
18.5 Triboelectric generator . . . . . . . . . . . . . . . . 337
18.6 Comparison . . . . . . . . . . . . . . . . . . . . . 340
19 Analog SystemVerilog 343

19.1 Digital simulation . . . . . . . . . . . . . . . . . . 345
19.2 Transient analog simulation . . . . . . . . . . . . 348
19.3 Mixed signal simulation . . . . . . . . . . . . . . . 349
19.4 Analog SystemVerilog Example . . . . . . . . . . 351
19.4.1 TinyTapeout TT06_SAR . . . . . . . . . . . 351
19.4.2 SAR operation . . . . . . . . . . . . . . . . 352
20 How to write a project report 357

20.1 Why . . . . . . . . . . . . . . . . . . . . . . . . . . 357
20.2 On writing English . . . . . . . . . . . . . . . . . 357
20.2.1 Shorter is better . . . . . . . . . . . . . . . 357
20.2.2 Be careful with adjectives . . . . . . . . . . 358
20.2.3 Use paragraphs . . . . . . . . . . . . . . . 358
20.2.4 Don’t be afraid of I . . . . . . . . . . . . . . 358
20.2.5 Transitions are important . . . . . . . . . . 358
20.2.6 However, is not a start of a sentence . . . . 359
20.3 Report Structure . . . . . . . . . . . . . . . . . . . 359
20.3.1 Introduction . . . . . . . . . . . . . . . . . 359
20.3.2 Theory . . . . . . . . . . . . . . . . . . . . 360
20.3.3 Implementation . . . . . . . . . . . . . . . 360
20.3.4 Result . . . . . . . . . . . . . . . . . . . . . 360
20.3.5 Discussion . . . . . . . . . . . . . . . . . . 360
20.3.6 Future work . . . . . . . . . . . . . . . . . 361
20.3.7 Conclusion . . . . . . . . . . . . . . . . . . 361
20.3.8 Appendix . . . . . . . . . . . . . . . . . . . 361
20.4 Checklist . . . . . . . . . . . . . . . . . . . . . . . 361
Background 1
In the spring of 2025 I lectured Advanced Integrated Circuits for
the fourth time. I have an inherent need to make things better, and
the course is no different.
In the first round I noticed that little of what I had on slides, or

said in lectures, made it into the student brain. That annoyed me,
and I realized that probably a few things needed to change.
I think the lectures have gotten better, but I don’t have any specific
proof. There were 19 students that took the exam in 2024. An
indication of lecture quality could be attendance. I don’t have all
the dates, but an average attendance of 76 % I think is pretty OK.
Date Attendance
2024-02-02 19
2024-02-09 17
2024-02-16 16
2024-03-01 14
2024-03-07 14
2024-03-15 12
2024-03-22 13
2024-04-12 16
2024-04-19 10
For the third semester I finally felt I achieved a balance. I spent

Thursday’s preparing for the lecture, writing these notes, making
a YouTube video (so I’ll remember next year what I wanted to talk
about). I passed 1k subscribers. Friday’s I had the lecture and the
group work.
For the group work I forced students into groups, and I forced that
they for the first 5-10 minutes do a check-in. That I need to do next
year too.
For the check in, they had go around in the group and answer one
of the following questions:
▶ What is one thing that is going on in your life (personal or

professional)?
▶ What is one thing that you’re grateful for right now?
▶ What is something funny that happened?
2 1 Background
The check-in led to excellent team work for those students that
showed up.
For the fourth semester I’m making a few tweaks. Hopefully I’ll
get the same schedule (Thursday’s/Friday’s).
One change will be the grading of the project, I’ll be using github
actions to do the GDS,DRC,LVS,SIM and docs.
I love programming and automation. Not much makes me more

happy than using the same source (the slide markdowns), to
generate the lecture notes, to translate into the book your looking
at right now.
If you find an error in what I’ve made, then fork aic2024, fix ,
commit, push and create a pull request. That way, we use the
global brain power most efficiently, and avoid multiple humans
spending time on discovering the same error.
Introduction 2
2.1 Who . . . . . . . . . . . 3
2.1 Who
2.2 How I see our roles . . 3
2.3 I want you to learn
My name is the skills necessary to
make your own ICs . . 4
Carsten Wulff [email protected]
2.4 There will always be
I finished my Masters in 2002, and did a Ph.D on analog-to-digital analog circuits, be-
converters finished in 2008. cause the real world is
analog . . . . . . . . . . 5
Since that time, I’ve had a three axis in my work/hobby life. 2.4.1 Will you tape-out an
IC? . . . . . . . . . . . . 9
I work at Nordic Semiconductor where I’ve been since 2008. The 2.4.2 What the team needs to
first 7 years I did analog design (ADCs, DC/DCs, GPIO). The next know to design ICs . . 9
7 years I was the Wireless Group Manager. The Wireless group 2.4.3 Zen of IC design (stolen
make most of the analog and RF designs for Nordic’s short-range from Zen of Python) . 10
products. Now I’m the IC Scientist, and focus on technical issues 2.4.4 IC design mantra . . . 10
with our integrated circuits that occur before we go into volume 2.4.5 Analog Design Process 11
production. 2.5 My Goal . . . . . . . . . 11
2.6 Syllabus . . . . . . . . . 12
I work at NTNU where I did a part time postdoc from 2014 - 2017. 2.7 JNW (2025) . . . . . . . 13
From 2020 I’ve been working on and teaching Advanced Integrated 2.7.1 Grading . . . . . . . . . 15
Circuits 2.7.2 Group dynamics . . . . 15
2.8 Software . . . . . . . . 16
I have a hobby trying to figure out how to make a new analog
circuit design paradigm. The one we have today with schemat-
ic/simulation/layout/verification/simulation is too slow
Summer intern First book University
Mom died chapter
NTNU of
Toronto
Started NTNU First paper, 2. dan ITF
Bought first Started Taekwon-do Compiled
Aruba
book on 1. dan ITF Met ex wife Nordic ADC,
Senior R & D Wireless ESSCIRC16
electronics Taekwon-do
Finished group
A year in Master Started Ph.D engineer
manager
Army, HTV Ph.D Post.Doc
Australia Got Post.Doc
Son End
Twins Start Rando Associate
Born First PC born Married born
Divorced
Professor IC Scientist
6a
1976 1986 1991 1996 2001 2006 2011 2016 2021 2026
Compiled
RX_ADC, ADC,JSSC
nRF52 SAADC,
ADC, nRF52 DC/DC Bluetooth
nRF51 DC/DC, nRF91 SIG CSWG
nRF52
2.2 How I see our roles
Professors: Guide students on what is impossible, possible, and

hints on what might be possible
Ph.D students: Venture into the unknown and make something

(more) possible
Master students: Learn all that is currently possible

4 2 Introduction
Bachelor students: Learn how to make complicated into easy
Industry: Take what is possible, and/or complicated, and make it

easy
2.3 I want you to learn the skills necessary to

make your own ICs
In 2020 the global integrated circuit market was 437.7 billion

dollars! The market is expected to grow to 1136 billion in 2028.
Integrated circuits enable pretty much all technologies.
I will be dead in approximately 50 years, and will retire in approx-

imately 20 years. Everything I know will be gone (except for the
small pieces I’ve left behind in videos or written word)
Someone must take over, and to do that, they need to know most
of what I know, and hopefully a bit more.
That’s were some of you come in. Some of you will find integrated
circuits interesting to make, and in addition, you have the stamina,
2.4 There will always be analog circuits, because the real world is analog 5
patience, and brain necessary to learn some of the hardest topics

in the world.
Making integrated circuits (that work reliably) is not

rocket science, it’s much harder.
In this course, we’ll focus on analog ICs, because the real world is
analog, and all ICs must have some analog components, otherwise
they won’t work.
2.4 There will always be analog circuits,

because the real world is analog
Status Abstraction Design Layout Why

:construction:Chip SystemVerilog
digital Complex
con-
nec-
tions,
few
ana-
log
inter-
faces
:construction:Module SystemVerilog
digital Large
amount
of
digital
sig-
nals,
few
ana-
log
sig-
nals
:warning: Block Schematic programmaticLarge
amount
of crit-
ical
ana-
log
inter-
faces,
few
digital
6 2 Introduction
Status Abstraction Design Layout Why

:white_- Cell Netlist/JSONcompiled Few
check_- ana-
mark: log
inter-
faces,
few
digital
inter-
faces
:white_- Device JSON compiled Polygon
check_- push-
mark: ing
:white_- Technology JSON/Rules compiled Custom
check_- for
mark: each
tech-
nol-
ogy
https://circuitcellar.com/insights/tech-the-future/kinget-the
-world-is-analog/
The steps to make integrated circuits is split in two. We have an

analog flow, and a digital flow.
It’s rare to find a single human that do both flows well. Usually
people choose, and I think it’s based on what they like and their
personality.
If you like the world to be ordered, with definite answers, then it’s
likely that you’ll find the digital flow interesting.
If you’re comfortable with not knowing, and an insatiable desire

to understand how the world really works at a fundamental level,
then it’s likely that you’ll find analog flow interesting.
8 2 Introduction
2.4.1 Will you tape-out an IC?
Something that would make me really happy is if someone is able

to tapeout an IC in this course.
It’s now possible without signing an NDA or buying expensive

software licenses.
In 2020 Google and Skywater joined forces to release a 130 nm

process design kit to the public. In addition, they have fueled a
renaissance of open source software tools.
Together with Efabless there are cheap alternatives, like tinytapeout,

which makes it possible for a private citizen to tape-out their own
integrated circuit.
2.4.2 What the team needs to know to design ICs
There are a multitude of tools and skills needed to design pro-

fessional ICs. It’s not likely that you’ll find all the skills in one
human, and even if you could, one human does not have suffi-
cient bandwidth to design ICs with all it’s aspects in a reasonable
timeline
That is, unless we can find a way to make ICs easier.
The skills needed are
▶ Project flow support: Confluence, JIRA, risk management

(DFMEA), failure analysis (8D)
▶ Language: English, Writing English (Latex, Word, Email)
▶ Psychology: Personalities, convincing people, presentations
(Powerpoint, Deckset), stress management (what makes
your brain turn off?)
▶ DevOps: Linux, bulid systems (CMake, make, ninja), con-
tinuous integration (bamboo, jenkins), version control (git),
containers (docker), container orchestration (swarm, kuber-
netes)
▶ Programming: Python, C, C++, Matlab Since 1999 I’ve pro-
grammed in Python, Go, Visual BASIC, PHP, Ruby, Perl, C#,
SKILL, Ocean, Verilog-A, C++, BASH, AWK, VHDL, SPICE,
MATLAB, ASP, Java, C, SystemC, Verilog, Assembler, and
probably a few I’ve forgotten.
▶ Firmware: signal processing, algorithms, software architec-
ture, security
▶ Infrastructure: Power management, reset, bias, clocks
▶ Domains: CPUs, peripherals, memories, bus systems
▶ Sub-systems: Radio’s, analog-to-digital converters, compara-
tors
10 2 Introduction
▶ Blocks: Analog Radio, Digital radio baseband

▶ Modules: Transmitter, receiver, de-modulator, timing recov-
ery, state machines
▶ Designs: Opamps, amplifiers, current-mirrors, adders, ran-
dom access memory blocks, standard cells
▶ Tools: schematic, layout, parasitic extraction, synthesis, place-
and-route, simulation, (System)Verilog, netlist
▶ Physics: transistor, pn junctions, quantum mechanics
2.4.3 Zen of IC design (stolen from Zen of Python)
When you learn something new, it’s good to listen to someone that
has done whatever it is before.
Here is some guiding principles that you’ll likely forget.
▶ Beautiful is better than ugly.

▶ Explicit is better than implicit.
▶ Simple is better than complex.
▶ Complex is better than complicated.
▶ Readability counts (especially schematics).
▶ Special cases aren’t special enough to break the rules.
▶ Although practicality beats purity.
▶ In the face of ambiguity, refuse the temptation to guess.
▶ There should be one and preferably only one obvious way
to do it.
▶ Now is better than never.
▶ Although never is often better than right now.
▶ If the implementation is hard to explain, it’s a bad idea.
▶ If the implementation is easy to explain, it may be a good
idea.
2.4.4 IC design mantra
To copy an old mantra I have on learning programming
Find a problem that you really want to solve, and learn

programming to solve it. There is no point in saying
“I want to learn programming”, then sit down with a
book to read about programming, and expect that you
will learn programming that way. It will not happen.
The only way to learn programming is to do it, a lot. –
Carsten Wulff
And run the perl program
s/programming/analog design/ig
2.5 My Goal 11
2.4.5 Analog Design Process
▶ Define the problem, what are you trying to solve?

▶ Find a circuit that can solve the problem (papers, books)
▶ Find right transistor sizes. What transistors should be weak
inversion, strong inversion, or don’t care?
▶ Write a verification plan. Plan to simulate everything that
could go wrong.
▶ Check operating region of transistors (.op)
▶ Check key parameters (.dc, .ac, .tran)
▶ Check function. Exercise all inputs. Check all control signals
▶ Check key parameters in all corners. Check mismatch (Monte-
Carlo simulation)
▶ Do layout, and check it’s error free. Run design rule checks
(DRC). Check layout versus schematic (LVS)
▶ Extract parasitics from layout. Resistance, capacitance, and
inductance if necessary.
▶ On extracted parasitic netlist, check key parameters in all
corners and mismatch (if possible).
▶ If everything works, then your done.
On failure, go back as far as necessary
2.5 My Goal
Don’t expect that I’ll magically take information and put it inside
your head, and you’ll suddenly understand everything about
making ICs.
You are the one that must teach yourself everything.
I consider my role as a guide, similar to a mountain guide. I can’t

carry you up the mountain, you need to walk up the mountain ,
but I know the safe path to take and increase the likelihood that
you’ll come back alive.
I want to:
▶ Enable you to read the books on integrated circuits

▶ Enable you to read papers (latest research)
▶ Correct misunderstandings on the topic
▶ Answer any questions you have on the chapters
I’m not a mind reader, I can’t see inside your head. That means,
you must ask questions, only by your questions can I start to
understand what pieces of information is missing from your head,
or maybe somehow to correct your understanding.
12 2 Introduction
At the same time, and similar to a mountain guide, you should not
assume I’m always right. I’m human, and I will make mistakes.
And maybe you can correct my understanding of something. All I
care about is to really understand how the world works, so if you
think my understanding is wrong, then I’ll happily discuss.
2.6 Syllabus
The syllabus will be from Analog Integrated Circuit Design (CJM)

and Circuits for all seasons.
These lecture notes are a supplement to the book. I try to give some
background, and how to think about electronics. It’s not my goal
to repeat information that you can find in the book.
Buy a hard-copy of the book if you don’t have that. Don’t expect to
understand the book by reading the PDF.
2.7 JNW (2025) 13
2.7 JNW (2025)
“You can use logic to justify almost anything. That’s its power.
And its flaw.” - Kathryn Janeway, Star Trek Voyager: Prime Fac-
tors
The project for 2025 is to
Design a integrated temperature sensor with digital read-out
An outline of the plan is shown below.
At the end of the project you will have a function that converts
temperature to a digital value.
𝐷 = 𝑓0 (𝑇)
14 2 Introduction
I’ve broken down the challenge into three steps, first convert
Temperature into a current
𝐼 = 𝑓1 (𝑇)
Then convert current into a time
𝑡 = 𝑓2 (𝐼)
then time to digital
𝐷 = 𝑓3 (𝑡) = 𝑓3 ( 𝑓2 ( 𝑓1 (𝑇))) = 𝑓0 (𝑇)
The third milestone is the layout, while the fourth milestone is the
report.
You can find an example of last years designs at cnr_gr02_-

sky130nm
You will be using a repository on github for all your design data.
In that repository I’ve made it possible to run github actions, or
github workflows. For each of the milestones there are associated
workflows (SIM/DOCS/GDS/DRC/LVS).
MI MY
RESET
I Emmet Report PDF
Pursue b
put 1414
Anna i
µ
REPO
Layout
M3
Milestone 0: The zero milestone is not really part of the project, but
it does introduce you too how you will work with the files in the
project. It’s important that you do this right away. To complete the
milestone, upload a link to blackboard with your github repository
for the tutorial Skywater 130 nm Tutorial
Milestone 1: The first milestone is to make a circuit that can convert

from a temperature, to a current that is proportional to temperature.
You will run a simulation on github that demonstrates that the
circuit works. That is the SIM workflow.
2.7 JNW (2025) 15
Milestone 2: In the second milestone you will complete the

schematic design of the circuit, and possibly also do some Sys-
temVerilog to demonstrate that you get a digital value out that
is proportional to temperature. Here, the simulations on github
may be too long, so it’s sufficient to describe the circuit, and how it
works in detail in the documentation. This is the DOC workflow.
Milestone 3: The third milestone, making the layout, is optional,

however, it will be impossible to get an A without getting some
points from the layout milestone. Once the layout is complete, I
expect that the design rule checks (DRC), Layout versus Schematic
(LVS), and GDS (stream out to a GDSII file) is passing on github.
Milestone 4: I will force you to work in groups. As such, it may be

that some contribute more than others. To ensure that the grading
is fair, the report will be indivirual. It’s OK to share figures, tables,
and so on, but the PDF shall be written by you and you alone.
2.7.1 Grading
Condition for
more than 0 Possible
Milestone
What does it mean points Points
M1 Circuit that can convert a SIM passing 10
I=f(T) temperature into a current
M2 Circuit that can convert from DOC passing 20
D=f(T) temperature into a digital
value
M3 Layout of your circuit DRC/LVS/GDS 20
Lay- passing
out
M4 Individual report Uploaded to 48
Re- blackboard
port
Cooleness
Extra points that I may 10
choose to award
Total 108
2.7.2 Group dynamics
How you work together is important. No-one can do everything by

them self. I know from experience it can be magical when bright
brains come together. The collective brain can be smarter, better,
faster, than anyone in the group.
16 2 Introduction
That’s why I think it’s important not to just work in groups, but
also focus on how we work in groups.
A group shall be maximum 4 members. There must be at least 3

that don’t know each-other that well.
The group will meet once per week in the exercise hours.
2.7.2.1 Check-in
All group session must start with a Check-in (10 minutes)
Some example questions could be
▶ Share one thing that is going on in your life (personal or

professional.)
▶ What is one thing that you are grateful for right now?
▶ What is something funny that happened?
Some examples answers could be: - My dog died yesterday, so

I’m not feeling great today. - I woke up early, had an omelet, and
went running, so I feel motivated and fantastic. - I feel blaaah today,
motivation is lacking. - I went running yesterday and did not
discover before I got home that I’d forgotten to put my pants on,
even though it was -10 C.
The point of this exercise is to get to know each other a bit, and
attempt to create psychological safety in the group.
2.8 Software
We’ll use professional Open source software (xschem, ngspice,

sky130A PDK, Magic VLSI, netgen)
I’ve made a rather detailed (at least I think so myself) tutorial on

how to make a current mirror with the open source tools. I strongly
recommend you start with that first.
Skywater 130 nm Tutorial
I’ve also made some more complex examples, that can be found at
the link below. There are digital logic cells, standard transistors,
and few other blocks.
aicex
A refresher 3
3.1 There are standard units of measurement 3.1 There are standard
units of measurement 17
3.2 Electrons . . . . . . . . . 18
All known physical quantities are derived from 7 base units (SI
3.3 Probability . . . . . . . 19
units)
3.4 Uncertainty principle . 20
▶ second (s) : time 3.5 States as a function of
▶ meter (m) : space time and space . . . . . 20
▶ kg (kilogram) : weight 3.6 Allowed energy levels
in atoms . . . . . . . . . 21
▶ ampere (A) : current
3.7 Allowed energy levels
▶ kelvin (K) : temperature
in solids . . . . . . . . . 21
▶ candela (cd) : luminous intensity
3.8 Silicon Unit Cell . . . . 22
All other units (for example volts), are derived from the base 3.9 Band structure . . . . . 23
units. 3.10 Valence band and
Conduction band . . . 24
I don’t go around remembering all of them, they are easily available
3.11 Fermi level . . . . . . . 24
online. When you forget the equation for charge (Q), voltage (V)
3.12 Metals . . . . . . . . . . 25
and capacitance (C), look at the units below, and you can see it’s
3.13 Insulators . . . . . . . . 26
𝑄 = 𝐶𝑉 ‗
3.14 Semiconductors . . . . 26
3.15 Band diagrams . . . . . 27
3.16 Density of electrons/-
holes . . . . . . . . . . . 27
3.17 Fields . . . . . . . . . . . 28
3.18 Permittivity and Per-
meability . . . . . . . . 28
3.19 Quantum electrody-
namics . . . . . . . . . . 29
3.20 Voltage . . . . . . . . . . 29
3.21 Current . . . . . . . . . 29
3.22 Drift current . . . . . . 30
3.23 Diffusion current . . . 31
3.24 Why are there two
currents? . . . . . . . . . 31
3.25 Currents in a semicon-
ductor . . . . . . . . . . 31
3.26 Resistors . . . . . . . . . 32
3.27 Capacitors . . . . . . . . 32
3.28 Inductors . . . . . . . . 32
‗ Although you do have to keep your symbols straight. We use “C” for Capacitance,
but C can also mean Columbs. Context matters.

18 3 A refresher
Figure 1: Si base units, from https://www.nist.gov/pml/owm/m

etric-si/si-units
3.2 Electrons
Electrons are fundamental, they cannot (as far as we know), be

divided into smaller parts. Explained further in the standard model
of particle physics
3.3 Probability 19
Standard Model of Elementary Particles

three generations of matter interactions / force carriers
(fermions) (bosons)
I II III
mass ≈2.2 MeV/c² ≈1.28 GeV/c² ≈173.1 GeV/c² 0 ≈125.11 GeV/c²
charge ⅔ ⅔ ⅔ 0 0
spin ½ u ½ c ½ t 1 g 0 H
up charm top gluon higgs
SCALAR BOSONS
QUARKS
≈4.7 MeV/c² ≈96 MeV/c² ≈4.18 GeV/c² 0
γ
−⅓ −⅓ −⅓ 0
½ d ½ s ½ b 1
down strange bottom photon
≈0.511 MeV/c² ≈105.66 MeV/c² ≈1.7768 GeV/c² ≈91.19 GeV/c²
GAUGE BOSONS
μ τ
−1 −1 −1 0
½ e ½ ½ 1 Z
electron muon tau Z boson
VECTOR BOSONS
LEPTONS
<1.0 eV/c² <0.17 MeV/c² <18.2 MeV/c² ≈80.360 GeV/c²

0
½ νe 0
½ νμ 0
½ ντ ±1
1 W
electron muon tau
neutrino neutrino neutrino
W boson
Figure 2: Standard model of particle physics, Wikipedia
Electrons have a negative charge of 𝑞 ≈ 1.602 × 10−19 . The proton

a positive charge. The two charges balance exactly! If you have
a trillion electrons and a trillion protons inside a volume, the
net external charge will be 0 (assuming we measure from some
distance away). I find this fact absolutely incredible. There must be
a fundamental connection between the charge of the proton and
electron. It’s insane that the charges balance out so exactly.
All electrons are the same, although the quantum state can be
different.
An electron cannot occupy the same quantum state as another.

This rule that applies to all Fermions (particles with spin of 1/2)
The quantum state of an electron is fully described by it’s spin,

momentum (p) and position in space (r).
3.3 Probability
The probability of finding an electron in a state as a function of

space and time is
20 3 A refresher
𝑃 = |𝜓(𝑟, 𝑡)|2
, where 𝜓 is named the probability amplitude, and is a complex

function of space and time. In some special cases, it’s
𝜓(𝑟, 𝑡) = 𝐴𝑒 𝑖(𝑘𝑟−𝜔𝑡)
, where A is complex number, k is the wave number, r is the position

vector from some origin, 𝜔 is the frequency and 𝑡 is time.
The energy is 𝐸 = ℏ𝜔 , where ℏ = ℎ/2𝜋 and ℎ is Planck Constant

and the momentum is 𝑝 = ℏ𝑘
The probability amplitude is also called the wave function. Type

of wave function depends on the scenario, and does not have to
take on the solution above. The possible wave functions are those
equations that fits with the time evolution of quantum states given
by the Schrodinger equation.
3.4 Uncertainty principle
We cannot, with ultimate precision, determine both the position

and the momentum of a particle, the precision is
ℏ
𝜎𝑥 𝜎𝑝 ≥
2
From the uncertainty (Unschärfe) principle we can actually estimate

the size of the atom
3.5 States as a function of time and space
The time-evolution of the probability amplitude is
𝑑
𝑖ℏ 𝜓(𝑟, 𝑡) = 𝐻𝜓(𝑟, 𝑡)
𝑑𝑡
, where H is named the Hamiltonian matrix, or the energy matrix or

(if I understand correctly) the amplitude matrix of the probability
amplitude to change from one state to another.
For example, if we have a system with two states, a simplified

version of two electrons shared between two atoms, as in 𝐻2 , or
hydrogen gas, or co-valent bonds, then the Hamiltonian is a 2 x 2
matrix. And the 𝜓 is a vector of [𝜓1 , 𝜓2 ]
3.6 Allowed energy levels in atoms 21
Computing the solution to the Schrodinger Equation can be tricky,

because you must know the number of relevant states to know the
vector size of 𝜓 and the matrix size of 𝐻 . In addition, the 𝐻 can be
a function of time and space (I think).
Compared to the equations of electric fields, however, Schrodinger

is easy, it’s a set of linear differential equations.
3.6 Allowed energy levels in atoms
Solutions to Schrodinger result in quantized energy levels for an

electron bound to an atom.
Take hydrogen, the electron bound to the proton can only exists
in quantized energy levels. The lowest energy state can have two
electrons, one with spin up, and one with spin down.
From Schrodinger you can compute the energy levels, which most
of us did at some-point, although now, I can’t remember how it
was done. That’s not important. The important is to internalize
that the energy levels in bound electrons are discrete.
Electrons can transition from one energy level to another by external

influence, i.e temperature, light, or other.
The probability of a state transition (change in energy) can be

determined from the probability amplitude and Schrodinger.
3.7 Allowed energy levels in solids
If I have two silicon atoms spaced far apart, then the electrons can
have the same spin and same momentum around their respective
nuclei. As I bring the atoms closer, however, the probability am-
plitudes start to interact (or the dimensions of the Hamiltonian
matrix grow), and there can be state transitions between the two
electrons.
The allowed energy levels will split. If I only had two states
interacting, the Hamiltonian could be
𝐴 0

𝐻=
0 −𝐴
and the new energy levels could be
𝐸1 = 𝐸0 + 𝐴
22 3 A refresher
and
𝐸2 = 𝐸0 − 𝐴
In a silicon crystal we can have trillions of atoms, and those that

are close, have states that interact. That’s why crystals stay solids.
All chemical bonds are states of electrons interacting! Some are
strong (co-valent bonds), some are weaker (ionic bonds), but it’s
all quantum states interacting.
The discrete energy levels of the electron transition into bands of

allowed energy states.
Figure 3: Electronic band structure, Wikipedia
For a crystal, the allowed energy bands is captured in the band

structure
3.8 Silicon Unit Cell
A silicon crystal unit cell is a diamond faced cubic with 8 atoms in

the corners spaced at 0.543 nm, 6 at the center of the faces, and 4
atoms inside the unit cell at a nearest neighbor distance of 0.235
nm.
3.9 Band structure 23
Figure 4: Silicon, Wikipedia
3.9 Band structure
The full band structure of a silicon unit cell is complicated, it’s a 3

dimensional concept
24 3 A refresher
Figure 5: Silicon Band Structure
3.10 Valence band and Conduction band
For bulk silicon we simplify, and we think of two bands, the

conduction band, and valence band
In the conduction band (𝐸𝐶 ) is the lowest energy where electrons

are free (not bound to atoms). The valence band (𝐸𝑉 ) is the highest
band where electrons are bound to silicon atoms.
The difference between 𝐸𝐶 and 𝐸𝑉 is a property of the material

we’ve named the band gap.
𝐸𝐺 = 𝐸𝐶 − 𝐸𝑉
3.11 Fermi level
From Wikipedia’s Fermi level
In band structure theory, used in solid state physics to

analyze the energy levels in a solid, the Fermi level can
be considered to be a hypothetical energy level of an
3.12 Metals 25
electron, such that at thermodynamic equilibrium this

energy level would have a 50% probability of being
occupied at any given time
The Fermi level is closely linked to the Fermi-Dirac distribution
1
𝑓 (𝐸) =
𝑒 (𝐸−𝐸𝐹 )/𝑘𝑇 + 1
If the energy of the state is more than a few kT away from the
Fermi-level, then
𝑓 (𝐸) ≈ 𝑒 (𝐸𝐹 −𝐸)/𝑘𝑇
The equation above is one of the reasons the structure 𝑒 𝐸/𝑘𝑇 or

𝑒 𝑞𝑉/𝑘𝑇 shows up all over the place. You’ll see it in the equations
for current in a diode, 𝐼𝐷 = 𝐼 𝑠 (𝑒 𝑞𝑉𝐷 /𝑛 𝑘𝑇 − 1), the subthreshold
conduction of a mosfet 𝐼𝐷 ∝ 𝑒 𝑞𝑉𝑔𝑠 /𝑛 𝑘𝑇 and even the Arrhenius
Equation 𝑘 = 𝐴𝑒 −𝐸 𝑎 /𝑘𝑇 .
It seems like any time you have something related to chemical

reactions (state transitions of electrons, breaking bonds, forming
bonds), or current in solids, there is a relation to the equation
above. To me, that makes sense.
The Fermi-Dirac function also explains why there are more free
carriers, and reaction rates increase, at high temperature. The
part of the equation that is 𝑒 −𝐸/𝑘𝑇 will approach one at high
temperatures.
3.12 Metals
In metals, the band splitting of the energy levels causes the valence
band and conduction band to overlap.
26 3 A refresher
Figure 6: Band splitting in materials. Electronic Band Structure,

Wikipedia
Electrons can easily transition between bound state and free state.
As such, electrons in metals are shared over large distances, and
there are many electrons readily available to move under an applied
field, or difference in electron density. That’s why metals conduct
well.
3.13 Insulators
In insulating materials the difference between the conduction band

and the valence band is large. As a result, it takes a large energy to
excite electrons to a state where they can freely move.
That’s why glass is transparent to optical frequencies. Visible light

does not have sufficient energy to excite electrons from a bound
state.
That’s also why glass is opaque to ultra-violet, which has enough

energy to excite electrons out of a bound state.
Based on these two pieces of information you could estimate the

bandgap of glass.
from scipy import constants

#- We must use the "correct" units for planck's constant to get ene
h = constants.physical_constants["Planck constant in eV/Hz"][0]
c = constants.physical_constants["speed of light in vacuum"][0]
lambda_optical = 450e-9
e_optical = h * c/lambda_optical
lambda_ultra = 380e-9
e_ultra = h * c/lambda_ultra
print("Bandgap of glass is above %.2f eV, maybe around %.2f eV " %(
3.14 Semiconductors
In silicon the bandgap is lower than an insulator, approximately
𝐸𝐺 = 1.12 𝑒𝑉
At room temperature, that allows a small number of electrons to

be excited into the conduction band, leaving behind a “hole” in
the valence band.
3.15 Band diagrams 27
3.15 Band diagrams
A band diagram or energy level diagrams shows the conduction

band energy and valence band energy as a function of distance in
the material.
Figure 7: Band diagram of a PN junction, Wikipedia
The horizontal axis is the distance in the material, the vertical axis
is the energy.
3.16 Density of electrons/holes
There are two components needed to determine how many elec-

trons are in the conduction band. The density of available states,
and the probability of an electron to be in that quantum state.
The probability is the Fermi-Dirac distribution. The density of

available states is a complicated calculation from the band-structure
of silicon.
For details see the Diodes chapter.
∫ ∞
𝑛𝑒 = 𝑁(𝐸) 𝑓 (𝐸)𝑑𝐸
𝐸𝐶
The Fermi level is assumed to be independent of energy level, so

we can write
∫ ∞
𝐸𝐹 /𝑘𝑇
𝑛𝑒 = 𝑒 𝑁(𝐸)𝑒 −𝐸/𝑘𝑇 𝑑𝐸
𝐸𝐶
for the density of electrons in the conduction band.

28 3 A refresher
3.17 Fields
There are equations that relate electric field, magnetic field, charge
density and current density to each-other.
∮ ∭
1
E · 𝑑S = 𝜌 · 𝑑𝑉
𝜕Ω 𝜖0 𝑉
,relates net electric flux to net enclosed electric charge
∮
B · 𝑑S = 0
𝜕Ω
,relates net magnetic flux to net enclosed magnetic charge
𝑑
∮ ∬
E · 𝑑ℓ = − B · 𝑑S
𝜕Σ 𝑑𝑡 Σ
,relates induced electric field to changing magnetic flux
𝑑
∮ ∬ ∬
B · 𝑑ℓ = 𝜇0 J · 𝑑S + 𝜖0 E · 𝑑S
𝜕Σ Σ 𝑑𝑡 Σ
,relates induced magnetic field to changing electric flux and to

current
These are the Maxwell Equations, and are non-linear time depen-
dent differential equations.
Under the best of circumstances they are fantastically hard to solve!

But it’s how the real world works.
3.18 Permittivity and Permeability
The permittivity of free space is defined as
1
𝜖0 =
𝜇0 𝑐 2
, where 𝑐 is the speed of light, and 𝜇0 is the vacuum permeability,

which, in SI units, is now
2𝛼 ℎ
𝜇0 =
𝑞2 𝑐
, where 𝛼 is the fine structure constant.

3.19 Quantum electrodynamics 29
3.19 Quantum electrodynamics
The quantum electrodynamics (QED) is a full description of in-

teractions between light and matter. The equations describe both
quantum mechanical effects, electromagnetism and is in agreement
with special relativity.
The equations are rather complicated, but it’s based on Lagrangian

physics. Maxwell’s equations actually fall out of the QED La-
grangian when one assumes local phase symmetry.
The QED Lagrangian is
¯
L = 𝜓[𝑖ℏ𝑐𝛾 𝜇 ¯ 𝜇 𝜓]𝐴𝜇 − 1 𝐹𝜇𝜈 𝐹 𝜇𝜈
𝜕𝜇 − 𝑚𝑐 2 ]𝜓 − 𝑞[𝜓𝛾
16𝜋
For more information, have a look at Electromagnetism as a Gauge

Theory
3.20 Voltage
The electric field has units voltage per meter, so the electric field is
the derivative of the voltage as a function of space.
𝑑𝑉
𝐸=
𝑑𝑥
3.21 Current
Current has unit 𝐴 and charge 𝐶 has unit 𝐴𝑠 , so the current is the
number of charges passing through a volume per second.
The current density 𝐽 has units 𝐴/𝑚 2 and is often used, since we
can multiply by the surface area of a conductor, if the current
density is uniform.
𝐼 =𝐴×𝐽
30 3 A refresher
3.22 Drift current
Charge carriers (electrons, holes, ions) in an electric field will give

rise to a drift current.
We know from Newtons laws that force equals mass times acceler-
ation
𝐹® = 𝑚®𝑎
If we assume a zero, or constant magnetic field, the force on a

particle is
𝐹® = 𝑞 𝐸®
The current density is then
®𝐽 = 𝑞 𝐸® × 𝑛 × 𝜇
where 𝑛 is the charge density, and 𝜇 is the mobility (how easily the
charges move) and has units 𝑚 2 /𝑉 𝑠
Assuming
𝐸 = 𝑉/𝑚
, we could write
𝐶 𝑉 𝑚2 𝐶
𝐽= = 𝑚 −2
𝑚 𝑚 𝑉𝑠
3 𝑠
So multiplying by an area A with unit meters squared
𝐼 = 𝑞𝑛𝜇𝐴𝑉
and we can see that the conductance
𝐺 = 𝑞𝑛𝜇𝐴
, and since
𝐺 = 1/𝑅
, where R is the resistance, we have

3.23 Diffusion current 31
𝐼 = 𝐺𝑉 ⇒ 𝑉 = 𝑅𝐼
Or Ohms law
3.23 Diffusion current
A difference in charge density will give rise to a diffusion current.

The current density is
𝑑𝜌
𝐽 = −𝑞𝐷𝑛
𝑑𝑥
,where 𝐷𝑛 is a diffusion constant, and 𝜌 is the charge density.
3.24 Why are there two currents?
I struggled with the concepts diffusion current and drift current

for a long time. Why are there two types of current? It was when I
read The Schrödinger Equation in a Classical Context: A Seminar
on Superconductivity I realized that the two types of current come
directly from the Schrodinger equation, there is one component
related to the electric field (potential energy) and a component
related to the momentum (kinetic energy).
In the absence of an electric field electrons will still jump from

state to state set by the probabilities of the Hamiltonian. If there
are more electrons in an area, then it will seem like there is an
average movement of charges away from that area. That’s how I
think about drift and diffusion currents. We can kinda see it from
the Schrödinger equation below.
ℏ2 𝜕 2 𝜕
− 𝜓(𝑥, 𝑡) + 𝑉(𝑥)𝜓(𝑥, 𝑡) = 𝑖ℏ 𝜓(𝑥, 𝑡)
2𝑚 𝜕 𝑥
2 𝜕𝑡
3.25 Currents in a semiconductor
Both electrons, and holes will contribute to current.
Electrons move in the conduction band, and holes move in the

valence band.
Both holes and electrons can only move if there are available
quantum states.
32 3 A refresher
For example, if the valence band is completely filled (all states

filled), then there can be no current.
To compute the total current in a semiconductor one must com-

pute
𝐼 = 𝐼𝑛 𝑑𝑟𝑖 𝑓 𝑡 + 𝐼𝑛 𝑑𝑖 𝑓 𝑓 𝑢𝑠𝑖𝑜𝑛 + 𝐼 𝑝 𝑑𝑟𝑖 𝑓 𝑡 + 𝐼 𝑝 𝑑𝑖 𝑓 𝑓 𝑢𝑠𝑖𝑜𝑛
where 𝑛 denotes electrons, and 𝑝 denote holes.
3.26 Resistors
We can make resistors with many materials. The behavior of the

charge carrier may be different between materials.
In metal the dominant carrier depends on the metal, but it’s usually
electrons. As such, one can often ignore the hole current.
In a semiconductor the dominant carrier depends on the Fermi

level in relation to the conduction band and valence band.
If the Fermi level is close to the valence band the dominant carrier
will be holes. If the Fermi level is close to the conduction band, the
dominant carrier will be electrons.
That’s why we often talk about “majority carriers” and “minority

carriers”, both are important in semiconductors.
3.27 Capacitors
A capacitor resists a change in voltage
𝑑𝑉
𝐼=𝐶
𝑑𝑡
and store energy in an electric field between two conductors with

an insulator between.
3.28 Inductors
An inductor resist a change in current
𝑑𝐼
𝑉=𝐿
𝑑𝑡
and store energy in the magnetic fields in a loop of a conductor.

Diodes 4
4.1 Why 4.1 Why . . . . . . . . . . . 33
4.2 Silicon . . . . . . . . . . 33
4.3 Intrinsic carrier con-
Diodes are a magical ‗ semiconductor device that conduct current
centration . . . . . . . . 35
in one direction. It’s one of the fundamental electronics components,
4.4 It’s all quantum . . . . 37
and it’s a good idea to understand how they work. 4.4.1 Density of states . . . . 38
If you don’t understand diodes, then you won’t understand tran- 4.4.2 How to think about
electrons (and holes) . 40
sistors, neither bipolar, or field effect transistors.
4.5 Doping . . . . . . . . . 41
A useful feature of the diode is the exponential relationship between 4.6 PN junctions . . . . . . 42
the forward current, and the voltage across the device. 4.6.1 Built-in voltage . . . . . 43
4.6.2 Current . . . . . . . . . 44
To understand why a diode works it’s necessary to understand the 4.6.3 Forward voltage tem-
physics behind semiconductors. perature dependence . 45
4.6.4 Current proportional to
This paper attempts to explain in the simplest possible terms how
temperature . . . . . . . 47
a diode works †
4.7 Equations aren’t real . 48
4.2 Silicon
Integrated circuits use single crystalline silicon. The silicon crystal

is grown with the Czochralski method which forms a ingot that is
cut into wafers. The wafer is a regular silicon crystal, although, it
is not perfect.
A silicon crystal unit cell, as seen in Figure 1 is a diamond faced

cubic with 8 atoms in the corners spaced at 0.543 nm, 6 at the
center of the faces, and 4 atoms inside the unit cell at a nearest
neighbor distance of 0.235 nm.
‗ It doesn’t stop being magic just because you know how it works. Terry Pratchett,
The Wee Free Men

† Simplify
as much as possible, but no more. Einstein
34 4 Diodes
Figure 1: Silicon crystal unit cell
As you hopefully know, the energy levels of an electron around

a positive nucleus are quantized, and we call them orbitals (or
shells). For an atom far away from any others, these orbitals, and
energy levels are distinct. As we bring atoms closer together, the
orbitals start to interact, and in a crystal, the distinct orbital energies
split into bands of allowed energy states. No two electrons, or any
Fermion (spin of 1/2), can occupy the same quantum state. We call
the outermost “shared” orbitial, or band, in a crystal the valence
band. Hence covalent bonds.
If we assume the crystal is perfect, then at 0 Kelvin all electrons

will be part of covalent bonds. Each silicon atom share 4 electrons
with its neighbors. What we really mean when we say “share 4
electrons” is that the wave-functions of the outer orbitals interact,
and we can no longer think of the orbitals as belonging to either of
the silicon nuclei. All the neighbors atoms “share” electrons, and
nowhere is there an vacant state, or a hole, in the valence band.
If such a crystal were to exist, where there were no holes in

the valence band, and a net neutral charge, the crystal could
not conduct any drift current. Electrons would move around
continuously, swapping states, but there could be no net drift of
charge carriers.
4.3 Intrinsic carrier concentration 35
In an atom, or a crystal, there are also higher energy states where

the carriers are “free” to move. We call these energy levels, or bands
of energy levels, conduction bands. In singular form “conduction
band”, refers to the lowest available energy level where the electrons
are free to move.
Due to imperfectness of the silicon crystal, and non-zero temper-

ature, there will be some electrons that achieve sufficient energy
to jump to the conduction band. The electrons in the conduction
band leave vacant states, or holes, in the valence band.
Electrons can move both in the conduction band, as free electrons,

and in the valence band, as a positive particle, or hole. Both bands
can support drift and diffusion currents.
4.3 Intrinsic carrier concentration
The intrinsic carrier concentration of silicon, or the density of free

electrons and holes at a given temperature, is given by
𝑁𝑐 𝑁𝑣 𝑒 −𝐸 𝑔 /(2 𝑘𝑇)
p
𝑛𝑖 = (1)
where 𝐸 𝑔 is the bandgap energy of silicon (approx 1.12 eV), 𝑘 is

Boltzmann’s constant, 𝑇 is the temperature in Kelvin, 𝑁𝑐 is the
density of states in conduction band, and 𝑁𝑣 is the density of states
in the valence band.
The density of states are
3/2
2𝜋𝑘𝑇𝑚 𝑝∗
3/2
2𝜋𝑘𝑇𝑚𝑛∗

𝑁𝑐 = 2 𝑁𝑣 = 2
ℎ2 ℎ2
where ℎ is Planck’s constant, 𝑚𝑛∗ is the effective mass of electrons,

and 𝑚 𝑝∗ is the effective mass of holes.
Leave it to engineers to simplify equations beyond understanding.

Equation (1) is complicated, and the density of states includes the
effective mass of electrons and holes, which is a parameter that
depends on the curvature of the band structure. To engineers, this
is too complicated, and 𝑛 𝑖 has been simplified so it “works” in
daily calculation.
Through engineering simplification, however, physics understand-

ing is lost.
In [1] they claim the intrinsic carrier concentration is a constant,

although they do mention 𝑛 𝑖 doubles every 11 degrees Kelvin.
36 4 Diodes
In BSIM 4.8 [2] the intrinsic carrier concentration is
r
𝑇𝑁 𝑂 𝑀 𝑇 𝐸𝑔
𝑛 𝑖 = 1.45𝑒 10 exp21.5565981− 2𝑘𝑇
300.15 300.15
Comparing the three models in Figure 2, we see the shape of BSIM

and the full equation is almost the same, while the “doubling every
11 degrees” is just wrong.
13
10
Advanced
Simple
12
10 BSIM 4.8
11
10
ni [1/cm3]
10
10
9
10
8
10
7
10
25 0 25 50 75 100 125
Figure 2: Intrinsic carrier concentration versus temperature
At room temperature the intrinsic carrier consentration is approxi-

mately 𝑛 𝑖 = 1 × 1016 carriers/m3 .
That may sound like a big number, however, if we calculate the

1016
electrons per 𝑢𝑚 3 it’s 𝑛 𝑖 = (11××10 6 )3 carriers/𝜇m < 1, so there are
3
really not that many free carriers in intrinsic silicon.
From Figure 2 we can see that 𝑛 𝑖 changes greatly as a function

of temperature, but the understanding “why” is not easy to get
from “doubling every 11 degrees”. To understand the temperature
behavior of diodes, we must understand Eq (1).
So where does Eq (1) come from? I find it unsatisfying if I don’t

understand where things come from. I like to understand why
there is an exponential, or effective mass, or Planck’s constant. If
you’re like me, then read the next section. If you don’t care, and
just want to memorize the equations, or indeed the number of
intrinsic carrier concentration number at room temperature, then
skip the next section.
4.4 It’s all quantum 37
4.4 It’s all quantum
There are two components needed to determine how many elec-

trons are in the conduction band. The density of available states,
and the probability of an electron to be in that quantum state.
For the density of states we must turn to quantum mechanics. The

probability amplitude of a particle can be described as
𝜓 = 𝐴𝑒 𝑖(𝑘 r−𝜔𝑡)
where 𝑘 is the wave number, and 𝜔 is the angular frequency, and r

is a spatial vector.
In one dimension we could write 𝜓(𝑥, 𝑡) = 𝐴𝑒 𝑖(𝑘𝑥−𝜔𝑡)
In classical physics we described the Energy of the system as
1 2
𝑝 +𝑉 = 𝐸
2𝑚
where 𝑝 = 𝑚𝑣 , 𝑚 is the mass, 𝑣 is the velocity and 𝑉 is the
potential.
In the quantum realm we must use the Schrodinger equation to

compute the time evolution of the Energy, in one space dimension
ℏ2 𝜕 2 𝜕
− 𝜓(𝑥, 𝑡) + 𝑉(𝑥)𝜓(𝑥, 𝑡) = 𝑖ℏ 𝜓(𝑥, 𝑡)
2𝑚 𝜕 𝑥
2 𝜕𝑡
where 𝑚 is the mass, 𝑉 is the potential, ℏ = ℎ/2𝜋.
We could rewrite the equation above as
𝜕
𝐻𝜓(𝑥,
b 𝑡) = 𝑖ℏ 𝜓(𝑥, 𝑡) = 𝐸𝜓(𝑥,
b 𝑡)
𝜕𝑡
where 𝐻b is sometimes called the Hamiltonian and is an operator, or

something that act on the wave-function. In Feynman’s Lectures
on Physics Feynman called the Hamiltonian the Energy Matrix of a
system. I like that better. The 𝐸
b is the energy operator, something
that operates on the wave-function to give the Energy.
We could re-arrange
[𝐻
b − 𝐸]𝜓(𝑟,
b 𝑡) = 0
This is an equation with at least 5 unknowns, the space vector in

three dimensions, time, and the energy matrix 𝐻b.
38 4 Diodes
The dimensions of the energy matrix depends on the system. The

energy matrix further up is for one free electron. For an atom, the
energy matrix will have more dimensions to describe the possible
quantum states.
I consider all energy matricies as infinite dimensions, but most

state transitions are so unlikely that they can be safely ignored.
I was watching Quantum computing in the 21st Century and David

Jamison mentioned that the largest system we could today compute
would be a system with about 30 electrons.
We know exactly how the equations of quantum mechanics appear

to be, and they’ve proven extremely successful, we must make
simplifications before we can predict how electrons behave in
complicated systems like the silicon lattice with approximately
0.7 trillion electrons per cube micro meter. You can check the
calculation
3
1 𝜇m

× 8 atoms per unit cell × 14 electrons per atom
0.543 nm
4.4.1 Density of states
To compute “how many Energy states are there per unit volume in
the conduction band”, or the “density of states”, we start with the
three dimensional Schrodinger equation for a free electron
ℏ2 2
− ∇ 𝜓 = 𝐸𝜓
2𝑚
I’m not going to repeat the computation here, but rather paraphrase
the steps. You can find the full derivation in Solid State Electronic
Devices.
The derivation starts by computing the density of states in the

k-space, or momentum space,
2
𝑁(𝑑𝑘) = 𝑑𝑘
(2𝜋)𝑝
Where 𝑝 is the number of dimensions (in our case 3).
The band structure 𝐸(𝑘) is used to convert to the density of states

to a function of energy 𝑁(𝐸). The simplest band structure, and an
approxmiation of the lowest conduction band is
4.4 It’s all quantum 39
ℏ2 𝑘 2
𝐸(𝑘) =
2𝑚 ∗
where 𝑚 ∗ is the effective mass of the particle. It is within this

effective mass that we “hide” the complexity of the actual three-
dimensional crystal structure of silicon.
The effective mass when we compute the density of states is
ℏ2
𝑚∗ =
𝑑2 𝐸
𝑑𝑘 2
as such, the effective mass depends on the localized band structure

of the silicon unit cell, and depends on direction of movement,
strain of the silicon lattice, and probably other things.
In 3D, once we use the above equations, one can compute that the
density of states per unit energy is
2 𝑚 ∗ 3/2 1/2
𝑁(𝐸)𝑑𝐸 = 𝐸 𝑑𝐸
𝜋2 ℏ2
In order to find the number of electrons, we need the probability

of an electron being in a quantum state, which is given by the
Fermi-Dirac distribution
1
𝑓 (𝐸) = (2)
𝑒 (𝐸−𝐸𝐹 )/𝑘𝑇 +1
where 𝐸 is the energy of the electron, 𝐸𝐹 is the Fermi level or checmi-

cal potential, 𝑘 is Boltzmann’s constant, and 𝑇 is the temperature
in Kelvin.
Fun fact, the Fermi level difference between two points is what you
measure with a voltmeter.
If the 𝐸 − 𝐸𝐹 > 𝑘𝑇 , then we can start to ignore the +1 and the

probability reduces to
1
𝑓 (𝐸) = = 𝑒 (𝐸𝐹 −𝐸)/𝑘𝑇
𝑒 (𝐸−𝐸𝐹 )/𝑘𝑇
A few observiation on the Fermi-Dirac distribution. If the Energy

of a state is at the Fermi level, then 𝑓 (𝐸) = 21 , or a 50 % probability
of being occupied.
In a metal, the Fermi level lies within a band, as the conduction

band and valence band overlap. As a result, there are a bunch of
free electrons that can move around. Metal does not have the same
type of covalent bonds as silicon, but electrons are shared between
40 4 Diodes
a large part of the metal structure. I would also assume that the
location of the Fermi level within the band structure explains the
difference in conductivity of metals, as it would determined how
many electrons are free to move.
In an insulator, the Fermi level lies in the bandgap between valence

band and conduction band, and usually, the bandgap is large, so
there is a low probability of finding electrons in the conduction
band.
In a semiconductor we also have a bandgap, but much lower energy

than an insulator. If we have thermal equilibrium, no external forces,
and we have an un-doped (intrinsic) silicon semiconductor, then
the fermi level 𝐸𝐹 lies half way between the conduction band edge
𝐸𝐶 and the valence band edge 𝐸𝑉 .
The bandgap is defined as the 𝐸𝐶 − 𝐸𝑉 = 𝐸 𝑔 , and we can use that

to get 𝐸𝐹 − 𝐸𝐶 = 𝐸𝐶 − 𝐸 𝑔 /2 − 𝐸𝐶 = −𝐸 𝑔 /2. This is why the bandgap
of silicon keeps showing up in our diode equations.
The number of electrons per delta energy will then be given by
𝑁𝑒 𝑑𝐸 = 𝑁(𝐸) 𝑓 (𝐸)𝑑𝐸
, which can be integrated to get
3/2
2𝜋𝑚 ∗ 𝑘𝑇

𝑛𝑒 = 2 𝑒 (𝐸𝐹 −𝐸𝐶 )/𝑘𝑇
ℎ2
For intrinsic silicon at thermal equlibrium, we could write
3/2
2𝜋𝑚 ∗ 𝑘𝑇

𝑛0 = 2 𝑒 −𝐸 𝑔 /(2 𝑘𝑇) (3)
ℎ2
As we can see, Equation (3) has the same coefficients and form as
the computation in Equation (1). The difference is that we also have
to account for holes. At thermal equilibrium and intrinsic silicon
𝑛 𝑖2 = 𝑛0 𝑝 0
4.4.2 How to think about electrons (and holes)
I’ve come to the realization that to imagine electrons as balls

moving around in the silicon crystal is a bad mental image.
For example, for a metal-oxide-semiconductor field effect transistor

(MOSFET) it is not the case that the electrons that form the inversion
layer under strong inversion come from somewhere else. They
are already at the silicon surface, but they are bound in covalent
4.5 Doping 41
bonds (there are literaly trillions of bound electrons in a typical

transistor).
What happens is that the applied voltage at the gate shifts the
energy bands close to the surface (or bends the bands in relation
to the Fermi level), and the density of carriers in the conduction
band in that location changes, according to the type of derivations
above.
Once the electrons are in the conduction band, then they follow the
same equations as diffusion of a gas, Fick’s law of diffusion. Any
charge density concentration difference will give rise to a diffusion
current given by
𝜕𝜌
𝐽diffusion = −𝑞𝐷𝑛 (4)
𝜕𝑥
where 𝐽 is the current density, 𝑞 is the charge, 𝜌 is the charge

density, and 𝐷 is a diffusion coefficient that through the Einstein
relation can be expressed as 𝐷 = 𝜇𝑘𝑇 , where mobility 𝜇 = 𝑣 𝑑 /𝐹 is
the ratio of drift velocity 𝑣 𝑑 to an applied force 𝐹 .
To make matters more complicated, an inversion layer of a MOSFET

is not in three dimensions, but rather a two dimensional electron
gas, as the density of states is confined close to the silicon surface.
As such, we should not expect the mobility of bulk silicon to be
the same as the mobility of a MOSFET transistor.
4.5 Doping
We can change the property of silicon by introducing other ele-

ments, something we’ve called doping. Phosphor has one more
electron than silicon, Boron has one less electron. Injecting these
elements into the silicon crystal lattice changes the number of free
electron/holes.
These days, we usually dope with ion implantation, while in

the olden days, most doping was done by diffusion. You’d paint
something containing Boron on the silicon, and then heat it in a
furnace to “diffuse” the Boron atoms into the silicon.
If we have an element with more electrons we call it a donor, and

the donor concentration 𝑁𝐷 .
The main effect of doping is that it changes the location of the

Fermi level at thermal equilibirum. For donors, the Fermi level will
shift closer to the conduction band, and increase the probabilty of
free electrons, as determined by Equation (2).
42 4 Diodes
Since the crystal now has an abundance of free electrons, which

have negative charge, we call it n-type.
If the element has less electrons we call it an acceptor, and the

acceptor concentration 𝑁𝐴 . Since the crystal now has an abundance
of free holes, we call it p-type.
The doped material does not have a net charge, however, as it’s the
same number of electrons and protons, so even though we dope
silicon, it does remain neutral.
The doping concentrations are larger than the intrinsic carrier

concentration, from maybe 1021 to 1027 carriers/m3 . To separate
between these concentrations we use 𝑝−, 𝑝, 𝑝+ or 𝑛−, 𝑛, 𝑛+.
The number of electrons and holes in a n-type material is
𝑛 𝑖2
𝑛 𝑛 = 𝑁𝐷 , 𝑝 𝑛 =
𝑁𝐷
and in a p-type material
𝑛 𝑖2
𝑝 𝑝 = 𝑁𝐴 , 𝑛 𝑝 =
𝑁𝐴
In a p-type crystal there is a majority of holes, and a minority of

electrons. Thus we name holes majority carriers, and electrons
minority carriers. For n-type it’s opposite.
4.6 PN junctions
Imagine an n-type material, and a p-type material, both are neutral

in charge, because they have the same number of electrons and
protons. Within both materials there are free electrons, and free
holes which move around constantly.
Now imagine we bring the two materials together, and we call

where they meet the junction. Some of the electrons in the n-type
will wander across the junction to the p-type material, and visa
versa. On the opposite side of the junction they might find an
opposite charge, and might get locked in place. They will become
stuck.
After a while, the diffusion of charges across the junction creates

a depletion region with immobile charges. Where as the two
materials used to be neutrally charged, there will now be a build
up of negative charge on the p-side, and positive charge on the
n-side.
4.6 PN junctions 43
4.6.1 Built-in voltage
The charge difference will create a field, and a built-in voltage will
develop across the depletion region.
The density of free electrons in the conduction band is
∫ ∞
𝑛= 𝑁(𝐸) 𝑓 (𝐸)𝑑𝐸
𝐸𝐶
, where 𝑁(𝐸) is the density of states, and 𝑓 (𝐸) is a probability of a

electron being in that state (Equation (2)).
We could write the density of electrons on the n-side as
∫ ∞
𝐸𝐹𝑛 /𝑘𝑇
𝑛𝑛 = 𝑒 𝑁𝑛 (𝐸)𝑒 −𝐸/𝑘𝑇 𝑑𝐸
𝐸𝐶
since the Fermi level is independent of the energy state of the

electrons (I think).
The density of electrons on the p-side could be written as
∫ ∞
𝐸𝐹𝑝 /𝑘𝑇
𝑛𝑝 = 𝑒 𝑁𝑝 (𝐸)𝑒 −𝐸/𝑘𝑇 𝑑𝐸
𝐸𝐶
If we assume that the density of states, 𝑁𝑛 (𝐸) and 𝑁𝑝 (𝐸) are the
same, and the temperature is the same, then
𝑛𝑛 𝑒 𝐸𝐹𝑛 /𝑘𝑇
= 𝐸 /𝑘𝑇 = 𝑒 (𝐸𝐹𝑛 −𝐸𝐹𝑝 )/𝑘𝑇
𝑛𝑝 𝑒 𝐹𝑝
The difference in Fermi levels is the built-in voltage multiplied by

the unit charge.
𝐸𝐹𝑛 − 𝐸𝐹𝑝 = 𝑞Φ
and by substituting for the minority carrier concentration on the

p-side we get
𝑁𝐴 𝑁𝐷
= 𝑒 𝑞Φ0 /𝑘𝑇
𝑛𝑖2
or rearranged to
!
𝑘𝑇 𝑁𝐴 𝑁𝐷
Φ0 = 𝑙𝑛
𝑞 𝑛 𝑖2
44 4 Diodes
4.6.2 Current
The derivation of current is a bit involved, but let’s try.
The hole concentration on the p-side and n-side could be written

as
𝑝𝑝
= 𝑒 −𝑞Φ0 /𝑘𝑇
𝑝𝑛
The negative sign is because the built in voltage is positive on the

n-type side
Asssume that −𝑥 𝑝 0 is the start of the junction on the p-side, and

𝑥 𝑛 0 is the start of the junction on the n-side.
Assume that we lift the p-side by a voltage 𝑞𝑉
Then the hole concentration would change to
𝑝(−𝑥 𝑝 0 )
= 𝑒 𝑞(𝑉−Φ0 )/𝑘𝑇
𝑝(𝑥 𝑛 0 )
while on the n-side the hole concentration would be
𝑝(𝑥 𝑛 0 )
= 𝑒 𝑞𝑉/𝑘𝑇
𝑝𝑛
So the excess hole concentration on the n-side due to an increase

of 𝑉 would be

Δ𝑝 𝑛 = 𝑝(𝑥 𝑛 0 ) − 𝑝 𝑛 = 𝑝 𝑛 𝑒 𝑞𝑉/𝑘𝑇 − 1
The diffusion current density, given by Equation (4) states
𝜕𝜌
𝐽(𝑥 𝑛 ) = −𝑞𝐷𝑝
𝜕𝑥
Thus we need to know the charge density as a function of 𝑥 . I’m

not sure why, but apparently it’s
𝜕𝜌(𝑥 𝑛 ) = Δ𝑝 𝑛 𝑒 −𝑥 𝑛 /𝐿𝑝
where 𝐿 𝑝 is a diffusion length. I think the equation above, the

exponential decay as a function of length, is related to the probabilty
of electron/hole recombination, and how the rate of recombination
must be related to the exceess hole concentration, as such related
to Exponential decay.
4.6 PN junctions 45
Anyhow, we can now compute the current density, and need only
compute it for 𝑥 𝑛 = 0, so you can show it’s
𝐷𝑝
𝐽(0) = 𝑞 𝑝 𝑛 𝑒 𝑞𝑉/𝑘𝑇 − 1
𝐿𝑝
which start’s to look like the normal diode equation. The 𝑝 𝑛 is the
minority concentration of holes on the n-side, which we’ve before
𝑛 𝑖2
estimated as 𝑝 𝑛 = 𝑁𝐷
We’ve only computed for holes, but there will be electron transport
from the p-side to the n-side also.
We also need to multiply by the area of the diode to get current

from current density. The full equation thus becomes
1 𝐷𝑛 1 𝐷𝑝 𝑞𝑉/𝑘𝑇

𝐼= 𝑞𝐴𝑛 𝑖2 𝑒

+ −1
𝑁𝐴 𝐿 𝑛 𝑁𝐷 𝐿 𝑝
where 𝐴 is the area of the diode, 𝐷𝑛 ,𝐷𝑝 is the diffusion coefficient

of electrons and holes and 𝐿𝑛 ,𝐿 𝑝 is the diffusion length of electrons
and holes.
Which we usually write as
𝑉𝐷
𝐼𝐷 = 𝐼𝑆 (𝑒 𝑉𝑇 − 1), where 𝑉𝑇 = 𝑘𝑇/𝑞
4.6.3 Forward voltage temperature dependence
We can rearrange 𝐼𝐷 equation to get
𝐼𝐷

𝑉𝐷 = 𝑉𝑇 ln
𝐼𝑆
and at first glance, it appears like 𝑉𝐷 has a positive temperature

coefficient. That is, however, wrong.
First rewrite
𝑉𝐷 = 𝑉𝑇 ln 𝐼𝐷 − 𝑉𝑇 ln 𝐼𝑆
𝐷𝑛 𝐷𝑝

ln 𝐼𝑆 = 2 ln 𝑛 𝑖 + ln 𝐴𝑞 +
𝐿 𝑛 𝑁𝐴 𝐿 𝑝 𝑁𝐷
46 4 Diodes
Assume that diffusion coefficient ‡ , and diffusion lengths are

independent of temperature.
That leaves 𝑛 𝑖 that varies with temperature.
p −𝐸 𝑔
𝑛𝑖 = 𝐵 𝑐 𝐵𝑣 𝑇 3/2 𝑒 2𝑘𝑇
where
3/2
2𝜋𝑘𝑚 𝑝∗
3/2
2𝜋𝑘𝑚𝑛∗

𝐵𝑐 = 2 𝐵𝑣 = 2
ℎ2 ℎ2
p 𝑉𝐺
2 ln 𝑛 𝑖 = 2 ln 𝐵 𝑐 𝐵𝑣 + 3 ln 𝑇 −
𝑉𝑇
with 𝑉𝐺 = 𝐸𝐺 /𝑞 and inserting back into equation for 𝑉𝐷
𝑘𝑇
𝑉𝐷 = (ℓ − 3 ln 𝑇) + 𝑉𝐺
𝑞
Where ℓ is temperature independent, and given by
𝐷𝑛 𝐷𝑝
p
ℓ = ln 𝐼𝐷 − ln 𝐴𝑞 + − 2 ln 𝐵 𝑐 𝐵𝑣
From equations above we can see that at 0 K, we expect the diode

voltage to be equal to the bandgap of silicon. Diodes don’t work at
0 K though.
Although it’s not trivial to see that the diode voltage has a negative
temperature coefficient, if you do compute it as in vd.py, then
you’ll see it decreases.
The slope of the diode voltage can be seen to depend on the area,
the current, doping, diffusion constant, diffusion length and the
effective masses.
Figure 3 shows the 𝑉𝐷 and the deviation of 𝑉𝐷 from a straight line.

The non-linear component of 𝑉𝐷 is only a few mV. If we could
combine 𝑉𝐷 with a voltage that increased with temperature, then
we could get a stable voltage across temperature to within a few
mV.
‡ From the Einstein relation 𝐷 = 𝜇𝑘𝑇 it does appear that the diffusion coefficient
increases with temperature, however, the mobility decreases with temperature.
I’m unsure of whether the mobility decreases with the same rate though.
4.6 PN junctions 47
0.95
Diode voltage [V]
0.90
0.85
25 0 25 50 75 100 125
Non-linear component (mV)
2
25 0 25 50 75 100 125
Temperature [C]
Figure 3: Diode forward voltage as a function of temperature
4.6.4 Current proportional to temperature
Assume we have a circuit like Figure 4.
Here we have two diodes, biased at different current densities. The

voltage on the left diode 𝑉𝐷 1 is equal to the sum of the voltage on
the right diode 𝑉𝐷 2 and voltage across the resistor 𝑅 1 . The current
in the two diodes are the same due to the current mirror. A such,
we have that
𝑞𝑉𝐷 1 𝑞𝑉𝐷 2
𝐼𝑆 𝑒 𝑘𝑇 = 𝑁 𝐼𝑆 𝑒 𝑘𝑇
Taking logarithm of both sides, and rearranging, we see that
𝑘𝑇
𝑉𝐷 1 − 𝑉𝐷 2 = ln 𝑁
𝑞
Or that the difference between two diode voltages biased at different

current densities is proportional to absolute temperature.
In the circuit above, this Δ𝑉𝐷 is across the resistor 𝑅 1 , as such,

the 𝐼𝐷 = Δ𝑉𝐷 /𝑅 1 . We have a current that is proportional to
temperature.
If we copied the current, and sent it into a series combination of a

resistor 𝑅 2 and a diode, we could scale the 𝑅 2 value to give us the
48 4 Diodes
exactly right slope to compensate for the negative slope of the 𝑉𝐷

voltage.
The voltage across the resistor and diode would be constant over
temperature, with the small exception of the non-linear component
of 𝑉𝐷 .
TN
Figure 4: Circuit to generate a current proportional to kT
4.7 Equations aren’t real
Nature does not care about equations. It just is.
We know, at the fundamental level, nature appears to obey the

mathematics on quantum mechanics, however, due to the com-
plexity of nature, it’s not possible today (which is not the same as
impossible), to compute exactly how the current in a diode works.
We can get close, by measuring a diode we know well, and hope
that the next time we make the same diode, the behavior will be
the same.
As such, I want to warn you about the “lies” or “simplifications”

we tell you. Take the diode equation above, some parts, like the
intrinsic carrier concentration 𝑛 𝑖 has roots directly from quantum
4.7 Equations aren’t real 49
mechanics, with few simplifications, which means it’s likely solid

truth, at least for a single unit cell.
But there is no reason nature should make all unit cells the same,
and infact, we know they are not the same, we put in dopants. As
we scale down to a few nano-meter transistors the simplification
that “all unit cells of silicon are the same, and extend to infinity” is
no longer true, and must be taken into account in how we describe
reality.
Other parts, like the exact value of the bandgap 𝐸 𝑔 , the diffusion
constant 𝐷𝑝 or diffusion length 𝐿 𝑝 are macroscopic phenomena,
we can’t expect them to be 100 % true. The values would be based
on measurement, but not always exact, and maybe, if you rotate
your diode 90 degrees on the integrated circuit, the values could
be different.
You should realize that the consequence of our imperfection is that

the equations in electronics should always be taken with a grain of
salt.
Nature does not care about your equations. Nature will easily have
the superposition of trillions of electrons, and they don’t have to
agree with your equations.
But most of the time, the behavior is similar.
References
[1] T. C. Carusone, D. Johns, and K. Martin, Analog integrated
circuit design. Wiley, 2011 [Online]. Available: https://book
s.google.no/books?id=1OIJZzLvVhcC
[2] Berkeley, “Berkeley short-channel IGFET model.” [Online].
Available: http://bsim.berkeley.edu/models/bsim4/
MOSFETs 5
5.0.1 Metal Oxide Semicon-
I’m stunned if you’ve never heared the word “transistor”. I think ductor . . . . . . . . . . 51
most people have heard the word. What I find funny is that almost 5.0.2 Field Effect . . . . . . . 53
nobody understand in full detail how transistors work. 5.1 Analog transistors in
the books . . . . . . . . 58
5.2 Transistors in weak
Through my 30 year venture into the world of electronics I’ve inversion . . . . . . . . 61
met “analog designers”, or people that should understand exactly 5.3 The Field Effect . . . . 64
how transistors work. I used to hire analog designers, and I’ve 5.4 Transistors in strong
interviewed hundred plus “analog designers” in my 8 years as inversion . . . . . . . . 66
manager and I’ve met hundreds of students of analog design. I 5.5 How should I size my
would go as far as to say none of them know everything about transistor? . . . . . . . 67
transistors, including myself.
Most of the people I’ve met have a good brain, so that is not the
reason they don’t understand. Transistors are incredibly compli-
cated! I say this, because if at some point in this document, you
don’t understand, then don’t worry, you are not alone.
In this document I’m focusing on Metal Oxide Semiconductor Field

Effect Transistors (MOSFETs), and ignore all other transistors.
5.0.1 Metal Oxide Semiconductor
The first part of the MOSFET name illustrates the 3 dimensional

composition of the transistor. Take a semiconductor (Silicon), grow
some oxide (Silicon Oxide, SiO2), and place a metal, or conductive,
gate on top of the oxide. With those three components we can build
our transistor.
Something like the cartoon below where only the Metal (gate) of
the MOS name is shown.
The oxide and the silicon bulk is not visible, but you can imagine
them to be underneath the gate, with a thin oxide (a few nano
meters thick) and the silicon the transparent part of the picture.
The length (L), and width (W) of the MOS is annotated in blue.
52 5 MOSFETs
Figure 1: 3D crossection of a transistor
MOSFETs come in two main types. There is NMOS, and PMOS.

The symbols are as shown below. The NMOS is MN1 and PMOS is
MP1.
VD VS
MN1 MP1
VG VG
VS VD
Figure 2: Transistor symbols
The MOS part of the name can be seen in MN1, where 𝑉𝐺 is the gate
connected to a vertical line (metal), a space (oxide), and another
vertical line (the silicon substrate or silicon bulk).
On the sides of the gate we have two connections, a drain 𝑉𝐷 and

a source 𝑉𝑆 .
If we have a sufficient voltage between gate and source 𝑉𝐺𝑆 , then

the transistor will conduct from drain to source. If the voltage is
too low, then there will not be much current.
The “source” name is because that’s where the charge carrier

(electrons) come from, they come from the source, and flow towards
the drain. As you may remember, the “current”, as we’ve defined
it, flows opposite of the electron current, from drain to source.
The PMOS works in a similar manner, however, the PMOS is made

of a different type of silicon, where the dominant charge carrier
is holes in the valence band. As a result, the gate-source voltage
needs to be negative for the PMOS to conduct.
53
In a PMOS the holes come from the source, and flow to the drain.
Since holes are positive charge carriers, the current flows from
source to drain.
In most MOSFETs there is no physical difference between source

and drain. If you flip the transistor it would work almost exactly
the same.
5.0.2 Field Effect
Imagine that the bulk (the empty space underneath the gate), and
the source is connected to 0 V. Assume that the gate is 0 V.
In the source and drain parts of the transistor there is an abundance

of free electrons that can move around, exactly like in a metal
conductor, however, underneath the gate there are almost no free
electrons.
There are electrons underneath the gate though, trillions upon

trillions of electrons, but they are stuck in co-valent bonds between
the Silicon atoms, and around the nucleus of the Silicon atoms.
These electrons are what we call bound electrons, they cannot
move, or more precisely, they cannot contribute to current (because
they do move, all the time, but mostly around the atoms).
Imagine that your eyes could see the free electrons as a blue
fluorescent color. What you would see is a bright blue drain, and
bright blue source, but no color underneath the gate.
Figure 3: MOSFET in “off” state
As you increase the gate voltage, the color underneath the gate
would change. First, you would think there might be some blue
color, but it would be barely noticeable.
54 5 MOSFETs
Figure 4: MOSFET in subthreshold
At a certain voltage, suddenly, there would be a thin blue sheet

underneath the gate. You’d have to zoom in to see it, in reality it’s
a ultra thin, 2 dimensional electron sheet.
As you continue to increase the gate voltage the blue color would
become a little brighter, but not much.
Figure 5: MOSFET in strong inversion
This thin blue sheet extend from source to drain, and create a
conductive channel where the electrons can move from source to
drain (or drain to source), exactly like a resistor. The conductance of
the sheet is the same as the brightness, higher gate source voltage,
more bright blue, higher conductance, less resistance.
Assume you raise the drain voltage. The electrons would move from
source to drain proportional to the voltage. How many electrons
could move would depend on the gate voltage.
If the gate voltage was low, then there is low density of electrons
in the sheet, and low current.
55
If the gate voltage is high, then the electron density in the sheet
is high, and there can be a high current, although, the electrons
do have a maximum speed, so at some point the current does not
change as fast with the gate voltage.
At a certain drain voltage you would see the blue color disappear
close to the drain and there would be a gap in the sheet.
Figure 6: MOSFET in strong inversion and saturation
That could make you think the current would stop, but it turns out,
that the electrons close to drain get swept across the gap because
the electric field is so high from the edge of the sheet to the drain.
As you continue to increase the drain voltage, the gap increases,

but the current does not really increase that much. It’s this exact
feature that make transistor so attractive in analog circuits. I can
create a current from drain to source that does not depend much
on the drain to source voltage! That’s why we sometimes imagine
transistors as a “trans-conductance”. The conductance between
drain and source depends on the voltage somewhere else, the
gate-source voltage.
And now you may think you understand how the transistor works.
By changing the gate voltage, we can change the electron current
from source to drain. We can turn on, and off, currents, creating a
0 and 1 state.
For example, if I take a PMOS and connect the source to a high

voltage, the drain to an output, and an NMOS with the source to
ground and the drain to the output, and connect the gates together,
I would have the simplest logic gate, an inverter, as shown below.
If the input 𝑉𝑖𝑛 is a high voltage, then the output 𝑉𝑜𝑢𝑡 is a low
voltage, because the NMOS is on. If the input 𝑉𝑖𝑛 is a low voltage,
then the output 𝑉𝑜𝑢𝑡 is a high voltage, because the PMOS is on.
56 5 MOSFETs
MP1
Vin Vout
MN1
Figure 7: Inverter
I can now build more complex “logic gates”. The one below is a
Not-AND gate (NAND). If both inputs (A and B) are high, then
the output is low (both NMOS are on). Otherwise, the output is
high.
I find it amazing that all digital computers in existence can be

constructed from the NAND gate. In principle, it’s the only logic
gate you need. If you actually did construct computers from
NANDs only, they would be costly, and consume lots of power.
There are smarter ways to use the transistors.
57
Figure 8: NAND
You may be too young to have seen the Matrix, but now is the time
to decide between the red pill and the blue pill.
The red will start your journey to discover the reality behind the
transistor, the blue pill will return you to your normal life, and you
can continue to think that you now understand how transistors
work.
58 5 MOSFETs
Figure 9: The choice
Because:
▶ Why did the area underneath the gate turn blue?

▶ Why is it only a thin sheet that turns blue?
▶ Where did the electrons for the sheet come from?
▶ Why did the blue color change suddenly?
▶ How does the brightness of the blue change with gate-source
voltage?
▶ How can the electrons stay in that sheet when we connect
the bulk to 0 V?
▶ Why is there not a current from the bulk (0 V) to drain?
▶ Why does not the electrons jump from source to drain? It’s a
gap, the same as from the sheet to drain?
And did you realize I never in this chapter explained how the field
effect worked?
Someday, I may write all the details, if I ever understand it all. For
now, I hope that the sections below will help you a bit.
5.1 Analog transistors in the books
In the books we learn the equations for weak inversion
𝐼𝐷 ∝ (𝑒 (𝑉𝑔𝑠 −𝑉𝑡 ℎ )/𝑈𝑇 − 1)
, where 𝐼𝐷 is the drain current, 𝑉𝑔𝑠 is the gate source voltage, 𝑉𝑡 ℎ

is the threshold voltage and 𝑈𝑇 = 𝑘𝑇/𝑞 , where 𝑘 is Boltzmann’s
constant, 𝑇 is the temperature in Kelvin and 𝑞 is the unit charge
5.1 Analog transistors in the books 59
The equation is similar to bipolar and diode equations, because

the physics is the same.
The drain current in weak inversion is mostly a diffusion current

and relates to the density of electrons in the conduction band (for
an NMOS), which can be computed from the density of available
energy states, and the Fermi-Dirac distribution.
∫ ∞
1
𝑛= 𝑁(𝐸) 𝑑𝐸
𝐸𝐶 𝑒 (𝐸−𝐸𝐹 )/𝑘𝑇 +1
, where 𝑛 is the density of electrons in the conduction band, 𝑁(𝐸) is

the density of available energy states, 𝐸 is the integration variable
(and the energy) and 𝐸𝐹 is the Fermi-level.
Maybe the equation looks complicated, but it’s really “Multiply

the available energy state with the probability of being in that state,
and sum for all available energy states”.
Changing the voltage changes the number of free electrons, simply

because we bring the conduction band closer to the Fermi level.
The Fermi level is just something we invented, and just means

“If there was an quantum state at the Fermi level Energy, then it
would have a 50 % probability of being occupied by a electron”.
In the equation above, moving the conduction band edge is equiva-

lent to reducing the 𝐸𝐶 . As such, more of the Fermi-Dirac distribu-
tion has available energy states 𝑁(𝐸), and the density of electrons
𝑛 in conduction band becomes higher.
In strong inversion, the MOSFET is more like a voltage controlled

resistor with a conductance that is proportional to gate-source
voltage.
The density of electrons increases because we bend the conduction

band beyond the Fermi level, as a result, most of the available
energy states in the conduction band are filled by electrons.
Electrons are only free to move, however, close to the surface of

the silicon, as far away from the surface, we don’t feel the effects
of the gate-source voltage, and the conduction band stays at the
same energy. As a result, electrons form a 2 dimensional electron
gas close to the silicon surface. What we call an inversion layer.
Once we have that electron gas, or inversion layer, we have a

connection between the drain and source n-type regions, and the
current can be estimated by a drift current. Parts of the diffusion
current will still be there, but much smaller magnitude than the
drift current, so we drop the diffusion current, and get
60 5 MOSFETs
1 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶 𝑜𝑥 (𝑉𝑔𝑠 − 𝑉𝑡 ℎ )2
2 𝐿
The equations in the books are good to give a physical understand-

ing of what happens. Although, we tend to forget that everybody
forgets.
We teach quantum physics one year, and how to compute the

density of states 𝑁(𝐸) from Schrodinger, the wave-function and
Fermi-Dirac distribution.
Next year we talk about semiconductors, crystal lattice, band

structure (density of states as a function of space), energy diagrams
(band structure is complex, so we just use the lowest conduction
band and highest valence band), doping to shift the Fermi level,
and how we can create PN-junctions, bipolars and MOSFETS.
The year after we teach the current equations for MOSFETs, and
the books don’t have the link back to solid-state physics, after all,
we already told the students that, they should remember!
I think, quite often, we just end up with confused students. And

I don’t think it’s necessary to end up with confused students.
Maybe sometimes we end up with confused students because the
Professors can’t necessarily remember where the equations come
from either, nor how electrons and holes really behave.
It’s not necessary for an analog design student to remember how

to compute the density of available energy states from Schrodinger
and the wave function. If we wanted to use the relativistc version
of Schrodinger (which includes magnetic fields, and if you did not
know, magnetic fields is just a relativistic effect of the electric field)
and the wave function to compute how an Silicon atom actually
behaves, I don’t think we can. As far as I’ve been able to figure out,
it’s not possible to have a closed form solution (symbolic), nor is
it possible with supercomputers to do a numeric time-evolution
of the states in a single Silicon atom with all the inter-particle
interactions, space, momentum, spins, electric fields and magnetic
fields.
But we can make sure we connect the links from Schrodinger to the
MOSFET equations, the short version of that was above, but the
following sections tries to explain with words how the transistor
actually works.
I’m not going to give all the equations and all the maths. For that,
there are excelent books and resources. I would recommend Mark
Lundstrom for the best in detail description of MOSFETs.
5.2 Transistors in weak inversion 61
5.2 Transistors in weak inversion
Consider the cartoon below which shows the hole concentration

in the valence band, and electron concentration in the conduction
band versus the x direction of the transistor.
For the moment we’ll ignore the field effect of the gate, and how
that modulates the hole concentration underneath the gate.
If you’re familiar with bipolars, then you may think I’ve drawn the
wrong transistor, because you see an NPN bipolar transistor. The
picture is correct, however, this is how a normal MOSFET looks.
It’s actually also a NPN bipolar transistor, but we don’t usually use
that part (you’ll see more when we get to ESD)
In the source we’ve doped with donors, and have an abundance of

free electrons. Underneath the gate, or the bulk, we have doped
with acceptors, and have an abundance of holes.
Source Gate Drain
n p n
Source Gate
Figure 10: Charge carrier density in a MOSFET
Drain
Let’s consider electron current for now, and only look at the
In
conduction band.
An electron in the source would see a energy barrier of 𝜙 𝐵 , and most

electrons would be turned around at the barrier. Some, however,
do have the energy to traverse the barrier and flow through the
bulk. Not all of them would reach the bulk, due to recombination,
n p and all electronsn injected into
but let’s assume the bulk is short,
the bulk show up at the drain.
e e
At the drain side they would fall down the potential barrier to the
drain. The same process would happen in reverse, from drain to
source.
Source Gate Drain

62 5 MOSFETs n p n
Source Gate Drain
In n
n p
e e
Figure 11: MOSFET subthreshold , 𝑉𝐷𝑆 = 0
Source Gate Drain

There would also be hole currents flowing between source/bulk/drain
Mma
and visa versa
Assume source and drain are at the same potential, then the sum
n n
of all currents (1,2,3,4) for both electrons and holes in Figure
p
11
must equal zero.
e e
Assume that we increase the drain voltage, as shown in Figure 12.
Increasing the drain voltage is the same as reducing the conduction
band in the drain.
Since there now is a higher barrier from drain to bulk, it’s now
much less probable that electrons are injected from drain to bulk.
Now the sum of all currents would not equal zero, as the 1 and 3
currents are larger than 2 and 4.
As such, there would be a net flow of electron current from source

to drain.
e e
5.2 Transistors in weak inversion 63
Source Gate Drain
n
Mma p n
e e
Figure 12: MOSFET subthreshold, 𝑉𝑆 = 0 V , 𝑉𝐷 > 0 V
Notice that if we increase the drain voltage further, then the electron
injection from drain to bulk would quickly approach zero.
At that point, even though we increase the drain voltage further,

the current does not really change. As the current is only now
given by the barrier height at the source.
The barrier height at the source is the built in voltage of the

junction, and as we’ve seen before, that voltage depends on doping
concentration. If we increase the hole concentration in bulk, then we
increase the barrier height, and it’s less probable that the electrons
have enough energy to be injected from source to bulk.
If we only need to consider the electrons and holes at source for the
subthreshold current (assuming the drain voltage is high enough),
then we should expect the equation look very similar to a diode,
and indeed it does.
The drain current, which is mostly a diffusion current, is given

by
𝑊 𝑞(𝑉𝐺𝑆 −𝑉𝑇𝐻 )/𝑛 𝑘𝑇

𝐼𝐷 = 𝐼𝐷 0 𝑒
𝐿
where
𝑛 = (𝐶 𝑜𝑥 + 𝐶 𝑗 0 )/𝐶 𝑜𝑥
2
𝑘𝑇

𝐼𝐷 0 = (𝑛 − 1)𝜇𝑛 𝐶 𝑜𝑥
𝑞
64 5 MOSFETs
This is not exactly the same as the diode equation, but we can see
that it looks similar. Most of the quantum mechanics is baked into
the 𝑉𝑇𝐻
The transconductance ( 𝑑𝐼𝐷 /𝑑𝑉𝐺𝑆 ) in weak inversion is then
𝐼𝐷
𝑔𝑚 =
𝑛𝑉𝑇
A big difference from the diode equation is the fact that the gate-
source voltage seems to determine the current, and not the voltage
across the pn junction.
5.3 The Field Effect
Consider the band diagram in Figure 13, in the figure we’re looking
at a cross section of the transistor. From left we’re in the gate, then
we have the oxide, and then the bulk of the transistor.
We don’t see the drain and source, as the source would be towards
Gate
you, and the drain would be into the picture.
Source Drain
The cartoon is not a real transistor. I don’t think there is necessarily
a combination of semiconductor and metal where we end up with
the same Fermi level (𝐸𝐹 ) without some bending of the conduction
band and valence band, but for illustration, let’s assume that’s the
case.
We can see the Fermi level in the semiconductor is shifted towards

the valence band, and thus we have a P-type semiconductor.
ab
n
The gate is metallic, so it does not have a bandgap, and we assume
that the Fermi level is at the conduction band edge.
Gate Eide Bulk

EC
Figure 13: Band diagram of a fictive MOSFET.

É
5.3 The Field Effect 65
Assume we increase the gate-source voltage. In a band diagram

that corresponds to shifting the energy down.
Gate Eide Bulk

Ec
at É
Figure 14: Band diagram with gate-source voltage applied
Moving the gate down has the effect of bending the bands in the
semiconductor. We’ll lose some voltage across the oxide, but not
necessarily that much.
The bending of the valence band will decrease the hole concen-
tration close to the silicon surface, and the semiconductor will be
depleted of mobile charge carriers.
The valence band bending will also reduce the barrier height in
Figure 12, which increases the number of carriers that can be
injected at source/bulk interface, so the subthreshold current will
start to increase.
At some point, the band bending of the conduction band will

become so large that the electron concentration underneath the
gate will increase signficantly. The gate-source voltage where the
electron concentration equals the bulk hole concentration far away
from the silicon surface is called the “threshold voltage”.
As you continue to increase the gate-source voltage there is a limit

to how much the electron concentration increases. When the band
bending of the conduction band passes the Fermi level, then over
50 percent of the available states in the conduction band are filled
with electrons.
66 5 MOSFETs
Gate Eide Bulk

Ec
qV IF
I
Figure 13: Band diagram with high gate-source voltage applied
5.4 Transistors in strong inversion
The conditions to be in strong inversion is that the gate/source

voltage is above some magic values (threshold voltage), and then
some.
The quantum state of the electron is fully determined by it’s spin,

momentum and position in space. How those parameters evolve
with time is determined by the Schrodinger equation. In the general
form
𝑑
𝑖ℏ Ψ(𝑟, 𝑡) = 𝐻Ψ(𝑟,
b 𝑡)
𝑑𝑡
The Hamiltonian (𝐻 ) is an “energy matrix” operator and may

contain terms both for the momentum and Columb force (electric
field) experienced by the system.
But what does the Schrodinger equation tell us? Well, the equation
above does not tell me much, it can’t be “solved”, or rather, it does
not have a single solution. It’s more a framework for how the wave
function, and the Hamiltonian, describes the quantum states of
a system, and the probability ampltiudes of transition between
states.
5.5 How should I size my transistor? 67
The Schrodinger equation describes the time evolution of the

bound electrons shared between the Silicon atoms, and the fact
that applying a electric field to silicon can free co-valent bonds.
As the gate-source voltage increases the wave function that fits in

the Schrodinger equation predicts that the free electrons will form
a 2d sheet underneath the gate. The thickness of the sheet is only a
few nano meters.
In Figure 2 in Carrier transport near the Si/SiO2 interface of a

MOSFET you can see how the free electron density is located
underneath the gate.
I would really recommend that you have a look at Mark Lund-

strom’s lecture series on Essentials of MOSFETs. It’s the most
complete description of electrons in MOSFET’s I’ve seen
5.5 How should I size my transistor?
The method that makes most sense to me, is to use the inversion-
coefficient method, described in Nanoscale MOSFET Modeling:
Part 1 and Nanoscale MOSFET Modeling: Part 2.
The inversion coefficient tells us how strongly inverted the MOSFET

channel (inversion layer) is. A number below 0.1 is weak inversion,
between 0.1 and 10 is moderate inversion. A number above 10 is
strong inversion.
There are also some blog posts worth looking at Inversion Coeffi-
cient Based Circuit Design and My Circuit Design Methodology.
I should caveat my proposal for method. For the past 7 years I’ve
not had the luxury to do full time, hardcore, analog design. As my
career progressed, most of my time is now spent telling others what
I think is a good idea to do, and not doing hardcore analog design
myself. I think, however, I have a pretty decent understanding of
analog circuits, and how to design them, so I think I’m correct in
the proposal. If I were to start hardcore analog design now, I would
go all in on inversion-coefficient based transistor size selection.
SPICE 6
6.1 SPICE . . . . . . . . . . 69
6.1 SPICE
6.2 Simulation Program
with Integrated Circuit
Emphasis . . . . . . . . 69
6.2 Simulation Program with Integrated Circuit 6.2.1 Today . . . . . . . . . . 69
Emphasis 6.2.2 But . . . . . . . . . . . . 70
6.2.3 Sources . . . . . . . . . 71
6.2.4 Passives . . . . . . . . . 72
To manufacture an integrated circuit we have to be able to predict 6.2.5 Transistor Models . . . 72
how it’s going to work. The only way to predict is to rely on our 6.2.6 Transistors . . . . . . . 73
knowledge of physics, and build models of the real world in our 6.2.7 Foundries . . . . . . . . 74
computers. 6.3 Find right transistor
sizes . . . . . . . . . . . 74
One simulation strategy for a model of the real world, which 6.3.1 Use unit size transistors
absolutely every single integrated circuit in the world has used to for analog design . . . 75
come into existence, is SPICE. 6.3.2 What about gm/Id ? . 76
6.3.3 Characterize the transis-
Published in 1973 by Nagel and Pederson tors . . . . . . . . . . . . 76
6.4 More information . . . 76
SPICE (Simulation Program with Integrated Circuit Emphasis) 6.5 Analog Design . . . . . 76
6.6 Demo . . . . . . . . . . 77
6.2.1 Today
There are multiple SPICE programs that has been written, but
they all work in a similar fashion. There are expensive ones, closed
source, and open source.
70 6 SPICE
Some are better at dealing with complex circuits, some are faster,
and some are more accurate. If you don’t have money, then start
with ngspice.
Commercial Cadence Spectre Siemens Eldo Synopsys HSPICE
Free Aimspice Analog Devices LTspice
Open Source ngspice
6.2.2 But
All SPICE simulators understand the same language (yes, even

spectre can speak SPICE). We write our testbenches in a text file,
and give it to the SPICE program. That’s the same for all programs.
Some may have built fancy GUI’s to hide the fact that we’re really
writing text files, but text files is what is under the hood.
Pretty much the same usage model as 48 years ago
<spice program> testbench.cir
for example
ngspice testbench.cir
Or in the most expensive analog tool (Cadence Spectre)
spectre input.scs +escchars +log ../psf/spectre.out

-format psfxl -raw ../psf +aps +lqtimeout 900 -maxw 5 -maxn 5 -
/tmp/wulff/virtuoso/TB_SUN_BIAS_GF130N/TB_SUN_BIAS/maestro/result
+logstatus
The expensive tools have built graphical user interface around the
SPICE simulator to make it easier to run multiple scenarios.
Corner Typical Fast Slow All

Mosfet Mtt Mff Mss Mff,Mfs,Msf,Mss
Resistor Rt Rl Rh Rl,Rh
Capacitors Ct Cl Ch Cl,Ch
Diode Dt Df Ds Df,Ds
Bipolar Bt Bf Bs Bf,Bs
Temperature Tt Th,Tl Th,Tl Th,Tl
Voltage Vt Vh,Vl Vh,Vl Vh,Vl
6.2 Simulation Program with Integrated Circuit Emphasis 71
I’m a fan of launching multiple simulations from the command

line. I don’t like GUI’s. As such, I wrote cicsim, and that’s what I
use in the video and demo.
6.2.3 Sources
The SPICE language is a set of conventions for how to write the

text files. In general, it’s one line, one command (although, lines
can be continued with a +).
I’m not going to go through an extensive tutorial in this document,

and there are dialects with different SPICE programs. You’ll find
more info at ngspice
6.2.3.1 Independent current sources
Infinite output impedance, changing voltage does not change

current
I<name> <from> <to> dc <number> ac <number>
I1 0 VDN dc In
I2 VDP 0 dc Ip
72 6 SPICE
6.2.3.2 Independent voltage source
Zero output impedance, changing current does not change volt-

age
V<name> <+> <-> dc <number> ac <number>
V2 VSS 0 dc 0
V1 VDD 0 dc 1.5
6.2.4 Passives
Resistors
R<name> <node 1> <node 2> <value>
R1 N1 N2 10k
R2 N2 N3 1Meg
R3 N3 N4 1G
R4 N4 N5 1T
Capacitors
C<name> <node 1> <node 2> <value>
C1 N1 N2 1a
C2 N1 N2 1f
C4 N1 N2 1p
C3 N1 N2 1n
C5 N1 N2 1u
6.2.5 Transistor Models
Needs a model file the transistor model
BSIM (Berkeley Short-channel IGFET Model) http://bsim.berkele

y.edu/models/bsim4/
Drain
Gate M1
Source
284 parameters in BSIM 4.5
6.2 Simulation Program with Integrated Circuit Emphasis 73
.MODEL N1 NMOS LEVEL=14 VERSION=4.5.0 BINUNIT=1 PARAMCHK=1 MOBMOD=0

CAPMOD=2 IGCMOD=1 IGBMOD=1 GEOMOD=1 DIOMOD=1 RDSMOD=0 RBODYMOD=0 RGATEMOD=3
PERMOD=1 ACNQSMOD=0 TRNQSMOD=0 TEMPMOD=0 TNOM=27 TOXE=1.8E-009
TOXP=10E-010 TOXM=1.8E-009 DTOX=8E-10 EPSROX=3.9 WINT=5E-009 LINT=1E-009
LL=0 WL=0 LLN=1 WLN=1 LW=0 WW=0 LWN=1 WWN=1 LWL=0 WWL=0 XPART=0
TOXREF=1.4E-009 SAREF=5E-6 SBREF=5E-6 WLOD=2E-6 KU0=-4E-6 KVSAT=0.2
KVTH0=-2E-8 TKU0=0.0 LLODKU0=1.1 WLODKU0=1.1 LLODVTH=1.0 WLODVTH=1.0
LKU0=1E-6 WKU0=1E-6 PKU0=0.0 LKVTH0=1.1E-6 WKVTH0=1.1E-6 PKVTH0=0.0
STK2=0.0 LODK2=1.0 STETA0=0.0 LODETA0=1.0 LAMBDA=4E-10 VSAT=1.1E 005
VTL=2.0E5 XN=6.0 LC=5E-9 RNOIA=0.577 RNOIB=0.37
LINTNOI=1E-009 WPEMOD=0 WEB=0.0 WEC=0.0 KVTH0WE=1.0 K2WE=1.0 KU0WE=1.0
SCREF=5.0E-6 TVOFF=0.0 TVFBSDOFF=0.0 VTH0=0.25 K1=0.35 K2=0.05
K3=0 K3B=0 W0=2.5E-006 DVT0=1.8 DVT1=0.52 DVT2=-0.032 DVT0W=0 DVT1W=0
DVT2W=0 DSUB=2 MINV=0.05 VOFFL=0 DVTP0=1E-007 DVTP1=0.05 LPE0=5.75E-008
LPEB=2.3E-010 XJ=2E-008 NGATE=5E 020 NDEP=2.8E 018 NSD=1E 020 PHIN=0
CDSC=0.0002 CDSCB=0 CDSCD=0 CIT=0 VOFF=-0.15 NFACTOR=1.2 ETA0=0.05
ETAB=0 UC=-3E-011 VFB=-0.55 U0=0.032 UA=5.0E-011 UB=3.5E-018 A0=2
AGS=1E-020 A1=0 A2=1 B0=-1E-020 B1=0 KETA=0.04 DWG=0 DWB=0 PCLM=0.08
PDIBLC1=0.028 PDIBLC2=0.022 PDIBLCB=-0.005 DROUT=0.45 PVAG=1E-020
DELTA=0.01 PSCBE1=8.14E 008 PSCBE2=5E-008 RSH=0 RDSW=0 RSW=0 RDW=0
FPROUT=0.2 PDITS=0.2 PDITSD=0.23 PDITSL=2.3E 006 RSH=0 RDSW=50 RSW=150
RDW=150 RDSWMIN=0 RDWMIN=0 RSWMIN=0 PRWG=0 PRWB=6.8E-011 WR=1
ALPHA0=0.074 ALPHA1=0.005 BETA0=30 AGIDL=0.0002 BGIDL=2.1E 009 CGIDL=0.0002
EGIDL=0.8 AIGBACC=0.012 BIGBACC=0.0028 CIGBACC=0.002 NIGBACC=1
AIGBINV=0.014 BIGBINV=0.004 CIGBINV=0.004 EIGBINV=1.1 NIGBINV=3 AIGC=0.012
BIGC=0.0028 CIGC=0.002 AIGSD=0.012 BIGSD=0.0028 CIGSD=0.002 NIGC=1
POXEDGE=1 PIGCD=1 NTOX=1 VFBSDOFF=0.0 XRCRG1=12 XRCRG2=5 CGSO=6.238E-010
CGDO=6.238E-010 CGBO=2.56E-011 CGDL=2.495E-10 CGSL=2.495E-10
CKAPPAS=0.03 CKAPPAD=0.03 ACDE=1 MOIN=15 NOFF=0.9 VOFFCV=0.02 KT1=-0.37
KT1L=0.0 KT2=-0.042 UTE=-1.5 UA1=1E-009 UB1=-3.5E-019 UC1=0 PRT=0
AT=53000 FNOIMOD=1 TNOIMOD=0 JSS=0.0001 JSWS=1E-011 JSWGS=1E-010 NJS=1
IJTHSFWD=0.01 IJTHSREV=0.001 BVS=10 XJBVS=1 JSD=0.0001 JSWD=1E-011
JSWGD=1E-010 NJD=1 IJTHDFWD=0.01 IJTHDREV=0.001 BVD=10 XJBVD=1 PBS=1 CJS=0.0005
MJS=0.5 PBSWS=1 CJSWS=5E-010 MJSWS=0.33 PBSWGS=1 CJSWGS=3E-010 MJSWGS=0.33
PBD=1 CJD=0.0005 MJD=0.5 PBSWD=1 CJSWD=5E-010 MJSWD=0.33 PBSWGD=1
CJSWGD=5E-010MJSWGD=0.33 TPB=0.005 TCJ=0.001 TPBSW=0.005 TCJSW=0.001 TPBSWG=0.005
TCJSWG=0.001 XTIS=3 XTID=3 DMCG=0E-006 DMCI=0E-006 DMDG=0E-006 DMCGT=0E-007 DWJ=0.0E-008 XGW
XGL=0E-008 RSHG=0.4 GBMIN=1E-010 RBPB=5 RBPD=15 RBPS=15 RBDB=15 RBSB=15 NGCON=1
JTSS=1E-4 JTSD=1E-4 JTSSWS=1E-10 JTSSWD=1E-10 JTSSWGS=1E-7 JTSSWGD=1E-7 NJTS=20.0
NJTSSW=20 NJTSSWG=6 VTSS=10 VTSD=10 VTSSWS=10 VTSSWD=10 VTSSWGS=2 VTSSWGD=2
XTSS=0.02 XTSD=0.02 XTSSWS=0.02 XTSSWD=0.02 XTSSWGS=0.02 XTSSWGD=0.02
6.2.6 Transistors
M<name> <drain> <gate> <source> <bulk> <modelname> [parameters]

74 6 SPICE
M1 VDN VDN VSS VSS nmos W=0.6u L=0.15u

M2 VDP VDP VDD VDD pmos W=0.6u L=0.15u
6.2.7 Foundries
Each foundry has their own SPICE models bacause the transistor
parameters depend on the exact physics of the technology!
https://skywater-pdk.readthedocs.io/en/main/
6.3 Find right transistor sizes
Assume active (
𝑉𝑑𝑠 > 𝑉𝑒 𝑓 𝑓
in strong inversion, or
𝑉𝑑𝑠 > 3𝑉𝑇
in weak inversion). For diode connected transistors, that is always
true.
Weak inversion:
𝑊 𝑉𝑒 𝑓 𝑓 /𝑛𝑉𝑇
𝐼𝐷 = 𝐼𝐷 0 𝑒
𝐿
,
𝑉𝑒 𝑓 𝑓 ∝ ln 𝐼𝐷
Strong inversion:
1 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶 𝑜𝑥 𝑉𝑒2𝑓 𝑓
2 𝐿
, p
𝑉𝑒 𝑓 𝑓 ∝ 𝐼𝐷
Operating region for a diode connected transistor only depends

on the current
6.3 Find right transistor sizes 75
6.3.1 Use unit size transistors for analog design
𝑊/𝐿 ≈∈ [4, 6, 10]

, but should have space for two contacts
Use parallel transistors for larger W/L

76 6 SPICE
Amplifiers
⇒ 𝐿 ≈ 1.2 × 𝐿𝑚𝑖𝑛
Current mirrors
⇒ 𝐿 ≈ 4 × 𝐿𝑚𝑖𝑛
Choose sizes that have been used by foundry for measurement to

match SPICE model
6.3.2 What about gm/Id ?
Weak
𝑔𝑚 1
=
𝐼𝑑 𝑛𝑉𝑇
Strong
𝑔𝑚 2
=
𝐼𝑑 𝑉𝑒 𝑓 𝑓
6.3.3 Characterize the transistors
http://analogicus.com/cnr_atr_sky130nm/mos/CNRATR_N
CH_2C1F2.html
6.4 More information
Ngspice Manual
Installing tools
6.5 Analog Design
1. Define the problem, what are you trying to solve?

2. Find a circuit that can solve the problem (papers, books)
3. Find right transistor sizes. What transistors should be weak
inversion, strong inversion, or don’t care?
4. Check operating region of transistors (.op)
5. Check key parameters (.dc, .ac, .tran)
6. Check function. Exercise all inputs. Check all control sig-
nals
7. Check key parameters in all corners. Check mismatch (Monte-
Carlo simulation)
8. Do layout, and check it’s error free. Run design rule checks
(DRC). Check layout versus schematic (LVS)
6.6 Demo 77
9. Extract parasitics from layout. Resistance, capacitance, and

inductance if necessary.
10. On extracted parasitic netlist, check key parameters in all
corners and mismatch (if possible).
11. If everything works, then your done.
On failure, go back
6.6 Demo
https://github.com/analogicus/jnw_spice_sky130A/tree/mai
n
Mixed Signal Simulation in
NGSPICE 7
7.1 Mixed Signal Simulation in ngspice 7.1 Mixed Signal Simula-
tion in ngspice . . . . . 79
7.2 Digital simulation . . . 79
7.2 Digital simulation 7.3 Transient analog simu-
lation . . . . . . . . . . . 80
▶ The order of execution of events at the same time-step do 7.4 Demo . . . . . . . . . . . 82

not matter 7.5 The circuit . . . . . . . . 82
▶ The system is causal. Changes in the future do not affect 7.6 The digital code . . . . 83
signals in the past or the now 7.7 Compile RTL . . . . . . 84
7.8 Import object into
There are both commercial an open source tools for digital simula- SPICE file . . . . . . . . 84
tion. If you’ve never used a digital simulator, then I’d recommend 7.9 Import in testbench . . 85
you start with iverilog. I’ve made some examples at dicex. 7.10 Override default digital
output voltage . . . . . 85
Commercial
7.11 Running . . . . . . . . . 86
▶ Cadence Excelium
▶ Siemens Questa
▶ Synopsys VCS
Open Source
▶ iverilog/vpp
▶ Verilator
▶ SystemDotNet
Below is an example of a counter in SystemVerilog. The code can

be found at counter_sv.
In the always_comb section we code what will become the combi-

natorial logic. In the always_ff section we code what will become
our registers.
module dig(
input wire clk,
input wire reset,
output logic [4:0] b
);
logic rst = 0;
always_ff @(posedge clk) begin

if(reset)
rst <= 1;
else
80 7 Mixed Signal Simulation in NGSPICE
rst <= 0;
end

if(rst)
b <= 0;
else
b <= b + 1;
end // dig
endmodule
7.3 Transient analog simulation
Analog simulation is different. There is no quantized time step.

How fast “things” happen in the circuit is entirely determined by
the time constants, change in voltage, and change in current in the
system.
It is possible to have a fixed time-step in analog simulation, for

example, we say that nothing is faster than 1 fs, so we pick that
as our time step. If we wanted to simulate 1 s, however, that’s at
least 1e15 events, and with 1 event per microsecond on a computer
it’s still a simulation time of 31 years. Not a viable solution for all
analog circuits.
Analog circuits are also non-linear, properties of resistors, capac-

itors, inductors, diodes may depend on the voltage or current
across, or in, the device. Solving for all the non-linear differential
equations is tricky.
An analog simulation engine must parse spice netlist, and setup

partial/ordinary differential equations for node matrix
The nodal matrix could look like the matrix below, 𝑖 are the currents,
𝑣 the voltages, and 𝐺 the conductances between nodes.
𝐺11 𝐺12 ··· 𝐺1𝑁 𝑣1 𝑖1

𝐺21 𝐺22 · · · 𝐺2𝑁 ® 𝑣2 ® 𝑖2 ®
© ª© ª © ª
. .. .. .. ®® .. ®® = .. ®®
. .
. . . ® . ® . ®
« 𝐺 𝑁 1 𝐺 𝑁 2 · · · 𝐺 𝑁 𝑁 ¬ «𝑣 𝑁 ¬ « 𝑖 𝑁 ¬
The simulator, and devices model the non-linear current/voltage

behavior between all nodes
as such, the 𝐺 ’s may be non-linear functions, and include the 𝑣 ’s

and 𝑖 ’s.
7.3 Transient analog simulation 81
Transient analysis use numerical methods to compute time evolu-

tion
The time step is adjusted automatically, often by proprietary algo-

rithms, to trade accuracy and simulation speed.
The numerical methods can be forward/backward Euler, or the

others listed below.
▶ Euler
▶ Runge-Kutta
▶ Crank-Nicolson
▶ Gear
If you wish to learn more, I would recommend starting with the

original paper on analog transient analysis.
SPICE (Simulation Program with Integrated Circuit Emphasis)

published in 1973 by Nagel and Pederson
The original paper has spawned a multitude of commercial, free

and open source simulators, some are listed below.
If you have money, then buy Cadence Spectre. If you have no

money, then start with ngspice.
Commercial - Cadence Spectre - Siemens Eldo - Synopsys

HSPICE
Free - Aimspice - Analog Devices LTspice - xyce
Open Source - ngspice

Digital Analog
Simulator Simulator
Event Timester Control
7.4 Demo
Tutorial at http://analogicus.com/jnw_sv_sky130a/
Repository at https://github.com/wulffern/jnw_sv_sky130a
Assumes knowledge of Tutorial
7.5 The circuit
In design/JNW_SV_SKY130A/JNWSW_CM.sch you’ll find a current

mirror, and a 5-bit current DAC.
What we want from the digital is to control the binary value of the
current DAC.
7.6 The digital code 83
7.6 The digital code
The digital code is shown below. The clk controls the stepping,
while the reset sets the output b=0. When reset is off, then the b
increments.
module dig(
input wire clk,
input wire reset,
output logic [4:0] b
);
logic rst = 0;

if(reset)
rst <= 1;
else
rst <= 0;
end

if(rst)
b <= 0;
else
b <= b + 1;
end // dig
endmodule
7.7 Compile RTL
The first thing we need to do is to translate the verilog into a

compiled object that can be used in ngspice.
cd sim/JNWSW_CM
ngspice vlnggen ../../rtl/dig.v
7.8 Import object into SPICE file
I’m lazy. So I don’t want to do the same thing multiple times. As

such, I’ve written a small script to help me instanciate the verilog
perl ../../tech/script/gensvinst ../../rtl/dig.v dig
The script generates an svninst.spi file. The first section imports

the digital compiled library
adut [clk
+ reset
+ ]
+ [b.4
+ b.3
+ b.2
+ b.1
+ b.0
+ ] null dut
.model dut d_cosim
+ simulation="../dig.so" delay=10p
Turns out that ngspice needs the digital inputs and outputs to
be connected to something to calculate them (I think), so connect
some resistors
* Inputs
Rsvi0 clk 0 1G
Rsvi1 reset 0 1G
* Outputs
Rsvi2 b.4 0 1G
Rsvi3 b.3 0 1G
Rsvi4 b.2 0 1G
Rsvi5 b.1 0 1G
Rsvi6 b.0 0 1G
7.9 Import in testbench 85
For the busses I find it easier to read the value as a real, so translate
the buses from digital b[4:0] to a real value dec_b
E_STATE_b dec_b 0 value={( 0

+ + 16*v(b.4)/AVDD
+ + 8*v(b.3)/AVDD
+ + 4*v(b.2)/AVDD
+ + 2*v(b.1)/AVDD
+ + 1*v(b.0)/AVDD
+)/1000}
.save v(dec_b)
7.9 Import in testbench
An example testbench can be seen below (sim/JNWSW_-

CM/tran.spi)
...
.include ../xdut.spi
.include ../svinst.spi
* Translate names
VB0 b.0 b<0> dc 0
VB1 b.1 b<1> dc 0
VB2 b.2 b<2> dc 0
VB3 b.3 b<3> dc 0
VB4 b.4 b<4> dc 0
...
7.10 Override default digital output voltage
We can override the output dac from digital to analog to ensure

that the digital signals have the right levels
*- Override the default digital output bridge.

pre_set auto_bridge_d_out =
+ ( ".model auto_dac dac_bridge(out_low =te 0.0 out_high = 1.8)"
+ "auto_bridge%d [ %s ] [ %s ] auto_dac" )
7.11 Running
You can run the whole thing with
cd sim/JNWSW_CM/
make typical
Sky130nm tutorial 8
8.1 Tools . . . . . . . . . 87
8.1 Tools
8.1.1 Setup WSL (Appli-
cable for Windows
I would strongly recommend that you install all tools locally on users) . . . . . . . . . 87
your system. 8.1.2 Setup public key
towards github . . . 87
For the analog toolchain we need some tools, and a process design 8.1.3 Get AICEX and setup
kit (PDK). your shell . . . . . . 88
8.1.4 On systems with
▶ Skywater 130nm PDK. I use open_pdks to install the PDK python3 > 3.12 . . . 88
▶ Magic VLSI for layout 8.1.5 Install Tools . . . . . 88
▶ ngspice for simulation 8.1.6 Install cicconf . . . . 89
8.1.7 Install cicsim . . . . 89
▶ netgen for LVS
8.1.8 Setup your ngspice
▶ xschem settings . . . . . . . . 89
▶ python > 3.10
8.2 Check that magic
and xschem works . 90
The tools are not that big, but the PDK is huge, so you need to have
8.3 Design tutorial . . . 90
about 50 GB disk space available.
8.3.1 Create the IP . . . . . 90
8.3.2 The file structure . . 90
8.3.3 Github setup . . . . 92
8.1.1 Setup WSL (Applicable for Windows users) 8.3.4 Start working . . . . 93
8.3.5 Draw Schematic . . 93
Install a Linux distribution such as Ubuntu 24.04 LTS by running 8.3.6 Typical corner SPICE
the following command in PowerShell on Windows and follow the simulation . . . . . . 95
instructions. 8.3.7 All corners SPICE
simulations . . . . . 98
wsl --install -d Ubuntu-24.04 8.3.8 Draw Layout . . . . 100
8.3.9 Layout verification 107
When you have installed the Linux distribution and signed into it, 8.3.10 Extract layout para-
install make sitics . . . . . . . . . 109
8.3.11 Simulate with layout
sudo apt install make parasitics . . . . . . 109
8.3.12 Make documentation 110
8.3.13 Edit info.yaml . . . . 110
8.3.14 Setup github pages . 111
8.1.2 Setup public key towards github
8.3.15 Frequency asked
questions . . . . . . . 111
Do
ssh-keygen -t rsa
And press “enter” on most things, or if you’re paranoid, add a

passphrase
Then
cat ~/.ssh/id_rsa.pub
88 8 Sky130nm tutorial
And add the public key to your github account. Settings - SSH and
GPG keys
8.1.3 Get AICEX and setup your shell
You don’t have to put aicex in $HOME/pro, but if you don’t know
where to put it, chose that directory.
cd
mkdir pro
cd pro
git clone --recursive https://github.com/wulffern/aicex.git
You need to add the following to your ~/.bashrc (note that

~ refers to your home directory $HOME/.bashrc also works, or
$HOME/.bash_profile on some newer macs)
export PDK_ROOT=/opt/pdk/share/pdk
export LD_LIBRARY_PATH=/opt/eda/lib
export PATH=/opt/eda/bin:$HOME/.local/bin:$PATH
8.1.4 On systems with python3 > 3.12
On newer systems it’s not trivial to install python packages because

python is externally managed. As such, we need to install a python
environment.
#- Find a package similar to name below

sudo apt install python3.12-venv
sudo mkdir /opt/eda/python3
sudo chown -R $USER:$USER /opt/eda/python3/
python3 -m venv /opt/eda/python3
Modify the ~/.bashrc to include the python environment
export PATH=/opt/eda/bin:/opt/eda/python3/bin:$HOME/.local/bin:$PAT
8.1.5 Install Tools
Make sure you load the settings before you proceed
source ~/.bashrc
Hopefully the commands below work, if not, then try again, or try
to understand what fails. There is no point in continuing if one
command fails.
8.1 Tools 89
cd aicex/tests/
make requirements
make tt
make eda_compile
sudo make eda_install
python3 -m pip install matplotlib numpy click svgwrite pyyaml pandas tabulate wheel setuptools
source install_open_pdk.sh
cd ../..
8.1.6 Install cicconf
cIcConf is used for configuration. How the IPs are connected, and
what version of IPs to get.
cd aicex/ip/cicconf
git checkout main
git pull
python3 -m pip install -e .
cd ../
Update IPs
cicconf update
cd ..
8.1.7 Install cicsim
cIcSim is used for simulation orchestration.
cd aicex/ip/cicsim
python3 -m pip install -e .
cd ../..
8.1.8 Setup your ngspice settings
Edit ~/.spiceinit and add
set ngbehavior=hsa ; set compatibility for reading PDK libs

set ng_nomodcheck ; don't check the model parameters
set num_threads=8 ; CPU hardware threads available
set skywaterpdk
option noinit ; don't print operating point data
option klu
optran 0 0 0 100p 2n 0 ; don't use dc operating point, but transient op
option opts
8.2 Check that magic and xschem works
To check that magic and xschem works
cd ~/pro/aicex/ip/sun_sar9b_sky130nm/work
magic ../design/SUN_SAR9B_SKY130NM/SUNSAR_SAR9B_CV.mag &
xschem -b ../design/SUN_SAR9B_SKY130NM/SUNSAR_SAR9B_CV.sch &
8.3 Design tutorial
8.3.1 Create the IP
I’ve made some scripts to automatically generate the IP.
To see what files are generated, see tech_sky130A/cicconf/ip_-

template.yaml
cd aicex/ip
cicconf newip ex
8.3.2 The file structure
It matters how you name files, and store files. I would be surprised
if you had a good method already, as such, I won’t allow you
to make your own folder structure and names for things. I also
control the filenames and folder structure because there are many
scripts to make your life easier (yes, really) that rely on an exact
structure. Don’t mess with it.
8.3.2.1 Github workflows
On github it’s possible use something called workflows to run

things every time you push a new version. It’s really nice, since it
can then do checks that you’re design is valid.
The grading of the milestones is determined by passing github

workflows.
We will also check that you have not cheated, and modified the
workflows just to get them passing.
The workflows are defined below.

8.3 Design tutorial 91
.github
workflows
docs.yaml # Generate a github page
drc.yaml # Run Design Rule Checks
gds.yaml # Generate a GDS file from layout
lvs.yaml # Run Layout Versus Schematic and Layout Parasitic Extraction
sim.yaml # Run a simulation
8.3.2.2 Configuration files
Each IP has a few files that define the setup, you’ll need to modify
at least the README.md and the info.yaml.
.gitignore # files that are ignored by git

README.md # Frontpage documentation
config.yaml # What libraries are used. This file can be used by cicconf
info.yaml # Setup names, authors etc
media # Where you should store images for documentation
tech -> ../tech_sky130A # The technology library
8.3.2.3 Design files
A “cell” in the open source EDA world should consists of the

following files
▶ Schematic (.sch)
▶ Layout (.mag)
▶ Documenation (.md)
The files must have the same name, and must be stored in
design/<LIB>/ as shown below.
Note there are also two symbolic links to other libraries. These two
libraries contain standard cells and standard analog transistors
(ATR) that you should be using.
design
JNW_EX_SKY130A
JNW_EX.sch
JNW_ATR_SKY130A -> ../../jnw_atr_sky130a/design/JNW_ATR_SKY130A
JNW_TR_SKY130A -> ../../jnw_tr_sky130a/design/JNW_TR_SKY130A
For example, if the cell name was JNW_EX, then you would have
▶ design/JNW_EX_SKY130A/JNW_EX.sch: Schematic (xschem)

▶ design/JNW_EX_SKY130A/JNW_EX.sym: Schematic (xschem)
▶ design/JNW_EX_SKY130A/JNW_EX.mag: Layout (Magic)
▶ design/JNW_EX_SKY130A/JNW_EX.md : Markdown docu-

mentation (any text editor)
All these files are text files, so you can edit them in a text editor,
but mostly you shouldn’t (except for the Markdown)
8.3.2.4 Simulations
All simulations shall be stored in sim. Once you have a Schematic

ready for simulation, then
cd sim
make cell CELL=JNW_EX
This will make a simulation folder for you. Repeat for all your
cells.
sim
Makefile
cicsim.yaml -> ../tech/cicsim/cicsim.yaml
8.3.2.5 The work
All commands (except for simulation), shall be run in the work

folder.
In the work/ folder there are startup files for Xschem (xschemrc)
and Magic (.magicrc). They tell the tools where to find the process
design kit, symbols, etc. At some point you probably need to learn
those also, but I’d wait until you feel a bit more comfortable.
work
.magicrc
Makefile
mos.24bit.dstyle -> ../tech/magic/mos.24bit.dstyle
mos.24bit.std.cmap -> ../tech/magic/mos.24bit.std.cmap
xschemrc
8.3.3 Github setup
Create a repository on github
cd jnw_ex_sky130nm
git remote add origin \
[email protected]:<your user name>/jnw_ex_sky130nm.git
8.3.4 Start working
8.3.4.1 Edit README.md
Open README.md in your favorite text editor and make necessary

changes.
8.3.4.2 Familiarize yourself with the Makefile and make
I write all commands I do into a Makefile. There is nothing special

with a Makefile, it’s just what I choose to use 20 years ago. I’m not
sure I’d choose something different now.
cd work
make
Take a look inside the file called Makefile.
8.3.5 Draw Schematic
The block we’ll make is a current mirror with a 1 to 5 scaling.
A schematic is how we describe the connectivity, and the types of

devices in an analog circuit. The open source schematic editor we
will use is XSchem.
Open the schematic:
xschem -b ../design/JNW_EX_SKY130A/JNW_EX.sch &
8.3.5.1 Add Ports
Add IBPS_5U and IBNS_20U ports, the P and N in the name

signifies what transistor the current comes from. So IBPS must go
into a diode connected NMOS, and N will be our output, and go
into a diode connected PMOS somewhere else.
8.3.5.2 Add transistors
Use ‘Shift-I’ to open the library manager. Click the jnw_ex0_-

sky130A/design path, then JNW_ATR_SKY130A and select JNW_-
ATR_4C5F0.sym
The naming convention for these transistors is <number of

contacts on drain/source>C<times minimum gate length>F,
so the before the C is the width, and before/after the F is the
length. The absolute size does not matter for now. Just think
“4C5F0 is a 4 contact wide long transistor”, while a “4C1F2 is a 4
contact wide, short transistor”.
Select the transistor and press ‘c’ to copy it, while dragging, press
‘shift-f’ to flip the transistor so our current mirror looks nice. ‘shift-r’
rotates the transistor, but we don’t want that now.
Press ESC to deselect everything
Select the input transistor, and change the name to ‘xi’
Select the output transistor, and change the name to ‘xo[3:0]’. Using
bus notation on the name will create 4 transistors
Select ports, and use ‘m’ to move the ports close to the transistors.
Press ‘w’ to route wires.
Use ‘shift-z’ and z, to zoom in and out
Use ‘f’ to zoom full screen
Remember to save the schematic

8.3.5.3 Netlist schematic
Check that the netlist looks OK
In work/
make xsch CELL=JNW_EX

cat xsch/JNW_EX.spice
8.3.6 Typical corner SPICE simulation
I’ve made cicsim that I use to run simulations (ngspice) and extract
results
8.3.6.1 Setup simulation environment
Navigate to the jnw\_ex0\_sky130nm/sim/ directory.
Make a new simulation folder
cicsim simcell JNW_EX_SKY130A JNW_EX ../tech/cicsim/cell_spice/template.yaml
I would recommend you have a look at simcell_template.yaml file

to understand what happens.
8.3.6.2 Familiarize yourself with the simulation folder
I’ve added quite a few options to cicsim, and it might be confusing.

For reference, these are what the files are used for
File Description
Makefile Simulation commands
cicsim.yaml Setup for cicsim
summary.yaml Generate a README with simulation results
tran.meas Measurement to be done after simulation
tran.py Optional python script to run for each simulation
tran.spi Transient testbench
tran.yaml What measurements to summarize
The default setup should run, so
cd JNW_EX
make typical
8.3.6.3 Modify default testbench (tran.spi)
Delete the VDD source
Add a current source of 5uA, and a voltage source of 1V to IBNS_-

20U
IBP 0 IBPS_5U dc 5u
V0 IBNS_20U 0 dc 1
Save the current in V0 by adding i(V0) to the save statement in the

testbench
Save the voltage by adding v(IBPS_5U) to the save statement
.save i(V0) v(IBPS_5U)
8.3.6.4 Modify measurements (tran.meas)
Add measurement of the current and VGS. It must be added

between the “MEAS_START” and “MEAS_END” lines.
let ibn = -i(v0)

meas tran ibns_20u find ibn at=5n
meas tran vgs_m1 find v(ibps_5u) at=5n
Run simulation
make typical
and check that the output looks okish.
Try to run the simulation again
make typical
If everything works, then the simulation now should not be run.

Every time cicsim runs (provided the sha: True option is set in
cicsim.yaml) cicsim will compute a SHA hash of all files (stored
in output_tran/.sha) that is referenced in the tran.spi. Next time
cicsim is run, it checks the hash’s and does not re-run if there is no
need (no files changed).
Sometimes you want to force running, and you can do that by
make typical OPT="--no-sha"
Often, it’s the measurement that I get wrong, so instead of rerun-

ning simulation every time I’ve added a “–no-run” option to cicsim.
For example
make typical OPT="--no-run"

will skip the simulation, and rerun only the measurement. This is
why you should split the testbench and the measurement. Simula-
tions can run for days, but measurement takes seconds.
8.3.6.5 Modify result specification (tran.yaml)
Add the result specifications, for example
ibn:
src:
- ibns_20u
name: Output current
min: -20%
typ: 20
max: 20%
scale: 1e6
digits: 3
unit: uA
vgs:
src:
- vgs_m1
name: Gate-Source voltage
typ: 0.6
min: 0.3
max: 0.7
scale: 1
digits: 3
unit: V
Re-run the measurement and result generation
make typical OPT="--no-run"
Open result/tran_Sch_typical.html
8.3.6.6 Check waveforms
You can either use ngspice, or you can use cicsim, or you can use
something I don’t know about
Open the raw file with
cicsim wave output_tran/tran_SchGtKttTtVt.raw
Load the results, and try to look at the plots. There might not be
that much interesting happening
8.3.7 All corners SPICE simulations
Analog circuits must be simulated for all physical conditions,

we call them corners. We must check high and low temperature,
high and low voltage, all process corners, and device-to-device
mismatch.
For the current mirror we don’t need to vary voltage, since we

don’t have a VDD.
8.3.7.1 Remove Vh and Vl corners (Makefile)
Open Makefile in your favorite text editor.
Change all instances of “Vt,Vl,Vh” and “Vl,Vh” to Vt
8.3.7.2 Run all corners
To simulate all corners do
make typical etc mc
where etc is extreme test condition and mc is monte-carlo.
Wait for simulations to complete.
8.3.7.3 Get creative with python
Open tran.py in your favorite editor, try to read and understand

it.
The name parameter is the corner currently running, for example

tran_SchGtAmcttTtVt.
The measured outputs from ngspice will be added to tran_-

SchGtAmcttTtVt.yaml
Delete the “return” line.
Add the following lines (they automatically plot the current and
gate voltage)
import cicsim as cs
fname = name +".png"
print(f"Saving {fname}")
cs.rawplot(name + ".raw","time","v(ibps_5u),i(v0)",ptype="",fname=f
Re-run measurements to check the python code
make typical etc mc OPT="--no-run"

You’ll see that cicsim writes all the png’s. Check with ls -l
output_tran/*.png.
You’ll also notice it will slow down the simulation, so maybe

remove the lines from tran.py again ;-)
8.3.7.4 Generate simulation summary
Run
make summary
Install pandoc if you don’t have it
Run
pandoc -s -t slidy README.md -o README.html
to generate a HTML slideshow that you can open in browser. Open

the HTML file.
8.3.7.5 Viewing results without GUI browser
If your on a system without a browser, or indeed a GUI, then it’s

possible to view the results in the terminal.
Check if lynx is installed, if it’s not installed, then
On linux
sudo apt-get install lynx
On Mac
brew install lynx
Then
lynx README.html
8.3.7.6 Think about the results
From the corner and mismatch simulation, we can observe a few

things.
▶ The typical value is not 20 uA. This is likely because we have

a M2 VDS of 1 V, which is not the same as the VDS of M1. As
such, the current will not be the same.
▶ The statistics from 30 corners show that when we add or
subtract 3 standard deviation from the mean, the resulting
current is outside our specification of +- 20 %. I’ll leave it up
to you to fix it.
8.3.8 Draw Layout
A foundry (the factory that makes integrated circuits) needs to

know how we want them to create our circuit. So we need to provide
them with a “layout”, the recipe, or instruction, for how to make
the circuit. Although the layout contains the same components as
the schematic, the layout contains the physical locations, and how
to actually instruct the foundry on how to make the transistors we
want.
Open Magic VLSI
cd work
magic ../design/JNW_EX_SKY130A/JNW_EX.mag
Now brace yourself, Magic VLSI was created in the 1980’s. For
it’s time it was extremely modern, however, today it seems dated.
However, it is free, so we use it.
8.3.8.1 Magic VLSI
Try google for most questions, and there are youtube videos that
give an intro.
▶ Magic Tutorial 1
▶ Magic command reference
▶ Magic Documentation
Default magic start with the BOX tool. Mouse left-click to select
bottom corner, left-click to select top corner.
Press “space” to select another tool (WIRING, NETLIST, PICK).
Type “macro help” in the command window to see all shortcuts

Hotkey Function
v View all
shift-z zoom out
z zoom in
x look inside box (expand)
shift-x don’t look inside box (unexpand)
u undo
d delete
s select
Shift-Up Move cell up
Shift-Down Move cell down
Shift-Left Move cell left
Shift-Right Moce cell right
8.3.8.2 Add transistors
Open Cell -> Place Instance. Navigate to the right transistor.
Place it. Hover over the transistor and select it with ‘s’. Now comes
a bit of tedious thing. Select again, and copy. It’s possible to align
the transistors on-top of eachother, but it’s a bit finicky.
Place all transistors on top of each other.

8.3.8.3 Add Ground
In the command window, type
see no *
see viali
see locali
see m1
see via1
see m2
Change to the ‘wire tool’ with spacebar. Press the top transistor ‘S’
and draw all the way down.
Change grid to 0.5 um.
Select a 0.5 um box below the transistors and paint the rectangle
(middle click on locali)
Connect guard rings to ground. Use the ‘wire tool’
Connect the sources to ground. Use the ‘wire tool’. Use ‘shift-right
click’ to change layer down
8.3.8.4 Route Gates
Press “space” to enter wire mode. Left click to start a wire, and
right click to end the wire.
The drain of M1 transistor needs a connection to from gate to drain.

We do that for the middle transistor.
Start the route, press ‘shift-left click’ to go up one layer, route over
to drain, and ‘shift-right click’ to go down.
8.3.8.5 Drain of M2
Use the wire tool to draw connections for the drains.
To add vias you can do “shift-left click” to move up a metal, and

“shift-right click” to go down.
8.3.8.6 Add labels
Select a box on a metal, and use “Edit->Text” to add labels for the
ports. Select the port button.
8.3.9 Layout verification
The DRC can be seen directly in Magic VLSI as you draw.
To check layout versus schematic navigate to work/ and do
make cdl lvs
If you’ve routed correctly, then the LVS should be correct.

8.3.10 Extract layout parasitics
With the layout complete, we can extract parasitic capacitance.
make lpe
Check the generated netlist
cat lpe/JNW_EX_lpe.spi
8.3.11 Simulate with layout parasitics
Navigate to sim/JNW_EX. We now want to simulate the layout.
The default tran.spi should already have support for that.
Open the Makefile, and change
VIEW=Sch
to
VIEW=Lay
8.3.11.1 Typical simuation
Run
make typical
8.3.11.2 Corners
Navigate to sim/JNW_EX. Run all corners again
make all
8.3.11.3 Simulation summary
Open summary.yaml and add the layout files.
- name: Lay_typ
src: results/tran_Lay_typical
method: typical
- name: Lay_etc
src: results/tran_Lay_etc
method: minmax
- name: Lay_3std
src: results/tran_Lay_mc
method: 3std
Run summary again
make summary
pandoc -s -t slidy README.md -o README.html
Open the README.html and have a look a the results. The layout
should be close to the schematic simulation.
8.3.12 Make documentation
Make a file (or it may exists) design/JNW_EX_SKY130A/JNW_EX.md

and add some docs.
8.3.13 Edit info.yaml
Finally, let’s setup the info.yaml so that all the github workflows
run correctly.
Mine will look like this.
You need to setup the url (probably something like <your

username>.github.io) to what is correct for you.
I’ve added the doc section such that the workflows will generate
the docs.
The sim is to run a typical simulation.
library: JNW_EX_SKY130A
cell: JNW_EX
author: Carsten Wulff
github: wulffern
tagline: The answer is 42
email: [email protected]
url: analogicus.github.io
doc:
libraries:
JNW_EX_SKY130A:
- JNW_EX
sim:
JNW_EX: make typical
8.3.14 Setup github pages
Go to github. Press Settings. Press Pages. Choose Build and De-

ployment -> GitHub Actions
Wait for the workflows to build. And check your github

pages. Mine is [https://analogicus.github.io/jnw_ex0_-
sky130a/](https://analogicus.github.io/jnw_ex0_sky130a/**
8.3.15 Frequency asked questions
My GDS/LVS/DRC action fails, even though it works locally.
Sometimes the reference to the transistors in the magic file might

be wrong. Open the .mag file in a text editor and check. The correct
way is
use JNWATR_NCH_4C5F0 JNWATR_NCH_4C5F0_0 ../JNW_ATR_SKY130A
It’s the last ../JNW_ATR_SKY130A that sometimes is missing.

IC and ESD 9
9.0.1 What blocks must our IC include? 9.0.1 What blocks must our
IC include? . . . . . . 113
9.1 Electrostatic Dis-
The project for 2024 is to design an integrated temperature sensor.
charge . . . . . . . . . 116
First, we need to have an idea of what comes in and out of the 9.1.1 When do ESD events
occur? . . . . . . . . . 117
temperature sensor. Before we have made the temperature sensor,
9.1.2 Before/during PCB . 117
we need to think what the signal interface could be, and we need 9.1.3 After PCB . . . . . . . 118
to learn. 9.1.4 Human body model
(HBM) . . . . . . . . . 118
Maybe we read Kofi Makinwa’s overview of temperature sensors
9.1.5 Charged device model
and find one of the latest papers, (CDM) . . . . . . . . . 119
A BJT-based CMOS Temperature Sensor with Duty-cycle- 9.2 An HBM ESD zap
example . . . . . . . . 121
modulated Output and ±0.54 °C (3-sigma) Inaccuracy from -40 °C
to 125 °C. 9.3 Permutations . . . . . 122
9.3.1 Why does this work? 124
At this point, you may struggle to understand the details of the 9.3.2 How can current in
paper, but at least it should be possible to see what comes in and one place lead to a
current somewhere
out of the module. What I could find is in the table below, maybe
else? . . . . . . . . . . 127
you can find more?
9.4 Want to learn more? 130
Pin Function in/out Value Unit

VDD_3V3 analog supply in 3.0 V
VDD_1V2 digital supply in 1.2 V
VSS ground in 0 V
CLK_1V2 clock in 20 MHz
RST_1V2 digital out 0 or 1.2 V
I_C bias in ? uA?
PHI1_1V2 digital out 0 or 1.2 V
PHI2_1V2 digital out 0 or 1.2 V
DCM_1V2 digital out 0 or 1.2 V
This list contains supplies, clocks, digital outputs, bias currents

and a ground. Let me explain what they are.
9.0.1.1 Supply
The temperature sensor has two supplies, one analog (3.3 V) and
one digital (1.2 V), which must come from somewhere.
We’re using Skywater, and to use the free tapeouts we must use
the Caravel test chip harness.
114 9 IC and ESD
That luckily has two supplies. It can be powered externally by up

to 5.0 V, and has an external low dropout regulator (LDO) that
provides the digital supply (1.8 V).
See more at Absolute maximum ratings
9.0.1.2 Ground
Most ICs have a ground, a pin which is considered 0 V. It may

have multiple grounds. Remember that a voltage is only defined
between two points, so it’s actually not true to talk about a voltage
in a node (or on a wire). A voltage is always a differential to
something. We’ve (as in global electronics engineers) have just
agreed that it’s useful to have a “node” or “wire” we consider 0
V.
9.0.1.3 Clocks
Most digital need a clock, and the Caravel provide a 40 MHz clock
which should suffice for most things. We could probably just use
that clock for our temperature sensor.
9.0.1.4 Digital
We need to read the digital outputs. We could either feed those

off chip, or use a on chip micro-controller. The Caravel includes
options to do both. We could connect digital outputs to the logic
analyzer, and program the RISC-V to store the readings. Or we
could connect the digital output to the I/O and use an instrument
in the lab.
9.0.1.5 Bias
The Caravel does not provide bias currents (that I found), so that
is something you will need to make.
9.0.1.6 Conclusion
Even a temperature sensor needs something else on the IC. We

need digital input/output, clock generation (PLL, oscillators),
bias current generators, and voltage regulators (which require a
constant reference voltage).
I would claim that any System-On-Chip will always need these

blocks!
115
I want you to pause, take a look at the
course plan
and now you might understand why I’ve selected the topics.
9.0.1.7 One more thing
There is one more function we need when we have digital logic

and a power supply. We need a “RESET” system.
Digital logic has a fundamental assumption that we can separate

between a “1” and a “0”, which is usually translated to for example
1.8 V (logic 1) and 0 V (logic 0). But if the power supply is at 0 V,
before we connect the battery, then that fundamental assumption
breaks.
When we connect the battery, how do we know the fundamental

assumption is OK? It’s certainly not OK at 30 mV supply. How
about 500 mV? or 1.0 V? How would we know?
Most ICs will have a special analog block that can keep the digital
logic, bias generators, clock generators, input/output and voltage
regulators in a safe state until the power supply is high enough
(for example 1.62 V).
One of the challenges with a POR is that we want to keep the

system in a reset state until we’re sure that the power is on. Another
challenge is that the POR should not consume current.
If we make a level triggered (triggers when VDD reaches a certain

level), then we need a reference, a comparator and maybe other
circuits. As a result, potentially high current.
If we make a delay based POR, then we need a long delay, which

means large resistors or capacitors. Accordingly, high cost.
Below is an idea for a Power-On-Reset (POR) I had way back when.

The POR uses a delay based on the tunneling current in a thin oxide
transistor (2), and uses a thick-oxide transistor (3) as a capacitor.
The output X would go to a Schmitt trigger (5).
116 9 IC and ESD
9.1 Electrostatic Discharge
If you make an IC, you must consider Electrostatic Discharge (ESD)

Protection circuits
ESD events are tricky. They are short (ns), high current (Amps)
and poorly modeled in the SPICE model.
Most SPICE models will not model correctly what happens to an

transistor during an ESD event. The SPICE models are not made to
model what happens during an ESD event, they are made to model
how the transistors behave at low fields and lower current.
But ESD design is a must, you have to think about ESD, otherwise
your IC will never work.
Consider a certain ESD specification, for example 1 kV human

body model, a requirement for an integrated circuit.
By requirement I mean if the 1 kV is not met, then the project will

be delayed until it is fixed. If it’s not fixed, then the project will be
infinitely delayed, or in other words, canceled.
Now imagine it’s your responsibility to ensure it meets the 1 kV

specification, what would you do? I would recommend you read
one of the few ESD books in existence, shown below, and rely on
you understanding of PN-junctions.
9.1 Electrostatic Discharge 117
The industry has agreed on some common test criteria for elec-
trostatic discharge. Test that model what happens when a person
touches your IC, during soldering, and PCB mounting. If your
IC passes the test then it’s probably going to survive in volume
production
Standards for testing at JEDEC
9.1.1 When do ESD events occur?
9.1.2 Before/during PCB
Human body model (HBM)
Models a person touching a device with a finger.

118 9 IC and ESD
Charged device model (CDM)
Models a device in an electric field where one pin is suddenly

connected
9.1.3 After PCB
Human body model (HBM)
System level ESD
Once mounted on the PCB, the ICs can be more protected against
ESD events, however, it depends on the PCB, and how that reacts
to a current.
Take a look at your USB-A connector, you will notice that the outer
pins, the power and ground, are made such that they connect first,
The 𝐷+ and 𝐷− pins are a bit shorter, so they connect some 𝜇s
later. The reason is ESD. The power and ground usually have a
low impedance connection in decoupling capacitors and power
circuits, so those can handle a large ESD zap. The signals can go
directly to an IC, and thus be more sensitive.
We won’t go into details on System level ESD, as that is more a

PCB type of concern. The physics are the same, but the details are
different.
9.1.4 Human body model (HBM)
▶ Models a person touching a device with a finger

▶ Long duration (around 100 ns)
▶ Acts like a current source into a pin
▶ Can usually be handled in the I/O ring
▶ 4 kV HBM ESD is 2.67 A peak current
9.1 Electrostatic Discharge 119
1.5 kOhm
100 pF
9.1.5 Charged device model (CDM)
An IC left alone for long enough will equalize the

Fermi potential across the whole IC.
Not entirely a true statement, but roughly true. One exception

is non-volatile memory, like flash, which uses Fowler-Norheim
100 k a capacitor that keeps it’s charge
tunneling to charge and discharge 1.5 k
for a very, very long time.
I’m pretty sure that if you leave an SSD hardrive to the heat death of
1056
100will
the universe in maybe 1010 years, then the charges pF equalize,
and the Fermi level will be the same across the whole IC, so it’s
just a matter of time.
Assume there is an equal number of electrons and protons on the

IC. According to Gauss’ law
∮ ∭
1
𝜕Ω 𝜖0 𝑉
So there is no external electric field from the IC.
If we place an IC in an electric field, the charges inside will

redistribute. Flip the IC on it’s back, place it on an metal plate with
an insulator in-between, and charge the metal plate to 1 kV.
120 9 IC and ESD
Inside the IC electrons and holes will redistribute to compensate for

the electric field. Closest to the metal plate there will be a negative
charge, and furthest away there will be a positive charge.
This comes from the fact that if you leave a metal inside an electric
field for long enough the metal will not have any internal field. If
there was an internal field, the charges would move. Over time the
charges will be located at the ends of the metal.
Take a grounded wire, touch one of the pins on the IC. Since we
now have a metal connection between a pin and a low potential
the charges inside the IC will redistribute extremely quickly, on
the order of a few ns.
During this Charged Device Model event the internal fields in the
IC will be chaotic, but at any given point in time, the voltage across
sensitive devices must remain below where the device physically
breaks.
Take the MOSFET transistor. Between the gate and the source there
is an thin oxide, maybe a few nm. If the field strength between gate
and source is high enough, then the force felt by the electrons in
co-valent bonds will be 𝐹® = 𝑞 𝐸®. At some point the co-valent bonds
might break, and the oxide could be permanently damaged. Think
of a lighting bolt through the oxide, it’s a similar process.
Our job, as electronics engineers, is to ensure we put in additional

circuits to prevent the fields during a CDM event from causing
damage.
For example, let’s say I have two inverters powered by different

supply, VDD1 and VDD2. If I in my ESD test ground VDD1, and
not VDD2, I will quickly bring VDD1 to zero, while VDD2 might
react slower, and stay closer to 1 kV. The gate source of the PMOS
in the second inverter will see approximately 1 kV across the oxide,
and will break. How could I prevent that?
9.2 An HBM ESD zap example 121
Assuming some luck, then VDD1 and VDD2 are separate, but
the same voltage, or at least close enough, I can take two diodes,
connected in opposite directions, between VDD1 and VDD2. As
such, when VDD1 is grounded, VDD2 will follow but maybe be
0.6 V higher. As a result, the PMOS gate never sees more than
approximately 0.6 V across the gate oxide, and everyone is happy.
Now imagine an IC will hundreds of supplies, and billions of

inverters. How can I make sure that everything is OK?
CDM is tricky, because there are so many details, and it’s easy to
miss one that makes your circuit break.
9.2 An HBM ESD zap example
Imagine a ESD zap between VSS and VDD. How can we protect
the device?
The positive current enters the VSS, and leaves via the VDD, so
our supplies are flipped up-side down. It’s a fair assumption that
none of the circuits inside will work as intended.
But the IC must not die, so we have to lead the current to ground
somehow
122 9 IC and ESD
100 k
1.5 k
100 pF
9.3 Permutations
Let’s simplify and think of the possible permutations, shown in

the figure below. We don’t know where the current will enter
nor where it will leave our circuit, so we must make sure that all
combinations are covered.
DD
e
ON 1 vs euro
1 to vno vss
us a Pin
of 2 pin
pin a Uss 2
2 to
1 02 vase PIN
PIN a Vbs
2 A 1
Uss
O
When the current enters VSS and must leave via VDD, then it’s
simple, we can use a diode.
Under normal operation the diode will be reverse biased, and

although it will add some leakage, it will not affect the normal
operation of our IC.
9.3 Permutations 123
I un
PIN
2
on
O Uss
The same is true for current in on VSS and out on PIN. Here we
can also use a diode.
VDP
g
2 PIN
on or
O Uss
For a current in on VDD and out on VSS we have a challenge.

That’s the normal way for current to flow.
For those from Norway that have played a kids game Bjørnen sover,
that’s a apt mental image. We want a circuit that most of the time
124 9 IC and ESD
sleeps, and does not affect our normal IC operation. But if a huge
current comes in on VDD, and the VDD voltage shoots up fast, the
circuit must wake up and bring the voltage down.
If the circuit triggers under normal operating condition, when your

watching a video on your phone, your battery will drain very fast,
and your phone might even catch fire.
As such, ESD design engineers have a “ESD design window”.

Never let the ESD circuit trigger when VDD < normal, but always
trigger the ESD circuit before VDD > breakdown of circuit.
A circuit that can sometimes be used, if the ESD design window is

not too small, is the Grounded-Gate-NMOS in the figure below.
V70
y or
on
1 NO PIN
É
or
2
Uss p
O
9.3.1 Why does this work?
2,6A
If you try the circuit above in with the normal BSIM spice model,
it will not work. The transistor model does not include that part of
the physics.
We need to think about how electrons, holes PN-junctions and

bipolars work.
9.3.1.1 Quick refresh of solid-state physics
Electrons sticking to atoms (bound electrons), can only exist at

discrete energy levels. As we bring atoms closer to each-other the
discrete energy levels will split, as computed from Schrodinger,
into bands of allowed energy states. These bands of energy can
have lower energy than the discrete energy levels of the atom.
That’s why some atoms stick together and form molecules through
co-valent bonds, ionic bonds, or whatever the chemists like to call
it. It’s all the same thing, it’s lower energy states that make the
electrons happy, some are strong, some are weak.
For silicon the energy band structure is tricky to compute, so

we simplify to band diagrams that only show the lowest energy
conduction band and highest energy valence band.
Electrons can move freely in the conduction band (until they hit
something, or scatter), and electrons moving in the valence band
act like positive particles, nicknamed holes.
How many free charges there are in a band is given by Fermi-Dirac

distribution and the density of states (allowed energy levels).
If an electron, or a hole have sufficient energy (accelerated by a

field), they can free an electron/hole pair when they scatter off an
atom. If you break too many bonds between atoms, your material
will be damaged.
9.3.1.2 The grounded-gate NMOS
Assume a transistor like the one below. The gate, source and bulk
is connected to ground. The drain is connected to a high voltage.
126 9 IC and ESD
I
ht 30
r
ht
Pto
P
9.3.1.3 Avalanche
The first thing that can happen is that the field in the depletion
zone between drain and bulk (1) is large, due to the high voltage
on drain, and the thin depletion region.
In the substrate (P-) there are mostly holes, but there are also
electrons. If an electron diffuses close to the drain region it will be
swept across to drain by the high field.
The high field might accelerate the electron to such an energy that
it can, when it scatters of the atoms in the depletion zone, knock
out an electron/hole pair.
The hole will go to the substrate (2), while the new electron will
continue towards drain. The new electron can also knock out a
new electron/hole pair (energy level is set by impact ionization of
the atom), so can the old one assuming it accelerates enough.
One electron turn into two, two to four, four to eight and so on.
The number of electrons can quickly become large, and we have an
avalanche condition. Same as a snow avalanche, where everything
was quiet and nice, now suddenly, there is a big trouble.
Usually the avalanche process does not damage anything, at least

initially, but it does increase the hole concentration in the bulk.
The number of holes in the bulk will be the same as the number of
electrons freed in the depletion region.
9.3.1.4 Forward bias of PN-junction
The extra holes underneath the transistor will increase the local
potential. If the substrate contact (5) is far away, then the local
potential close to the source/bulk PN-junction (3) might increase
enough to significantly increase the number of electrons injected
from source.
Some of the electrons will find a hole, and settle down, while others
will diffuse around. If some of the electrons gets close to the drain
region, and the field in the depletion zone, they will be accelerated
by the drain/bulk field, and can further increase the avalanche
condition.
9.3.1.5 Bad things can happen
For a normal transistor, not designed to survive, the electron flow

(4) can cause local damage to the drain. Normally there is nothing
that prevents the current from increasing, and the transistor will
eventually die.
If we add a resistor to the drain region (unscilicided drain), however,

we will slow down the electron flow, and we can get a stable
condition, and design a transistor that survives.
9.3.1.6 What have we done
Turns out, that every single NMOS has a sleeping bear. A parasitic
bipolar. That’s exactly what this GGNMOS is, a bipolar transis-
tor, although a pretty bad one, that is designed to trigger when
avalanche condition sets in and is designed to survive.
A normal NMOS, however, can also trigger, and if you have not
thought about limiting the electron current, it can die, with IC
killing consequences. Specifically, the drain and source will be
shorted by likely the silicide on top of the drain, and instead of a
transistor with high output impedance, we’ll have a drain source
connection with a few kOhm output impedance.
Take a look at New Ballasting Layout Schemes to Improve ESD

Robustness of I/O Buffers in Fully Silicided CMOS Process for the
pretty pictures you’ll get when the drain/source breaks.
9.3.2 How can current in one place lead to a current

somewhere else?
Another fun physics problem can happen in digital logic that is

close to an electron source, like a connection to the real world, what
we call a pad. A pad is where you connect the bond-wire in a QFN
type of package with wire-bonding
Assume we have the circuit below.

128 9 IC and ESD
Mt
lo too
O o
Toome tooma
We can draw a cross section of the inverter.
9.3.2.1 Electron injection
Assume that we have an electron source, for example a pad that

is below ground for a bit. This will inject electrons into the sub-
strate/bulk (1) and electrons will diffuse around.
If some of the electrons comes close to the N-well depletion region

(2) they will be swept across by the built-in field. As a result, the
potential of the N-well will decrease, and we can forward bias the
source or drain junction of a PMOS.
9.3.2.2 Forward biased PMOS source or drain junction
With a forward biased source/bulk junction (2), holes will be

injected into the N-Well, but similarly to the GGNMOS, they might
not find a electron immediately.
Some of the holes can reach the depletion region towards our
NMOS, and be swept across the junction.
9.3.2.3 Forward biased NMOS source or drain junction
The increase in hole concentration underneath the NMOS can

forward bias the PN diode between source (or drain) and bulk.
If this happens, then we get electron injection into bulk. Some
of those electrons can reach the N-well depletion region, and be
swept across (3).
9.3.2.4 Positive-feedback
Now we have a condition where the process accellerates, and

locks-up. Once turned on, this circuit will not turn off until the
supply is low.
This is a phenomena called latch-up. Similar to ESD circuits, latch-

up can short the supply to ground, and make things burn.
That is why, when we have digital logic, we need to be extra careful

close to the connection to the real world. Latch-up is bad.
We can prevent latch-up if we ensure that the electrons that start

the process never reach the N-wells. We can also prevent latch-up
by separating the NMOS and PMOS by guard rings (connections
to ground, or indeed supply), to serve as places where all these
electrons and holes can go.
Maybe it seems like a rare event for latch-up to happen, but trust
me, it’s real, and it can happen in the strangest places. Similar to
ESD, it’s a problem that can kill an IC, and make us pay another X
million dollars for a new tapeout, in addition to the layout work
needed to fix it.
Latch-up is why you will find the design rule check complaining if
you don’t have enough substrate connections to ground, or N-well
connections to power close to your transistors.
Similar to the GGNMOS, this circuit, a thyristor can be a useful

circuit in ESD design. If we can trigger the thyristor when the VDD
shoots to high, then we can create a good ESD protection circuit.
See low-leakage ESD for a few examples.
You must always handle ESD on an IC
▶ Do everything yourself
▶ Use libraries from foundry
▶ Get help www.sofics.com
130 9 IC and ESD
9.4 Want to learn more?
ESD (Electrostatic Discharge) Protection Design for Nanoelectron-

ics in CMOS Technology
Overview on Latch-Up Prevention in CMOS Integrated Circuits

by Circuit Solutions
Overview on ESD Protection Designs of Low-Parasitic Capacitance

for RF ICs in CMOS Technologies
References and bias 10
Keywords: VREf, IREF, VD, BGAP, LVBGAP, VI, GMCELL 10.1 Routing . . . . . . . 131
10.2 Bandgap voltage
In our testbenches, and trial schematics, it’s common to include reference . . . . . . . 133
voltage sources and current sources. However, the ideal voltage 10.2.1 A voltage comple-
source, or ideal current source does not exist in the real world. mentary to tempera-
There is no such thing. ture (CTAT) . . . . . 133
10.2.2 A current propor-
We can come close to creating a voltage source, a known voltage, tional to temperature
with a low source impedance, but not zero impedance. And it (PTAT) . . . . . . . . 135
won’t be infinitely fast either. If we suddenly decide to pull 1 kA 10.2.3 How to combine a
from a lab supply I promise you the voltage will drop. CTAT with a PTAT ? 136
10.2.4 Brokaw reference . . 138
So how do we create something that is a good enough voltage and 10.2.5 Low voltage bandgap 140
current source on an IC? 10.3 Bias . . . . . . . . . . 143
10.3.1 How does a VI con-
verter circuit work? 143
10.3.2 GmCell: Why is
1/Z proportional to
transistor transcon-
ductance? . . . . . . 144
10.1 Routing
Before we take a take a look at the voltage and current source,

I want you to think about how you would route a current, or a
voltage on an IC.
Assume we have a known voltage on our IC. How can we make

sure we can share that voltage across an IC?
A voltage is only defined between two points. There is no such

thing as the voltage at a point on a wire, nor voltage in a node. Yes,
I know we say that, but it’s not right. What we forget is that by
voltage in a node we always, always mean voltage in a node referred to
ground.
We’ve invented this magical place called ground, the final resting
place of all electrons, and we have agreed that all voltages refer to
that point.
As such, when we say “Voltage in node A is 1V”, what we actually

mean is “Voltage in node A is 1 V referred to ground”.
132 10 References and bias
Maybe you now understand why we can’t just route a voltage

across the IC, the other side might not have the same ground.
The other side might have a different impedance to ground, and
the impedance might be a function of time, voltage, frequency
temperature, pressure and presence of gremlins.
Most of the time, in order not to think about the ground impedance,
we choose to route a known quantity as a current instead of a
voltage. That means, however, we must convert from a voltage to a
current, but we can do that with a resistor (you’ll see later), and
as long as the resistor is the same on the other side of the IC, then
we’ll know what the voltage is.
Resistors have finite matching across die, let’s say 2 % 3-sigma

variation. As a result, if we need a accurate voltage reference, then
we must distribute voltage.
But how can “It’s better to distribute a voltage as a current across

the IC, it’s more accurate” and “If you need something really
accurate, you must distribute voltage” both be true?
10.2 Bandgap voltage reference 133
Imagine I have a 0.5 % 3-sigma accurate voltage reference at 1.22 V,

that’s a sigma of 2 mV. I need this reference voltage on a block on
the other side of the IC, I don’t want to distribute voltage, because
I don’t know that the ground is the same on the other side, at least
not to a precision of 2 mV. I convert the voltage into a current,
however, I know the R has a 2 % 3-sigma across die, so my error
budget immediately increases to 2.06%.
But what if I must have 0.5 % 3-sigma voltage in the block? For
example in a battery charger, where the 4.3 V termination voltage
must be 1 % accurate? I have no choice but to go with voltage
directly from the reference, but the key point, is then the receiving
block cannot be on the other side of the IC. The reference must be
right next to my block.
I could use two references on my IC, one for the ADC and one
for the battery charger. Ask yourself, “Why do we care if there is
two references?” And the answer is “Silicon area is expensive, to
make things cheep, we must make things small”, in other words,
we should not duplicate features unless we absolutely have to.
10.2 Bandgap voltage reference
10.2.1 A voltage complementary to temperature (CTAT)
A diode connected bipolar transistor, or indeed a PN diode, assum-

ing a fixed current, will have a voltage across that is temperature
dependent
𝑉𝐵𝐸
𝑉𝐵𝐸
𝐼 𝐷 = 𝐼𝑆 𝑒 𝑉𝑇
− 1 + 𝐼 𝐵 ≈ 𝐼𝑆 𝑒 𝑉𝑇
As 𝐼𝑆 is much smaller that 𝐼𝐷 we can ignore the -1, and we assume

that the base current is much smaller than the drain current.
Re-arranging for 𝑉𝐵𝐸 and inserting for
𝑘𝑇
𝑉𝑇 =
𝑞
𝑘𝑇 𝐼𝐶
𝑉𝐵𝐸 = ln
𝑞 𝐼𝑆
𝐷𝑛 𝐷𝑝

𝐼𝑆 = 𝑞𝐴𝑛 𝑖2 +
From this equation, it looks like the voltage 𝑉𝐵𝐸 is proportional to

temperature
However, it turns out that the 𝑉𝐵𝐸 decreases with temperature due
to the temperature dependence of 𝐼𝑆 .
The 𝑉𝐵𝐸 is linear with temperature with a property that if you

extrapolate the 𝑉𝐵𝐸 line to zero Kelvin, then all diode voltages
seem to meet at the bandgap voltage of silicon (approx 1.12 eV).
To see the temperature coefficient, I find it easier to re-arrange the

equation above.
Some algebra (see Diodes)
𝑘𝑇
𝑉𝐵𝐸 = (ℓ − 3 ln 𝑇) + 𝑉𝐺
𝑞
The ℓ is a temperature independent constant given by
𝐷𝑛 𝐷𝑝 2𝜋𝑘

3 3
ℓ = ln 𝐼𝐶 −ln 𝑞𝐴−ln + −2 ln 2− ln 𝑚𝑛∗ − ln 𝑚 𝑝∗ −3 ln 2
𝐿 𝑛 𝑁𝐴 𝐿 𝑝 𝑁𝐷 2 2 ℎ
And if we plot the diode voltage, we can see that the voltage
decreases as a function of temperature.
0.95
Diode voltage [V]
0.90
0.85
25 0 25 50 75 100 125
Non-linear component (mV)
2
25 0 25 50 75 100 125
Temperature [C]
10.2.2 A current proportional to temperature (PTAT)
If we take two diodes, or bipolars, biased at different current

densities, as shown in the figure below, then
𝐼𝐷
𝑉𝐷 1 = 𝑉𝑇 ln
𝐼𝑆1
𝐼𝐷
𝑉𝐷 2 = 𝑉𝑇 ln
𝐼𝑆2
The OTA will force the voltage on top of the resistor to be equal to
𝑉𝐷 1 , thus the voltage across the resistor 𝑅 1 is
𝐼𝐷 𝐼𝐷 𝐼𝑆2
𝑉𝐷 1 − 𝑉𝐷 2 = 𝑉𝑇 ln − 𝑉𝑇 ln = 𝑉𝑇 ln = 𝑉𝑇 ln 𝑁
𝐼𝑆1 𝐼𝑆2 𝐼𝑆1
This is a remarkable result. The difference between two voltages is

only defined by boltzmann’s constant, temperature, charge, and a
know size difference.
This differential voltage can be used to read out directly the

temperature on an IC, provided we have a known voltage to
compare with.
We often call this voltage Δ𝑉𝐷 or Δ𝑉𝐵𝐸 , and we can clearly see it’s
proportional to absolute temperature.
We know that the 𝑉𝐷 decreases linearly with temperature, so if we

combined a multi-plum of the Δ𝑉𝐵𝐸 with a 𝑉𝐷 voltage, then we
should get a constant voltage.
ID
a verb in
R1
V02
I N 1 N
D1 D2 D
VREE
R2
10.2.3 How to R2a PTAT ?
combine a CTAT with
Vn
R1
V02
I N
One method is the figure below. The voltage across resistor 𝑅 2
would compensate for the decrease in 𝑉𝐷 3 , as such, 𝑅 2 would be
bigger than 𝑅 1 . D1 D2
VREE
rb in
1 R ID RL
2 V02 V02
1 Na verb in
D Dz 03
R1 R R
V02 V02 V0
I N 1 N
D1 D2
Another method would be to stack the 𝑅 2 on top of 𝑅 1 as shown D Dz 0
below.
VREE
VREE
R2 R2
Vn
R1
V02
I N
D1 D2
10.2.4 Brokaw reference
Paul Brokaw was a pioneer within reference circuits. Below is the

Brokaw reference, which I think was first published in A simple
three-terminal IC bandgap reference.
I 1 D
Rz Ry
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Q Q2
In
8
use
Ere
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N
The opamp ensures the two bipolars have the same current. 𝑄 1 is
larger than 𝑄 2 . The Δ𝑉𝐵𝐸 is across the 𝑅 2 , so we know the current
𝐼 . We know that 𝑅1 must then have 2𝐼 .
The voltage at the output will then be.
𝑘𝑇 𝑇0 𝑘 𝐽2 2𝑅 2 𝑉𝐺0 − 𝑉𝑏𝑒 0

𝑉𝐵𝐺 = 𝑉𝐺0 + (𝑚 − 1) ln +𝑇 ln −
𝑞 𝑇 𝑞 𝐽1 𝑅 1 𝑇0
to do I
where 𝑉𝐺0 is the bandgap, 𝑉𝑏𝑒 0 is the base emitter measured at a
temperature 𝑇0 and the 𝐽 ’s are the current densities.
To get a constant output voltage, the relationship between the

resistors should be approximately
𝑅2 𝑉𝐺0 − 𝑉𝑏𝑒 0
=
𝑅1 2𝑇0 𝑘 ln( 𝐽2 )
𝑞 𝐽1
In typical simulations, the variation can be low over the temperature

range. The second order error is the remaining error from
𝑘𝑇 𝑇0 𝑘 𝐽2 2𝑅2 𝑉𝐺0 − 𝑉𝑏𝑒 0

𝑉𝐵𝐺 = 𝑉𝐺0 + (𝑚 − 1) ln +𝑇 ln −
𝑞 𝑇 𝑞 𝐽1 𝑅 1 𝑇0
Where the last term is zero, so
𝑘𝑇 𝑇0
𝑉𝐵𝐺 = 𝑉𝐺0 + (𝑚 − 1) ln
𝑞 𝑇
Over corners, I do expect that there is variation. It may be that the

𝑉𝐷 modeling is not perfect, which means the cancellation of the
last term is incomplete.
We could include trimming of PTAT to calibrate for the remaining

error, however, if we wanted to remove the linear gradient, we
would need a two point temperature test of every IC, which too
expensive for low-cost devices.
10.2.5 Low voltage bandgap
The Brokaw reference, and others, have a 1.2 V output voltage,

which is hard if your supply is below about 1.4 V. As such, people
have investigated lower voltage references. The original circuit
was presented by Banba A CMOS bandgap reference circuit with
sub-1-V operation
In real ICs though, you should ask yourself long and hard whether
you really need these low-voltage references. Most ICs today still
have a high voltage, either 1.8 V or 3.0 V.
If you do need them though, consider the circuit below. We have

two diodes at different current densities. The Δ𝑉𝐷 will be across
𝑅 1 . The voltage at the input of the OTA will be 𝑉𝐷 and the OTA
will ensure the both are equal.
The current will then be
Δ𝑉𝐷
𝐼1 =
𝑅1
and we know the current increases with temperature, since Δ𝑉𝐷

increases with temperature.
TN
In the figure below I’ve used Δ𝑉𝐵𝐸 , it’s the same as Δ𝑉𝐷 , so ignore
that error.
Assume we copy the 𝑉𝐷 to another node, and place it across a

second resistor 𝑅 2 , as shown in the figure below. The current in
this second resistor is then
𝑉𝐷
𝐼2 =
𝑅2
and we know the current decreases with temperature, since 𝑉𝐷

decreases with temperature.
From before, we know the current in 𝑅 1 is proportional to temper-

ature. As such, if we combine the two with the correct proportions,
then we can get a current that does not change with temperature.
I WE
R
R2
9N
Let’s remove the OTA, and connect 𝑅 2 directly to 𝑉𝐷 nodes, you

should convince yourself of the fact that this does not change 𝐼1 at
all.
Ra in
ti NE R
Iz
13g
It does, however, change the current in the PMOS. Provided we scale

𝑅 2 correctly, then the PTAT 𝐼1 can be compensated by the CTAT 𝐼2 ,
and we have a current that is independent of temperature.
10.3 Bias 143
𝑉𝐷 Δ𝑉𝐷
𝐼𝑃𝑀𝑂𝑆 = +
𝑅2 𝑅1
Assuming we copy the current into another resistor 𝑅 3 , as shown

below, we can get a voltage that is
𝑉𝐷 Δ𝑉𝐷

𝑉𝑂𝑈𝑇 = 𝑅3 +
𝑅2 𝑅1
Where the output voltage can be chosen freely, and indeed be lower
than 1.2 V.
p p
ti MI p
12 152
Rz
10.3 Bias
Sometimes we just need a current
10.3.1 How does a VI converter circuit work?

BE
With a known voltage, we can convert to a known current with the
circuit below.
On-chip we don’t have accurate resistors, but for bias currents, it’s
usually ok with + − 20 variation (the variation of R).
Across a IC, we can expect the resistors to match within a few

percent, as such, we can recreate a voltage with a accuracy of a few
percent difference from the original if we have a second resistor on
the other side of the IC.
If we wanted to create an accurate current, then we’d trim the R

until the current is what we want.
IRV
R
10.3.2 GmCell: Why is 1/Z proportional to transistor

transconductance?
Ib ImmbxEMVet
lil Vett
ITEM
j vett Mf V
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1 1
Velt 2V
Vo Veltz
KI
F Vo ZI
Vet
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Z
Its
y
Sometimes we don’t need a full bandgap reference. In those cases,
we can use a GM cell, where the impedance could be a resistor, in
which case
Vo Vo
𝑉𝑜 = 𝑉𝐺𝑆1 − 𝑉𝐺𝑆2 = 𝑉𝑒 𝑓 𝑓 1 + Z gu ta
𝑉𝑡𝑛 − 𝑉𝑒 𝑓 𝑓 2 − 𝑉𝑡𝑛 = 𝑉𝑒 𝑓 𝑓 1 − 𝑉𝑒 𝑓 𝑓 2
10.3 Bias 145
Assuming strong inversion, then
1 𝑊1 2
𝐼𝐷 1 = 𝜇𝑛 𝐶 𝑜𝑥 𝑉
2 𝐿1 𝑒 𝑓 𝑓 1
1 𝑊1
𝐼𝐷 2 = 𝜇𝑛 𝐶 𝑜𝑥 4 𝑉𝑒2𝑓 𝑓 2
2 𝐿1
𝐼𝐷 1 = 𝐼𝐷 2
1 𝑊1 2 1 𝑊1
𝜇𝑛 𝐶 𝑜𝑥 𝑉𝑒 𝑓 𝑓 1 = 𝜇𝑛 𝐶 𝑜𝑥 4 𝑉𝑒2𝑓 𝑓 2
2 𝐿1 2 𝐿1
𝑉𝑒 𝑓 𝑓 1 = 2𝑉𝑒 𝑓 𝑓 2
Inserted into above
1 1
𝑉𝑜 = 𝑉𝑒 𝑓 𝑓 1 − 𝑉𝑒 𝑓 𝑓 1 = 𝑉𝑒 𝑓 𝑓 1
2 2
Still assuming strong inversion, such that
2𝐼 𝑑
𝑔𝑚 =
𝑉𝑒 𝑓 𝑓
we find that
𝑉𝑒 𝑓 𝑓 1
𝐼=
2𝑍
1
𝑍⇒
𝑔𝑚
If we use a resistor for Z, then we can get a transconductance that

is proportional to a resistor, or a constant 𝑔𝑚 bias.
We can use other things for Z, like a switched capacitor

Vo
Vo
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air
C E
V I R Qc Vo C
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A simple three-terminal IC bandgap reference
A CMOS bandgap reference circuit with sub-1-V operation

E
I
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A sub-1-V 15-ppm//spl deg/C CMOS bandgap voltage reference
without requiring low threshold voltage device
The Bandgap Reference rn

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The Design of a Low-Voltage Bandgap Reference
Analog frontend and filters 11
Keywords: H(s), BiQuad, Gm-C, Active-RC, OTA 11.1 Introduction . . . . . 147
11.2 Filters . . . . . . . . . 149
11.2.1 First order filter . . . 150
11.2.2 Second order filter . 151
11.1 Introduction 11.2.3 How do we im-
plement the filter
The world is analog, and these days, we do most signal processing sections? . . . . . . . 152
in the digital domain. With digital signal processing we can reuse 11.3 Gm-C . . . . . . . . . 152
the work of others, buy finished IPs, and probably do processing 11.3.1 Differential Gm-C . . 153
11.3.2 Finding a transcon-
at lower cost than for analog.
ductor . . . . . . . . . 155
Analog signals, however, might not be suitable for conversion to 11.4 Active-RC . . . . . . 156
digital. A sensor might have a high, or low impedance, and have 11.4.1 General purpose first
the signal in the voltage, current, charge or other domain. order filter . . . . . . 156
11.4.2 General purpose
To translate the sensor signal into something that can be converted biquad . . . . . . . . 159
to digital we use analog front-ends (AFE). How the AFE looks 11.5 The OTA is not ideal 160
will depend on application, but it’s common to have amplification, 11.6 Example circuit . . . 160
frequency selectivity or domain transfer, for example current to 11.7 My favorite OTA . . 161
voltage. 11.8 Want to learn more? 164
An ADC will have a sample rate, and will alias (or fold) any signal
Why
above half the sample rate, as such, we also must include a anti-
alias filter in AFE that reduces any signal outside the bandwidth
of the ADC as close to zero as we need.
Sensor AFE Abc

Amplification
Frequency selectivity
discrete time?
Discrete value
Bits
(Quantization)
Domain transfer
One example of an analog frontend is the recieve chain of a typical

bluetooth radio. The signal that arrives at the antenna, or the
“sensor”,
Sensor AFE
can Abc-90 dBm.
be weak, maybe
At the same time, at another frequency, there could be a unwanted

signal, or blocker, of -30 dBm
Assume for the moment we actually used an ADC at the antenna,

how many bits would we need?
Bluetooth uses Gaussian Frequency Shift Keying, which is a con-

stant envelope binary modulation, and it’s ususally sufficient with
Sensor RFE AFE ADC

148 11 Analog frontend and filters
low number of bits, assume 8-bits for the signal is more than
enough.
If we assume the maximum of the ADC should be the blocker in

the table below, and the resolution of the digital should be given
by
What Power [dBm] Voltage [V]

Blocker -30 7m
Wanted -90 7u
Resolution Wanted/255 = 28 n
Then we can calculate the number of bits as
7 mV
ADC resolution ⇒ ln /ln 2 ≈ 18 bits
28 nV
If we were to sample at 5 GHz, to ensure the bandwidth is sufficient

for a 2.480 GHz maximum frequency we can actually compute the
power consumption.
Given the Walden figure of merit of
𝑃
𝐹𝑂 𝑀 =
2𝐸𝑁 𝑂𝐵 𝑓 𝑠
The best FOM in literature is about 1 fJ/step, so
𝑃 = 1 fJ/step × 218 × 5GHz = 1.31 W
If we look at a typical system, like the Whoop. We can have a look

at teardowns, to find the battery size.
Whoop battery is 205mAh at 3.8 V
Then we can compute the lifetime running an ADC based Bluetooth

Radio
205 mAh
Hours = = 0.6 h
1.32 W/3.8 V
I know my whoop lasts for almost a week, so it can’t be what

Bluetooth ICs do.
I know a little bit about radio’s, especially inside the Whoop, since
it has
Nordic Inside
Amplification
Frequency selectivity
discrete time?
Discrete value
Bits
(Quantization)
Domain transfer 11.2 Filters 149
I can’t tell you how the Nordic radio works, but I can tell you
how others usually make their radio’s. The typical radio below has
multiple blocks in the AFE.
Sensor AFE Abc
First is low-noise amplifier (LNA) amplifying the signal by maybe

10 times. The LNA reduces the noise impact of the following blocks.
The next is the complex mixer stage, which shifts the input signal
from radio frequency down to a low frequency, but higher than the
AFErejects ADC
bandwidth of the wanted signal. Then there is a complex anti-alias
Sensor
filter, also called RFE filter, which
a poly-phase parts of the
unwanted signals. Lastly there is a complex ADC to convert to
digital.
In digital we can further filter to select exactly the wanted signal.

Digital filters can have high stop band attenuation at a low power
and cost. There could also be digital mixers to further reduce the
frequency.
The AFE makes the system more efficient. In the 5 GHz ADC
output, from the example above, there’s lot’s of information that
we don’t use.
An AFE can reduce the system power consumption by constraining

digital information processing and conversion to the parts of the
spectrum with information of interest.
There are instances, though, where the full 2.5 GHz bandwidth has
useful information. Imagine in a cellular base station that should
process multiple cell-phones at the same time. In that case, it could
make sense with an ADC at the antenna.
What make sense depends on the application.
11.2 Filters
A filter can be fully described by the transfer function, usually

output
denoted by 𝐻(𝑠) = input .
Most people will today start design with a high-level simulation,

in for example Matlab, or Python. Once they know roughly the
transfer function, they will implement the actual analog circuit.
For us, as analog designers, the question becomes “given an 𝐻(𝑠),

how do we make an analog circuit?” It can be shown that a
combination of 1’st and 2’nd order stages can synthesize any order
filter.
Once we have the first and second order stages, we can start looking
into circuits.
11.2.1 First order filter
In the book they use signal flow graphs to show how the first
order stage can be generated. By selecting the coefficients 𝑘 0 , 𝑘 1
and 𝜔0 we can get any first order filter, and thus match the 𝐻(𝑠)
we want.
I would encourage you to try and derive from the signal flow graph
the 𝐻(𝑠) and prove to your self the equation is correct.
Vi Ys Vo
order
Signal flow graphs are useful when dealing with linear systems.
Second The instructions to compute the transfer functions are
1. any line with a coefficient is a multiplier

2. any box output is a multiplication of the coefficient and theMÉE
input
3. any sum, well, sum all inputs
a 4. be aware of gremlins (a sudden -+ swap)

11.2 Filters 151
𝑉𝑜 (𝑠) 𝑘 1 𝑠 + 𝑘 0
𝐻(𝑠) = =
𝑉𝑖 (𝑠) 𝑠 + 𝑤𝑜
Let’s call the 1/𝑠 box input 𝑢 Wo
Vi ko V0
𝑢 = (𝑘 0 + 𝑘 1 𝑠)𝑉𝑖 − 𝜔0𝑉𝑜
Ks
𝑉𝑜 = 𝑢/𝑠
𝑢 = 𝑉𝑜 𝑠 = (𝑘 0 + 𝑘1 𝑠)𝑉𝑖 − 𝜔0𝑉𝑜
Second order
(𝑠 + 𝜔0 )𝑉𝑜 = (𝑘 0 + 𝑘 1 𝑠)𝑉𝑖
𝑉𝑜 𝑘1 𝑠 + 𝑘0
=
𝑉𝑖 𝑠 + 𝜔0
11.2.2 Second order filter
V25
Bi-quadratic is a general purpose second order filter.
Bi-quadratic just means “there are two quadratic equations”. Once

we match the 𝑘 ’s 𝜔0 and 𝑄 to our wanted 𝐻(𝑠) we can proceed
with the circuit implementation.
Wo
Wo Q
Vi kowo wo
V0
has
𝑘2 𝑠 2 + 𝑘1 𝑠 + 𝑘0
𝐻(𝑠) =
𝑠 2 + 𝜔𝑄0 𝑠 + 𝜔2𝑜
Follow exactly the same principles as for first order signal flow
graph. If you fail, and you can’t find the problem with your algebra,
then maybe you need to use Maple or Mathcad.
I guess you could also spend hours training on examples to get

better at the algebra. Personally I find such tasks mind numbingly
boring, and of little value. What’s important is to remember that
you can always look up the equation for a bi-quad in a book.
11.2.3 How do we implement the filter sections?
While I’m sure you can invent new types of filters, and there
probably are advanced filters, I would say there is roughly three
types. Passive filters, that do not have gain. Active-RC filters, with
OTAs, and usually trivial to make linear. And Gm-C filters, where
we use the transconductance of a transistor and a capacitor to
set the coefficients. Gm-C are usually more power efficient than
Active-RC, but they are also more difficult to make linear.
In many AFEs, or indeed Sigma-Delta modulator loop filters, it’s

common to find a first Active-RC stage, and then Gm-C for later
stages.
11.3 Gm-C
In the figure below you can see a typical Gm-C filter and the
equations for the transfer function. One important thing to note
is that this is Gm with capital G, not the 𝑔𝑚 that we use for small
signal analysis.
Gnc
In a Gm-C filter the input and output nodes can have significant
swing, and thus cannot always be considered small signal.
to
Io
Vi Gm Vo Vo
c
Wti
𝐼𝑜 𝜔𝑡𝑖
𝑉𝑜 = = 𝑉𝑖
𝑠𝐶 𝑠
𝜔𝑡𝑖 =Io𝐺𝐶𝑚
V
Vi am
I
Vi Gm IE WE
11.3 Gm-C 153
11.3.1 Differential Gm-C

wei
of
In a real IC we would almost always use differential circuit, as
shown below. The transfer function is luckily the same.
gmVi
V
Vit ut
Gm
I
am
I c
to Gulf
grivi guv
Vo Vo
I
IE
e
𝑠𝐶𝑉𝑜 = 𝐺 𝑚 𝑉 𝑖
𝑉𝑜 𝐺𝑚
WEVi
𝐻(𝑠) = = 2
𝑉𝑖 𝑠𝐶
wei
of Crease
Differential circuits are fantastic for multiple reasons, power supply
rejection ratio, noise immunity, symmetric non-linearity, but the
qualities I like the most is that the outputs can be flipped to
Use 3D cap
figure
implement negative, or positive gain.
i
V
ut
I
am
I c
guv
𝑉𝑜 𝐺𝑚
𝐻(𝑠) = =−
𝑉𝑖 𝑠𝐶
The figure below shows a implementation of a first-order Gm-C

filter that matches our signal flow graph.
rease Use 3D cap

I would encourage you to try and calculate the transfer function.
figure
ex
Ganz
is
Vi s iz
Gm
i t Vols
do
do
i
is
iz
Gy
Given the transfer function from the signal flow graph, we see that
G
we can select 𝐶 𝑥 , 𝐶 𝑎 and 𝐺 𝑚 to get the desired 𝑘 ’s and 𝜔0Gs
or
Ca
GL CB
𝑘1 𝑠 + 𝑘0
Vi G 𝐻(𝑠) =
𝑠 + 𝑤𝑜
63
Vo
𝑠 𝐶 𝑎𝐶+𝐶
𝑥
𝑥
+ 𝐺𝑚1
𝐶 𝑎 +𝐶 𝑥
𝐻(𝑠) = 𝐺𝑚2
𝑠+ 𝐶 𝑎 +𝐶 𝑥
Below is a general purpose Gm-C bi-quadratic system.
Gmt Gul Gms Vout

ca c
20
Guy Gms
Vin
20
𝑘2 𝑠 2 + 𝑘1 𝑠 + 𝑘0
𝐻(𝑠) =
𝑠 2 + 𝜔𝑄0 𝑠 + 𝜔2𝑜
11.3 Gm-C 155
𝑠 2 𝐶𝑋𝐶+𝐶
𝑋
𝐵
+ 𝑠 𝐶𝑋𝐺+𝐶
𝑚5
𝐵
+ 𝐺𝑚2 𝐺𝑚4
𝐶 𝐴 (𝐶 𝑋 +𝐶 𝐵 )
𝐻(𝑠) =
𝑠 2 + 𝑠 𝐶𝑋𝐺+𝐶
𝑚2
𝐵
11.3.2 Finding a transconductor
Although you can start with the Gm-C cells in the book, I would
actually choose to look at a few papers first.
The main reason is that any book is many years old. Ideas turn
into papers, papers turn into books, and by the time you read the
book, then there might be more optimal circuits for the technology
you work in.
If I were to do a design in 22 nm FDSOI I would first see if someone

has already done that, and take a look at the strategy they used. If
I can’t find any in 22 nm FDSOI, then I’d find a technology close to
the same supply voltage.
Start with IEEEXplore
I could not find a 22 nm FDSOI Gm-C based circuit on the initial

search. If I was to actually make a Gm-C circuit for industry I
would probably spend a bit more time to see if any have done it,
maybe expanding to other journals or conferences.
I know of Pieter Harpe, and his work is usually superb, so I

would take a closer look at A 77.3-dB SNDR 62.5-kHz Bandwidth
Continuous-Time Noise-Shaping SAR ADC With Duty-Cycled
Gm-C Integrator
And from Figure 10 a) we can see it’s a similar Gm-C cell as chapter
12.5.4 in CJM.
One of my Ph.d’s used the transonductor below on his master

thesis Design Considerations for a Low-Power Control-Bounded
A/D Converter.
inherent linearity and the state boundary bx .
The schematic for the transconductor considered in this thesis is given in
156 11 Analog frontendfigure 5.16. Spectre netlist and some additional design details are given
and filters
in appendix F and a summary of some key performance metrics is listed
in table 5.3.
Vdd
Vcmf b
M3a M3b
io Vdd Vdd i+
o
M2a M2b
vi+ M1a M1b vi
Vbn Mbn1
Vss
Figure 5.16: Transconductor schematic
The transconductor comprises a single di↵erential pair (M1 ) with an ac-

tive load (M3 ). The cascode/common-gate transistors, M2 , are included
to limit11.4
the Active-RC
Miller-e↵ect on the gate-drain capacitor Cgd1 of the input
transistors. The transconductor achieves a DC-gain of about 150. In
the absence of M2 , Cfilter
The Active-RC gd1 would
shouldhave been
be well boosted
know at thisfrom
point.about 200aF to
However,
more than
what20fF,
mightthereby
be newbecoming
is that the aopen
dominating
loop gaincapacitor at the
𝐴0 and unity floating
gain
gate node.
𝜔𝑡 𝑎 The DC-gain, and thereby the gate-drain capacitance, follow
72
11.4.1 General purpose first order filter
Below is a general purpose first order filter and the transfer function.
I’ve used the condutance 𝐺 = 𝑅1 instead of the resistance. The
reason is that it sometimes makes the equations easier to work
out.
If you’re stuck on calculating a transfer function, then try and

switch to conductance, and see if it resolves.
I often get my mind mixed up when calculating transfer functions.

I don’t know if it’s only me, but if it’s you also, then don’t worry,
it’s not that often you have to work out transfer functions.
Once in a while, however, you will have a problem where you must
calculate the transfer function. Sometimes it’s because you’ll need
to understand where the poles/zeros are in a circuit, or you’re
trying to come up with a clever idea, or I decide to give this exact
problem on the exam.
11.4 Active-RC 157
Ga
Ven Ci Cr
Vout
G
𝑘1 𝑠 + 𝑘0
𝐻(𝑠) =
𝑠 + 𝑤𝑜
− 𝐶𝐶12 𝑠 − 𝐺1
𝐶2
𝐻(𝑠) = 𝐺2
𝑠+ 𝐶2
Let’s work through the calculation.
VI
11.4.1.1 Step 1: Simplify Vo
The conductance from 𝑉𝑖𝑛 to virtual ground can be written as
𝐺 𝑖𝑛 = 𝐺1 + 𝑠𝐶1
The feedback conductance, between 𝑉𝑜𝑢𝑡 and virtual ground I

write as
𝐺 𝑓 𝑏 = 𝐺2 + 𝑠𝐶2
11.4.1.2 Step 2: Remember how an OTA works
An ideal OTA will force its inputs to be the same. As a result, the
potential at OTA− input must be 0.
The input current must then be
𝐼 𝑖𝑛 = 𝐺 𝑖𝑛 𝑉𝑖𝑛
Here it’s important to remember that there is no way for the input
current to enter the OTA. The OTA is high impedance. The input
current must escape through the output conductance 𝐺 𝑓 𝑏 .
What actually happens is that the OTA will change the output
voltage 𝑉𝑜𝑢𝑡 until the feedback current , 𝐼 𝑓 𝑏 , exactly matches 𝐼 𝑖𝑛 .
That’s the only way to maintain the virtual ground at 0 V. If

the currents do not match, the voltage at virtual ground cannot
continue to be 0 V, the voltage must change.
11.4.1.3 Step 3: Rant a bit
The previous paragraph should trigger your spidy sense. Words

like “exactly matches” don’t exist in the real world. As such, how
closely the currents match must affect the transfer function. The
open loop gain 𝐴0 of the OTA matters. How fast the OTA can
react to a change in voltage on the virtual ground, approximated
by the unity-gain frequency 𝜔𝑡 𝑎 (the frequency where the gain of
the OTA equals 1, or 0 dB), matters. The input impedance of the
OTA, whether the gate leakage of the input differential pair due
to quantum tunneling, or the capacitance of the input differential
pair, matters. How much current the OTA can deliver (set by slew
rate), matters.
Active-RC filter design is “How do I design my OTA so it’s good

enough for the filter”. That’s also why, for integrated circuits, you
will not have a library of OTAs that you just plug in, and they
work.
I would be very suspicious of working anywhere that had an OTA

library I was supposed to use for integrated filter design. I’m not
saying it’s impossible that some company actually has an OTA
library, but I think it’s a bad strategy. First of all, if an OTA is generic
enough to be used “everywhere”, then the OTA is likely using too
much power, consumes too much area, and is too complex. And
the company runs the risk that the designer have not really checked
that the OTA works porperly in the filter because “Someone else
designed the OTA, I just used in my design”.
But, for now, to make our lifes simpler, we assume the OTA is ideal.
That makes the equations pretty, and we know what we should
get if the OTA actually was ideal.
11.4.1.4 Step 4: Do the algebra
The current flowing from 𝑉𝑜𝑢𝑡 to virtual ground is
𝐼 𝑜𝑢𝑡 = 𝐺 𝑓 𝑏 𝑉𝑜𝑢𝑡
The sum of currents into the virtual ground must be zero
𝐼 𝑖𝑛 + 𝐼 𝑜𝑢𝑡 = 0
11.4 Active-RC 159
Insert, and do the algebra
𝐺 𝑖𝑛 𝑉𝑖𝑛 + 𝐺 𝑜𝑢𝑡 𝑉𝑜𝑢𝑡 = 0
⇒ −𝐺 𝑖𝑛 𝑉𝑖𝑛 = 𝐺 𝑜𝑢𝑡 𝑉𝑜𝑢𝑡
𝑉𝑜𝑢𝑡 𝐺 𝑖𝑛
=−
𝑉𝑖𝑛 𝐺 𝑜𝑢𝑡
𝐺1 + 𝑠𝐶1
=−
𝐺2 + 𝑠𝐶2
−𝑠 𝐶𝐶21 − 𝐺1
𝐶2
= 𝐺2
𝑠+ 𝐶2
11.4.2 General purpose biquad
A general bi-quadratic active-RC filter is shown below. These kind

of general purpose filter sections are quite useful.
Imagine you wanted to make a filter, any filter. You’d decompose

into first and second order sections, and then you’d try and match
the transfer functions to the general equations.
Gy
G Gs
or
Ca
L
CB
Vi G
63
Vo
𝑘2 𝑠 2 + 𝑘1 𝑠 + 𝑘0
𝐻(𝑠) =
𝑠 2 + 𝜔𝑄0 𝑠 + 𝜔2𝑜
h i
𝐶1 2
𝐶𝐵 𝑠 + 𝐺2
𝐶𝐵 𝑠 + ( 𝐶𝐺𝐴1 𝐺𝐶𝐵3 )
𝐻(𝑠) = h i
𝐺5 𝐺3 𝐺4
𝑠2 + 𝐶𝐵 𝑠 + 𝐶𝐴 𝐶𝐵
11.5 The OTA is not ideal
VI
Vo
𝐴0
𝐻(𝑠) ≈ 𝑠
(1 + 𝑠𝐴 𝑜 𝑅𝐶)(1 + 𝑤 𝑡𝑎 )
where
𝐴0
is the gain of the amplifier, and
𝜔𝑡 𝑎
is the unity-gain frequency.
At frequencies above 𝐴01𝑅𝐶 and below 𝑤 𝑡 𝑎 the circuit above is a

good approximation of an ideal integrator.
See page 511 in CJM (chapter 5.8.1)
11.6 Example circuit
One place where both active-RC and Gm-C filters find a home are
continuous time sigma-delta modulators. More on SD later, for now,
just know that SD us a combination of high-gain, filtering, simple
ADCs and simple DACs to make high resolution analog-to-digital
converters.
One such an example is
A 56 mW Continuous-Time Quadrature Cascaded Sigma-Delta

Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band
Below we see the actual circuit. It may look complex, and it is.
Not just “complex” as in complicated circuit, it’s also “complex”

as in “complex numbers”.
11.7 My favorite OTA 161
We can see there are two paths “i” and “q”, for “in-phase” and
“quadrature-phase”. The fantasitc thing about complex ADCs is
that we can have a-symmetric frequency response around 0 Hz.
It will be tricky understanding circuits like this in the beginning,

but know that it is possible, and it does get easier to understand.
With a complex ADC like this, the first thing to understand is the
rough structure.
There are two paths, each path contains 2 ADCs connected in series
(Multi-stage Noise-Shaping or MASH). Understanding everything
at once does not make sence.
Start with “Vpi” and “Vmi”, make it into a single path (set Rfb1
and Rfb2 to infinite), ignore what happens after R3 and DAC2i.
Now we have a continuous time sigma delta with two stages. First
stage is a integrator (R1 and C1), and second stage is a filter (Cff1,
R2 and C2). The amplified and filtered signal is sampled by the
ADC1i and fed back to the input DAC1i.
It’s possible to show that if the gain from 𝑉(𝑉 𝑝𝑖, 𝑉 𝑝𝑚) to ADC1i
input is large, then 𝑌 1 𝑖 = 𝑉(𝑉 𝑝𝑖, 𝑉 𝑝𝑚) at low frequencies.
11.7 My favorite OTA
Over the years I’ve developed a love for the current mirror OTA. A
single stage, with load compensation, and an adaptable range of
DC gains.
Sometimes simple current mirrors are sufficient, sometimes cas-

coded, or even active cascodes are necessary.
Below is the differential current mirror OTA.
1 1
Von Vop
Vin Vip
In a differential OTA we need to control the output common mode.

In order to control the common mode, we must sense the common
mode.
Below is a circuit I often use to sense the common mode. Ideally

the source followers would be nativeVontransistors, but those areVop
not
always available.
VCREF
The reference for the common mode can be from a bandgap, or in
the case below, VDD/2. VCOUT
11.7 My favorite OTA 163
Von Vop
VCREF
VCOUT
Once we have both the sensed common mode, and the common
mode reference, we can use another OTA to control the common
mode.
The nice thing about the circuit below is that the common mode
feedback loop has the same dominant pole as the differential
loop.
Von Vop
VCOUT VCREF
You can find the schematic for the OTA at
CNR_OTA_SKY130NM
A 77.3-dB SNDR 62.5-kHz Bandwidth Continuous-Time Noise-

Shaping SAR ADC With Duty-Cycled Gm-C Integrator
Design Considerations for a Low-Power Control-Bounded A/D

Converter

Switched-Capacitor Circuits 12
Keywords: SC DAC, SC FUND, DT, Alias, Subsample, Z Do- 12.1 Active-RC . . . . . . 165
main, FIR, IIR, SC MDAC, SC INT, Switch, Non-Overlap, VBE 12.2 Gm-C . . . . . . . . . 167
SC, Nyquist 12.3 Switched capacitor 167
12.3.1 An example SC
circuit . . . . . . . . . 170
12.1 Active-RC 12.4 Discrete-Time Sig-
nals . . . . . . . . . . 172
12.4.1 The mathematics . . 173
A general purpose Active-RC bi-quadratic (two-quadratic equa- 12.4.2 Python discrete time
tions) filter is shown below example . . . . . . . 174
12.4.3 Aliasing, bandwidth
and sample rate
Gy theory . . . . . . . . 176
G Gs
12.4.4 Z-transform . . . . . 178
12.4.5 Pole-Zero plots . . . 179
or
Ca 12.4.6 Z-domain . . . . . . 179
L
CB 12.4.7 First order filter . . . 180
12.4.8 Finite-impulse re-
Vi G
sponse(FIR) . . . . . 182
63
Vo
12.5 Switched-Capacitor 183
12.5.1 Switched capacitor
gain circuit . . . . . . 185
12.5.2 Switched capacitor
integrator . . . . . . 186
If you want to spend a bit of time, then try and calculate the transfer 12.5.3 Noise . . . . . . . . . 188
function below. 12.5.4 Sub-circuits for
SC-circuits . . . . . . 189
h i 12.5.5 Example . . . . . . . 193
𝐶1 2
𝐶𝐵 𝑠 + 𝐺2
𝐶𝐵 𝑠 + ( 𝐶𝐺𝐴1 𝐺𝐶𝐵3 ) 12.6 Want to learn more? 194
𝐻(𝑠) = h i
𝐺5 𝐺3 𝐺4
𝑠2 + 𝐶𝐵 𝑠 + 𝐶𝐴 𝐶𝐵
Active resistor capacitor filters are made with OTAs (high output
impedance) or OPAMP (low output impedance). Active amplifiers
will consume current, and in Active-RC the amplifiers are always
on, so there is no opportunity to reduce the current consumption
by duty-cycling (turning on and off).
Both resistors and capacitors vary on an integrated circuit, and the

3-sigma variation can easily be 20 %.
The pole or zero frequency of an Active-RC filter is proportional to

the inverse of the product between R and C
𝐺 1
𝜔 𝑝|𝑧 ∝ =
𝐶 𝑅𝐶
166 12 Switched-Capacitor Circuits
As a result, the total variation of the pole or zero frequency is can

have a 3-sigma value of
q √
𝜎𝑅𝐶 = 𝜎𝑅2 + 𝜎𝐶2 = 0.022 + 0.022 = 0.028 = 28 %
On an IC we sometimes need to calibrate the R or C in production

to get an accurate RC time constant.
We cannot physically change an IC, every single one of the 100

million copies of an IC is from the same Mask set. That’s why ICs
are cheap. To make the Mask set is incredibility expensive (think 5
million dollars), but a copy made from the Mask set can cost one
dollar or less. To calibrate we need additional circuits.
Imagine we need a resistor of 1 kOhm. We could create that

by parallel connection of larger resistors, or series connection of
smaller resistors. Since we know the maximum variation is 0.02,
then we need to be able to calibrate away +- 20 Ohms. We could
have a 980 kOhm resistor, and then add ten 4 Ohm resistors in
series that we can short with a transistor switch.
But is a resolution of 4 Ohms accurate enough? What if we need a

precision of 0.1%? Then we would need to tune the resistor within
+-1 Ohm, so we might need 80 0.5 Ohm resistors.
But how large is the on-resistance of the transistor switch? Would

that also affect our precision?
But is the calibration step linear with addition of the transistors? If

we have a non-linear calibration step, then we cannot use gradient
decent calibration algorithms, nor can we use binary search.
Analog designers need to deal with an almost infinite series of

“But”.
The experienced designer will know when to stop, when is the

“But what if” not a problem anymore.
The most common error in analog integrated circuit design is a “I

did not imagine that my circuit could fail in this manner” type of
problem. Or, not following the line of “But”’s far enough.
But if we follow all the “But”’s we will never tapeout!
Active-RC filters are great for linearity, but if we need accurate

time constant, there are better alternatives.
GL
Vi G
63
Vo 12.2 Gm-C 167
12.2 Gm-C
Gmt Gul Gms Vout

ca c
20
Guy Gms
Vin
20
h i
𝑠 2 𝐶𝑋𝐶+𝐶
𝑋
𝐵
+ 𝑠 𝐶𝑋𝐺+𝐶
𝑚5
𝐵
𝐻(𝑠) = h i
𝑠 2 + 𝑠 𝐶𝑋𝐺+𝐶
𝑚2
𝐵
The pole and zero frequency of a Gm-C filter is
𝐺𝑚
𝜔 𝑝|𝑧 ∝
𝐶
The transconductance accuracy depends on the circuit, and the

bias circuit, so we can’t give a general, applies for all circuits, sigma
number. Capacitors do have 3-sigma 20 % variation, usually.
Same as Active-RC, Gm-C need calibration to get accurate pole or

zero frequency.
12.3 Switched capacitor
The first time you encounter Switched Capacitor (SC) circuits, they
do require some brain training. So let’s start simple.
Consider the circuit below. Assume that the two transistors are
ideal (no-charge injection, no resistance).
Vi
zi 0
C
Q
Vgud
For SC circuits, we need to consider the charge on the capacitors,

and how they change with time.
The charge on the capacitor at the end ‗ of phase 2 is
𝑄 𝜙2$ = 𝐶1𝑉𝐺𝑁 𝐷 = 0
while at the end of phase 1 V0

Vi
𝑄 𝜙1$ = 𝐶1𝑉𝐼
zi C
The impedance, from Ohm’s law is
𝑍 𝐼 = (𝑉𝐼 − 𝑉𝐺𝑁 𝐷 )/𝐼𝐼
9 a
And from SI units units we can see current is
𝑄
𝐼𝐼 = = 𝑄 𝑓𝜙
𝑑𝑡
Vi Vo
Charge cannot disappear, charge is conserved. As such, the charge
Zi
going out from the input must be equal to the difference of charge
C
at the end of phase 1 and phase 2.
𝑉𝐼 − 𝑉𝐺𝑁 𝐷
𝑍𝐼 =
𝑄 𝜙1$ − 𝑄 𝜙2$ 𝑓𝜙

‗I use the $ to mark the end of the period. It comes from Regular Expressions.
12.3 Switched capacitor 169
Vi
zi
Inserting for the charges, we can see that the impedance is
0
𝑉𝐼 1
𝑍𝐼 = =
(𝑉𝐼 𝐶 − 0) 𝑓𝜙 𝐶1 𝑓𝜙
C
A common confusion with SC circuits is to confuse the impedance
of a capacitor 𝑍 = 1/𝑠𝐶 with the impedance of a SC circuit
Q
𝑍 = 1/ 𝑓 𝐶 . The impedance of a capacitor is complex (varies with
Vgud
frequency and time), while the SC circuit impedance is real (a
resistance).
The main difference between the two is that the impedance of a

capacitor is continuous in time, while the SC circuit is a discrete
time circuit, and has a discrete time impedance.
The circuit below is drawn slightly differently, but the same equa-
tion applies.
V0
Vi
zi C
If we compute the impedance.

9 a
𝑉𝐼 − 𝑉𝑂
𝑍𝐼 =
𝑄 𝜙1$ − 𝑄 𝜙2$ 𝑓𝜙

Vi Vo
𝑄 𝜙1$ = 𝐶1 (𝑉𝐼 − 𝑉𝑂 )
Zi C
𝑄 𝜙2$ = 0
𝑉𝐼 − 𝑉𝑂 1
𝑍𝐼 = =
(𝐶1 (𝑉𝐼 − 𝑉𝑂 )) 𝑓𝜙 𝐶1 𝑓𝜙
Which should not be surprising, as all I’ve done is to rotate the

circuit and call 𝑉𝐺𝑁 𝐷 = 𝑉0 .
Let’s try the circuit below.

zi C
9 a
Vi Vo
Zi C
𝑉𝐼 − 𝑉𝑂
𝑍𝐼 =
𝑄 𝜙1$ − 𝑄 𝜙2$ 𝑓𝜙

𝑄 𝜙1$ = 𝐶1𝑉𝐼 )
𝑄 𝜙2$ = 𝐶1𝑉𝑂
Inserted into the impedance we get the same result.
𝑉𝐼 − 𝑉𝑂 1
𝑍𝐼 = =
(𝐶1𝑉𝐼 − 𝐶1𝑉𝑂 )) 𝑓𝜙 𝐶1 𝑓𝜙
The first time I saw the circuit above it was not obvious to me that
the impedance still was 𝑍 = 1/𝐶 𝑓 . It’s one of the cases where
mathematics is a useful tool. I could follow a set of rules (charge
conservation), and as long as I did the mathematics right, then
from the equations, I could see how it worked.
12.3.1 An example SC circuit
An example use of an SC circuit is
A pipelined 5-Msample/s 9-bit analog-to-digital converter
Shown in the figure below. You should think of the switched

capacitor circuit as similar to a an amplifier with constant gain. We
can use two resistors and an opamp to create a gain. Imagine we
create a circuit without the switches, and with a resistor of 𝑅 from
input to virtual ground, and 4𝑅 in the feedback. Our Active-R
would have a gain of 𝐴 = 4.
12.3 Switched capacitor 171
The switches disconnect the OTA and capacitors for half the time,
but for the other half, at least for the latter parts of 𝜙2 the gain is
four.
The output is only correct for a finite, but periodic, time interval.
The circuit is discrete time. As long as all circuits afterwards also
have a discrete-time input, then it’s fine. An ADC can sample the
output from the amplifier at the right time, and never notice that
the output is shorted to a DC voltage in 𝜙1
We charge the capacitor 4𝐶 to the differential input voltage in 𝜙1
𝑄 1 = 4𝐶𝑉𝑖𝑛
Then we turn off 𝜙1 , which opens all switches. The charge on 4𝐶

will still be 𝑄 1 (except for higher order effects like charge injection
from switches).
After a short time (non-overlap), we turn on 𝜙2 , closing some of the

switches. The OTA will start to force its two inputs to be the same
voltage, and we short the left side of 4𝐶 . After some time we would
have the same voltage on the left side of 4𝐶 for the two capacitors,
and another voltage on the right side of the 4𝐶 capacitors. The two
capacitors must now have the same charge, so the difference in
charge, or differential charge must be zero.
Physics tell us that charge is conserved, so our differential charge

𝑄 1 cannot vanish into thin air. The difference in electrons that
made 𝑄 1 must be somewhere in our circuit.
Assume the designer of the circuit has done a proper job, then the
𝑄 1 charge will be found on the feedback capacitors.
We now have a 𝑄 1 charge on smaller capacitors, so the differential

output voltage must be
𝑄1 = 4𝐶𝑉𝑖𝑛 = 𝑄 2 = 𝐶𝑉𝑜𝑢𝑡
The gain is
𝑉𝑜𝑢𝑡
𝐴= =4
𝑉𝑖𝑛
Why would we go to all this trouble to get a gain of 4?
In general, we can sum up with the following equation.
𝐶1
𝜔 𝑝|𝑧 ∝
𝐶2
We can use these “switched capacitor resistors” to get pole or zero

frequency or gain proportional to a the relative size of capacitors,
which is a fantastic feature. Assume we make two identical ca-
pacitors in our layout. We won’t know the absolute size of the
capacitors on the integrated circuit, whether the 𝐶1 is 100 fF or 80
fF, but we can be certain that if 𝐶1 = 80 fF, then 𝐶2 = 80 fF to a
precision of around 0.1 %.
With switched capacitor amplifiers we can set an accurate gain,

and we can set an accurate pole and zero frequency (as long as we
have an accurate clock and a high DC gain OTA).
The switched capacitor circuits do have a drawback. They are

discrete time circuits. As such, we must treat them with caution,
and they will always need some analog filter before to avoid a
phenomena we call aliasing.
12.4 Discrete-Time Signals
An random, Gaussian, continuous time, continuous value, signal

has infinite information. The frequency can be anywhere from
zero to infinity, the value have infinite levels, and the time division
is infinitely small. We cannot store such a signal. We have to
quantize.
12.4 Discrete-Time Signals 173
If we quantize time to 𝑇 = 1 ns, such that we only record the value

of the signal every 1 ns, what happens to all the other information?
The stuff that changes at 0.5 ns or 0.1 ns, or 1 ns.
We can always guess, but it helps to know, as in absolutely know,

what happens. That’s where mathematics come in. With mathe-
matics we can prove things, and know we’re correct.
12.4.1 The mathematics
Define
𝑥𝑐
as a continuous time, continuous value signal
Define (
1 if 𝑡 ≥ 0
ℓ (𝑡) =
0 if 𝑡 < 0
Define
𝑥 𝑐 (𝑛𝑇)
𝑥 𝑠𝑛 (𝑡) = [ℓ (𝑡 − 𝑛𝑇) − ℓ (𝑡 − 𝑛𝑇 − 𝜏)]
𝜏
where 𝑥 𝑠𝑛 (𝑡) is a function of the continuous time signal at the time

interval 𝑛𝑇 .
Define
∞
X
𝑥 𝑠 (𝑡) = 𝑥 𝑠𝑛 (𝑡)
𝑛=−∞
where 𝑥 𝑠 (𝑡) is the sampled, continuous time, signal.
Think of a sampled version of an analog signal as an infinite sum

of pulse trains where the area under the pulse train is equal to the
analog signal.
Why do this?
With a exact definition of a sampled signal in the time-domain it’s

sometimes possible to find the Laplace transform, and see how the
frequency spectrum looks.
If
∞
X
𝑥 𝑠 (𝑡) = 𝑥 𝑠𝑛 (𝑡)
𝑛=−∞
Then
1 1 − 𝑒 −𝑠𝜏
𝑋𝑠𝑛 (𝑠) = 𝑥 𝑐 (𝑛𝑇)𝑒 −𝑠𝑛𝑇
𝜏 𝑠
And
∞
1 1 − 𝑒 −𝑠𝜏 X
𝑋𝑠 (𝑠) = 𝑥 𝑐 (𝑛𝑇)𝑒 −𝑠𝑛𝑇
𝜏 𝑠 𝑛=−∞
Thus
∞
X
lim → 𝑋𝑠 (𝑠) = 𝑥 𝑐 (𝑛𝑇)𝑒 −𝑠𝑛𝑇
𝜏→0 𝑛=−∞
Or
∞
𝑗 𝑘 2𝜋

1 X
𝑋𝑠 (𝑗𝜔) = 𝑋𝑐 𝑗𝜔 −
𝑇 𝑘=−∞ 𝑇
The spectrum of a sampled signal is an infinite sum of frequency

shifted spectra
or equivalently
When you sample a signal, then there will be copies of the input
spectrum at every
𝑛 𝑓𝑠
However, if you do an FFT of a sampled signal, then all those

infinite spectra will fold down between
0 → 𝑓𝑠 1 /2
or
− 𝑓𝑠 1 /2 → 𝑓𝑠 1 /2
for a complex FFT
12.4.2 Python discrete time example
If your signal processing skills are a bit thin, now might be a good
time to read up on FFT, Laplace transform and But what is the
Fourier Transform?
In python we can create a demo and see what happens when

we “sample” an “continuous time” signal. Hopefully it’s obvious
that it’s impossible to emulate a “continuous time” signal on a
digital computer. After all, it’s digital (ones and zeros), and it has
a clock!
We can, however, emulate to any precision we want.
The code below has four main sections. First is the time vector.
I use Numpy, which has a bunch of useful features for creating
ranges, and arrays.
Secondly, I create continuous time signal. The time vector can

be used in numpy functions, like np.sin(), and I combine three
sinusoid plus some noise. The sampling vector is a repeating
pattern of 11001100, so our sample rate should be 1/2’th of the input
sample rate. FFT’s can be unwieldy beasts. I like to use coherent
sampling, however, with multiple signals and samplerates I did

not bother to figure out whether it was possible.
The alternative to coherent sampling is to apply a window function

before the FFT, that’s the reason for the Hanning window below.
dt.py
#- Create a time vector

N = 2**13
t = np.linspace(0,N,N)
#- Create the "continuous time" signal with multiple

#- "sinusoidal signals and some noise
f1 = 233/N
fd = 1/N*119
x_s = np.sin(2*np.pi*f1*t) + 1/1024*np.random.randn(N) + \
0.5*np.sin(2*np.pi*(f1-fd)*t) + 0.5*np.sin(2*np.pi*(f1+fd)*t)
#- Create the sampling vector, and the sampled signal

t_s_unit = [1,1,0,0,0,0,0,0]
t_s = np.tile(t_s_unit,int(N/len(t_s_unit)))
x_sn = x_s*t_s
#- Convert to frequency domain with a hanning window to avoid FFT bin

#- energy spread
Hann = True
if(Hann):
w = np.hanning(N+1)
else:
w = np.ones(N+1)
X s = np.fft.fftshift(np.fft.fft(np.multiply(w[0:N],x_s)))
_
X_sn = np.fft.fftshift(np.fft.fft(np.multiply(w[0:N],x_sn)))
Try to play with the code, and see if you can understand what it
does.
Below are the plots. On the left side is the “continuous value,
continuous time” emulation, on the right side “discrete time,
continuous value”.
The top plots are the time domain, while the bottom plots is
frequency domain.
The FFT is complex, so that’s why there are six sinusoids bottom
left. The “0 Hz” would be at x-axis index 4096 (213 /2).
The spectral copies can be seen bottom right. How many spectral
copies, and the distance between them will depend on the sample
rate (length of t_s_unit). Try to play around with the code and
see what happens.
2.0 2.0
1.5 1.5
1.0 1.0
0.5 0.5
Time Domain
0.0 0.0
0.5 0.5
1.0 1.0
1.5 1.5
2.0 2.0
0 2000 4000 6000 8000 0 2000 4000 6000 8000
60
60
40
40
20
Frequency Domain
20
0
0
20
20
40
40
60
60
80
0 2000 4000 6000 8000 0 2000 4000 6000 8000
Continuous time, continuous value Discrete time, continuous value
12.4.3 Aliasing, bandwidth and sample rate theory
I want you to internalize that the spectral copies are real. They
are not some “mathematical construct” that we don’t have to deal
with.
They are what happens when we sample a signal into discrete

time. Imagine a signal with a band of interest as shown below in
Wesuch
Green.As should
sample atx 𝑓𝑠t. The be band
pink and
limited before
red unwanted signals do not
disappearsampling
after sampling, even though they are above the Nyquist
frequency ( 𝑓𝑠 /2). They fold around 𝑓𝑠 /2, and in may appear in-
band. That’s why it’s important to band limit analog signals before
they are sampled.
Before Saulius
P T
Es th
N it it
th f ask o
After sampling
8 I
Es th
i Iii th Is
f
Before Sampling
Anti Alias
P T
Es th
N it it
th f ask o
After sampling
With an anti-alias filter (yellow) we ensure that the unwanted
Iii
components are low enough before sampling. As a result, our
wanted signal (green) is undisturbed.
8 I i f
Es th th Is
Before Sampling
Anti Alias
ot I o LP o SH o
Es th it th f
After sampling
8 1 I f
Es th th f
Assume that we we’re interested in the red signal. We could still

use a sample rate of 𝑓𝑠 . If we bandpass-filtered all but the red signal
the red signal would fold on sampling, as shown in the figure
below.
Remember that the Nyquist-Shannon states that a sufficient no-

loss condition is to sample signals with a sample rate of twice the
bandwidth of the signal.
Nyquist-Shannon has been extended for sparse signals, compressed

sensing, and non-uniform sampling to demonstrate that it’s suffi-
cient for the average sample rate to be twice the bandwidth. One
2009 paper Blind Multiband Signal Reconstruction: Compressed
Sensing for Analog Signal is a good place to start to delve into the
latest on signal reconstruction.
Before Sampling
AEs p th I I
th Is
M a app ask o
A
After sampling
o 1 I p p 1 I f
Es th th f
12.4.4 Z-transform
Someone got the idea that writing
∞
X
𝑋𝑠 (𝑠) = 𝑥 𝑐 (𝑛𝑇)𝑒 −𝑠𝑛𝑇
𝑛=−∞
was cumbersome, and wanted to find something better.
∞
X
𝑋𝑠 (𝑧) = 𝑥 𝑐 [𝑛]𝑧 −𝑛
𝑛=−∞
For discrete time signal processing we use Z-transform
If you’re unfamiliar with the Z-transform, read the book or search

https://en.wikipedia.org/wiki/Z-transform
The nice thing with the Z-transform is that the exponent of the
z tell’s you how much delayed the sample 𝑥 𝑐 [𝑛] is. A block that
delays a signal by 1 sample could be described as 𝑥 𝑐 [𝑛]𝑧 −1 , and an
accumulator
𝑦[𝑛] = 𝑦[𝑛 − 1] + 𝑥[𝑛]
in the Z domain would be
𝑌(𝑧) = 𝑧 −1𝑌(𝑧) + 𝑋(𝑧)
With a Z-domain transfer function of

𝑌(𝑧) 1
=
𝑋(𝑧) 1 − 𝑧 −1
12.4.5 Pole-Zero plots
If you’re not comfortable with pole/zero plots, have a look at
What does the Laplace Transform really tell us
Think about the pole/zero plot as a surface your looking down

onto. At 𝑎 = 0 we have the steady state fourier transform. The “x”
shows the complex frequency where the fourier transform goes to
infinity.
Any real circuit will have complex conjugate, or real, poles/zeros.

A combination of two real circuits where one path is shifted 90
degrees in phase can have non-conjugate complex poles/zeros.
If the “x” is 𝑎 < 0, then any perturbation will eventually die out. If
the “x” is on the 𝑎 = 0 line, then we have a oscillator that will ring
forever. If the “x” is 𝑎 > 0 then the oscillation amplitude will grow
without bounds, although, only in Matlab. In any physical circuit
an oscillation cannot grow without bounds forever.
Growing without bounds is the same as “being unstable”.
jw s atjw
a
X
poles
12.4.6 Z-domain 440
O
0 repeat every
Spectra Leros ifs𝜋
2
Discrete time
180 12 Switched-Capacitor Circuits a
X
As such, it does not make sense to talk about a plane with a 𝑎 and
a 𝑗𝜔 . Rather we use the complex number 𝑧 = 𝑎 + 𝑗𝑏 .
As long as the poles (“x”) are within the unit circle, oscillations
will die out. If the poles are on the unit-circle, then we have an
oscillator. Outside the unit circle the oscillation will grow without
poles 440
bounds, or in other words, be unstable.
We can translate between Laplace-domain and Z-domain with the
O
ifs
Bi-linear transform
0 Leros
𝑧−1
𝑠=
𝑧+1
Discrete time
Warning: First-order approximation https://en.wikipedia.org/w
iki/Bilinear_transform
Z plane
b
jw Zsa
g
x
x
12.4.7 First order filter
Assume a first order filter given by the discrete time equation.
𝑦[𝑛 + 1] = 𝑏𝑥[𝑛] + 𝑎 𝑦[𝑛] ⇒ 𝑌𝑧 = 𝑏𝑋 + 𝑎𝑌
The “n” index and the “z” exponent can be chosen freely, which
sometimes can help the algebra.
𝑦[𝑛] = 𝑏𝑥[𝑛 − 1] + 𝑎 𝑦[𝑛 − 1] ⇒ 𝑌 = 𝑏𝑋 𝑧 −1 + 𝑎𝑌𝑧 −1
The transfer function can be computed as

𝑏
𝐻(𝑧) =
𝑧−𝑎
From the discrete time equation we can see that the impulse will
never die out. We’re adding the previous output to the current
input. That means the circuit has infinite memory. Accordingly,
filters of this type are known as. Infinite-impulse response (IIR)
(
𝑘 if 𝑛 < 1
ℎ[𝑛] =
𝑎 𝑛−1 𝑏 + 𝑎 𝑛 𝑘 if 𝑛 ≥ 1
Head’s up: Fig 13.12 in AIC is wrong
From the impulse response it can be seen that if 𝑎 > 1, then the
filter is unstable. Same if 𝑏 > 1. As long as |𝑎 + 𝑗𝑏| < 1 the filter
should be stable.
First order
Hz Ia
stable
unstable
akestan
66 ha
It t a
xD
gylate
Aza Sta yEnt1
The first order filter can be implemented in python, and it’s really
not hard. See below. The 𝑥 𝑠 𝑛 vector is from the previous python
example.
FIR
There are smarter, and faster ways to do IIR filters (and FIR) in
112
python, see scipy.signal.iirfilter
Fitt impulse repose

From the plot below we can see the sampled time domain and
spectra on the left, and the filtered time domain and spectra on the
Infinite inputs
right. e response
iir.py
H t Ea
E
z Hee
1.00 1.00
0.75 0.75
0.50 0.50
0.25 0.25
Time Domain
0.00 0.00
0.25 0.25
0.50 0.50
0.75 0.75
1.00 1.00
1000 1050 1100 1150 1200 1250 1300 1350 1400 1000 1050 1100 1150 1200 1250 1300 1350 1400
60
40
40
20 20
Frequency Domain
0 0
20
20
40
40
60
60 80
0 2000 4000 6000 8000 0 2000 4000 6000 8000
Sampled IIR Filter
#- IIR filter
b = 0.3
a = 0.25
z = a + 1j*b
z_abs = np.abs(z)
print("|z| = " + str(z_abs))
y = np.zeros(N)
y[0] = a
for i in range(1,N):
y[i] = b*x_sn[i-1] + y[i-1]
The IIR filter we implemented above is a low-pass filter, and the

filter partially rejects the copied spectra, as expected.
12.4.8 Finite-impulse response(FIR)
FIR filters are unconditionally stable, since the impulse response

will always die out. FIR filters are a linear sum of delayed inputs.
In my humble opinion, there is nothing wrong with an IIR. Yes,

the could become unstable, however, they can be designed safely.
I’m not sure there is a theological feud on IIR vs FIR, I suspect
there could be. Talk to someone that knows digital filters better
than me.
But be wary of rules like “IIR are always better than FIR” or visa
versa. Especially if statements are written in books. Remember that
the book was probably written a decade ago, and based on papers
two decades old, which were based on three decades old state of
Fitt impulse repose Infinite inputs
e response
12.5 Switched-Capacitor
183
H t Ea
E
z
the art. Our abilities to use computers for design has improved a Hee
bit the last three decades.
hlultakestan
2
1X
𝐻(𝑧) = 𝑧 −1
3 𝑖=0
XE
4
43
Iya
12.5 Switched-Capacitor
Below is an example of a switched-capacitor circuit during phase 1.

Think of the two phases as two different configurations of a circuit,
each with a specific purpose.
Cz Cz
t t
it q Ve un
t c G
Q
This is the SC circuit during the sampling phase. Imagine that
Q
we somehow have stored a voltage 𝑉1 = ℓ on capacitor 𝐶1 (the
switches for that sampling or storing are not shown). The charge
on 𝐶1 is
Qz Qz
𝑄1𝜙1 $ = 𝐶1𝑉1
The 𝐶2 capacitor is shorted, as such, 𝑉2 = 0, which must mean that

the charge on 𝐶2 given by
𝑄 2 𝜙1 $ = 0
C E E
The voltage at the negative input of the OTA must be 0 V, as the

positive input is 0 V, and we assume the circuit has settled all
transients.
Imagine we (very carefully) open the circuit around 𝐶2 and close

the circuit from the negative side of 𝐶1 to the OTA negative input,
as shown below.
Cz Cz
t t
it q Ve un
c G
Q
It’s the OTA that ensures that the negative input is the same as the
Q positive input, but the OTA cannot be infinitely fast. At the same
time, the voltage across 𝐶1 cannot change instantaneously. Neither
Qz Qz
can the voltage across 𝐶2 . As such, the voltage at the negative input
must immediately go to −𝑉1 (ignoring any parasitic capacitance at
the negative input).
The OTA does not like it’s inputs to be different, so it will start to
charge 𝐶2 to increase the voltage at the negative input to the OTA.
When the negative input reaches 0 V the OTA is happy again. At
that point the charge on 𝐶1 is
𝑄 1 𝜙2 $ = 0
C E E
A key point is, that even the voltages now have changed, there is
zero volt across 𝐶1 , and thus there cannot be any charge across 𝐶1
the charge that was there cannot have disappeared. The negative
input of the OTA is a high impedance node, and cannot supply
A B A A B
charge. The charge must have gone somewhere, but where?
B
In process of changing the voltage at the negative input of the OTA
we’ve changed the voltage across 𝐶2 . The voltage change must
exactly match the charge that was across 𝐶1 , as such
c
c
𝑄 2𝜙2 $ = 𝑄1𝜙1 $ = 𝐶1𝑉1 = 𝐶2𝑉2
A B
thus C
on
if
𝑉2
𝑉1
=
𝐶1
𝐶2
a
ur
12.5.1 Switched capacitor gain circuit

a
Redrawing the previous circuit, and adding a few more switches

we can create a switched capacitor gain circuit.
Vocutis Vi n
Cg
There is now a switch to sample the input voltage across 𝐶1 during
H
phase 1 and reset 𝐶2 . During phase 2 we configure the circuit to
VoOTA
leverage the
Evi HE
g a 𝐶1 to 𝐶2 .
Z to do the charge transfer from
Cz
Vien viii
VoEu
error
The discrete time output from the circuit will be as shown below.
It’s only at the end of the second phase that the output signal is
valid. As a result, it’s common to use the sampling phase of the
next circuit close to the end of phase 2.
For charge to be conserved the clocks for the switch phases must
never be high at the same time.
H
Z
Evi HE
186
ga
12 Switched-Capacitor Circuits
Cz
viii
VoEu
error
The discrete time, Z-domain and transfer function is shown below.
The transfer function tells us that the circuit is equivalent to a
gain, and a delay of one clock cycle. The cool thing about switch
capacitor circuits is that the precision of the gain is set by the
relative size between two capacitors. In most technologies that
relative sizing can be better than 0.1 %.
Gain circuits like the one above find use in most Pipelined ADCs,
and are common, with some modifications, in Sigma-Delta
ADCs.
𝐶1
𝑉𝑜 [𝑛 + 1] = 𝑉𝑖 [𝑛]
𝐶2
𝐶1
𝑉𝑜 𝑧 = 𝑉𝑖
𝐶2
𝑉𝑜 𝐶 1 −1
= 𝐻(𝑧) = 𝑧
𝑉𝑖 𝐶2
12.5.2 Switched capacitor integrator
Removing one switch we can change the function of the switched

capacitor gain circuit. If we don’t reset 𝐶2 then we accumulate the
input charge every cycle.
Vos
C Cz
Cz
Vith
Nt
a
VoEu
G
N
no
The output now will grow without bounds, so integrators are most arrow
often used in filter circuits, or sigma-delta ADCs where there is
feedback to control the voltage swing at the output of the OTA.
C Cz
Vos
Vo
En VoEn I Vicu r
Cz Et
Vo ElVo zaVi
É
Nt
E EEE E
VoEu HCA
N
no
arrow
Make sure you read and understand the equations below, it’s good
to realize that discrete time equations, Z-domain and transfer
functions in the Z-domain are actually easy.
icu r 𝑉𝑜 [𝑛] = 𝑉𝑜 [𝑛 − 1] +
𝐶1
𝐶2
𝑉𝑖 [𝑛 − 1]
𝐶 1 −1
𝑉𝑜 − 𝑧 −1𝑉𝑜 = 𝑧 𝑉𝑖
𝐶2
E
Maybe one confusing thing is that multiple transfer functions can

mean the same thing, as below.
𝐶 1 𝑧 −1 𝐶1 1
𝐻(𝑧) = =
𝐶2 1 − 𝑧 − 1 𝐶2 𝑧 − 1
12.5.3 Noise
Capacitors don’t make noise, but switched-capacitor circuits do

have noise. The noise comes from the thermal, flicker, burst noise
in the switches and OTA’s. Both phases of the switched capacitor
circuit contribute noise. As such, the output noise of a SC circuit is
usually
2 𝑘𝑇
𝑉𝑛2 >
𝐶
I find that sometimes it’s useful with a repeat of mathematics, and

since we’re talking about noise.
The mean, or average of a signal is defined as
Mean ∫ +𝑇/2
1
𝑥(𝑡) = lim 𝑥(𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2
Define
Mean Square
∫ +𝑇/2
1
𝑥 2 (𝑡) = lim 𝑥 2 (𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2
How much a signal varies can be estimated from the Variance

2
𝜎2 = 𝑥 2 (𝑡) − 𝑥(𝑡)
where
𝜎
is the standard deviation. If mean is removed, or is zero, then
𝜎2 = 𝑥 2 (𝑡)
Assume two random processes,
𝑥 1 (𝑡)
and
𝑥 2 (𝑡)
with mean of zero (or removed).
𝑥 𝑡𝑜𝑡 (𝑡) = 𝑥 1 (𝑡) + 𝑥 2 (𝑡)
𝑥 𝑡𝑜𝑡
2
(𝑡) = 𝑥 12 (𝑡) + 𝑥 22 (𝑡) + 2𝑥 1 (𝑡)𝑥 2 (𝑡)
Variance (assuming mean of zero)

∫ +𝑇/2
1
𝜎𝑡𝑜𝑡
2
= lim 𝑥 𝑡𝑜𝑡
2
(𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2
∫ +𝑇/2
1
𝜎𝑡𝑜𝑡
2
= 𝜎12 + 𝜎22 + lim 2 𝑥 1 (𝑡)𝑥 2 (𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2
Assuming uncorrelated processes (covariance is zero), then
𝜎𝑡𝑜𝑡
2
= 𝜎12 + 𝜎22
In other words, if two noises are uncorrelated, then we can sum

the variances. If the noise sources are correlated, for example,
noise comes from the same transistor, but takes two different paths
through the circuit, then we cannot sum the variances. We must
also add the co-variance.
12.5.4 Sub-circuits for SC-circuits
Switched-capacitor circuits are so common that it’s good to delve

a bit deeper, and understand the variants of the components that
make up SC circuits.
12.5.4.1 OTA
At the heart of the SC circuit we usually find an OTA. Maybe a

current mirror, folded cascode, recycling cascode, or my favorite: a
fully differential current mirror OTA with cascoded, gain boosted,
output stage using a parallel common mode feedback.
Not all SC circuits use OTAs, there are also comparator based SC
circuits.
Below is a fully-differential two-stage OTA that will work with

most SC circuits. The notation “24F1F25” means “the width is 24
F” and “length is 1.25 F”, where “F” is the minimum gate length
in that technology.
As bias circuit to make the voltages the below will work
12.5.4.2 Switches
If your gut reaction is “switches, that’s easy”, then you’re very

wrong. Switches can be incredibly complicated. All switches will be
made of transistors, but usually we don’t have enough headroom
to use a single NMOS or PMOS. We may need a transmission
gate
C E E
A B A B A B
c
c
A B
C
The challenge with transmission gates is that when the voltage at

the input is in the middle between VDD and ground then both
PMOS and NMOS, although they are on , they might not be that
on. Especially in nano-scale CMOS with a 0.8 V supply and 0.5 V
threshold voltage. The resistance mid-rail might be too large.
For switched-capacitor circuits we must settle the voltages to the

required accuracy. In general
𝑡 > − log(error)𝜏
For example, for a 10-bit ADC we need 𝑡 > − log(1/1024)𝜏 = 6.9𝜏.

This means we need to wait at least 6.9 time constants for the voltage
to settle to 10-bit accuracy in the switched capacitor circuit.
Assume the capacitors are large due to noise, then the switches
must be low resistance for a reasonable time constant. Larger
switches have smaller resistance, however, they also have more
charge in the inversion layer, which leads to charge injection when
the switches are turned of. Accordingly, larger switches are not
always the solution.
Sometimes it may be sufficient to switch the bulks, as shown on

the left below. But more often that one would like, we have to
implement bootstrapped switches as shown on the right.
c e
c e
A c e B c
A B
The switch I used in my JSSC SAR is a fully differential boostrapped

switch with cross coupled dummy transistors. The JSSC SAR I’ve
also ported to GF130NM, as shown
bottom.
i
i
below. The switch is at the
Be
wulffern/sun_sar9b_sky130nm
Ap
E e
C E
g
An Bu
looks like the one below.

i
i
Be
Ap
E e
C E
g
An Bu
12.5.4.3 Non-overlapping clocks
The non-overlap generator is standard. Use the one shown below.

Make sure you simulate that the non-overlap is sufficient in all
corners.
on
if
a
ur
12.5.5 Example
cutis
Vo Vi n
Cg
H
In the circuit below there
HE is anaexample of a switched capacitor cir-
VoZ
Evi g
cuit used to increase the Δ𝑉𝐷 across the resistor. We can accurately
set the gain, and thus the equation for the differential output will
be
Cz
Vien viii
VoEu
𝑘𝑇
𝑉𝑂 (𝑧) = 10 ln(𝑁)𝑧 −1
𝑞
n
I 2
TCalooff
Blind Multiband Signal Reconstruction: Compressed Sensing for

Analog Signal
Comparator-based switched-capacitor pipelined analog-to-digital

converter with comparator preset, and comparator delay compen-
sation
A Compiled 9-bit 20-MS/s 3.5-fJ/conv.step SAR ADC in 28-nm

FDSOI for Bluetooth Low Energy Receivers
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching

Procedure
Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-

Sigma Modulator
Ring Amplifiers for Switched Capacitor Circuits
A Switched-Capacitor RF Power Amplifier
Design of Active N-Path Filters

Oversampling and Sigma-Delta
ADCs 13
Keywords: Quantization, OSR, NEG FB, STF, NTF, SAR, First Order, 13.1 ADC state-of-the-art 195
SC SD, CT SD, INCR, FOM 13.1.1 What makes a state-
of-the-art ADC . . . 196
13.1.2 High resolution FOM 203
13.2 Quantization . . . . 204
13.1 ADC state-of-the-art 13.2.1 Signal to Quantiza-
tion noise ratio . . . 208
13.2.2 Understanding
The performance of an analog-to-digital converter is determined
quantization . . . . . 208
by the effective number of bits (ENOB), the power consumption, 13.2.3 Why you should care
and the maximum bandwidth. The effective number of bits contain about quantization
information on the linearity of the ADC. The power consumption noise . . . . . . . . . 211
shows how efficient the ADC is. The maximum bandwidth limits 13.3 Oversampling . . . 211
what signals we can sample and reconstruct in digital domain. 13.3.1 Noise power . . . . . 212
13.3.2 Signal power . . . . 213
Many years ago, Robert Walden did a study of ADCs, one of the 13.3.3 Signal to Noise Ratio 213
plot’s is shown below. 13.3.4 Signal to Quantiza-
tion Noise Ratio . . . 213
1999, R. Walden: Analog-to-digital converter survey and analysis 13.3.5 Python oversample 214
13.4 Noise Shaping . . . 215
There are obvious trends, the faster an ADC is, the less precise
13.4.1 The magic of feed-
the ADC is ( lower SNDR). There are also fundamental limits, back . . . . . . . . . . 215
Heisenberg tells us that a 20-bit 10 GS/s ADC is impossible, 13.4.2 Sigma-delta principle 216
according to Walden. 13.4.3 Signal transfer func-
tion . . . . . . . . . . 218
13.4.4 Noise transfer func-
tion . . . . . . . . . . 219
13.4.5 Combined transfer
function . . . . . . . 219
13.5 First-Order Noise-
Shaping . . . . . . . 219
13.5.1 SQNR and ENOB . . 221
13.6 Examples . . . . . . 222
13.6.1 Python noise-
shaping . . . . . . . . 222
13.6.2 The wonderful world
of SD modulators . . 224
The uncertainty principle states that the precision we can determine
position and the momentum of a particle is
ℏ
𝜎𝑥 𝜎𝑝 ≥
2
. There is a similar relation of energy and time, given by
ℎ
Δ𝐸Δ𝑡 >
2𝜋
196 13 Oversampling and Sigma-Delta ADCs
where Δ𝐸 is the difference in energy, and Δ𝑡 is the difference in

time.
You should take these limits with a grain of salt. The plot assumes
50 Ohm and 1 V full-scale. As a result, the “Heisenberg” line that
appears to be unbreakable certainly is breakable. Just change the
voltage to 100 V, and the number of bits can be much higher. Always
check the assumptions.
A more recent survey of ADCs comes from Boris Murmann. He

still maintains a list of the best ADCs from ISSCC and VLSI
Symposium.
B. Murmann, ADC Performance Survey 1997-2023
A common figure of merit for low-to-medium resolution ADCs is

the Walden figure of merit, defined as
𝑃
𝐹𝑂 𝑀𝑊 =
2𝐵 𝑓 𝑠
Below 10 fJ/conv.step is good.
Below 1 fJ/conv.step is extreme.
In the plot below you can see the ISSCC and VLSI ADCs.
2.E+03
FOMW,hf [fJ/conv-step]
2.E+02
2.E+01
ISSCC 2021
2.E+00 VLSI 2021

ISSCC 1997-2020
VLSI 1997-2020
Envelope
2.E-01
1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11
fsnyq [Hz]
13.1.1 What makes a state-of-the-art ADC
People from NTNU have made some of the worlds best ADCs
If you ever want to make an ADC, and you want to publish

the measurements, then you must be better than most. A good
algorithm for state-of-the-art ADC design is to first pick a sample
rate with low number of data (blank spaces in the plot above), then
13.1 ADC state-of-the-art 197
read the papers in the vicinity of the blank space to understand

the application, then set a target FOM which is best in world, then
try and find a ADC architecture that can achieve that FOM.
That’s pretty much the algorithm I, and others, have followed to

make state-of-the-art ADCs. A few of the NTNU ADCs are:
[1] A Compiled 9-bit 20-MS/s 3.5-fJ/conv.step SAR ADC in 28-nm

FDSOI for Bluetooth Low Energy Receivers
[2] A 68 dB SNDR Compiled Noise-Shaping SAR ADC With

On-Chip CDAC Calibration
In order to publish, there must be something new. Preferably a

new circuit. Below is the circuit from [1]. It’s a standard successive-
approximation register (SAR) analog-to-digital converter.
The differential input signal is sampled on a capacitor array where

the bottom plate is connected to either VSS or VREF. Once the volt-
age is sampled, the comparator will decide whether the differential
voltage is larger, or smaller than 0. Depending on the decision, the
MSB capacitors (left-most) in figure will switch the bottom plate in
order to effectively subtract a voltage equivalent to half the VREF
voltage.
The comparator makes another decision, and 1/4’th the VREF

voltage is subtracted or added. Then 1/8’th and so on implementing
a binary search to find the input voltage.
The “bit-cycling” (binary-search) loop is self-timed, as such, when

the comparator has made a decision, the next cycle starts.
In (b) we can see the enable flip-flop for the next stage. The CK
bar is the sample clock, as such, A is high during sampling. The
output of the comparator (P and N) is low.
As soon as the comparator makes a decision, P or N goes high, A

will be pulled low, if EI is enabled.
In (c) we can see that the bottom plate of the capacitors 𝐷𝑃 0 , 𝐷𝑃 1 ,

𝐷𝑁 0 , and 𝐷𝑁 1 , are controlled by P and N.
In (d) we can see that the bottom plate of the capacitors also used to
set the comparator clock low again (CO), resetting the comparator,
and pulling P and N low, which in (b) enables the next SAR logic
state.
How fast the 𝐷𝑋𝑋 settle depend on the size of the capacitors, as
such, the comparator clock will be slow for the MSB, and very fast
for the LSB. This was my main circuit contribution in the paper.
I think it’s quite clever, because both the VDD and the capacitor
corner will change the settling time. It’s important that the capacitor
values fully settle before the next comparator decision, and as a
result of the circuit in (c,d) the delay is automatically adjusted.
For further details see the paper.
CK D8 CK D7 CK D6 CK D5 CK D4 CK D3 CK D2 CK D1 CK D0
DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N
CI CO CI CO CI CO CI CO CI CO CI CO CI CO CI CO CI CO
LOGIC[8] LOGIC[7] LOGIC[6] LOGIC[5] LOGIC[4] LOGIC[3] LOGIC[2] LOGIC[1] LOGIC[0] CK
CK EI EO EI EO EI EO EI EO EI EO EI EO EI EO EI EO EI EO
DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 1 DN 0 DP 1 DN 0 DP 1 DN 0 DP 1 DN 0 X1
X2
CK
CK CM P
VP +
P
VN −
Bootstrapped 28 · CU N IT 27 · CU N IT 26 · CU N IT 25 · CU N IT 24 · CU N IT 23 · CU N IT 22 · CU N IT 21 · CU N IT 20 · CU N IT N
NMOS switches
(a)
VDD VDD VDD VDD
VREF VREF VDD VDD

CK MP 0 MP 3 CK MP 4 CK MP 5
MP 6 MP 7
DP 0 DN 0 DN 1 DP 1
N MP 2 EI MN 6 EI MN 9
A
EI MN 0 P MP 1 MN 5 MN 8
EO B
P MN 1 N MN 2 MN 3 P MN 4 N MN 7 CK MN 10
CI CO
(b) (c) (d)
For state-of-the-art ADC papers it’s not sufficient with the idea,
and simulation. There must be proof that it actually works. No-one
will really believe that the ADC works until there is measurements
of an actual taped out IC.
Below you can see the layout of the IC I made for the paper. Notice
that there are 9 ADCs. I had many ideas that I wanted to try out,
and I was not sure what would actually be state of the art. As a
result, I taped out multiple ADCS.
The two ADCs that I ended up using in the paper is shown below.
The one on the left was made with 180 nm IO transistors, while
the one on the right was made with core-transistors. Notice that
the layout of the two is quite similar.
Comparator
Logic
106µm
CDAC
80µm
Switch
39µm
40µm
(a) (b)
Once taped out, and many months of waiting, a few months of

measurement in the lab, I had some results that would be good
enough to qualify for the best conference, and luckily the best
journal.
0 0
Amplitude = -0.42 dBFS, ENOB = 7.82 b Amplitude = -0.60 dBFS, ENOB = 7.42 b
Magnitude [dBFS]
Magnitude [dBFS]
−20 −20
SNDR = 48.84 dB, SFDR = 63.11 dBc SNDR = 46.43 dB, SFDR = 61.72 dBc
Samples = 16384 Samples = 16384
−40 −40
VDD = 0.69 V, IDD = 23 µA VDD = 0.47 V, IDD = 2 µA
FoM = 3.51 fJ/conv.step FoM = 2.73 fJ/conv.step
−60 −60
−80 −80
0 1 2 3 4 5 6 7 8 9 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency [MHz] Frequency [MHz]
(a) (b)
8.5 70
Peak ENOB @ fs/2 [bit]
Magnitude [dB]
8
60
SNDR [dB]
7.5 SFDR [dBc]
80 kS/s
2 MS/s 50
7 20 MS/s
80 MS/s
6.5 40
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0 1 2 3 4 5 6 7 8 9 10
VDD [V] Input frequency [MHz]
(c) (d)
Comparing my ADCs to others, we can see that the FOM is similar

to others. Based on the FOM it might not be clear why the paper
was considered state-of-the-art.
The circuit technique mentioned above would not have been

enough to qualify. The big thing was the “Compiled” line. Com-
pared to the other “Compiled” mine was 300 times better, and on
par with other state-of-the-art.
Weaver [5] Harpe [9] Patil [10] Liu [11] This work
Technology (nm) 90 90 28 FDSOI 28 28 FDSOI
Fsample (MS/s) 21 2 No sampling 100 2 20
Core area (mm2 ) 0.18 0.047 0.0032 0.0047 0.00312
SNDR (dB) 34.61 57.79 40 64.43 46.43 48.84
SFDR (dBc) 40.81 72.33 30 75.42 61.72 63.11
ENOB (bits) 5.45 6.7 - 9.4 6.35 10.41 7.42 7.82
Supply (V) 0.7 0.7 0.65 0.9 0.47 0.69
Pwr (µW) 1110 1.64 -3.56 24 350 0.94 15.87
Compiled Yes No No No Yes
FoM (fJ/c.step) 838 2.8 - 6.6 3.7 2.6 2.7 3.5
The big thing was how I made the ADC. I started with a definition
of a transistor, as shown below
Vertical Grid
D
Horizontal Grid
G B
S
OD CO PO M1
And then wrote a compiler (in Perl, later C++ ciccreator) to compile
a object definition file, a SPICE netlist and a technology rule file
into the full ADC layout.
In (a) you can see one of the cells in the SAR logic, (b) is the spice
file, and (c) is the definition of the routing. The numbers to the
right in the routing creates the paths shown in (d).
.SUBCKT SAREMX1_CV P N EI EO CK_N AVDD AVSS

MN0 N3 EI A AVSS NCHDL
MN1 N3 P AVSS AVSS NCHDL
MN2 AVSS N N3 AVSS NCHDL
MN3 EO A AVSS AVSS NCHDL
MP0 AVDD CK_N A AVSS PCHDL
MP1 N2 P EO AVSS PCHDL
MP2 N1 N N2 AVSS PCHDL
MP3 AVDD A N1 AVSS PCHDL
.ENDS
(b)
{ "name": "SAREMX1_CV",
"class" : "Layout::LayoutDigitalCell",
"addConnectivityRoutes": [
["M1","N1|N2","||",""], 1
["M1","N3","-|",""], 2
["M1","EO","--|-","onTopR"] 3
],
"addDirectedRoutes" : [
["PO","P","MN1:G-MP1:G"], 4
["PO","N","MN2:G-MP2:G"], 5
["PO","A","MN3:G-MP3:G"], 6
["M1","A","MN0:S-MP0:S"], 7
["M1","A","MP0:S-|--MP3:G"] 8
]
}
(a) } (c)
MN3 6 MP3
1 8
MN2 5 MP2
N
1
2
MN1 4 MP1
P 3
EO
MN0 MP0
EI 7 CK
V SS V DD
OD CO PO M1 M2 M3 M4
(d)
The implementation is the SPICE netlist, and the object definition

file (JSON) and the rule file.
What I really like is the fact that the compilation could generate
GDSII or SKILL, or these days, Xschem schematics and Magic
layout.
Architecture Implementation Compilation

Hand Analysis SPICE netlist
Schematic Initial netlist Object definition file Compiler
Testbench Technology file
Simulation GDSII SKILL
Physical Simulation Initial Loading

Compiled cells
verification Visual
visual SKILL into
Testbench LVS DRC inspection Cadence
inspection (seconds) Virtuoso
(minutes)
Parasitic netlist
Compiled schematics and layout (OpenAccess database)
The cool thing with a compiled ADC is that it’s easy to port
between technologies. Since the original ADC, I’ve ported the ADC
to multiple closed PDKs (22 nm FDSOI, 22 nm, 28 nm, 55 nm, 65
nm and 130nm). In the summer of 2022 I made an open source

port to skywater 130nm.
SUN_SAR9B_SKY130NM
IEEE Asian Solid-State Circuits Conference

November 4 – 6, 2019
One of my Ph.D students
Thebuilt on-top
Parisian on Macao
Macao, my work,SAR,and made a
China
noise-shaped compiled SAR ADC, shown below, more on that
later.
TF|0→BW -27.8 dB
Fig. 3. Die photo and ADC layout.
−1 −2
2)z +z
+ (a2 − a1 + 1)z −2 13.1.2 High Corrected
resolutionon-chip:FOM Corrected offline:
SNDR 68.2 dB Uncal. Cal.
SNR 68.3 dB SNDR 64.3 dB 67.7 dB
For high-resolution
SFDR ADCs,
84.6 dB it’s more common
SFDR 69.6todBuse the
83.9 dB Schreier
0 0
e SNDR
transfer
68.2function.
dB
figure of-25merit, which can also be found in Uncal.
Cal.
Power [dBFS]
Power [dBFS]
SNR 68.3 dB -25

SFDR 84.6 dB Cal.
-50 -50
B. Murmann,
ive solution because -75
ADC Performance Survey
-75
1997-2022 (ISSCC & VLSI
d or resampled. Symposium)
-100 -100
10k 100k 1M 5M 20M 10k 100k 1M 5M 20M
ULTS Frequency [Hz] Frequency [Hz]
m FDSOI, and Fig. 3 (a) (b)

ns. The entire region Fig. 4. Measured results and power spectrums: (a): On-chip correction, (b):
netlist, rule file, and offline correction. The power spectra have 212 bins from DC to fs /2.
piler presented in [7].
The Walden figure of merit assumes that thermal noise does not
constrain the power consumption of the ADC, which is usually
true for low-to-medium resolution ADCs. To keep the Walden
FOM you can double the power for a one-bit increase in ENOB.
If the ADC is limited by thermal noise, however, then you must
quadruple the capacitance (reduce 𝑘𝑇/𝐶 noise power) for each
1-bit ENOB increase. Accordingly, the power must also go up four
times.
For higher resolution ADC the power consumption is set by thermal

noise, and the Schreier FOM allows for a 4x power consumption
increase for each added bit.
𝑓𝑠 /2

𝐹𝑂 𝑀𝑆 = 𝑆𝑁 𝐷𝑅 + 10 log
𝑃
Above 180 dB is extreme
190
ISSCC 2021
VLSI 2021
180 ISSCC 1997-2020
VLSI 1997-2020
Envelope
170
FOMS,hf [dB]
160
150
140
130
120
1.E+02 1.E+04 1.E+06 1.E+08 1.E+10 1.E+12
fsnyq [Hz]
13.2 Quantization
Sampling turns continuous time into discrete time. Quantization

turns continuous value into discrete value. Any complete ADC is
always a combination of sampling and quantization.
In our mathematical drawings of quantization we often define 𝑦[𝑛]

as the output, the quantized signal, and 𝑥[𝑛] as the discrete time,
continuous value input, and we add some “noise”, or “quantization
noise” 𝑒[𝑛], where 𝑥[𝑛] = 𝑦[𝑛] − 𝑒[𝑛].
13.2 Quantization 205
a
XD y
een
gEn
XED o
It
Maybe you’ve even heard the phrase “Quantization noise is white”

or “Quantization noise is a random Gaussian process”?
É
I’m here to tell you that you’ve been lied to. Quantization noise is
not white, nor is it a Gaussian process. Those that have lied to you
may say “yes, sure, but for high number of bits it can be considered
white noise”. I would say that’s similar to saying “when you look at
the earth from the moon, the surface looks pretty smooth without
bumps, so let’s say the earth is smooth with no mountains”.
I would claim that it’s an unnecessary simplification. It’s obvious

to most that the earth would appear smooth from really far away,
but they would not be surprised by Mount Everest, since they d a
y
x
know it’s not smooth. An Alien that has been told that the earth is
smooth, would be surprised to see Mount Everest.
But if Quantization noise is not white, what is it?
The figure below shows the input signal x and the quantized signal
y.
É
a
XD y
I 1 i t t t t t t t
En EBI
g
een
TIFFT
It
Else I
É
To see the quantization noise, first take a look at the sample and
held version of 𝑥 in green in the figure below. The difference
between the green ( 𝑥 at time n) and the red ( 𝑦 ) would be our
quantization noise 𝑒
d noise is contained between + 12 Least
a Significant
y
x
The quantization
1
Bit (LSB) and − 2 LSB.
É
This noise does not look random to me, but I can’t see what it is,
and I’m pretty sure I would not be able to work it out either.
d a
y
x
I 1 i t t t t t t t
EBI
een
Else I
TIFFT
Luckily, there are people in this world that love mathematics,
and that can delve into the details and figure out what 𝑒[𝑛] is. A
guy called Blachman wrote a paper back in 1985 on quantization
noise.
See The intermodulation and distortion due to quantization of

sinusoids for details
In short, quantization noise is defined as
∞
X
𝑒 𝑛 (𝑡) = 𝐴 𝑝 sin 𝑝𝜔𝑡
𝑝=1
where p is the harmonic index, and
( P∞
𝛿 𝑝1 𝐴 + 𝑚=1 𝑚𝜋 𝐽𝑝 (2𝑚𝜋𝐴)
2
, 𝑝 = odd
𝐴𝑝 =
0 , 𝑝 = even
(
1 ,𝑝 =1
𝛿 𝑝1
0 ,𝑝 ≠1
and
𝐽𝑝 (𝑥)
is a Bessel function of the first kind, A is the amplitude of the input
signal.
If we approximate the amplitude of the input signal as
2𝑛 − 1
𝐴= ≈ 2𝑛−1
2
where n is the number of bits, we can rewrite as
∞
X
𝑒 𝑛 (𝑡) = 𝐴 𝑝 sin 𝑝𝜔𝑡
𝑝=1
∞
2
𝐴 𝑝 = 𝛿 𝑝 1 2𝑛−1 + 𝐽𝑝 (2𝑚𝜋2𝑛−1 ), 𝑝 = 𝑜𝑑𝑑
X
𝑚=1 𝑚𝜋
Obvious, right?
I must admit, it’s not obvious to me. But I do understand the

implications. The quantization noise is an infinite sum of input
signal odd harmonics, where the amplitude of the harmonics is
determined by a sum of a Bessel function.
A Bessel function of the first kind looks like this
So I would expect the amplitude to show signs of oscillatory

behavior for the harmonics. That’s the important thing to remember.
The quantization noise is odd harmonics of the input signal
The mean value is zero
𝑒 𝑛 (𝑡) = 0
and variance (mean square, since mean is zero), or noise power,

can be approximated as
Δ2
𝑒 𝑛 (𝑡)2 =
12
13.2.1 Signal to Quantization noise ratio
Assume we wanted to figure out the resolution, or effective number

of bits for an ADC limited by quantization noise. A power ratio, like
signal-to-quantization noise ratio (SQNR) is one way to represent
resolution.
Take the signal power, and divide by the noise power
𝐴2 /2 6 𝐴2

𝑆𝑄𝑁 𝑅 = 10 log 2 = 10 log
Δ /12 Δ2
2𝐴
Δ=
2𝐵
6 𝐴2

𝑆𝑄𝑁 𝑅 = 10 log = 20𝐵 log 2 + 10 log 6/4
4𝐴2 /2𝐵
𝑆𝑄𝑁 𝑅 ≈ 6.02𝐵 + 1.76
You may have seen the last equation before, now you know where
it comes from.
13.2.2 Understanding quantization
Below I’ve tried to visualize the quantization process q.py.
The left most plot is a sinusoid signal and random Gaussian noise.
The signal is not a continuous time signal, since that’s not possible
on a digital computer, but it’s an approximation.
The plots are FFTs of a sinusoidal signal combined with noise.

These are complex FFTs, so they show both negative and positive
frequencies. The x-axis is the FFT bin (not the frequency). Notice
that there are two spikes, which should not be surprising, since a
sinusoidal signal is a combination of two frequencies.
𝑒 𝑖𝑥 − 𝑒 −𝑖𝑥
𝑠𝑖𝑛(𝑥) =
2𝑖
The second plot from the left is after sampling, notice that the noise
level increases. The increase in the noise level should be due to
noise folding, and reduced number of points in the FFT, but I have
not confirmed (maybe you could confirm?).
The right plot is after quantization, where I’ve used the function
below.
def adc(x,bits):
levels = 2**bits
y = np.round(x*levels)/levels
return y
I really need you to internalize a few things from the right most
plot. Really think through what I’m about to say.
Can you see how the noise (what is not the two spikes) is not white?
White noise would be flat in the frequency domain, but the noise
is not flat.
0 0 0
1-bit
f =127
20 20 20
40 40 40
60 60 60
Frequency Domain
80 80 80
100 100 100
120 120 120
140 140 140
160 160 160

4000 2000 0 2000 4000 1000 500 0 500 1000 1000 500 0 500 1000
Continuous time, continuous value Discrete time, continuous value Discrete time, Discrete value
If you run the python script you can zoom in and check the highest
spikes. The fundamental is at 127, so odd harmonics would be
381, 635, 889, and from the function of the quantization noise we
would expect those to be the highest harmonics (at least when we
look at the Bessel function), however, we can see that it’s close, but
that bin 396 is the highest. Is the math’s wrong?
No, the math is correct. Never bet against mathematics. If you

change the python script to reduce the frequency, fdivide=2**9,
and increase number of points, N=2**16, as in the plot below, you’ll
see it’s the 11’th harmonic that is highest.
All the other spikes are the odd harmonics above the sample rate
that fold. The infinite sum of harmonics will fold, some in-phase,
some out of phase, depending on the sign of the Bessel function.
From the function for the amplitude of the quantization noise for
harmonic indices higher than 𝑝 = 1
∞
2
𝐽𝑝 (2𝑚𝜋2𝑛−1 ), p=odd
X
𝐴𝑝 =
𝑚=1 𝑚𝜋
we can see that the input to the Bessel function increases faster
for a higher number of bits 𝑛 . As such, from the Bessel function
figure above, I would expect that the sum of the Bessel function
is a lower value. Accordingly, the quantization noise reduces at
higher number of bits.
A consequence is that the quantization noise becomes more and

more uniform, as can be seen from the plot of a 10-bit quantizer be-
low. That’s why people say “Quantization noise is white”, because
for a high number of bits, it looks white in the FFT.
13.3 Oversampling 211
0 0 0
10-bit
f =127
20 20 20
40 40 40
60 60 60
Frequency Domain
80 80 80
100 100 100
120 120 120
140 140 140
160 160 160

4000 2000 0 2000 4000 1000 500 0 500 1000 1000 500 0 500 1000
Continuous time, continuous value Discrete time, continuous value Discrete time, Discrete value
13.2.3 Why you should care about quantization noise
So why should you care whether the quantization noise looks white,
or actually is white? A class of ADCs called oversampling and
sigma-delta modulators rely on the assumption that quantization
noise is white. In other words, the cross-correlation between noise
components at different time points is zero. As such the noise power
sums as a sum of variance, and we can increase the signal-to-noise
ratio.
We know that assumption to be wrong though, quantization noise

is not white. For noise components at harmonic frequencies the
cross-correlation will be high. As such, when we design oversam-
pling or sigma-delta based ADC we will include some form of
dithering (making quantization noise whiter). For example, before
the actual quantizer we inject noise, or we make sure that the
thermal noise is high enough to dither the quantizer.
Everybody that thinks that quantization noise is white will design

non-functioning (or sub-optimal) oversampling and sigma-delta
ADCs. That’s why you should care about the details around
quantization noise.
13.3 Oversampling
Assume a signal 𝑥[𝑛] = 𝑎[𝑛] + 𝑏[𝑛] where 𝑎 is a sampled sinusoid

and 𝑏 is a random process where cross-correlation is zero for any
time except for 𝑛 = 0. Assume that we sum two (or more) equally
spaced signal components, for example
𝑦 = 𝑥[𝑛] + 𝑥[𝑛 + 1]
What would the signal to noise ratio be for 𝑦 ?
13.3.1 Noise power
Our mathematician friends have looked at this, and as long the

noise signal 𝑏 is random then the noise power for the oversampled
signal 𝑏 𝑜𝑠𝑟 = 𝑏[𝑛] + 𝑏[𝑛 + 1] will be
𝑏 2𝑜𝑠𝑟 = 𝑂𝑆𝑅 × 𝑏 2
where OSR is the oversampling ratio. If we sum two time points

the 𝑂𝑆𝑅 = 2, if we sum 4 time points the 𝑂𝑆𝑅 = 4 and so on.
For fun, let’s go through the mathematics
Define 𝑏 1 = 𝑏[𝑛] and 𝑏 2 = 𝑏[𝑛 + 1] and compute the noise power
(𝑏1 + 𝑏2 )2 = 𝑏12 + 2𝑏 1 𝑏2 + 𝑏22
Let’s replace the mean with the actual function
𝑁
1 X
𝑏12 + 2𝑏1 𝑏2 + 𝑏22

𝑁 𝑛=0
which can be split up into
𝑁 𝑁 𝑁
1 X 1 X 1 X
𝑏12 + 2𝑏 1 𝑏 2 + 𝑏2
𝑁 𝑛=0 𝑁 𝑛=0 𝑁 𝑛=0 2
we’ve defined the cross-correlation to be zero, as such
𝑁 𝑁
1 X 1 X
(𝑏1 + 𝑏2 )2 = 𝑏12 + 𝑏 2 = 𝑏12 + 𝑏22
𝑁 𝑛=0 𝑁 𝑛=0 2
but the noise power of each of the 𝑏 ’s must be the same as 𝑏 , so
(𝑏1 + 𝑏2 )2 = 2𝑏 2
13.3 Oversampling 213
13.3.2 Signal power
For the signal 𝑎 we need to calculate the increase in signal power

as OSR increases.
I like to think about it like this. 𝑎 is low frequency, as such, samples

𝑛 and 𝑛 + 1 is pretty much the same value. If the sinusoid has
an amplitude of 1, then the amplitude would be 2 if we sum two
samples. As such, the amplitude must increase with the OSR.
The signal power of a sinusoid is 𝐴2 /2, accordingly, the signal

power of an oversampled signal must be (𝑂𝑆𝑅 × 𝐴)2 /2.
13.3.3 Signal to Noise Ratio
Take the signal power to the noise power
(𝑂𝑆𝑅 × 𝐴)2 /2 𝐴2 /2
= 𝑂𝑆𝑅 ×
𝑂𝑆𝑅 × 𝑏 2 𝑏2
We can see that the signal to noise ratio increases with increased
oversampling ratio, as long as the cross-correlation of the noise
is zero
13.3.4 Signal to Quantization Noise Ratio
The in-band quantization noise for a oversampling ratio (OSR)
Δ2
𝑒 𝑛 (𝑡)2 =
12𝑂𝑆𝑅
And the improvement in SQNR can be calculated as
6 𝐴2 6 𝐴2

𝑆𝑄𝑁 𝑅 = 10 log 2 = 10 log + 10 log(𝑂𝑆𝑅)
Δ /𝑂𝑆𝑅 Δ2
𝑆𝑄𝑁 𝑅 ≈ 6.02𝐵 + 1.76 + 10 log(𝑂𝑆𝑅)
For an OSR of 2 and 4 the SQNR improves by
10 log(2) ≈ 3 𝑑𝐵
and for OSR=4

10 log(4) ≈ 6 𝑑𝐵
which is roughly equivalent to a 0.5-bit per doubling of OSR
13.3.5 Python oversample
There are probably more elegant (and faster) ways of implementing

oversampling in python, but I like to write the dumbest code I can,
simply because dumb code is easy to understand.
Below you can see an example of oversampling. The oversample

function takes in a vector and the OSR. For each index it sums OSR
future values.
def oversample(x,OSR):
N = len(x)
y = np.zeros(N)
for n in range(0,N):
for k in range(0,OSR):
m = n+k
if (m < N):
y[n] += x[m]
return y
Below we can see the plot for OSR=2, the right most plot is the
oversampled version.
The noise has all frequencies, and it’s the high frequency compo-
nents that start to cancel each other. An average filter (sometimes
called a sinc filter due to the shape in the frequency domain) will
have zeros at ± 𝑓 𝑠/2 where the noise power tends towards zero.
0 0 0 0
10-bit OSR=2
20 20 20 20
40 40 40 40
60 60 60 60
Frequency Domain
80 80 80 80
100 100 100 100
120 120 120 120
140 140 140 140
160 160 160 160

0 2000 4000 6000 8000 0 500 1000 1500 2000 0 500 1000 1500 2000 0 500 1000 1500 2000
Continuous time, continuous value Discrete time, continuous value Discrete time, Discrete value Oversampled
13.4 Noise Shaping 215
The low frequency components will add, and we can notice how
the noise power increases close to the zero frequency (middle of
the x-axis).
For an OSR of 4 we can notice how the noise floor has 4 zero’s.
0 0 0 0
10-bit OSR=4
20 20 20 20
40 40 40 40
60 60 60 60
Frequency Domain
80 80 80 80
100 100 100 100
120 120 120 120
140 140 140 140
160 160 160 160

0 2000 4000 6000 8000 0 500 1000 1500 2000 0 500 1000 1500 2000 0 500 1000 1500 2000
Continuous time, continuous value Discrete time, continuous value Discrete time, Discrete value Oversampled
The code for the plots is osr.py. I would encourage you to play a
bit with the code, and make sure you understand oversampling.
13.4 Noise Shaping
Look at the OSR=4 plot above. The OSR=4 does decrease the noise
compared to the discrete time discrete value plot, however, the
noise level of the discrete time continuous value is much lower.
What if we could do something, add some circuitry, before the

quantization such that the quantization noise was reduced?
That’s what noise shaping is all about. Adding circuits such that we
can “shape” the quantization noise. We can’t make the quantization
noise disappear, or indeed reduce the total noise power of the
quantization noise, but we can reduce the quantization noise power
for a certain frequency band.
But what circuitry can we add?
13.4.1 The magic of feedback
A generalized feedback system is shown below, it could be a

regulator, a unity-gain buffer, or something else.
The output 𝑉𝑜 is subtracted from the input 𝑉𝑖 , and the error 𝑉𝑥 is

shaped by a filter 𝐻(𝑠).
If we make 𝐻(𝑠) infinite, then 𝑉𝑜 = 𝑉𝑖 . If you’ve never seen such a

circuit, you might ask “Why would we do this? Could we not just
use 𝑉𝑖 directly?”. There are many reasons for using a circuit like
this, let me explain one instance.
Imagine we have a VDD of 1.8 V, and we want to make a 0.9 V

voltage for a CPU. The CPU can consume up to 10 mA. One way to
make a divide by two circuit is with two equal resistors connected
between VDD and ground. We don’t want the resistive divider to
consume a large current, so let’s choose 1 MOhm resistors. The
current in the resistor divider would then be about 1 𝜇A. We can’t
connect the CPU directly to the resistor divider, the CPU can draw
10 mA. As such, we need a copy of the voltage at the mid-point of
the resistor divider that can drive 10 mA.
Do you see now why a circuit like the one below is useful? If not,
you should really come talk to me so I can help you understand.
VI VX Hcs V0
Ux Vo VxHCS
VI Vo
VI Vo E
YE
VI V
13.4.2 Sigma-delta principle
Hes ADC DAC
Do
Let’s modify the feedback circuit into the one below. I’ve added
an ADC and a DAC to the feedback loop, and the 𝐷𝑜 is now the
output we’re interested in. The equation for the loop would be
𝐷𝑜 = 𝑎𝑑𝑐 [𝐻(𝑠) (𝑑𝑎𝑐(𝐷𝑜 ) − 𝑉𝑖 )]
But how can we now calculate the transfer function 𝐷 𝑉𝑖 ? Both 𝑎𝑑𝑐
𝑜
and 𝑑𝑎𝑐 could be non-linear functions, so we can’t disentangle the

equation. Let’s make assumptions.
Ux Vo VxHCS
VI Vo
VI Vo E 13.4 Noise Shaping 217
YE
VI V
Hes ADC DAC
Do
13.4.2.1 The DAC assumption
Assumption 1: the 𝑑𝑎𝑐 is linear, such that 𝑉𝑜 = 𝑑𝑎𝑐(𝐷𝑜 ) = 𝐴𝐷𝑜 + 𝐵,

where 𝐴 and 𝐵 are scalar values.
The DAC must be linear, otherwise our noise-shaping ADC will

not work.
One way to force linearity is to use a 1-bit DAC, which has only
two points, so should be linear. For example
𝑉𝑜 = 𝐴 × 𝐷𝑜
, where 𝐷𝑜 ∈ (0 , 1). Even a 1-bit DAC could be non-linear if 𝐴 is

time-variant, so 𝑉𝑜 [𝑛] = 𝐴(𝑡) × 𝐷𝑜 [𝑛], this could happen if the
reference voltage for the DAC changed with time.
I’ve made a couple noise shaping ADCs, and in the first one I
made I screwed up the DAC. It turned out that the DAC current
had a signal dependent component which lead to a non-linear
behavior.
13.4.2.2 The ADC assumption
Assumption 2: the 𝑎𝑑𝑐 can be modeled as a linear function 𝐷𝑜 =

𝑎𝑑𝑐(𝑥) = 𝑥 + 𝑒 , where e is white noise source
We’ve talked about this, the 𝑒 is not white, especially for low-bit
ADCs, so we usually have to add noise. Sometimes it’s sufficient
with thermal noise, but often it’s necessary to add a random, or
pseudo-random noise source at the input of the ADC.
13.4.2.3 The modified equation
With the assumptions we can change the equation into
𝐷𝑜 = 𝑎𝑑𝑐 [𝐻(𝑠) (𝑉𝑖 − 𝑑𝑎𝑐(𝐷𝑜 ))] = 𝐻(𝑠) (𝑉𝑖 − 𝐴𝐷𝑜 ) + 𝑒

In B Pn
axhxxx.MX
In B Paz
In noise-shaping texts it’s common to write the above equation
l
as
𝑦 = 𝐻(𝑠)(𝑢 − 𝑦) + 𝑒
PSD
tf
or in2the sample domain
tf
𝑦[𝑛] = 𝑒[𝑛] + ℎ ∗ (𝑢[𝑛] − 𝑦[𝑛])
which could be drawn in a signal flow graph as below.
to yen
I o Ha
in the Z-domain the equation would turn into
YET𝑌(𝑧)een
= 𝐸(𝑧) + 𝐻(𝑧)HA UET
[𝑈(𝑧) − 𝑌(𝑧)] YET
YG ECz HE UG 4
The whole point of this exercise was to somehow shape the zquan-
tization noise, and we’re almost at the point, but to show how it
ECHO
works we need to look at the transfer function for the signal 𝑈 and
for the noise 𝐸 .
y HU HY
t
13.4.3STF
Signal transfer function
Assume U and E are uncorrelated, and E is zero
𝑌 = 𝐻𝑈 − 𝐻𝑌
𝑌 𝐻 1
𝑆𝑇𝐹 = = =
𝑈 1+𝐻 1 + 𝐻1
Imagine what will happen if H is infinite. Then the signal transfer

function (STF) is 1, and the output 𝑌 is equal to our input 𝑈 . That’s
exactly what we wanted from the feedback circuit.
13.5 First-Order Noise-Shaping 219
13.4.4 Noise transfer function
Assume U is zero
1
𝑌 = 𝐸 + 𝐻𝑌 → 𝑁𝑇𝐹 =
1+𝐻
Imagine again what happens when H is infinite. In this case the

noise-transfer function becomes zero. In other words, there is no
added noise.
13.4.5 Combined transfer function
In the combined transfer function below, if we make 𝐻(𝑧) infinite,

then 𝑌 = 𝑈 and there is no added quantization noise. I don’t
know how to make 𝐻(𝑧) infinite everywhere, so we have to choose
at what frequencies it’s “infinite”.
𝑌(𝑧) = 𝑆𝑇𝐹(𝑧)𝑈(𝑧) + 𝑁𝑇𝐹(𝑧)𝐸(𝑧)
There are a large set of different 𝐻(𝑧) and I’m sure engineers
will invent new ones. We usually classify the filters based on the
number of zeros in the NTF, for example, first-order (one zero),
second order (two zeros) etc. There are books written about sigma-
delta modulators, and I would encourage you to read those to
get a deeper understanding. I would start with Delta-Sigma Data
Converters: Theory, Design, and Simulation.
13.5 First-Order Noise-Shaping
We want an infinite 𝐻(𝑧). One way to get an infinite function is an

accumulator, for example
𝑦[𝑛 + 1] = 𝑥[𝑛] + 𝑦[𝑛]
or in the Z-domain
𝑧𝑌 = 𝑋 + 𝑌 → 𝑌(𝑧 − 1) = 𝑋
which has the transfer function
1
𝐻(𝑧) =
𝑧−1
The signal transfer function is
1/(𝑧 − 1) 1
𝑆𝑇𝐹 = = = 𝑧 −1
1 + 1/(𝑧 − 1) 𝑧
and the noise transfer function
1 𝑧−1
𝑁 𝐹𝑇 = = = 1 − 𝑧 −1
1 + 1/(𝑧 − 1) 𝑧
In order calculate the Signal to Quantization Noise Ratio we need to

have an expression for how the NTF above filters the quantization
noise.
In the book they replace the 𝑧 with the continuous time variable
𝑠=𝑗𝜔
𝑧 = 𝑒 𝑠𝑇 → 𝑒 𝑗𝜔𝑇 = 𝑒 𝑗 2𝜋 𝑓 / 𝑓𝑠
inserted into the NTF we get the function below.
𝑁𝑇𝐹( 𝑓 ) = 1 − 𝑒 −𝑗 2𝜋 𝑓 / 𝑓𝑠
𝑒 𝑗𝜋 𝑓 / 𝑓𝑠 − 𝑒 −𝑗𝜋 𝑓 / 𝑓𝑠
= × 2 𝑗 × 𝑒 −𝑗𝜋 𝑓 / 𝑓𝑠
2𝑗
𝜋𝑓
= sin × 2 𝑗 × 𝑒 −𝑗𝜋 𝑓 / 𝑓𝑠
𝑓𝑠
The arithmetic magic is really to extract the 2 𝑗 × 𝑒 −𝑗𝜋 𝑓 / 𝑓𝑠 from the

first expression such that the initial part can be translated into a
sinusoid.
When we take the absolute value to figure out how the NTF changes
with frequency the complex parts disappears (equal to 1)
𝜋𝑓

|𝑁 𝐹𝑇( 𝑓 )| = 2 sin
𝑓𝑠
The signal power for a sinusoid is
𝑃𝑠 = 𝐴2 /2
The in-band noise power for the shaped quantization noise is

13.5 First-Order Noise-Shaping 221
𝑓0 2
Δ2 1 𝜋𝑓
∫
𝑃𝑛 = 2 sin 𝑑𝑡
− 𝑓0 12 𝑓𝑠 𝑓𝑠
and with a bunch of tedious maths, we can get to the conclusion
..
.
𝑆𝑄𝑁 𝑅 = 6.02𝐵 + 1.76 − 5.17 + 30 log(𝑂𝑆𝑅)
If we compare to pure oversampling, where the SQNR improves by

10 log(𝑂𝑆𝑅), a first order sigma-delta improves by 30 log(𝑂𝑆𝑅).
That’s a significant improvement.
13.5.1 SQNR and ENOB
Below is the signal-to-quantization noise ratio’s for Nyquist up to

second order sigma-delta.
𝑆𝑄𝑁 𝑅 𝑛 𝑦𝑞𝑢𝑖𝑠𝑡 ≈ 6.02𝐵 + 1.76
𝑆𝑄𝑁 𝑅 𝑜𝑣𝑒𝑟𝑠 𝑎𝑚𝑝𝑙𝑒 ≈ 6.02𝐵 + 1.76 + 10 log(𝑂𝑆𝑅)
𝑆𝑄𝑁 𝑅ΣΔ1 ≈ 6.02𝐵 + 1.76 − 5.17 + 30 log(𝑂𝑆𝑅)
𝑆𝑄𝑁 𝑅ΣΔ2 ≈ 6.02𝐵 + 1.76 − 12.9 + 50 log(𝑂𝑆𝑅)
We could compute an effective number of bits, as shown below.
𝐸𝑁 𝑂𝐵 = (𝑆𝑄𝑁 𝑅 − 1.76)/6.02
The table below shows the effective number of bits for oversam-
pling, and sigma-delta modulators. For a 1-bit quantizer, pure
oversampling does not make sense at all. For first-order and second-
order sigma delta modulators, and a OSR of 1024 we can get high
resolution ADCs.
Assume 1-bit quantizer, what would be the maximum ENOB?
OSR Oversampling First-Order Second Order

4 2 3.1 3.9
OSR Oversampling First-Order Second Order

64 4 9.1 13.9
1024 6 15.1 23.9
13.6 Examples
13.6.1 Python noise-shaping
I want to demystify noise-shaping modulators. I think one way to

do that is to show some code. You can find the code at sd_1st.py
Below we can see an excerpt. Again pretty stupid code, and I’m
sure it’s possible to make a faster version (for loops in python are
notoriously slow).
For each sample in the input vector 𝑢 I compute the input to the
quantizer 𝑥 , which is the sum of the previous input to the quantizer
and the difference between the current input and the previous
output 𝑦 𝑠𝑑 .
The quantizer generates the next 𝑦 𝑠𝑑 and I have the option to add
dither.
# u is discrete time, continuous value input

M = len(u)
y_sd = np.zeros(M)
x = np.zeros(M)
for n in range(1,M):
x[n] = x[n-1] + (u[n]-y_sd[n-1])
y_sd[n] = np.round(x[n]*2**bits
+ dither*np.random.randn()/4)/2**bits
The right-most plot is the one with noise-shaping. We can observe

that the noise seems to tend towards zero at zero frequency, as we
would expect. The accumulator above would have an infinite gain
at infinite time (it’s the sum of all previous values), as such, the
NTF goes towards zero at 0 frequency.
If we look at the noise we can also see the non-white quantization

noise, which will degrade our performance. I hope by now, you’ve
grown tired of me harping on the point that quantization noise is
not white
13.6 Examples 223
0 0 0 0
1-bit
20 20 20 20
40 40 40 40
60 60 60 60
Frequency Domain
80 80 80 80
100 100 100 100
120 120 120 120
140 140 140 140

dither=0
160 160 160 160
0 1000 2000 3000 4000 0 250 500 750 1000 0 250 500 750 1000 0 250 500 750 1000
Continuous time, continuous value Discrete time, continuous value Discrete time, Discrete value Noise-shaped
In the figure below I’ve turned on dither, and we can see how the
noise looks “better”, which I know is not a qualitative statement,
but ask anyone that’s done 1-bit quantizers. It’s important to have
enough random noise.
0 0 0 0
1-bit
20 20 20 20
40 40 40 40
60 60 60 60
Frequency Domain
80 80 80 80
100 100 100 100
120 120 120 120
140 140 140 140

dither=1
160 160 160 160
0 1000 2000 3000 4000 0 250 500 750 1000 0 250 500 750 1000 0 250 500 750 1000
Continuous time, continuous value Discrete time, continuous value Discrete time, Discrete value Noise-shaped
In papers it’s common to use a logarithmic x-axis for the power

spectral density, as shown below. In the plot I only show the
positive frequencies of the FFT. From the shape of the quantization
noise we can also see the first order behavior.
20
40
Magnitude [dB20]
60
80
100
120
10 3 10 2 10 1
Normalized frequency
13.6.2 The wonderful world of SD modulators
13.6.2.1 Open-Loop Sigma-Delta
On my Ph.D I did some work on
Resonators in Open-Loop Sigma-Delta Modulators
which was a pure theoretical work. The idea was to use modulo
integrators (local control of integrator output swing) in front of
large latency multi-bit quantizers to achieve a high SNR.
The plot below shows a fifth order NFT where there are two
complex conjugate zeros, and a zero at zero frequency. With a
higher order filter one can use a lower OSR, and still achieve high
ENOB.
13.6 Examples 225
A=−3dB ENOB=13.8 SNDR=84.9dB M=32768

0
−20
−40
−60
Magnitude [dB]
−80
−100
−120
−140
−160
Output
Bandwidth
−180
−4 −3 −2 −1
10 10 10 10
Normalized Frequency, fs = 1
13.6.2.2 Noise Shaped SAR
One of my Ph.d students made a
A 68 dB SNDR Compiled Noise-Shaping SAR ADC With On-Chip

CDAC Calibration
In a SAR ADC, once the bit-cycling is complete, the analog value

on the capacitors is the actual quantization error. That error can
be fed to a loop filter, H(z), and amplified in the next conversion,
accordingly a combination of SAR and noise-shaping.
In the paper the SD modulator was also used to calibrate the

non-linearity in the CDAC, as the MSB capacitor won’t be exactly
N times larger than the smallest capacitor.
The loop filter was a switched cap loop filter, and we can see the
NTF below. The first OTA made use of chopping to reduce the
offset.
13.6.2.3 Control-Bounded ADCs
One of my current Ph.D students is working an even more advanced

type of sigma-delta ADC. Actually, it’s more a super-set of SD
ADCs called control-bounded ADCs.
Design Considerations for a Low-Power Control-Bounded A/D

Converter
A block diagram of a Leapfrog ADC version of a control-bounded

ADC is shown below.
Here we’re walking into advanced maths territory, but to simplify,

I think it’s correct to say that a control-bounded ADC seeks to
control the local analog state, 𝑥 𝑛 (𝑡) such that no voltage is saturated.
The digital control signals 𝑠 𝑛 (𝑡) are used to infer the state of the
input 𝑢(𝑡) using a form of Bayesian Statistics.
13.6 Examples 227
High-Level Architecture
↵2 ↵3 ··· ↵N
1
x1 (t) 2
x2 (t) 3
x3 (t) N
xN (t)
u(t) + s+⇢1 + s+⇢2 + s+⇢3
··· + s+⇢N
1 fclk 2 fclk 3 fclk N fclk
< < < <
Design Considerations
s (t) s2 (t) s3 (t) sN (t)
1
Figure 3.1: The general structure of the Leapfrog ADC
by A0i = i/⇢i .
Below we can see a power spectral density plot of the ADC, and
The Leapfrog ADC di↵ers from the Chain-of-integrators by the addi-
we can feedback
tional observe how
pathsthe quantization
between noisestates.
neighboring is shaped. I think it’s
The feedback from xi
ato
third order NTF with a zero at zero frequency and a complex
xi 1 is achieved through ↵i , feeding a portion of xi back to the input of
integratorpole
conjugate (i at
1).8Each integrator is stabilized by a local digital control,
MHzish.
which is represented by a clocked comparator in figure 3.1. The output of
comparator i is the control-contribution si (t) which is scaled by a factor
i before entering the integrator input.
0
û(t)
3.2 20
Parametrization NTF
40 of the state vector is described by
The evolution
60 ẋ(t) = Ax(t) + Bu(t) + s(t), (3.1)

PSD [dB]
where 0 1
80 ⇢1 1 ↵2
B 2 ⇢2 2 ↵3 C
B C
100 A = B
B ⇢3
... C
C, (3.2)
3
B .. .. C
@ . . 1 ↵N
A
120 N
N ⇢N
140
T
B= 1 ··· 0 , (3.3)
and 160 0 1
5 1 6
10 B
1
10
.. C 107
=@ . A. (3.4)
Frequency [Hz]
N N
Figure 5.6:local
For this Estimated PSD oftheû(t)
digital control, plotted
control together
observation s̃(t)with corresponding
coincides with
theoretical NTF. Obtained from an ideal circuit simulation
the state vector x(t) meaning that the control observation matrix of a˜4th
T
= order
Leapfrog ADC with LNA driven, passive integrator and floating-gate
voltage
13.6.2.4summation
Complex Sigma-Delta 22
There are cool sigma-delta modulators with crazy configurations

and that may look like an exercise in “Let’s make something
complex”, however, most of them have a reasonable application.
One example is the one below for radio recievers

58
13.6.2.5 My first Sigma-Delta
The first sigma-delta modulator I made in “real-life” was similar

to the one shown below.
The input voltage is translated into a current, and the current is

integrated on capacitor 𝐶 . The 𝑅 𝑜 𝑓 𝑓 𝑠𝑒𝑡 is to change the mid-level
voltage, while 𝑅 𝑟𝑒 𝑓 is the 1-bit feedback DAC. The comparator is
the quantizer. When the clock strikes the comparator compares the
𝑉𝑜 and 𝑉𝑟𝑒 𝑓 /2 and outputs a 1-bit digital output 𝐷
The complete ADC is operated in a “incremental mode”, which is

a fancy way of saying
Reset your sigma-delta modulator, run the sigma delta

modulator for a fixed number of cycles (i.e 1024), and
count the number of ones at 𝐷
The effect of an “incremental mode” is to combine the modulator

and a output filter so the ADC appears to be a slow Nyquist
ADC.
For more information, ask me, or see the patent at Analogue-to-

digital converter
The design of sigma-delta modulation analog-to-digital convert-

ers
Delta-sigma modulation in fractional-N frequency synthesis
A CMOS Temperature Sensor With a Voltage-Calibrated Inaccuracy

of ± 0.15 C (3sigma) From -55 Cto 125 C
A 20-mW 640-MHz CMOS Continuous-Time Sigma-Delta ADC

With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit
ENOB
A Micro-Power Two-Step Incremental Analog-to-Digital Con-

verter
Voltage regulation 14
14.1 Voltage source . . . 231
14.1.1 Core voltage . . . . . 235
14.1.2 IO voltage . . . . . . 236
Keywords: Battery, Vreg, LDOP, LDON, Flipped voltage follower, 14.1.3 Supply planning . . 236
Buck, Boost, Load, Line, PSRR, MAX C, Quiescent, Settling, Effi-
14.2 Linear Regulators . 237
ciency, PWM, PFM 14.2.1 PMOS pass-fet . . . 237
14.2.2 NMOS pass-fet . . . 239
14.2.3 Control of pass-fet . 239
14.3 Switched Regulators 241
14.3.1 Principles of
switched regula-
tors . . . . . . . . . . 242
14.1 Voltage source 14.3.2 Inductive DC/DC
converter details . . 245
14.3.3 Pulse width modula-
tion (PWM) . . . . . 246
14.3.4 Real world use . . . 248
14.3.5 Pulsed Frequency
Most, if not all, integrated circuits need a supply and ground to Mode (PFM) . . . . . 249
work. 14.4 Want to learn more? 252
14.4.1 Linear regulators . . 252
14.4.2 DC-DC converters . 252
Assume a system is AC powered. Then there will be switched

regulator to turn wall AC into DC. The DC might be 48 V, 24 V, 12
V, 5 V, 3 V 1.8 V, 1.0 V, 0.8 V, or who knows. The voltage depends
on the type of IC and the application.
Many ICs are battery operated, whether it’s your phone, watch,
heart rate monitor, mouse, keyboard, game controller or car.
For batteries the voltage is determined by the difference in Fermi

level on the two electrodes, and the Fermi level (chemical potential)
is a function of the battery chemistry. As a result, we need to know
the battery chemistry in order to know the voltage.
Linden’s Handbook of Batteries is a good book if you want to

dive deep into primary (non-chargeable) or secondary (chargeable)
batteries and their voltage curves.
232 14 Voltage regulation
Some common voltage sources are listed below.
Chemistry Voltage [V]

Primary Cell LiFeS2 , Zn/Alk/MnO2 , LiMnO2 0.8 - 3.6
Secondary Cell Li-Ion 2.5 - 4.3
USB - 4.0 - 6.5 (20)
The battery determines the voltage of the “electron source”, how-

ever, can’t we just run everything directly off the battery? Why do
we need DC to DC converters or voltage regulators?
Turns out, transistors can die.
Today’s transistor, as shown below, are a complicated three dimen-

sional structure. Dimensions are measured in nano-meter, which
14.1 Voltage source 233
makes the transistors fragile.
In Analog Circuit Design in Nanoscale CMOS Technologies Lanny

explains how to design around some of the breakdown effects.
The transistors in a particular technology (from GlobalFoundries,

TSMC, Samsung or others) have a maximum voltage that they can
survive for a certain time. Exceed that time, or voltage, and the
transistors die.
14.1.0.1 Why transistors die
A gate oxide will break due to Time Dependent Dielectric Break-

down (TDDB) if the voltage across the gate oxide is too large. Silicon
oxide can break down at approximately 5 MV/cm. The breakdown
forms a conductive channel from the gate to the channel and is
permanent. After breakdown there will be a resistor of kOhms
between gate and channel.
A similar breakdown phenomena is used in Metal-Oxide RRAM

and the SkyWater ReRAM
Below is an example of ReRAM. In the Pristine state the conduc-

tance is low, resistance is in the hundreds of mega Ohm. In a
transistor we want the oxide to stay high resistive. In ReRAM,
however, we apply a high voltage across the oxide, which forms a
conductive channel across the oxide. Turns out, that the conductive
channel can be flipped back and forth between a high resistive
state, and a low resistive state to store a 1 or a 0 in a non-volatile
manner.
The threshold voltage of a transistor can shift excessively over time

caused by Hot-Carrier Injection (HCI) or Negative Bias Tempera-
ture Instability.
Hot-Carrier injection is caused by electrons, or holes, accelerated

to high velocity in the channel, or drain depletion region , causing
impact ionization (breaking a co-valent bond releasing an elec-
tron/hole pair). At a high drain/source field, and
medium gate/(source or drain) field, the channel minority carriers
can be accelerated to high energy and transition to traps in the
oxide, shifting the threshold voltage.
Negative Bias Temperature Instability is a shift in threshold voltage

due to a physical change in the oxide. A strong electric field across
the oxide for a long time can break co-valent, or ionic bonds, in
the oxide. The bond break will change the forces (stress) in the
amorphous silicon oxide which might not recover. As such, there
might be more traps (states) than before. See Simultaneous Extrac-
tion of Recoverable and Permanent Components Contributing to
Bias-Temperature Instability for more details.
For a long time, I had trouble with “traps in the oxide”“. I had a
hard time visualizing how electrons wandered down the channel
and got caught in the oxide. I was trying to imagine the electric
field, and that the electron needed to find a positive charge in the
oxide to cancel. Diving a bit deeper into quantum mechanics, my
mental image improved a bit, so I’ll try to give you a more accurate
mental model for how to think about traps.
Quantum mechanics tells us that bound electrons can only occupy

fixed states. The probability of finding an electron in a state is given
14.1 Voltage source 235
by the Fermi function, but if there is no energy state at a point in

space, there cannot be an electron there.
For example, there might be a 50 % probability of finding an

electron in the oxide, but if there is no state there, then there will
not be any electron , and thus no change to the threshold voltage.
What happens when we make “traps”, through TDDB, HCI, or

NBTI is that we create new states that can potentially be occupied
by electrons. For example one, or more, broken silicon co-valent
bonds and a dislocation of the crystal lattice.
If the Fermi-Dirac statistics tells us the probability of an electron

being in those new states is 50 %, then there will likely be electrons
there.
The threshold voltage is defined as the voltage at which we can

invert the channel, or create the same density of electrons in the
channel (for NMOS) as density of dopant atoms (density of holes)
in the bulk.
If the oxide has a net negative charge (because of electrons in

new states), then we have to pull harder (higher gate voltage) to
establish the channel. As a result, the threshold voltage increases
with electrons stuck in the oxide.
In quantum mechanics the time evolution, and the complex proba-

bility amplitude of an electron changing state, could, in theory, be
computed with the Schrodinger equation. Unfortunately, for any
real scenario, like the gate oxide of a transistor, using Schrodinger
to compute exactly what will happen is beyond the capability of
the largest supercomputers.
14.1.1 Core voltage
The voltage where the transistor can survive is estimated by the

foundry, by approximation, and testing, and may be like the table
below.
Node [nm] Voltage [V]

180 1.8
130 1.5
55 1.2
22 0.8
14.1.2 IO voltage
Most ICs talk to other ICs, and they have a voltage for the general
purpose input/output. The voltage reduction in I/O voltage does
not need to scale as fast as the core voltage, because foundries have
thicker oxide transistors that can survive the voltage.
Voltage [V]
5.0
3.0
1.8
1.2
14.1.3 Supply planning
For any IC, we must know the application. We must know where
the voltage comes from, the IO voltage, the core voltage, and any
other requirements (like charging batteries).
One example could be an IC that is powered from a Li-Ion battery,

with a USB to provide charging capability.
Between each voltage we need an analog block, a regulator, to

reduce the voltage in an effective manner. What type of regulator
depends again on the application, but the architecture of the analog
design would be either a linear regulator, or a switched regulator.
5 OV
VBUS
BAT O 2.50 4.30
10 1.8 V
IO BIASIANA
In 50m In loom
0.80
CORE
RISC V ADC RADIO
In 50M In Im In 300m
The dynamic range of the power consumed by an IC can be large.

From nA when it’s not doing anything, to hundreds of mA when
there is high computation load.
As a result, it’s not necessarily possible, or effective, to have one

regulator from 1.8 V to 0.8 V. We may need multiple regulators.
14.2 Linear Regulators 237
Some that can handle low load (nA - 𝜇A) effectively, and some that
can handle high loads.
For example, if you design a regulator to deliver 500 mA to the

load, and the regulator uses 5 mA, that’s only 1 % of the current,
which may be OK. The same regulator might consume 5 mA even
though the load is 1 uA, which would be bad. All the current flows
in the regulator at low loads.
Name Voltage Min [nA] Max [mA] PWR DR [dB]

VDD_VBUS 5 10 500 77
VDD_VBAT 4 10 400 76
VDD_IO 1.8 10 50 67
VDD_CORE 0.8 10 350 75
Most product specifications will give you a view into what type of
regulators there are on an IC. The picture below is from nRF5340
(page 23)
14.2 Linear Regulators
14.2.1 PMOS pass-fet
One way to make a regulator is to control the current in a PMOS

with a feedback loop, as shown below. The OTA continuously
adjusts the gate-source voltage of the PMOS to force the input
voltages of the OTA to be equal.
IN W
it
0,8V
TI LOAD
For digital loads, where 𝐼 𝑙𝑜𝑎𝑑 is a digital current, with high current
every rising edge of the clock, it’s an option to place a large external
decoupling capacitor (a reservoir of charge) in parallel with the
load. Accordingly, the OTA would supply the average current.
The device between supply (1.5 V) and output voltage (0.8 V) is

often called a pass-fet. A PMOS pass-fet regulator is often called
for
a LDO, or low dropout regulator, since we only need a 𝑉𝐷𝑆𝑆𝐴𝑇
Dos
across the PMOS, which can be a few hundred mV.
IEE
Key parameters of regulators are
Parameter Description Unit

Load How much does the output voltage change V/A
regulation with load current
Line How much does the output voltage change V/V
regulation with input voltage
Power What is the transfer function from input dB
supply voltage to output voltage? The PSRR at DC is
rejection the line regulation
ratio
Max current How much current can be delivered through A
the pass-fet?
Quiescent What is the current used by the regulator A
current
Settling time How fast does the output voltage settle at a s
current step
14.2 Linear Regulators 239
A disadvantage of a PMOS is the hole mobility, which is lower

than for NMOS. If the maximum current of an LDO is large, then
the PMOS can be big. Maybe even 50 % of the IC area.
14.2.2 NMOS pass-fet
An NMOS pass-fet will be smaller than a PMOS for large loads.

The disadvantage with an NMOS is the gate-source voltage needed.
For some scenarios the needed gate voltage might exceed the input
voltage (1.5 V). A gate voltage above input voltage is possible,
but increases complexity, as a charge pump (switched capacitor
regulator) is needed to make the gate voltage.
Another interesting phenomena with NMOS pass-fet is that the

PSRR is usually better, but we do have a common gate amplifier,
as such, high frequency voltage ripple on output voltage will be
amplified to the input voltage, and may cause issues for others
using the input voltage.
W
1,5
0,8V
I LOAD
II LOAD
14.2.3 Control of pass-fet
The large dynamic range in power management systems can make

it challenging to have a single pass-fet.
The size of the pass-fet is set by the maximum Vgs, and the current
r
that needs to be delivered.
IEEE
Assume we need 500 mA from the LDO. If we assume that the

maximum Vgs is 1.5 V, then we can simulate to try and find a
size.
I’ve made a testbench at
Testbench for LDO pass-fet
Below is an excerpt from the testbench. The pass-fet size has been
determined by iteration.
The OTA in the LDO is modeled by the B source. Notice the use of
the tanh function in order to keep the G voltage within the rails.
* Pass-fet
XM1 OUT G VDD VDD sky130_fd_pr__pfet_01v8 L=0.252 W=11.52 nf=2 ...
* Reference
VREF VREF 0 dc 0.8
* OTA
BOTA G 0 V=(1 + tanh(-1000*(v(vref) -v(out) )))/2*{AVDD}
* Load cap
CL OUT 0 1u
* Current load
ILOAD OUT 0 pwl 0 0 1u 0 50u 0.5
Below is a plot of the current on the y-axis as a function of the Vgs

on the x-axis. Although it’s possible to have almost 6 orders of
magnitude change in current in the transistor it does become hard
to make the loop stable over such a large range.
Sometimes it’s easier to split the range into multiple ranges.

v(il) output_loadreg/loadreg_SchGtKttTtVt.raw
10 1
10 2
10 3
10 4
10 5
0.6 0.8 1.0 1.2 1.4
As such, there are multiple control options for the pass-fet. Below
is a summary of a few methods.
We can control the Vgs, or we can switch the number of instances,

or we can turn the pass-fet on and off dynamically. What we choose
will depend on the application.
1 1 1 DutyCycle
Control
or
ILOAD ILOAD ILOAD
14.3 Switched Regulators
Linear regulator have poor power efficiency. Linear regulators have

Vinthe same current inVoat Vin
the load, as from the input. Voat
For some applications a poor efficiency might be OK, but for most
battery operated systems we’re interested in using the electrons
from the battery in the most effective manner.
Another challenge is temperature. A linear regulator with a 5 V

input voltage, and 1 V output voltage will have a maximum power
efficiency of 20 % (1/5). 80 % of the power is wasted in the pass-fet

as heat.
Imagine a LDO driving an 80 W CPU at 1 V from a 5 V power

supply. The power drawn from the 5 V supply is 400 W, as such,
320 W would be wasted in the LDO. A quad flat no-leads (QFN)
package usually have a thermal resistance of 20 ◦ C/W, so if it
would be possible, the temperature of the LDO would be 6400 ◦ C.
Obviously, that cannot work.
For increased power efficiency, we must use switched regulators.
Imagine a switched regulator with 93 % power efficiency. The

power from the 5 V supply would be 80 W/0.93 = 86 W, as
such, only 6 W is wasted as heat. A temperature increase of
6 W × 20 ◦ C/W = 120◦ C is still high, but not impossible with a
small heat-sink.
All switched regulators are based on devices that store electric

field (capacitors), or magnetic field (inductors).
14.3.1 Principles of switched regulators
There is a big difference between the idea for a cir-

cuit, and the actual implementation. A real DC/DC
implementation may seem overwhelming.
Just look at figure 7 in A 10-MHz 2–800-mA 0.5–1.5-V 90% Peak

Efficiency Time-Based Buck Converter With Seamless Transition
Between PWM/PFM Modes
So before we go into details, let’s have a look at the principles.
14.3.1.1 Inductive BUCK DC/DC
Below is a common illustration of a inductive DC/DC to step down

the voltage.
Imagine Vout is at our desired output voltage, for example 0.8 V.

Assume Vin is 1.8 V.
When we close the switch, the inductor will begin to integrate

the voltage across the inductor, and the current from Vin to Vout
increases.
When we turn off the switch, the inductor current will not stop
immediately, it cannot, that’s what
𝑑𝐼
𝑉=𝐿
𝑑𝑡
1 1 1 DutyCycle
Control
or
tells us. As a result, the current continues, but now the current is
pulled from ground through the diode.
ILOAD ILOAD
Since we’re pulling current from ground, it should be intuitive that
the current from Vin is less than the load current at Vout, assuming
Vin > Vout.
The output voltage can be controlled by how long we turn on the

switch. Each time we turn on the switch the inductor will inject a
charge packet into the load capacitance.
If we have a control loop on the output voltage, then we can get an

output voltage that is independent of the input voltage.
Vin Voat Vin Voat
14.3.1.2 Capacitive BUCK DC/DC
In a capacitive buck below what we’re doing is charging two

capacitors in series to a high voltage, Vin, and then re-configuring
the capacitors to be in parallel.
If the capacitors are the same size, then the output voltage would
be half the input voltage.
To re-configure the circuit we’d use switches.
A disadvantage with capacitive bucks is that the output voltage

is always a factor of the input voltage. When the input voltage
changes, the output voltages changes proportionally.
Often we have to insert an LDO after a capacitive buck to make

the output voltage independent of input voltage.
A A
Vin
3 20in 1 1 1
Vink
DutyCycle
A C C Vin A
Control C
Vin or
B b b b B D
ILOAD ILOAD ILOAD
14.3.1.3 Inductive BOOST DC/DC
Consider the circuit below. Here we setup a current from Vin to

ground when the switch is on. When the switch is off push the
current through the diode, and thus, the Vout can be higher than
Vin.
In a similar manner to the Buck, the output voltage will be impacted

by how long we turn on the switch for.
Vin Voat Vin Voat
14.3.1.4 Capacitive BOOST DC/DC
In a capacitive boost we start with a parallel connection, charge the

capacitors to Vin, then reconfigure the circuit to a series combina-
tion.
As such, the output voltage would be two times the input voltage,
assuming the capacitors are equal.
The configuration below is quite often called a “Charge pump”, and

can be configured to generate both positive, or negative voltages.
A A
Vin
Vin 3 20in Vink
A C C Vin A C
Vin
B b b b B D
14.3.2 Inductive DC/DC converter details
I’ve found that people struggle with inductive DC/DCs. They see
a circuit inductors, capacitors, and transistors and think filters,
Laplace and steady state. The path of Laplace and steady state will
lead you astray and you won’t understand how it works.
Hopefully I can put you on the right path to understanding.
In the figure below we can see a typical inductive switch mode

DC/DC converter. The input voltage is 𝑉𝐷𝐷𝐻 , and the output is
𝑉𝑂 .
Most DC/DCs are feedback systems, so the control will be adjusted
Buch
to force the output to be what is wanted, however, let’s ignore
closed loop for now.
Mott Ex
Vo
Ix C R
Vo
Control B
To see what happens I find the best path to understanding is to

look at the integral equations.
Vx
I Idt
Cdg L
The current in the inductor is given by
V
LEI I
Efrat t T t
t
∫
1
𝐼 𝑥 (𝑡) = 𝑉𝑥 (𝑡)𝑑𝑡
𝐿
and the voltage on the capacitor is given by
∫
1
𝑉𝑜 (𝑡) = (𝐼 𝑥 (𝑡) − 𝐼 𝑜 (𝑡))𝑑𝑡
𝐶
Before you dive into Matlab, Mathcad, Maple, SymPy or another

of your favorite math software, it helps to think a bit.
My mathematics is not great, but I don’t think there is any closed

form solution to the output voltage of the DC/DC, especially since
the state of the NMOS and PMOS is time-dependent.
The output voltage also affect the voltage across the inductor, which
affects the current, which affects the output voltage, etc, etc.
The equations can be solved numerically, but a numerical solution

to the above integrals needs initial conditions.
There are many versions of the control block, let’s look at two.
14.3.3 Pulse width modulation (PWM)
Assume 𝐼 𝑥 = 0 and 𝐼 𝑜 = 0 at 𝑡 = 0. Assume the output voltage

is 𝑉𝑂 = 0. Imagine we set 𝐴 = 1 for a fixed time duration. The
voltage at 𝑉1 = 𝑉𝐷𝐷𝐻 , and 𝑉𝑥 = 𝑉𝑉 𝐷𝐷𝐻 − 𝑉𝑂 . As 𝑉𝑥 is positive,
and roughly constant, the current 𝐼 𝑥 would increase linearly, as
given by the equation of the current above.
Since the 𝐼 𝑥 is linear, then the increase in 𝑉𝑜 would be a second

order, as given by the equation of the output voltage above.
Let’s set 𝐴 = 0 and 𝐵 = 1 for fixed time duration (it does not need
to be the same as duration as we set 𝐴 = 1). The voltage across the
inductor would be 𝑉𝑥 = 0 − 𝑉𝑜 . The output voltage would not have
increased much, so the absolute value of 𝑉𝑥 during 𝐴 = 1 would
be higher than the absolute value of 𝑉𝑥 during the first 𝐵 = 1.
The 𝑉𝑥 is now negative, so the current will decrease, however, since

𝑉𝑥 is small, it does not decrease much.
I’ve made a
Jupyter PWM BUCK model
that numerically solves the equations.
In the figure below we can see how the current during A increases
fast, while during B it decreases little. The output voltage increases
similarly to a second order function.
0.25 Ix
0.20 Io
0.15
0.10
0.05
0.00
0.03
0.02
vo
0.01
0.00
1
A
0
0.00 0.05 0.10 0.15 0.20 0.25
Time [us]
If we run the simulation longer, see plot below, the DC/DC will
start to settle into a steady state condition.
On the top we can see the current 𝐼 𝑥 and 𝐼 𝑜 , the second plot you
can see the output voltage. Turns out that the output voltage will
be
𝑉𝑜 = 𝑉𝑖𝑛 × Duty-Cycle
, where the duty-cycle is the ratio between the duration of 𝐴 = 1

and 𝐵 = 1.
0.6
Ix
Io
0.4
0.2
0.0
1.00
0.75
vo
0.50
0.25
0.00
1
A
0
0 2 4 6 8 10
Time [us]
Once the system has fully settled, see figure below, we can see the
reason for why DC/DC converters are useful.
During 𝐴 = 1 the current 𝐼 𝑥 increases fast, and it’s only during

𝐴 = 1 we pull current from 𝑉𝐷𝐷𝐻 . At the start of 𝐴 = 0 the current
is still positive, which means we pull current from ground. The
average current in the inductor is the same as the average current
in the load, however, the current from 𝑉𝐷𝐷𝐻 is lower than the
average inductor current, since some of the current comes from
ground.
If the DC/DC was 100% efficient, then the current from the 4
V input supply would be 1/4’th of the 1 V output supply. 100%
efficient DC/DC converters violate the laws of nature, as such, we
can expect to get up to 9X% under optimal conditions.
0.06
0.04 Ix
Io
0.02
0.00
0.02
0.04
0.06
0.990
0.989
vo
0.988
0.987
1
A
0
13.60 13.65 13.70 13.75 13.80 13.85 13.90 13.95 14.00
Time [us]
14.3.4 Real world use
DC/DC converters are used when power efficiency is important.

Below is a screenshot of the hardware description in the nRF5340
Product Specification.
We can see 3 inductor/capacitor pairs. One for the “VDDH”, and

two for “DECRF” and “DECD”, as such, we can make a good guess
there are three DC/DC converters inside the nRF5340.
14.3.5 Pulsed Frequency Mode (PFM)
Power efficiency is key in DC/DC converters. For high loads, PWM,

as explained above, is usually the most efficient and practical. For
lighter loads, other configurations can be more efficient.
In PWM we continuously switch the NMOS and PMOS, as such,

the parasitic capacitance on the 𝑉1 node is charged and discharged,
consuming power. If the load is close to 0 A, then the parasitic
load’s can be significant.
In pulsed-frequency mode we switch the NMOS and PMOS when

it’s needed. If there is no load, there is no switching, and 𝑉1 or
𝐷𝐶𝐶 in figure below is high impedant.
IEEE DC DC
I
Vo
CK FSM Da
Vz
Vol
REF
Imagine 𝑉𝑜 is at 1 V, and we apply a constant output load. According

to the integral equations the 𝑉𝑜 would decrease linearly.
In the figure above we observe 𝑉𝑜 with a comparator that sets 𝑉𝑂𝐿

high if the 𝑉𝑜 < 𝑉𝑅𝐸𝐹 . The output from the comparator could be
the inputs to a finite state machine (FSM).
Consider the FSM below. On 𝑣𝑜𝑙 = 1 we transition to “UP” state

where turn on the PMOS for a fixed number of clock cycles. The
inductor current would increase linearly. From the “UP” state
we go to the “DOWN” state, where we turn on the NMOS. The
inductor current would decrease roughly linearly.
The “zero-cross” comparator observes the voltage across the NMOS

drain/source. As soon as we turn the NMOS on the current
direction in the inductor is still from 𝐷𝐶𝐶 to 𝑉𝑜 . Since the current
is pulled from ground, the 𝐷𝐶𝐶 must be below ground. As the
current in the inductor decreases, the voltage across the NMOS
will at some point be equal to zero, at which point the inductor
current is zero.
When 𝑣𝑧 = 1 happens in the state diagram, or the zero cross

comparator triggers, we transition from the “DWN” state back to
“IDLE”. Now the FSM wait for the next time 𝑉𝑜 < 𝑉𝑅𝐸𝐹 .
count < up_cycles
UP
vol = 0 a=1 vz = 0
b=0 count = up_cycles
vol = 1 count++
IDLE DWN
a=0 a=0
b=0
vz = 1 b=1
count=0 count=0
I think the name “pulsed-frequency mode” refers to the fact that

the frequency changes according to load current, however, I’m
not sure of the origin of the name. The name is not important.
What’s important is that you understand that mode 1 (PWM) and
mode 2 (PFM) are two different “operation modes” of a DC/DC
converter.
I made a jupyter model for the PFM mode. I would encourage you
to play with them.
Below you can see a period of the PFM buck. The state can be seen
in the bottom plot, the voltage in the middle and the current in the
inductor and load in the top plot.
Jupyter PFM BUCK model
0.08 Ix
0.06 Io
0.04
0.02
0.00
1.03
1.02
vo
1.01
1.00
0.99
2
STATE
0=IDLE, 1=UP, 2=DWN

0
98 99 100 101 102 103 104 105
Time [us]
Search terms: regulator, buck converter, dc/dc converter, boost

converter
14.4.1 Linear regulators
A Scalable High-Current High-Accuracy Dual-Loop Four-Phase

Switching LDO for Microprocessors Overview of fancy LDO
schemes, digital as well as analog
Development of Single-Transistor-Control LDO Based on Flipped

Voltage Follower for SoC In capacitor less LDOs a flipped voltage
follower is a common circuit, worth a read.
A 200-mA Digital Low Drop-Out Regulator With Coarse-Fine Dual

Loop in Mobile Application Processor Some insights into large
power systems.
14.4.2 DC-DC converters
Design Techniques for Fully Integrated Switched-Capacitor DC-DC

Converters Goes through design of SC DC-DC converters. Good
place to start to learn the trade-offs, and the circuits.
High Frequency Buck Converter Design Using Time-Based Control

Techniques I love papers that challenge “this is the way”. Why
should we design analog feedback loops for our bucks, why not
design digital feedback loops?
Single-Inductor Multi-Output (SIMO) DC-DC Converters With

High Light-Load Efficiency and Minimized Cross-Regulation for
Portable Devices Maybe you have many supplies you want to
drive, but you don’t want to have many inductors. SIMO is then
an option
A 10-MHz 2–800-mA 0.5–1.5-V 90% Peak Efficiency Time-Based

Buck Converter With Seamless Transition Between PWM/PFM
Modes Has some lovely illustrations of PFM and PWM and the
trade-offs between those two modes.
A monolithic current-mode CMOS DC-DC converter with on-

chip current-sensing technique In bucks converters there are two
“religious” camps. One hail to “voltage mode” control loop, another
hail to “current mode” control loops. It’s good to read about both
and make up your own mind.
Clocks and PLLs 15
Keywords: Systems, Feedback, PLL, Integer Divider, SD, SD PLL, 15.1 Why clocks? . . . . . 253
15.1.1 A customer story . . 253
Modulation, linear phase model
15.1.2 Frequency . . . . . . 255
15.1.3 Noise . . . . . . . . . 255
15.1.4 Stability . . . . . . . 255
15.1 Why clocks? 15.1.5 Conclusion . . . . . 255
15.2 A typical System-
On-Chip clock
Virtually all integrated circuits have some form of clock system. system . . . . . . . . 256
15.2.1 32 MHz crystal . . . 256
For digital we need clocks to tell us when the data is correct. For 15.2.2 32 KiHz crystal . . . 257
Radio’s we need clocks to generate the carrier wave. For analog 15.2.3 PCB antenna . . . . 257
we need clocks for switched regulators, ADCs, accurate delay’s or 15.2.4 DC/DC inductor . . 257
indeed, long delays. 15.3 PLL . . . . . . . . . . 259
15.3.1 Integer PLL . . . . . 260
The principle of a clock is simple. Make a 1-bit digital signal that 15.3.2 Fractional PLL . . . 261
toggles with a period 𝑇 and a frequency 𝑓 = 1/𝑇 . 15.3.3 Modulation in PLLs 261
15.4 PLL Example . . . . 262
The implementation is not necessarily simple. 15.4.1 Loop gain . . . . . . 264
15.4.2 Controlled oscillator 264
The key parameters of a clock are the frequency of the fundamental, 15.4.3 Phase detector and
noise of the frequency spectrum, and stability over process and charge pump . . . . 266
15.4.4 Loop filter . . . . . . 267
enviromental conditions.
15.4.5 Divider . . . . . . . . 267
When I start a design process, I want to know why, how, what (and 15.4.6 Loop transfer func-
tion . . . . . . . . . . 268
sometimes who). If I understand the problem from first principles
it’s more likely that the design will be suitable.
But proving that something is suitable, or indeed optimal, is not

easy in the world of analog design. Analog design is similar to
physics. An hypothesis is almost impossible to prove “correct”, but
easier to prove wrong.
15.1.1 A customer story
Take an example.
15.1.1.1 Imagine a world
“I have a customer that needs an accurate clock to count

seconds”. – Some manager that talked to a customer,
but don’t understand details.
254 15 Clocks and PLLs
As a designer, I might latch on to the word “accurate clock”, and

translate into “most accurate clock in the world”, then I’d google
atomic clocks, like Rubidium standard that I know is based on
the hyperfine transition of electrons between two energy levels in
rubidium-87.
I know from quantum mechanics that the hyperfine transition

between two energy levels will produce an precise frequency, as the
frequency of the photons transmitted is defined by 𝐸 = ℏ𝜔 = ℎ 𝑓 .
I also know that quantum electro dynamics is the most precise

theory in physics, so we know what’s going on.
As long as the Rubidium crystal is clean (few energy states in the

vicinity of the hyperfine transition), the distance between atoms
stay constant, the temperature does not drift too much, then the
frequency will be precise. So I buy a rubidium oscillator at a cost
of $ 3k.
I design a an ASIC to count the clock ticks, package it plastic, make

a box, and give my manager.
Who will most likely say something like
“Are you insane? The customer want’s to put the clock

on a wristband, and make millions. We can’t have a
cost of $ 3k per device. You must make it smaller an it
must cost 10 cents to make”
Where I would respond.
“What you’re asking is physically impossible. We can’t

make the device that cheap, or that small. Nobody can
do that.”
And both my manager and I would be correct.
15.1.1.2 Imagine a better world
Most people in this world have no idea how things work. Very
few people are able to understand the full stack. Everyone of us
must simplify what we know to some extent. As such, as a circuit
designer, it’s your responsibility to fully understand what is asked
of you.
When someone says
” I have a customer that needs an accurate clock to

count seconds”
15.1 Why clocks? 255
Your response should be “Why does the customer need an accurate

clock? How accurate? What is the customer going to use the clock
for?”. Unless you understand the details of the problem, then your
design will be sub-optimal. It might be a great clock source, but it
will be useless for solving the problem.
15.1.2 Frequency
The frequency of the clock is the frequency of the fundamental. If

it’s a digital clock (1-bit) with 50 % duty-cycle, then we know that
a digital pulse train is an infinite sum of odd-harmnoics, where
the fundamental is given by the period of the train.
15.1.3 Noise
Clock noise have many names. Cycle-to-cycle jitter is how the

period changes with time. Jitter may also mean how the period
right now will change in the future, so a time-domain change in
the amount of cycle-to-cycle jitter. Phase noise is how the period
changes as a function of time scales. For example, a clock might
have fast period changes over short time spans, but if we average
over a year, the period is stable.
What type of noise you care about depends on the problem. Digital
will care about the cycle-to-cycle jitter affects on setup and hold
times. Radio’s will care about the frequency content of the noise
with an offset to the carrier wave.
15.1.4 Stability
The variation over all corners and enviromental conditions is

usually given in a percentage, parts per million, or parts per
billion.
For a digital clock to run a Micro-Controller, maybe it’s sufficient

with 10% accuracy of the clock frequency. For a Bluetooth radio
we must have +-50 ppm, set by the standard. For GPS we might
need parts-per-billion.
15.1.5 Conclusion
Each “clock problem” will have different frequency, noise and

stability requirements. You must know the order of magnitude
of those before you can design a clock source. There is no “one-
solution fits all” clock generation IP.
15.2 A typical System-On-Chip clock system
On the nRF52832 development kit you can see some components

that indicate what type of clock system must be inside the IC.
In the figure below you can see the following items.
1. 32 MHz crystal
2. 32 KiHz crystal
3. PCB antenna
4. DC/DC inductor
15.2.1 32 MHz crystal
Any Bluetooth radio will need a frequency reference. We need to

generate an accurate 2.402 MHz - 2.480 MHz carrier frequency
for the gaussian frequency shift keying (GFSK) modulation. The
Bluetooth Standard requires a +- 50 ppm accurate timing reference,
and carrier frequency offset accuracy.
I’m not sure it’s possible yet to make an IC that does not have some
form of frequency reference, like a crystal. The ICs I’ve seen so far
that have “crystal less radio” usually have a resonator (crystal or
bulk-accustic-wave or MEMS resonator) on die.
The power consumption of a high frequency crystal will be pro-

portional to frequency. Assuming we have a digital output, then
the power of that digital output will be 𝑃 = 𝐶𝑉 2 𝑓 , for exam-
ple 𝑃 = 100 fF × 1 V2 × 32 MHz = 3.2 𝜇W is probably close to a
minimum power consumption of a 32 MHz clock.
15.2 A typical System-On-Chip clock system 257
15.2.2 32 KiHz crystal
Reducing the frequency, we can get down to minimum power

consumption of 𝑃 = 100 fF × 1 V2 × 32 KiHz = 3.2 nW for a
clock.
For a system that sleeps most of the time, and only wakes up at
regular ticks to do something, then a low-frequency crystal might
be worth the effort.
15.2.3 PCB antenna
Since we can see the PCB antenna, we know that the IC includes a
radio. From that fact we can deduce what must be inside the SoC.
If we read the Product Specification we can understand more.
15.2.4 DC/DC inductor
Since we can see a large inductor, we can also make the assumption
that the IC contains a switched regulator. That switched regulator,
especially if it has a pulse-width-modulated control loop, will need
a clock.
From our assumptions we could make a guess what must be inside

the IC, something like the picture below.
There will be a crystal oscillator connected to the crystal. We’ll

learn about those later.
These crystal oscillators generate a fixed frequency, 32 MHz, or 32

KiHz, but there might be other clocks needed inside the IC.
To generate those clocks, there will be phase-locked loops (PLL),

frequency locked loops (FLL), or delay-locked loops (DLL).
PLLs take a reference input, and can generate a higher frequency,

(or indeed lower frequency) output. A PLL is a magical block. It’s
one of the few analog IPs where we can actually design for infinite
gain in our feedback loop.
32MHz
Xo
RADIO
PLL PLL Lo
MCU
XO
32768 Hz
RC
Most of the digital blocks on an IC will be synchronous logic, see

figure below. A fundamental principle of sychnronous logic is that
the data at the flip-flops (DFF, rectangles with triangle clock input,
D, Q and Q) only need to be correct at certain times.
The sequence of transitions in the combinatorial logic is of no

consequence, as long as the B inputs are correct when the clock
goes high next time.
The registers, or flip-flops, are your SystemVerilog “always_ff”

code. While the blue cloud is your “always_comb” code.
In a SoC we have to check, for all paths between a Y[N] and B[M]
that the path is fast enough for all transients to settle before the
clock strikes next time. How early the B data must arrive in relation
to the clock edge is the setup time of the DFFs.
We also must check for all paths that the B[M] are held for long
enough after the clock strikes such that our flip-flop does not
change state. The hold time is the distance from the clock edge
to where the data is allowed to change. Negative hold times are
common in DFFs, so the data can start to change before the clock
edge.
In an IC with millions of flip-flops there can be billions of paths.

The setup and hold time for every single one must be checked.
One could imagine a simulation of all the paths on a netlist with
parasitics (capacitors and resistors from layout) to check the delays,
but there are so many combinations that the simulation time
becomes unpractical.
15.3 PLL 259
Static Timing Analysis (STA) is a light-weight way to check all

the paths. For the STA we make a model of the delay in each cell
(captured in a liberty file), the setup/hold times of all flip-flops,
wire propagation delays, clock frequency (or period), and the
variation in the clock frequency. The process, voltage, temperature
variation must also be checked for all components, so the number
of liberty files can quickly grow large.
Enable Clk out

For an analog designerLogic D Q from digital will tell us
the constraints
Lo
what’s the maximum frequency we can have at any point in time,
and what is the maximum cycle-to-cycle variation in the period.
Clk in
Alo yo XXX Bos x o3
BED XD
AID
Clk out
15.3 PLL
PLL, or it’s cousins FLL and DLL are really cool. A PLL is based
on the familiar concept of feedback, shown in the figure below. As
long as we make 𝐻(𝑠) infinite we can force the output to be an
exact copy of the input.
VI VX
Hs
V0
Vo Vx H s
VI Vo Ux
Vo I
VI Vo YE
15.3.1 Integer PLL
VI VX V0
For a frequency loop the figure looks a bit different. If we want a
H
higher output frequency we cans divide the frequency by a number
(N) and compare with our reference (for example the 32 MHz
reference from the crystal oscillator). N
Ux Vo Vx H s
VI Vo
fin
We then take the error, apply a transfer function 𝐻(𝑠) with high
gain, and control our oscillator frequency. Vo
Vo I
to
VI yes
YE
If the down-divided output frequency is too high, we force the os-
cillator to a lower frequency. If the down-divided output frequency
is too low we force the oscillator to a higher frequency.
If we design the 𝐻(𝑠) correctly, then we have 𝑓𝑜 = 𝑁 × 𝑓𝑖𝑛
fin to
yes
Sometimes you want a finer frequency resolution, in that case

𝑓𝑖𝑛
you’d add a divider on the reference and get 𝑓𝑜 = 𝑁 × 𝑀 ..
15.3 PLL 261
fin M Hcs
to
in
15.3.2 Fractional PLL
MTrouble is that dividing

Hcs
to
ED N
down the input frequency will reduce your
loop bandwidth, as the low-pass filter needs to be about 1/10’th of
fin
the reference frequency. As such, the PLL will respond slower to a
frequency change.
to
yes
We can also use a fractional divider, where we swap between two,
or more, integeres in a sigma-delta fashion in the divider.
ED N
fin to
yes
15.3.3 Modulation in PLLs
From your signal processing, or communication courses, you may

recognize the equation below.
𝐴𝑚 (𝑡) × 𝑐𝑜𝑠 2𝜋 𝑓𝑐𝑎𝑟𝑟𝑖𝑒𝑟 𝑡 + 𝜙 𝑚 (𝑡)

The 𝐴𝑚 is the amplitude modulation, while the 𝜙 𝑚 is the phase

modulation. Bluetooth Low Energy is constant envelope, so the
𝐴𝑚 is a constant. The phase modulation is applied to the carrier,
but how is it done?
One option is shown below. We could modulate our frequency

reference directly. That could maybe be a sigma-delta divider on
the reference, or directly modulating the oscillator.
fin yes
Amos N
fin to
His N
Most modern radios, however, will have a two-point modulation.

The modulation signal is applied to the VCO (or DCO), and the
opposite signal is applied to the feedback divider. As such, the
modulation is not seen by the loop.
food
ED N
fin to
yes
fmod
15.4 PLL Example
I’ve made an example PLL that you can download and play with.
I make no claims that it’s a good PLL. Actually, I know it’s a bad
PLL. The ring-oscillator frequency varies to fast with the voltage
control. But it does give you a starting point.
A PLL can consist of a oscillator (SUN_PLL_ROSC) that generates

our output frequency. A divider (SUN_PLL_DIVN) that generates a
feedback frequency that we can compare to the reference. A Phase
and Frequency Detector (SUN_PLL_PFD) and a charge-pump
(SUN_PLL_CP) that model the +, or the comparison function
in our previous picture. And a loop filter (SUN_PLL_LPF and
SUN_PLL_BUF) that is our 𝐻(𝑠).
/Users/wulff/pro/aicex/ip/sun_pll_sky130nm/design/SUN_PLL_SKY130NM/SUN_PLL.sch
15.4 PLL Example 263
CK_REF x 32 PLL (max 512 MHz)

AVDD
VDD_ROSC
CP_UP_N xa1 xa5
xa0
AVDD
AVDD
AVDD
Kcp = Ibp/2pi xa4
AVDD
VLPF
CK_REF CK_REF CP_UP_N CP_UP_N VO VDD_ROSC
PWRUP_1V8
CK_FB CP_DOWN CP_DOWN LPF VI CK CK
PWRUP_1V8
VFB
CP_DOWN
xd0
VLPF
AVSS
AVSS
LPFZ
AVSS
KICK
VBN
VBN
AVSS
VLPFZ
SUN_PLL_PFD SUN_PLL_CP SUN_PLL_BUF
VLPFZ
SUN_PLL_ROSC
KICK
AVSS
xaa6
AVDD
SUN_PLL_LPF
CK_FB
IBPSR_1U 1
CK
PWRUP_1V8
CK_FB 32
AVSS
xbb1
xaa3
BIAS
IBPSR_1U
AVDD KICK SUN_PLL_DIVN

PWRUP_1V8 KICK_N
AVSS
AVSS PWRUP_1V8_N PWRUP_1V8_N

PWRUP_1V8_N
SUN_PLL_KICK
SUN_PLL_BIAS
PWRUP_1V8
Designer Carsten Wulff

AVSS Updated wulff
Modified 2024-02-29 14:25:41
Copyright Carsten Wulff Software
Library/Cell SUN_PLL
Read any book on PLLs, talk to any PLL designer and they will all
tell you the same thing. PLLs require calculation. You must setup
a linear model of the feedback loop, and calculate the loop transfer
function to check the stability, and the loop gain. This is the way!
(to quote Mandalorian).
But how can we make a linear model of a non-linear system? The

voltages inside a PLL must be non-linear, they are clocks. A PLL is
not linear in time-domain!
I have no idea who first thought of the idea, but it turns out, that
one can model a PLL as a linear system if one consider the phase
of the voltages inside the PLL, especially when the PLL is locked
(phase of the output and reference is mostly aligned). Where the
phase is defined as
∫ 𝑡
𝜙(𝑡) = 2𝜋 𝑓 (𝑡)𝑑𝑡
0
As long as the bandwidth of the 𝐻(𝑠) is about 10

1
of the reference
frequency, then the linear model below holds (at least is good
enough).
The phase of our input is 𝜙 𝑖𝑛 (𝑠), the phase of the output is 𝜙(𝑠),
the divided phase is 𝜙 𝑑𝑖𝑣 (𝑠) and the phase error is 𝜙 𝑑 (𝑠).
The 𝐾 𝑝𝑑 is the gain of our phase-frequency detector and charge-

pump. The 𝐾 𝑙𝑝 𝐻𝑙𝑝 (𝑠) is our loop filter 𝐻(𝑠). The 𝐾 𝑜𝑠𝑐 /𝑠 is our
oscillator transfer function. And the 1/𝑁 is our feedback divider.
Girls OÉpd 0 s
Kuhns Kosel
Oldies
YN
15.4.1 Loop gain

ked Koeller Kosel
OdeThe0in
loop transfer function can then be analyzed and we get.
𝜙𝑑 1
=
𝜙 𝑖𝑛 1 + 𝐿(𝑠)
Old It kpdkgtk.sk din
𝐾 𝐾 𝑜𝑠𝑐 𝑝𝑑 𝐾 𝑙𝑝 𝐻 𝑙𝑝 (𝑠)
𝐿(𝑠) =
𝑁𝑠
IE ILG
Here is the magic of PLLs. Notice what happens when 𝑠 = 𝑗𝜔 = 𝑗 0,
or at zero frequency. If we assume that 𝐻𝑙𝑝 (𝑠) is a low pass
filter, then 𝐻𝑙𝑝 (0) = constant. The loop gain, however, will have a
𝐿(0) ∝ 01 which approaces infinity at 0.
That means, we have an infinite DC gain in the loop transfer

function. It is the only case I know of in an analog design where we
can actually have infinite gain. Infinite gain translate can translate
to infinite precision.
If the reference was a Rubidium oscillator we could generate

any frequency with the same precision as the frequency of the
Rubidium oscillator. Magic.
For the linear model, we need to figure out the factors, like 𝐾 𝑣𝑐𝑜 ,
which must be determined by simulation.
15.4.2 Controlled oscillator
The gain of the oscillator is the change in output frequency as a

function of the change of the control node. For a voltage-controlled
oscillator (VCO) we could sweep the control voltage, and check the
frequency. The derivative of the f(V) would be proportional to the
𝐾 𝑣𝑐𝑜 .
The control node does not need to be a voltage. Anything that

changes the frequency of the oscillator can be used as a control node.
2 = 512 There
MHz PLL
exist PLLs with voltage control, current control, capacitance
control, and digital control.
For the SUN_PLL_ROSC it is the VDD of the ring-oscillator (VDD_-

ROSC) that is our control node.
𝑑𝑓
𝐾 𝑜𝑠𝑐 = 2𝜋
𝑑𝑉𝑐𝑛𝑡𝑙
VDD_ROSC
xaa5
AVDD
xaa4
AVDD
VO VDD_ROSC
VI CK CK
PWRUP_1V8
VFB
xbb0
VLPF
AVSS
VBN
AVSS
SUN_PLL_BUF
VLPFZ
SUN_PLL_ROSC
AVSS
xaa6
AVDD
SUN_PLL_LPF
CK_FB
1
15.4.2.1 SUN_PLL_SKY130NM/sim/ROSC/CK
PWRUP_1V8
CK_FB 32
AVSS
I simulate the ring oscillator in ngspice with a transient simulation

SUN_PLL_DIVN
and get the oscillator frequency as a function of voltage.
tran.spi
let start_v = 1.1 Designer Carsten Wulff

Updated wulff
let stop_v = 1.7 Modified 2023-01-22 22:00:43
let delta_v = 0.1
let v_act = start_v
* loop
while v_act le stop_v
alter VROSC v_act
tran 1p 40n
meas tran vrosc avg v(VDD_ROSC)
meas tran tpd trig v(CK) val='0.8' rise=10 targ v(CK) val='0.8' rise=11
let v_act = v_act + delta_v
end
I use tran.py to extract the time-domain signal from ngspice into

a CSV file.
Then I use a python script to extract the 𝐾 𝑜𝑠𝑐
kvco.py
df = pd.read_csv(f)
freq = 1/df["tpd"]
kvco = np.mean(freq.diff()/df["vrosc"].diff())
Below I’ve made a plot of the oscillation frequency over corners.
tran_LayGtVtKttTt
1200 tran_LayGtVtKssTt
tran_LayGtVtKffTt
tran_LayGtVtKttTh
1000 tran_LayGtVtKssTh
tran_LayGtVtKffTh
Frequency [MHz]
tran_LayGtVtKttTl
tran_LayGtVtKssTl
800 tran_LayGtVtKffTl
600
400
1.1 1.2 1.3 1.4 1.5 1.6

VDD_ROSC [V]
/Users/wulff/pro/aicex/ip/sun_pll_sky130nm/work/../design/SUN_PLL_SKY130NM/SUN
15.4.3 Phase detector and charge pump
The gain of the phase-detector and charge pump is the current we

feed into the loop filter over a period. I don’t remember why, check
in the book for a detailed description.
The two blocks compare our reference clock to our feedback clock,
16 MHz x 32 = 512
and produce an error signal.
AVDD
𝐼 𝑐𝑝
𝐾 𝑝𝑑 =
2𝜋
CP_UP_N
xaa1
xaa0
AVDD
AVDD
Kcp = Ibp/2pi
VLPF
CK_REF CK_REF CP_UP_N CP_UP_N

PWRUP_1V8
CK_FB CP_DOWN CP_DOWN LPF

CP_DOWN
xbb0
VLPF
AVSS
AVSS
LPFZ
KICK
VBN
VLPFZ
SUN_PLL_PFD SUN_PLL_CP
VLPFZ
KICK
AVSS
SUN_PLL
IBPSR_1U
xbb1
xaa3
BIAS
IBPSR_1U
AVDD KICK
PWRUP_1V8 KICK_N
SS
AVSS PWRUP_1V8_N PWRUP_1V8_N

15.4.4 Loop filter
In the book you’ll find a first order loop filter, and a second order
0nm/work/../design/SUN_PLL_SKY130NM/SUN_PLL.sch
loop filter. Engineers are creative, so you’ll likely find other loop
filters in the literature.
I would start with the “known to work” loop filters before you
explore on your own.
If you’re really interested in PLLs, you should buy Design of CMOS

Phase-Locked Loops by Behzad Razavi.
The loop filter has a unity gain buffer. My oscillator draws current,
while the VPLF node is high impedant, so I can’t draw current
/SUN_PLL.sch
16 MHz x 32 = 512 MHz PLL from the loop filter without changing the filter transfer function.

1 1
𝐾 𝑙𝑝 𝐻𝑙𝑝 (𝑠) = 𝐾 𝑙𝑝 +
𝑠 𝜔𝑧
1 1 + 𝑠𝑅𝐶1
𝐾 𝑙𝑝 𝐻𝑙𝑝 (𝑠) =
𝑠(𝐶1 + 𝐶2 ) 1 + 𝑠𝑅 𝐶1 𝐶2
𝐶1 +𝐶2
VDD_ROSC
CP_UP_N
xaa1 xaa5
512 MHz PLL

0
AVDD
AVDD
Kcp = Ibp/2pi xaa4

AVDD
VLPF
UP_N CP_UP_N VO VDD_ROSC

PWRUP_1V8
OWN CP_DOWN LPF VI CK CK

PWRUP_1V8
VFB
CP_DOWN
xbb0
VLPF
AVSS
LPFZ
AVSS
KICK
VBN
VBN
AVSS
VLPFZ
D SUN_PLL_CP SUN_PLL_BUF
VLPFZ
SUN_PLL_ROSC
KICK
AVSS
xaa6
AVDD
SUN_PLL_LPF
CK_FB
1
CK
PWRUP_1V8
CK_FB 32
AVSS
VDD_ROSC
xaa3
xbb1
15.4.5 Divider
BIAS
IBPSR_1U
xaa5
KICK SUN_PLL_DIVN
AVDD
V8 KICK_N xaa4
AVSS
AVDD
PWRUP_1V8_N
PWRUP_1V8_N
The divider is modelled as
PWRUP_1V8_N
L_KICK VO VDD_ROSC
SUN_PLL_BIAS
VI CK CK
PWRUP_1V8
VFB
b0
1
AVSS
VBN
𝐾 𝑑𝑖𝑣 =
AVSS
SUN_PLL_BUF
SUN_PLL_ROSC
𝑁 Designer
Updated
Carsten Wulff
wulff
Modified 2023-01-22 22:00:43
xaa6
AVDD
UN_PLL_LPF
CK_FB
1
CK
PWRUP_1V8
CK_FB 32
AVSS
SUN_PLL_DIVN
Designer Carsten Wulff

Updated wulff
Modified 2023-01-22 22:00:43
15.4.6 Loop transfer function
With the loop transfer function we can start to model what happens
in the linear loop. What is the phase response, and what is the gain
response.
𝐾 𝑜𝑠𝑐 𝐾 𝑝𝑑 𝐾 𝑙𝑝 𝐻𝑙𝑝 (𝑠)

𝐿(𝑠) =
𝑁𝑠
15.4.6.1 Python model
I’ve made a python model of the loop, you can find it at sun_pll_-
sky130nm/jupyter/pll
In the jupyter notbook below you can find some more information
on the phase/frequency detector, and charge pump.
sun_pll_sky130nm/jupyter/pfd
Below is a plot of the loop gain, and the transfer function from
input phase to divider phase.
We can see that the loop gain at low frequency is large, and
proportional to 1/𝑠 . As such, the phase of the divided down
feedback clock is the same as our reference.
The closed loop transfer function 𝜙 𝑑𝑖𝑣 /𝜙 𝑖𝑛 shows us that the

divided phase at low frequency is the same as the input phase.
Since the phase is the same, and the frequency must be the same,
then we know that the output clock will be N times reference
frequency.
100 Lg
div/ in
Magnitude [dB]
50
0
50
103 104 105 106 107 108
0 Frequency [Hz]
Lg
div/ in
Phase [Degrees]
50
Phase margin = 55.0
100
150
103 104 105 106 107 108

Frequency [Hz]
The top testbench for the PLL is tran.spi.
I power up the PLL and wait for the output clock to settle. I use
freq.py to plot the frequency as a function of time. The orange curve
is the average frequency. We can see that the output frequency
settles to 256 MHz.
tran_LayGtVtKttTt.raw
mid,end: 259.270,256.04 MHz
500
400
Frequency [MHz]
300
200
100
0
2 4 6 8 10 12 14
Time [us]
You can find the schematics, layout, testbenches, python script etc
at SUN_PLL_SKY130NM
Below are a couple layout images of the finished PLL

Back in 2020 there was a Master student at NTNU on PLL. I would

recommend looking at that thesis to learn more, and to get inspired
Ultra Low Power Frequency Synthesizer.
A Low Noise Sub-Sampling PLL in Which Divider Noise is Elimi-

nated and PD/CP Noise is Not Multiplied by N2
All-digital PLL and transmitter for mobile phones
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase

Detector and 560-fsrms Integrated Jitter at 4.5-mW Power
Oscillators 16
Keywords: Crystal model, Pierce, Temperature, Controlled oscilla- 16.1 Atomic clocks . . . . 273
tor, Ring osc, Ictrl Rosc, DCO Ring, LCOSC, RCOSC 16.1.1 Microchip 5071B
Cesium Primary
The world depends on accurate clocks. From the timepiece on your Time and Frequency
Standard . . . . . . . 273
wrist, to the phone in your pocket, they all have a need for an
16.1.2 Rubidium standard 274
accurate way of counting the passing of time.
16.2 Crystal oscillators . 276
Without accurate clocks an accurate GPS location would not be 16.2.1 Impedance . . . . . . 279
16.2.2 Circuit . . . . . . . . 280
possible. In GPS we even correct for Special and General Relativity
16.2.3 Temperature behav-
to the tune of about +38.6𝜇s/day .
ior . . . . . . . . . . . 282
Let’s have a look at the most accurate clocks first. 16.3 Controlled Oscilla-
tors . . . . . . . . . . 283
16.3.1 Ring oscillator . . . . 283
16.3.2 Capacitive load . . . 285
16.1 Atomic clocks 16.3.3 Realistic . . . . . . . 285
16.3.4 Digitally controlled
oscillator . . . . . . . 288
Cesium standard 16.3.5 Differential . . . . . . 288
16.3.6 LC oscillator . . . . . 289
The second is defined by taking the fixed numerical value of the 16.4 Relaxation oscilla-
cesium frequency Cs, the unperturbed ground-state hyper-fine tors . . . . . . . . . . 291
transition frequency of the cesium 133 atom, to be 9 192 631 770 16.5 Want to learn more? 292
when expressed in the unit Hz, which is equal to s–1 16.5.1 Crystal oscillators . 292
16.5.2 CMOS oscillators . . 292
As a result, by definition, the cesium clocks are exact. That’s how
the second is defined. When we make a real circuit, however, we
never get a perfect, unperturbed system.
16.1.1 Microchip 5071B Cesium Primary Time and

Frequency Standard
One example of a ultra precise time piece is shown below. The

bullets in the list below is from the marketing blurb.
Why would the thing take 30 minutes to start up? Does the tem-
perature need to settle? Is it the loop bandwidth of the PLL that is
low? Who knows, but 30 minutes is too long for a IC startup time.
And we can’t really pack the big box onto a chip.
▶ < 5E-13 accuracy high-performance models

▶ Accuracy levels achieved within 30 minutes of startup
▶ < 8.5E-13 at 100s high-performance models
▶ < 1E-14 flicker floor high-performance models
274 16 Oscillators
Also, when they say
“Ask for a quote” => The price is really high, and we don’t want to
tell you yet
16.1.2 Rubidium standard
Rubidium standard, use the rubidium hyper-fine transition of 6.8

GHz (6834682610.904 Hz)
and can actually be made quite small. Below is a picture of a tiny

atomic clock. According to the marketing blurb:
The MAC is a passive atomic clock, incorporating the interrogation

technique of Coherent Population Trapping (CPT) and operating upon
the D1 optical resonance of atomic Rubidium Isotope 87.
A rubidium clock is basically a crystal oscillator locked to an

atomic reference.
16.1 Atomic clocks 275
But how do the clocks work? According to Wikipedia, the picture

below, is a common way to operate a rubidium clock.
A light passing through the Rubidium gas will be affected if the

frequency injected is at the hyper-fine energy levels (E = hf). The
change in brightness can be detected by the photo detector, and
we can adjust the frequency of the crystal oscillator, we’ll see later
how that can be done. The crystal oscillator is used as reference
for a PLL (freqency synthesizer ) to generate the exact frequency
needed.
The negative feedback loop ensures that the 5 MHz clock coming
out is proportional to the hyper-fine energy levels in the Rubidium
atoms. Negative feedback is cool! Especially when we have a pole
at DC and infinite gain.
276 16 Oscillators
16.2 Crystal oscillators
For accuracy’s of parts per million, which is sufficient for your

wrist watch, or most communication, it’s possible to use crystals.
A quartz crystal can resonate at specific frequencies. If we apply

a electric field across a crystal, we will induce a vibration in the
crystal, which can again affect the electric field. For some history,
see Crystal Oscillators
16.2 Crystal oscillators 277
The vibrations in the crystal lattice can have many modes, as

illustrated by figure below.
All we need to do with a crystal is to inject sufficient energy to

sustain the oscillation, and the resonance of the crystal will ensure
we have a correct enough frequency.
278 16 Oscillators
16.2.1 Impedance
The impedance of a crystal is usually modeled as below. A RLC

circuit with a parallel capacitor.
I Our job is to make a circuit that we can connect to the two pins
and provide the energy we will loose due to 𝑅 𝑠 .
D Rst Sh t IE Zin
Rs
Gp sCp
L Cp
CF
Gin
pkg
Assuming zero series resistance
t SCP
𝑠2𝐶 𝐿 + 1
Gin𝑍𝑖𝑛 = 𝑠 3 𝐶𝑃 𝐿𝐶𝐹 + 𝑠𝐶𝑃 +t𝑠𝐶SCP
𝐹
Eye 𝐹
Notice that at 𝑠 = 0 the impedance goes to infinity, so a crystal is

L JonH
high impedant at DC.
É tsar
Since the 1/(sCp) does not change much at resonance, then
CF SFF
Cp 5pF
sctg.es
𝑍 𝑖𝑛 ≈
𝐿𝐶 𝑠 + 1
𝐿𝐶 𝐹 𝐶 𝑝 fstet
𝐹
𝑠2
2
+ 𝐶𝐹 + 𝐶𝑃
II
so
See Crystal oscillator impedance for a detailed explanation.
zm ss
In the impedance plot below we can clearly see that there are
two “resonance” points. Usually noted by series and parallel
resonance.
I would encourage you to read The Crystal Oscillator for more

details.
280 16 Oscillators
16.2.2 Circuit
Below is a common oscillator circuit, a Pierce Oscillator. The crystal

is the below the dotted line, and the two capacitance’s are the
on-PCB capacitance’s.
Above the dotted line is what we have inside the IC. Call the left
side of the inverter XC1 and right side XC2. The inverter is biased
by a resistor, 𝑅 1 , to keep the XC1 at a reasonable voltage. The XC1
and XC2 will oscillate in opposite directions. As XC1 increases, XC2
will decrease. The 𝑅 2 is to model the internal resistance (on-chip
wires, bond-wire).
n n
Negative transconductance compensate crystal series resis-

tance
The transconductance of the inverter must compensate for the

energy loss caused by 𝑅 𝑠 in the crystal model. The transconductor
also need to be large enough for the oscillation to start, and build
up.
I’ve found that sometimes people get confused by the negative

transconductance. There is nothing magical about that. Imagine
the PMOS and the NMOS in the inverter, and that the input voltage
is exactly the voltage we need for the current in the PMOS and
NMOS to be the same. If the current in the PMOS and NMOS is
the same, then there can be no current flowing in the output.
Imagine we increase the voltage. The PMOS current would de-

crease, and the NMOS current would increase. We would pull
current from the output.
Imagine we now decrease the voltage instead. The PMOS current

would increase, and the NMOS current would decrease. The
current in the output would increase.
As such, a negative transconductance is just that as we increase

the input voltage, the current into the output decreases, and visa
versa.
Long startup time caused by high Q
The Q factor has a few definitions, so it’s easy to get confused.

Think of Q like this, if a resonator has high Q, then the oscillations
die out slowly.
Imagine a perfect world without resistance, and an inductor and

capacitor in parallel. Imagine we initially store some voltage across
the capacitor, and we let the circuit go. The inductor shorts the
plates of the capacitor, and the current in the inductor will build up
until the voltage across the capacitor is zero. The inductor still has
stored current, and that current does not stop, so the voltage across
the capacitor will become negative, and continue decreasing until
the inductor current is zero. At that point the negative voltage will
flip the current in the inductor, and we go back again.
The LC circuit will resonate back and forth. If there was no resis-
tance in the circuit, then the oscillation would never die out. The
system would be infinite Q.
The Q of the crystal oscillator can be described as 𝑄 = 1/(𝜔𝑅 𝑠 𝐶 𝑓 ),

assuming some common values of 𝑅 𝑠 = 50, 𝐶 𝑓 = 5 𝑒 −15 and
𝜔 = 2𝜋 × 32 MHz then 𝑄 ≈ 20 k.
That number may not tell you much, but think of it like this, it
will take 20 000 clock cycles before the amplitude falls by 1/e.
For example, if the amplitude of oscillation was 1 V, and you stop
282 16 Oscillators
introducing energy into the system, then 20 000 clock cycles later,
or 0.6 ms, the amplitude would be 0.37 V.
The same is roughly true for startup of the oscillator. If the crystal
had almost no amplitude, then an increase 𝑒 would take 20 k
cycles. Increasing the amplitude of the crystal to 1 V could take
milliseconds.
Most circuits on-chip have startup times on the order of microsec-

onds, while crystal oscillators have startup time on the order of
milliseconds. As such, for low power IoT, the startup time of crystal
oscillators, or indeed keeping the oscillator running at a really low
current, are key research topics.
Can fine tune frequency with parasitic capacitance
The resonance frequency of the crystal oscillator can be modified by

the parasitic capacitance from XC1 and XC2 to ground. The tunabil-
ity of crystals is usually in ppm/pF. Sometimes micro-controller
vendors will include internal load capacitance’s to support multiple
crystal vendors without changing the PCB.
16.2.3 Temperature behavior
One of the key reasons for using crystals is their stability over
temperature. Below is a plot of a typical temperature behavior.
The cutting angle of the crystal affect the temperature behavior,
as such, the closer crystals are to “no change in frequency over
temperature”, the more expensive they become.
In communication standards, like Bluetooth Low Energy, it’s com-

mon to specify timing accuracy’s of +- 50 ppm. Have a look in
the Bluetooth Core Specification 5.4 Volume 6, Part A, Chapter 3.1
(page 2653) for details.
16.3 Controlled Oscillators 283
16.3 Controlled Oscillators
On an integrated circuit way may need multiple clocks, and we

can’t have crystal oscillators for all of them. We can use frequency
locked loops, phase locked loops and delay locked loops to make
multiples of the crystal reference frequency.
All phase locked loops contain an oscillator where we control the

frequency of oscillation.
16.3.1 Ring oscillator
The simplest oscillator is a series of inverters biting their own tail,

a ring oscillator.
The delay of each stage can be thought of as a RC time constant,

where the R is the transconductance of the inverter, and the C is
the gate capacitance of the next inverter.
𝑡 𝑝𝑑 ≈ 𝑅𝐶
1 1
𝑅≈ ≈
𝑔𝑚 𝜇𝑛 𝐶 𝑜𝑥 𝑊 (𝑉 𝐷𝐷 − 𝑉𝑡 ℎ )
𝐿
2
𝐶≈ 𝐶 𝑜𝑥 𝑊 𝐿
3
284 16 Oscillators
tpd
One way to change the oscillation frequency is to change the VDD

of the ring oscillator. Based on the delay of a single inverter we
can make an estimate of the oscillator gain. How large change in
frequency do we get for a change in VDD.
𝑡 𝑝𝑑 ≈ 𝑊
2/3𝐶 𝑜𝑥 𝑊 𝐿 Er
𝐿 𝜇𝑛 𝐶 𝑜𝑥 (𝑉 𝐷𝐷 − 𝑉𝑡 ℎ )
1 𝜇𝑛 (𝑉 𝐷𝐷 − 𝑉𝑡 ℎ )
𝑓 = =
2 𝑁𝑡 𝑝𝑑 3 𝑁𝐿
4 2
𝜕𝑓 2𝜋𝜇𝑛
𝐾 𝑣𝑐𝑜 = 2𝜋 = 4
𝜕𝑉 𝐷𝐷 3 𝑁𝐿
2
The 𝐾 𝑣𝑐𝑜 is proportional to mobility, and inversely proportional to

the number of stages and the length of the transistor squared. In
most PLLs we don’t want the 𝐾 𝑣𝑐𝑜 to be too large. Ideally we want
the ring oscillator to oscillate close to the frequency we want, i.e 512
MHz, and a small 𝐾 𝑣𝑐𝑜 to account for variation over temperature
(mobility of transistors decreases with increased temperature, the
threshold voltage of transistors decrease with temperature), and
changes in VDD.
To reduce the 𝐾 𝑣𝑐𝑜 of the standard ring oscillator we can increase

the gate length, and increase the number of stages.
I think it’s a good idea to always have a prime number of stages in

the ring oscillator. I have seen some ring oscillators with 21 stages
oscillate at 3 times the frequency in measurement. Since 21 = 7 × 3
it’s possible to have three “waves” of traveling through the ring
oscillator at all times, forever. If you use a prime number of stages,
then sustained oscillation at other frequencies cannot happen.
As such, then number of inverter stages should be ∈

[3, 5, 7, 11, 13, 17, 19, 23, 29, 31]
16.3.2 Capacitive load
The oscillation frequency of the ring oscillator can also be changed

by adding capacitance.
𝜇𝑛 𝐶 𝑜𝑥 𝑊
𝐿 (𝑉 𝐷𝐷 − 𝑉𝑡 ℎ )
𝑓 =
2𝑁 3 𝐶 𝑜𝑥 𝑊 𝐿
2
+𝐶

2𝜋𝜇𝑛 𝐶 𝑜𝑥 𝑊
𝐿
𝐾 𝑣𝑐𝑜 =
2𝑁 3 𝐶 𝑜𝑥 𝑊 𝐿
2
+𝐶

Assume that the extra capacitance is much larger than the gate
capacitance, then
𝜇𝑛 𝐶 𝑜𝑥 𝑊
𝐿 (𝑉 𝐷𝐷 − 𝑉𝑡 ℎ )
𝑓 =
2𝑁 𝐶
f
t.FI Fifty tamarett
2𝜋𝜇𝑛 𝐶 𝑜𝑥 𝑊
𝐿
𝐾 𝑣𝑐𝑜 =
2𝑁 𝐶
And maybe we could make the 𝐾 𝑣𝑐𝑜 relatively small.
The power consumption of an oscillator, however, will be similar

to a digital circuit of 𝑃 = 𝐶 × 𝑓 × 𝑉 𝐷𝐷 2 , so increasing capacitance
will also increase the power consumption.
c c e
16.3.3 Realistic
re
qq.LI
Assume you wanted to design a phase-locked loop, what type
of oscillator should you try first? If the noise of the clock is not
too important, so you don’t need an LC-oscillator, then I’d try the
oscillator below, although I’d expand the number of stages to fit
the frequency.
t
EYeI tamara
286 16 Oscillators
The circuit has a capacitance loaded ring oscillator fed by a current.

The 𝐼 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 will give a coarse control of the frequency, while the
𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 can give a more precise control of the frequency.
Since the 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 can only increase the frequency it’s important
that the 𝐼 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 is set such that the frequency is below the target.
Most PLLs will include some form of self calibration at startup. At

startup the PLL will do a coarse calibration to find a sweet-spot for
𝐼 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 , and then use 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 to do fine tuning.
Since PLLs always have a reference frequency, and a phase and

frequency detector, it’s possible to sweep the calibration word for
𝐼 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 and then check whether the output frequency is above or
below the target based on the phase and frequency detector output.
Although we don’t know exactly what the oscillator frequency is,
we can know the frequency close enough.
It’s also possible to run a counter on the output frequency of the

VCO, and count the edges between two reference clocks. That way
we can get a precise estimate of the oscillation frequency.
Another advantage with the architecture below is that we have

some immunity towards supply noise. If we decouple both the
current mirror, and the 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 towards VDD, then any change to
VDD will not affect the current into the ring oscillator.
Maybe a small side track, but inject a signal into an oscillator from
an amplifier, the oscillator will have a tendency to lock to the
injected signal, we call this “injection locking”, and it’s common
to do in ultra high frequency oscillators (60 - 160 GHz). Assume
we allow the PLL to find the right 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 that corresponds to the
injected frequency. Assume that the injected frequency changes,
for example frequency shift keying (two frequencies that mean 1
or 0), as in Bluetooth Low Energy. The PLL will vary the 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙
of the PLL to match the frequency change of the injected signal, as
such, the 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 is now the demodulated frequency change.
Still today, there are radio recievers that use a PLLs to directly de-
modulate the incoming frequency shift keyed modulated carrier.
We can calculate the 𝐾 𝑣𝑐𝑜 of the oscillator as shown below. The

inverters mostly act as switches, and when the PMOS is on, then the
rise time is controlled by the PMOS current mirror, the additional
𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 and the capacitor. For the calculation below we assume
that the pull-down of the capacitor by the NMOS does not affect
the frequency much.
The advantage with the above ring-oscillator is that we can control

the frequency of oscillation with 𝐼 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 and have a independent
𝐾 𝑣𝑐𝑜 based on the sizing of the 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 transistors.
𝑑𝑉
𝐼=𝐶
𝑑𝑡
𝐼 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 + 12 𝜇𝑝 𝐶 𝑜𝑥 𝑊
𝐿 (𝑉 𝐷𝐷 − 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 − 𝑉𝑡 ℎ )
2
𝑓 ≈
𝐶 𝑉 𝐷𝐷
2 𝑁
𝜕𝑓
𝐾 𝑣𝑐𝑜 = 2𝜋
𝜕𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙
𝜇𝑝 𝐶 𝑜𝑥 𝑊/𝐿
𝐾 𝑣𝑐𝑜 = 2𝜋
𝐶 𝑉 𝐷𝐷
2 𝑁
288 16 Oscillators
16.3.4 Digitally controlled oscillator
We can digitally control the oscillator frequency as shown below

by adding capacitors.
Today there are all digital loops where the oscillator is not really
a “voltage controlled oscillator”, but rather a “digital control
oscillator”. DCOs are common in all-digital PLLs.
Another reason to use digital frequency control is to compensate for

process variation. We know that mobility affects the 𝐾 𝑣𝑐𝑜 , as such,
for fast transistors the frequency can go up. We could measure
the free-running frequency in production, and compensate with a
digital control word.
16.3.5 Differential
Differential circuits are potentially less sensitive to supply noise
Imagine a single ended ring oscillator. If I inject a voltage onto the

input of one of the inverters that was just about to flip, I can either
delay the flip, or speed up the flip, depending on whether the
voltage pulse increases or decreases the input voltage for a while.
Such voltage pulses will lead to jitter.
Imagine the same scenario on a differential oscillator (think diff

pair). As long as the voltage pulse is the same for both inputs, then
no change will incur. I may change the current slightly, but that
depends on the tail current source.
Another cool thing about differential circuits is that it’s easy to

multiply by -1, just flip the wires, as a result, I can use a 2 stage
ring differential ring oscillator.
16.3.6 LC oscillator
Most radio’s are based on modulating information on-to a carrier

frequency, for example 2.402 GHz for a Bluetooth Low Energy
Advertiser. One of the key properties of the carrier waves is that it
must be “clean”. We’re adding a modulated signal on top of the
carrier, so if there is noise inherent on the carrier, then we add
noise to our modulation signal, which is bad.
Most ring oscillators are too high noise for radio’s, we must use a
inductor and capacitor to create the resonator.
Inductors are huge components on a IC. Take a look at the nRF51822

below, the two round inductors are easily identifiable. Actually,
based on the die image we can guess that there are two oscillators
in the nRF51822. Maybe it’s a multiple conversion superheterodyne
reciever
290 16 Oscillators
Below is a typical LC oscillator. The main resonance is set by the

L and C, while the tunability is provided by a varactor, a voltage
variable capacitor. Or with less fancy words, the gate capacitance
of a transistor, since the gate capacitance of a transistor depends
on the effective voltage, and is thus a “varactor”
The NMOS at the bottom provide the “negative transconductance”

to compensate for the loss in the LC tank.
16.4 Relaxation oscillators 291
I 1
C fate
Vent
1
𝑓 ∝√
𝐿𝐶
16.4 Relaxation oscillators
A last common oscillator is the relaxation oscillator, or “RC” oscil-

lator. By now you should be proficient enough to work through
the equations below, and understand how the circuit works. If not,
ask me.
o n
V
I U
R C
292 16 Oscillators
𝑉1 = 𝐼𝑅
𝑑𝑉
𝐼=𝐶
𝑑𝑡
𝐶𝑉2 𝐶𝐼𝑅
𝑑𝑡 = =
𝐼 𝐼
1 1
𝑓 = =
𝑑𝑡 𝑅𝐶
1 1
𝑓𝑜 = 𝑓 =
2 2𝑅𝐶
16.5.1 Crystal oscillators
The Crystal Oscillator - A Circuit for All Seasons
High-performance crystal oscillator circuits: theory and applica-

tion
Ultra-low Power 32kHz Crystal Oscillators: Fundamentals and

Design Techniques
A Sub-nW Single-Supply 32-kHz Sub-Harmonic Pulse Injection

Crystal Oscillator
16.5.2 CMOS oscillators
The Ring Oscillator - A Circuit for All Seasons
A Study of Phase Noise in CMOS Oscillators
An Ultra-Low-Noise Swing-Boosted Differential Relaxation Oscil-

lator in 0.18-um CMOS
Ultra Low Power Frequency Synthesizer

Low Power Radio 17
Keywords: Range, Antenna Size, Modulation, OFDM, GFSK, pi/4- 17.1 Data Rate . . . . . . 293
qpsk, 8-psk, 16 QAM, Bluetooth LE, LP RX, LNA, MIxer, AAF, 17.1.1 Data . . . . . . . . . . 293
ADC, BB 17.1.2 Rate . . . . . . . . . . 294
17.1.3 Data Rate . . . . . . . 294
Radio’s are all around us. In our phone, on our wrist, in our house, 17.2 Carrier Frequency &
there is Bluetooth, WiFi, Zigbee, LTE, GPS and many more. Range . . . . . . . . . 294
17.2.1 ISM (industrial, sci-
A radio is a device that receives and transmits light encoded with entific and medical)
information. The frequency of the light depends on the standard. bands . . . . . . . . . 294
How the information is encoded onto the light depends on the 17.2.2 Antenna . . . . . . . 295
standard. 17.2.3 Range (Friis) . . . . . 296
17.2.4 Range (Free space) . 297
Assume that we did not know any standards, what would we do if 17.2.5 Range (Real world) . 297
we wanted to make the best radio IC for gaming mice? 17.3 Power supply . . . . 298
There are a few key concepts we would have to know before we 17.3.1 Battery . . . . . . . . 298
decide on a radio type: Data Rate, Carrier Frequency and range, 17.4 Decisions . . . . . . 299
17.4.1 Modulation . . . . . 299
and the power supply.
17.4.2 BPSK . . . . . . . . . 300
17.4.3 Single carrier, or
multi carrier? . . . . 307
17.1 Data Rate 17.4.4 Use a Software
Defined Radio . . . . 308
17.1.1 Data 17.5 Bluetooth . . . . . . 309
17.5.1 Bluetooth Basic
Rate/Extended Data
A mouse reports on the relative X and Y displacement of the mouse
rate . . . . . . . . . . 310
as a function of time. A mouse has buttons. There can be many 17.5.2 Bluetooth Low En-
mice in a room, as such, they must have an address , so PCs can ergy . . . . . . . . . . 310
tell them apart. 17.6 Algorithm to design
state-of-the-art LE
A mouse must be low-power. As such, the radio cannot be on all
radio . . . . . . . . . 312
the time. The radio must start up and be ready to receive quickly. 17.6.1 LNTA . . . . . . . . . 313
We don’t know how far away from the PC the mice might be, as 17.6.2 MIXER . . . . . . . . 314
17.6.3 AAF . . . . . . . . . . 316
such, we don’t know the dB loss in the communication channel. As
17.6.4 ADC . . . . . . . . . 316
a result, the radio needs to have a high dynamic range, from weak
17.6.5 AD-PLL . . . . . . . 318
signals to strong signals. In order for the radio to adjust the gain 17.6.6 Baseband . . . . . . . 319
of the reciever we should include a pre-amble, a known sequence, 17.7 What do we really
for example 01010101, such that the radio can adjust the gain, and want, in the end? . . 319
also, recover the symbol timing. 17.8 Want to learn more? 321
All in all, the packets we send from the mouse may need to have
the following bits.
294 17 Low Power Radio
What Bits Why

X displacement 8
Y displacement 8
CRC 4 Bit errors
Buttons 16 One-hot coding. Most mice have buttons
Preamble 8 Synchronization
Address 32 Unique identifier
Total 76
17.1.2 Rate
Gamers are crazy for speed, they care about milliseconds. So our
mice needs to be able to send and receive data quite often.
Assume 1 ms update rate
17.1.3 Data Rate
To compute the data rate, let’s do a back of the envelope estimate

of the data, and the rate.
Application Data Rate > 76 bits/ms = 76 kbps
Assume 30 % packet loss
Raw Data Rate > 228 kbps
Multiply by
𝜋
> 716 kbps
Round to nearest nice number = 1Mbps
The above statements are a exact copy of what happens in industry

when we start design of something. We make an educated guess
and multiply by a number. More optimistic people would multiply
with 𝑒 .
17.2 Carrier Frequency & Range
17.2.1 ISM (industrial, scientific and medical) bands
There are rules and regulations that prevent us from transmitting

and receiving at any frequency we want. We need to pick one of the
ISM bands, or we need to get a license from governments around
the world.
17.2 Carrier Frequency & Range 295
For the ISM bands, there are regions, as seen below.
▶ Yellow: Region 1
▶ Blue: Region 2
▶ Pink: Region 3
Below is a table of the available frequencies, but how should we

pick which one to use? There are at least two criteria that should
be investigated. Antenna and Range.
Flow Fhigh Bandwidth Description

40.66 MHz 40.7 MHz 40 kHz Worldwide
433.05 MHz 434.79 MHz 1.74 MHz Region 1
902 MHz 928 MHz 26 MHz Region 2
2.4 GHz 2.5 GHz 100 MHz Worldwide
5.725 GHz 5.875 GHz 150 MHz Worldwide
24 GHz 24.25 GHz 250 MHz Worldwide
61 GHz 61.5 GHz 500 MHz Subject to local acceptance
17.2.2 Antenna
For a mouse we want to hold in our hand, there is a size limit to

the antenna. There are many types of antenna, but
assume
𝜆/4
is an OK antenna size (
𝜆 = 𝑐/ 𝑓
)
The below table shows the ISM band and the size of a quarter
wavelength antenna. Any frequency above 2.4 GHz may be OK
from a size perspective.
ISM band 𝜆/4 Unit OK/NOK

40.68 MHz 1.8 m :x:
433.92 MHz 17 cm :x:
915 MHz 8.2 cm
2450 MHz 3.06 cm :white_check_mark:
5800 MHz 1.29 cm :white_check_mark:
24.125 GHz 3.1 mm :white_check_mark:
61.25 GHz 1.2 mm :white_check_mark:
17.2.3 Range (Friis)
One of the worst questions a radio designer can get is “What is

the range of your radio?”, especially if the people asking are those
that don’t understand physics, or the real world. The answer to the
question is incredibly complicated, as it depends on exactly what
is between two devices talking.
If we assume, however, that there is only free space, and no real

reflections from anywhere, then we can make an estimate of the
range.
Assume no antenna gain, power density p at distance D is
𝑃𝑇𝑋
𝑝=
4𝜋𝐷 2
Assume reciever antenna has no gain, then the effective aperture

is
𝜆2
𝐴𝑒 =
4𝜋
Power received is then
2
𝑃𝑇𝑋 𝜆

𝑃𝑅𝑋 = 2
𝐷 4𝜋
Or in terms of distance

𝑃𝑇𝑋 −𝑃𝑅𝑋 +20𝑙𝑜 𝑔10 𝑐
4𝜋 𝑓
𝐷 = 10 20
17.2 Carrier Frequency & Range 297
17.2.4 Range (Free space)
If we take the ideal equation above, and use some realistic numbers
for TX and RX power, we can estimate a range.
Assume TX = 0 dBm, assume RX sensitivity is -80 dBm
20 𝑙𝑜 𝑔10 𝑐/4𝜋 𝑓 [dB]

Freq D [m] OK/NOK
915 MHz -31.7 260.9 :white_check_mark:
2.45 GHz -40.2 97.4 :white_check_mark:
5.80 GHz -47.7 41.2 :white_check_mark:
24.12 GHz -60.1 9.9 :x:
61.25 GHz -68.2 3.9 :x:
160 GHz -76.52 1.5 :x:
17.2.5 Range (Real world)
In the real world, however, the
path loss factor,

𝑛 ∈ [1.6, 6]
,
𝑃𝑇𝑋 −𝑃𝑅𝑋 +20 𝑙𝑜 𝑔10 𝑐
4𝜋 𝑓
𝐷 = 10 𝑛×10
So the real world range of a radio can vary more than an order of
magnitude. Still, 2.4 GHz seems like a good choice for a mouse.
20 𝑙𝑜 𝑔10 𝑐/4𝜋 𝑓

D@n=2 D@n=6
Freq [dB] [m] [m] OK/NOK
2.45 GHz -40.2 97.4 4.6 :white_-
check_-
mark:
5.80 GHz -47.7 41.2 3.45 :white_-
check_-
mark:
24.12 -60.1 9.9 2.1 :x:
GHz
17.3 Power supply
We could have a wired mouse for power, but that’s boring. Why
would we want a wired mouse to have wireless communication?
It must be powered by a battery, but what type of battery?
There exists a bible of batteries, see picture below. It’s worth a

read if you want to dive deeper into chemistry and properties of
primary (non-chargeable) and secondary (chargeable) cells.
17.3.1 Battery
Mouse is maybe AA, 3000 mAh

17.4 Decisions 299
Cell Chemistry Voltage (V) Capacity (Ah)

AA LiFeS2 1.0 - 1.8 3
2xAA LiFeS2 2.0 - 3.6 3
AA Zn/Alk/MnO2 0.8 - 1.6 3
2xAA Zn/Alk/MnO2 1.6 - 3.2 3
17.4 Decisions
Now we know that we need a 1 Mbps radio at 2.4 GHz that runs
of a 1.0 V - 1.8 V or 2.0 V - 3.6 V supply.
Next we need to decide what modulation scheme we want for our

light. How should we encode the bits onto the 2.4 GHz carrier
wave?
17.4.1 Modulation
Any modulation can be described by the function below.
𝐴𝑚 (𝑡) × 𝑐𝑜𝑠 2𝜋 𝑓𝑐𝑎𝑟𝑟𝑖𝑒𝑟 (𝑡)𝑡 + 𝜙 𝑚 (𝑡)

The amplitude of the carrier can be modulated, or the phase of the

carrier.
People have been creative over the last 50 years in terms of encoding
bits onto carriers. Below is a small excerpt of some common
schemes.
Scheme Acronym Pro Con

Binary phase BPSK Simple Not constant
shift keying envelope
Quadrature QPSK 2bits/symbol Not constant
phase-shift envelope
keying
Offset QPSK OQPSK 2bits/symbol Constant
envelope with
half-sine
pulse shaping
Gaussian GFSK 1 bit/symbol Constant
Frequency envelope
Shift Keying
Quadrature QAM > 1024 Really
amplitude bits/symbol non-constant
modulation envelope
17.4.2 BPSK
In binary phase shift keying the 1 and 0 is encoded in the phase

change. Change the phase 180 degrees and we’ve transitioned from
a 0 to a 1. Do another 180 degrees and we’re back to where we
were.
It’s common to show modulation schemes in a constellation dia-

gram with the real axis and the complex axis. For the real light we
send the phase and amplitude is usually real.
I say usually, because in quantum mechanics, and the time evolution

of a particle, the amplitude of the wave function is actually a
complex variable. As such, nature is actually complex at the most
fundamental level.
But for now, let’s keep it real in the real world.
Still, the maths is much more elegant in the complex plane.
The equation for the unit circle is 𝑦 = 𝑒 𝑖(𝜔𝑡+𝜙) where 𝜙 is the phase,
and 𝜔 is the angular frequency.
Imagine we spin a bike wheel around at a constant frequency

(constant 𝜔 ), on the bike wheel there is a red dot. If you keep your
eyes open all the time, then the red dot would go round and round.
But imagine that you only opened your eyes every second for a
brief moment to see where the dot was. Sometimes it could be on
the right side, sometimes on the left side. If our “eye opening rate”,
or your sample rate, matched how fast the “wheel rotator” changed
the location of the dot, then you could receive information.
Now imagine you have a strobe light matched to the “normal” car-
rier frequency. If one rotation of the wheel matched the frequency
of the strobe light, then the red dot would stay in exactly the same
place. If the wheel rotation was slightly faster, then the red dot
would move one way around the circle at every strobe. If the wheel
rotation was slightly slower, the red dot would move the other way
around the circle.
That’s exactly how we can change the position in the constellation.

We increase the carrier frequency for a bit to rotate 180 degrees,
and we can decrease the frequency to go back 180 degrees. In
this example the dot would move around the unit circle, and the
amplitude of the carrier can stay constant.
17.4 Decisions 301
X X
R
There is another way to change phase 180 degrees, and that’s simply
to swap the phase in the transmitter circuit. Imagine as below we
have a local oscillator driving pseudo differential common source
stages with switches on top. If we flip the switches we can change
the phase 180 degrees pretty fast.
A challenge is, however, that the amplitude will change. In general,

constant envelope (don’t change amplitude) modulation is less
bandwidth efficient (slower) than schemes that change both phase
and amplitude.
met
bo Jo bo I
Lo
Standards like Zigbee used offset quadrature phase shift keying,

with a constellation as shown below. With 4 points we can send 2
bits per symbol.
17.4 Decisions 303
jo
I
A É Fret B
q
R
LO
D
ti
Be it
LEE
I
In ZigBee, or 802.15.4 as the standard is called, the phase changes
is actually done with a constant envelope.
Q
The nice thing about constant envelope is that the radio transmitter
can be simple. We don’t need to change the amplitude. If we
have a PLL as a local oscillator, where we can change the phase
(or frequency), then we only need a power amplifier before the
LO
antenna.
jo pa
t B
q A
For phase and amplitude modulation, or complex transmitters, we
need a way to change the amplitude and phase. What a shocker.
LO pi
There are two ways to do that. A polar architecture where phase
change is done in the PLL, and amplitude in the power amplifier.
E
jo pa
I B
Fret
q A
R
LO pi
jo pa
LEE
I
A É Fret B
I q A
Or a Cartesian architecture where we make the in-phase compo-
nent, and quadrature-phase components in digital, then use two
R
pi pa
digital to analog converters, and a set of complex mixers to encode
onto the carrier. The powerLO amplifier would not need to change
Q
the amplitude, but it does need to be linear.
D
ti
Be it
LEE
I
LO
pa
Q
LO
We can continue to add constellation points around the unit circle.

Below we can see 8-PSK, where we can send 3-bits per symbol.
Assuming we could shift position between the constellation points
at a fixed rate, i.e 1 mega symbols per second. With 1-bit per symbol
we’d get 1 Mbps. With 3-bits per symbol we’d get 3 Mbps.
We could add 16 points, 32 points and so on to the unit circle,

however, there is always noise in the transmitter, which will create
a cloud around each constellation point, and it’s harder and harder
to distinguish the points from each other.
17.4 Decisions 305
j j
IR
Bluetooth Classic uses 𝜋/4-DQPSK and 8DPSK.
DPSK means differential phase shift keying. Think about DPSK

like this. In the QPSK diagram above the symbols (00,01,10,11) are
determined by the constellation point 1 + 𝑗 , 1 − 𝑗 and so on. What
would happen if the constellation rotated slowly? Would 1 + 𝑗 turn
into 1 − 𝑗 at some point? That might screw up our decoding if
the received constellation point was at 1 + 0 𝑗 , we would not know
what it was.
If we encoded the symbols as a change in phase instead (differen-

tial), then it would not matter if the constellation rotated slowly. A
change from 1 + 𝑗 to 1 − 𝑗 would still be 90 degrees.
Why would the constellation rotate you ask? Imagine the trans-
mitter transmits at 2 400 000 000 Hz. How does our reciever
generate the same frequency? We need a reference and a PLL.
The crystal-oscillator reference has a variation of +-50 ppm, so
2.4 𝑒 9 × 50/1 𝑒 6 = 120 kHz.
Assume our receiver local oscillator was at 2 400 120 000 Hz. The
transmitter sends 2 400 000 000 Hz + modulation. At the reciever we
multiply with our local oscillator, and if you remember your math,
multiplication of two sine creates a sum and a difference between
the two frequencies. As such, the low frequency part (the difference
between the frequencies) would be 120 kHz + modulation. As a
result, our constellation would rotate 120 000 times per second.
Assuming a symbol rate of 1MS/s our constellation would rotate
roughly 1/10 of the way each symbol.
In DPSK the rotation is not that important. In PSK we have to

measure the carrier offset, and continuously de-rotate the constel-
lation.
Most radios will de-rotate somewhat based on the preamble, for

example in Bluetooth Low Energy there is an initial 10101010
sequence that we can use to estimate the offset between TX and
RX carriers, or the frequency offset.
The 𝜋/4 part of 𝜋/4 − 𝐷𝑄𝑃𝑆𝐾 just means we actively rotate

the constellation 45 degrees every symbol, as a consequence, the
amplitude never goes through the origin. In the transmitter circuit,
it’s difficult to turn the carrier off, so we try to avoid the zero point
in the constellation.
I don’t think 16PSK is that common, at 4-bits per symbol it’s

common to switch to Quadrature Amplitude Modulation (QAM),
as shown below. The goal of QAM is to maximize the distance
between each symbol. The challenge with QAM is the amplitude
modulation. The modulation scheme is sensitive to variations in
the transmitter amplitude. As such, more complex circuits than
8PSK could be necessary.
If you wanted to research “new fancy modulation schemes” I’d

think about Sphere packing.
17.4 Decisions 307
Irx
Ei a
17.4.3 Single carrier, or multi carrier?
Assume we wanted to send 1024PLL free

AD Mbps over the air. We could
choose a bandwidth of a about 1 GHz with 1-bit per symbol, or
have a bandwidth of 1 MHz if we sent 1024 QAM at 1MS/s. Both
cases would look like the figure below.
In both cases we get problems with the physical communication

channel, the change in phase and amplitude affect what is received.
For a 1 GHz bandwidth at 2.4 GHz carrier we’d have problems with
the phase. At 1024 QAM we’d have problems with the amplitude.
And I I Ault
Q
TX RX a S
9m glt
Back in 1966 Orthogonal frequency division multiplexing was

introduced to deal with the communication channel. In OFDM we
modulate a number of sub-carriers in the frequency space with
our wanted modulation scheme (BPSK, PSK, QAM), then doeilwitta.lt
an
f e witta
Ainverse I I Af
fourier transform to get the time domain signal, mix on
to the carrier, and transmit. At the reciever we take an FFT and
IFFT TX FFTin figure
RXexample
do demodulation in the frequency space. See a
below. Q
outta
A.ltei
wt94 actei
And I I Ault
Q
TX RX a S
9m glt
The name “multiple carriers” is a bit misleading. Although there
are multiple carriers on the left and right side of the figure, there
is normally still just one carrier in the TX/RX.
witta eilwitta.lt
Af e I I Af
IFFT TX RX a FFT
Q
outta
A.ltei
wt94 actei
There are more details in OFDM than the simple statement above,
but the details are just to fix challenges, such as “How do I recover
the symbol timing? How do I correct for frequency offset? How do
I ensure that my time domain signal terminates correctly for every
FFT chunk”
The genius with OFDM is that we can pick a few of the sub-carriers
to be pilot tones that carry no new information. If we knew exactly
what was sent in phase and amplitude, then we could measure the
phase and amplitude change due to the physical communication
channel, and we could correct the frequency space before we tried
to de-modulate.
It’s possible to do the same with single carrier modulation also.

Imagine we made a 128-QAM modulation on a single carrier. As
long as we constructed the time domain signal correctly (cyclic
prefix to make the FFT work nicely, some preamble to measure the
communication channel, then we could take an FFT at the reciever,
correct the phase and amplitude, do an IFFT and demodulate the
time-domain signal as normal.
In radio design there are so many choices it’s easy to get lost.
17.4.4 Use a Software Defined Radio
For our mouse, what radio scheme should we choose? One common
instances of “how to make a choice” in industry is “Delay the choice
as long as possible so your sure the choice is right”.
Maybe the best would be to use a software defined radio reciever?

Something like the picture below, an antenna, low noise amplifier,
and a analog-to-digital converter. That way we could support any
transmitter. Fantastic idea, right?
17.5 Bluetooth 309
LNA ADC
Well, lets check if it’s a good idea. We know we’ll use 2.4 GHz, so
we need about 2.5 GHz bandwidth, at least. We know we want
good range, so maybe 100 dB dynamic range. In analog to digital
converter design there are figure of merits, so we can actually
compute a rough power consumption for such an ADC.
ADC FOM
𝑃
=
2𝐵𝑊 2𝑛
State of the art FOM

≈ 5 fJ/step
𝐵𝑊 = 2.5 GHz
𝐷𝑅 = 100 dB = (96 − 1.76)/6.02 ≈ 16 bit
𝑃 = 5 fF × 5 GHz × 216 = 1.6 W
At 1.6 W our mouse would only last for 2 hours. That’s too short.
It will never be a low power idea to convert the full 2.5 GHz
bandwidth to digital, we need some bandwidth selectivity in the
receive chain.
17.5 Bluetooth
Bluetooth was made to be a “simple” standard and was introduced

in 1998. The standard has continued to develop, with Low Energy
introduced in 2010. The latest planned changes can be seen at
Specifications in Development.
17.5.1 Bluetooth Basic Rate/Extended Data rate
▶ 2.400 GHz to 2.4835 GHz

▶ 1 MHz channel spacing
▶ 78 Channels
▶ Up to 20 dBm
▶ Minimum -70 dBm sensitivity (1 Mbps)
▶ 1 MHz GFSK (1 Mbps), pi/4-DQPSK (2 Mbps), 8DPSK (3
Mbps)
You’ll find BR/EDR in most audio equipment, cars and legacy

devices. For new devices (also audio), there is now a transition to
Bluetooth Low Energy.
17.5.2 Bluetooth Low Energy
▶ 2.400 GHz to 2.480 GHz

▶ 2 MHz channel spacing
▶ 40 Channels (3 primary advertising channels)
▶ Up to 20 dBm
▶ Minimum -70 dBm sensitivity (1 Mbps)
▶ 1 MHz GFSK (1 Mbps, 500 kbps, 125 kbps), 2 MHz GFSK (2
Mbps)
Below are the Bluetooth LE channels. The green are the advertiser
channels, the blue are the data channels, and the yellow is the WiFi
channels.
The advertiser channels have been intentionally placed where there

is space between the WiFi channels to decrease the probability of
collisions.
Any Bluetooth LE peripheral will advertise it’s presence, it will

wake up once in a while (every few hundred milliseconds, to
seconds) and transmit a short “I’m here” packet. After transmitting
it will wait a bit in receive to see if anyone responds.
17.5 Bluetooth 311
A Bluetooth LE central will camp in receive on a advertiser channel

and look for these short messages from peripherals. If one is
observed, the Central may choose to respond.
Take any spectrum analyzer anywhere, and you’ll see traffic on

2402, 2426, and 2480 MHz.
In a connection a central and peripheral (the master/slave names

below have been removed from the spec, that was a fun update
to a 3500 page document) will have agreed on an interval to talk.
Every “connection interval” they will transmit and receive data.
The connection interval is tunable from 7.5 ms to seconds.
Bluetooth LE is the perfect standard for wireless mice.
For further information Building a Bluetooth application on nRF

Connect SDK
Bluetooth Specifications in Development

17.6 Algorithm to design state-of-the-art LE

radio
▶ Find most recent digest from International Solid State Circuit

Conference (ISSCC)
▶ Find Bluetooth low energy papers
▶ Pick the best blocks from each paper
A typical Bluetooth radio may look something like the picture

below. There would be a single antenna for both RX and Tx. There
will be some way to combine the transmit and receive path in a
match, or balun.
The receive chain would have a LNA, mixer, anti-alias filter and
analog-to-digital converters. It’s likely that the receive path would
be complex (in-phase and quadrature phase) after mixer.
There would be a local oscillator (all-digital phase-locked-loop)

to provide the frequency to the mixers and transmit path, which
could be either polar or Cartesian.
AAF ADC
IRX
MIX
LNA
AAF ADC QRX
I
MATCH
FREE
ADPLL
ITX
TX QTX
In the typical radio we’ll need the blocks below. I’ve added a column
for how many people I would want if I was to lead development
of a new radio.
Complexity
Blocks Key parameter Architecture(nr people)
Antenna Gain, impedance lambda/4 <1
RF match loss, input impedance PI- <1
match
Low noise NF, current, linearity LNTA 1
amp
17.6 Algorithm to design state-of-the-art LE radio 313
Complexity
Blocks Key parameter Architecture(nr people)
Mixer NF, current, linearity Passive 1
Anti-alias NF, current, linearity Active- 1
filter RC
ADC Sample rate, dynamic NS-SAR 1-2
range, linearity
PLL Phase noise, current AD-PLL 2-3
Baseband Eb/N0, gate count, SystemVerilog
> 10
current.
17.6.1 LNTA
The first thing that must happen in the radio is to amplify the noise
as early as possible. Any circuit has inherent noise, be it thermal-,
flicker-, burst-, or shot-noise. The earlier we can amplify the input
noise, the less contribution there will be from the radio circuits.
The challenges in the low noise amplifier is to provide the right

gain. If there is a strong input signal, then reduce the gain. If there
is a low input signal, then increase the gain.
One way to implement variable gain is to reconfigure the LNA. For

an example, see
30.5 A 0.5V BLE Transceiver with a 1.9mW RX Achieving -96.4dBm

Sensitivity and 4.1dB Adjacent Channel Rejection at 1MHz Offset
in 22nm FDSOI
A typical Low Noise Transconductance Amplifier is seen below.

It’s a combination of both a common source, and a common gate
amplifier. The current in the NMOS and PMOS is controlled by
Vgp and Vgn. Keep in mind that at RF frequencies the signals are
weak, so it’s easy to provide the DC for the LNA with a resistor to
a diode connected PMOS or NMOS.
In a LNA the input impedance must be matched to what is required

by the antenna/match in order to have maximum power transfer,
that’s the role of the inductors/capacitors.
Vge Mixer
THE van
17.6.2 MIXER
In the mixer we multiply the input signal with our local oscillator.
Most often a complex mixer is used. There is nothing complex
about complex signal processing, just read
Complex signal processing is not complex
In order to reduce power, it’s most common with a passive mixer

as shown below. A passive mixer is just MOS that we turn on and
off with 25% duty-cycle. See example in
A 370uW 5.5dB-NF BLE/BT5.0/IEEE 802.15.4-Compliant Receiver

with >63dB Adjacent Channel Rejection at >2 Channels Offset in
22nm FDSOI
I
m
Is
Q2
Vn
I
LNA Un
a
Q2
un
Q
To generate the quadrature and in-phase clock signals, which must

be 90 degrees phase offset, it’s common to generate twice the
frequency in the local oscillator (4.8 GHz), and then divide down
to 4 2.4 GHz clock signals.
If the LO is the same as the carrier, then the modulation signal will
be at DC, often called direct conversion.
The challenge at DC is that there is flicker noise, offset, and burst

noise. The modulation type, however, can impact whether low
frequency noise is an issue. In OFDM we can choose to skip
the sub-carriers around 0 Hz, and direct conversion works well.
An advantage with direct conversion is that there is no “image
frequency” and we can use the full complex bandwidth.
For FSK and direct conversion the low frequency noise can cause
issues, as such, it’s common to offset the LO from the transmitted
signal, for example 4 MHz offset. The low frequency noise problem
disappears, however, we now have a challenge with the image

frequency (-4 MHz) that must be rejected, and we need an increased
bandwidth.
There is no “one correct choice”, there are trade-offs that both ways.
KISS (Keep It Simple Stupid) is one of my guiding principles when
working on radio architecture.
These days most de-modulation happens in digital, and we need

to convert the analog signal to digital, but first AAF.
17.6.3 AAF
The anti alias filter rejects frequencies that can fold into the band
of interest due to sampling. A simple active-RC filters is often good
enough.
We often need gain in the AAF, as the LNA does not have sufficient
gain for the weakest signals. -100 dBm in 50 ohm is 6.2 nV RMS,
while input range of an ADC may be 1 V. Assume we place
the lowest input signal at 0.1 V, so we need a voltage gain of
20 log(0.1/6.2 𝑒 − 9) = 76dB in the reciever.
Gy
G Gs
or
Ca
L
CB
Vi G
63
Vo
17.6.4 ADC
Aaah, ADCs, an IP close to my heart. I did my Ph.d and Post-Doc

on ADCs, and the Ph.D students I’ve co-supervised have worked
on ADCs.
At NTNU there have been multiple students through the years that
have made world-class ADCs, and there’s still students at NTNU
working on state-of-the-art ADCs.
These days, a good option is a SAR, or a Noise-Shaped SAR.

If I were to pick, I’d make something like A 68 dB SNDR Compiled

Noise-Shaping SAR ADC With On-Chip CDAC Calibration as
shown in the figure below.
Or if I did not need high resolution, I’d choose my trusty A

Compiled 9-bit 20-MS/s 3.5-fJ/conv.step SAR ADC in 28-nm
FDSOI for Bluetooth Low Energy Receivers.
The main selling point of that ADC was that it’s compiled from a
JSON file, a SPICE file and a technology file into a DRC/LVS clean
layout.
I also included a few circuit improvements. The bottom plate of

the SAR capacitor is in the clock loop for the comparator (DN0,
DP1 below), as such, the delay of the comparator automatically
adjusts with capacitance corner, so it’s more robust over corners
CK D8 CK D7 CK D6 CK D5 CK D4 CK D3 CK D2 CK D1 CK D0
DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N
CI CO CI CO CI CO CI CO CI CO CI CO CI CO CI CO CI CO
LOGIC[8] LOGIC[7] LOGIC[6] LOGIC[5] LOGIC[4] LOGIC[3] LOGIC[2] LOGIC[1] LOGIC[0] CK
CK EI EO EI EO EI EO EI EO EI EO EI EO EI EO EI EO EI EO
DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 1 DN 0 DP 1 DN 0 DP 1 DN 0 DP 1 DN 0 X1
X2
CK
CK CM P
VP +
P
VN −
Bootstrapped 28 · CU N IT 27 · CU N IT 26 · CU N IT 25 · CU N IT 24 · CU N IT 23 · CU N IT 22 · CU N IT 21 · CU N IT 20 · CU N IT N
NMOS switches
(a)
VDD VDD VDD VDD
VREF VREF VDD VDD

CK MP 0 MP 3 CK MP 4 CK MP 5
MP 6 MP 7
DP 0 DN 0 DN 1 DP 1
N MP 2 EI MN 6 EI MN 9
A
EI MN 0 P MP 1 MN 5 MN 8
EO B
P MN 1 N MN 2 MN 3 P MN 4 N MN 7 CK MN 10
CI CO
(b) (c) (d)
The compiled nature also made it possible to quickly change

the transistor technology. Below is a picture with 180 nm FDSOI
transistors on the left, and 28 nm FDSOI transistors on the right.
I detest doing anything twice, so I love the fact that I never have to
re-draw that ADC again. I just fix the technology file (and maybe
some tweaks to the other files), and I have a completed ADC.
Comparator
Logic
106µm
CDAC
80µm
Switch
39µm
40µm
(a) (b)
17.6.5 AD-PLL
The phase locked loop is the heart of the radio, and it’s probably
the most difficult part to make. Depends a bit on technology, but
these days, All Digital PLLs are cool. Start by reading Razavi’s PLL
book.
You can spend your life on PLLs.
food
ED N
fin to
yes
fmod
AD-PLL with Bang-Bang phase detector for steady-state

17.7 What do we really want, in the end? 319
Freq. offset estimator Cal

n
-n
z CLK estimator delay cal?
- ferror
DCO Cal. Engine
lf_state fine mode coarse
+
CLK Loop Filter
1 coarse
enable set_state
Sync. Phase Error
0 a0 + + DCO OUT
z -1 0
Counter Logic 1 + +
a1
BB-PD z -1
SS
D Q Detect
Q
enable
17.6.6 Baseband
Once the signal has been converted to digital, then the de-
modulation, and signal fixing start. That’s for another course, but
there are interesting challenges.
Baseband block Why

Mixer? If we’re using low intermediate
frequency to avoid DC offset
problems and flicker noise
Channel filters? If the AAF is insufficient for
adjacent channel
Power detection To be able to control the gain of
the radio
Phase extraction Assuming we’re using FSK
Timing recovery Figure out when to slice the
symbol
Bit detection single slice, multi-bit slice,
correlators etc
Address detection Is the packet for us?
Header detection What does the packet contain
CRC Does the packet have bit errors
Payload de-crypt Most links are encrypted by
AES
Memory access Payload need to be stored until
CPU can do something
17.7 What do we really want, in the end?
The reciever part can be summed up in one equation for the

sensitivity. The noise in a certain bandwidth. The Noise Figure
of the analog reciever. The Energy per bit over Noise of the de-
modulator.
𝑃𝑅𝑋𝑠𝑒𝑛𝑠 = −174 𝑑𝐵𝑚 + 10 × 𝑙𝑜 𝑔 10(𝐷𝑅) + 𝑁 𝐹 + 𝐸𝑏/𝑁 0

for example, for nRF5340
𝑃𝑅𝑋𝑠𝑒𝑛𝑠 + 174 − 60 = 𝑁 𝐹 + 𝐸𝑏/𝑁 0 = 17𝑑𝐵
In the block diagram of the device the radio might be a small box,
and the person using the radio might not realize how complex the
radio actually is.
I hope you understand now that it’s actually complicated.

A 0.5V BLE Transceiver with a 1.9mW RX Achieving -96.4dBm

Sensitivity and 4.1dB Adjacent Channel Rejection at 1MHz Offset in
22nm FDSOI, M. Tamura, Sony Semiconductor Solutions, Atsugi,
Japan, 30.5, ISSCC 2020
A 370uW 5.5dB-NF BLE/BT5.0/IEEE 802.15.4-Compliant Receiver

with >63dB Adjacent Channel Rejection at >2 Channels Offset in
22nm FDSOI, B. J. Thĳssen, University of Twente, Enschede, The
Netherlands
A 68 dB SNDR Compiled Noise-Shaping SAR ADC With On-Chip

CDAC Calibration, H. Garvik, C. Wulff, T. Ytterdal
A Compiled 9-bit 20-MS/s 3.5-fJ/conv.step SAR ADC in 28-nm

FDSOI for Bluetooth Low Energy Recievers, C. Wulff, T. Ytterdal
Cole Nielsen, https://github.com/nielscol/thesis_presentatio

ns
“Python Framework for Design and Simulation of Integer-N AD-

PLLs”, Cole Nielsen, https://github.com/nielscol/tfe4580-repor
t/blob/master/report.pdf
Design of CMOS Phase-Locked Loops, Behzad Razavi, University

of California, Los Angeles
Energy Sources 18
18.1 Thermoelectric . . . 325
18.1.1 Radioisotope Ther-
Integrated circuits are wasteful of energy. Digital circuits charge moelectric generator 329
transistor gates to change states, and when discharged, the charges 18.1.2 Thermoelectric
are dumped to ground. In analog circuits the transconductance generators . . . . . . 330
requires a DC current, a continuous flow of charges from positive 18.2 Photovoltaic . . . . . 331
supply to ground. 18.3 Piezoelectric . . . . 333
18.4 Electromagnetic . . 335
18.4.1 “Near field” harvest-
ing . . . . . . . . . . . 335
Integrated circuits are incredibly useful though. Life without would 18.4.2 Ambient RF Harvest-
be different. ing . . . . . . . . . . . 336
18.5 Triboelectric genera-
tor . . . . . . . . . . . 337
A continuous effort from engineers like me have reduced the 18.6 Comparison . . . . . 340
power consumption of both digital and analog circuits by order of 18.7 Want to learn more? 341
magnitudes since the invention of the transistor 75 years ago.
One of the first commercial ADCs, the DATRAC on page 24, was
a 11-bit 50 kSps that consumed 500 W. That’s Walden figure of
merit of 4 𝜇J/conv.step. Today’s state-of-the-art ADCs in the same
sampling range have a Walden figure of merit of 0.6 fJ/conv.step.
4 𝜇 / 0.6 f = 8.1e9, a difference in power consumption of almost 10

billion times !!!
Improvements to power consumption have become harder and

harder, but I believe there is still far to go before we cannot reduce
power consumption any more.
Towards a Green and Self-Powered Internet of Things Using Piezo-

electric Energy Harvesting [1] has a nice overview of power con-
sumption of technologies, seen in the next figures below.
In the context of energy harvesting, there is energy in electromag-

netic fields, temperature, and mechanical stress, and there are ways
to translate between them the energy forms.
324 18 Energy Sources
Below we can see a figure of the potential energy that can be

harvested per volume, and the type power consumption of tech-
nologies [1].
As devices approach average power consumption of 𝜇𝑊 it becomes

possible to harvest the energy from the environment, and do away
with the battery.
For wireless standards, there are some that can be run on en-
18.1 Thermoelectric 325
ergy harvesting. Below is an overview from [1]. Many of us will

have a NFC card in our pocket for payment, or entry to build-
ings. NFC card has a integrated circuit that is powered from the
electromagnetic field from the NFC reader.
Other standards, like Bluetooth, WiFi, LTE are harder to run battery
less, because the energy requirement above 1 mW.
Technologies like Bluetooth LE, however, can approach < 10 𝜇W

for some applications, although the burst power may still be 10
mW to 100 mW. As such, although the average power is low, the
energy harvesting cannot support peak loads and a charge storage
device is required (battery, super-capacitor, large capacitor).
I’d like to give you an introduction to the possible ways of harvest-

ing energy. I know of five methods: - thermoelectric - photovoltaic
- piezoelectric - electromagnetic - triboelectric
18.1 Thermoelectric
Apply heat to one end of a metal wire, what happens to the free
electrons? As we heat the material we must increase the energy
of the free electrons at the hot end of the wire. The atoms wiggle
more, and when the free electrons scatter off the atomic structure
there should be an exchange of energy. Think of the electrons at
the hot side as high energy electrons, while on the cold side there
are low energy electrons, I think.
There will be diffusion current of electrons in both directions in

the material, however, if the mobility of electrons in the material is
dependent on the energy, then we would get a difference in current
of low energy electrons and high energy electrons. A difference in
current would lead to a charge difference at the hot end and cold
end, which would give a difference in voltage.
Take a copper wire, bend it in half, heat the end with the loop, and
measure the voltage at the cold end. Would we measure a voltage
difference?
NO, there would not be a voltage difference between the two ends
of the wire. The voltage on the loop side would be different, but on
the cold side, where we have the ends, there would be no voltage
difference.
Gauss law tell us that inside a conductor there cannot be a static

field without a current. As such, if there was a voltage difference
between the cold ends, it would quickly dissipated, and no DC
current would flow.
The voltage difference in the material between the hot and cold
end will create currents, but we can’t use them if we only have one
type of material.
Imagine we have Iron and copper wires, as shown below, and we

heat one end. In that case, we can draw current between the cold
ends.
The voltage difference at the hot and cold end is described by the
Seebeck coefficient
Imagine two parallel wires with different Seebeck coefficients, one

of copper (6.5 𝜇𝑉/𝐾 ) and one of iron (19 𝜇/𝐾 ). We connect them
at the hot end. The voltage difference between hot and cold would
be higher in the iron, than in the copper. At the cold end, we would
now measure a difference in voltage between the wires!
In silicon, the Seebeck coefficient can be modified through doping.

A model of Seebeck coefficient is shown below. The value of the
Seebeck coefficient depends on the location of the Fermi level in
relation to the Conduction band or the V valence band.
In the picture below we have a silicon (the cyan and yellow col-
ors).
Assume we dope with acceptors (yellow, p-type), that shifts the

Fermi level closer to the Valence band (𝐸𝑉 ), and the dominant
current transport will be by holes, maybe we get 1 mV/K from the
picture above.
For the material doped with donors (cyan, n-type) the Fermi level
is shifted towards the Conduction band (𝐸𝐶 ), and the dominant
charge transport is by electrons, maybe we get -1 mV/K from the
picture above.
Assume we have a temperature difference of 50 degrees, then

maybe we could get a voltage difference at the cold end of 100 mV.
That’s a low voltage, but is possible to use.
The process can be run in reverse. In the picture below we force a

current through the material, we heat one end, and cool the other.
Maybe you’ve heard of Peltier elements.
18.1.1 Radioisotope Thermoelectric generator
Maybe you’ve heard of a nuclear battery. Sounds fancy, right? Must

be complicated, right?
Not really, take some radioactive material, which generates heat,

stick a thermoelectric generator to the hot side, make sure you can
cool the cold side, and we have a nuclear battery.
Nuclear batteries are “simple”, and ultra reliable. There’s not

really a chemical reaction. The nucleus of the radioactive material
degrades, but not fast. In the thermoelectric generator, there are
no moving parts.
In a normal battery there is a chemical reaction that happens when

we pull a current. Atoms move around. Eventually the chemical
battery will change and degrade.
Nuclear batteries were used in Voyager, and they still work to this
day. The nuclear battery is the round thing underneath Voyager
in the picture below. The radioisotopes provide the heat, space
provides the cold, and voila, 470 W to run the electronics.
18.1.2 Thermoelectric generators
Assume a we wanted to drive a watch from a thermoelectric

generator (TEG). The skin temperature is maybe 33 degrees Celsius,
while the ambient temperature is maybe 23 degrees Celsius on
average.
From the model of a thermoelectric generator below we’d get a

voltage of 10 mV to 500 mV, too low for most integrated circuits.
In order to drive an integrated circuit we’d need to boost the voltage

to maybe 1.8 V.
The main challenge with thermoelectric generators is to provide a

cold-boot function where the energy harvester starts up at a low
voltage.
In silicon, it is tricky to make anything work below some thermal

voltages (kT/q). We at least need about 3 – 4 thermal voltages to
make anything function.
The key enabler for an efficient, low temperature differential, energy

harvester is an oscillator that works at low voltage (i.e 75 mV). If
we have a clock, then we can boost with capacitors
In A 3.5-mV Input Single-Inductor Self-Starting Boost Converter

With Loss-Aware MPPT for Efficient Autonomous Body-Heat En-
ergy Harvesting they use a combination of both switched capacitor
and switched inductor boost.
18.2 Photovoltaic 331
Ll or
1 50MY ÉITga
18.2 Photovoltaic
man
In silicon, photons can knock out electron/hole pairs. If we have

É
a PN junction, then it’s possible to separate the electron/holes
before they recombine as shown in figure below.
piezo
An electron/hole pair knocked out in the depletion region (1) will
separate due to the built-in field. The hole will go to P and the
electron to N. This increases the voltage VD across the diode.
Pr
A similar effect will occur if the electron/hole pair is knocked out
in the P region (2). Although the P region has an abundance of
holes, the electron will not recombine immediately. If the electron
diffuses close to the depletion region, then it will be swept across
to the N side, and further increase VD.
On the N-side the same minority carrier effect would further

increase the voltage (3).
B A
P
minorities
imminent 3
up t
Va P
A circuit model of a Photodiode can be seen in figure below, where
Vb P
it is assumed that a single photodiode is used. It is possible to stack
photodiodes to get a higher output voltage.
Vb P
man
piezo
Pr
As the load current is increased, the voltage VD will drop. As the
photo current is increased, the voltage VD will increase. As such,
there is an optimum current load where there is a balance between
the photocurrent, the voltage VD and the load current.
𝑉𝐷

𝐼 𝐷 = 𝐼𝑆 𝑒 𝑉𝑇
−1
𝐼𝐷 = 𝐼𝑃 ℎ𝑜𝑡𝑜 − 𝐼𝐿𝑜𝑎𝑑
𝐼𝑃 ℎ𝑜𝑡𝑜 − 𝐼𝐿𝑜𝑎𝑑

𝑉𝐷 = 𝑉𝑇 𝑙𝑛 +1
𝐼𝑆
𝑃𝐿𝑜𝑎𝑑 = 𝑉𝐷 𝐼𝐿𝑜𝑎𝑑
Below is a model of the power in the load as a function of diode

voltage
#!/usr/bin/env python3
import numpy as np
import matplotlib.pyplot as plt
m = 1e-3
i_load = np.linspace(1e-5,1e-3,200)
i_s = 1e-12 # saturation current

i_ph = 1e-3 # Photocurrent
V_T = 1.38e-23*300/1.6e-19 #Thermal voltage
V_D = V_T*np.log((i_ph - i_load)/(i_s) + 1)
P_load = V_D*i_load
plt.subplot(2,1,1)
18.3 Piezoelectric 333
plt.plot(i_load/m,V_D)
plt.ylabel("Diode voltage [mA]")
plt.grid()
plt.subplot(2,1,2)
plt.plot(i_load/m,P_load/m)
plt.xlabel("Current load [mA]")
plt.ylabel("Power Load [mW]")
plt.grid()
plt.savefig("pv.pdf")
plt.show()
From the plot below we can see that to optimize the power we
could extract from the photovoltaic cell we’d want to have a current
of 0.9 mA in the model above.
0.5
Diode voltage [V]
0.4
0.3
0.2
0.1
0.0
0.0 0.2 0.4 0.6 0.8 1.0
0.4
Power Load [mW]
0.3
0.2
0.1
0.0
0.0 0.2 0.4 0.6 0.8 1.0
Current load [mA]
Most photovoltaic energy harvesting circuits will include a max-

imum power point tracker as the optimum changes with light
conditions.
In A Reconfigurable Capacitive Power Converter With Capacitance

Redistribution for Indoor Light-Powered Batteryless Internet-of-
Things Devices they include a maximum power point tracker and
a reconfigurable charge pump to optimize efficiency.
18.3 Piezoelectric
I’m not sure I understand the piezoelectric effect, but I think it goes
something like this.
Consider a crystal made of a combination of elements, for example

Gallium Nitride. In GaN it’s possible to get a polarization of the unit
cell, with a more negative charge on one side, and a positive charge
on the other side. The polarization comes from an asymmetry in
the electron and nucleus distribution within the material.
In a polycrystaline substance the polarization domains will usually

be random, and no electric field will observable. The polarization
domains can be aligned by heating the material and applying a
electric field. Now all the small electric fields point in the same
direction.
From Gausses law we know that the electric field through a surface
is determined by the volume integral of the charges inside.
∮ ∭
1
𝜕Ω 𝜖0 𝑉
Although there is a net zero charge inside the material, there is an

uneven distribution of charges, as such, some of the field lines will
cross through the surface.
Assume we have a polycrystaline GaN material with polarized

domains. If we measure the voltage across the material we will
read 0 V. Even though the domains are polarized, and we should
observe an external electric field, the free charges in the material
will redistribute if there is a field inside, such that there is no
current flowing, and thus no external field.
If we apply stress, however, all the domains inside the material

will shift. Now the free charges do not exactly cancel the electric
field in the material, the free charges are in the wrong place. If we
have a material with low conductivity, then it will take time for the
free charges to redistribute. As such, for a while, we can measure
an voltage across the material.
Assuming the above explanation is true, then there should not be

piezoelectric materials with high conductivity, and indeed, most
piezoelectric materials have resistance of 1012 to 1014 Ohm.
Vibrations on a piezoelectric material will result in a AC voltage

across the surface, which we can harvest.
A model of a piezoelectric transducer can be seen below.
The voltage on the transducer can be on the order of a few volts,

but the current is usually low (nA – µA). The key challenge is to
rectify the AC signal into a DC signal. It is common to use tricks to
reduce the energy waste due to the rectifier.
18.4 Electromagnetic 335
An example of piezoelectric energy harvester can be found in A

Fully Integrated Split-Electrode SSHC Rectifier for Piezoelectric
Energy Harvesting
18.4 Electromagnetic
18.4.1 “Near field” harvesting
Near Field Communication (NFC) operates at close physical dis-

tances
Reactive near field or inductive near field
𝜆
Inductive <
2𝜋
Within the inductive near field the antenna’s can “feel” each other.
The NFC reader inside the card reader can “feel” the antenna of
the NFC tag. When the tag get’s close it will load down the NFC
reader by presenting a load impedance. As the circuit inside the
tag is powered, it can change the impedance of it’s antenna, which
is sensed by the reader, and thus the reader can get data from the
tag. The tag could lock in on the 13.56 MHz frequency and decode
both amplitude and phase modulation from the reader.
Since the NFC or Qi system operates at close distances, then the

coupling factor between antenna’s, or really, inductors, can be
decent, and it’s possible to achieve efficiencies of maybe 70 %.
At Bluetooth frequencies, as can be seen below, it does not really

make sense to couple inductors, as they need to be within 2 cm to be
in the inductive near field. The inductive near field is a significant
problem for the coupling between inductors on chip, but I don’t
think I would use it to transfer power.
Standard Frequency [MHz] Inductive [m]

AirFuel Resonant 6.78 7.03
NFC 13.56 3.52
Qi 0.205 232
Bluetooth 2400 0.02
18.4.2 Ambient RF Harvesting
Extremely inefficient idea, but may find special use-cases at short-

distance.
Will get better with beam-forming and directive antennas
There are companies that think RF harvesting is a good idea.
AirFuel RF
I think that ambient RF harvesting should tingle your science spidy

senses.
Let’s consider the power transmitted in wireless standards. Your

cellphone may transmit 30 dBm, your WiFi router maybe 20 dBm,
and your Bluetooth LE device 10 dBm.
In case those numbers don’t mean anything to you, below is a

conversion to watts.
dBm W
30 1
0 1m
-30 1u
-60 1n
-90 1p
Now ask your self the question “What’s the power at a certain
distance?”. It’s easier to flip the question, and use Friis to calculate
the distance.
Assume
𝑃𝑇𝑋
= 1 W (30 dBm) and
𝑃𝑅𝑋
18.5 Triboelectric generator 337
= 10 uW (-20 dBm)
then

𝑃𝑇𝑋 −𝑃𝑅𝑋 +20 𝑙𝑜 𝑔10 𝑐
4𝜋 𝑓
𝐷 = 10 20
In the table below we can see the distance is not that far!
20 𝑙𝑜 𝑔10 𝑐/4𝜋 𝑓 [dB]

Freq D [m]
915M -31.7 8.2
2.45G -40.2 3.1
5.80G -47.7 1.3
I believe ambient RF is a stupid idea.
Assuming an antenna that transmits equally in all direction, then

the loss on the first meter is 40 dB at 2.4 GHz. If I transmitted
1 W, there would only be 100 µW available at 1 meter. That’s an
efficiency of 0.01 %.
Just fundamentally stupid. Stupid, I tell you!!!
Stupidity in engineering really annoys me, especially when people

don’t understand how stupid ideas are.
18.5 Triboelectric generator
Although static electricity is an old phenomenon, it is only re-

cently that triboelectric nanogenerators have been used to harvest
energy.
An overview can be seen in Current progress on power manage-

ment systems for triboelectric nanogenerators.
A model of a triboelectric generator can be seen in below. Although

the current is low (nA) the voltage can be high, tens to hundreds
of volts.
The key circuit challenge is the rectifier, and the high voltage output
of the triboelectric generator.
Take a look in A Fully Energy-Autonomous Temperature-to-Time

Converter Powered by a Triboelectric Energy Harvester for Biomed-
ical Applications for more details.
Below is a custom triboelectric material that converts friction into

a sparse electric field.
The key idea of the triboelectric circuit below is to rectify the sparse
voltage pulses and store the charge on a capacitor. Once the voltage
is high enough, then a temperature sensor is started.
18.5 Triboelectric generator 339
Below is some more details on the operation of the harvesting

circuit, and the temperature sensor. Notice how the temperature
sensor part of the circuit (PTAT bandgap, capacitor and compara-
tor) produce a pulse width modulated signal that depends on
temperature.
Also notice the “VDD_ext” in the figure. That means the system is
not fully harvested. The paper is a prime example on how we in
academia can ignore key portions of a system. They’ve focused on
the harvesting part, and making the temperature dependent pulse
width modulated signal. Maybe they’ve completely ignored how
the data is transmitted from the system to where it would be used,
and that’s OK.
It’s academia’s job to prove that something could be possible. It’s

industry’s job to make some that could be possible actually work.
18.6 Comparison
Imagine you’re a engineer in a company that makes integrated

circuits. Your CEO comes to you and says “You need to make
a power management IC that harvest energy and works with
everything”.
Hopefully, your response would now be “That’s a stupid idea, any

energy harvester circuit must be made specifically for the energy
source”.
Thermoelectric and photovoltaic provide low DC voltage. Piezo-

electric and Triboelectric provide an AC voltage. Ambient RF is
stupid.
For a “energy harvesting circuit” you must also know the applica-
tion (wrist watch, or wall switch) to know what energy source is
available.
Below is a table that show’s a comparison in the power that can be

extracted.
The power levels below are too low for the peak power consumption
of integrated circuits, so most applications must include a charge
storage device, either a battery, or a capacitor.
[1] Towards a Green and Self-Powered Internet of Things Using

Piezoelectric Energy Harvesting
A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With

Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy
Harvesting
A Reconfigurable Capacitive Power Converter With Capacitance

Redistribution for Indoor Light-Powered Batteryless Internet- of-
Things Devices
A Fully Integrated Split-Electrode SSHC Rectifier for Piezoelectric

Energy Harvesting
Current progress on power management systems for triboelectric

nanogenerators
A Fully Energy-Autonomous Temperature-to-Time Converter Pow-

ered by a Triboelectric Energy Harvester for Biomedical Applica-
tions
Analog SystemVerilog 19
Design of integrated circuits is split in two, analog design, and 19.1 Digital simulation . 345
digital design. 19.2 Transient analog
simulation . . . . . . 348
Digital design is highly automated. The digital functions are coded 19.3 Mixed signal simula-
in SystemVerilog (yes, I know there are others, but don’t use those), tion . . . . . . . . . . 349
translated into a gate level netlist, and automatically generated 19.4 Analog SystemVer-
layout. Not everything is push-button automation, but most is. ilog Example . . . . 351
19.4.1 TinyTapeout TT06_-
SAR . . . . . . . . . . 351
Analog design, however, is manual work. We draw schematic,
19.4.2 SAR operation . . . . 352
simulation with a mathematical model of the real world, draw the
analog layout needed for the foundries to make the circuit, verify
that we drew the schematic and layout the same, extract parasitics,
simulate again, and in the end get a GDSII file.
When we mix analog and digital designs, we have two choices,

analog on top, or digital on top.
In analog on top we take the digital IP, and do the top level layout
by hand in analog tools.
In digital on top we include the analog IPs in the SystemVerilog,

and allow the digital tools to do the layout. The digital layout is
still orchestrated by people.
Which strategy is chosen depends on the complexity of the inte-

grated circuit. For medium to low level of complexity, analog on
top is fine. For high complexity ICs, then digital on top is the way
to go.
Below is a description of the open source digital-on-top flow. The

analog is included into GDSII at the OpenRoad stage of the flow.
The GDSII is not sufficient to integrate the analog IP. The digital
needs to know how the analog works, what capacitance is on every
digital input, the propagation delay for digital input to digital
outputs , the relation between digital outputs and clock inputs,
and the possible load on digital outputs.
The details on timing and capacitance is covered in a Liberty file.

The behavior, or function of the analog circuit must be described
in a SystemVerilog file.
But how do we describe an analog function in SystemVerilog?

SystemVerilog is simulated in an digital simulator.
344 19 Analog SystemVerilog
19.1 Digital simulation 345
19.1 Digital simulation
Conceptually, the digital simulator is easy.
▶ The order of execution of events at the same time-step do

not matter
▶ The system is causal. Changes in the future do not affect
signals in the past or the now
In a digital simulator there will be an event queue, see below. From

start, set the current time step equals to the next time step. Check
if there are any events scheduled for the time step. Assume that
execution of events will add new time steps. Check if there is
another time step, and repeat.
Since the digital simulator only acts when something is supposed

to be done, they are inherently fast, and can handle complex
systems.
It’s a fun exercise to make a digital simulator. On my Ph.D I wanted

to model ADCs, and first I had a look at SystemC, however, I
disliked C++, so I made SystemDotNet
In SystemDotNet I implemented the event queue as a hash table,

so it ran a bit faster. See below.
19.1.0.1 Digital Simulators
There are both commercial an open source tools for digital simula-
tion. If you’ve never used a digital simulator, then I’d recommend
you start with iverilog. I’ve made some examples at dicex.
Commercial
▶ Cadence Excelium
▶ Siemens Questa
▶ Synopsys VCS
Open Source - iverilog/vpp - Verilator - SystemDotNet
19.1.0.2 Counter
Below is an example of a counter in SystemVerilog. The code can

be found at counter_sv.
In the always_comb section we code what will become the combi-

natorial logic. In the always_ff section we code what will become
our registers.
module counter(
output logic [WIDTH-1:0] out,
input logic clk,
input logic reset
);
parameter WIDTH = 8;
19.1 Digital simulation 347
logic [WIDTH-1:0] count;

always_comb begin
count = out + 1;
end
always_ff @(posedge clk or posedge reset) begin

if (reset)
out <= 0;
else
out <= count;
end
endmodule // counter
In the context of a digital simulator, we can think through how the

event queue will look.
When the clk or reset changes from zero to 1, then schedule an

event where if the reset is 1, then out will be zero in the next time
step. If reset is 0, then out will be count in the next time step.
In a time-step where out changes, then schedule an event

to setcounttoout‘ plus one. As such, each positive edge of the
clock at least 2 events must be scheduled in the register transfer
level (RTL) simulation.
For example:
Assume `clk, reset, out = 0`
Assume event with `clk = 1`
0: Set òut = count` in next event (1)
1: Set `count = out + 1` using

logic (may consume multiple events)
X: no further events
When we synthesis the code below into a netlist it’s a bit harder to
see how the events will be scheduled, but we can notice that clk
and reset are still inputs, and for example the clock is connected to
d-flip-flops. The image below is the synthesized netlist
It should feel intuitive that a gate-level netlist will take longer to

simulate than an RTL, there are more events.
19.2 Transient analog simulation
Analog simulation is different. There is no quantized time step.

How fast “things” happen in the circuit is entirely determined by
the time constants, change in voltage, and change in current in the
system.
It is possible to have a fixed time-step in analog simulation, for

example, we say that nothing is faster than 1 fs, so we pick that
as our time step. If we wanted to simulate 1 s, however, that’s at
least 1e15 events, and with 1 event per microsecond on a computer
it’s still a simulation time of 31 years. Not a viable solution for all
analog circuits.
Analog circuits are also non-linear, properties of resistors, capac-

itors, inductors, diodes may depend on the voltage or current
across, or in, the device. Solving for all the non-linear differential
equations is tricky.
An analog simulation engine must parse spice netlist, and setup

partial/ordinary differential equations for node matrix
The nodal matrix could look like the matrix below, 𝑖 are the currents,
𝑣 the voltages, and 𝐺 the conductances between nodes.
𝐺11 𝐺12 ··· 𝐺1𝑁 𝑣1 𝑖1

𝐺21 𝐺22 · · · 𝐺2𝑁 ® 𝑣2 ® 𝑖2 ®
© ª© ª © ª
. .. .. .. ®® .. ®® = .. ®®
. .
. . . ® . ® . ®
« 𝐺 𝑁 1 𝐺 𝑁 2 · · · 𝐺 𝑁 𝑁 ¬ «𝑣 𝑁 ¬ « 𝑖 𝑁 ¬
The simulator, and devices model the non-linear current/voltage

behavior between all nodes
19.3 Mixed signal simulation 349
as such, the 𝐺 ’s may be non-linear functions, and include the 𝑣 ’s

and 𝑖 ’s.
Transient analysis use numerical methods to compute time evolu-

tion
The time step is adjusted automatically, often by proprietary algo-

rithms, to trade accuracy and simulation speed.
The numerical methods can be forward/backward Euler, or the

others listed below.
▶ Euler
▶ Runge-Kutta
▶ Crank-Nicolson
▶ Gear
If you wish to learn more, I would recommend starting with the

original paper on analog transient analysis.
SPICE (Simulation Program with Integrated Circuit Emphasis)

published in 1973 by Nagel and Pederson
The original paper has spawned a multitude of commercial, free

and open source simulators, some are listed below.
If you have money, then buy Cadence Spectre. If you have no

money, then start with ngspice.
Commercial - Cadence Spectre - Siemens Eldo - Synopsys

HSPICE
Free - Aimspice - Analog Devices LTspice - xyce
Open Source - ngspice
19.3 Mixed signal simulation
It is possible to co-simulate both analog and digital functions. An

illustration is shown below.
The system will have two simulators, one analog, with transient
simulation and differential equation solver, and a digital, with
event queue.
Between the two simulators there would be analog-to-digital, and

digital-to-analog converters.
To orchestrate the time between simulators there must be a global

event and time-step control. Most often, the digital simulator will
end up waiting for the analog simulator.
The challenge with mixed-mode simulation is that if the digital

circuit becomes to large, and the digital simulation must wait for
analog solver, then the simulation would take too long.
Most of the time, it’s stupid to try and simulate complex system-
on-chip with mixed-signal , full detail, simulation.
For IPs, like an ADC, co-simulation works well, and is the best way
to verify the digital and analog.
But if we can’t run mixed simulation, how do we verify analog

with digital?
Digital Analog
Simulator Simulator
Event Timester Control

19.4 Analog SystemVerilog Example 351
19.4 Analog SystemVerilog Example
19.4.1 TinyTapeout TT06_SAR

19.4.2 SAR operation
The key idea is to model the analog behavior to sufficient detail

such that we can verify the digital code. I think it’s best to have a
look at a concrete example.
▶ Analog input is sampled when clock goes low (sarp/sarn)

▶ uio_out[0] goes high when bit-cycling is done
▶ Digital output (ro) changes when uio_out[0] goes high
//tt06-sar/src/project.v
module tt_um_TT06_SAR_wulffern (
input wire VGND,
input wire VPWR,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
ìfdef ANA_TYPE_REAL
input real ua_0,
input real ua_1,
èlse
// analog pins
inout wire [7:0] ua,
èndif
input wire ena,
input wire clk,
input wire rst_n
);
//tt06-sar/src/tb_ana.v
real ua_0 = 0;
real ua_1 = 0;
èlse
tri [7:0] ua;
logic uain = 0;
assign ua = uain;
èndif
always #100 begin
ua_0 = $sin(2*3.14*1/7750*$time);
ua_1 = -$sin(2*3.14*1/7750*$time);
end
èndif
//tt06-sar/src/tb_ana.v
tt_um_TT06_SAR_wulffern dut (
.VGND(VGND),
.VPWR(VPWR),
.ui_in(ui_in),
.uo_out(uo_out),
.uio_in(uio_in),
.uio_out(uio_out),
.uio_oe(uio_oe),
.ua_0(ua_0),
.ua_1(ua_1),
èlse
.ua(ua),
èndif
.ena(ena),
.clk(clk),
.rst_n(rst_n)
);
#tt06-sar/src/Makefile
runa:
iverilog -g2012 -o my_design -c tb_ana.fl -DANA_TYPE_REAL
_
vvp -n my design
rund:
iverilog -g2012 -o my_design -c tb_ana.fl
vvp -n my_design
//Main SAR loop
always_ff @(posedge clk or negedge clk) begin
if(~ui_in[0]) begin
state <= OFF;
tmp = 0;
dout = 0;
end
else begin
if(OFF) begin
end
else if(clk == 1) begin
state = SAMPLE;
end
else if(clk == 0) begin
state = CONVERT;
smpl = ua_0 - ua_1;
tmp = smpl;
for(int i=7;i>=0;i--) begin

if(tmp >= 0) begin
tmp = tmp - lsb*2**(i-1);
if(i==7)
dout[i] <= 0;
else
dout[i] <= 1;
end
else begin
tmp = tmp + lsb*2**(i-1);
if(i==7)
dout[i] = 1;
else
dout[i] = 0;
end
end
èlse
if(tmp == 0) begin
dout[7] <= 1;
tmp <= 1;
end
else begin
dout[7] <= 0;
tmp = 0;
end
èndif
end
state = next_state;
end // else: !if(~ui_in[0])
end // always_ff @ (posedge clk)
always @(posedge done) begin
state = DONE;
sampled_dout = dout;
end
always @(state) begin

if(state == OFF)
#2 done = 0;
else if(state == SAMPLE)
#1.6 done = 0;
else if(state == CONVERT)
#115 done = 1;
end
For more information on real-number modeling I would recom-

mend The Evolution of Real Number Modeling
How to write a project report 20
20.1 Why . . . . . . . . . 357
20.1 Why
20.2 On writing English 357
20.2.1 Shorter is better . . 357
Them who has a Why? in life can tolerate almost any 20.2.2 Be careful with
How? adjectives . . . . . . 358
20.2.3 Use paragraphs . . . 358
You’re writing the report on the project for me to be able to see 20.2.4 Don’t be afraid of I . 358
inside your head, and grade how much of the project you have 20.2.5 Transitions are
understood. important . . . . . . 358
20.2.6 However, is not a
▶ Have you learned what is to be expected? start of a sentence . 359
▶ Do you understand what you’re trying to explain? 20.3 Report Structure . . 359
20.3.1 Introduction . . . . . 359
You will work on the project in groups, however, on the report, 20.3.2 Theory . . . . . . . . 360
you will write on your own. 20.3.3 Implementation . . 360
20.3.4 Result . . . . . . . . . 360
That means, that there will be X projects reports that describe the 20.3.5 Discussion . . . . . . 360
same circuit. You shall not copy someone elses report text. 20.3.6 Future work . . . . . 361
20.3.7 Conclusion . . . . . 361
It’s fine to share figures between reports, and also references. 20.3.8 Appendix . . . . . . 361
20.4 Checklist . . . . . . 361
I’m also forcing you to use a report format that matches well with
what would be expected if you were to publish a paper.
Should you make a fantastic temperature sensor, and maybe even

reach close to a tapeout I would strongly suggest you submit a
paper to NorCas. The deadline is August 15 2024.
20.2 On writing English
Writing well is important. I would recommend that you read On

writing Well.
Most of you won’t buy the book, as such, a few tips.
20.2.1 Shorter is better
I can write the section title idea in many words:
A shorter text will more elequently describe the intrica-

cies of your thoughts than a long, distinguished, tirade
of carefully, wonderfully, choosen words.
or
358 20 How to write a project report
Shorter is better
Describe an idea with as few words as possible. The text will be

better, and more readable.
20.2.2 Be careful with adjectives
Words like “very, extremely, easily, simply, . . . ” don’t belong in a

readable text. They serve no purpose. Delete them.
20.2.3 Use paragraphs
You write a text to place ideas into anothers head. Ideas and
thoughts are best communicated in chunks. I can write a dense set
of text, or I can split a dense set of text into multiple paragraphs.
The more I try to cram into a paragraph, for example, how magical
the weather has been the last weeks, with lots of snow, and good
skiing, the more difficult the paragraph is to read.
One paragraph, one thought. For example:
You write a text to place ideas into anothers head. Ideas and
thoughts are best communicated in chunks.
I can write a dense set of text, or I can split a dense set of text into
multiple paragraphs.
The more I try to cram into a paragraph, for example, how magical
the weather has been the last weeks, with lots of snow, and good
skiing, the more difficult the paragraph is to read.
20.2.4 Don’t be afraid of I
If you did something, then say “I” in the text. If there were more
people, then use “we”.
20.2.5 Transitions are important
Sentences within a paragraph are sometimes linked. Use
▶ As a result,
▶ As such,
▶ Accordingly,
▶ Consequently,
And mix them up.

20.3 Report Structure 359
20.2.6 However, is not a start of a sentence
If you have to use “However” it should come in the middle of the

sentence.
I want to go skiing, however, I cannot today due to work.
20.3 Report Structure
The sections below go through the expected structure of a report,

and what the sections should contain.
20.3.1 Introduction
The purpose of the introduction is to put the reader into the right
frame of mind. Introduce the problem statement, key references,
the key contribution of your work, and an outline of the work
presented. Think of the introduction as explaining the “Why” of
the work.
Although everyone has the same assignment for the project, you
have chosen to solve the problem in different ways. Explain what
you consider the problem statement, and tailor the problem state-
ment to what the reader will read.
Key references are introduced. Don’t copy the paper text, write
why they designed the circuit, how they chose to implement it,
and what they achieved. The reason we reference other papers
in the introduction is to show that we understand the current
state-of-the-art. Provide a summary where state-of-the-art has
moved since the original paper.
The outline should be included towards the end of the introduction.

The purpose of the outline is to make this document easy to read. A
reader should never be surprised by the text. All concepts should
be eased into. We don’t want the reader to feel like they been
thrown in at the end of a long story. As such, if you chosen to solve
the problem statement in a way not previously solved in a key
references, then you should explain that.
A checklist for all chapters can be seen in table below.

20.3.2 Theory
It is safe to assume that all readers have read the key references, if
they have not, then expect them to do so.
The purpose of the theory section is not to demonstrate that you

have read the references, but rather, highlight theory that the
reader probably does not know.
The theory section should give sufficient explanation to bridge the

gap between references, and what you apply in this text.
20.3.3 Implementation
The purpose of the implementation is to explain what you did.

How have you chosen to architect the solution, how did you split
it up in analog and digital parts? Use one subsection per circuit.
For the analog, explain the design decisions you made, how did
you pick the transistor sizes, and the currents. Did you make other
choices than in the references? How does the circuit work?
For the digital, how did you divide up the digital? What were the
design choices you made? How did you implement readout of the
data? Explain what you did, and how it works. Use state diagrams
and block diagrams.
Use clear figures (i.e. circuitikz), don’t use pictures from schematic
editors.
20.3.4 Result
The purpose of the results is to convince the reader that what

you made actually works. To do that, explain testbenches and
simulation results. The key to good results is to be critical of your
own work. Do not try to oversell the results. Your result should
speak for themself.
For analog circuits, show results from each block. Highlight key
parameters, like current and delay of comparator. Demonstrate
that the full analog system works.
Show simulations that demonstrate that the digital works.
20.3.5 Discussion
Explain what the circuit and results show. Be critical.

20.4 Checklist 361
20.3.6 Future work
Give some insight into what is missing in the work. What should
be the next steps?
20.3.7 Conclusion
Summarize why, how, what and what the results show.
20.3.8 Appendix
Include in appendix the necessary files to reproduce the work. One

good way to do it is to make a github repository with the files, and
give a link here.
20.4 Checklist
Item Description OK
Is the Describe which parts of the problem you chose
problem to focus on. The problem description should
description match the results you’ve achieved.
clearly
defined?
Is there a The reader might need help to understand why
clear the problem is interesting
explanation
why the
problem is
worth
solving?
Is status of You should make sure that you know what
state-of-the- others have done for the same problem. Check
art clearly IEEEXplore. Provide summary and references.
explained? Explain how your problem or solution is
different
Is the key Highlight what you’ve achieved. What was
contribu- your contribution?
tion clearly
explained?
Is there an Give a short summary of what the reader is
outline of about to read
the report?
Item Description OK
Is it Have you included references to relevant
possible for papers
a reader
skilled in
the art to
understand
the work?
Is the The theory section should be less than 10 % of
theory the work
section too
long
Are all Have you explained how every single block
circuits works?
explained?
Are figures Remember to explain all colors, and all
clear? symbols. Explain what the reader should
understand from the figure. All figures must be
referenced in the text.
Is it clear It’s a good idea to explain what type of
how you testbenches you used. For example, did you use
verified the dc, ac or transient to verify your circuit?
circuit?
Are key You at least need current from VDD. Think
parameters through what you would need to simulate to
simulated? prove that the circuit works.
Have you Knowing how circuits fail will increase
tried to confidence that it will work under normal
make the conditions.
circuit fail?
Have you Try to look at the verification from different
been critical perspectives. Play devil’s advocate, try to think
of your own through what could go wrong, then explain
results? how your verification proves that the circuit
does work.
Have you Imagine that someone reads your work. Maybe
explained they want to reproduce it, and take one step
the next further. What should that step be?
steps?
No new in- Never put new information into conclusion. It’s
formation a summary of what’s been done
in
conclusion.
Story Does the work tell a story, is it readable? Don’t
surprise the reader by introducing new topics
without background information.
20.4 Checklist 363
Item Description OK
Chronology Don’t let the report follow the timeline of the
work done. What I mean by that is don’t write
“first I did this, then I spent huge amount of
time on this, then I did that”. No one cares what
the timeline was. The report does not need to
follow the same timeline as the actual work.
Too much How much time you spent on something
time should not be correlated to how much text
there is in the report. No one cares how much
time you spent on something. The report is
about why, how, what and does it work.
Length A report should be concise. Only include what
is necessary, but no more. Shorter is almost
always better than longer.
Template Use IEEEtran.cls. Example can be seen from an
old version of this document at
https://github.com/wulffern/dic2021/tree/
main/2021-10-19_project_report. Write in
LaTeX. You will need LaTeX for your project
and master thesis. Use http://overleaf.com if
you’re uncomfortable with local text editors
and LaTeX.
Spellcheck Always use a spellchecker. Misspelled words
are annoying, and may change content and
context (peaked versus piqued)
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Advanced Integrated

Built on Fri Dec 6 14:28:19 UTC 2024

©Carsten Wulff 2025

7 Mixed Signal Simulation in NGSPICE 79

9 IC and ESD 113

10 References and bias 131

11 Analog frontend and filters 147

12 Switched-Capacitor Circuits 165

13 Oversampling and Sigma-Delta ADCs 195

15 Clocks and PLLs 253

17 Low Power Radio 293

19 Analog SystemVerilog 343

20 How to write a project report 357

In the first round I noticed that little of what I had on slides, or

For the third semester I finally felt I achieved a balance. I spent

▶ What is one thing that is going on in your life (personal or

I love programming and automation. Not much makes me more

2.2 How I see our roles

Professors: Guide students on what is impossible, possible, and

Ph.D students: Venture into the unknown and make something

Master students: Learn all that is currently possible

Bachelor students: Learn how to make complicated into easy

Industry: Take what is possible, and/or complicated, and make it

2.3 I want you to learn the skills necessary to

In 2020 the global integrated circuit market was 437.7 billion

Integrated circuits enable pretty much all technologies.

I will be dead in approximately 50 years, and will retire in approx-

patience, and brain necessary to learn some of the hardest topics

Making integrated circuits (that work reliably) is not

2.4 There will always be analog circuits,

Status Abstraction Design Layout Why

Status Abstraction Design Layout Why

The steps to make integrated circuits is split in two. We have an

analog flow, and a digital flow.

If you’re comfortable with not knowing, and an insatiable desire

2.4.1 Will you tape-out an IC?

Something that would make me really happy is if someone is able

It’s now possible without signing an NDA or buying expensive

In 2020 Google and Skywater joined forces to release a 130 nm

Together with Efabless there are cheap alternatives, like tinytapeout,

2.4.2 What the team needs to know to design ICs

There are a multitude of tools and skills needed to design pro-

That is, unless we can find a way to make ICs easier.

The skills needed are

▶ Project flow support: Confluence, JIRA, risk management

▶ Blocks: Analog Radio, Digital radio baseband

2.4.3 Zen of IC design (stolen from Zen of Python)

Here is some guiding principles that you’ll likely forget.

▶ Beautiful is better than ugly.

2.4.4 IC design mantra

To copy an old mantra I have on learning programming

Find a problem that you really want to solve, and learn

And run the perl program

2.4.5 Analog Design Process

▶ Define the problem, what are you trying to solve?

On failure, go back as far as necessary

You are the one that must teach yourself everything.

I consider my role as a guide, similar to a mountain guide. I can’t

▶ Enable you to read the books on integrated circuits

The syllabus will be from Analog Integrated Circuit Design (CJM)