VLSI Design Thirunaavukarasan

RTL-GDSII FLOW
The Process by Which a Chip is Manufactured and Undergoes Several Stages to Meet User Requirements
FrontEnd flow
1) RTL Design -
Tools used :
Description: RTL is the first step in the design process, where the chip's functionality is described at a high level using HDL
Cadence Incisive
(Hardware Description Language). It specifies how data flows and operations are performed, particularly with
respect to clock cycles. This provides a blueprint for the chip's function. Xilinx Vivado
Output : The output of RTL design includes synthesizable HDL code (Verilog/VHDL), simulation results (waveforms and Modelsim
logs), and a constraints file specifying timing, area, and power requirements for synthesis.
2) Stimulation :
Description: Simulation verifies the RTL design's functionality by simulating various input conditions and observing the ModelSim
output. It helps catch logical errors early
VCS
Output : Simulation waveforms showing signal behavior over time and Log files providing detailed reports on Questa
functionality and errors.
3) Synthesis :
Description: Synthesis is the process of converting the RTL code into a gate-level netlist, suitable for physical design. It Cadence Genus
involves optimization for speed, area, and power. Xilinx Vivado
Output : Reports on timing, area, and power estimates. and Gate-level netlist which represents the design as a network
of logic gates.
4) DFT :
Description: DFT focuses on incorporating testability features into the design to ensure the chip can be easily tested Cadence Modus
during manufacturing. This includes adding scan chains, built-in self-test (BIST), and other test structures Synopsys TetraMAX
Output : The output of DFT includes a testable netlist, test patterns, and fault coverage reports for manufacturing
testing.
BACKEND FLOW
5) Floorplanning Tools used :
Description: Arranges blocks on the chip and reserves areas for routing, power, and I/O. Cadence Innovus
Synopsys IC Compiler
Output : Chip layout blueprint, area estimates. Mentor Graphics Olympus-SoC
6) Placement :
Cadence Innovus
Description: Places standard cells from the gate-level netlist into specific locations on the die Synopsys IC Compiler
Goal : Minimize timing delay, area, and power. Mentor Graphics Olympus-SoC
7) Clock Tree Synthesis :

Cadence Innovus
Description: Creates a clock distribution network to minimize skew and latency.
Mentor Graphics Olympus-SoC
Goal : Ensure synchronous operation
8) Routing : Cadence Innovus
Description: Connects the placed cells with wires according to the netlist. Mentor Graphics Olympus-SoC
Goal : Minimize signal interference and timing violations.
9) DRC & LVS : Cadence Assura
Description: Ensures the physical layout meets manufacturing rules (DRC) and verifies that the layout Mentor Graphics Calibre
matches the logical design (LVS). Synopsys IC Validator
Goal : DRC and LVS reports that validate the design for fabrication.
10) Post Layout Simulation : Cadence Spectre
Description: Verifies functionality and performance after layout, considering parasitic effects(RLC). HSPICE
Synopsys PrimeTime
Goal : Ensure timing, power, and signal integrity meet design specifications.
Design is ready for GDSII file generation.
CMOS
Complementary Metal-Oxide-Semiconductor
Combination of n & p mos to

function as inverter
CMOS Twin tub technology of Inverter
Overview Features and Advantages of CMOS Logic:
Combination of nMOS and pMOS transistors connected in a

Low Power Consumption: Consumes minimal power in the steady state
complementary manner to achieve specific logic functions.
due to no direct current flow between VDD and GND.
Outputs are always complemented (inverted), as evident

High Noise Margin: Output voltage swings between 0 and VDD, offering
from its name.
a better noise margin compared to BJTs.
Scalability: CMOS technology is highly scalable, allowing for advanced

miniaturization in modern IC design.
The CMOS is constructed using a combination of MOSFET
transistors, enabling efficient logic design and operation. Speed and Efficiency: Faster operation with minimal power loss.
Working of CMOS
nMOS (Strong Pull-Down): Provides a path to GND when active,
pulling the output LOW.
pMOS (Strong Pull-Up): Provides a path to VDD when active,

pulling the output HIGH.
MOSFET
1. Type N MOS P MOS
For cmos mostly Enhancement-mode
Regions of Operation:
MOSFETs are used (normally OFF by default).
2. Terminals
Cut-Off Region: MOSFET is OFF, no current flows (switch OFF).
Four terminals – Drain, Source, Gate, and Body.
3. Drain and Source Doping: Linear (Triode) Region: The MOSFET behaves like a variable resistor.
It is typically used in switching applications.
The drain and source regions are highly doped to
enhance conductivity. Saturation (Active) Region: The MOSFET is fully ON and acts as a
current source. This region is used for amplification in analog
The type of doping (n-type or p-type) determines circuits.
whether the MOSFET has an n-channel or p-channel.
4.SiO₂ Insulation: Applications:

SiO₂ (Silicon Dioxide) serves as an insulator between Digital: Acts as a switch for logic gates.
the gate and the body, preventing direct current
flow while enabling electric field control. Analog: Acts as an amplifier in circuits requiring signal amplification.

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RTL-GDSII FLOW

7) Clock Tree Synthesis :

Combination of n & p mos to

CMOS Twin tub technology of Inverter

Overview Features and Advantages of CMOS Logic:

Combination of nMOS and pMOS transistors connected in a

Outputs are always complemented (inverted), as evident

Scalability: CMOS technology is highly scalable, allowing for advanced

pMOS (Strong Pull-Up): Provides a path to VDD when active,

4.SiO₂ Insulation: Applications:

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