sit Thee Meme CHAPTER 4 41 Introduction gmbedded platforms can have a memory hierarchy, @ collection of different types of memory, each with unique speeds, sizes, and Usages (sce Figure 4.1). Figure 4.1 Memory Hierarchy » Some of this memory can be physically integrated on the processor, like registers and certain types of primary memory, which is memory connected directly to or integrated in the processor such as ROM, RAM, and level-1 cache. In this chapter, it ig memory that is typically located. outside of the processor, or that can both be either integrated into the processor or located outside the. processor, that is discussed. This includes other types of primary memory, such as ROM, level-2+ cache, and main memory, and secondary/tertiary memory, which is memory that is connected to the board but not the master processor directly, such as CD- ROM, floppy drives, hard drives, and tape. Embedded System W= atMi * Primary memory is typi pically a memory subsystem (shown in Figut, 4 made up of three components; |. °“* 4.9) © The memory IC ; © An address bus © Adata a Das bus Data ‘Adds tn Figure 4.2 Hardware Primary Memory Subsystem * In general, a {nae memory IC is made up of three o The memory array © The address decoder and © The data interface. * The memory array is actually the physical memory that stores the data bits. While the master processor, and programmers, memory as a one-dimensional array, ‘where each cell of the array is a row of bytes’ and the number of bits per row can vary, in, realty Embedded System Ww. cs : sical memory iS @ two-dimensional array fe up of memory cells addressed by a row and column, in which each cell nique Fi unrstore 1 bit (as shown in Figure 4.3), i ce a = py y 7. = Figure 4.3 (ROM) Memory Array + The locations of each of the cells within the two-dimensional memory array are commonly referred to as the physical memory addresses, made up of the column and row parameters. + The main basic hardware building blocks of memory cells depend on the type of memory. + ‘The remaining major component of a memory IC, the address decoder, locates the address of data within the memory array, based on information received over the address bus, and the data interface provides the data to the data bus for transmission. Embedded System W= 43.ey sand data buses take address d from the memory address doo ° data oN jt gata interface of the memory IC, a s that can connect 0 board * Mervvariety of packages, depending type of memory. Types of packages inchy o Dual. ny + As shown in Figure 4.4, DIPs are pa enclosing the IC, made up of ce plastic material, wi two opposing is 43 2 19 9 | | 123 $604 8 Figure 44 DIP Example * The number of pins can vary between m ICs and actual pinouts of ICs have been standard Electronic Device Engineering Commi simplify the process of interfacing extemal ‘memory ICs to processors, * SIMMs and DIMMs (shown in Figures 4 and (b)) are mini modules (PCBs) that emo the various memo ized by JEDEC yee E and bac nto 0 wuRaKRE EH EBS: '.0RGTTIE- lo PUTDD UY — | Srrerrr rr ey? Greckctialcoat oo cepuing pica ie, (a) 30-Pin STM Example: Embedded System We K) of the module that connect ‘ain embedded motherboard, 45nit Three ; |e Corer! Coren Cerrmed ] i] Creed ere Gerreed ° (6) 168-Pin DIMM Example Figure 4.5 * The configurations of SIMMs and DIMMs can both vary in the size of the memory ICs on the module (256KB, 1MB, etc.). a * For example, a 256K * 8 SIMM is a module providing 256K (256 * 1025) addresses of one byte each. Embedded System yp Three Memo Yrs support a 16-bit master processor, for + [xample, two of these SIMMs would be needed; to support a 32-bit architecture, four SIMMs of this configuration would be needed, and so on. the number of pins protruding from SIMMs * and DIMMs can vary as well (30 pin, 72 pin, 168 pin, etc.). The advantage of a SIMM or DIMM having more pins is that it allows for fewer modules “needed to support larger architectures. So, for example, one_72-pin SIMM (256K * 32) would replace the four 30- pin SIMMs (256K * 8) for 32-bit architectures. , Finally, -the main-difference-between SIMMs and DIMMs is how the pins function on the module: on SIMMs the two pins on either side of the board are connected, creating one contact, whereas on DIMMs opposing pins are each independent contacts (see Figures 4.5 (a) and (b))- + At the highest level, both primary and secondary memory can be divided into two groups: o Non-volatile o Volatile * Non-volatile memory is memory that can store data after the main power source to the board has been shut off (usually due to a small, on-board, longer-life battery source). * Volatile memory loses all of its “bits” when the main power source on the board has been shut off, Embedded System Wa. a7* On embedded boards, there are t non-volatile memory families: © Read-only memory (ROM) and © Auxiliary memory * One family of volatile memo TY, access memory (RAM). Tana 4.2 Read-Only Memory (ROM), * Read-only memory (ROM) is a Basically, a ROM ci column and row address inputs, as Figure 4.6. Each cell (addressed column and row combinatio: depending on some voltage value. ircuit works, by acceptit In fact, every ROM cell is designed to field on either a 1 or 0 permanently u: ing the voltage source attached. Embedded System inp! ated decoder uses the row/column inteselect the specific ROM cell, White ts Mal storage and selection mechanisms ge OCS dent on the type of components depenilding the ROM (i. (re it in Figure 4.6 includes three The Cee es (log28) for all eight words, ig the 3-bit addresses ranging from 000 1 each represent one of the 8 bytes. * qddress mean toll Figure 4.6 8 X 8 ROM Logic Circuit * Note that diferent ROM designs can include a wide variety of addressing configuratic this the exact same matrix size, and this addressing scheme is just an examp! We 49 Embedded system:such scheme. Do through Dy are the ou lines from which data is read, one outpy,' for each bit. * Adding additional rows to the ROM'y, increases its size in terms of the nump address spaces, whereas adding adgitt’ columns increases a ROM’s data size, 4.” number of bits per address, it can store, + ROM sizes are identified in the real worl matrix reference (i.c., 8 x 8, 16K’ x Ba reflecting the actual size of ROM. is or 4] * The first number is the number of addres, and the second number (after the “«") rene’ the size of the data, or number of bi address location (that is, 8 = one byte, half word, 32 = word, and so on). » 16 + Also note that in some design documenta the ROM matrix size may be summarized, pj example, 16 kB (kBytes) of ROM is 16K . ROM, 32 MB of ROM is 32 M x 8 ROM, and on. « In this example, the 8 x 8*ROM is an 8x matrix, meaning it can store eight different § bit words, or 64 bits of information. * Every intersection of a row and column in thi matrix is a memory location, called a memo cell. Each memory cell can contain either bipolar or MOSFET transistor (depending 0 the type of ROM) or a fusible link (see Figu 4.7). Embedded System Wooo-oo ofp p= == 2505), possibi, addresses one address line for every addrese digit of the address. Al Figure 4.10 4K x 8 SRAM Logic Circuit + There ate 8 input and output lines (Do-D7), a byte for every byte stored at'an address. There are also, CS (chip select) and WE (write enable) input. signals to indicate whether the data pins are enabled (CS) and to indicate whether .the operation is a READ or WRITE operation (WE), respectively. In this example, the 4K x 8 SRAM is set up as. a 64° x 64 array of rows and columns with addresses Ao-As identifying the row, and As- Au identifying the column, Were ea | Embedded System ">+ As with ROM, every intersection of a row an column in the SRAM matrix is a memory aay and in the case of SRAM memory cells, th°l can contain flip-flop circuitry mainly baseq o semiconductor devices such as_ polysilice” load resistors and NMOS transistors, pipgt” transistors, and/or CMOS (NMOS and PMog transistors (see Figure 4.11 for exam circuits). Ple — stored within these cells by the pata ise current being switched, in both . contin’ directions, on the two inverting gates il Peenin the flip-flop. ip select (CS) in Figure 4.10 is the Cr mony . in standby mode (no pIGH, then 3 are occurring). When CS is oF LOW (i.e., from HIGH to LOW) and 5 4 abi Input (WE) is LOW, then a byte write Enevv ing written through these dat of data. Gs (De-D7) at the address indicated by Vee ea Ea P a then a byte of ‘ LOW and WE HIGH, < with CS ing read from-the-data output lines data iat the address indicated by the (Do- Fr x address lines (Ao~A7)- ah ~ Zo ie Cee ee eee cate «Signals oe i : tes how the ferent si; a (9 SRAM MOSFET storege Menorca |” Seng memory ad and memery Wate ve in SRAM. +) BitSclect Bit Select Das (b) SRAM Bipolar Storage Memory Cell Figure 4.11 Flip-flop SRAM Memory Cell Logic Circuit Example Ee Ww Figure 4.12 SRAM Timing Diagram * As shown in Figure 4.13, DRAM memory cells are circuits with capacitors that hold a charge Embedded System »5@-48 | Embedded System We 4-19Memory three i aa 4.14 demonstrates how address lines + rie be multiplexed in this example. cot Unit Three in place the charges or lack thereof rep data. DRAM capacitors need to be rele frequently with power in order to their respective charges, and to Te DRAM is read, since go SS charges the capacitor. The oye! discharging and rechar, Sled g of memory og why this type of RAM is called dynamic. Data Out ala Pee PRPS Data In Figure 4.13 DRAM (capacitor-based) Memory cel * Let's look at a sample logic DRAM circuit 16K x 8. This RAM configuration is dimensional array of 128 rows an columns, meaning it can store 16384 (j 1024) different 8-bit bytes, or 131072 tte, information. ‘ Figure 4.14 16K x 8 DRAM Logic Circuit + The 16K * 8 DRAM is set up with addresses Ac-As identifying the row, and AyAis identifying the column. + As shown in Figure 4.15, the Row Address Strobe (RAS) line is toggled (ie., from HIGH to LOW) for Ao-As to be transmitted, and then the Column Address Strobe (CAS) line is toggled (i.e., from HIGH to LOW) for A7-A1s to be transmitted. * With this address configuration, larger DRAM can either be designed with 14 address lines (Ao-Ais) needed to address all 16384 le |* i i ll is latched and (000000000000b-11111111111111b) possible |* After this point the memory cell is late ready to be written to or read from. There are cight output lines (Do - Dz), a byte for every byte stored at an address. w= 421 be multiplexed with some type of data selection circuit m: Embedded System a* When the Write Enable HIGH, data can be read fr Dz, when WE are LOW, d: input lines Do-D7. Figure.4.16 DRAM Write Timi Embedded System Wu Figure 4.15 DRAM Read Timing Diagran =. (WE) input om output lin, lata can be writ ‘The i i in. Figure 4.16 demonstrates how the differeht signals cay function for a memory read and memory write in DRAM. : ne of the major differences between SRAM ond DRAM lies in the makeup of the‘DRAM memory array. The capacitors in the memory array of DRAM are not able to hold a charge (data). The charge gradually dissipates over time, thus requiring some additional mechanism to refresh DRAM, in order to maintain the integrity of the data. . This mechanism reads the data in DRAM before it is lost using..a:sense amplification circuit that senses a charge stored within the memory ‘cell, and writes it back onto the DRAM circuitry. + The process of reading the cell also discharges the capacitor (even though reading the cell is part of the process of correcting the problem of the capacitor gradually discharging in the first place). + A memory ‘controller in the embedded system typically manages a DRAM’s recharging and discharging cycle by initiating refreshes and keeping track of the refresh sequence of events. It is this refresh cycling’ mechanism that discharges and recharges memory cells that gives this type of RAM its. name “dynamic” RAM (DRAM) and the fact that the charge in SRAM stays put is the basis. for its name, “static” RAM (SRAM). Embedded System We 438unit Three + It is this same additional recharge which makes DRAM slower in comp SRAM. Note that one of the reasons gf usually slower than registers is that wit transistors within the SRAM. flip-n{¢® smaller, they do not carry as much @°? those typically used within registers, Wen + SRAMs also usually consume less pg DRAMS, since there is no extra ene ov th for a refresh. On the flip side, ore Ciroy: arisen l , Beca capacitance-based design. DRA} ao hold more data than SRAM circuitry is much smaller’ th circuitry, and more DRAM circuitey SR integrated into an IC. can'y| * DRAM is usually the “main” memory in quantities, as well as being used for RAM and cache. DRAMs used for dispel memory are also commonly referr frame buffers. area + SRAM, because it is more expensive typically used in small quantities, but bees it is also typically the fastest type of RAM, fi used in external cache and video -mey (where processing certain types of and given a more generous budget, a systen can implement a better performing RAM). 4.3.1 Level-2+ Caches 5 ¢ Level 2+ (level 2 and higher) cache is the lev¢l of memory that exists between the CPU ani main memory in the memory hierarchy. Embedded System Memory in this section, cache that is external'to the processor is introduced, which is éaches Pigher than level 1. gRAM memory is usually’ used as external cache (like level-1 cache), because the purpose of cache is to improve the performance of the memory system, and SRAM is faster than DRAM. Since (SRAM) cache. memory . is typically more expensive because of its speed, processors will usually have a small amount PF cache (on-chip, off-chip, or both). using cache became popular in response to systems that displayed a:good locality of reference, meaning-that-these-systems, in a given time period, accessed most of their data from a limited section of memory. Basically, cache is used to store subsets of main memory that are used or accessed often, capitalizing on the locality of reference and making main memory seem to execute faster. Because cache holds copies of what is in main memory, it gives the illusion to the master processor that it is operating from main memory even if actually operating from cache. There are different strategies when writing to and reading data from a. set of memory addresses, called the working set, to and from cache. One-word or multiword blocks are used to transfer data between memory and cache. These blocks are made up of data from main memory, as well as the location of that data in main memory (called tags) “Embedded System ia* When writing to memory, the memory ad from the CPU is translated to determi equivalent location in level-1 cache, giye”® | cache is a snapshot of a subset of memory uy * Writes must be done in both cache ang” memory to ensure that cache Ral ; ang memory are consistent (have the same 8 * The two most common write strate, ‘el guarantee this are: ‘i “Y © Write-through © Write-back * Write-through, in which data is write: ~ both cache and main memory. every.tin write-back, in which data is initially’ Ywitten into cache, and only when it 104 bumped and replaced by from cache wil ry. ne * When the CPU wants to read data: fro, memory, level-1 cache is checked. first Ifthe data is in cache, itis called a cache hit, data is returned to the CPU and the Memon] access process is complete. * If the data is not located in level-1 cache, it called cache miss. External off-chip caches are then checked, and if there is a miss ther also, then on to main memory to retrieve and Teturn the data to the CPU. ; * Data is usually stored in cache in one of. three schemes: 7 ‘, © Direct mapped ts © Set associative ‘ © Full associative. Embedded System yoitThee Memory + In the ‘direct mapped cache scheme. addresses in cache are divided into section called blocks. Every block is made up of the data, a valid tag (Nag indicating if block is valid), and a tag indicating the memory address(es) represented by the block, . « In this scheme, data is associated block address in the “tag” portion of the block. + The tag is derived from the actual memory address, and is made up of three secti ions: oA tag o Anindex, and o An offset. located by ‘its memory, using The index value indicates the block, the offset value is the offset of the desired address within the block, and the tag is used to compare with the actual address tag to insure the correct address was located. The set associative cache scheme is one in which cache is divided into sections called sets, and within each set, multiple blocks are located at the set-level. The set associative scheme is implemented at the set-level. At the block level, the direct- mapped scheme is used, Essentially, all’ sets are’ checked for the desired address via a universal broadcast request. The desired block is then located according to a tag that maps into a cache’s Particular set. Embedded System 427 Y=* The full associative cache scheme, set associative cache scheme, composed of blocks, In the full associative scheme, however, jy are placed anywhere in cache, and muakt located by searching the entire cache ¢ be time. Very As with any scheme, each of the drawinagy Whereas the set associative ang ““K. associative schemes are slower than the qj! mapped, the direct mapped cache sq! Tuns into performance problems when block sizes get too big, he the On the flip side, the cache and full ass Schemes are less predictable than the iit? mapped cache scheme, since their algonthe™ are more complex. es! Finally, the actual cache swapping scheme jg determined by the architecture. The mos common cache selection schemes include: and” replacement * Optimal, using future _ reference, time, swapping out pages that won't be used in the near future. Least recently used (LRU), which swaps out pages that were used the least recently... FIFO (first in, first out) is another scheme which, as its name impliés, swaps’ out the pages that are the oldest, regardless of how often they are accessed in the system. While a simpler algorithm then LRU, FIFO is much less efficient. Embedded System Wm 428 pit Thee ot recently used (NRU), ¢ not used within a c Swaps out pages tl ertain time period, second chance, FIFO scheme with a referenY , if “0” will be swapped out (a reference bit jg set to “1” when access occurs, and reset to 20” after the check). "wert Clock paging, pages replaced according to clock (how long they have been in memory), in clock order, if they haven’t been accessed (a reference bit is set to “1” when access occurs, and reset to “0” after the check). "> » On a final note, these selection and replacement algorithms are not only limited to swapping data in atid Out of cache, but can be implemented via software for other types of memory swapping. 4.4 Auxiliary Memory + As we know, certain types of memory can be connected directly to the master processor, such’ as RAM, ROM, and cache, while other types.of memory, called secondary memory, are connected to the master processor indirectly via another device. This type of memory, as shown in Figure 4.17, is: the external. secondary. memory and tertiary memory and is commonly ‘referred to as auxiliary or storage memory. * ‘Auxiliary memory. is typically nonvolatile memory used to store larger amounts of regular, archival, and/or backups of data, for longer periods of time to indefinitely. Embedded system ee 429 _ne only data that can be accessed: at any moment in time is the data in contact with the read/write/erase head(s) of the tape drive, When, the Tead/write/erase head(s) ig positioned at the beginning of the tape, the access time for retrieving data . is dependent upon the location of that data I the data bef itis ee ‘Th because all the data before the requested seer Here Memory must be accessed before retrieving the desired 23 ita. * Guuslliary memory can only be aco, ‘ 7 fevice that is plugged inte an emge! a| « Figures 4.18 () and (b) show such as the dis The auxiliary devices used to access Ita or 2 SPically classified as 1/0". tis the auxiliary memories ther plug inte maeaSctted within these 1/0 devices, that the master CPU can access, auxiliary how magnetic tape works, an example of Auudliary memory is typically classified by how its data is accessed (read and written) by its Gecess in which data can only be accessed in Sequential order; random access in which any data can be accessed directly; or direct which is both sequential and random acces} schemes combined. me 1 fadat ais = om =o a0 - == =O =o Magnetic tape is a sequential type of memory, meaning that data can only be accessed in Sequential order, and the information is stored on the tape in a sequence of rows, where sets of rows form blocks. : Embedded System oo sh 430 =o (b) Tape Drive Block 431* Markers on the tape indicate the start ang of the tape. Within ‘the tape, marke indicate the start and end of files. + The data with each file is divided into separated by gaps (of no data) to hardware to accelerate to begin opera example and slow down when needed. each block, data is separated , rows, where each row is a “bit” of © Withi data width * Each track has its own read, head| nine erase heads, + In this storage medium, the ofa polyester transportatior overlying - ferromagnetic powdered-oxide layer (see Tead/write/erase head is also made materials that are highly magnetic (g iron, cobalt, etc.). wscone (Foe the and pj tape is made y mn layer with Figure 4.19), write data onto the Me 0 nthe tape: ide layer on the tape, and a “|” eae of that layer. write) read the datafrom a magnetic ta ack thee ef e heads, nine read heads, “3 ‘oltage is induced into the magnetic coi Up multiple ‘platters, which are’ metal uch covered with a magnetic material (fi tracks, shown in Figure 4.20 (b). Ferm Partin | “Potyeste? Love Backing Figure'4.19 Magnetic Tape Embedded System Yn (a) Internals of Hard Drive oct) Embedded System Yu =. ta ‘ it is passed through Pe, an electrical e data is written in magnetized island ing TH, when the Lape passes the head, wheres ‘Hy is no change in magnetic polarity of the is a polarity the Thagne * curt write head, creating a qanaeretic col fe writ » ‘agnetic |¢ SY of Oe hin the air gap ofthe hen This fa nel at magneties the tape, and ree es | a ing through the write heate went slowing though the write heart tng op reverses the polarity of the magnetic part a) is of Pe, a. of the ‘ad head by the tape passing over it, which then is translated to a “0” or “I” depending on the polarity of the magnetic field on the tape. ‘an Erase Head, for example, would then (highly magne} demagnetize the tape, «As shown in Figure.4,20 (a), hard drive has disks record data, Every platter contains multiple 433Embedded System (b) Hard Drive Platter Figure 4.20 These are separate concentric Representing separate sections for seq, data, Every track is broken down into sec basic subsections which can’ be ttn, written to simultaneously, ae Depending on the size of the hard drive ; have multiple heads, electromagnets record data to and read data from the via switchable magnetic fields, The head is supported by the disk arm th moves around by an actuator, which posi the head at the appropriate location wo a retrieve, and or delete data, ‘ A hard disk is/an example of'a memory’ that uses the direct access memory scheme, where a combination of random access and Sequential access schemes aré used to retrieve and storé data. On each track, data is then stored sequentially. The read/write head (s) can be moved randomly to access the right track, and the sectors of each track are ;then accessed sequentially to locate the appropriate data. ‘Used. to Platters 434 | pike the disks in a hard dy, js broken : re, down into tracks Figure 4.21). 1 2 Compact disk and Sectors (see BP sae Figure 4.21 Compact Disk the key difference between the platters in a hard drive and @ CD is that the film on the purely optical CD isn’t magnetic, but an ultrathin optical metal material. Also, where in a hard drive electromagnet are used to read and write data to a platter, lasers are used to read and write data toa CD. Another key difference between the hard disk device and a CD is that data can be read and written ‘to’ the platters of the disk multiple times, whereas the CD can only be written to one time (with a high intensity laser) and read from (via a low intensity laser) multiple times. There are optical disks that can be, erased, whose film is made up of magnetic and optical metal material. These disks are read, written, and erased via a combination of manipulating lasers and magnetic fields. The main difference between primary: and secondary memory lies in how they interact with the master processor. Embedded system: Ws 435Mein * The master processor is- directly conne : cr ptimary memory, and can only acco’ these Gata directly that is in primary memory,” the| _jntegrated onto the master proces they are * Any other data that the master pe tw Most. common t wants to access (euch as that in seogest | fyanager® found on an empefEe® of memory memory) must be transmitted to py Memory controllers (MEqy4 eat memory first before it is accessible a" ° ae master processor. the o Memory management units (vnauy), a memory controller (enc, gure 4.22, is used to implement ay , prueless interfaces to the differesr prvae Secondary memory is typically controtteg some intermediary device, and is not age, accessible by the master processor. Setly : nt types’ of i ‘mory in the system, such The various access schemes, such as Tandon oral .M, synchronizing access te access, sequential access, direct access, ang DRvying. the , integrity of the memory and So on, can be used. in-either- primary, verifying ee © data’ ‘being secondary memory designs. or transferred. : However, since primary memories typicay need to be faster, they usually employ | random-access scheme, which is normally ¢ faster of the access schemes. 7 * However, the circuitry required for, this type of access method makes primary memory larger, more expensive, and consume, more power than secondary memory, oy Sie fa 4.5 Memory Management of External Memory Figure 4.22 Memory Controller Sample Circuit Memory controllers access memory directly with . the ..memory’s own physical two- dimensional addresses. © There are several different types of memory that can be integrated into a system, and there are also. differences in how software running on the CPU views logical/virtual memory addresses and the actual physical memory addresses the two-dimensional array or row and column. ere) Embedded System : Embedded system The controller manages the request from the Master processor and accesses’ the appropriate banks, awaiting feedback and Wo 437 etreturning that Processor, feedback’ to. the In some cases, where the memo. mainly managing one type of mercer Oll ‘memo; be referred to by that memory’: AL : Ty's ni ty DRAM controlier, cache controller’ che! forth, * ang’ Memory management units (Mmu, allow for the flexibility in a system of Hi Main), larger virtual memory (abstract) space an actual smaller physical memory. i An MMU, shown in Figure 4.23, can outside the master processor and ig Tags translate logical (virtual)“addressest physical addresses (memory mi appir ina as handle memory secunty eee va Protection), controlling cache, handling ¢2 arbitration between the CPU and memory, «“t generating appropriate exceptions. 2 4 nite Mcs8851 K—= Menay ‘68020 Figure 4.23 Motorola/Freescale M68020 External Memory Management *- In the case of translated addresses, the! MMU can use level-1 cache or portions of cache allocated as buffers ‘for’ caching addréss translations, commonly eferred’ to’ as the translation lookaside ‘buffer or TLB, on the processor to store. the mappings of ‘logical addresses to physical addresses. veoh 38 Embedded System Noses niet oes so must suppor aoa hig | yMUS Cranslating ade ous etlinne, tation, paging, men th schemes. al, Segmentation ; 9 8 pemory into large “Ne Vision, re . of isi ns, WHETEAS Paging igh, “ATAbIe ging “ction S> into © dividin, seal memory into smaller freq M8 Up of : size wit poth schemes are implens nits, Whe? vis first divided inty nen ed, logical om ate are then divided into paeee™'® and set 4 : tection scher memory prot mes then prov + The 0, read/write or read-only accessinic’ sh the varioWs Pages and/or segments, a to ‘, memory access is not defined or allow ‘ winterrapt is typically triggered, i i . An interry je also triggered if a page or 5 . is r segment isn’t is Zesible during address translation, ple, in the case of a paging scheme, a ee fa ult, etc. At that point the interrupt Mould need to be handled (the page or segment would have to be retrieved from secondary memory, for example). ‘the scheme supporting segmentation or paging of the MMU typically depends on the software (the operating system). bedded System eS4.6 Board Memory and Perform, * One of the Most cot memory access ti wz: ‘ ime: ancy types of memory," 8M those of other omen. Measures © hierarchic 7 ’s “pe isi S. jemory ies (show, i (bandwidth) ee oimaRce is its throngdt + Mee Secigned in part to improve pigete, 4-1) ), or the CPU’s avera, ‘Ghp,i| were de Prove performanc) rate, a ge execygitt] this _ is because memory acesee ene ‘1 "| execution of programs tends eel ‘ring The performance throughput éan be Sindom, and exhibits . impacted by main’ mem Negati i Ds Bood localities or lory es; i ve} ference. the DRAM used for main men ney, sigh] in memory can is means that systems, in a given u much lower bandwidth than tha have’ + Tod, access most of then data from eeansers: There are specific’ 9! th| Ponited section of memory (locality in space) or Parameters associated with memory (antag access the same data again within that given access times, refresh cycle times fo. Dev period of time (locality in time). Thus, faster and ‘so on) that act as indicators of _ DRAM memory (usually SRAM), performance, Memo, RAM), ‘called cache, was integrated into a memory system for this type of data to be stored and accessed by the CPU. This integration of different types of memories is referred to as the memory hierarchy, Solutions for improvin, memory include: + It is important that the memory hierarchy be effective, since the master processor spends most of its time accessing memory in order to process the applicable data: The memory hierarchy can be evaluated by calculating how many cycles are spent (wasted) due to memory latency or throughput problems, where Memory stall cycles =, Instruction Count. * Memory feferences/Instruction * Cache Miss Rate * Cache Miss Penalty improved by: * Introducing cache, which means fewer slower DRAM accesses with a decrease in the average main memory access time; non-blocking cache will especially decrease any cache miss ° accesses and computations oo ay amount of data. ae © Using DRAMs, such as ‘DRDRAM: and SLDRAM that integrate bus signals into one line, to decrease the time it takes tf arbitrate the -memory "bus, to” access memory. ome Using more memory interface c&nnections (pins), increasing transfer bandwidth. Using a higher signaling rate on’ memory interface connections (pins). o Implementing a memory hierarchy with Penalties, multiple levels of cache, which has faster | Embedded System, We 4-41. Embedded System QGoze ern "i