ICE5xRxxxxxZ

Fixed-frequency 800 V / 950 V CoolSET™

in DIP-7 package
Features
 Integrated 800 V / 950 V avalanche rugged CoolMOS™
 Enhanced Active Burst mode with selectable entry and
exit standby power
 Digital frequency reduction for better overall system efficiency
 Fast startup achieved with cascode configuration PG-DIP-7
 DCM and CCM operation with slope compensation
 Frequency jitter and soft gate driving for low EMI
 Built-in digital soft start
 Integrated error amplifier to support direct feedback
in non-isolated flyback and buck topologies
 Comprehensive protection with input line overvoltage, VCC
overvoltage, VCC undervoltage, overload, open loop and
overtemperature
 All protections are in auto restart mode
 Limited charging current for VCC short to GND
 Pb-free lead plating, halogen-free mold compound, RoHS-compliant

Potential applications
 Auxiliary power supply for home appliances, white goods, TV, PC and server, smart metering
 Blu-ray players, set-top boxes, and LCD/LED monitors

Product validation
Fully qualified according to JEDEC for Industrial Applications.

Description
The ICE5xRxxxxxZ is the fifth-generation of fixed-frequency integrated power IC (CoolSET™) optimized for off-
line switch-mode power supplies in cascode configuration. The CoolSET™ package contains two separate
chips. One is the controller chip and the other is the 800 V / 950 V CoolMOS™ chip. The cascode configuration
helps achieve fast startup. The frequency reduction with soft gate driving and frequency jitter operation offers
lower EMI and better efficiency between a light load and 50% load. The selectable entry and exit standby power
ABM enables flexibility and ultra-low power consumption in standby mode with small and controllable output
voltage ripple. The product has a wide operating range (10.0 V to 25.5 V) of IC power supply and lower power
consumption. The numerous protection functions support the power supply system in failure situations. All
these make the fifth-generation CoolSET™ series an outstanding integrated power stage fixed frequency
flyback and buck converter in the market.

Datasheet Please read the Important Notice and Warnings at the end of this document Rev 1.1
www.infineon.com page 1 of 40 2022-07-19
Fixed-frequency 800 V / 950 V CoolSET™
in DIP-7 package

Wp DO1 Lf1
Cbus RSTART UP Snubber CO1 Cf1 VO1
Ws1
85 ~ 300 VAC RVCC DVCC
CVCC
DO2 Lf2
CO2 Cf2 VO2
Wa Ws2
Dr1~Dr4
VCC GATE DRAIN
RI1
CPS
CoolMOSTM
VIN Power Management

D
RI2 PWM controller
Current Mode Control
Cycle-by-Cycle Gate
GND current limitation Rb1 Rb2 Rovs1 # Rovs3
Driver CS RCS
Digital Control Rc1

FB
Active Burst Mode Control Unit
# Optional Cc1 Cc2

# RSel
RSel (Burst mode detect) C2
Protections TL431
Rovs3 (V02 feedback) TM Optocoupler Rovs2
ICE5xRxxxxCZ CoolSET

Figure 1 Typical application in isolated flyback using TL431 and optocoupler

Wp DO1 Lf1
Cbus RSTART UP Snubber CO1 Cf1 VO1
Ws1
85 ~ 300 VAC RVCC DVCC
CVCC

Wa
Dr1~Dr4
VCC GATE DRAIN LfP1 DP1
TM
CoolMOS VP1 W
Power Management CfP1 CP1 P1

D CPS
PWM controller
Current Mode Control
Cycle-by-Cycle Gate
GND current limitation Driver CS RCS RF2
Digital Control
VERR
Error Amplifier
FB
Active Burst Mode RF1
# Optional Control Unit R1
C2
# RSel

RSel (Burst mode detect) Protections C1

ICE5xRxxxxBZ CoolSET TM

Figure 2 Typical application in non-isolated flyback utilizing integrated error amplifier

ICE5BRxxxxBZ CoolSETTM

DRAIN VCC
Cvc c Rh Daux
Rstartup
GATE VERR
AC line Cin Rcs
CS Rl Cfb D2
FB
C1 GND
C2 *Rs L1
R1 D1 Cout

*Rs is recommended to avoid saturation of inductor (L1) during output short circuit
Figure 3 Typical application in non-isolated buck

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Fixed-frequency 800 V / 950 V CoolSET™
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Output power of fifth-generation fixed-frequency CoolSET™ in flyback design

Table 1 Output power of fifth-generation fixed-frequency CoolSET™ in flyback design

220 V AC 85-300 V AC2 85-300 V AC2
Type Package Marking VDS Fsw RDSon1
±20%2 at DCM at DCM at CCM
ICE5BR4780BZ PG-DIP-7 5BR4780BZ 800 V 65 kHz 4.13 Ω 27.5 W 15 W 16.5 W
ICE5BR3995BZ PG-DIP-7 5BR3995BZ 950 V 65 kHz 3.46 Ω 30 W 16.5 W 18 W
ICE5BR3995CZ PG-DIP-7 5BR3995CZ 950 V 65 kHz 3.46 Ω 30 W 16.5 W 18 W
ICE5AR3995BZ PG-DIP-7 5AR3995BZ 950 V 100 kHz 3.46 Ω 30 W 16.5 W 18 W
ICE5BR2280BZ PG-DIP-7 5BR2280BZ 800 V 65 kHz 2.13 Ω 40 W 22 W 24 W
ICE5AR2280CZ PG-DIP-7 5AR2280CZ 800 V 100 kHz 2.13 Ω 40 W 22 W 24 W

Output current of fifth-generation fixed-frequency CoolSET™ in non-isolated buck design

Infineon® recommends the 65 kHz variant for a non-isolated Buck converter.

Table 2 Output current of fifth-generation generation fixed-frequency CoolSET™ in non-isolated

buck design
85-265 V AC3 Typical output
Type Package Marking VDS Fsw RDSon1
at DCM voltage
ICE5BR4780BZ PG-DIP-7 5BR4780BZ 800 V 65 kHz 4.13 Ω 450 mA
ICE5BR3995BZ PG-DIP-7 5BR3995BZ 950 V 65 kHz 3.46 Ω 550 mA 15 V
ICE5BR2280BZ PG-DIP-7 5BR2280BZ 800 V 65 kHz 2.13 Ω 700 mA

1
Typically at Ti = 25°C (inclusive of low side MOSFET).
2
Calculated maximum output power rating in an open frame design at Ta = 50°C, Tj = 125°C (integrated high voltage MOSFET) and using
minimum drain pin copper area in a 2 oz copper single-sided PCB. The output power figure is for selection purpose only. The actual
power can vary depending on the designs. Contact a technical expert from Infineon® for more information.
3
Calculated maximum output currrent rating in an open frame design at Ta = 50°C, Tj = 125°C (integrated high voltage MOSFET) and using
minimum 100mm2 drain pin copper area in a 2 oz copper single-sided PCB. The output current figure is for selection purpose only.
The actual current can vary depending on the designs. Contact a technical expert from Infineon® for more information.

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Fixed-frequency 800 V / 950 V CoolSET™
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Table of contents

Table of contents
Table of contents ............................................................................................................................ 4
1 Block diagram........................................................................................................................ 6
2 Pin configuration ................................................................................................................... 7
3 Functional description ............................................................................................................ 8
3.1 VCC precharging and typical VCC voltage during startup ......................................................................... 8
3.2 Soft start .................................................................................................................................................. 9
3.3 Normal operation .................................................................................................................................... 9
3.3.1 PWM operation and peak current mode control .............................................................................. 9
3.3.1.1 Switch-on determination.............................................................................................................. 9
3.3.1.2 Switch-off determination ............................................................................................................. 9
3.3.2 Current sense ................................................................................................................................... 10
3.3.3 Frequency reduction ........................................................................................................................ 11
3.3.4 Slope compensation ........................................................................................................................ 11
3.3.5 Oscillator and frequency jittering.................................................................................................... 12
3.3.6 Modulated gate drive ....................................................................................................................... 12
3.4 Peak current limitation ......................................................................................................................... 12
3.4.1 Propagation delay compensation ................................................................................................... 13
3.5 Active burst mode with selectable power level ................................................................................... 14
3.5.1 Entering ABM operation ................................................................................................................... 14
3.5.2 During ABM operation ...................................................................................................................... 14
3.5.3 Leaving ABM operation .................................................................................................................... 14
3.5.4 ABM configuration............................................................................................................................ 16
3.6 Non-isolated/isolated configuration .................................................................................................... 16
3.7 Protection functions ............................................................................................................................. 17
3.7.1 Line overvoltage (CZ version) .......................................................................................................... 17
3.7.2 VCC overvoltage and undervoltage ................................................................................................... 17
3.7.3 Overload or open loop ..................................................................................................................... 17
3.7.4 Overtemperature ............................................................................................................................. 17
3.7.5 VCC short to GND................................................................................................................................ 18
3.7.6 Protection modes............................................................................................................................. 18
4 Electrical characteristics ........................................................................................................ 20
4.1 Absolute maximum ratings ................................................................................................................... 20
4.2 Operating range .................................................................................................................................... 21
4.3 Operating conditions ............................................................................................................................ 21
4.4 Internal voltage reference..................................................................................................................... 22
4.5 PWM section .......................................................................................................................................... 22
4.6 Error amplifier ....................................................................................................................................... 23
4.7 Current sense......................................................................................................................................... 23
4.8 Soft start ................................................................................................................................................ 24
4.9 Active burst mode ................................................................................................................................. 24
4.10 Line overvoltage protection (CZ version) ............................................................................................. 25
4.11 VCC overvoltage protection .................................................................................................................... 25
4.12 Overload protection .............................................................................................................................. 25
4.13 Thermal protection ............................................................................................................................... 25
4.14 CoolMOS™ section ................................................................................................................................. 26
5 CoolMOS™ performance characteristics ................................................................................... 27
6 Output power curve .............................................................................................................. 33
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Table of contents

7 Output current curve ............................................................................................................. 36

8 Package information ............................................................................................................. 37
8.1 Marking .................................................................................................................................................. 38
9 Revision history .................................................................................................................... 39

Datasheet 5 of 40 Rev 1.1

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Fixed-frequency 800 V / 950 V CoolSET™
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Block diagram

1 Block diagram
VCC GATE DRAIN

Line Overvoltage Protection CZ Version Power Management Thermal Protection

250 µs Undervoltage Lockout 50 µs
VVIN_LOVP C7a Blanking Input 16.0V Voltage Internal Tj > Tjcon_OTP Blanking S Q
OVP Reference Bias time OTP
VIN time S Q
Mode
10.0V
Mode
R
100 ns R
Blanking
Autorestart C20 tVCC_OVP_B Tj < Tjcon_OTP-TjHYS_OTP Autorestart
time VVCC_OVP
Protect Protect

CoolMOS TM
Error Amplifier fOSC_2
BZ Version OSC with
Non- Jitter and
Isolated Frequency
Detector Reduction fOSC
OSC D1
VERR
ERR
VERR_REF Gate Driver
VREF Gate
Drive
Protection and PWM Digital Control
RFB
Overload Protection Gate
Drive
Burst
Mode GND
detect VFB_OLP/ C12 tFB_OLP_B
VFB_LB VCS_BLP VREF
VCS_BHP
FB C13
Slope
Active Burst Block Peak current Comp
limit
Burst Mode
25kΩ

VCS_Nx Leading
Level Select
C15 Edge 10kΩ
VFB_EBHP
VFB_EBLP Active
Blanking CS
1pF D2
No burst C9 tFB_BEB tCS_LEB
Burst Mode PWM
Comparator C15a
2pF V1 CPWM
C10 Soft-start
VFB_BOn PWM OP Delay
VPWM
C19
tCS_STG VCS_STG
C11 GPWM
VFB_BOff Current Mode
Slope Compensation/Current Limiting

Figure 4 Block diagram

Note: Junction temperature of the controller chip is sensed for overtemperature protection. The
CoolMOSTM is a separate chip from the controller chip in the same package. Refer to the design
guide or consult a technical expert for the proper thermal design.

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Pin configuration

2 Pin configuration
The pin configuration is shown in Figure 5 and the functions are described in Table 3.

Figure 5 Pin configuration

Table 3 Pin definitions and functions

Pin Symbol Function
Error amplifier
VERR
VERR pin is internally connected to the transconductance error amplifier for a non-
(BZ version)
isolated converter. Connect this pin to GND for an isolated converter.
1 Input line overvoltage protection (LOVP)
VIN VIN pin is connected to the bus via a resistor divider (see Figure 1) to sense the line
(CZ version) voltage. Internally, it is connected to the line overvoltage comparator which stops the
switching when a LOVP condition occurs. To disable LOVP, connect this pin to GND.
Feedback and ABM entry and exit control
2 FB FB pin combines the functions of feedback control, selectable burst entry/exit control
and overload/open loop protection.
Current sense
The CS pin is connected to the shunt resistor for the primary current sensing externally
3 CS
and to the PWM signal generator block for switch-off determination (together with the
feedback voltage) internally.
Gate driver output
The GATE pin is connected to the Gate of the internal CoolMOS™ and additionally, a pull-
4 GATE
up resistor is connected from a bus voltage to turn on the internal CoolMOS™ for charging
up the VCC capacitor during startup.
DRAIN (Drain of integrated CoolMOS™)
5 DRAIN
The DRAIN pin is connected to the drain of the integrated CoolMOS™.
VCC (Positive voltage supply)
7 VCC The VCC pin is the positive voltage supply to the IC. The operating range is between
VVCC_OFF and VVCC_OVP.
Ground
8 GND
The GND pin is the common ground of the controller.

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Functional description

3 Functional description
3.1 VCC precharging and typical VCC voltage during startup
As shown in Figure 1, once the line input voltage is applied, a rectified voltage appears across the capacitor
CBUS. The pull-up resistor RSTARTUP provides a current to charge the Ciss (input capacitance) of CoolMOS™ and
gradually generate one voltage level. If the voltage over Ciss is high enough, CoolMOS™ and the VCC capacitor are
charged through the primary inductance of a transformer LP, CoolMOS™ and the internal diode D1 with the two
steps constant current source IVCC_ Charge11 and IVCC_ Charge31.
A very small constant current source (IVCC_Charge1) is charged to the VCC capacitor until VCC reaches VCC_SCP to protect
the controller from the VCC pin short to ground during the startup. After this, the second step constant current
source (IVCC_Charge3) is provided to charge the VCC capacitor further, until the VCC voltage exceeds the turned-on
threshold VVCC_ON. As shown in the time phase I in Figure 6, the VCC voltage increases almost linearly with two
steps.

VVCC
VVCC_ON I II III

VVCC_OFF
tA tB
VVCC_SCP t

IVCC

IVCC_Normal2
t
0
IVCC_Charge1

IVCC_Charge2/3
-IVCC t1 t2

Figure 6 VCC voltage and current at startup

The time for the VCC precharging can then be calculated as:

𝑉𝑉𝐶𝐶_𝑆𝐶𝑃 × 𝐶𝑉𝐶𝐶 (𝑉𝑉𝐶𝐶_𝑂𝑁 − 𝑉𝑉𝐶𝐶_𝑆𝐶𝑃 ) × 𝐶𝑉𝐶𝐶 (1)

𝑡1 = 𝑡A + 𝑡B = +
𝐼𝑉𝐶𝐶_𝐶ℎ𝑎𝑟𝑔𝑒1 𝐼𝑉𝐶𝐶_𝐶ℎ𝑎𝑟𝑔𝑒3

When the VCC voltage exceeds the VCC turn on threshold VVCC_ON at time t1, the IC starts to operate with soft start.
Due to the power consumption of the IC and the fact that there is still no energy from the auxiliary winding to
charge the VCC capacitor before the output voltage is built up, the VCC voltage drops (phase II). Once the output
voltage rises close to regulation, the auxiliary winding starts to charge the VCC capacitor from the time t2 onward
and delivering the IVCC_ Normal22to the CoolSET™. VCC then reaches a constant value depending on the output load.

1
IVCC_ Charge1/2/3 is charging current from the controller to VCC capacitor during startup.
2
IVCC_ Normal2 is supply current from VCC capacitor or auxiliary winding to the CoolSET™ during normal operation.
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Functional description

3.2 Soft start

As shown in Figure 7, the IC starts to operate with a soft start at time ton. The switching stresses on the power
MOSFET, diode, and transformer are minimized during soft start. The soft start implemented in ICE5xRxxxxxZ is
a digital time-based function. The preset soft start time is tSS (12 ms) with four steps. If not limited by other
functions, the peak voltage on CS pin increases step by step from 0.3 V to finally VCS_N (0.8 V). The normal
feedback loop takes over the control when the output voltage reaches its regulated value.

Figure 7 Maximum current sense voltage during soft start

3.3 Normal operation

The PWM controller during normal operation consists of a digital signal processing circuit including regulation
control and an analog circuit including a current measurement unit and a comparator. Details about the full
operation of the CoolSET™ in normal operation are illustrated in the following paragraphs.

3.3.1 PWM operation and peak current mode control

3.3.1.1 Switch-on determination

The power MOSFET turn-on is synchronized with the internal oscillator with a switching frequency FSW that
corresponds to the voltage level VFB (see Figure 9).

3.3.1.2 Switch-off determination

In peak current mode control, the PWM comparator monitors voltage V1 (see Figure 4), which represents the
instantaneous current of the power MOSFET. When V1 exceeds VFB, the PWM comparator sends a signal to
switch off the GATE of the power MOSFET. Therefore, the peak current of the power MOSFET is controlled by
the feedback voltage VFB (see Figure 8).
At switch-on transient of the power MOSFET, a voltage spike across RCS can cause V1 to increase and exceed VFB.
To avoid a false switch off, the IC has a blanking time tCS_LEB before detecting the voltage across RCS to mask the
voltage spike. Therefore, the minimum turn on time of the power MOSFET is tCS_LEB.
If the voltage level at V1 takes a long time to exceed VFB, the IC has implemented a maximum duty cycle control
to force the power MOSFET to switch off when DMAX = 0.75 is reached.

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Functional description

Figure 8 Pulse width modulation

3.3.2 Current sense

The power MOSFET current generates a voltage VCS across the current sense resistor RCS connected between the
CS pin and the GND pin. VCS is amplified with gain GPWM, then, added with an offset VPWM to become V1 as
described below in equation 3.

𝑉CS = 𝐼D × 𝑅CS (2)

𝑉1 = 𝑉CS × 𝐺PWM + 𝑉PWM (3)

where:
VCS : CS pin voltage
ID : Power MOSFET current
RCS : Resistance of the current sense resistor
V1 : Voltage level compared to VFB as described in chapter 3.3.1.2
GPWM : PWM-OP gain
VPWM : Offset for voltage ramp

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Fixed-frequency 800 V / 950 V CoolSET™
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Functional description

If the voltage at the current sense pin is lower than the preset threshold VCS_STG after the time tCS_STG_SAM for three
consecutive pulses during on-time of the power switch, this abnormal VCS triggers the IC into auto restart mode.

3.3.3 Frequency reduction

Frequency reduction is implemented in ICE5xRxxxxxZ to achieve a better efficiency during the light load.
At light load, the reduced switching frequency FSW improves efficiency by reducing the switching loses.
When the load decreases, VFB decreases as well. FSW is dependent on the VFB as shown in Figure 9. Therefore, FSW
decreases as the load decreases.
For example, FSW at high load is 65 kHz and starts to decrease at VFB = 1.7 V. There is no further frequency
reduction once it reached the fOSC2_MIN even the load is further reduced.

fSW(VFB) VCS (VFB)

Vcs
VCS_N
0.80 V

fOSC2 / fOSC4 Fsw

65 kHz / 100 kHz

fOSC2_ABM / fOSC4_ABM BM
54 kHz / 83 kHz

fOSC2_MIN / fOSC4_MIN No B M
28 kHz / 43 kHz
BM VCS_BHP / VCS_BLP
0.27 V /0.22 V

No B M

VFB
VFB_EBxP VFB_OLP
0.5 V 0.93 / 1.03 V 1.35 V 1.7 V 2.73 V
Figure 9 Frequency reduction curve

3.3.4 Slope compensation

ICE5xRxxxxxZ can operate at continuous conduction mode (CCM). At CCM operation, a duty cycle greater than
50% may generate a subharmonic oscillation. To avoid the subharmonic oscillation, slope compensation is
added to VCS pin when the gate of the power MOSFET is turned on for more than 40% of the switching cycle
period.
The relationship between VFB and the VCS for CCM operation is described in equation 4:

𝑉FB = 𝑉CS × 𝐺PWM + 𝑉PWM + 𝑀COMP × (𝑇ON − 40% × 𝑇PERIOD ) (4)

where:
TON : Gate turn on time of the power MOSFET

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Functional description

MCOMP : Slope compensation rate

TPERIOD : Switching cycle period
Slope compensation circuit is disabled and no slope compensation is added into the VCS pin during Active Burst
mode to save the power consumption.

3.3.5 Oscillator and frequency jittering

The oscillator generates a frequency of 65 kHz / 100 kHz with frequency jittering of ±4% at a jittering period of
TJITTER (4 ms). The frequency jittering helps to reduce conducted EMI.
A capacitor, a current source, and a current sink that determine the frequency are integrated. The charging and
discharging current of the implemented oscillator capacitor are internally trimmed to achieve a highly accurate
switching frequency.
Once the soft start period is over and when the IC goes into normal operating mode, the frequency jittering is
enabled. There is also frequency jittering during frequency reduction.

3.3.6 Modulated gate drive

The drive-stage is optimized for EMI consideration. The switch-on speed is slowed down before it reaches the
CoolMOS™ turn on threshold. That is a slope control of the rising edge at the output of the driver (see Figure
10). Thus the leading switch spike during turn on is minimized.

Figure 10 Gate rising waveform

3.4 Peak current limitation

There is a cycle-by-cycle peak current limitation realized by the current limit comparator to provide primary
over-current protection. The primary current generates a voltage VCS across the current sense resistor RCS
connected between the CS pin and the GND pin. If the voltage VCS exceeds an internal voltage limit VCS_N, the
comparator immediately turns off the gate drive.
The primary peak current IPEAK_PRI can be calculated as below:

𝐼PEAK_PRI = 𝑉CS_N⁄𝑅CS (5)

To avoid mistriggering caused by the MOSFET switch on transient voltage spikes, a leading edge-blanking time
(tCS_LEB) is integrated in the current sensing path.

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Functional description

3.4.1 Propagation delay compensation

In case of an overcurrent detection, there is always a propagation delay from sensing the VCS to switching the
power MOSFET off. An overshoot on the peak current Ipeak caused by the delay depends on the ratio of dI/dt of
the primary current (see Figure 11).

Figure 11 Current limiting

The overshoot of Signal2 is larger than Signal1 due to the steeper rising waveform. This change in the slope is
depending on the AC input voltage. Propagation delay compensation is integrated to reduce the overshoot due
to dI/dt of the rising primary current. Thus the propagation delay time between exceeding the current sense
threshold VCS_N and the switching off of the power MOSFET is compensated over wide bus voltage range.
Current limiting becomes more accurate, which results in a minimum difference of overload protection
triggering power between low and high AC line input voltage.
Under CCM operation, the same VCS do not result in the same power. To achieve a close overload triggering level
for CCM, ICE5xRxxxxxZ has implemented a two compensation curve as shown Figure 12. One of the curve is
used for TON greater than 0.40 duty cycle and the other is for lower than 0.40 duty cycle.

Figure 12 Dynamic voltage threshold VCS_N

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Functional description

Similarly, the same concept of propagation delay compensation is also implemented in ABM with reduced
level. With this implementation, the entry and exit Burst mode power can be close between low and high AC
line input voltage.

3.5 Active burst mode with selectable power level

At light load condition, the IC enters Active Burst mode (ABM) operation to minimize the power consumption.
Details about the ABM operation are explained in the following paragraphs.

3.5.1 Entering ABM operation

The system enters into ABM operation when the two conditions below are met:
 The FB voltage is lower than the threshold of VFB_EBLP/VFB_EBHP, depending on the burst configuration option
setup.
 A certain blanking time tFB_BEB.

Once all of these conditions are fulfilled, the ABM flip-flop is set and the controller enters ABM operation. This
multicondition determination for entering ABM operation prevents mis-triggering of entering ABM operation,
so that the controller enters ABM operation only when the output power is really low.

3.5.2 During ABM operation

After entering ABM, the PWM section is inactive, making the VOUT start to decrease. As the VOUT decreases, VFB
rises. Once VFB exceeded VFB_BOn, the internal circuit is again activated by the internal bias to start with the
switching.
If the PWM is still operating and the output load is still low, VOUT increases and VFB signal starts to decrease.
When VFB reaches the low threshold VFB_BOff, the internal bias is reset again and the PWM section is disabled with
no switching until VFB increases back to exceed VFB_BOn threshold.
In ABM, VFB is like a sawtooth waveform swinging between VFB_BOff and VFB_BOn shown in Figure 13.
During ABM, the peak current IPEAK_ABM of the power MOSFET is defined by:

𝐼PEAK_ABM = 𝑉CS_BxP⁄𝑅CS (6)

where VCS_BxP is the peak current limitation in ABM.

3.5.3 Leaving ABM operation

The FB voltage immediately increases if there is a sudden increase in the output load. When VFB exceeds VFB_LB, it
leaves ABM and the peak current limitation threshold voltage returns back to VCS_N immediately.

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Functional description

VFB
Entering Active Burst Mode Leaving Active Burst Mode
VFB_LB
VFB_BOn
VFB_BOff

VFB_EBHP/VFB_EBLP

Blanking Window (tFB_BEB) t

VCS

VCS_N
Current limit level during Active Burst Mode

VCS_BHP/VCS_BLP

t
VVCC

VVCC_off

t
VO
Max. Ripple < 1%

t
Burst Mode Operation

Figure 13 Signals in ABM

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Functional description

3.5.4 ABM configuration

The burst mode entry level can be selected by changing the different resistance RSel at FB pin. There are three
configuration options depending on RSel, which corresponds to the options of no ABM (option 1), low range of
ABM power (option 2) and high range of ABM power (option 3). The table below shows the control logic for the
entry and exit level with the FB voltage.

Table 4 ABM configuration option setup

Option RSel VFB VCS_BxP Entry level Exit level
VFB_EBxP VFB_LB
1 < 470 kΩ VFB < VFB_P_BIAS1 - No ABM No ABM
2 720 kΩ ~ 790 kΩ VFB_P_BIAS1 < VFB < VFB_P_BIAS2 0.22 V 0.93 V 2.73 V
3 (default) > 1210 kΩ VFB > VFB_P_BIAS2 0.27 V 1.03 V 2.73 V

During IC first startup, the controller preset the ABM selection to option 3, the FB resistor (RFB) is turned off by
internal switch S2 (see Figure 14) and a current source Isel is turned on instead. From VCC = 4.44 V to VCC on
threshold, the FB pin starts to charge resistor RSel with current ISel to a certain voltage level. When VCC reaches VCC
on threshold, the FB voltage is sensed. The burst mode option is then chosen according to the FB voltage level.
After finishing the selection, any change on the FB level does not change the burst mode option and the current
source (Isel) is turned off while the FB resistor (RFB) is connected back to the circuit (Figure 14).

Figure 14 ABM detect and adjust

3.6 Non-isolated/isolated configuration

ICE5xRxxxxBZ has a VERR pin, which is connected to the input of an integrated error amplifier to support a non-
isolated converter (see Figure 2). When VCC is charging and before reaching the VCC on threshold, a current
source IERR_P_BIAS from the VERR pin together with RF1 and RF2 generates a voltage across it. If the VERR voltage is
more than VERR_P_BIAS (0.2 V), non-isolated configuration is selected, otherwise, isolated configuration is selected.
In an isolated configuration, the error amplifier output is disconnected from the FB pin.
In case of non-isolated configuration, the voltage divider RF1 and RF2 are used to sense the output voltage and
compared with the internal reference voltage VERR_REF. The difference between the sensed voltage and the

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Functional description

reference voltage is converted as an output current by the error amplifier. The output current charges or
discharges the resistor and capacitor network connected at the FB pin for the loop compensation.

3.7 Protection functions

The ICE5xRxxxxxZ provides numerous protection functions that considerably improve the power supply system
robustness, safety, and reliability. The following table summarizes these protection functions and the
corresponding protection mode whether as a non-switch auto restart, auto restart or odd skip auto restart
mode. Refer to Figure 15, Figure 16 and Figure 17 for the waveform illustration of protection modes.

Table 5 Protection functions

Protection functions Normal mode Burst mode Protection mode
Burst ON Burst OFF
Line overvoltage (CZ version) √ √ √ Non-switch auto restart
VCC overvoltage √ √ n/a1 Odd skip auto restart
VCC undervoltage √ √ √ Auto restart
Overload or open loop √ n/a1 n/a1 Odd skip auto restart
Overtemperature √ √ √ Non-switch auto restart
VCC short to GND √ √ √ No startup

3.7.1 Line overvoltage (CZ version)

The AC line overvoltage protection (LOVP) is detected by the sensing bus capacitor voltage through the VIN pin
via the voltage divider resistors, Rl1 and Rl2 (Figure 1). Once the VVIN voltage is higher than the line overvoltage
threshold (VVIN_LOVP), the controller enters into protection mode until VVIN is lower than VVIN_LOVP. This protection
can be disabled by connecting the VIN pin to GND.

3.7.2 VCC overvoltage and undervoltage

During operation, the VCC voltage is continuously monitored. If VCC is either below VVCC_OFF for 50 µs (tVCC_OFF_B) or
above VVCC_OVP for 55 µs (tVCC_OVP_B), the power MOSFET is kept switch off. After the VCC voltage falls below the
threshold VVCCoff, the new startup sequence is activated. The VCC capacitor is then charged up. Once the voltage
exceeds the threshold VVCC_ON, the IC begins to operate with a new soft start.

3.7.3 Overload or open loop

In case of open control loop or output overload, the FB voltage is pulled up. When VFB exceeds VFB_OLP after a
blanking time of tFB_OLP_B, the IC enters odd skip auto restart mode. The blanking time enables the converter to
provide a peak power in case the increase in VFB is due to a sudden load increase.

3.7.4 Overtemperature
If the junction temperature of the controller exceeds Tjcon_OTP, the IC enters into overtemperature protection
(OTP) auto restart mode. The IC has also implemented with a 40°C hysteresis. That means the IC can only be
recovered from OTP when the controller junction temperature is dropped 40°C lower than the
overtemperature trigger point.

1
Not applicable.
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3.7.5 VCC short to GND

To limit the power dissipation of the startup circuit at VCC short to GND condition, the VCC charging current is
limited to a minimum level of IVCC_ Charge1. With such low current, the power loss of the IC is limited to prevent
overheating.

3.7.6 Protection modes

All the protections are in auto restart mode with a new soft start sequence. The three auto restart modes are
illustrated in the following figures.

Fault Fault released

detected

Switching start at the

Start up and detect at
VVCC every charging cycle
following restartt cycle

VCC_ON

VCC_OFF

VCS t
No switching

Figure 15 Non-switch auto restart mode

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Functional description

Fault Fault released

detected

Start up and detect at every

charging cycle Switching start at the
VVCC t cycle
following restart

VCC_ON

VCC_OFF

VCS t

Figure 16 Auto restart mode

Fault Fault released

detected

Start up and detect at

every even charging
cycle Switching start at the
VVCC following event restart
No detect No detect cycle

VCC_ON

VCC_OFF

VCS t

Figure 17 Odd skip auto restart

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Electrical characteristics

4 Electrical characteristics
Attention: All voltages are measured with respect to ground (pin 8). The voltage levels are valid if other
ratings are not violated.

4.1 Absolute maximum ratings

Attention: Stresses above the maximum values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding any one of these values may cause
irreversible damage to the integrated circuit. For the same reason, make sure that any capacitor
that is connected to pin 7 (VCC) is discharged before assembling the application circuit.
Ta = 25°C unless otherwise specified.

Table 6 Absolute maximum ratings

Parameter Symbol Limit values Unit Note or
Min. Max. test condition
Drain voltage VDRAIN V Tj = 25°C
ICE5xRxx80xZ 800 –
ICE5xR3995xZ 950 –
Pulse drain current ID,Pulse A
ICE5xR3995xZ – 5.0 1

ICE5BR4780BZ – 2.61
ICE5xR2280xZ – 5.82
Avalanche energy, repetitive, tAR limited EAR mJ
by maximal Tj = 150°C and Tj,Start = 25°C
ICE5xR2280xZ – 0.05 ID = 0.40 A, VDD = 50 V
ICE5BR4780BZ – 0.02 ID = 0.20 A, VDD = 50 V
ICE5xR3995xZ – 0.04 ID = 0.20 A, VDD = 50 V
Avalanche current, repetitive, tAR limited IAR A
by maximal Tj = 150°C and Tj,Start = 25°C
ICE5BR4780BZ – 0.20
ICE5xR3995xZ – 0.20
ICE5xR2280xZ – 0.40
VCC supply voltage VCC -0.3 27.0 V
GATE voltage VGATE -0.3 27.0 V
FB voltage VFB -0.3 3.6 V
VERR voltage VERR -0.3 3.6 V
CS voltage VCS -0.3 3.6 V
VIN voltage VVIN -0.3 3.6 V
Maximum DC current on any pin -10.0 10.0 mA Except DRAIN and CS pin.

1
Pulse width tP limited by Tj,max.
2
Pulse width tP = 20 µs and limited by Tj,max.
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Parameter Symbol Limit values Unit Note or

Min. Max. test condition
ESD robustness HBM VESD_HBM – 2000 V According to EIA/JESD22.
ESD robustness CDM VESD_CDM – 500 V
Junction temperature range Tj -40 150 °C Controller and CoolMOS™.
Storage temperature TSTORE -55 150 °C
Thermal resistance (junction-ambient) RthJA K/W Setup according to the
ICE5BR4780BZ – 107 JEDEC standard JESD51
ICE5xR3995xZ – 106 and using minimum drain
pin copper area in a 2 oz
ICE5xR2280xZ – 104
copper single-sided PCB.

4.2 Operating range

Note: Within the operating range, the IC operates as described in the functional description.

Table 7 Operating range

Parameter Symbol Limit values Unit Note or
Min. Max. test condition
VCC supply voltage VVCC VVCC_OFF VVCC_OVP
Junction temperature of controller TjCon_op -40 TjCon_OTP °C Maximum value limited due to
OTP of controller chip.
Junction temperature of TjCoolMOS_op -40 150 °C
CoolMOS™

4.3 Operating conditions

Note: The electrical characteristics involve the spread of values within the specified supply voltage and
junction temperature range TJ from – 40°C to 125°C. Typical values represent the median values,
which are related to 25°C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.

Table 8 Operating conditions

Parameter Symbol Limit values Unit Note or
Min. Typ. Max. test Condition
VCC charge current IVCC_Charge1 -0.35 -0.20 -0.09 mA VVCC = 0 V, RStartUp = 50 MΩ
and VDRAIN = 90 V
IVCC_Charge2 – -3.2 – mA VVCC = 3 V, RStartUp = 50 MΩ
and VDRAIN = 90 V
IVCC_Charge3 -5 -3 -1 mA VVCC = 15 V, RStartUp = 50 MΩ
and VDRAIN = 90 V
Current consumption, startup current IVCC_Startup – 0.25 – mA VVCC = 15 V
Current consumption, normal with IVCC_Normal1 – 0.9 – mA IFB = 0 A
Inactive Gate

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Electrical characteristics

Parameter Symbol Limit values Unit Note or

Min. Typ. Max. test Condition
Current consumption, normal with IVCC_Normal2 mA
Active Gate
ICE5BR2280BZ – – 1.89
ICE5BR3995xZ – – 1.82
ICE5AR3995BZ – – 2.21
ICE5BR4780BZ – – 1.69
ICE5AR2280CZ – – 2.31
Current consumption, auto restart IVCC_AR – 410 – µA
Current consumption, Burst mode – IVCC_Burst – 0.54 – mA
isolated Mode_ISO

Current consumption, Burst mode – IVCC_Burst – 0.61 – mA

non-isolated Mode_NISO

VCC turn-on threshold voltage VVCC_ON 15.3 16.0 16.5 V

VCC turn-off threshold voltage VVCC_OFF 9.4 10.0 10.4 V
VCC short circuit protection VVCC_SCP – 1.1 1.9 V
VCC turn-off blanking tVCC_OFF_B – 50 – µs

4.4 Internal voltage reference

Table 9 Internal voltage reference
Parameter Symbol Limit values Unit Note or
Min. Typ. Max. test condition
Internal reference voltage VREF 3.20 3.30 3.39 V Measured at FB pin
IFB = 0 A

4.5 PWM section

Table 10 PWM section
Parameter Symbol Limit values Unit Note or
Min. Typ. Max. test condition
Fixed oscillator frequency – fOSC3 92 100 108 kHz
100 kHz fOSC4 94 100 106 kHz Tj = 25°C
Fixed oscillator frequency – fOSC4_ABM 71 83 94 kHz Tj = 25°C
100 kHz (ABM)
Fixed oscillator frequency – fOSC4_MIN 36 43 51 kHz Tj = 25°C
100 kHz (minimum Fsw)
Fixed oscillator frequency – fOSC1 59.8 65 70.2 kHz
65 kHz fOSC2 61.1 65 68.9 kHz Tj = 25°C
Fixed oscillator frequency – fOSC2_ABM 46.2 54 61.1 kHz Tj = 25°C
65 kHz (ABM)

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Electrical characteristics

Parameter Symbol Limit values Unit Note or

Min. Typ. Max. test condition
Fixed oscillator frequency – fOSC2_MIN 23.4 28 33.2 kHz Tj = 25°C
65 kHz (minimum Fsw)
Frequency jittering range FJITTER – ±4 – % Tj = 25°C
Frequency jittering period TJITTER – 4 – ms Tj = 25°C
Maximum duty cycle DMAX 70 75 80 %
Feedback pull-up resistor RFB 11 15 20 kΩ
PWM-OP gain GPWM 1.91 2.03 2.16
Offset for voltage ramp VPWM 0.42 0.50 0.58 V
Slope compensation rate -
MCOMP 41 50 58 mV/μs Vcs = 0 V
100 kHz
Slope compensation rate -
MCOMP 26.5 32.5 38 mV/μs Vcs = 0 V
65 kHz

4.6 Error amplifier

Table 11 Error amplifier
Parameter Symbol Limit values Unit Note or
Min. Typ. Max. test condition
Transconductance GERR_M 2.14 2.80 3.44 mA/V
Transconductance – Burst mode GERR_BM 6.9 9.2 11.6 mA/V
Error amplifier source current IERR_SOURCE 85 150 223 μA
Error amplifier sink current IERR_SINK 85 150 223 μA
Error amplifier reference voltage VERR_REF 1.76 1.80 1.84 V
Error amplifier output dynamic VERR_DYN 0.05 – 3.15 V
range of transconductance
Error amplifier mode bias current IERR_P_BIAS 9.5 14.0 18.5 μA
Error amplifier mode threshold VERR_P_BIAS 0.16 0.20 0.24 V

4.7 Current sense

Table 12 Current sense
Parameter Symbol Limit values Unit Note or
Min. Typ. Max. test condition
Peak current limitation in normal VCS_N 0.72 0.80 0.88 V dVsense/dt = 0.41 V/μ s
operation
Peak current limitation in normal VCS_N15 0.74 0.79 0.84 V
operation, 15% of TON
Leading edge-blanking time tCS_LEB 70 220 365 ns
Peak current limitation in ABM - VCS_BHP 0.23 0.27 0.31 V
high power

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Peak current limitation in ABM - VCS_BLP 0.18 0.22 0.26 V

low power
Abnormal CS voltage threshold VCS_STG 0.06 0.10 0.15 V
Abnormal CS voltage consecutive PCS_STG – 3 – cycle
trigger
Abnormal CS voltage sample tCS_STG_SAM tPERIOD tPERIOD tPERIOD µs
period × 0.36 × 0.4 × 0.44

4.8 Soft start

Table 13 Soft start
Parameter Symbol Limit values Unit Note or
Min. Typ. Max. test condition
Soft start time tSS 7.3 12.0 – ms
Soft start time step tSS_S1 – 3 – ms
CS peak voltage at first step of soft VSS11 – 0.30 – V CS peak voltage.
start
Step increment of CS peak voltage VSS_S1 – 0.15 – V CS peak voltage.
in soft start

4.9 Active burst mode

Table 14 Active Burst mode
Parameter Symbol Limit values Unit Note or
Min. Typ. Max. test condition
Charging current to select burst Isel 2.5 3.0 3.5 µA
mode
Burst mode selection reference VFB_P_BIAS1 1.65 1.73 1.80 V
voltage threshold
Burst mode selection reference VFB_P_BIAS2 2.76 2.89 3.01 V
voltage threshold
Feedback voltage for entering VFB_EBHP 0.98 1.03 1.08 V
ABM for high power
Feedback voltage for entering VFB_EBLP 0.88 0.93 0.98 V
ABM for low power
Blanking time for entering ABM tFB_BEB – 36 – ms
Feedback voltage for leaving ABM VFB_LB 2.63 2.73 2.83 V
Feedback voltage for burst-on VFB_Bon_ISO 2.26 2.35 2.45 V
– isolated case
Feedback voltage for burst-off VFB_BOff_ISO 1.88 2.00 2.05 V
– isolated case

1
Not subject to production test, specified by design.
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Electrical characteristics

Feedback voltage for burst-on VFB_Bon_NISO 1.88 1.95 2.05 V

– non-isolated case
Feedback voltage for burst-off VFB_BOff_NISO 1.50 1.55 1.64 V
– non-isolated case

4.10 Line overvoltage protection (CZ version)

Table 15 Line OVP
Parameter Symbol Limit values Unit Note or
Min. Typ. Max. test condition
Line overvoltage threshold VVIN_LOVP 2.75 2.85 2.95 V Test Condition
test conditions
Line overvoltage blanking tVIN_LOVP_B – 250 – µs

4.11 VCC overvoltage protection

Table 16 VCC overvoltage protection
Parameter Symbol Limit values Unit Note or
Min. Typ. Max. test condition
VCC overvoltage threshold VVCC_OVP 24.0 25.5 27.0 V Test Condition
test conditions
VCC overvoltage blanking tVCC_OVP_B – 55 – µs

4.12 Overload protection

Table 17 Overload protection
Parameter Symbol Limit values Unit Note or
Min. Typ. Max. test condition
Overload detection threshold for VFB_OLP 2.63 2.73 2.83 V
OLP protection at FB pin
Overload protection blanking time tFB_OLP_B 30 54 – ms

4.13 Thermal protection

Table 18 Thermal protection
Parameter Symbol Limit values Unit Note or
Min. Typ. Max. test condition
Overtemperature protection Tjcon_OTP 1
129 140 150 °C Junction temperature of
Overtemperature hysteresis TjHYS_OTP – 40 – °C the controller chip (not
the CoolMOS™ chip).
Overtemperature blanking time Tjcon_OTP_B – 50 – µs

1
Not subject to production test, specified by design.
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Electrical characteristics

4.14 CoolMOS™ section

Table 19 ICE5xRxxxxxZ
Parameter Symbol Limit values Unit Note or
Min. Typ. Max. test condition
Drain source breakdown voltage V(BR)DSS V Tj = 25°C
ICE5xRxx80xZ 800 – –
ICE5xR3995xZ 950 – –
Drain source on-resistance RDSon Ω
(inclusive of low side MOSFET)
ICE5BR4780BZ – 4.13 4.85 Tj = 25°C
– 8.691 – Tj = 125°C at ID = 0.4 A
ICE5xR2280xZ – 2.13 2.35 Tj = 25°C
– 4.311 – Tj = 125°C at ID = 1 A
ICE5xR3995xZ – 3.46 4.05 Tj = 25°C
– 7.691 – Tj = 125°C at ID = 0.8 A
Effective output capacitance, Co(er) pF
energy related1
ICE5BR4780BZ – 3 – VGS = 0 V, VDS = 0 ~ 500 V
ICE5xR2280xZ – 7 – VGS = 0 V, VDS = 0 ~ 500 V
ICE5xR3995xZ – 5 – VGS = 0 V, VDS = 0 ~ 400 V
Rise time trise2 – 30 – ns
Fall time tfall 2
– 30 – ns

1
Not subject to production test, specified by design.
2
Measured in a typical flyback / buck converter application.
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CoolMOS™ performance characteristics

5 CoolMOS™ performance characteristics

Figure 18 Safe operating area (SOA) curve for ICE5BR4780BZ

Figure 19 Safe operating area (SOA) curve for ICE5xR2280xZ

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Figure 20 Safe operating area (SOA) curve for ICE5xR3995xZ

Figure 21 Power dissipation of ICE5BR4780BZ; Ptot = f(Ta) (Maximum ratings as given in chapter 4.1
must not be exceeded)

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Figure 22 Power dissipation of ICE5xR3995xZ; Ptot = f(Ta) (Maximum ratings as given in chapter 4.1
must not be exceeded)

Figure 23 Power dissipation of ICE5xR2280xZ; Ptot = f(Ta) (Maximum ratings as given in chapter 4.1
must not be exceeded)

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Figure 24 Drain-source breakdown voltage ICE5xRxx80xZ; VBR(DSS) = f(TJ), ID = 1 mA

Figure 25 Drain-source breakdown voltage ICE5xR3995xZ; VBR(DSS) = f(TJ), ID = 1 mA

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CoolMOS™ performance characteristics

Figure 26 Typical CoolMOS™ capacitances of ICE5BR4780BZ (C = f(VDS); VGS = 0 V; f = 250 kHz)

Figure 27 Typical CoolMOS™ capacitances of ICE5xR2280xZ (C = f(VDS); VGS = 0 V; f = 250 kHz)

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Figure 28 Typical CoolMOS™ capacitances of ICE5xR3995xZ (C = f(VDS); VGS = 0 V; f = 250 kHz)

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Output power curve

6 Output power curve

The calculated output power curves versus ambient temperature are shown below. The curves are derived
based on a typical DCM/CCM flyback in an open frame design setting the maximum Tj of the integrated
CoolMOS™ at 125°C, using minimum drain pin copper area in a 2 oz copper single-sided PCB and steady state
operation only (no design margins for abnormal operation modes are included).
The output power figure is for selection purpose only. The actual power can vary depending on a particular
design. In a power supply system, appropriate thermal design margins must be considered to make sure that
the operation of the device is within the maximum ratings given in chapter 4.1.

Figure 29 Output power curve of ICE5BR4780BZ

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Output power curve

Figure 30 Output power curve of ICE5BR3995xZ

Figure 31 Output power curve of ICE5AR3995BZ

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Output power curve

Figure 32 Output power curve of ICE5AR2280CZ

Figure 33 Output power curve of ICE5BR2280BZ

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Output current curve

7 Output current curve

The calculated output current curves showing typical output power against ambient temperature are shown
below. The curves are derived based on an open-frame design at Ta = 50°C, TJ = 125°C (integrated HV MOSFET
for CoolSET™), using the minimum 100 mm2 drain pin copper area in a 2 oz copper single-sided PCB and steady-
state operation only (no design margins for abnormal operation modes are included). The output power figure
is for selection purposes only. The actual power can vary depending on the specific design.

Figure 34 Output current curve of ICE5BRxxxxBZ

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Package information

8 Package information

Figure 35 PG-DIP-7

Green product (RoHS-compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations, the device is available as a green product. Green products are RoHS-compliant
(i.e., Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Further information on packages
https://www.infineon.com/packages

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Package information

8.1 Marking

Figure 36 Marking of PG-DIP-7

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Revision history

9 Revision history
Revision Date Changes
Rev 1.0 22 February 2022 Initial release
Rev 1.1 19 July 2022 Add new part number - ICE5AR3995BZ

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Trademarks
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IMPORTANT NOTICE
Edition 2022-07-19 The information given in this document shall in no For further information on the product, delivery
event be regarded as a guarantee of conditions or terms and conditions and prices please contact
Published by characteristics ("Beschaffenheitsgarantie"). your nearest Infineon Technologies office
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Infineon Technologies AG With respect to any examples, hints or any typical
81726 Munich, Germany values stated herein and/or any information
regarding the application of the product, Infineon WARNINGS
Technologies hereby disclaims any and all
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Email: [email protected] not be used in any applications where a failure of
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Document reference The data contained in this document is exclusively injury.
ICE5xRxxxxxZ intended for technically trained staff. It is the
responsibility of customer's technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.