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    18032

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    of 4

    Reg. No.

    Question Paper Code : 18032

    B.E. / B.TECH. DEGREE EXAMINATION, NOVEMBER / DECEMBER 2021


    Fifth Semester
    B.E. – Electronics and Communication Engineering
    19ECC01 – COMPUTER ARCHITECTURE AND ORGANIZATION
    (Regulations: Mepco – R2019)
    Duration: 3 Hours Max. : 100 Marks
    Answer ALL Questions
    PART A – (10  2 = 20 Marks)
    BTL, CO

    U, CO1 1. What is Turing Machine? Write a program for Subtraction using the machine
    (n1=5 and n2=3).
    U, CO1 2. Which of the following is/are true of the auto-increment addressing mode?
    Justify your answer.
    I. It is useful in creating self-relocating code.
    II. If it is included in an Instruction Set Architecture, then an additional ALU is
    required for effective address calculation.
    III. The amount of increment depends on the size of the data item accessed.
    A) I only B) II only C) III only D) II and III only
    R, CO2 3. Define Spatial and Temporal Expansion.
    A, CO2 4. What is the resultant Chopping and Rounding value for 3 digit resolution after
    the decimal of 0.10100111? Justify your answer.
    A) 0.101 & 0.110 B) 0.110 & 0.101
    C) 0.111 & 0.110 D) 0.101 & 0.101
    A, CO3 5. Find the GCD (100, 48).
    A, CO3 6. How many numbers of Flip-Flops are required for One-Hot and Classical
    Hardwired implementation of an algorithm which has 32 States? Justify your
    answer.
    A) 32 & 5 B) 32 & 4 C) 6 & 5 D) 32 & 6
    U, CO4 7. What is TLB? Draw its Architecture for a segmented virtual memory.
    U, CO4 8. In designing a computer’s cache system, the cache block (or cache line) size is an
    important parameter. Which one of the following statements is correct in this
    context? Justify your answer.
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    A) A smaller block size implies better spatial locality
    B) A smaller block size implies a smaller cache tag and hence lower cache tag
    overhead
    C) A smaller block size implies a larger cache tag and hence lower cache hit time
    D) A smaller block size incurs a lower cache miss penalty
    R, CO5 9. What is Semaphore? At what scenarios it is used?
    U, CO5 10. In the context of Memory layout of a Process match the following:
    I. Text section A. memory that is dynamically allocated
    II. Data section B. the executable code
    III. Heap section C. global variables

    A) I-A; II-B; III-C B) I-B; II-C; III-A


    C) I-C; II-B; III-A D) I-B; II-A; III-C
    Justify your answer.

    PART B – (5  16 = 80 Marks)
    U, CO1 11. a) i. Explain about Eight Addressing Modes used in a computer with
    suitable examples. (8 Marks)
    A, CO1 11. a) ii. Write a Machine Language for Z = (A*B) + (C/D) in Zero, One,
    Two and Three operand format. (8 Marks)
    OR
    U, CO1 11. b) i. Explain in detail about CPU Organization with suitable sketches. (8 Marks)
    A, CO1 11. b) ii. Derive the M/M/1 Queuing model of a computer with necessary
    specifications (lq, tq, tw etc...). (8 Marks)

    A, CO2 12. a) i. Find X+Y for


    X= 0 01111111 1000 0000 0000 0000 0000 000 (1.5)
    Y= 0 10000111 0010 1011 0100 0000 0000 000 (299.25)
    Using 32-bit Floating Point Arithmetic Unit with the detailed
    steps to be followed for the operation. Also, design Hardware for
    the same. (12 Marks)
    A, CO2 12. a) ii. Design a 4-bit Carry Look Ahead adder and derive 16-bit CLA
    using the same. (4 Marks)
    OR

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    A, CO2 12. b) i. Construct a hardware to find Z=X/Y for X=42 and Y=5. Find the
    remainder and quotient of the above with the help of Restoring
    Algorithm in unsigned binary format. Also, analyze the
    performance of the Algorithm(s). (8 Marks)
    A, CO2 12. b) ii. Find the product of (23) × (-6) using Booth Algorithm. Verify the
    result using Modified Booth encoding Technique. (8 Marks)

    A, CO3 13. a) Find the GCD (24, 18). Design a Hardwired Control unit for the
    GCD Processor using One-Hot Method with necessary flow
    diagram. Also, map the list and map the necessary control signals. (16 Marks)
    OR
    A, CO3 13. b) Design a Microprogrammed control unit for Multiplier with
    necessary control signals and also, explain about encoding
    methods followed in Control word format towards optimization. (16 Marks)

    A, CO4 14. a) Identify FIFO, LRU and OPT are Stack algorithm or not using the
    following Address Traces of Pages in a Cache Memory. Assume
    that the page capacity (n) is 3 and 4.Justify your answer with
    inclusion property.
    Time 1 2 3 4 5 6 7 8 9 10 11 12
    Address Trace 2 3 2 1 5 2 4 5 3 2 5 2 (16 Marks)
    OR
    A, CO4 14. b) i. Design Inter Integrated Circuit Bus (I2C Bus) with its interfacing
    methods in Device Level or Board Level. (8 Marks)
    U, CO4 14. b) ii. Explain in detail about the IEEE 7394 (Firewire), RS232C &
    RS485 with its pin details for external data communication
    interface. (8 Marks)

    U, CO5 15. a) i. What is System Calls? What are the types of System Calls?
    Explain about them in detail with necessary keywords. (12 Marks)
    U, CO5 15. a) ii. List and Explain the Scheduling Criteria for the CPU utilization. (4 Marks)
    OR
    U, CO5 15. b) i. What are the three Classic Problems of Synchronization? Explain
    them with the necessary algorithms. (12 Marks)
    U, CO5 15. b) ii. Explain about shared memory and message passing in the context
    of inter-process communication in operating systems. (4 Marks)

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