TR-20210526150845828

288pin DDR4 SDRAM Registered DIMM
DDR4 SDRAM Registered DIMM

Based on 16Gb A-die
HMAA8GR7AJR4N
HMAA4GR7AJR8N
HMAA4GR7AJR4N
*SK hynix reserves the right to change products or specifications without notice.
Rev. 1.4 / Aug.2019 1

Revision History
Revision No. History Draft Date Remark
0.1 Initial Release Nov.2018
1.0 Define IDD/IPP Specifiation Dec.2018
1.1 Change tRFC Feb.2019
1.2 Add HMAA4GR7AJR4N (1Rx4) Feb.2019
1.3 Update 2Rx4 IDD/IPP Specification May.2019

Define 2Rx8, 1Rx4 IDD/IPP Specification
Modify font size and format
1.4 Correct IDD/IPP Specification Aug.2019
Rev. 1.4 / Aug.2019 2

Description
SK hynix Registered DDR4 SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM Dual In-Line
Memory Modules) are low power, high-speed operation memory modules that use DDR4 SDRAM devices.
These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as
servers and workstations.
Features
• Power Supply: VDD=1.2V (1.14V to 1.26V)

• VDDQ = 1.2V (1.14V to 1.26V)
• VPP - 2.5V (2.375V to 2.75V)
• VDDSPD=2.25V to 2.75V
• Functionality and operations comply with the DDR4 SDRAM datasheet
• 16 internal banks
• Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or dif-
ferent bank group accesses are available
• Data transfer rates: PC4-3200, PC4-2933, 2666, PC4-2400, PC4-2133, PC4-1866, PC4-1600
• Bi-Directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
• Supports ECC error correction and detection
• On-Die Termination (ODT)
• Temperature sensor with integrated SPD
• This product is in compliance with the RoHS directive.
• Per DRAM Addressability is supported
• Internal Vref DQ level generation is available
• Write CRC is supported at all speed grades
• DBI (Data Bus Inversion) is supported(x8)
• CA parity (Command/Address Parity) mode is supported
Ordering Information
# of
Part Number Density Organization Component Composition
ranks
HMAA8GR7AJR4N - WM/XN/XN 64GB 8Gx72 4Gx4(H5ANAG4NAJR)*36 2
HMAA4GR7AJR8N - VK/WM/XN 32GB 4Gx72 2Gx8(H5ANAG8NAJR)*18 2
HMAA4GR7AJR4N - VK/WM/XN 32GB 4Gx72 4Gx4(H5ANAG4NAJR)*18 1
Rev. 1.4 / Aug.2019 3

Key Parameters
CAS
tCK tRCD tRP tRAS tRC
MT/s Grade Latency CL-tRCD-tRP
(ns) (ns) (ns) (ns) (ns)
(tCK)
13.75 13.75 48.75
DDR4-1600 -PB 1.25 11 35 11-11-11
(13.50)* (13.50)* (48.50)*
13.92 13.92 47.92
DDR4-1866 -RD 1.071 13 34 13-13-13
(13.50)* (13.50)* (47.50)*
14.06 14.06 47.06
DDR4-2133 -TF 0.937 15 33 15-15-15
(13.50)* (13.50)* (46.50)*
14.16 14.16 46.16
DDR4-2400 -UH 0.833 17 32 17-17-17
(13.75)* (13.75)* (45.75)*
14.25 14.25 46.25
DDR4-2666 -VK 0.75 19 32 19-19-19
(13.75)* (13.75)* (45.75)*
14.32 14.32 46.32
DDR4-2933 -WM 0.682 21 32 21-21-21
(13.75)* (13.75)* (45.75)*
DDR4-3200 -XN 0.625 22 13.75 13.75 32 47.0 22-22-22
*SK hynix DRAM devices support optional downbinning to CL21, CL19, CL17, CL17, CL15, CL13 and CL11. SPD setting
is programm
Address Table
64GB(2RX4) 32GB(2RX8) 32GB(1RX4)
# of Bank Groups 4 4 4
Bank Address BG Address BG0~BG1 BG0~BG1 BG0~BG1
Bank Address in a BG BA0~BA1 BA0~BA1 BA0~BA1
Row Address A0~A17 A0~A16 A0~A17
Column Address A0~ A9 A0~ A9 A0~ A9
Page size 512B 1KB 512B
Rev. 1.4 / Aug.2019 4

Pin Descriptions
Pin Name Description Pin Name Description
I2C serial bus clock for SPD-TSE and

A0-A171 Register address input SCL
register
I2C serial data line for SPD-TSE and

BA0, BA1 Regisiter bank select input SDA
register
I2C slave address select for SPD-TSE

BG0, BG1 Regisiter bank group select input SA0-SA2
and register
RAS_n2 Register row address strobe input PAR Register parity input
CAS_n3 Register column address strobe input VDD SDRAM core power supply
WE_n4 Register write enable input C0, C1, C2 Chip ID lines for SDRAMx
CS0_n, CS1_n, Optional Power Supply on socket but
DIMM Rank Select Lines input 12V
CS2_n, CS3_n not used on RDIMM
SDRAM command/address reference
CKE0, CEK1 Register clock enable lines input VREFCA
supply
Register on-die termination control
ODT0, ODT1 VSS Power supply return (ground)
lines input
ACT_n Register input for activate input VDDSPD Serial SPD/TS positive power supply
DQ0-DQ63 DIMM memory data bus ALERT_n Register ALERT_n output
CB0-CB7 DIMM ECC check bits VPP SDRAM Supply
TDQS9_t-TDQS17_t Dummy loads for mixed populations of
TDQS9_c-TDQS17_c x4 based and x8 based RDIMMs.
Data Buffer data strobes
DQS0_t-DQS17_t DM0_n-DM8_n Data Mask
(positive line of differential pair)
Data Buffer data strobes Set Register and SDRAMs to a Known
DQS0_c-DQS17_c RESET_n
(negative line of differential pair) State
SPD signals a thermal event has
DBI0_n-DBI8_n Data Bus Inversion EVENT_n
occurred
Register clock input (positive line of dif-
CK0_t, CK1_t VTT SDRAM I/O termination supply
ferential pair)
Register clocks input (negative line of
CK0_c, CK1_c RFU Reserved for future use
differential pair)
1. Address A17 is only valid for 16Gbx4 based SDRAMs.

2. RAS_n is a multiplexed function with A16.
3. CAS_n is a multiplexed function with A15.
4. WE_n is a multiplexed function with A14.
Rev. 1.4 / Aug.2019 5

Input/Output Functional Descriptions
Symbol Type Function
CK0_t, CK0_c, Clock: CK_t and CK_c are differential clock inputs. All address and control input signals
Input
CK1_t, CK1_c are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals and
device input buffers and output drivers. Taking CKE LOW provides Precharge Power-
Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in
any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref
CKE0, CKE1 Input have become stable during the power on and initialization sequence, they must be
maintained during all operations (including Self-Refresh). CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK_t, CK_c, ODT and CKE,
are disabled during power-down. Input buffers, excluding CKE, are disabled during Self-
Refresh.
CS0_n, CS1_n, Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for
Input
CS2_n, CS3_n external Rank selection. CS_n is considered part of the command code.
Chip ID: Chip ID is only used for 3DS for 2,4,8 high stack via TSV to select each slice of
C0, C1, C2 Input
stacked component. Chip ID is considered part of the command code.
On-Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance
internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t,
ODT0, ODT1 Input
DQS_c, TDQS_t, and TDQS_c signal. The ODT pin will be ignored if MR1 is programmed
to disable RTT_NOM.
Activation Command Input: ACT_n defines the Activation command being entered along
ACT_n Input with CS_n. The input into RAS_n/A16, CAS_n/A15, and WE_n/A14 will be considered as
Row Address A16, A15, and A14.
Command Inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n) define the
RAS_n/A16, command being entered. Those pins are multi-function. For example, for activation with
CAS_n/A15, Input ACT_n Low, these are Addresses like A16, A15, and A14, but for non-activation
WE_n/A14 command with ACT_n High, these are Command pins for Read, Write, and other
commands defined in command truth table.
Bank Group Inputs: BG0 - BG1 define to which bank group an Active, Read, Write, or
BG0 - BG1 Input Precharge command is being applied. BG0 also determines which mode register is to be
accessed during a MRS cycle.
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write, or
BA0 - BA1 Input Precharge command is being applied. Bank address also determines which mode
register is to be accessed during a MRS cycle.
Address Inputs: Provide the row address for ACTIVATE Commands and the column
address for Read/Write commands to select one location out of the memory array in the
A0 - A17 Input respective bank. A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have
additional functions. See other rows. The address inputs also provide the op-code during
Mode Register Set commands. A17 is only defined for 16Gb x4 SDRAM configurations.
Rev. 1.4 / Aug.2019 6

Auto-precharge: A10 is sampled during Read/Write commands to determine whether

Autoprecharge should be performed to the accessed bank after the Read/Write
operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a
A10 / AP Input
Precharge command to determine whether the Precharge applies to one bank (A10
LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected
by bank addresses.
Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if
A12 / BC_n Input burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped).
See command truth table for details.
CMOS Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive
RESET_n
Input when RESET_n is HIGH. RESET_n must be HIGH during normal operation.
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register, then
Input / CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the
DQ
Output internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor
specific data sheets to determine which DQ is used.
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
DQS0_t-DQS17_t, Input / centered in write data. The data strobe DQS_t is paired with differential signals DQS_c,
DQS0_c-DQS17_c Output respectively, to provide differential pair signaling to the system during reads and writes.
DDR4 SDRAM supports differential data strobe only and does not support single-ended.
TDQS9_t-TDQS17_t, Provides a dummy load for x8 based RDIMMs where mixed populations of x4 and x8
Input
TDQS9_c-TDQS17_c based RDIMMs are present.
Input/ Provides for data bus inversion. Only possible for x8 based RDIMMs and where only x8
DBI0_n-DBI8_n
Output based RDIMMs are on a channel.
Provides for masking of a byte on WRITE commands to the SDRAMs. Only Possible x8
DM0_n-DM8_n Input
based RDIMMs and where only x8 based RDIMMs are on a channel.
Command and Address Parity Input : DDR4 Supports Even Parity check in SDRAMs with
MR setting. Once it’s enabled via Register in MR5, then SDRAM calculates Parity with
PAR Input ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A17-A0. Input parity
should be maintained at the rising edge of the clock and at the same time as command
& address, with CS_n LOW.
Alert: Is multi functions, such as CRC error flag or Command and Address Parity error
flag, as on Output signal. If there is an error in the CRC, then ALERT_n goes LOW for the
period time interval and goes back HIGH. If there is an error in the Command Address
Output
ALERT_n Parity Check, then ALERT_n goes LOW for a relatively long period until on going SDRAM
(Input)
internal recovery transaction is complete. During Connectivity Test mode, this pin
functions as an input.
Using this signal or not is dependent on the system.
RFU Reserved for Future Use: No on-DIMM electrical connection is present.
NC No Connect: No on-DIMM electrical connection is present.
VDD1 Supply Power Supply: 1.2 V ± 0.06 V
VSS Supply Ground
Rev. 1.4 / Aug.2019 7

VTT Supply Power Supply for termination of Address, Command and Control, VDD/2.
12V Supply 12V supply not used on RDIMMs.
VPP Supply SDRAM Activating Power Supply: 2.5V (2.375V min , 2.75V max)
VDDSPD Supply Power supply used to power the I2C bus on the SPD-TSE and register.
VREFCA Supply Reference voltage for CA
Note: For PC4, VDD is 1.2V.
Rev. 1.4 / Aug.2019 8

Pin Assignments
Front Side Back Side Front Side Back Side
Pin Pin Pin Pin
Pin Label Pin Label Pin Label Pin Label
1 NC 145 NC 74 CK0_t 218 CK1_t
2 VSS 146 VREFCA 75 CK0_c 219 CK1_c
3 DQ4 147 VSS 76 VDD 220 VDD
4 VSS 148 DQ5 77 VTT 221 VTT
5 DQ0 149 VSS
KEY
6 VSS 150 DQ1
TDQS9_t, DQS9_t,
7 151 VSS 78 EVENT_n 222 PARITY
DM0_n, DBI0_n
8 TDQS9_C, DQS9_C 152 DQS0_c 79 A0 223 VDD
9 VSS 153 DQS0_t 80 VDD 224 BA1
10 DQ6 154 VSS 81 BA0 225 A10/AP
11 VSS 155 DQ7 82 RAS_n/A16 226 VDD
12 DQ2 156 VSS 83 VDD 227 RFU
13 VSS 157 DQ3 84 CS0_n 228 WE_n/A14
14 DQ12 158 VSS 85 VDD 229 VDD
15 VSS 159 DQ13 86 CAS_n/A15 230 NC
16 DQ8 160 VSS 87 ODT0 231 VDD
17 VSS 161 DQ9 88 VDD 232 A13
TDQS10_t, DQS10_t,
18 162 VSS 89 CS1_n, NC 233 VDD
DM1_n, DBI1_n
19 TDQS10_c, DQS10_c 163 DQS1_c 90 VDD 234 A17
20 VSS 164 DQS1_t 91 ODT1, NC 235 NC, C2
21 DQ14 165 VSS 92 VDD 236 VDD
22 VSS 166 DQ15 93 C0, CS2_n, NC 237 NC, CS3_n, C1
23 DQ10 167 VSS 94 VSS 238 SA2
24 VSS 168 DQ11 95 DQ36 239 VSS
25 DQ20 169 VSS 96 VSS 240 DQ37
26 VSS 170 DQ21 97 DQ32 241 VSS
27 DQ16 171 VSS 98 VSS 242 DQ33
TDQS13_t, DQS13_t,
28 VSS 172 DQ17 99 243 VSS
DM4_n, DBI4_n
TDQS11_t, DQS11_t,
29 173 VSS 100 TDQS13_C, DQS13_C 244 DQS4_c
DM2_n, DBI2_n
30 TDQS11_c, DQS11_c 174 DQS2_c 101 VSS 245 DQS4_t
31 VSS 175 DQS2_t 102 DQ38 246 VSS
32 DQ22 176 VSS 103 VSS 247 DQ39
33 VSS 177 DQ23 104 DQ34 248 VSS
34 DQ18 178 VSS 105 VSS 249 DQ35
35 VSS 179 DQ19 106 DQ44 250 VSS
36 DQ28 180 VSS 107 VSS 251 DQ45
Rev. 1.4 / Aug.2019 9

Front Side Back Side Front Side Back Side
Pin Pin Pin Pin
Pin Label Pin Label Pin Label Pin Label
37 VSS 181 DQ29 108 DQ40 252 VSS
38 DQ24 182 VSS 109 VSS 253 DQ41
TDQS14_t, DQS14_t,
39 VSS 183 DQ25 110 254 VSS
DM5_n, DBI5_n
TDQS12_t, DQS12_t,
40 184 VSS 111 TDQS14_c, DQS14_c 255 DQS5_C
DM3_n, DBI3_n
41 TDQS12_C, DQS12_C 185 DQS3_c 112 VSS 256 DQS5_t
42 VSS 186 DQS3_t 113 DQ46 257 VSS
43 DQ30 187 VSS 114 VSS 258 DQ47
44 VSS 188 DQ31 115 DQ42 259 VSS
45 DQ26 189 VSS 116 VSS 260 DQ43
46 VSS 190 DQ27 117 DQ52 261 VSS
47 CB4 191 VSS 118 VSS 262 DQ53
48 VSS 192 CB5 119 DQ48 263 VSS
49 CB0 193 VSS 120 VSS 264 DQ49
TDQS15_t, DQS15_t,
50 VSS 194 CB1 121 265 VSS
DM6_n, DBI6_n
TDQS17_t, DQS17_t,
51 195 VSS 122 TDQS15_c, DQS15_c 266 DQS6_c
DM8_n, DBI8_n
52 TDQS17_c, DQS17_c 196 DQS8_c 123 VSS 267 DQS6_t
53 VSS 197 DQS8_t 124 DQ54 268 VSS
54 CB6 198 VSS 125 VSS 269 DQ55
55 VSS 199 CB7 126 DQ50 270 VSS
56 CB2 200 VSS 127 VSS 271 DQ51
57 VSS 201 CB3 128 DQ60 272 VSS
58 RESET_n 202 VSS 129 VSS 273 DQ61
59 VDD 203 CKE1, NC 130 DQ56 274 VSS
60 CKE0 204 VDD 131 VSS 275 DQ57
TDQS16_t, DQS16_t,
61 VDD 205 RFU 132 276 VSS
DM7_n, DBI7_n
62 ACT_n 206 VDD 133 TDQS16_t, DQS16_c 277 DQS7_c
63 BG0 207 BG1 134 VSS 278 DQS7_t
64 VDD 208 ALERT_n 135 DQ62 279 VSS
65 A12/BC_n 209 VDD 136 VSS 280 DQ63
66 A9 210 A11 137 DQ58 281 VSS
67 VDD 211 A7 138 VSS 282 DQ59
68 A8 212 VDD 139 SA0 283 VSS
69 A6 213 A5 140 SA1 284 VDDSPD
70 VDD 214 A4 141 SCL 285 SDA
71 A3 215 VDD 142 VPP 286 VPP
72 A1 216 A2 143 VPP 287 VPP
73 VDD 217 VDD 144 RFU 288 VPP
Rev. 1.4 / Aug.2019 10

Functional Block Diagram
64GB, 8Gx72 Module(2Rank of x4) - page1
BG[1:0] QABG[1:0] -> BG[1:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
QBBG[1:0] -> BG[1:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
BA[1:0] QABA[1:0] -> BA[1:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
QBBA[1:0] -> BA[1:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
A[17:0] R QAA[17:0] -> A[17:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
E QBA[17:0] -> A[17:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
ACT_n G QAACT_n -> ACT_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
I QBACT_n -> ACT_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
C[2:0] S QAC[2:0] -> C[2:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
T QBC[2:0] -> C[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
PARITY E QAPAR -> PAR: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
R QBPAR -> PAR: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
CKE0 QACKE0 -> CKE: SDRAMs D[3:0], D[12:8], D17
QBCKE0 -> CKE: SDRAMs D[7:4], D[16:13]
CKE1 QACKE1 -> CKE: SDRAMs D[21:18], D[30:26], D35
QBCKE1 -> CKE: SDRAMs D[25:22], D[34:31]
ODT0 QAODT0 -> ODT: SDRAMs D[3:0], D[12:8], D17
QBODT0 -> ODT: SDRAMs D[7:4], D[16:13]
ODT1 QAODT1 -> ODT: SDRAMs D[21:18], D[30:26], D35
QBODT1 -> ODT: SDRAMs D[25:22], D[34:31]
CS0_n QACS0_n -> CS_n: SDRAMs D[3:0], D[12:8], D17
QBCS0_n -> CS_n: SDRAMs D[7:4], D[16:13]
CS1_n QACS1_n -> CS_n: SDRAMs D[21:18], D[30:26], D35
QBCS1_n -> CS_n: SDRAMs D[25:22], D[34:31]
CK0_t Y0_t -> CK_t: SDRAMs D[7:4], D[25:22]
Y1_t -> CK_t: SDRAMs D[3:0], D8, D[21:18], D26
Y2_t -> CK_t: SDRAMs D[16:13], D[34:31]
Y3_t -> CK_t: SDRAMs D[12:9], D17, D[30:27], D35
CK0_c Y0_c -> CK_c: SDRAMs D[7:4], D[25:22]
Y1_c -> CK_c: SDRAMs D[3:0], D8, D[21:18], D26
CK1_t Y2_c -> CK_c: SDRAMs D[16:13], D[34:31]
Y3_c -> CK_c: SDRAMs D[12:9], D17, D[30:27], D35
CK1_c
RESET_n QRST_n -> RESET_n: All SDRAMs

ALERT_n ERROR_IN_n <- ALERT_n: All SDRAMs
D0 D1 D2 D3 D8 D4 D5 D6 D7
Front
D9 D11 D12 D17 D13 D14 D15 D16
D10
D28 D30 D32 D34

D27 D29 D35 D31 D33
Back D19 D23 D25

D18 D20 D21 D26 D22 D24
Note: Address, Command and Control lines

1. CK0_t, CK0_c terminated with 120 Ω ±5% resistor.
2. CK1_t, CK1_c terminated with 120 Ω ±5% resistor but not used.
3. Unless otherwise noted resistors are 22 Ω ±5%.
Rev. 1.4 / Aug.2019 11

QACS0_n
QAODT0
QACKE0
QACS1_n
QAODT1
QACKE1
CS_n
CS_n
CS_n
CS_n
ZQ VSS ZQ VSS ZQ VSS ZQ VSS
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
DQS0_t DQS_t DQS_t DQS9_t DQS_t DQS_t
DQS0_c DQS_c DQS_c DQS9_c DQS_c DQS_c
DQ [3:0] DQ [3:0] D9 DQ [3:0] D27 DQ [7:4] DQ [3:0] D0 DQ [3:0] D18
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE

CB [3:0] DQ [3:0] D17 DQ [3:0] D35 CB [7:4] DQ [3:0] D8 DQ [3:0] D26
Note:
1. Unless otherwize noted, resistor values are 15 Ω ±5%.
2. See the Net Structure diagrams for all resistor associated with the command, address and control bus.
3. ZQ resistors are 240 Ω ±1%.For all other resistor values refer to the appropriate wiring diagram.
4. DRAM TEN pin need to be tied to VSS.
5. VDDSPD also connects to the register (RCD).
6. VREFCA from the edge connector only connects with the register (RCD). The RCD sources a separate VREFCA to all the SDRAMs.
Rev. 1.4 / Aug.2019 12

QBCS0_n
QBODT0
QBCKE0
QBCS1_n
QBODT1
QBCKE1
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
VDDSPD SPD SDA SDA SDA RCD

VPP D0–D35 SCL SCL SCL
VDD D0–D35 EVENT_n EVENT_n VSS BFUNC
VTT SA0 SA1 SA2 SA0 SA1 SA2
VREFCA D0–D35 SA0
SA0 SA1 SA2 SA1 SA2
VSS D0–D35 Serial PD with Thermal sensor 1KΩ
±5%
Note:
4. DRAM TEN pin need to be tied to VSS.
5. VDDSPD also connects to the register (RCD).
6. VREFCA from the edge connector only connects with the register (RCD). The RCD sources a separate VREFCA to all the SDRAMs.
Rev. 1.4 / Aug.2019 13

BG[1:0] BG[1:0]A -> BG[1:0]: SDRAMs D[4:0], D[13:9]

BG[1:0]B -> BG[1:0]: SDRAMs D[8:5], D[17:14]
BA[1:0] BA[1:0]A -> BA[1:0]: SDRAMs D[4:0], D[13:9]
BA[1:0]A -> BA[1:0]: SDRAMs D[8:5], D[17:14]
A[16:0] R A[17:0]A -> A[16:0]: SDRAMs D[4:0], D[17:13]
E A[17:0]B -> A[16:0]: SDRAMs D[8:5], D[12:9]
ACT_n G ACTA_n -> ACT_n: SDRAMs D[4:0], D[13:9]
I ACTB_n -> ACT_n: SDRAMs D[8:5], D[17:14]
PARITY S PARA -> PAR: SDRAMs D[4:0], D[13:9]
T PARB -> PAR: SDRAMs D[8:5], D[17:14]
CKE0 E CKE0A -> CKE: SDRAMs D[4:0]
CKE0B -> CKE: SDRAMs D[8:5]
CKE1
R CKE1A -> CKE: SDRAMs D[13:9]
CKE1B -> CKE: SDRAMs D[17:14]
ODT0 ODT0A -> ODT: SDRAMs D[4:0]
ODT0B -> ODT: SDRAMs D[8:5]
ODT1 ODT1A -> ODT: SDRAMs D[13:9]
ODT1B -> ODT: SDRAMs D[17:14]
CS0_n CS0A_n -> CS_n: SDRAMs D[4:0]
CS0B_n -> CS_n: SDRAMs D[8:5]
CS1_n CS1A_n -> CS_n: SDRAMs D[13:9]
CS1B_n -> CS_n: SDRAMs D[17:14]
CK0_t Y0_t -> CK_t: SDRAMs D[8:5]
Y1_t -> CK_t: SDRAMs D[4:0]
Y2_t -> CK_C: SDRAMs D[17:14]
Y3_t -> CK_C: SDRAMs D[13:9]
CK0_c Y0_c -> CK_t: SDRAMs D[8:5]
CK1_t Y1_c-> CK_t: SDRAMs D[4:0]
Y2_c -> CK_C: SDRAMs D[17:14]
CK1_c Y3_c -> CK_C: SDRAMs D[13:9]

Front RC
D
D0 D1 D2 D3 D4 D5 D6 D7 D8
01 01 01 01 010
D9 D10 D11 D12 D13 D14 D15 D16 D17
Back
Note:
Rev. 1.4 / Aug.2019 14

CKE0A CKE0B
ODT0A ODT0B
CS0A_n CS0B_n
CKE1A CKE1B
ODT1A ODT1B
CS1A_n CS1B_n
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
CB [7:0] DQ [7:0] D4 DQ [7:0] D13 DQ [39:32] DQ [7:0] D5 DQ [7:0] D14
DBI8_n/DM8_n DBI_n/DM_n DBI_n/DM_n DBI4_n/DM4_n DBI_n/DM_n DBI_n/DM_n
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
DQS‘_t DQS_t DQS_t DQS7_t DQS_t DQS_t
DQS‘_c DQS_c DQS_c DQS7_c DQS_c DQS_c
CS_n
CS_n
ODT
ODT
ZQ VSS ZQ VSS
CKE
CKE
DQS0_t DQS_t DQS_t

DQS0_c DQS_c DQS_c
DQ [7:0] DQ [7:0] D0 DQ [7:0] D9
DBI0_n/DM0_n DBI_n/DM_n DBI_n/DM_n
VDDSPD RCD, Serial PD SDA SDA SDA RCD

VDD D0–D17 EVENT_n EVENT_n VSS BFUNC
VREFCA D0–D17 SA0
SA0 SA1 SA2 SA1 SA2
VSS D0–D17, RCD, Serial PD Serial PD with Thermal sensor 1KΩ
±5%
Note:
4. The TEN pin on the SDRAMs are tied to Vss.
5. VDD and VDDSPD also connect to the RCD
Rev. 1.4 / Aug.2019 15

BG[1:0] BG[1:0]A -> BG[1:0]: SDRAMs D[4:0], D[17:13]

BG[1:0]B -> BG[1:0]: SDRAMs D[8:5], D[12:9]
BA[1:0] BA[1:0]A -> BA[1:0]: SDRAMs D[4:0], D[17:13]
BA[1:0]A -> BA[1:0]: SDRAMs D[8:5], D[12:9]
A[17:0] R A[17:0]A -> A[17:0]: SDRAMs D[4:0], D[17:13]
E A[17:0]B -> A[17:0]: SDRAMs D[8:5], D[12:9]
ACT_n G ACTA_n -> ACT_n: SDRAMs D[4:0], D[17:13]
I ACTB_n -> ACT_n: SDRAMs D[8:5], D[12:9]
C[2:0] S C[2:0]A -> C[2:0]: SDRAMs D[4:0], D[17:13]
T C[2:0]B -> C[2:0]: SDRAMs D[8:5], D[12:9]
PARITY E PARA -> PAR: SDRAMs D[4:0], D[17:13]
PARB -> PAR: SDRAMs D[8:5], D[12:9]
R
CKE0 CKE0A -> CKE: SDRAMs D[4:0], D[17:13]
CKE0B -> CKE: SDRAMs D[8:5], D[12:9]
ODT0 ODT0A -> ODT: SDRAMs D[4:0], D[17:13]
ODT0B -> ODT: SDRAMs D[8:5], D[12:9]
CS0_n CS0A_n -> CS_n: SDRAMs D[4:0], D[17:13]
CS0B_n -> CS_n: SDRAMs D[8:5], D[12:9]
CK0_t Y0_t -> CK_t: SDRAMs D[8:5], D[12:9]

Y1_t -> CK_t: SDRAMs D[4:0], D[17:13]
CK0_c Y0_C -> CK_C: SDRAMs D[8:5], D[12:9]

Y1_C -> CK_C: SDRAMs D[4:0], D[17:13]
CK1_t
CK1_c

Note:
4. Register input CS1_n is tied to VDD. Register inputs ODT1 and CKE1 are tied to VSS.
Rev. 1.4 / Aug.2019 16

CS0A_n CS0B_n
ODT0A ODT0B
CKE0A CS_n CKE0B
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
DQS9_t DQS_t DQS0_t DQS_t DQS4_t DQS_t DQS13_t DQS_t
DQS9_c DQS_c DQS0_c DQS_c DQS4_c DQS_c DQS13_c DQS_c
DQ [9:4] DQ [3:0] D0 DQ [3:0] DQ [3:0] D17 DQ [35:32] DQ [3:0] D5 DQ [39:36] DQ [3:0] D9
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
CS_n
CS_n
CS_n
CS_n
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
CS_n
CS_n
ODT
ODT
ZQ VSS ZQ VSS
CKE
CKE
DQS17_t DQS_t DQS8_t DQS_t

DQS17_c DQS_c DQS8_c DQS_c
CB [7:4] DQ [3:0] D4 CB [3:0] DQ [3:0] D13
VDDSPD SPD
SDA SDA SDA RCD
VDD D0–D17
EVENT_n EVENT_n VSS BFUNC
VREFCA D0–D17
SA0 SA1 SA2 SA0 SA1 SA2
VSS D0–D17 1KΩ
Serial PD with Thermal sensor
±5%
Note:
4. VDD and VDDSPD also connect to the register. TEN pin of SDRAMs is tied to VSS.
Rev. 1.4 / Aug.2019 17

Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol Parameter Rating Units NOTE
VDD Voltage on VDD pin relative to Vss -0.3 ~ 1.5 V 1,3
VDDQ Voltage on VDDQ pin relative to Vss -0.3 ~ 1.5 V 1,3
VPP Voltage on VPP pin relative to Vss -0.3 ~ 3.0 V 4
VIN, VOUT Voltage on any pin except VREFCA relative to Vss -0.3 ~ 1.5 V 1,3,5
TSTG Storage Temperature -55 to +100 °C 1,2
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indi-
cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x
VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV
4. VPP must be equal or greater than VDD/VDDQ at all times
5. Overshoot area above 1.5V is specified in DDR4 Device Operation.
DRAM Component Operating Temperature Range

Temperature Range
Symbol Parameter Rating Units Notes

0 to 85 oC 1,2
Normal Operating Temperature Range
TOPER oC
Extended Temperature Range 85 to 95 1,3
NOTE:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measure-
ment conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported.
During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating condi-
tions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is
also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use
the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b)
or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).
Rev. 1.4 / Aug.2019 18

AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions
Rating
Symbol Parameter Unit NOTE
Min. Typ. Max.
VDD Supply Voltage 1.14 1.2 1.26 V 1,2,3
VDDQ Supply Voltage for Output 1.14 1.2 1.26 V 1,2,3
VPP Supply Voltage for DRAM Activating 2.375 2.5 2.75 V 3
NOTE:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. DC bandwidth is limited to 20MHz.
Rev. 1.4 / Aug.2019 19

AC & DC Input Measurement Levels
AC & DC Logic input levels for single-ended signals
Single-ended AC & DC input levels for Command and Address
DDR4-1600/1866/2133/
DDR4-2666/2933/3200
Symbol Parameter 2400 Unit NOTE
Min. Max. Min. Max.
DC input logic VREFCA+ VREFCA+
VIH.CA(DC75) VDD VDD V
high 0.075 0.065
VREFCA- VREFCA-
VIL.CA(DC75) DC input logic low VSS VSS V
0.075 0.065
AC input logic
VIH.CA(AC100) VREF + 0.1 Note 2 VREF + 0.09 Note 2 V 1
high
VIL.CA(AC100) AC input logic low Note 2 VREF - 0.1 Note 2 VREF - 0.09 V 1
Reference Volt-
VREFCA(DC) age for ADD, CMD 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V 2,3
inputs
NOTE :
1. See “Overshoot and Undershoot Specifications”
2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1%
VDD (for reference : approx. ± 12mV)
3. For reference : approx. VDD/2 ± 12mV
Rev. 1.4 / Aug.2019 20

AC and DC Input Measurement Levels: VREF Tolerances
The DC-tolerance limits and ac-noise limits for the reference voltages VREFCA is illustrated in Figure below.
It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to
meet the min/max requirement in Table X. Furthermore VREF(t) may temporarily deviate from VREF(DC) by
no more than ± 1% VDD.
voltage
VDD
VSS
time
Illustration of VREF(DC) tolerance and VREF AC-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are
dependent on VREF.
"VREF" shall be understood as VREF(DC), as defined in Figure above.
This clarifies, that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the
input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and
voltage associated with VREF AC-noise. Timing and voltage effects due to AC-noise on VREF up to the spec-
ified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
Rev. 1.4 / Aug.2019 21

AC and DC Logic Input Levels for Differential Signals
Differential signal definition
tDVAC
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
(CK_t - CK_c)
Differential Input Voltage (CK-CK)
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
NOTE:
1. Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.
2. Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.
Definition of differential ac-swing and “time above ac-level” tDVAC
Rev. 1.4 / Aug.2019 22

Differential swing requirements for clock (CK_t - CK_c)
Differential AC and DC Input Levels
DDR4 -
1600,1866,21 DDR4 -2400 DDR4 -2666 DDR4 -2933 DDR4 -3200 un NO
Symbol Parameter 33 it TE
min max min max min max min max min max
differential
VIHdiff +0.150 NOTE 3 +0.135 NOTE 3 +0.135 NOTE 3 +0.125 NOTE 3 +0.110 NOTE 3 V 1
input high
differential
VILdiff NOTE 3 -0.150 NOTE 3 -0.135 NOTE 3 -0.135 NOTE 3 -0.125 NOTE 3 -0.110 V 1
input low
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD and VREFCA;
3. These values are not defined; however, the differential signals CK_t - CK_c, need to be within the
respective limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for
overshoot and undershoot.
Allowed time before ringback (tDVAC) for CK_t - CK_c

tDVAC [ps] @ |VIH/Ldiff(AC)| = 200mV tDVAC [ps] @ |VIH/Ldiff(AC)| = TBDmV
Slew Rate [V/ns]
min max min max
> 4.0 120 - TBD -
4.0 115 - TBD -
3.0 110 - TBD -
2.0 105 - TBD -
1.8 100 - TBD -
1.6 95 - TBD -
1.4 90 - TBD -
1.2 85 - TBD -
1.0 80 - TBD -
< 1.0 80 - TBD -
Rev. 1.4 / Aug.2019 23

Single-ended requirements for differential signals
Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain require-
ments for single-ended signals.
CK_t and CK_c have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels
(VIH.CA(AC) / VIL.CA(AC) ) for ADD/CMD signals) in every half-cycle.
Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g., if Different
value than VIH.CA(AC100)/VIL.CA(AC100) is used for ADD/CMD signals, then these ac-levels apply also for
the single-ended signals CK_t and CK_c
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
CK
VSEL max
VSEL
VSS or VSSQ
time
Single-ended requirement for differential signals
Note that, while ADD/CMD signal requirements are with respect to VrefCA, the single-ended components
of differential signals have a requirement with respect to VDD / 2; this is nominally the same. The transi-
tion of single-ended signals through the ac-levels is used to measure setup time. For single-ended compo-
nents of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but
adds a restriction on the common mode characteristics of these signals.
Rev. 1.4 / Aug.2019 24

Single-ended levels for CK_t, CK_c
DDR4-1600/ U
Sym DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 NO
Parameter 1866/2133 ni
bol TE
Min Max Min Max Min Max Min Max Min Max t
Single-ended (VDD/ (VDD/ (VDD/ (VDD/ (VDD/
VSEH high-level for 2) NOTE3 2) NOTE3 2) NOTE3 2) NOTE3 2) NOTE3 V 1, 2
CK_t , CK_c +0.100 +0.095 +0.095 +0.085 +0.085
Single-ended (VDD/ (VDD/ (VDD/ (VDD/ (VDD/
VSEL low-level for NOTE3 2)- NOTE3 2)- NOTE3 2)- NOTE3 2)- NOTE3 2)- V 1, 2
CK_t , CK_c 0.100 0.095 0.095 0.085 0.085
NOTE :
1. For CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD;
2. VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA;
3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the
respective limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for
overshoot and undershoot.
Rev. 1.4 / Aug.2019 25

Address and Control Overshoot and Undershoot specifications
AC overshoot/undershoot specification for Address, Command and Control pins
Specification
Uni
Parameter DDR4- DDR4- DDR4- DDR4- DDR4- DDR4- DDR4- t
1600 1866 2133 2400 2666 2933 3200
Maximum peak amplitude above VDD Abso-
0.06 0.06 V
lute Max allowed for overshoot area
Delta value between VDD Absolute Max and
VDD + 0.24 VDD + 0.24 V
VDD Max allowed for overshoot area
Maximum peak amplitude allowed for under- V-
0.30 0.30
shoot area ns
Maximum overshoot area per 1tCK Above V-
0.0083 0.0071 0.0062 0.0055 0.0055
Absolute Max ns
Maximum overshoot area per 1tCK Between V-
0.2550 0.2185 0.1914 0.1699 0.1699
Absolute Max ns
Maximum undershoot area per 1tCK Below V-
0.2644 0.2265 0.1984 0.1762 0.1762
VSS ns
(A0-A13,A17,BG0-BG1,BA0-BA1,ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A14,CS_n,CKE,ODT,C2-C0)
Overshoot Area above VDD Absolute Max

VDD Absolute Max Overshoot Area Between
VDD Absolute Max and VDD Max
VDD
Volts 1 tCK
(V)
VSS
Undershoot Area below VSS

Address,Command and Control Overshoot and Undershoot Definition
Rev. 1.4 / Aug.2019 26

Clock Overshoot and Undershoot Specifications
AC overshoot/undershoot specification for Clock
Specification
Uni
1600 1866 2133 2400 2666 2933 3200
Maximum peak amplitude above VDD Abso-
0.06 0.06 V
lute Max allowed for overshoot area
Delta value between VDD Absolute Max and
VDD + 0.24 VDD + 0.24 V
VDD Max allowed for overshoot area
Maximum peak amplitude allowed for under-
0.30 0.30 V
shoot area
Maximum overshoot area per 1UI Above V-
0.0038 0.0032 0.0028 0.0025 0.0025
Absolute Max ns
Maximum overshoot area per 1UI Between V-
0.1125 0.0964 0.0844 0.0750 0.0750
Absolute Max ns
Maximum undershoot area per 1UI Below V-
0.1144 0.0980 0.0858 0.0762 0.0762
VSS ns
(CK_t, Ck_c)
Overshoot Area above VDD Absolute Max

VDD Absolute Max Overshoot Area Between
VDD Absolute Max and VDD Max
VDD
Volts 1 UI
(V)
VSS
Undershoot Area below VSS

Clock Overshoot and Undershoot Definition
Rev. 1.4 / Aug.2019 27

Data, Strobe and Mask Overshoot and Undershoot Specifications
AC overshoot/undershoot specification for Data, Strobe and Mask
Specification
Uni
1600 1866 2133 2400 2666 2933 3200
Maximum peak amplitude above Max abso-
0.16 0.16 0.16 0.16 0.16 V
lute level of Vin,Vout
Overshoot area Between Max Absolute level
VDDQ + 0.24 VDDQ+0.24 V
of Vin, Vout and VDDQ Max
Undershoot area Between Min absolute level
0.30 0.30 0.30 0.30 0.30 V
of Vin,Vout and VDDQ Max
Maximum peak amplitude below Min absolute
0.10 0.10 0.10 0.10 0.10 V
level of Vin,Vout
Maximum overshoot area per 1UI Above Max V-
0.0150 0.0129 0.0113 0.0100 0.0100
absolute level of Vin,Vout ns
Maximum overshoot area per 1UI Between
V-
Max absolute level of Vin,Vout and VDDQ 0.1050 0.0900 0.0788 0.0700 0.0700
ns
Max
Maximum undershoot area per 1UI Between V-
0.1050 0.0900 0.0788 0.0700 0.0700
Min absolute level of Vin,Vout and VSSQ ns
Maximum undershoot area per 1UI Below Min V-
0.0150 0.0129 0.0113 0.0100 0.0100
absolute level of Vin,Vout ns
(DQ, DQS_t, DQS_c, DM_n, DBI_n, TDQS_t, TDQS_c)
Overshoot Area above Max absolute level of Vin,Vout
Max absolute level of Vin,Vout Overshoot Area Between

Max absolute level of Vin,Vout and VDDQ
VDDQ
Volts 1 UI
(V)
VSSQ
Undershoot Area Between

Min absolute level of Vin,Vout Min absolute level of Vin,Vout and VSSQ
Undershoot Area below Min absolute level of Vin, Vout
Data, Strobe and Mask Overshoot and Undershoot Definition
Rev. 1.4 / Aug.2019 28

Slew Rate Definitions
Slew Rate Definitions for Differential Input Signals (CK)
Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Table and Fig-
ure below.
Differential Input Slew Rate Definition
Description Defined by
from to
Differential input slew rate for rising edge(CK_t - V V
VILdiffmax VIHdiffmin [ IHdiffmin - ILdiffmax ] / DeltaTR-
CK_c) diff
Differential input slew rate for falling edge(CK_t - V V
VIHdiffmin VILdiffmax [ IHdiffmin - ILdiffmax ] / DeltaTF-
CK_c) diff
NOTE: The differential signal (i,e.,CK_t - CK_c) must be linear between these thresholds.
Delta TRdiff
Differential Input Voltage(i,e, CK_t - CK_c)
V
IHdiffmin
V
ILdiffmax
Delta TFdiff
Differential Input Slew Rate Definition for CK_t, CK_c
Rev. 1.4 / Aug.2019 29

Slew Rate Definition for Single-ended Input Signals (CMD/ADD)
Delta TRsingle
V
IHCA(AC) Min
V
IHCA(DC) Min
VREFCA(DC)
V
ILCA(DC) Max
V
ILCA(AC) Max
Delta TFsingle
Single-ended Input Slew Rate definition for CMD and ADD

NOTE :
1. Single-ended input slew rate for rising edge = { VIHCA(AC)Min - VILCA(DC)Max } / Delta TR single
2. Single-ended input slew rate for falling edge = { VIHCA(DC)Min - VILCA(AC)Max } / Delta TF single
3. Single-ended signal rising edge from VILCA(DC)Max to VIHCA(DC)Min must be monotonic slope.
4. Single-ended signal falling edge from VIHCA(DC)Min to VILCA(DC)Max must be monotonic slope
Rev. 1.4 / Aug.2019 30

Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each
cross point voltage of differential input signals (CK_t, CK_c) must meet the requirements in Table. The dif-
ferential input cross point voltage VIX is measured from the actual cross point of true and complement sig-
nals to the midlevel between of VDD and VSS.
VDD
CK_t
Vix
VDD/2
Vix
CK_c
VSEH VSEL
VSS
Vix Definition (CK)
Cross point voltage for differential input signals (CK)

DDR4-1600/1866/2133
Symbol Parameter
min max
VDD/2 -
VSEL =< VDD/2 + 100mV VDD/2 +
145mV =<
- Area of VSEH, VSEL =< VSEH =< 145mV =<
VDD/2 - 145mV VSEL =< VDD/ VDD/2 + 145mV VSEH
2 - 100mV
Differential Input Cross (VSEH - VDD/2)
- (VDD/2 -
VlX(CK) Point Voltage relative to -120mV 120mV
VSEL) + 25mV - 25mV
VDD/2 for CK_t, CK_c
Rev. 1.4 / Aug.2019 31

DDR4-2400/2666/2933/3200
Symbol Parameter
min max
VDD/2 -
VSEL =< VDD/2 + 100mV VDD/2 +
145mV =<
- Area of VSEH, VSEL =< VSEH =< 145mV =<
VDD/2 - 145mV VSEL =< VDD/ VDD/2 + 145mV VSEH
2 - 100mV
Differential Input Cross (VSEH - VDD/2)
- (VDD/2 -
VlX(CK) Point Voltage relative to -120mV 120mV
VSEL) + 25mV - 25mV
VDD/2 for CK_t, CK_c
Rev. 1.4 / Aug.2019 32

CMOS rail to rail Input Levels
CMOS rail to rail Input Levels for RESET_n
CMOS rail to rail Input Levels for RESET_n
Parameter Symbol Min Max Unit NOTE
AC Input High Voltage VIH(AC)_RESET 0.8*VDD VDD V 6
DC Input High Voltage VIH(DC)_RESET 0.7*VDD VDD V 2
DC Input Low Voltage VIL(DC)_RESET VSS 0.3*VDD V 1
AC Input Low Voltage VIL(AC)_RESET VSS 0.2*VDD V 7
Rising time TR_RESET - 1.0 us 4
RESET pulse width tPW_RESET 1.0 - us 3,5
NOTE :
1. After RESET_n is registered LOW, RESET_n level shall be maintained below VIL(DC)_RESET during tPW_RESET,
otherwise, SDRAM may not be reset.
2. Once RESET_n is registered HIGH, RESET_n level must be maintained above VIH(DC)_RESET, otherwise, SDRAM
operation will not be guaranteed until it is reset asserting RESET_n signal LOW.
3. RESET is destructive to data contents.
4. No slope reversal(ringback) requirement during its level transition from Low to High.
5. This definition is applied only “Reset Procedure at Power Stable”.
6. Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings.
7. Undershoot might occur. It should be limited by Absolute Maximum DC Ratings
tPW_RESET
0.8*VDD
0.7*VDD
0.3*VDD
0.2*VDD
TR_RESET
RESET_n Input Slew Rate Definition
Rev. 1.4 / Aug.2019 33

AC and DC Logic Input Levels for DQS Signals
Differential signal definition
Definition of differential DQS Signal AC-swing Level
Differential swing requirements for DQS (DQS_t - DQS_c)

Differential AC and DC Input Levels for DQS
DDR4-1600,1866,2133 DDR4-2400 DDR4-2666,2933,3200
Symbol Parameter Unit Note
Min Max Min Max Min Max
VIHDiffPeak VIH.DIFF.Peak Voltage 186 Note2 160 Note2 140 Note2 mV 1
VILDiffPeak VIL.DIFF.Peak Voltage Note2 -186 Note2 -160 Note2 -140 mV 1
NOTE :
1. Used to define a differential signal slew-rate.
2. These values are not defined; however, the differential signals DQS_t - DQS_c, need to be within the respective
limits Overshoot, Undershoot Specification for single-ended signals.
Rev. 1.4 / Aug.2019 34

Peak voltage calculation method
The peak voltage of Differential DQS signals are calculated in a following equation.
VIH.DIFF.Peak Voltage = Max(f(t))
VIL.DIFF.Peak Voltage = Min(f(t))
f(t) = VDQS_t - VDQS_c
The Max(f(t)) or Min(f(t)) used t o determine the midpoint which to reference the +/-35% window of the
exempt non-monotonic signaling shall be the samllest peak voltage observed in all ui’s.
Definition of differential DQS Peak Voltage and rage of exempt non-monotonic signaling
Rev. 1.4 / Aug.2019 35

Differential Input Cross Point Voltage
To achieve tight RxMask input requirements as well as output skew parameters with respect to strobe, the
cross point voltage of differential input signals (DQS_t, DQS_c) must meet the requirements in Tabel
below. The differential input cross point voltage VIX_DQS (VIX_DQS_FR and VIX_DQS_RF) ins measured
from the actual cross point of DQS_t, DQS_c relative to the VDQSmid fo the DQS_t and DQS_c signals.
VDQSmid is the midpoint of the minimum levels achieved by the transitioning DQS_t and DQS_c signals,
and noted by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above
VDQSmid of the transitioning DQS signals and the highest horizontal tangent below VDQSmid of the tran-
sitioning DQS signals.
A non-monotonic transitioning signal’s ledge is exempt or not used in determination of a horizontal tangent
provieded the said ledge occurs within +/- 30% of the midpoint of either VID.DIFF.Peak Voltage (DQS_t
rising) of VIL.DIFF.Peak Voltage (DQS_c rising), refer to Furure Definition of differential DQS Peak Voltage
and rage of exempt non-monotonic signaling. A secondary horizontal tangent resulting from a ring-back
transition is also exempt in determination of a horizontal tangent. Thath is, a falling transition’s horizontal
tangent is derived from its negative slope to zero slope transition (point A in Fugure bloew) and a ring-
back’s horizontal tangent derived from its positive slope to zero slope transition (point B in Figure below) is
not a valid horizontal tangent; and a rising transition’s horizontal tangent is derived from its positive slope
to zero slope transition (point C in Figure below) and a ring-back’s horizontal tangent derived from its neg-
ative slope to zero slope transition (point D in Figure below) is not a valid horizontal tangent.
Vix Definition (DQS)
Rev. 1.4 / Aug.2019 36

Cross point voltage for differential input signals
DDR4- DDR4-
Symbol Parameter 1600,1866,2133,2400 2666,2933,3200 Unit Note
Min Max Min Max
DQS_t and DQS_c crossing relative
Vix_DOS_
to the midpoint of the DQS_t and - 25 - 25 % 1,2
ratio
DQS_c signal swings
VDQSmid_to_ VDQSmid offset relative to min(VIH- min(VIH-
- - mV 3,4,5
Vcent Vcent_DQ(midpoint) diff, 50) diff, 50)
NOTE :
1. Vix_DQS_Ratio is DQS VIX crossing (Vix_DQS_FR or Vix_DQS_RF) divided by VDQS_trans. VDQS_trans is the
difference between the lowest horizontal tangent above VDQSmid of the transitioning DQS signals and the highest
horizontal tangent below VDQSmid of the transitioning DQS signals.
2. VDQSmid will be similar to the VREFDQ internal setting value obtained during Vref Training if the DQS and DQs
drivers and paths are matched.
3. Teh maximum limite shall not exceed the smaller of VIHdiff minimum limit or 50mV.
4. VIX measurements are only applicable for transitioning DQS_t and DQS_c signals when toggling data, preamble and
high-z states are not applicable conditions.
5. The parameter VDQSmid is defined for simulation and ATE testing purposes, it is not expected to be tested in a
system.
Rev. 1.4 / Aug.2019 37

Differential Input Slew Rate Definition
Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in Figure
below.
NOTE :
1. Differential signal rising edge from VILDiff_DQS to VIHDiff_DQS must be monotonic slope.
2. Differential signal falling edge from VIHDiff_DQS to VILDiff_DQS must be monotonic slope.
Differential Input Slew Rate Definition for DQS_t, DQS_c
Differential Input Slew Rate Definition for DQS_t, DQS_c
From To
Differential input slew rate for
VILDiff_DQS VIHDiff_DQS |VILDiff_DQS - VIHDiff_DQS|/DeltaTRdiff
rising edge(DQS_t - DQS_c)
Differential input slew rate for
VIHDiff_DQS VILDiff_DQS |VILDiff_DQS - VIHDiff_DQS|/DeltaTFdiff
falling edge(DQS_t - DQS_c)
Rev. 1.4 / Aug.2019 38

Differential Input Level for DQS_t, DQS_c
DDR4-
1600,1866, DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 U N
Symbol Parameter 2133 ni ot
t e
Min Max Min Max Min Max Min Max Min Max
VIHDif- Differential m
136 - 130 - 130 - 115 - 110 -
f_DQS Input High V
VILDif- Differential m
- -136 - -130 - -130 - -115 - -110
f_DQS Input Low V
Differential Input Slew Rate for DQS_t, DQS_c

DDR4-
1600,1866,21 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 U
No
Symbol Parameter 33 ni
te
t
Min Max Min Max Min Max Min Max Min Max
Differential
V/
SRIdiff Input Slew 3 18 3 18 2.5 18 2.5 18 2.5 18
ns
Rate
Rev. 1.4 / Aug.2019 39

AC and DC output Measurement levels
Single-ended AC & DC Output Levels
Single-ended AC & DC output levels
DDR4-1600/1866/2133/
Symbol Parameter Units NOTE
2400/2666/2933
VOH(DC) DC output high measurement level (for IV curve linearity) 1.1 x VDDQ V
VOM(DC) DC output mid measurement level (for IV curve linearity) 0.8 x VDDQ V
VOL(DC) DC output low measurement level (for IV curve linearity) 0.5 x VDDQ V
VOH(AC) AC output high measurement level (for output SR) (0.7 + 0.15) x VDDQ V 1
VOL(AC) AC output low measurement level (for output SR) (0.7 - 0.15) x VDDQ V 1
NOTE :
1. The swing of ± 0.15 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing
with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ.
Differential AC & DC Output Levels

Differential AC & DC output levels
DDR4-1600/1866/
Symbol Parameter Units NOTE
2133/2400/2666/2933
VOHdiff(AC) AC differential output high measurement level (for output SR) +0.3 x VDDQ V 1
VOLdiff(AC) AC differential output low measurement level (for output SR) -0.3 x VDDQ V 1
NOTE :
1. The swing of ± 0.3 × VDDQ is based on approximately 50% of the static differential output peak-to-peak swing with
a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ at each of the differential outputs.
Rev. 1.4 / Aug.2019 40

Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table and Figure below.
Single-ended output slew rate definition

Measured
From To
[VOH(AC)-VOL(AC)] /
Single ended output slew rate for rising edge VOL(AC) VOH(AC)
Delta TRse
[VOH(AC)-VOL(AC)] /
Single ended output slew rate for falling edge VOH(AC) VOL(AC)
Delta TFse
NOTE :
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
VOH(AC)
VOL(AC)
delta TFse delta TRse
Single-ended Output Slew Rate Definition
Single-ended output slew rate

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200
Parameter Symbol Units
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Single ended output slew rate SRQse 4 9 4 9 4 9 4 9 4 9 4 9 4 9 V/ns
Description: SR: Slew Rate

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
NOTE:
1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.
-Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or
low).
-Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction
(i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction,
the regular maximum limit of 9 V/ns applies
Rev. 1.4 / Aug.2019 41

Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table and Figure
below.
Differential output slew rate definition

Measured
From To
[VOHdiff(AC)-VOLdiff(AC)] /
Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC)
Delta TRdiff
[VOHdiff(AC)-VOLdiff(AC)] /
Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC)
Delta TFdiff
NOTE :
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
VOHdiff(AC)
VOLdiff(AC)
delta TFdiff delta TRdiff
Differential Output Slew Rate Definition
Differential output slew rate

Parameter Symbol Units
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Differential output slew rate SRQdiff 8 18 8 18 8 18 8 18 8 18 8 18 8 18 V/ns
Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
diff: Differential Signals
For Ron = RZQ/7 setting
Rev. 1.4 / Aug.2019 42

Single-ended AC & DC Output Levels of Connectivity Test Mode
Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test
Mode.
Single-ended AC & DC output levels of Connectivity Test Mode

DDR4-1600/1866/2133/
Symbol Parameter Unit Note
2400/2666/2933
VOH(DC) DC output high measurement level (for IV curve linearity) 1.1 x VDDQ V
VOM(DC) DC output mid measurement level (for IV curve linearity) 0.8 x VDDQ V
VOL(DC) DC output low measurement level (for IV curve linearity) 0.5 x VDDQ V
VOB(DC) DC output below measurement level (for IV curve linearity) 0.2 x VDDQ V
VOH(AC) AC output high measurement level (for output SR) VTT + (0.1 x VDDQ) V 1
VOL(AC) AC output below measurement level (for output SR) VTT - (0.1 x VDDQ) V 1
NOTE :
1. The effective test load is 50 terminated by VTT = 0.5 * VDDQ.
VOH(AC)
VTT 0.5 * VDDQ
VOL(AC)
TF_output_CT TR_output_CT
Differential Output Slew Rate Definition of Connectivity Test Mode
Single-ended output slew rate of Connectivity Test Mode

DDR4-1600/1866/2133/2400/2666/2933
Parameter Symbol Unit Note
Min Max
Output signal Falling time TF_output_CT - 10 ns/V
Output signal Rising time TR_output_CT - 10 ns/V
Rev. 1.4 / Aug.2019 43

Standard Speed Bins
DDR4-1600 Speed Bins and Operations
Speed Bin DDR4-1600K
CL-nRCD-nRP 11-11-11 Unit NOTE
Parameter Symbol min max
14
Internal read command to first 13.75
tAA 18.00 ns 12
data (13.50)5,12
Internal read command to first
tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 12
data with read DBI enabled
ACT to internal read or write 13.75
tRCD - ns 12
delay time (13.50)5,12
13.75
PRE command period tRP - ns 12
(13.50)5,12
ACT to PRE command period tRAS 35 9 x tREFI ns 12
ACT to ACT or REF command 48.75
tRC - ns 12
period (48.50)5,12
Normal Read DBI
CL = 11 1,2,3,4,
CL = 9 (Optional) tCK(AVG) 1.5 1.6 ns 11,14
CWL = 9 5
1,2,3,4,
CL = 10 CL = 12 tCK(AVG) Reserved ns
11
CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4
CWL =
CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4
9,11
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3
Supported CL Settings (9),11,12 nCK 13,14
Supported CL Settings with read DBI (11),13,14 nCK 13
Supported CWL Settings 9,11 nCK
Rev. 1.4 / Aug.2019 44

Speed Bin DDR4-1866M
tAA 18.00 ns 12
data (13.50)5,12
tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 12
tRCD - ns 12
13.92
(13.50)5,12
tRC - ns 12
period (47.50)5,12
Normal Read DBI

CL = 11 1,2,3,4,
CL = 9 tCK(AVG) 1.5 1.6 ns 11,14
(Optional)5
CWL = 9
1,2,3,4,
CL = 10 CL = 12 tCK(AVG) Reserved ns
11
CL = 10 CL = 12 tCK(AVG) Reserved ns 4
CWL = 1,2,3,4,
CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns
6
9,11
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,6

CWL =
CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4
10,12
CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3
Supported CL Settings 9,11,12,13,14 nCK 13,14
Supported CL Settings with read DBI 11,13,14 15,16 nCK 13
Supported CWL Settings 9,10,11,12 nCK
Rev. 1.4 / Aug.2019 45

Speed Bin DDR4-2133P

tAA 18.00 ns 12
data (13.50)5,12
tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 12
ACT to internal read or write delay 14.06
tRCD - ns 12
time (13.50)5,12
14.06
(13.50)5,12
tRC - ns 12
period (46.50)5,12
Normal Read DBI
1,2,3,4,
CL = 9 CL = 11 tCK(AVG) 1.5 1.6 ns
CWL = 9 11,14
1,2,3,4,
CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns
CWL = 9,11 7
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,7
1,2,3,4,
CWL = CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns
7
10,12
CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,7
CWL =
11,14
CL = 15 CL = 18 tCK(AVG) 0.937 <1.071 ns 1,2,3,4
CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3
Supported CL Settings (9),(11),12,(13),14,15,16 nCK 13,14
Supported CL Settings with read DBI (11),(13),14,(15),16,18,19 nCK
Supported CWL Settings 9,10,11,12,14 ns 12
Rev. 1.4 / Aug.2019 46

Speed Bin DDR4-2400T
tAA 18.00 ns 12
data (13.75)5,12
tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 12
tRCD - ns 12
14.16
(13.75)5,12
tRC - ns 12
period (45.75)5,12
Normal Read DBI
CL = 11 1,2,3,4,11
CL = 9 Reserved ns
CWL = 9 (Optional)5 tCK(AVG)
CL = 10 CL = 12 1.5 1.6 ns 1,2,3,4,11
CWL = 9,11 CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,8
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,8
CWL =
10,12
CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4,8
CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,8
CWL =
11,14
CL = 15 CL = 18 tCK(AVG) 0.937 <1.071 ns 1,2,3,4,8
CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,8
CWL = CL = 16 CL = 19 tCK(AVG) Reserved ns 1,2,3,4

12,16 CL = 17 CL = 20 tCK(AVG) 0.833 <0.937
CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 ns 1,2,3
Supported CL Settings 10,11,12,13,14,15,16,17,18 nCK 13
Supported CL Settings with read DBI 12,13,14,15,16,18,19,20,21 nCK
Supported CWL Settings 9,10,11,12,14,16 nCK
Rev. 1.4 / Aug.2019 47

Speed Bin DDR4-2666V
Internal read command to 14.2514
tAA 18.00 ns 12
first data (13.75)5,12
Internal read command to
first data with read DBI tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 12
enabled
tRCD - ns 12
PRE command period 14.25
tRP - ns 12
(13.75)5,12
ACT to PRE command
tRAS 32 9 x tREFI ns 12
period
ACT to ACT or REF com- 46.25
tRC - ns 12
mand period (45.75)5,12
Normal Read DBI
CWL = 9 CL = 9 CL = 11 tCK(AVG) Reserved ns 1,2,3,4,11
CL = 10 CL = 12 tCK(AVG) 1.5 1.6 ns 1,2,3,11
CWL = CL = 10 CL = 12 tCK(AVG) Reserved ns 4
9,11 CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,9
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,9
10,12 CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4,9
CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,9
11,14 CL = 15 CL = 18 tCK(AVG) 0.937 <1.071 ns 1,2,3,4,9
CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,9
12.16 CL = 16 CL = 19 tCK(AVG) Reserved ns 1,2,3,4,9
CL = 17 CL = 20 tCK(AVG) 0.833 <0.937 ns 1,2,3,4,9
CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 ns 1,2,3
14,18 CL = 18 CL = 21 tCK(AVG) Reserved ns 1,2,3,4
CL = 19 CL = 22 tCK(AVG) 0.75 <0.833 ns 1,2,3,4
CL = 20 CL = 23 tCK(AVG) 0.75 <0.833 ns 1,2,3
Supported CL Settings 10,(11),12,(13),14,(15),16,(17),18,19,20 nCK 13
Supported CL Settings with read DBI 12,(13),14,(15),17,(18),19,(20),21,22,23 nCK
Supported CWL Settings 9,10,11,12,14,16,18 nCK
Rev. 1.4 / Aug.2019 48

Speed Bin DDR4-2933Y
Internal read command to tAA 14.3214 18.00 ns 12
first data (13.75)5,12
first data with read DBI tAA_DBI tAA(min) + 4nCK tAA(max) + 4nCK ns 12
enabled
tRCD - ns 12
14.32
(13.75)5,12
ACT to PRE command
period
ACT to ACT or REF com- 46.32
tRC - ns 12
mand period (45.75)5,12
Read
Normal
DBI
CWL = CL = 9 CL = 11 tCK(AVG) Reserved ns 1,2,3,4,11
9 CL = 10 CL = 12 tCK(AVG) 1.5 1.6 ns 1,2,3,11
9,11 CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,13
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,15
10,12 CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4,15
CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,15
11,14 CL = 15 CL = 18 tCK(AVG) 0.937 <1.071 ns 1,2,3,4,15
CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,15
CL = 17 CL = 20 tCK(AVG) 0.833 0.937 ns 1,2,3,4,15
CL = 18 CL = 21 tCK(AVG) 0.833 0.937 ns 1,2,3,15
14,18 CL = 18 CL = 21 tCK(AVG) Reserved ns 1,2,3,4,15
CL = 19 CL = 22 tCK(AVG) 0.75 <0.833 ns 1,2,3,4,15
CL = 20 CL = 23 tCK(AVG) 0.75 <0.833 ns 1,2,3,15
16,20 CL = 20 CL = 24 tCK(AVG) Reserved ns 1,2,3,4
CL = 21 CL = 26 tCK(AVG) 0.682 <0.75 ns 1,2,3,4
CL = 22 CL = 26 tCK(AVG) 0.682 <0.75 ns 1,2,3
Supported CL Settings 10,(11),12,(13),14,(15),16,(17),18,(19),20, nCK 13
21,22
Supported CL Settings with read DBI 12,(13),14,(15),16,(18),19,(20),21,(22),23, nCK 13
25,26
Supported CWL Settings 9,10,11,12,14,15,16,18,20 nCK
Rev. 1.4 / Aug.2019 49

Speed Bin DDR4-3200AA
tAA 13.75 18.00 ns 12
first data
tAA(min)
first data with read DBI tAA_DBI tAA(max) + 4nCK ns 12
+ 4nCK
enabled
ACT to internal read or
tRCD 13.75 - ns 12
write delay time
PRE command period tRP 13.75 - ns 12
ACT to PRE command
period
ACT to ACT or REF com-
tRC 45.75 - ns 12
mand period
Read
Normal
DBI
CWL = CL = 9 CL = 11 tCK(AVG) Reserved ns 1,2,3,4,11
9 CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4,11
9,11 CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,10
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,10
10,12 CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4,10
CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,10
11,14 CL = 15 CL = 18 tCK(AVG) 0.937 <1.071 ns 1,2,3,4,10
CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,10
CL = 17 CL = 20 tCK(AVG) 0.833 <0.937 ns 1,2,3,4,10
CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 ns 1,2,3,10
14,18 CL = 18 CL = 21 tCK(AVG) Reserved ns 1,2,3,4,10
CL = 19 CL = 22 tCK(AVG) 0.75 <0.833 ns 1,2,3,4,10
CL = 20 CL = 23 tCK(AVG) 0.75 <0.833 ns 1,2,3,10
16,20 CL = 22 CL = 26 tCK(AVG) 0.625 <0.75 ns 1,2,3,4
CL = 24 CL = 28 tCK(AVG) 0.625 <0.75 ns 1,2,3
Supported CL Settings 10,11,12,13,14,15, 16,17,18,19,20,22, nCK 13
24
Supported CL Settings with read DBI 12,13,14,15,16,18, 19,20,21,22,23,24, nCK
26, 28
Supported CWL Settings 9,10,11,12,14,16, nCK
18,20


Rev. 1.4 / Aug.2019 50

Speed Bin Table Note
Absolute Specification
- VDDQ = VDD = 1.20V +/- 0.06 V
- VPP = 2.5V +0.25/-0.125 V
- The values defined with above-mentioned table are DLL ON case.
- DDR4-1600, 1866, 2133, 2400, 2933 and 3200 Speed Bin Tables are valid only when Geardown Mode is
disabled.
1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection
of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL
- all possible intermediate frequencies may not be guaranteed. CL in clock cycle is calculated from tAA following
rounding algorithm defined in Section 13.5.
3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg) down to the
next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071 ns or 0.937 ns or 0.833 ns). This result is tCK(avg).MAX corre-
sponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory fea-
ture. Refer to supplier's data sheet and/or the DIMM SPD information if and how this setting is supported.
6. Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are
not subject to Production Tests but verified by Design/Characterization.
11. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.
12. DDR4-2400,2666,2933 and 3200Mbps speed bin support CL=10 if DRAM operate at 1333MT/s data rate.
13. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the
Speed Bin Tables.
14. CL number in parentheses, it means that these numbers are optional.
15. DDR4 SDRAM supports CL=9 as long as a system meets tAA(min).
16. Each speed bin lists the timing requirements that need to be supported in order for a given DRAM to be JEDEC
compliant. JEDEC compliance does not require support for all speed bins within a given speed. JEDEC compliance
requires meeting the parameters for a least one of the listed speed bins.
Rev. 1.4 / Aug.2019 51

IDD and IDDQ Specification Parameters and Test Conditions
IDD, IPP and IDDQ Measurement Conditions
In this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined.
Figure shows the setup and test load for IDD, IPP and IDDQ measurements.
• IDD currents (such as IDD0, IDD0A, IDD1, IDD1A, IDD2N, IDD2NA, IDD2NL, IDD2NT, IDD2P, IDD2Q,
IDD3N, IDD3NA, IDD3P, IDD4R, IDD4RA, IDD4W, IDD4WA, IDD5B, IDD5F2, IDD5F4, IDD6N, IDD6E,
IDD6R, IDD6A, IDD7 and IDD8) are measured as time-averaged currents with all VDD balls of the
DDR4 SDRAM under test tied together. Any IPP or IDDQ current is not included in IDD currents.
• IPP currents have the same definition as IDD except that the current on the VPP supply is measured.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR4 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-
rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR4 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD, IPP and IDDQ measurements, the following definitions apply:
• “0” and “LOW” is defined as VIN <= VILAC(max).
• “1” and “HIGH” is defined as VIN >= VIHAC(min).
• “MID-LEVEL” is defined as inputs are VREF = VDD / 2.
• Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns are provided in Table 1.
• Basic IDD, IPP and IDDQ Measurement Conditions are described in Table 2.
• Detailed IDD, IPP and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 11.
• IDD Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not lim-
ited to setting 
RON = RZQ/7 (34 Ohm in MR1); 
RTT_NOM = RZQ/6 (40 Ohm in MR1);
RTT_WR = RZQ/2 (120 Ohm in MR2);
RTT_PARK = Disable;
Qoff = 0B (Output Buffer enabled) in MR1;
TDQS_t disabled in MR1;
CRC disabled in MR2;
CA parity feature disabled in MR5;
Gear down mode disabled in MR3
Read/Write DBI disabled in MR5;
DM disabled in MR5
• Attention: The IDD, IPP and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
• Define D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, LOW, LOW, LOW, LOW} ; apply BG/BA
changes when directed.
• Define D# = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, HIGH, HIGH, HIGH, HIGH} ; apply
invert of BG/BA changes when directed above.
Rev. 1.4 / Aug.2019 52

IDD IPP IDDQ
VDD VPP VDDQ

RESET
CK_t/CK_c
DDR4 SDRAM
CKE
CS DQS_t/DQS_c
C DQ
ACT,RAS,CAS,WE DM
A,BG,BA
ODT VSS VSSQ
ZQ
NOTE:
1. DIMM level Output test load condition may be different from above
Figure 1 - Measurement Setup and Test Load for IDD, IPP and IDDQ Measurements
Application specific
memory channel IDDQ
TestLad
environment
Channel
IO Powe IDDQ IDDQ
Simuaion Measurement
Simulatin
X Correlation
X
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ
Measurement
Rev. 1.4 / Aug.2019 53

Table 1-Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns
Symbol Unit
11-11-11 13-13-13 15-15-15 17-17-17 19-19-19 21-21-21 22-22-22
tCK 1.25 1.071 0.937 0.833 0.75 0.682 0.625 ns
CL 11 13 15 17 19 21 22 nCK
CWL 11 12 14 16 18 20 20 nCK
nRCD 11 13 15 17 19 21 22 nCK
nRC 39 45 51 56 62 68 74 nCK
nRAS 28 32 36 39 43 47 52 nCK
nRP 11 13 15 17 19 21 22 nCK
x4 16 16 16 16 16 16 16 nCK
nFAW x8 20 22 23 26 28 31 34 nCK
x16 28 28 32 36 40 44 48 nCK
x4 4 4 4 4 4 4 4 nCK
nRRDS x8 4 4 4 4 4 4 4 nCK
x16 5 5 6 7 8 8 9 nCK
x4 5 5 6 6 7 8 8 nCK
nRRDL x8 5 5 6 6 7 8 8 nCK
x16 6 6 7 8 9 10 11 nCK
tCCD_S 4 4 4 4 4 4 4 nCK
tCCD_L 5 5 6 6 7 8 8 nCK
tWTR_S 2 3 3 3 4 4 4 nCK
tWTR_L 6 7 8 9 10 11 12 nCK
nRFC 2Gb 128 150 171 193 214 235 256 nCK
nRFC 4Gb 208 243 278 313 347 382 416 nCK
nRFC 8Gb 280 327 374 421 467 514 560 nCK
nRFC 16Gb 280 327 374 421 467 514 560 nCK
Rev. 1.4 / Aug.2019 54

Table 2 -Basic IDD, IPP and IDDQ Measurement Conditions
Symbol Description
Operating One Bank Active-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 81; AL: 0; CS_n: High
between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially
IDD0
toggling according to Table 3; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: Cycling with one
bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Regis-
ters2; ODT Signal: stable at 0; Pattern Details: see Table 3
Operating One Bank Active-Precharge Current (AL=CL-1)
IDD0A
AL = CL-1, Other conditions: see IDD0
Operating One Bank Active-Precharge IPP Current
IPP0
Same condition with IDD0
Operating One Bank Active-Read-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 81; AL: 0; CS_n: High
between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs,
IDD1
Data IO: partially toggling according to Table 4; DM_n: stable at 1; Bank Activity: Cycling with one
bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Regis-
ters2; ODT Signal: stable at 0; Pattern Details: see Table 4
Operating One Bank Active-Read-Precharge Current (AL=CL-1)
IDD1A
AL = CL-1, Other conditions: see IDD1
Operating One Bank Active-Read-Precharge IPP Current
IPP1
Precharge Standby Current (AL=0)
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
IDD2N Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data
IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 5
Precharge Standby Current (AL=CL-1)
IDD2NA
AL = CL-1, Other conditions: see IDD2N
Precharge Standby IPP Current
IPP2N
Same condition with IDD2N
Precharge Standby ODT Current
IDD2NT Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 6; Data
IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: toggling according to Table 6; Pattern Details: see Table 6
IDDQ2NT Precharge Standby ODT IDDQ Current
(Optional) Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Standby Current with CAL enabled
IDD2NL
Same definition like for IDD2N, CAL enabled3
Precharge Standby Current with Gear Down mode enabled
IDD2NG
Same definition like for IDD2N, Gear Down mode enabled3,5
Precharge Standby Current with DLL disabled
IDD2ND
Same definition like for IDD2N, DLL disabled3
Rev. 1.4 / Aug.2019 55

Precharge Standby Current with CA parity enabled
IDD2N_par
Same definition like for IDD2N, CA parity enabled3
Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 81; AL:
0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at
IDD2P
0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT:
Enabled in Mode Registers2; ODT Signal: stable at 0
Precharge Power-Down IPP Current
IPP2P
Same condition with IDD2P
Precharge Quiet Standby Current
IDD2Q Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable
at 1;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT
Signal: stable at 0
Active Standby Current
IDD3N Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data
IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks open; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 5
Active Standby Current (AL=CL-1)
IDD3NA
AL = CL-1, Other conditions: see IDD3N
Active Standby IPP Current
IPP3N
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
IDD3P Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable
at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at 0
Active Power-Down IPP Current
IPP3P
Same condition with IDD3P
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 82; AL: 0; CS_n: High between RD;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to
IDD4R Table 7; Data IO: seamless read data burst with different data between one burst and the next one
according to Table 7; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through
banks: 0,0,1,1,2,2,... (see Table 7); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at 0; Pattern Details: see Table 7
Operating Burst Read Current (AL=CL-1)
IDD4RA
AL = CL-1, Other conditions: see IDD4R
Operating Burst Read Current with Read DBI
IDD4RB
Read DBI enabled3, Other conditions: see IDD4R
Operating Burst Read IPP Current
IPP4R
Same condition with IDD4R
IDDQ4R Operating Burst Read IDDQ Current
(Optional) Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
IDDQ4RB Operating Burst Read IDDQ Current with Read DBI
(Optional) Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current
Rev. 1.4 / Aug.2019 56

Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: High between WR;
IDD4W Table 8; Data IO: seamless write data burst with different data between one burst and the next one
according to Table 8; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through
banks: 0,0,1,1,2,2,... (see Table 8); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at HIGH; Pattern Details: see Table 8
Operating Burst Write Current (AL=CL-1)
IDD4WA
AL = CL-1, Other conditions: see IDD4W
Operating Burst Write Current with Write DBI
IDD4WB
Write DBI enabled3, Other conditions: see IDD4W
Operating Burst Write Current with Write CRC
IDD4WC
Write CRC enabled3, Other conditions: see IDD4W
Operating Burst Write Current with CA Parity
IDD4W_par
CA Parity enabled3, Other conditions: see IDD4W
Operating Burst Write IPP Current
IPP4W
Same condition with IDD4W
Burst Refresh Current (1X REF)
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 81; AL: 0; CS_n: High between REF;
IDD5B
Table 9; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: REF command every nRFC (see Table 9);
Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see
Table 9
Burst Refresh Write IPP Current (1X REF)
IPP5B
Same condition with IDD5B
IDD5F2
tRFC=tRFC_x2, Other conditions: see IDD5B
IPP5F2
Same condition with IDD5F2
IDD5F4
tRFC=tRFC_x4, Other conditions: see IDD5B
IPP5F4
Same condition with IDD5F4
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock:
IDD6N Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group
Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation;
Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
Self Refresh IPP Current: Normal Temperature Range
IPP6N
Self-Refresh Current: Extended Temperature Range)
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock:
IDD6E Off; CK_t and CK_c: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n, Command, Address, Bank Group
Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
Self Refresh IPP Current: Extended Temperature Range
IPP6E
Same condition with IDD6E
Rev. 1.4 / Aug.2019 57

Self-Refresh Current: Reduced Temperature Range
TCASEfor CT devices: 0 to 45°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low;
External clock: Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command,
IDD6R
Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity:
Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2;
ODT Signal: MID-LEVEL
Self Refresh IPP Current: Reduced Temperature Range
IPP6R
Same condition with IDD6R
Auto Self-Refresh Current
TCASEfor CT devices: 0 to 95°C; Low Power Array Self Refresh (LP ASR) : Auto4; CKE: Low;
External clock: Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command,
IDD6A
Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity:
Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-
LEVEL
Auto Self-Refresh IPP Current
IPP6A
Same condition with IDD6A
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 1; BL: 81; AL:
CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address
IDD7 Inputs: partially toggling according to Table 10; Data IO: read data bursts with different data between
one burst and the next one according to Table 10; DM_n: stable at 1; Bank Activity: two times
interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 10; Output Buffer and
RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 10
Operating Bank Interleave Read IPP Current
IPP7
Maximum Power Down Current
IDD8
TBD
Maximum Power Down IPP Current
IPP8
Rev. 1.4 / Aug.2019 58

NOTE :
1. Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00].
2. Output Buffer Enable
- set MR1 [A12 = 0] : Qoff = Output buffer enabled
- set MR1 [A2:1 = 00] : Output Driver Impedance Control = RZQ/7
RTT_Nom enable
- set MR1 [A10:8 = 011] : RTT_NOM = RZQ/6
RTT_WR enable
- set MR2 [A10:9 = 01] : RTT_WR = RZQ/2
RTT_PARK disable
- set MR5 [A8:6 = 000]
3. CAL enabled : set MR4 [A8:6 = 001] : 1600MT/s
010] : 1866MT/s, 2133MT/s
011] : 2400MT/s
Gear Down mode enabled :set MR3 [A3 = 1] : 1/4 Rate
DLL disabled : set MR1 [A0 = 0]
CA parity enabled :set MR5 [A2:0 = 001] : 1600MT/s,1866MT/s, 2133MT/s
010] : 2400MT/s
Read DBI enabled : set MR5 [A12 = 1]
Write DBI enabled : set :MR5 [A11 = 1]
4. Low Power Array Self Refresh (LP ASR) : set MR2 [A7:6 = 00] : Normal
01] : Reduced Temperature range
10] : Extended Temperature range
11] : Auto Self Refresh
5. IDD2NG should be measured after sync pulse(NOP) input.
Rev. 1.4 / Aug.2019 59

Table 3 - IDD0, IDD0A and IPP0 Measurement-Loop Pattern1
RAS_n/ A16
CAS_n/ A15
A[17,13,11]
CK_t /CK_c
WE_n/ A14
A12/BC_n
Command
Sub-Loop
A[10]/AP
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
D_#,
3,4
D_#
1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
... repeat pattern 1...4 until nRAS - 1, truncate if necessary

nRAS PRE 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1 1*nRC repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 1 instead
Static High
toggling

11 11*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead For x4
and x8
12 12*nRC repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead only
NOTE:
1 .DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4. DQ signals are VDDQ.
Rev. 1.4 / Aug.2019 60

Table 4 - IDD1, IDD1A and IPP1 Measurement-Loop Patterna)
CK_t, CK_c
RAS_n/A16
CAS_n/A15
A[17,13,11]
WE_n/A14
Command
A12/BC_n
Sub-Loop
A[10]/AP
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
CKE
ODT
Data4
0 0 WR 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
1 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -
2,3 D#, D# 1 1 1 1 1 1 0 3 2 3 0 0 0 7 F 0 -
1 4 WR 0 1 1 0 0 1 0 1 1 0 0 0 7 F 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
5 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -
6,7 D#, D# 1 1 1 1 1 1 0 3 2 3 0 0 0 7 F 0 -
2 8-11 2
repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead
3 12-15 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
8 32-35 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead For x4 and x8 only

Static High
14 56-59
toggling
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead

NOTE:
1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ
4.Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ.
Rev. 1.4 / Aug.2019 61

Table 5 - IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2ND, IDD2N_par, IPP2,IDD3N,
IDD3NA and IDD3P
Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
A[9:7]
A[6:3]
A[2:0]
ACT_n
Cycle
CS_n
ODT
CKE
Data4
0 0 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 D#, 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 0
D#
3 D#, 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 0
D#
Static High

toggling

NOTE :
1. DQS_t, DQS_c are VDDQ.
Rev. 1.4 / Aug.2019 62

Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
1 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
2 D#, D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
3 D#, D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
1 4-7 repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 1 instead
Static High
toggling

For x4
11 44-47 repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 3 instead and x8
12 48-51 repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 1 instead only
NOTE :
Rev. 1.4 / Aug.2019 63

Table 7 - IDD4R, IDDR4RA, IDD4RB and IDDQ4R Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 RD 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
1 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
2,3 D#, D# 1 1 1 1 1 0 0 3 2 3 0 0 0 7 F 0 -
1 4 RD 0 1 1 0 1 0 0 1 1 0 0 0 7 F 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
5 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
6,7 D#, D# 1 1 1 1 1 0 0 3 2 3 0 0 0 7 F 0 -
Static High

toggling

For x4 and x8 only
NOTE :
1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ.
4. Burst Sequence driven on each DQ signal by Read Command.
Rev. 1.4 / Aug.2019 64

Table 8 - IDD4W, IDD4WA, IDD4WB and IDD4W_par Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 WR 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
1 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -
2,3 D#, D# 1 1 1 1 1 1 0 3 2 3 0 0 0 7 F 0 -
1 4 WR 0 1 1 0 1 1 0 1 1 0 0 0 7 F 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
5 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -
6,7 D#, D# 1 1 1 1 1 1 0 3 2 3 0 0 0 7 F 0 -
2 8-11 repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead 2
Static High

toggling

For x4 and x8 only
NOTE :
1. DQS_t, DQS_c are used according to WR Commands, otherwise VDDQ.
4. Burst Sequence driven on each DQ signal by Write Command.
Rev. 1.4 / Aug.2019 65

Table 9 - IDD4WC Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]b
Number
BA[1:0]
C[2:0]c
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Datad
0 0 WR 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
D8=CRC
1,2 D, D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -
3,4 D#, D# 1 1 1 1 1 1 0 3 2 3 0 0 0 7 F 0 -
5 WR 0 1 1 0 1 1 0 1 1 0 0 0 7 F 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
D8=CRC
6,7 D, D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -
8,9 D#, D# 1 1 1 1 1 1 0 32 3 0 0 0 7 F 0 -
Static High
toggling

For x4 and x8 only
NOTE :
2. BG1 is don’t care for x16 device.
3. C[2:0] are used only for 3DS device.
4. Burst Sequence driven on each DQ signal by Write Command.
Rev. 1.4 / Aug.2019 66

Table 10 - IDD5B Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 REF 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
1 1 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
2 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
3 D#, D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
4 D#, D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
4-7 repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 1 instead
Static High
toggling

For x4 and x8
44-47 repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 3 instead only
2 64 ... nRFC - 1 repeat Sub-Loop 1, Truncate, if necessary
NOTE :
Rev. 1.4 / Aug.2019 67

Table 11 - IDD7 Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 ACT 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0
1 RDA 0 1 1 0 1 0 0
0 D0=00, D1=FF 0 0 0 1 0 0
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
2 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
3 D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
... repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary
1 nRRD ACT 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 -
nRRD + 1 RDA 0 1 1 0 1 0 1 1 0 0 1 0 0 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
... repeat pattern 2 ... 3 until 2*nRRD - 1, if nRRD > 4. Truncate if necessary
2 2*nRRD repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
3 3*nRRD repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
4 4*nRRD repeat pattern 2 ... 3 until nFAW - 1, if nFAW > 4*nRRD. Truncate if necessary
Static High
5 nFAW BG[1:0]2 = 0, BA[1:0] = 1

toggling
repeat Sub-Loop 0, use instead

6 nFAW + nRRD repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
7 nFAW + 2*nRRD repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
8 nFAW + 3*nRRD repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
9 nFAW + 4*nRRD repeat Sub-Loop 4
10 2*nFAW repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead

11 2*nFAW + nRRD repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead
12 2*nFAW + 2*nRRD repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
14 2*nFAW + 4*nRRD repeat Sub-Loop 4
For x4 and x8
15 3*nFAW repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead only
16 3*nFAW + nRRD repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead
19 3*nFAW + 4*nRRD repeat Sub-Loop 4
20 4*nFAW repeat pattern 2 ... 3 until nRC - 1, if nRC > 4*nFAW. Truncate if necessary
NOTE :
4. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ
Rev. 1.4 / Aug.2019 68

IDD Specification
Module IDD values in the datasheet are only a calculation based on the component IDD spec and register power. The
actual measurements may vary according to DQ loading cap.
64GB, 8Gx72 R-DIMM: HMAA8GR7AJR4N

IDD not IPP not
unit unit
Symbol 2400 2666 2933 3200 e Symbol 2400 2666 2933 3200 e
IDD0 1789 1855 1902 1957 mA IPP0 62 62 62 62 mA
IDD0A 1792 1857 1904 1960 mA IPP1 62 62 62 62 mA
IDD1 1953 2018 2068 2130 mA IPP2N 48 48 48 48 mA
IDD1A 1998 2071 2130 2194 mA IPP2P 48 48 48 48 mA
IDD2N 1654 1720 1762 1819 mA IPP3N 62 62 62 62 mA
IDD2NA 1655 1721 1764 1822 mA IPP3P 62 62 62 62 mA
IDD2NT 1804 1881 1941 2122 mA IPP4R 55 55 55 55 mA
IDD2NL 1258 1301 1345 1377 mA IPP4W 55 55 55 55 mA
IDD2NG 1636 1701 1758 1797 mA IPP5B 1193 1193 1189 1189 mA
IDD2ND 1608 1670 1715 1760 mA IPP5F2 790 797 797 801 mA
IDD2NP 1688 1756 1802 1862 mA IPP5F4 666 652 659 666 mA
IDD2P 1102 1129 1169 1210 mA IPP6N 150 150 150 150 mA
IDD2Q 1570 1616 1660 1695 mA IPP6E 255 255 255 255 mA
IDD3N 2112 2187 2227 2286 mA IPP6R 77 77 77 77 mA
IDD3NA 2112 2189 2227 2286 mA IPP6A 217 217 217 217 mA
IDD3P 1610 1634 1678 1720 mA IPP7 200 207 214 221 mA
IDD4R 2821 2984 3130 3297 mA IPP8 48 48 48 48 mA
IDD4RA 2860 3022 3169 3329 mA
IDD4RB 2829 2979 3128 3303 mA
IDD4W 2620 2757 2882 3025 mA
IDD4WA 2687 2838 2970 3118 mA
IDD4WB 2529 2657 2773 2906 mA
IDD4WC 2625 2759 2886 3031 mA
IDD4WP 3137 3299 3486 3659 mA
IDD5B 8113 8152 8182 8227 mA
IDD5F2 5903 5997 6073 6155 mA
IDD5F4 5254 5229 5314 5401 mA
IDD6N 1195 1196 1196 1196 mA
IDD6E 1775 1776 1776 1774 mA
IDD6R 691 696 694 694 mA
IDD6A 1777 1778 1776 1779 mA
IDD7 3592 3843 4084 4337 mA
IDD8 527 530 530 530 mA
Rev. 1.4 / Aug.2019 69

IDD not IPP not
unit unit
Symbol 2400 2666 2933 3200 e Symbol 2400 2666 2933 3200 e
IDD0 1104 1138 1167 1199 mA IPP0 31 31 31 31 mA
IDD0A 1105 1139 1169 1200 mA IPP1 31 31 31 31 mA
IDD1 1218 1249 1282 1317 mA IPP2N 25 25 25 24 mA
IDD1A 1241 1276 1313 1350 mA IPP2P 25 25 25 25 mA
IDD2N 1027 1058 1088 1119 mA IPP3N 35 35 35 35 mA
IDD2NA 1028 1060 1089 1120 mA IPP3P 35 35 35 35 mA
IDD2NT 1106 1145 1184 1254 mA IPP4R 30 30 30 30 mA
IDD2NL 830 855 881 906 mA IPP4W 30 30 30 30 mA
IDD2NG 1018 1049 1077 1107 mA IPP5B 603 603 601 599 mA
IDD2ND 998 1032 1061 1089 mA IPP5F2 399 401 403 405 mA
IDD2NP 1044 1077 1108 1141 mA IPP5F4 339 330 335 338 mA
IDD2P 666 677 703 727 mA IPP6N 76 76 76 76 mA
IDD2Q 980 1006 1030 1054 mA IPP6E 129 129 129 129 mA
IDD3N 1356 1385 1414 1446 mA IPP6R 39 39 39 39 mA
IDD3NA 1356 1385 1414 1446 mA IPP6A 114 114 114 114 mA
IDD3P 1018 1020 1053 1075 mA IPP7 87 87 87 87 mA
IDD4R 1868 1963 2078 2182 mA IPP8 25 25 25 25 mA
IDD4RA 1888 1983 2086 2191 mA
IDD4RB 1882 1975 2089 2195 mA
IDD4W 1724 1798 1885 1970 mA
IDD4WA 1751 1838 1929 2020 mA
IDD4WB 1668 1743 1824 1907 mA
IDD4WC 1713 1793 1877 1969 mA
IDD4WP 1937 2029 2138 2295 mA
IDD5B 4250 4268 4294 4317 mA
IDD5F2 3154 3201 3244 3287 mA
IDD5F4 2827 2770 2841 2912 mA
IDD6N 595 597 597 597 mA
IDD6E 892 895 895 895 mA
IDD6R 340 341 341 339 mA
IDD6A 894 895 895 895 mA
IDD7 1980 2041 2075 2131 mA
IDD8 257 258 258 258 mA
Rev. 1.4 / Aug.2019 70

IDD not IPP not
unit unit
Symbol 2400 2666 2933 3200 e Symbol 2400 2666 2933 3200 e
IDD0 1170 1205 1237 1268 mA IPP0 38 38 38 38 mA
IDD0A 1172 1206 1237 1270 mA IPP1 38 38 38 38 mA
IDD1 1333 1368 1402 1441 mA IPP2N 24 24 24 24 mA
IDD1A 1378 1420 1464 1503 mA IPP2P 24 24 24 24 mA
IDD2N 1034 1070 1096 1130 mA IPP3N 31 31 31 31 mA
IDD2NA 1035 1071 1097 1131 mA IPP3P 31 31 31 31 mA
IDD2NT 1109 1151 1186 1282 mA IPP4R 31 31 31 31 mA
IDD2NL 836 860 888 909 mA IPP4W 31 31 31 31 mA
IDD2NG 1025 1060 1094 1119 mA IPP5B 1170 1170 1167 1167 mA
IDD2ND 1011 1045 1073 1100 mA IPP5F2 767 774 774 778 mA
IDD2NP 1051 1088 1116 1151 mA IPP5F4 643 629 636 643 mA
IDD2P 682 693 718 744 mA IPP6N 75 75 75 75 mA
IDD2Q 992 1018 1045 1068 mA IPP6E 128 128 128 128 mA
IDD3N 1264 1305 1330 1364 mA IPP6R 39 39 39 39 mA
IDD3NA 1264 1306 1330 1364 mA IPP6A 109 109 108 109 mA
IDD3P 937 946 974 1000 mA IPP7 177 184 191 198 mA
IDD4R 2203 2336 2467 2610 mA IPP8 24 24 24 24 mA
IDD4RA 2242 2373 2504 2640 mA
IDD4RB 2211 2331 2464 2615 mA
IDD4W 2002 2108 2218 2337 mA
IDD4WA 2068 2189 2304 2429 mA
IDD4WB 1911 2008 2109 2218 mA
IDD4WC 2006 2110 2222 2343 mA
IDD4WP 2517 2649 2821 2970 mA
IDD5B 7499 7507 7522 7543 mA
IDD5F2 5287 5350 5410 5468 mA
IDD5F4 4637 4583 4651 4715 mA
IDD6N 603 604 604 604 mA
IDD6E 893 894 894 893 mA
IDD6R 351 354 353 353 mA
IDD6A 894 895 894 895 mA
IDD7 2974 3194 3420 3650 mA
IDD8 269 271 271 271 mA
Rev. 1.4 / Aug.2019 71

Module Dimensions
8Gx72 - HMAA8GR7AJR4N
Front
133.35
129.55
SPD/TS
2.10
Clock Driver
Registering
30.75
3.00
11.00
17.10
14.10
Detail A Detail B Detail D Detail E Detail C Detail F
2.70±0.15
8.00
Pin 1 Pin 35 Pin 47 Pin 105 Pin 117
3.35
64.60 56.10
Back
31.25±0.15
2x R0.60 Max
Side
Detail of Contacts A, F Detail of Contacts B Detail of Contacts C
0.60± 0.03 Pin 35 Pin 47 Pin 105 Pin 117 3.98mm max
2.10
2.10
2.60
2.60
Max 0.30
2.10
9.35 9.35
10.20 10.20
Non-matarized keep out area

0.85 Detail of Contacts D Detail of Contacts E
Max 0.25 Max 0.35
0.60± 0.03
4.30
3.85±0.1
0.2 ±0.15
2.60 1.40±0.1mm
Max 0.30
max
0.20 ±0.15
0.85
Max 0.25 Max 0.35 1.50 ±0.05
5.95
Note:
1.  0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.4 / Aug.2019 72

Front
133.35
129.55
SPD/TS
2.10±0.15
Clock Driver
Registering
30.75
3.00
11.00
17.10
14.10
2.70±0.15
8.00
3.35
64.60 56.10
Back
31.25±0.15
2x R0.75 Max
Side
2.10
2.10
2.60
2.60
Max 0.30
2.10
9.35 9.35
10.20 10.20

Max 0.25 Max 0.35
0.60± 0.03
4.30
3.85±0.1
0.2 ±0.15
2.60 1.40±0.1mm
Max 0.30
max
0.20 ±0.15
0.85
Max 0.25 Max 0.35 1.50 ±0.05
5.95
Note:
Units: millimeters
Rev. 1.4 / Aug.2019 73

Front
133.35
129.55
2.10±0.15 SPD/TS
Clock Driver
Registering
30.75
3.00
11.00
17.10
14.10
2.70±0.15
8.00
3.35
64.60 56.10
Back
31.25±0.15
2x R0.75 Max
Side
2.10
2.10
2.60
2.60
Max 0.30
2.10
9.35 9.35
10.20 10.20

Max 0.25 Max 0.35
0.60± 0.03
4.30
3.85±0.1
0.2 ±0.15
2.60
Max 0.30 1.40±0.1mm
max
0.20 ±0.15
0.85
Max 0.25 Max 0.35 1.50 ±0.05
5.95
Note:
Units: millimeters
Rev. 1.4 / Aug.2019 74

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288pin DDR4 SDRAM Registered DIMM

DDR4 SDRAM Registered DIMM

Rev. 1.4 / Aug.2019 1

Revision No. History Draft Date Remark

0.1 Initial Release Nov.2018

1.0 Define IDD/IPP Specifiation Dec.2018

1.1 Change tRFC Feb.2019

1.2 Add HMAA4GR7AJR4N (1Rx4) Feb.2019

1.3 Update 2Rx4 IDD/IPP Specification May.2019

1.4 Correct IDD/IPP Specification Aug.2019

Rev. 1.4 / Aug.2019 2

• Power Supply: VDD=1.2V (1.14V to 1.26V)

HMAA8GR7AJR4N - WM/XN/XN 64GB 8Gx72 4Gx4(H5ANAG4NAJR)*36 2

HMAA4GR7AJR8N - VK/WM/XN 32GB 4Gx72 2Gx8(H5ANAG8NAJR)*18 2

HMAA4GR7AJR4N - VK/WM/XN 32GB 4Gx72 4Gx4(H5ANAG4NAJR)*18 1

Rev. 1.4 / Aug.2019 3

64GB(2RX4) 32GB(2RX8) 32GB(1RX4)

Bank Address BG Address BG0~BG1 BG0~BG1 BG0~BG1

Bank Address in a BG BA0~BA1 BA0~BA1 BA0~BA1

Row Address A0~A17 A0~A16 A0~A17

Column Address A0~ A9 A0~ A9 A0~ A9

Page size 512B 1KB 512B

Rev. 1.4 / Aug.2019 4

I2C serial bus clock for SPD-TSE and

I2C serial data line for SPD-TSE and

I2C slave address select for SPD-TSE

1. Address A17 is only valid for 16Gbx4 based SDRAMs.

Rev. 1.4 / Aug.2019 5

Symbol Type Function

Rev. 1.4 / Aug.2019 6

Auto-precharge: A10 is sampled during Read/Write commands to determine whether

Rev. 1.4 / Aug.2019 7

Rev. 1.4 / Aug.2019 8

Rev. 1.4 / Aug.2019 9

Rev. 1.4 / Aug.2019 10

RESET_n QRST_n -> RESET_n: All SDRAMs

D28 D30 D32 D34

Back D19 D23 D25

Note: Address, Command and Control lines

Rev. 1.4 / Aug.2019 11

ZQ VSS ZQ VSS ZQ VSS ZQ VSS

DQS8_t DQS_t DQS_t DQS17_t DQS_t DQS_t

Rev. 1.4 / Aug.2019 12

VDDSPD SPD SDA SDA SDA RCD

Rev. 1.4 / Aug.2019 13

BG[1:0] BG[1:0]A -> BG[1:0]: SDRAMs D[4:0], D[13:9]

RESET_n QRST_n -> RESET_n: All SDRAMs

D9 D10 D11 D12 D13 D14 D15 D16 D17

Rev. 1.4 / Aug.2019 14

DQS0_t DQS_t DQS_t

VDDSPD RCD, Serial PD SDA SDA SDA RCD

Rev. 1.4 / Aug.2019 15

BG[1:0] BG[1:0]A -> BG[1:0]: SDRAMs D[4:0], D[17:13]

CK0_t Y0_t -> CK_t: SDRAMs D[8:5], D[12:9]

CK0_c Y0_C -> CK_C: SDRAMs D[8:5], D[12:9]

RESET_n QRST_n -> RESET_n: All SDRAMs

Rev. 1.4 / Aug.2019 16

DQS17_t DQS_t DQS8_t DQS_t

Rev. 1.4 / Aug.2019 17

DRAM Component Operating Temperature Range