Progress In Electromagnetics Research Symposium, Hangzhou, China, March 24-28, 2008 1357

Analysis and Design of Power Generator on Passive RFID

Transponders
Fan Jiang1, 3 , Donghui Guo1, 2, 3 , and L. L. Cheng4
1
EDA Lab, Department of Physics, Xiamen University, Xiamen 361005, China
2
Department of Electronic Engineering, Xiamen University, Xiamen 361005, China
3
Xiamen RichIT Microelectronic Technologies LTD, Xiamen 361005, China
4
Electronic Engineering Department of City University of Hong Kong, Hong Kong, China

Abstract— Rectifier is the essential part of passive RFID transponders. This paper based on
two types of conventional rectifier, analysed several factors which influence the output voltage
and Power Conversion Efficiency (PCE) of the rectifier. From the analysis results of these two
types of rectifier, we proposed a modified version of the rectifier which has high output voltage
and high PCE. Simulation results are also studied and presented in this paper.

1. INTRODUCTION
The radio frequency identification (RFID) system is a system makes use of the bidirectional wireless
communication technology in order to identify the target and then process the relevant data. The
system is mainly formed by two parts, it includes a RFID tag and a reader [1]. According to the
power supply of RFID tag could be either one of the passive, semi-active or active power supplies.
The passive RFID tag, due to its low cost and longer lasting life, hence it is more popular [2].
Passive tag does not consist of any power source in general and the tag obtains power energy
from the electromagnetic waves sending by the RFID reader through the coupling antenna. The
electromagnetic waves after rectification, voltage stabilization then the tag obtain the DC voltage
which maintain the need of the normal operations of the RFID tag and its circuitry. Hence, DC
voltage generation technique is the key technology for passive RFID tag.
The rectifier is the basic part of the DC voltage generation circuit of the RFID tag, the per-
formance of tag relies on it. The main parameters of the rectifier affecting the performance of the
RFID tags are the output voltage Vout and the Power Conversion Efficiency (PCE). The PCE is
defined as the ratio of the output power Pout and the input power Pin of the rectifying circuit. (i.e.,
PCE = Pout /Pin ).
Recently researches have paid attentions to this topic [3–5]. The RFID rectifier discussed in [4]
is using the structure of a half wave rectifier and the PCE is low. The RFID rectifier discussed in [5]
is a self-boosting circuit, with 3.16 V induced voltage on the tag antenna, the output voltage and
PCE could reach 2.38 V and 70.1% respectively. However the structure is more complex and it uses
more chip area. This paper is to discuss the factors that affect the PCE of rectifier, then proposed
a new type of rectifier with the addition of two more MOSFET switches to the conventional circuit
which help to reduce the power loss, hence increase the PCE and output voltage.
In order to explain the circuit design in detail, we first analysis of the functionalities and per-
formances of two conventional rectification circuits, then a modified circuit will be proposed. Sim-
ulations and comparisons of the two types of conventional rectifier and the modified rectifier will
be done.
2. CONVENTIONAL RECTIFICATION CIRCUIT
Figure 1 shows two types of conventional rectification circuits [5], they are mainly suitable for power
source generator of the low and high frequency band passive RFID tag. In Figure 1(a) is the NMOS
gate cross connection bridge rectification circuit and this circuit has two diodes connecting to the
MOSFET, for this reason, the circuit will have a threshold voltage drop V th from the antenna
to the load capacitor. In Figure 1(b), it is using PMOS and NMOS device and has a cross gate
connection structure. Although it solved the threshold voltage drop of the diodes connected to
MOSFET, this circuit has to face another problem, such as the antenna voltage is smaller than the
storage capacitor voltage, the storage charge will feedback to the antenna through the PMOS, thus
it causes low PCE and a bigger voltage swing on the load.
Below is using the structure of the rectification circuit of Figure 1(b) as an example to analysis
the factors affect the PCE. Figure 2 shows the transient equivalent circuit of the (N) MOS device
1358 PIERS Proceedings, Hangzhou, China, March 24-28, 2008

(a) (b)

Figure 1: Two types of conventional rectifier circuit. (a) NMOS gate cross-connection bridge rectifier circuit.
(b) PMOS, NMOS gate cross-connection bridge rectifier circuit.

(i.e., MOS1 model [6]), Dbd, Dbs are the substrate-drain diode and the substrate-source diode
respectively. The rs, rd and rds are the source connection resistor, drain connection resistor and
channel resistor respectively. The cgb, cgs, cgd, cbs and cbd represent the parasitic capacitances,
comparing with the parameters above, rs and rd can be ignored [7]. Such that you can provide the
transient equivalent circuit of the PMOS, NMOS gate cross-connection bridge rectifier circuit as
shown in Figure 3.

Figure 2: The transient equivalent circuit of a MOS device (i.e., MOS1 model).

Figure 3: The transient equivalent circuit of PMOS, NMOS grid cross-connection bridge rectifier circuit.

Based on the working condition of an equivalent circuit as shown in Figure 3, we could find out
the source that creates the power loss of this circuit:
Progress In Electromagnetics Research Symposium, Hangzhou, China, March 24-28, 2008 1359

1. The A1(A2) is a high voltage and A2(A1) is a low voltage, the PMOS1(PMOS2) and NMOS2
(NMOS1) are conductive, the circuit charge up the load capacitor through the conductive
resistor rds. The main power loss is on the conductive resistor.
2. When A1(A2) is a high voltage and A2(A1) is a low voltage, if the voltage of the load capacitor
CL is higher than the voltage on A1(A2), the charge on the load capacitor will go through
the conductive resistor rds and parasitic capacitor then feedback to the antenna and it causes
the power loss.
3. When the threshold of NMOS1(NMOS2) is greater than the conductive voltage of the parasitic
diode Dbd, and the voltage of A1(A2) is smaller than the ground with the conductive voltage
of the parasitic diode Dbd, the current will from the ground and pass through the diode to the
antenna. This causes the current leakage of the substrate and the power conversion efficiency
will drop.
4. PMOS and NMOS transistors are both treated as switches and the current pass through them
will make the parasitic capacitor of the transistor being charged and then discharged, this will
introduce power loss of the transistor.
3. MODIFICATION AND IMPROVEMENT OF THE CONVENTIONAL RECTIFIER
CIRCUIT
According to the above analysis, we may improve the circuit in certain aspects,
1. In order to reduce or eliminate the threshold voltage drop from the antenna to the load
capacitor, it can make use of the PMOS, NMOS gate cross connection bridge rectifier circuit.
2. In order to reduce the power loss on rds it can use a bigger size MOS transistor, but the
bigger size MOS transistor will raise a larger parasitic capacitor. When the MOS transistor
is conductive, the power loss will increase when the capacitor is charged and discharged. For
this reason, the optimization of the size of the MOS transistor is needed.
3. The power loss due the current leakage could be reduced by using the substrate bias [8]
technology.
4. Try hard to suppress the feedback current from the loading capacitor to the antenna.
This paper has shown the modified rectifier circuit as shown in Figure 4 and two more NMOS-
FET switches are added in front of the storage capacitor based on the circuit on Figure 1(b). The
main purpose of these switches is to suppress the current feedback when the voltage on the antenna
is lower than the voltage on CL.

Figure 4: The rectifier circuit after improvement.

4. COMPARISONS OF THE SIMULATION RESULTS

The comparisons of the simulation results of two types of conventional rectifier circuits and the
modified rectifier circuit will be shown below. The rectifier circuit input is complied with the
standard of ISO/IEC 15693-2 and the sine-wave carrier frequency is decided to be 13.56 MHz, the
amplitude is 3.16 V [5]. It is using the same size of the MOS transistors. The load capacitor is
1360 PIERS Proceedings, Hangzhou, China, March 24-28, 2008

200 p and the typical load resistor value is 45 KΩ [3] and CSMC 0.6 µm CMOS layout model is
adopted [9]. Pspice is the tool for modeling the circuits and the simulations was done by the tool
also. The simulation results are shown in Figure 5.

Vout vs Time PCE vs Time

(a)

Vout vs Time PCE vs Time

(b)

Vout vs Time PCE vs Time

(c)

Figure 5: Simulation results for three types of rectifier circuits being discussed. (a) The NMOS gate cross-
connection bridge rectifier circuit Vout ≈ 2.1V and PCE ≈ 56%. (b) The PMOS, NMOS gate cross-connection
bridge rectifier circuit of Vout ≈ 2.4 V and PCE ≈ 3.1%. (c) Modified rectifier circuit of Vout ≈ 2.58 V and
PCE ≈ 74%.

Comparing of the simulation results, the modified rectifier circuit overcomes the threshold volt-
age drop of NMOS gate cross-connection bridge rectifier circuit. Hence, the output voltage can
reach 2.58 V; simultaneously it overcomes the feedback current of the load capacitance of the PMOS,
NMOS gate cross-connection bridge rectifier which causes the instability of the output voltage and
the low efficiency of the power conversion. The PCE of the rectifier circuit hence can reach 74%.
In Figure 5(b), the simulation shows the PCE is very low because of the power loss on the
conductive resistors and the parasitic capacitors due to the feedback current from the load capacitor.
The output voltage Vout and the PCE is limited by the size of the MOS transistor, due to its
channel resistors and the parasitic capacitors.
From Figure 6, follows the change of the size of the MOS transistor, as the size increase, the
channel resistance will become small. The voltage drop on the channel resistor will less, hence this
will increase the output voltage Vout . These three types of rectifier have quite the same results.
For PCE, as the size of the MOS transistor has increased, the power loss on the channel resistance
will become less, however, it will introduce the parasitic capacitance simultaneously. Then, it
will cause the power loss becomes larger. In this case, the channel resistance and the parasitic
capacitance will be the major factors influence the value of PCE. In order to get the highest value
Progress In Electromagnetics Research Symposium, Hangzhou, China, March 24-28, 2008 1361

of PCE, an optimized size of the MOS transistor has to be found. In Figure 6(a) shows that when
the channel width of the MOS transistor is w = 15 µm, PCE = 56.3%. In Figure 6(c) shows that
when the channel width of the MOS transistor is w = 10 µm , PCE = 75.7%. In Figure 6(b), for
PMOS, NMOS gate cross-connection bridge rectifier circuit, due to feedback current from the load
capacitance to the antenna, the power loss due to the parasitic capacitance is higher than the
channel resistance, therefore as the size of the MOS transistor increases, the PCE on the whole will
decrease and the value of PCE is relatively low.

Vout vs MOS width

PEC vs MOS width

(a)

Vout vs MOS width

PEC vs MOS width

(b)

Vout vs MOS width

PEC vs MOS width

(c)

Figure 6: The relation between Output voltage Vout , the Energy Conversion Efficiency and MOS Transistor
size. (a) NMOS gate cross-connection bridge rectifier circuit. (b) PMOS, NMOS gate cross-connection bridge
rectifier circuit. (c) Modified rectifier circuit.

From the simulation results shown above, the performance of the modified rectifier circuit is
higher than the two typical rectifier circuits. It has been significantly improved for Vout and PCE.

5. CONCLUSION
This paper has proposed a new type of rectifier circuit for RFID tag and it has done modification
to the conventional rectifier circuit. It eliminates the threshold voltage drop from the antenna to
the RFID chip such that it increases the output voltage. Moreover, two more MOS switches are
added in order to suppress the feedback current from the RFID to the antenna. This improves
1362 PIERS Proceedings, Hangzhou, China, March 24-28, 2008

the PCE and the maximum PCE can reach 75.7%. The proposed circuit is compliance to the
industrial standard of CMOS technology and is suitable for passive RFID tag chip application with
low frequency and short distance.
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