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    This document outlines the key information students need to know for the ELEC ENG 2EI5 Microelectronic Devices and Circuits I final exam. It provides exam details such as date, time, and calculator policy. It also lists 10 important formulas and concepts covering diodes, MOSFETs, BJTs, and transistor amplifiers that may appear on the exam. Students are responsible for understanding all concepts and should attempt all problems, showing all work.

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    Formula

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    This document outlines the key information students need to know for the ELEC ENG 2EI5 Microelectronic Devices and Circuits I final exam. It provides exam details such as date, time, and calculator policy. It also lists 10 important formulas and concepts covering diodes, MOSFETs, BJTs, and transistor amplifiers that may appear on the exam. Students are responsible for understanding all concepts and should attempt all problems, showing all work.

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    This document outlines the key information students need to know for the ELEC ENG 2EI5 Microelectronic Devices and Circuits I final exam. It provides exam details such as date, time, and calculator policy. It also lists 10 important formulas and concepts covering diodes, MOSFETs, BJTs, and transistor amplifiers that may appear on the exam. Students are responsible for understanding all concepts and should attempt all problems, showing all work.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    93 views4 pages

    Formula

    Uploaded by

    margaret_navaei
    This document outlines the key information students need to know for the ELEC ENG 2EI5 Microelectronic Devices and Circuits I final exam. It provides exam details such as date, time, and calculator policy. It also lists 10 important formulas and concepts covering diodes, MOSFETs, BJTs, and transistor amplifiers that may appear on the exam. Students are responsible for understanding all concepts and should attempt all problems, showing all work.

    Copyright:

    Attribution Non-Commercial (BY-NC)
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    Download as pdf or txt
    of 4

    ELEC ENG 2EI5 Microelectronic Devices and Circuits I Winter 2008 Final Exam date TBD

    INSTRUCTOR: Yaser M. Haddara Ext. 24968 Email: [email protected]

    EXAMINATION TIME 3 HOURS CALCULATOR Use of Casio FX-991 calculator only is allowed THIS EXAMINATION PAPER INCLUDES # PAGES AND 9 QUESTIONS. YOU ARE RESPONSIBLE FOR ENSURING THAT YOUR COPY OF THE PAPER IS COMPLETE. BRING ANY DISCREPANCY TO THE ATTENTION OF YOUR INVIGILATOR. ATTEMPT ALL PROBLEMS. ALL PROBLEMS HAVE EQUAL WEIGHT. SHOW ALL WORK. Correct answers without appropriate justification or reasoning may receive NO CREDIT. You may use the following formulas in your work: 1. Diode model: v i D = I S exp D VT

    i v D = VT ln D + 1 IS

    VT = 25 mV at room temperature.

    2. n-MOSFET model: Region of Conditions Operation vGS VTN Cutoff vGS VTN Linear 0 v DS (vGS VTN )
    Saturation vGS VTN v DS (vGS VTN ) 0

    i-v relationship i DS = 0
    i DS
    2 v DS = K n (vGS VTN )v DS 2 K 2 = n (vGS VTN ) (1 + v DS ) 2

    i DS

    ' W Kn = Kn L For DC analysis, unless explicitly specified otherwise, assume = 0

    3. p-MOSFET model: Region of Conditions Operation v SG VTP Cutoff


    Linear Saturation

    i-v relationship

    i SD = 0
    2 v SD i SD = K p (v SG + VTP )v SD 2 K 2 iSD = p ( vSG + VTP ) (1 + vSD ) 2

    0 v SD (v SG + VTP )
    v SG VTP v SD (v SG + VTP ) 0

    v SG VTP

    ' W Kp = Kp L For DC analysis, unless explicitly specified otherwise, assume = 0

    4. NPN BJT: Region of operation Cutoff

    Assume . . . i B = iC = 0

    v BE

    Check . . . < V BEon

    v BC < V BCon

    Saturation Linear

    v BE = V BEon v BC = V BCon v BE = V BEon iC = i B

    i B , iC 0 iC i B iB 0 v BC < V BCon

    Unless otherwise stated, assume VBEon = 0.7V, VBCon = 0.5V, VA = 5. PNP BJT: Region of operation Cutoff

    Assume . . . i B = iC = 0

    v EB

    Check . . . < V EBon

    vCB < V CBon

    Saturation Linear

    v EB = V EBon vCB = V CBon v EB = V EBon iC = i B

    i B , iC 0 iC i B iB 0 vCB < V CBon

    Unless otherwise stated, assume VEBon = 0.7V, VCBon = 0.5V, VA =

    6. MOSFET Small Signal Model Parameters:


    2 I DS gm = = 2 KI DS (1 + V DS ) 2 KI DS (VGS VT )

    1 + V DS ro = I DS

    Valid for v gs 0.2(V GS VT )

    here VT is the threshold voltage of the MOSFET

    (For p-MOSFET replace IDS with ISD, VDS with VSD, VGS with VSG) 7. BJT Small Signal Model Parameters:
    gm = IC VT

    r =

    gm

    re =

    gm

    ro =

    V A + V CE IC

    (also recall =

    +1

    here, VT is the thermal voltage, 25 mV at room temperature Valid for vbe 0.2VT (For PNP replace VCE with VEC)

    8. Reference CMOS Inverter Propagation Delay: For the reference inverter with VDD = +5V, VTN = VTP = 1V, and load capacitance C, Vref = VDD/2 we get:
    W = 2 /1 L n Kn = K p = K W = 5 /1 L p

    PHL = PLH = 0.322

    C K

    9. MOSFET Single Stage Transistors Common Source Circuit

    Common Gate RL RS

    Common Drain

    vin

    Av =

    vo vin

    gm (R L || ro ) ro 0.2(V GS VT )

    + gm (R L || ro ) 1 + gm R S

    gm R L 1 1 + gm R L

    Rin (looking into FET input) Rout (looking into FET output) Allowed input signal range
    10. BJT Single Stage Transistors

    gm

    1 gm

    ro (1 + gm RS ) 0.2(V GS VT )(1 + gm RS )

    0.2(V GS VT )(1 + gm R L )

    Common Emitter

    Circuit vin

    Common Base RL RS

    Common Collector

    Av =

    vo vin

    gm (R L || ro )

    r RS + r

    + gm (R L || ro ) 1 + gm R S

    gm R L Rin 1 1 + gm R L Rin + RS

    Rin (looking into BJT input) Rout (looking into BJT output) Allowed input signal range

    r ro
    0.2VT

    gm

    r (1 + gm R L )

    ro (1 + gm RS ) 0.2VT (1 + gm RS )

    gm

    0.2VT (1 + gm R L )

    RS +1

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