VIPER - N18E LA-J521PR02 - X01 - Final

A B C D E
Layout Dell logo
1 1
COPYRIGHT 2015
ALL RIGHT RESERVED
REV: X00
PWB: XXXXX
DATE: 1450-06
ZZZ1
PCB 2VR LA-J521P REV0 M/B NVIDIA N18E S

DAB0005V000
PCB@
Dell/Compal Confidential
2
Schematic Document 2
(Viper Comet Lake H with nVIDIA N18E)

DVT1
2019-09-24
Rev: 0.2 (X01)
3 BOM Structure 3
PCB@ : PCB PN
@ : Nopop Component
EMI@,ESD@,RF@ : EMI/ESD/RF part
CONN@ : Connector Component
@EMI@,@ESD@,@RF@ : EMI, ESD and RF Un-POP Component
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-J521P
Date: Tuesday, September 24, 2019 Sheet 1 of 115
A B C D E
A B C D E
VRAM*8 P.35-36
GDDR6 8GB
256Mx32*8=8GB
nVIDIA GPU GB4B-256
DP 1.4 Max-P:
Fan control
mDP
Conn. P.39 IFPE N18E-G0
N18E-G1 NCT7718W
N18E-G2 W83L771AWG-2
HDMI HDMI2.0 N18E-G3
Conn. Max-Q :
1 1
P.40 IFPC PEGx8

N18E-G3 Port 8~15
Intel CPU
Memory Bus DDR4 on Board 32GB
DP 1.4 P.23-26
Comet Lake-H
P.27-34 Dual Channel
IFPD 1.2V DDR4
DDR4 x16 DDR4 x16 DDR4 x16 DDR4 x16
8+2
DP 1.4x4 DP 1.4x4 (2666) MHz
IFPB IFPA
BGA 1440
eDP DP 1.2 MUX eDP 1.2 x4
DDR4 x16 DDR4 x16 DDR4 x16 DDR4 x16
Conn. P.38 PS8331B P.38
CIO/USB3.1
Thunderbolt For Debug 45W/65W
Titan Ridge SP
Power LED
USB3.1 VBUS/CC I2C2 I2C DDI 1 x4 P.63
BOM
TypeC
PD
TLC59116F AlienFX
P.42 option
Conn.
USB2
CCG5C PEGx4 P.38
P.50 Port 4~7 P.6-13

P.63
TRON P.63
@
P.44 TRON/B
I2C1 UART DMI x 4
ELC Controller
2 PCIe re-driver 2
STM32F070CB
I2C DS80PCI402 P.74
To EC USB2.0 port4
Caldera
USB3.0 port3 P.62
Conn.
USB2.0 port3 Digital camera
P.74 USB2.0 port7
(with digital MIC) P.38
PCIE x4
Port 17~20 USB3.1 port4
USB Type-A *1 , left side P.73
USB2.0 port11
USB2.0 port1
USB3.1(Gen1) with power share IO/B 1
G-Sensor USB3.1 por5

LSM6DSLUSTR ISH_I2C0 USB2.0 port2
USB Type-A *2, right side
USB3.1(Gen1)
FUNCTION/B
P.65 USB3.1 port6 IO/B 2
P.73
PCH-H
USB2.0 port8
BGA874
USB3.1 port2 SD5.1
IO/B 1
P.73
RJ45
Conn.
2.5 Gigabit LAN
Killer E2600/E3100
PCIE port15
USB2.0 port5 Card reader
RTS5330
uSD
3
IO/B 2
WLAN+BT PCIE port16
USB2.0 port14
USB2.0 port9
Tobii (15&17) P.65
3
P.73 Kill 1650W SIP
USB2.0 port10
Per key /4 Zone / Mechanical KB MCU/B P.64
uSIM
Conn.
SSD3 M.2 Key-B 2230 PCIEx2
PCIe SSD/WWAN Port 13~14
SSD2 M.2 Key-M 2280 PCIEx4

PCIe SSD P.68 Port 21~24 digital MIC
Audio codec
SSD1 M.2 Key-M 2280 SATAx1/PCIEx4

Port 1/Port9~12
HD Audio Realtek
ALC3281
Headphone/MIC Global headset
PCIe/SATA SSD P.68 combo JACK
AMP
SPI ROM SPI P.14-20
DC in
ALC1309
128Mbit P.15
Battery
dGPU
1.00V
Core I2C ESPI BUS
SPI ROM IO/B 1
PWM P.73
3V/5V Charger Touch pad KC3810

64Mbit P.15 P.63 Speaker Speaker
4 4
2.5V FAN P.77
P.59
ENE KB9542
I2C
System CPU dGPU
PS2 P.58 Thermal Sensor P.77
F75305M
1.2V Vcore 1.35V

Block Diagram
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.2
A B C D E
A
Board ID Table for AD channel

Vcc 3.3V +/- 1% PCH-H CM246
Ra 100K +/- 1% HSIO USB3.1 PCIe SATA3 Function USB2 Function
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3
0 0 0.000V 0.000V 0.300V 0x00 - 0x13 0 1 1 JUSB3 left side
1 12K +/- 1% 0.347V 0.354V 0.360V 0x14 - 0x1E 1 2 Card reader 2 JIO right side USB1
2 15K +/- 1% 0.423V 0.430V 0.438V 0x1F - 0x25
3 20K +/- 1% 0.541V 0.550V 0.559V 0x26 - 0x30 2 3 Caldera 3 Caldera
4 27K +/- 1% 0.691V 0.702V 0.713V 0x31 - 0x3A 3 4 JUSB3 left side 4 ELC
5 33K +/- 1% 0.807V 0.819V 0.831V 0x3B - 0x45
6 43K +/- 1% 0.978V 0.992V 1.006V 0x46 - 0x54 4 5 JIO right side USB2 5 Card reader
7 56K +/- 1% 1.169V 1.185V 1.200V 0x55 - 0x64 5 6 JIO right side USB1 6 WWAN
8 75K +/- 1% 1.398V 1.414V 1.430V 0x65 - 0x76
9 100K +/- 1% 1.634V 1.650V 1.667V 0x77 - 0x87 6 7 1 7 Camera
10 130K +/- 1% 1.849V 1.865V 1.881V 0x88 - 0x96 7 8 2 8 JIO right side USB2
11 160K +/- 1% 2.015V 2.031V 2.046V 0x97 - 0xA4
12 200K +/- 1% 2.185V 2.200V 2.215V 0xA5 - 0xAF 8 9 3 9 Tobii
13 240K +/- 1% 2.316V 2.329V 2.343V 0xB0 - 0xB7 9 10 4 10 Per Key
14 270K +/- 1% 2.395V 2.408V 2.421V 0xB8 - 0xBF
15 330K +/- 1% 2.521V 2.533V 2.544V 0xC0 - 0xC9 10 5 11 Thunderbolt PD
16 430K +/- 1% 2.667V 2.677V 2.687V 0xCA - 0xD4 11 6 12 Tron light
17 560K +/- 1% 2.791V 2.800V 2.808V 0xD5 - 0xDD
18 750K +/- 1% 2.905V 2.912V 2.919V 0xDE - 0xF0 12 7 13
19 1.2M +/- 1% 3.020V 3.046V 3.067V 0xF1 - 0xFF 13 8 14 Bluetooth
PCIE CLK table Board ID table 14 9
PCIE CLK PCB Revision NV AMD
0 GPU N18E PCB Revision 15 10 JSSD1 , 2280
N18P SATA/PCIe x4
1 SSD2 2Stage 1Stage 16 11 0a
2 SSD3/WWAN 0 4 8 12 EVT-1
3 TBT 1 5 9 13 DVT-1 17 12 1a Symbol Note :
4 LAN 2 6 10 14 DVT-2 18 13 0b WWAN
JSSD3
1 1
5 WLAN 3 7 11 15 Pilot
6 caldera 19 14 1b PCIE X2 Digital Ground
7 SSD1 20 15 2 LAN
Voltage Rails 21 16 3 WLAN
Analog Ground
Power Plane Description S0 S3 S4 / S5
VIN Adapter power supply N/A N/A N/A 22 17 4
BATT+ Battery power supply N/A N/A N/A 23 18 5
+19VB AC or battery power rail for power circuit N/A N/A N/A TBT PCIE X4
+VCC_CORE Core voltage for CPU ON OFF OFF 24 19
+VCC_GT Sliced graphics power rail ON OFF OFF 25 20
+0.6VS_VTT DDR +0.6VS power rail for DDR terminator ON OFF OFF
+1VALW System +1VALW power rail ON ON ON* 26 21
+1V_PRIM System +1VALW power rail ON ON ON* 27 22
+VCCIO +1.0VS IO power rail ON OFF OFF JSSD2 , 2280
+VGA_PCIE +1.0VS power rail for GPU ON OFF OFF 28 23 PCIe x4
+MEM_GFX +1.5VS power rail for GPU ON OFF OFF 29 24
+1.2V_VDDQ DDR-IV +1.2V power rail ON ON OFF
+1VS_VCCST +1.0V power rail for CPU ON ON OFF
+1VS_VCCSTG +1.0VS power rail for CPU ON OFF OFF
+3VALW System +3VALW always on power rail ON ON ON*
+3VLP +19VB to +3VLP power rail for suspend power ON ON ON
+3VALW_DSW +3VALW power for PCH DSW rails ON ON ON*
+3V_LAN +3VALW power for LAN power rails ON ON ON*
+3VS System +3VS power rail ON OFF OFF
+1.8VALW +1.8VALW power rail for PCH ON OFF OFF
+3VGS +3VS power rail for GPU ON OFF OFF
+5VALW System +5VALW power rail ON ON ON*
+5VS System +5VS power rail ON OFF OFF Security Classification Compal Secret Data Compal Electronics, Inc.
+3VL_RTC RTC power ON ON ON Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title
+VCC_SA System Agent power rail ON OFF OFF THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-J521P 0.2

A
5 4 3 2 1
IMVP_VR_ON SIC632CDT1GE3
ISL95855HRTZ +VCC_CORE
(PU502)
(PU500) (PU503)
(PU504)
SIC632CDT1GE3
+VCCGT
(PU507)
(PU510)
SIC531CDT1GE3
+VCCSA
(PU511)
D D
8880mA (PJP200 PJP201) APE8937GN2

+1.2VP +1.2V_DDR +1.2V_VCCPLL_OC
SYSON
(UZ21)
RT8207MZQW
(PU200) 1470mA (PJP202)
+0.6VSP +0.6VS JDIMM1/2
PCH_PW R_EN TPS51212DSCR 9410mA (PJP300 PJP302) SYSON TPS22961

ADAPTER +1VALWP +1VALW +VCCST
(PU300) (U19)
SUSP# TPS22961
+VCCSTG
(U20)
NVVDD_EN NCP81278 58000mA
(PU6100) +NVVDD1
CHARGER
BQ24780SRUYR NVVDD2_EN 28000mA
NCP81278
(PU700)
B+ (PU6200) +NVVDD2
F75305M
BQ24780S (U2407)
SUSP# SY8286RAC 3740mA (PJP505)
+VCCIOP +VCCIO
(PU509) PI6CEQ20200LIEX
(UM4)
BATTERY
+1.0VS_VGA_PGOOD
DS80PCI402
FBVDD/Q_EN 18200mA
(UM8)
RT8812AGQW (PJP8201 PJP8202)
C +1.35VS_VGAP +1.35VS_VGA C
(PU8200) (R2)
+3VS_TOUCH (JPWR)
RM34 +3VS_WLAN_NGFF NGFF Conn.

(JWLAN)
Fuse +INV_PWR_SRC +3VS
KB9022QD
+EC_VCCA (RV81) JEDP Conn.
(UE5) +VDD_TOUCH
(JEDP)
KC3810
(UE6)
3/5V_B+ TPS51225CRUKR 10010mA (PJP102) PCH_PW R_EN SY6288C20AAC (J6)
+3VALWP +3VALW +3VALW_PCH +3V_PCH
(PU100) (U18)
AP2337SA-7
+3VS_DP JDP Conn.
SUSP#
(UV18)
AOZ1331 (J5)
(U17)
SKY-H-PCH
EN_W OL# (UH1H)
SY6288D20AAC +LAN_IO E2400-BL3A-R
(UL2) (UL1)
SODIMM Conn.
(JDIMM1/2)
RT53 +3VALW_PD
3V_F383_ON
SN1508014
SY6288C20AAC (UT4)
+3.3V_ELC
(UE9)
(RA5)
(RT95) +3.3V_1.8V_DVDD_IO ALC3266
+3VS_TBT ALPINE-RIDGE ALC1309
(UT1)
(RA11) (UA1, UA4)
B (RT97) +3.3V_1.8V_DVDD B
+3VS_TBT_SX
PCH_ENVDD JEDP Conn.

SY6288C20AAC +LCDVDD 3V3_SYS_EN SY6288D20AAC
(JEDP) +3V3_SYS
(UV17) (UG14)
SUSP#
TPS22961 NGFF Conn.
+3VS_SSD
(U16) (JSSD1/2/3)
(PJP1301) SY8003DFC (PJP1300)

+2.5V_MEMP +2.5V_MEM
(PU1300)
3000 mA
10770mA (PJ800) SY8286RAC (PJP801)
3/5V_B+ TPS51225CRUKR +5VALWP +1.05VS_VGAP SI3456DDV
PEX_VDD_EN
(PU800) +PEX_VDD +5VS_TP_LED JTP Conn.
(PU100) (PJP100 PJP101) (Q2409)
+5VALW
USB_PW R_EN SY6288C20AAC
+5V_USB_PWR2
(UU3) APL3517AI
+5VS +HDMI_5V_OUT JHDMI Conn.
(UV22)
PWRSHARE_EN_EC# TPS2546RTER
+5V_USB_PWR1
(UU1)
USB_PW R_EN
(RA3)
TPS25810RVCR +5V_PVDD ALC3266
+5V_USBC_VBUS ALC1309
(UU7)
PQ3 B+_BIAS LA21 +PVDD
(RA8) (UA1, UA4)
+5VA
SUSP# AOZ1331
5VS_GATE (U17)
ALC1309 RT56 +5VALW _PD UT4,PD +TBTA_VBUS
A (UA4) A
1V8_AON_EN
1V8_EN RT8061AZQW (PJP803)
+1.8VGSP +1.8VALW +1V8_AON N17E-G1 GB4-256
1V8_EN
(PU802) AOZ1331
(UG9)
(UG12)
+1V8_AON +1V8_MAIN N17E-G1 GB4-256
1V8_MAIN_EN (UG9)
ALC3266
ALC1309
LA4
+CODEC_AVDD2
(UA1, UA4)
Power Rail
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
5 4 3 2 1
5 4 3 2 1
+3VS PR802
+3VS PR8204
1V8_EN +1.8VALW
15 PU802 G0 +1.35VS_VGA_PGOOD
+5VALW +1.35VS_VGA
G6A +1.0VS_VGA_PGOOD PU8200
PR14 FBVDD/Q_EN G7
16 PR8212
20K RT8812A
DG5
PQ3 B+_BIAS GPU_GC6_FB_EN FBVDD/Q_EN
SI3457CDV PR8216
PMOS +1.0VS_VGA_PGOOD
15
D
H_VCCST_PWRGD SOC D
123 RH154 H13
CPU1 DG5 +3VS PR821
OVERT#
10
+1.0VS_VGA_PGOOD
Will Modify 9 G6A
DGPU_PWR_EN ME_SUS_PWR_ACK 11 G5A NVVDD2_PGOOD
1 71 NVVDD1_PGOOD +PEX_VDD
BD19 DGPU_PWROK PR801 PU800
AJ44 SY8286 G6
ACIN1_AV_IN 7a AC_PRESENT PEX_VDD_EN
ACIN 110 110 BB15 17 PR823
NVVDD2_PGOOD
DG6 G5A
POK PM_SLP_SUS# 8
38 BB13 AJ39 13
NVVDD_EN NVVDD2_EN
PR6230 PU6200
+NVVDD2
GPU_GC6_FB_EN NCP81278 G5
9 AW27 BB5 G4A NVVDD1_PGOOD 1.8VS_PGOOD
PBTN_OUT# PR6201
106 AT13
ACIN G0A
12 @ +3V3_SYS
PM_SLP_S5# UE10 Will Modify PR6107
A5 B6 14 BA13 DG3 OVERT#
A1
7
14
KC3810
AC VIN 5 A2 +3VALW PM_SLP_S3# NVVDD1_PGOOD
6 AW15 G8 DG3 G4A
MODE B+ PU100 +5VALW
PU700
BQ24780SRUYR TPS51225 13
CHARGER CRUKR SUSACK# 9 +1.35VS_VGA_PGOOD NVVDD1_EN
BATT+ 97 BB19 NVVDD_EN
+3VLP,VL UE5 19 PR6131 PU6100 +NVVDD1
A3 B3 EC9022QD PCH G4
18 SYS_PWROK UH1 CLKREQ#_GPU PEX_CLKREQ#
G3 +3V3_SYS 1.8VS_PGOOD
PR6103
NCP81278
DC 74 AY1
MODE BC24 QG5 BL26 G0A
B1 @
B2 VCOUT0_PH# 7
BATT+ PQ703 PCH_DPWROK Will Modify
104 127 AV11 GPU
NMOS
C UG9 3V3_SYS_EN +3V3_SYS C
10 20 UG14 G3
A4 B5 EC_RSMRST#
100 BA11 10K
G2 +1V8_MAIN SY6288
112 PG515
EC_ON
19
PCIRST# TC7SH08FU PCH_PLTRST#
A6 B4 13 4 BB27 1V8_MAIN_EN +1V8_MAIN
SW1 (UH3) G2
ON/OFFBTN# G9 1V8_AON_EN UG12
+3VALW +1VALWP_PGOOD 22 +1V8_AON
PR301 DGPU_HOLD_RST# SYS_PEX_RST_MON#
BE2 G1
114 AL36
PCH_PWR_EN 9 TPS512212 +1VALW
107 UG10 G10 1V8_MAIN_EN G1A
3 (PU300) BB27 PCH_PLTRST# BE1
SY6288C20AAC +3V_PCH
(U18) +1V8_AON G1
17
PCH_PWROK
32 AW11
+1VALWP_PGOOD
122 KB_RST#
2 AT17
73 PM_SLP_S4# BD15
13 SM_PG_CTRL G0 G1 G2 G4 G5 G6 G7
SY8003DFC +2.5V_MEMP BT13
7 (PU1300)
UC1 GPU power on
121 101 116 95 15
SYSON TPS22961DNYR +VCCST

Compal Net
(U19) 13b
15
13a G1
+1.8VS_AON
VR_PWRGD
IMVP_VR_ON
SYSON 8 +1.2VP BH29

B RT8207MZQW BH31 G2 B
SM_PG_CTRL
(PU201) +1.8VS_MAIN Compal Net
15 7 +0.6VSP BH32
15a
G1
SVID Bus
14a +3V3_SYS G3 +1.8VS_AON
SUSP# AOZ1331 +3VS

16 (U17)
+NVVDD1 G4 G2
+5VS, +3VS
+1.8VS_MAIN
SUSP# SY8286RAC +NVVDD2 G5

(PU509)
+VCCIO G3
+3V3_SYS
+PEX_VDD G6
SUSP# APE8937GN2
(UZ21)
+1.2V_VCCPLL_OC 43,44,45
+1.35VS_VGA G7 +NVVDD1 G4
SVID Bus
SUSP# TPS22961DNYR
(U20)
+VCCSTG G5
+NVVDD2
IMVP_VR_ON +VCC_CORE
PR523 48 PCH_PLTRST# +PEX_VDD G6
ISL95855 SIC632
(PU500) (PU502/503/504) UM3 CDRA_RST#
47 CALDERA_RST# 22
16 TC7SH08FU +1.35VS_VGA G7
for power down sequence VR_PWRGD

16
SIC632
+VCCGT JCDRA
(PU507/510) UE6
CALDERA_ PWRGD
Caldera
+3VS KC3810 15 2 GPU power off G7 G6 G5 G4
A @ Q7A IMVP_VR_ON PR515 A
G3
PM_SLP_S3# @ Q8A @ Q7B H_VCCST_PWRGD +VCCSA DGPU_PWROK
SIC531 19
(PU511) G2
@ Q8B SUSP#
G1
PM_SLP_S4# DMN65D8LDW SYSON
(Q9) @

Power Sequence
5 4 3 2 1
5 4 3 2 1
UC1
UC1C
CL8070104399007 QTJ0 R0 2.8G S E25 B25
SA0000D3G0L D25 PEG_RXP_0 PEG_TXP_0 A25
QTJ0@ PEG_RXN_0 PEG_TXN_0
E24 B24
UC1 F24 PEG_RXP_1 PEG_TXP_1 C24
PEG_RXN_1 PEG_TXN_1
E23 B23
D
D23 PEG_RXP_2 PEG_TXP_2 A23 D
PEG_RXN_2 PEG_TXN_2
E22 B22
F22 PEG_RXP_3 PEG_TXP_3 C22
CL8070104398806 QTJ1 R0 2.1G S PEG_RXN_3 PEG_TXN_3
SA0000D3I0L
QTJ1@ E21 B21 PEG_CTX_GRX_P11 CC24 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_P11 D21 PEG_RXP_4 PEG_TXP_4 A21 PEG_CTX_GRX_N11 PEG_CTX_C_GRX_P11 <74>
CC12 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_N11 PEG_RXN_4 PEG_TXN_4 PEG_CTX_C_GRX_N11 <74>
UC1 E20 B20 PEG_CTX_GRX_P10 CC23 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_P10 PEG_RXP_5 PEG_TXP_5 PEG_CTX_GRX_N10 PEG_CTX_C_GRX_P10 <74>
F20 C20 CC11 1 2 0.22U_0201_6.3V
Caldera TX Caldera RX
E19 B19 PEG_CTX_GRX_P9 CC22 1 2 0.22U_0201_6.3V
D19 A19 CC10 1 2 0.22U_0201_6.3V
E18 B18 PEG_CTX_GRX_P8 CC21 1 2 0.22U_0201_6.3V
S IC A31 CL8070104398908 QTJ2 R0 2.4G S <74> PEG_CRX_GTX_P8 PEG_RXP_7 PEG_TXP_7 PEG_CTX_GRX_N8 PEG_CTX_C_GRX_P8 <74>
SA0000D3N0L F18 C18 CC9 1 2 0.22U_0201_6.3V
QTJ2@
D17 A17 PEG_CTX_GRX_P7 CC20 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_P7 E17 PEG_RXP_8 PEG_TXP_8 B17 PEG_CTX_GRX_N7 PEG_CTX_C_GRX_P7 <27>
CC8 1 2 0.22U_0201_6.3V
F16 C16 PEG_CTX_GRX_P6 CC19 1 2 0.22U_0201_6.3V
CC7 1 2 0.22U_0201_6.3V
E15 B15 CC6 1 2 0.22U_0201_6.3V
GPU TX
E14 B14 CC5 1 2 0.22U_0201_6.3V
GPU RX
E13 B13 CC4 1 2 0.22U_0201_6.3V
CC3 1 2 0.22U_0201_6.3V
CC2 1 2 0.22U_0201_6.3V
C C
E10 B10 CC1 1 2 0.22U_0201_6.3V
1 2 PEG_RCOMP G2
+VCCIO PEG_RCOMP
RC2
24.9_0402_1%
D8 B8
<17> DMI_CRX_PTX_P0 E8 DMI_RXP_0 DMI_TXP_0 A8 DMI_CTX_PRX_P0 <17>
<17> DMI_CRX_PTX_N0 DMI_RXN_0 DMI_TXN_0 DMI_CTX_PRX_N0 <17>
E6 C6
<17> DMI_CRX_PTX_P1 F6 DMI_RXP_1 DMI_TXP_1 B6 DMI_CTX_PRX_P1 <17>
D5 B5
<17> DMI_CRX_PTX_P2 DMI_RXP_2 DMI_TXP_2 DMI_CTX_PRX_P2 <17>
E5 A5
J8 D4
<17> DMI_CRX_PTX_P3 DMI_RXP_3 DMI_TXP_3 DMI_CTX_PRX_P3 <17>
J9 B4
CML-H_BGA1440
3 OF 13
@
UC1D
K36 D29
<42> CPU_DP1_P0 DDI1_TXP_0 EDP_TXP_0 EDP_TXP0 <38>
K37 E29
B <42> CPU_DP1_N0 DDI1_TXN_0 EDP_TXN_0 EDP_TXN0 <38> B
J35 F28
<42> CPU_DP1_P1 J34 DDI1_TXP_1 EDP_TXP_1 E28 EDP_TXP1 <38>
<42> CPU_DP1_N1 DDI1_TXN_1 EDP_TXN_1 EDP_TXN1 <38>
H37 A29
<42> CPU_DP1_P2 H36 DDI1_TXP_2 EDP_TXP_2 B29 EDP_TXP2 <38>
FOR TBT DDI1 <42>
<42>
CPU_DP1_N2
CPU_DP1_P3
J37
J38
DDI1_TXN_2
DDI1_TXP_3
EDP_TXN_2
EDP_TXP_3
C28
B28
EDP_TXN2
EDP_TXP3
<38>
<38>
<42> CPU_DP1_N3 DDI1_TXN_3 EDP_TXN_3 EDP_TXN3 <38>
D27 C26
<42> CPU_DP1_AUXP E27 DDI1_AUXP EDP_AUXP B26 EDP_AUXP <38>
<42> CPU_DP1_AUXN DDI1_AUXN EDP_AUXN EDP_AUXN <38>
H34
H33 DDI2_TXP_0
F37 DDI2_TXN_0 A33 1
G38 DDI2_TXP_1 EDP_DISP_UTIL PAD~D @ T194 +VCCIO
F34 DDI2_TXN_1
F35 DDI2_TXP_2 D37 EDP_RCOMP 1 2
E37 DDI2_TXN_2 DISP_RCOMP RC30 24.9_0201_1%
E36 DDI2_TXP_3
DDI2_TXN_3
F26
DDI2_AUXP
Net : EDP_RCOMP
E26
DDI2_AUXN Trace Width/Space: 15 mil/ 20 mil
C34
D34 DDI3_TXP_0 Max Trace Length: 600 mil
B36 DDI3_TXN_0
B34 DDI3_TXP_1
F33 DDI3_TXN_1
E33 DDI3_TXP_2
C33 DDI3_TXN_2
B33 DDI3_TXP_3
DDI3_TXN_3 G27
PROC_AUDIO_CLK CPU_DISPA_BCLK <16>
A27 G25
B27 DDI3_AUXP PROC_AUDIO_SDI G29 CPU_DISPA_SDI_R 1 2 CPU_DISPA_SDO <16>
DDI3_AUXN PROC_AUDIO_SDO CPU_DISPA_SDI <16>
4 of 13 RC66
CML-H_BGA1440 20_0201_5%
A @ A

CPU(1/7) DMI,PEG,DDI,EDP
5 4 3 2 1
5 4 3 2 1
D D
+3V_PCH
RC9 1 2 1.5K_0201_5% XDP_SPI_SI
PCH_JTAG_TCK
<9,16> PCH_JTAG_TCK T278 PAD~D @
<9,20> CPU_XDP_TRST# T279 PAD~D @
+1VALW <9,16> XDP_TMS T280 PAD~D @
<9,16> XDP_TDI XDP_TCK T281 PAD~D @
<16> XDP_TCK T282 PAD~D @
C XDP_ITP_PMODE <9,16> XDP_TDO T283 PAD~D @ C
RC353 1 @ 2 1K_0201_5%
<9> CFG0 T284 PAD~D @
<9> CFG1 T285 PAD~D @
<9> CFG2 T286 PAD~D @
<9> CFG3 T287 PAD~D @
<9> CFG4 T288 PAD~D @
<9> CFG5 T289 PAD~D @
<9> CFG6 T290 PAD~D @
PCH_JTAG_TCK <9> CFG7 T291 PAD~D @
RC35 2 CMC@ 1 51_0201_5%
2 1 51_0201_5% XDP_TCK <9> CFG17 T292 PAD~D @

RC348 @
<9> CFG16 T293 PAD~D @
RH497 1 @ 2 51_0201_5% CPU_XDP_TRST#
<9> CFG8 T294 PAD~D @
<9> CFG9 T295 PAD~D @
<9> CFG10 T296 PAD~D @
<9> CFG11 T297 PAD~D @
<9> CFG12 T298 PAD~D @
<9> CFG13 T299 PAD~D @
<9> CFG14 T300 PAD~D @
<9> CFG15 T301 PAD~D @
<9> CFG19 T302 PAD~D @

<9> CFG18 T303 PAD~D @
<9,20> XDP_PREQ# T304 PAD~D @

<9,20> XDP_PRDY# T305 PAD~D @
<15> XDP_SPI_SI T306 PAD~D @

<16> XDP_ITP_PMODE T307 PAD~D @
B B
1K_0201_5% 2 @ 1 RC355 XDP_HOOK0
<16,58> EC_RSMRST# T308 PAD~D @
XDP_SPI_IO2 RC354 1 @ 2 1K_0201_5%

@ PAD~D T309 PCH_SPI_0_D2 <15>
SYS_RESET#
@ PAD~D T310 SYS_RESET# <16>
A A

CMC Conn
0.2
5 4 3 2 1
5 4 3 2 1
D D
UC1A UC1B
DDR CHANNEL A DDR CHANNEL B
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4 DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_A_D0 BR6 AG1 DDR_A_D16 BT11 AM9
DDR_A_D1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR_A_CLK0 <23,24> DDR_A_D17 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK0 <25,26>
BT6 AG2 BR11 AN9
DDR_A_D2 BP3 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 AK2 DDR_A_CLK#0 <23,24> DDR_A_D18 BT9 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 AM7 DDR_B_CLK#0 <25,26>
<23,24> DDR_A_D[0..63] DDR_A_D3 BR3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 AK1 DDR_A_D19 BR8 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 AM8
<23,24> DDR_A_MA[0..16] DDR_A_D4 BN5 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 AL3 DDR_A_D20 BP11 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 AM11
<23,24> DDR_A_DQS#[0..7] DDR_A_D5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3 DDR_A_D21 BN11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM10
<23,24> DDR_A_DQS[0..7] DDR_A_D6 BP2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 AL2 DDR_A_D22 BP8 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2 AJ10
DDR_A_D7 BN3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 AL1 DDR_A_D23 BN8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ11
DDR_A_D8 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3 DDR_A_D24 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3
DDR_A_D9 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_A_D25 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8
DDR_A_D10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE0 <23,24> DDR_A_D26 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE0 <25,26>
BL2 AT2 BL8 AT10
DDR_A_D11 BM1 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 AT3 DDR_A_D27 BJ8 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 AT7
<25,26> DDR_B_D[0..63] DDR_A_D12 BK4 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT5 DDR_A_D28 BJ11 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 AT11
<25,26> DDR_B_MA[0..16] DDR_A_D13 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3 DDR_A_D29 BJ10 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3
<25,26> DDR_B_DQS#[0..7] DDR_A_D14 BK1 DDR0_DQ_13/DDR0_DQ_13 AD5 DDR_A_D30 BL7 DDR1_DQ_13/DDR0_DQ_29 AF11
<25,26> DDR_B_DQS[0..7] DDR_A_D15 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#0 <23,24> DDR_A_D31 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 DDR_B_CS#0 <25,26>
BK2 AE2 BJ7 AE7
DDR_A_D32 BG4 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 AD2 DDR_A_D48 BG11 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 AF10
DDR_A_D33 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5 DDR_A_D49 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10
DDR_A_D34 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3 DDR_A_D50 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3
DDR_A_D35 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_A_D51 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7
DDR_A_D36 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT0 <23,24> DDR_A_D52 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 DDR_B_ODT0 <25,26>
BG2 AE4 BF11 AE8
DDR_A_D37 BG1 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 AE1 DDR_A_D53 BF10 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 AE9
DDR_A_D38 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4 DDR_A_D54 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11
DDR_A_D39 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3 DDR_A_D55 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3
C C
DDR_A_D40 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 DDR_A_D56 BB11 DDR1_DQ_23/DDR0_DQ_55 AH10 DDR_B_MA16
DDR_A_D41 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA0 <23,24> DDR_A_D57 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 DDR_B_MA14
BD1 AH1 BC11 AH11
DDR_A_D42 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 DDR_A_BA1 <23,24> DDR_A_D58 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 DDR_B_MA15
BC4 AU1 BB8 AF8
DDR_A_D43 BC5 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <23,24> DDR_A_D59 BC8 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15
DDR_A_D44 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 DDR_A_MA16 DDR_A_D60 BC10 DDR1_DQ_27/DDR0_DQ_59 AH8
DDR_A_D45 BD4 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 AG4 DDR_A_MA14 DDR_A_D61 BB10 DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 AH9 DDR_B_BA0 <25,26>
DDR_A_D46 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 DDR_A_MA15 DDR_A_D62 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 DDR_B_BA1 <25,26>
BC1 AD1 BC7 AR9
DDR_A_D47 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_D63 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <25,26>
BC2 BB7
DDR_B_D0 AB1 DDR0_DQ_31/DDR0_DQ_47 AH3 DDR_A_MA0 DDR_B_D16 AA11 DDR1_DQ_31/DDR0_DQ_63 AJ9 DDR_B_MA0
DDR_B_D1 AB2 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 AP4 DDR_A_MA1 DDR_B_D17 AA10 DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 AK6 DDR_B_MA1
DDR_B_D2 AA4 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 AN4 DDR_A_MA2 DDR_B_D18 AC11 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_8/DDR1_MA_1 AK5 DDR_B_MA2
DDR_B_D3 AA5 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_5/DDR0_MA_2 AP5 DDR_A_MA3 DDR_B_D19 AC10 DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_5/DDR1_MA_2 AL5 DDR_B_MA3
DDR_B_D4 AB5 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 AP2 DDR_A_MA4 DDR_B_D20 AA7 DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3 AL6 DDR_B_MA4
DDR_B_D5 AB4 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 AP1 DDR_A_MA5 DDR_B_D21 AA8 DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 AM6 DDR_B_MA5
DDR_B_D6 AA2 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 AP3 DDR_A_MA6 DDR_B_D22 AC8 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 AN7 DDR_B_MA6
DDR_B_D7 AA1 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 AN1 DDR_A_MA7 DDR_B_D23 AC7 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 AN10 DDR_B_MA7
DDR_B_D8 V5 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 AN3 DDR_A_MA8 DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7
DDR_B_D9 V2 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 AT4 DDR_A_MA9 DDR_B_D24 W8 AN8 DDR_B_MA8
DDR_B_D10 U1 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 AH2 DDR_A_MA10 DDR_B_D25 W7 DDR1_DQ_40/DDR1_DQ_24 DDR1_CAA_3/DDR1_MA_8 AR11 DDR_B_MA9
DDR_B_D11 U2 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 AN2 DDR_A_MA11 DDR_B_D26 V10 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 AH7 DDR_B_MA10
DDR_B_D12 V1 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 AU4 DDR_A_MA12 DDR_B_D27 V11 DDR1_DQ_42/DDR1_DQ_26 DDR1_CAB_7/DDR1_MA_10 AN11 DDR_B_MA11
DDR_B_D13 V4 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 AE3 DDR_A_MA13 DDR_B_D28 W11 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 AR10 DDR_B_MA12
DDR_B_D14 U5 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 AU2 DDR_B_D29 W10 DDR1_DQ_44/DDR1_DQ_28 DDR1_CAA_6/DDR1_MA_12 AF9 DDR_B_MA13
DDR_B_D15 U4 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 AU3 DDR_A_BG1 <23,24> DDR_B_D30 V7 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 AR7
DDR_B_D32 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# DDR_A_ACT# <23,24> DDR_B_D31 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR_B_BG1 <25,26>
R2 V8 AT9
DDR_B_D33 P5 DDR0_DQ_48/DDR1_DQ_32 AG3 DDR_B_D48 R11 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT# DDR_B_ACT# <25,26>
DDR_B_D34 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR_A_PARITY <23,24> DDR_B_D49 DDR1_DQ_48/DDR1_DQ_48
R4 AU5 P11 AJ7
DDR_B_D35 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR_A_ALERT# <23,24> DDR_B_D50 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR_B_PARITY <25,26>
P4 P7 AR8
DDR_B_D36 R5 DDR0_DQ_51/DDR1_DQ_35 DDR_B_D51 R8 DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# DDR_B_ALERT# <25,26>
DDR_B_D37 P2 DDR0_DQ_52/DDR1_DQ_36 BR5 DDR_A_DQS#0 DDR_B_D52 R10 DDR1_DQ_51/DDR1_DQ_51
DDR_B_D38 R1 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 BL3 DDR_A_DQS#1 DDR_B_D53 P10 DDR1_DQ_52/DDR1_DQ_52 BN9 DDR_A_DQS#2
DDR_B_D39 P1 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 BG3 DDR_A_DQS#4 DDR_B_D54 R7 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 BL9 DDR_A_DQS#3
DDR_B_D40 M4 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 BD3 DDR_A_DQS#5 DDR_B_D55 P8 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 BG9 DDR_A_DQS#6
DDR_B_D41 M1 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 AA3 DDR_B_DQS#0 DDR_B_D56 L11 DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6 BC9 DDR_A_DQS#7
DDR_B_D42 L4 DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 U3 DDR_B_DQS#1 DDR_B_D57 M11 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 AC9 DDR_B_DQS#2
DDR_B_D43 L2 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 P3 DDR_B_DQS#4 DDR_B_D58 L7 DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2 W9 DDR_B_DQS#3
DDR_B_D44 M5 DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 L3 DDR_B_DQS#5 DDR_B_D59 M8 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 R9 DDR_B_DQS#6
B DDR_B_D45 M2 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5 DDR_B_D60 L10 DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6 M9 DDR_B_DQS#7 B
DDR_B_D46 L5 DDR0_DQ_61/DDR1_DQ_45 BP5 DDR_A_DQS0 DDR_B_D61 M10 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7
DDR_B_D47 L1 DDR0_DQ_62/DDR1_DQ_46 DDR0_DQSP_0/DDR0_DQSP_0 BK3 DDR_A_DQS1 DDR_B_D62 M7 DDR1_DQ_61/DDR1_DQ_61 BP9 DDR_A_DQS2
DDR0_DQ_63/DDR1_DQ_47 DDR0_DQSP_1/DDR0_DQSP_1 BF3 DDR_A_DQS4 DDR_B_D63 L8 DDR1_DQ_62/DDR1_DQ_62 DDR1_DQSP_0/DDR0_DQSP_2 BJ9 DDR_A_DQS3
BA2 DDR0_DQSP_2/DDR0_DQSP_4 BC3 DDR_A_DQS5 DDR1_DQ_63/DDR1_DQ_63 DDR1_DQSP_1/DDR0_DQSP_3 BF9 DDR_A_DQS6
BA1 NC/DDR0_ECC_0 DDR0_DQSP_3/DDR0_DQSP_5 AB3 DDR_B_DQS0 AW11 DDR1_DQSP_2/DDR0_DQSP_6 BB9 DDR_A_DQS7
AY4 NC/DDR0_ECC_1 DDR0_DQSP_4/DDR1_DQSP_0 V3 DDR_B_DQS1 AY11 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 AA9 DDR_B_DQS2
AY5 NC/DDR0_ECC_2 DDR0_DQSP_5/DDR1_DQSP_1 R3 DDR_B_DQS4 AY8 NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 V9 DDR_B_DQS3
BA5 NC/DDR0_ECC_3 DDR0_DQSP_6/DDR1_DQSP_4 M3 DDR_B_DQS5 AW8 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 P9 DDR_B_DQS6
BA4 NC/DDR0_ECC_4 DDR0_DQSP_7/DDR1_DQSP_5 AY10 NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 L9 DDR_B_DQS7
AY1 NC/DDR0_ECC_5 AY3 AW10 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7
AY2 NC/DDR0_ECC_6 DDR0_DQSP_8/DDR0_DQSP_8 BA3 AY7 NC/DDR1_ECC_5 AW9
NC/DDR0_ECC_7 1 OF 13 DDR0_DQSN_8/DDR0_DQSN_8 AW7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AY9
CML-H_BGA1440 DDR CHANNEL A NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8
@
RH149
RH148 1 2 121_0402_1% DDR_RCOMP0 G1 BN13
DDR_RCOMP1 DDR_RCOMP_0 DDR_VREF_CA +0.6V_VREFCA
RH149 1 CFL@ 2 121_0402_1% H1 BP13 @ T144
RH150 1 2 100_0402_1% DDR_RCOMP2 J2 DDR_RCOMP_1 DDR0_VREF_DQ BR13
2 OF 13 +0.6V_B_VREFDQ
DDR_RCOMP_2 DDR1_VREF_DQ
CML-H_BGA1440 DDR CHANNEL B
75_0402_1% @
CML@
Net : DDR_RCOMP0
Net : DDR_RCOMP1
Net : DDR_RCOMP2
Trace Width/Space: 15 mil/ 25 mil
Max Trace Length: 500 mil
A A

CPU(2/7) DDR4
5 4 3 2 1
5 4 3 2 1
+VCCST
UC1E
RH163 1 2 1K_0201_5% H_THERMTRIP#
RH156 1 @ 2 51_0201_5% XDP_PREQ# B31 BN25

<15> PCH_CPU_BCLK_P BCLKP CFG_0 CFG0 <7>
A32 BN27
1 2 H_VCCST_PWRGD <15> PCH_CPU_BCLK_N BCLKN CFG_1 BN26 CFG1 <7>
RH164 1K_0201_5% CFG2
CFG_2 CFG2 <7>
D35 BN28
D VR_SVID_DATA <15> PCH_CPU_PCIBCLK_P PCI_BCLKP CFG_3 CFG3 <7> D
RH151 1 2 100_0402_1% C36 BR20 CFG4
<15> PCH_CPU_PCIBCLK_N PCI_BCLKN CFG_4 BM20 CFG4 <7>
CFG5
VR_SVID_ALERT# CFG_5 CFG5 <7>
RH152 1 2 56.2_0402_1% E31 BT20 CFG6
<15> CPU_24MHZ_P D31 CLK24P CFG_6 BP20 CFG6 <7>
CFG7
<15> CPU_24MHZ_N CLK24N CFG_7 CFG7 <7>
BR23
+VCCSTG CFG_8 CFG8 <7>
BR22
CFG_9 BT23 CFG9 <7>
CFG_10 CFG10 <7>
BT22
CFG_11 BM19 CFG11 <7>
CFG_12 CFG12 <7>
BR19
H_PROCHOT# CFG_13 CFG13 <7>
RH165 1 2 1K_0201_5% BP19
VR_SVID_ALERT# VR_SVID_ALERT#_R CFG_14 CFG14 <7>
RH153 1 2 BH31 BT19
<91,95> VR_SVID_ALERT# VIDALERT# CFG_15 CFG15 <7>
220_0201_5% BH32
<91,95> VR_SVID_CLK VR_SVID_DATA BH29 VIDSCK BN23
<91,95> VR_SVID_DATA H_PROCHOT# VIDSOUT CFG_17 CFG17 <7>
RH158 1 2 499_0402_1% BR30 BP23
<44,58,82,83,85,91> H_PROCHOT# PROCHOT# CFG_16 CFG16 <7>
BP22
CFG_19 CFG19 <7>
1
DDR_VTT_PG_CTRL BT13 BN22
DDR_VTT_CNTL CFG_18 CFG18 <7>
ESD@
CH240
2
0.1U_0402_25V6 BR27
BPM#_0 BT27
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS BPM#_1 BM31
H_VCCST_PWRGD RH154 1 2 60.4_0402_1% H13 BPM#_2 BT30
<58,78> H_VCCST_PWRGD VCCST_PWRGD BPM#_3
1: Normal Operation; Lane # definition matches
CFG2 BT31
socket pin map definition <16> H_CPUPWRGD
BP35 PROCPWRGD BT28 XDP_TDO
<14> PLTRST_CPU# BM34 RESET# PROC_TDO BL32 XDP_TDI XDP_TDO <7,16>
<14> H_PM_SYNC PM_SYNC PROC_TDI XDP_TMS XDP_TDI <7,16>
0:Lane Reversed RH155 1 2 20_0201_5% BP31 BP28
* <14> H_PM_DOWN
<14,58> H_PECI
<14> H_THERMTRIP#
H_THERMTRIP#
BT34
J31
PM_DOWN
PECI
THERMTRIP#
PROC_TMS
PROC_TCK
BR28 PCH_JTAG_TCK
CPU_XDP_TRST#
XDP_TMS <7,16>
PCH_JTAG_TCK <7,16>
BP30
CFG2 1 2 RH519 1 @ 2 0_0201_5% BR33 PROC_TRST# BL30 XDP_PREQ# CPU_XDP_TRST# <7,20>
<14> PROC_DETECT# PROC_SELECT# SKTOCC# PROC_PREQ# XDP_PRDY# XDP_PREQ# <7,20>
RH184 1K_0201_5% RE716 1 2 0_0201_5% BN1 BP27
PROC_SELECT# PROC_PRDY# XDP_PRDY# <7,20>
RC693 1 @ 2 51_0201_5% H_CATERR# BM30
+VCCST CATERR# CFG_RCOMP
BT25
AT13 CFG_RCOMP
C AW13 ZVM#
MSM#
Net :CFG_RCOMP C
1
AU13
RSVD1
RH59 Trace Width/Space: 4 mil/ 12 mil
AY13
Display Port Presence Strap RSVD2 49.9_0201_1%
Max Trace Length: 600 mil
5 OF 13
2
1 : Disabled; No Physical Display Port CML-H_BGA1440
CFG4 attached to Embedded Display Port +1.2V_DDR @
UC2
0 : Enabled; An external Display Port device is 5 1
* connected to the Embedded Display Port
1
VCC NC
A
2 DDR_VTT_PG_CTRL
4
CH197 Y 3
0.1U_0201_10V6K GND H_VCCST_PWRGD H_CPUPWRGD PLTRST_CPU#
CFG4 1 2 2 74AUP1G07SE-7_SOT353-5
RH185 1K_0201_5%
1 1 1
CH193 CH194 CH195
0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K
+3VS ESD@ ESD@ ESD@
2 2 2
1
PCIE Port Bifurcation Straps RH525
330K_0402_5%
2
11: (Default) x16 - Device 1 functions 1 and 2 disabled
<87> SM_PG_CTRL
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
B B
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
* PCH_SYS_PWROK_XDP
RH489 1 2 1K_0201_5%
<15> PCH_SPI_0_D0
CFG5 1 2
RH186 1K_0201_5%
CFG6 1 2 RH489,RH493 close to UH4

RH187 1K_0201_5% +3V_PCH
RH493 1 2 2.2K_0201_5% PCH_SYS_PWROK_XDP
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB

CFG7 * de assertion
+VCCSTG
0: PEG Wait for BIOS for training
RH494 1 @ 2 51_0201_5% XDP_TMS

CFG7 1 @ 2
RH188 1K_0201_5% RH495 1 CMC@ 2 51_0201_5% XDP_TDI
RH496 1 CMC@ 2 51_0201_5% XDP_TDO
A A

CPU(3/7) CFG,XDP
5 4 3 2 1
5 4 3 2 1
D D
+VCC_CORE +VCC_CORE
+VCC_CORE +VCC_CORE
UC1J
UC1M K14 W35

L13 VCC1 VCC64 W36
UC1I L14 VCC2 VCC65 W37
AA13 AH13 E2 N13 VCC3 VCC66 W38
AA31 VCC1 VCC64 AH14 IST_TRIG E3 RSVD_TP5 N14 VCC4 VCC67 Y29
VCC2 VCC65 TC13 @ IST_TRIG VCC5 VCC68
AA32 AH29 E1 N30 Y30
AA33 VCC3 VCC66 AH30 D1 RSVD_TP4 N31 VCC6 VCC69 Y31
AA34 VCC4 VCC67 AH31 RSVD_TP3 N32 VCC7 VCC70 Y32
AA35 VCC5 VCC68 AH32 BR1 BK28 N35 VCC8 VCC71 Y33
AA36 VCC6 VCC69 AJ14 BT2 RSVD_TP1 RSVD11 BJ28 N36 VCC9 VCC72 Y34
AA37 VCC7 VCC70 AJ29 RSVD_TP2 RSVD10 N37 VCC10 VCC73 Y35
AA38 VCC8 VCC71 AJ30 BN35 N38 VCC11 VCC74 Y36
AB29 VCC9 VCC72 AJ31 RSVD15 P13 VCC12 VCC75
AB30 VCC10 VCC73 AJ32 J24 P14 VCC13
AB31 VCC11 VCC74 AJ33 H24 RSVD28 P29 VCC14
AB32 VCC12 VCC75 AJ34 BN33 RSVD27 P30 VCC15
AB35 VCC13 VCC76 AJ35 BL34 RSVD14 P31 VCC16
AB36 VCC14 VCC77 AJ36 RSVD13 P32 VCC17
AB37 VCC15 VCC78 AK31 N29 P33 VCC18
AB38 VCC16 VCC79 AK32 R14 RSVD30 P34 VCC19
AC13 VCC17 VCC80 AK33 AE29 RSVD31 P35 VCC20
AC14 VCC18 VCC81 AK34 AA14 RSVD2 P36 VCC21
AC29 VCC19 VCC82 AK35 AP29 RSVD1 R13 VCC22
AC30 VCC20 VCC83 AK36 AP14 RSVD5 R31 VCC23
AC31 VCC21 VCC84 AK37 RH592 1 2 0_0201_5% A36 RSVD4 R32 VCC24
AC32 VCC22 VCC85 AK38 VSS_A36 R33 VCC25
C
AC33 VCC23 VCC86 AL13 RH593 1 2 0_0201_5% A37 R34 VCC26 C
AC34 VCC24 VCC87 AL29 VSS_A37 R35 VCC27
AC35 VCC25 VCC88 AL30 RH167 1 2 30_0201_5% H23 R36 VCC28
VCC26 VCC89 <20> PCH_TRIGGER PROC_TRIGIN VCC29
AC36 AL31 RH192 1 2 30_0201_5% J23 R37
VCC27 VCC90 <20> CPU_TRIGGER PROC_TRIGOUT VCC30
AD13 AL32 R38
AD14 VCC28 VCC91 AL35 F30 T29 VCC31
AD31 VCC29 VCC92 AL36 RSVD24 T30 VCC32
AD32 VCC30 VCC93 AL37 T31 VCC33
AD33 VCC31 VCC94 AL38 E30 T32 VCC34
AD34 VCC32 VCC95 AM13 RSVD23 T35 VCC35
AD35 VCC33 VCC96 AM14 T36 VCC36
AD36 VCC34 VCC97 AM29 B30 BL31 T37 VCC37
AD37 VCC35 VCC98 AM30 C30 RSVD7 RSVD12 AJ8 T38 VCC38
AD38 VCC36 VCC99 AM31 RSVD21 RSVD3 G13 U29 VCC39
AE13 VCC37 VCC100 AM32 RSVD25 U30 VCC40
AE14 VCC38 VCC101 AM33 G3 U31 VCC41
AE30 VCC39 VCC102 AM34 J3 RSVD26 C38 U32 VCC42
AE31 VCC40 VCC103 AM35 RSVD29 RSVD22 C1 U33 VCC43
AE32 VCC41 VCC104 AM36 RSVD20 BR2 U34 VCC44
AE35 VCC42 VCC105 AN13 BR35 RSVD17 BP1 U35 VCC45
AE36 VCC43 VCC106 AN14 BR31 RSVD19 RSVD16 B38 U36 VCC46
AE37 VCC44 VCC107 AN31 BH30 RSVD18 RSVD8 B2 V13 VCC47
AE38 VCC45 VCC108 AN32 RSVD9 RSVD6 V14 VCC48
AF29 VCC46 VCC109 AN33 V31 VCC49
AF30 VCC47 VCC110 AN34 13 OF 13 V32 VCC50
AF31 VCC48 VCC111 AN35 CML-H_BGA1440 V33 VCC51
VCC50 VCC113 @ VCC53
AF33 AN37 V35
AF35 VCC52 VCC115 AP13 V37 VCC55
AF36 VCC53 VCC116 AP30 V38 VCC56
AF37 VCC54 VCC117 AP31 W13 VCC57
AF38 VCC55 VCC118 AP32 W14 VCC58
AG14 VCC56 VCC119 AP35 +VCC_CORE W29 VCC59
AG31 VCC57 VCC120 AP36 W30 VCC60
B B
VCC60 VCC123 VCC63
1
AG34 K13 10 OF 13
AG35 VCC61 VCC124 RH197 CML-H_BGA1440
AG36 VCC62
100_0201_1% @
VCC63
2
AG37
VCC_SENSE VCCSENSE <91>
AG38
9 OF 13 VSS_SENSE VSSSENSE <91>
CML-H_BGA1440
1
@
RH466
100_0201_1%
2
A A

CPU(4/7) +VCC_CORE,RSVD
5 4 3 2 1
5 4 3 2 1
+VCCIO +VCCSTG +VCCST
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
D D
1 1 1 1 1 1
CH102
CH103
CH104
+VCCSA +1.2V_DDR
CH105
CH106
CH107
2 2 2 2 2 2
UC1L
J30 AA6
K29 VCCSA1 VDDQ1 AE12
K30 VCCSA2 VDDQ2 AF5
K31 VCCSA3 VDDQ3 AF6
K32 VCCSA4 VDDQ4 AG5
K33 VCCSA5 VDDQ5 AG9
VCCPLL_OC is allowed to be turned off

K34 VCCSA6 VDDQ6 AJ12
K35 VCCSA7 VDDQ7 AL11
during S3 and DS3 if it is not powered directly from VDDQ

L31 VCCSA8 VDDQ8 AP6
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12
L36 VCCSA11 VDDQ11 AR6
L37 VCCSA12 VDDQ12 AT12
L38 VCCSA13 VDDQ13 AW6
M29 VCCSA14 VDDQ14 AY6
M30 VCCSA15 VDDQ15 J5
M31 VCCSA16 VDDQ16 J6
M32 VCCSA17 VDDQ17 K12
M33 VCCSA18 VDDQ18 K6
M34 VCCSA19 VDDQ19 L12
M35 VCCSA20 VDDQ20 L6
C M36 VCCSA21 VDDQ21 R6 C
+VCCIO VCCSA22 VDDQ22 T6
VDDQ23 W6
VDDQ24 Y12 +1.2V_VCCPLL_OC +1.2V_DDR
AG12 VDDQ25
G15 VCCIO1 RH530 1 @ 2 0_0402_5%
G17 VCCIO2
G19 VCCIO3 BH13
G21 VCCIO4 VCCPLL_OC1 BJ13 +1.2V_DDR +1.2V_DDR
H15 VCCIO5 VCCPLL_OC2 G11 +VCCST
H16 VCCIO6 VCCPLL_OC3
H17 VCCIO7 H30 10mil +VCCSTG +VCCSA
H19 VCCIO8 VCCST
VCCIO9
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
H20 H29 10mil
VCCIO10 VCCSTG2
2
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
H21 1 1 1 1
H26 VCCIO11 G30 10mil +VCCST RH201
VCCIO12 VCCSTG1 1 1 1 1 1 1 1 1 1 1 1
CH129
CH130
CH131
CH132
H27 100_0201_1%
VCCIO13
CH118
CH121
CH124
CH120
CH119
CH122
CH123
CH125
CH126
CH127
CH128
J15 H28 10mil
J16 VCCIO14 VCCPLL1 J28 10mil 2 2 2 2
1
J17 VCCIO15 VCCPLL2 2 2 2 2 2 2 2 2 2 2 2

J19 VCCIO16
J20 VCCIO17 M38
VCCIO18 VCCSA_SENSE VCCSA_SENSE <95>
J21 M37
VCCIO19 VSSSA_SENSE VSSSA_SENSE <95>
J26
VCCIO20
1
J27 H14
VCCIO21 VCCIO_SENSE VCCIO_SENSE <90>
J14 RH469
VSSIO_SENSE VSSIO_SENSE <90>
100_0201_1%
12 OF 13
CML-H_BGA1440
2
B B
+1.2V_VCCPLL_OC +VCCST
1U_0201_6.3V6M
1U_0201_6.3V6M
22U_0402_6.3V6M
1 1 1
CC39
@
CC36
CC37
2 2 2
A A

CPU(5/7) +VCCSA,+VCCIO
0.2
5 4 3 2 1
5 4 3 2 1
+VCCGT +VCCGT
UC1K
AT14 BD35
AT31 VCCGT1 VCCGT80 BD36
AT32 VCCGT2 VCCGT81 BE31
D AT34 VCCGT4 VCCGT83 BE33 D
AU14 VCCGT9 VCCGT88 BE38
AU29 VCCGT10 VCCGT89 BF13
AV29 VCCGT18 VCCGT97 BF37
AV30 VCCGT19 VCCGT98 BF38
AV31 VCCGT20 VCCGT99 BG29
AW14 VCCGT26 VCCGT105 BG35
AW31 VCCGT27 VCCGT106 BG36
AW32 VCCGT28 VCCGT107 BH33
AW38 VCCGT34 VCCGT113 BJ16
AY29 VCCGT35 VCCGT114 BJ17
C AY30 VCCGT36 VCCGT115 BJ19 C
BA13 VCCGT43 VCCGT122 BJ37
BA14 VCCGT44 VCCGT123 BJ38
BA29 VCCGT45 VCCGT124 BK16
BB13 VCCGT53 VCCGT132 BK27
BB14 VCCGT54 VCCGT133 BL15
BC29 VCCGT63 VCCGT142 BL36
BC30 VCCGT64 VCCGT143 BL37
BC31 VCCGT65 VCCGT144 BM15
B BC36 VCCGT68 VCCGT147 BM36 B
BC38 VCCGT70 VCCGT149 BN15
BD13 VCCGT71 VCCGT150 BN16
BD32 VCCGT76 VCCGT155 BP15
BD33 VCCGT77 VCCGT156 BP16 +VCCGT
BD34 VCCGT78 VCCGT157 BP17
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15
2
BR15 VCCGT160 VCCGT165 BT16
VCCGT161 VCCGT166 RH203
BR16 BT17
BR17 VCCGT162 VCCGT167 BT37 100_0402_1%
VCCGT163 VCCGT168
VSSGT_SENSE
AH37 1 VSSGT_SENSE <91>
AH38
VCCGT_SENSE VCCGT_SENSE <91>
CML-H_BGA1440
1
11 OF 13
@
RH472
100_0402_1%
2
1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils

2. Maintain 25-mil separation distance away from any other dynamic signals.
A A
3. RC1, RC2 should be placed within 2 inches (50.8 mm) of CPU

CPU(6/7) +VCCGT
0.2
5 4 3 2 1
5 4 3 2 1
UC1H
UC1F UC1G BN4 F15
A10 AK4 AW5 BJ15 BN7 VSS_325 VSS_409 F17
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BP12 VSS_326 VSS_410 F19
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP14 VSS_327 VSS_411 F2
D A18 VSS_3 VSS_84 AL14 AY34 VSS_165 VSS_246 BJ25 BP18 VSS_328 VSS_412 F21 D
A20 VSS_4 VSS_85 AL33 B9 VSS_166 VSS_247 BJ29 BP21 VSS_329 VSS_413 F23
A22 VSS_5 VSS_86 AL34 BA10 VSS_167 VSS_248 BJ30 BP24 VSS_330 VSS_414 F25
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP34 VSS_335 VSS_419 F36
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP7 VSS_336 VSS_420 F4
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BR12 VSS_337 VSS_421 F5
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR14 VSS_338 VSS_422 F8
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR18 VSS_339 VSS_423 F9
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR21 VSS_340 VSS_424 G10
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR26 VSS_343 VSS_427 G16
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR29 VSS_344 VSS_428 G18
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR34 VSS_345 VSS_429 G20
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BT12 VSS_348 VSS_432 G24
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT24 VSS_352 VSS_436 G5
AD11 VSS_28 VSS_109 AP8 BC6 VSS_190 VSS_271 BL33 BT26 VSS_353 VSS_437 G6
AD12 VSS_29 VSS_110 AP9 BD10 VSS_191 VSS_272 BL35 BT29 VSS_354 VSS_438 G8
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT32 VSS_355 VSS_439 G9
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT5 VSS_356 VSS_440 H11
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 C11 VSS_357 VSS_441 H12
C AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C17 VSS_360 VSS_444 H25 C
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C19 VSS_361 VSS_445 H32
AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C21 VSS_362 VSS_446 H35
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C23 VSS_363 VSS_447 J10
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C8 VSS_370 VSS_454 J4
AG11 VSS_46 VSS_127 AR5 BF33 VSS_208 VSS_289 BM29 C9 VSS_371 VSS_455 J7
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 D10 VSS_372 VSS_456 K1
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D12 VSS_373 VSS_457 K10
AG30 VSS_49 VSS_130 AT6 BG12 VSS_211 VSS_292 BM35 D14 VSS_374 VSS_458 K11
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D16 VSS_375 VSS_459 K2
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D22 VSS_378 VSS_462 K4
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D24 VSS_379 VSS_463 K5
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D26 VSS_380 VSS_464 K7
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D28 VSS_381 VSS_465 K8
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D3 VSS_382 VSS_466 K9
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D30 VSS_383 VSS_467 L29
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D33 VSS_384 VSS_468 L30
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D6 VSS_385 VSS_469 L33
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D9 VSS_386 VSS_470 L34
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 E34 VSS_387 VSS_471 M12
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E35 VSS_388 VSS_472 M13
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E38 VSS_389 VSS_473 N10
B AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 N3 VSS_392 VSS_476 N2 B
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N33 VSS_393 VSS_477 BT8
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N34 VSS_394 VSS_478 BR9
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N4 VSS_395 VSS_479
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N5 VSS_396 A3
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N6 VSS_397 VSS_A3 A34
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N7 VSS_398 VSS_A34 A4
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N8 VSS_399 VSS_A4 B3
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N9 VSS_400 VSS_B3 B37
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 P12 VSS_401 VSS_B37 BR38
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P37 VSS_402 VSS_BR38 BT3
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 M14 VSS_403 VSS_BT3 BT35
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M6 VSS_404 VSS_BT35 BT36
AK30 VSS_80 VSS_161 W34 BJ14 VSS_242 VSS_323 T14 N1 VSS_405 VSS_BT36 BT4
VSS_81 VSS_162 VSS_243 VSS_324 F11 VSS_406 VSS_BT4 C2
CML-H_BGA1440 CML-H_BGA1440 F13 VSS_407 VSS_C2 D38
6 OF 13 7 OF 13 VSS_408 VSS_D38
@ @
CML-H_BGA1440
8 OF 13
@
A A

CPU(7/7) VSS
0.2
5 4 3 2 1
5 4 3 2 1
UH1
FHSSKU_MBL QS64 A0 FCBGA 874P S

SA0000D3F0L
PCH@
D UH1C D
AR2 G36
CL_CLK PCIE9_RXN PCIE_PRX_DTX_N9 <68>
AT5 F36
AU4 CL_DATA PCIE9_RXP C34 PCIE_PTX_DRX_N9 2 1 CH202 PCIE_PRX_DTX_P9 <68>
0.22U_0201_6.3V
CL_RST# PCIE9_TXN PCIE_PTX_DRX_P9 PCIE_PTX_C_DRX_N9 <68>
D34 0.22U_0201_6.3V 2 1 CH203
PCIE9_TXP PCIE_PTX_C_DRX_P9 <68>
P48 M.2 SSD Slot#1
V47 GPP_K8
V48 GPP_K9 K37 PCIe/SATA
W47 GPP_K10 PCIE10_RXN J37 PCIE_PRX_DTX_N10 <68>
GPP_K11 PCIE10_RXP PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 <68>
C35 0.22U_0201_6.3V 2 1 CH204
PCIE10_TXN PCIE_PTX_DRX_P10 PCIE_PTX_C_DRX_N10 <68>
L47 B35 0.22U_0201_6.3V 2 1 CH205
L46 GPP_K0 PCIE10_TXP PCIE_PTX_C_DRX_P10 <68>
U48 GPP_K1 F44
U47 GPP_K2 PCIE15_RXN/SATA2_RXN E45 PCIE_PRX_DTX_N15 <73>
GPP_K3 PCIE15_RXP/SATA2_RXP PCIE_PRX_DTX_P15 <73>
N48
GPP_K4 PCIE15_TXN/SATA2_TXN
B40
PCIE_PTX_DRX_N15 <73> LAN
N47 C40
P47 GPP_K5 PCIE15_TXP/SATA2_TXP PCIE_PTX_DRX_P15 <73>
R46 GPP_K6 L41
GPP_K7 PCIE16_RXN/SATA3_RXN M40 PCIE_PRX_DTX_N16 <73>
PCIE_PTX_DRX_P11 PCIE16_RXP/SATA3_RXP PCIE_PRX_DTX_P16 <73>
<68> PCIE_PTX_C_DRX_P11
0.22U_0201_6.3V 2 1 CH206
PCIE_PTX_DRX_N11
C36
PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN
B41
PCIE_PTX_DRX_N16 <73> WLAN
0.22U_0201_6.3V 2 1 CH207 B36 C41
<68> PCIE_PTX_C_DRX_N11 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP PCIE_PTX_DRX_P16 <73>
M.2 SSD Slot#1 <68> PCIE_PRX_DTX_P11
F39
PCIE11_RXP/SATA0A_RXP
G38 K43
PCIe/SATA <68> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN K44 PCIE_PRX_DTX_N17 <42>
PCIE17_RXP/SATA4_RXP PCIE_PTX_DRX_N17 PCIE_PRX_DTX_P17 <42>
AR42 A42 0.22U_0201_6.3V 2 1 CH218
GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN PCIE_PTX_DRX_P17 PCIE_PTX_C_DRX_N17 <42>
AR48 B42 0.22U_0201_6.3V 2 1 CH219
AU47 GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP PCIE_PTX_C_DRX_P17 <42>
AU46 GPP_F13/SATA_SDATAOUT0 P41
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN PCIE_PRX_DTX_N18 <42> TBT
R40
PCIE_PTX_DRX_N14 PCIE18_RXP/SATA5_RXP PCIE_PTX_DRX_N18 PCIE_PRX_DTX_P18 <42>
0.22U_0201_6.3V 2 1 CH255 C39 C42 0.22U_0201_6.3V 2 1 CH220
<73> PCIE_PTX_C_DRX_N14 PCIE_PTX_DRX_P14 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN PCIE_PTX_DRX_P18 PCIE_PTX_C_DRX_N18 <42>
0.22U_0201_6.3V 2 1 CH256 D39 D42 0.22U_0201_6.3V 2 1 CH221
<73> PCIE_PTX_C_DRX_P14 D46 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP PCIE_PTX_C_DRX_P18 <42>
<73> PCIE_PRX_DTX_N14 PCIE14_RXN/SATA1B_RXN PCH_SATADET#
C47 AK48
<73> PCIE_PRX_DTX_P14 PCIE14_RXP/SATA1B_RXP GPP_E8/SATALED#
M.2 SSD Slot#3 GPP_E0/SATAXPCIE0/SATAGP0
AH41
0.22U_0201_6.3V 2 1 CH257 PCIE_PTX_DRX_N13 B38 AJ43
PCIe <73> PCIE_PTX_C_DRX_N13
2 1 CH258 PCIE_PTX_DRX_P13 C38 PCIE13_TXN/SATA0B_TXN GPP_E1/SATAXPCIE1/SATAGP1 AK47
SATA_GP1 <68>
0.22U_0201_6.3V
<73> PCIE_PTX_C_DRX_P13 C45 PCIE13_TXP/SATA0B_TXP GPP_E2/SATAXPCIE2/SATAGP2 AN47
WWAN +3VS
<73> PCIE_PRX_DTX_N13 PCIE13_RXN/SATA0B_RXN GPP_F0/SATAXPCIE3/SATAGP3
C C46 AM46 C
<73> PCIE_PRX_DTX_P13 PCIE13_RXP/SATA0B_RXP GPP_F1/SATAXPCIE4/SATAGP4 AM43 SATA_GP4 <68>
0.22U_0201_6.3V 2 1 CH208 PCIE_PTX_DRX_P12 E37 GPP_F2/SATAXPCIE5/SATAGP5 AM47
<68> PCIE_PTX_C_DRX_P12 PCIE_PTX_DRX_N12 PCIE12_TXP/SATA1A_TXP GPP_F3/SATAXPCIE6/SATAGP6 PCH_SATADET#
M.2 SSD Slot#1 0.22U_0201_6.3V 2 1 CH209 D38 AM48 RH512 2 1 10K_0201_5%
<68> PCIE_PTX_C_DRX_N12 J41 PCIE12_TXN/SATA1A_TXN GPP_F4/SATAXPCIE7/SATAGP7 TBT_RTD3_RST# <42>
PCIe/SATA <68> PCIE_PRX_DTX_P12
H42 PCIE12_RXP/SATA_1A_RXP AU48
<68> PCIE_PRX_DTX_N12 1 2 PCIE_PTX_DRX_P20 B44 PCIE12_RXN/SATA1A_RXN GPP_F21/EDP_BKLTCTL AV46 BIA_PWM_PCH <38>
0.22U_0201_6.3V CH225
<42> PCIE_PTX_C_DRX_P20 PCIE_PTX_DRX_N20 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN ENBKL_PCH <38>
0.22U_0201_6.3V 1 2 CH224 A44 AV44
<42> PCIE_PTX_C_DRX_N20 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN ENVDD_PCH <38>
R37
<42> PCIE_PRX_DTX_P20 R35 PCIE20_RXP/SATA7_RXP AD3 H_THERMTRIP#_R RH79 1 2 620_0402_5%
<42> PCIE_PRX_DTX_N20 PCIE_PTX_DRX_P19 PCIE20_RXN/SATA7_RXN THRMTRIP# PCH_PECI H_THERMTRIP# <9>
0.22U_0201_6.3V 1 2 CH223 D43 AF2 RH73 1 2 12.1_0402_1%
<42> PCIE_PTX_C_DRX_P19 1 2 PCIE_PTX_DRX_N19 C44 PCIE19_TXP/SATA6_TXP PECI AF3 H_PM_SYNC_R H_PECI <9,58>
TBT 0.22U_0201_6.3V CH222 RH15 1 2 30_0201_5%
<42> PCIE_PTX_C_DRX_N19 PCIE19_TXN/SATA6_TXN PM_SYNC H_PM_SYNC <9>
N42 AG5
<42> PCIE_PRX_DTX_P19 PCIE19_RXP/SATA6_RXP PLTRST_CPU# PLTRST_CPU# <9>
M44 AE2
<42> PCIE_PRX_DTX_N19 PCIE19_RXN/SATA6_RXN 3 OF 13 PM_DOWN H_PM_DOWN <9>
CML-H_BGA874
1
@ @
RH14
12.1_0201_1%
2
UH1E
AL13 CPU_DDC1CLK
AT6 GPP_I5/DDPB_CTRLCLK AR8 CPU_DDC1DATA
B <42> CPU_DP1_HPD GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I6/DDPB_CTRLDATA B
AN10 AN13
AP9 GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I7/DDPC_CTRLCLK AL10 +3VS
AL15 GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I8/DDPC_CTRLDATA AL9
GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I9/DDPD_CTRLCLK AR3
GPP_I10/DDPD_CTRLDATA AN40
GPP_F23/DDPF_CTRLDATA AT49 CPU_DDC1CLK 2.2K_0201_5% 2 1 RH604
GPP_F22/DDPF_CTRLCLK
AP41 CPU_DDC1DATA 2.2K_0201_5% 2 1 RH605
EDP_HPD AN6 GPP_F14/PS_ON# PROC_DETECT# <9>
<38> EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4 CPU_DP1_HPD RH1602
M45 100K_0201_5% 2 1
GPP_K23/IMGCLKOUT1 STRAP3_PCH <30>
L48
GPP_K22/IMGCLKOUT0 T45 STRAP5_PCH <30>
1
GPP_K21 T46
RH9 GPP_K20 AJ47
100K_0201_5% 5 OF 13 GPP_H23/TIME_SYNC0
CML-H_BGA874 DDP[B..F]CTRLDATA
2
@ This signal has a weak internal Pull-down.

0 = Port B~D is not detected.
1 = Port B,C,D is detected. (Default)
Notes:
1. The internal Pull-down is disabled after
PCH_PWROK de-asserts.
2. This signal is in the primary well.
A A

PCH (1/7) SATA,DDC,PCIE
5 4 3 2 1
5 4 3 2 1
PCH_RTCX1
RH70
10M_0201_5%
UH1G 1 2 PCH_RTCX2
BE33
D7 GPP_A16/CLKOUT_48 Y3 PCH_XDP_CLK_N T49 PAD~D @ YH1
<9> CPU_24MHZ_P CLKOUT_CPUNSSC_P CLKOUT_ITPXDP# PCH_XDP_CLK_P
C6 Y4 T50 PAD~D @ 32.768KHZ_9PF_9H03280012
<9> CPU_24MHZ_N CLKOUT_CPUNSSC# CLKOUT_ITPXDP_P
B8 B6 1 2
D <9> PCH_CPU_BCLK_P CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK# PCH_CPU_PCIBCLK_N <9> D
C8 A6
<9> PCH_CPU_BCLK_N CLKOUT_CPUBCLK# CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_P <9>
AJ6 1 1
XTAL24_OUT U9 CLKOUT_PCIE_N0 AJ7 CLK_PEG_N0 <27>
+1V_PCH XTAL24_IN U10 XTAL_OUT CLKOUT_PCIE_P0 AH9 CLK_PEG_P0 <27> GPU
Net : XCLK_BIASREF CH45 CH46
XTAL_IN CLKOUT_PCIE_N1 CLK_PCIE_N1 <68>
AH10 SSD2 10P_0201_50V8J 10P_0201_50V8J
Trace Width/Space: 15mil /15 mil RH71 1 @ 2 2.7K_0402_1% XCLK_BIASREF T3 CLKOUT_PCIE_P1 CLK_PCIE_P1 <68> 2 2
Max Trace Length: 1000 mil 1 2 XCLK_BIASREF AE14
+3VS PCH_RTCX1 BA49 CLKOUT_PCIE_N2 AE15 CLK_PCIE_N2 <73>
RH590 60.4_0402_1% SSD3/WWAN
PCH_RTCX2 RTCX1 CLKOUT_PCIE_P2 CLK_PCIE_P2 <73>
BA48
RTCX2 AE6
BF31 CLKOUT_PCIE_N3 AE7 CLK_PCIE_N3 <42> 9/12 DVT1 Modify
CLKREQ_PEG#0 PEG(dGPU) <27> CLKREQ_PEG#0 GPP_B5/SRCCLKREQ0# CLKOUT_PCIE_P3 CLK_PCIE_P3 <42> TBT
RH1613 1 2 10K_0201_5% BE31
RH1614 1 2 10K_0201_5% CLKREQ_PCIE#1 SSD2 <68> CLKREQ_PCIE#1 AR32 GPP_B6/SRCCLKREQ1# AC2
CLKREQ_PCIE#2 SSD3/WWAN <73> CLKREQ_PCIE#2 GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_N4 CLK_PCIE_N4 <73>
RH1615 1 2 10K_0201_5% BB30 AC3 LAN
CLKREQ_PCIE#4 <42> CLKREQ_PCIE#3 GPP_B8/SRCCLKREQ3# CLKOUT_PCIE_P4 CLK_PCIE_P4 <73>
RH1616 1 2 10K_0201_5% Thunderbolt BA30
1 2 CLKREQ_PEG#6 <73> CLKREQ_PCIE#4 AN29 GPP_B9/SRCCLKREQ4# AB2
RH1619 10K_0201_5%
RH1620 1 2 10K_0201_5% CLKREQ_PCIE#5 LAN <73> CLKREQ_PCIE#5
AE47 GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_N5 AB3
CLK_PCIE_N5 <73>
1 2 CLKREQ_PCIE#3 WLAN <58,74> CLKREQ_PEG#6 AC48 GPP_H0/SRCCLKREQ6# CLKOUT_PCIE_P5 CLK_PCIE_P5 <73> WLAN
RH1621 @ 10K_0201_5%
<68> CLKREQ_PCIE#7 GPP_H1/SRCCLKREQ7#
Caldera AE41
GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_N6
W4
CLK_PEG_N6 <74>
AF48 W3 Caldera EMI@
SSD1 AC41 GPP_H3/SRCCLKREQ9# CLKOUT_PCIE_P6 CLK_PEG_P6 <74>
RH91
AC39 GPP_H4/SRCCLKREQ10# W7 33_0201_5%
AE39 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_N7 W6 CLK_PCIE_N7 <68>
AB48 GPP_H6/SRCCLKREQ12# CLKOUT_PCIE_P7 CLK_PCIE_P7 <68> SSD1 XTAL24_IN_R 1 2 XTAL24_IN
AC44 GPP_H7/SRCCLKREQ13# AC14 RH72
AC43 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_N8 AC15 200K_0402_5%
+3V_PCH GPP_H9/SRCCLKREQ15# CLKOUT_PCIE_P8 1 2 XTAL24_OUT_R 1 2 XTAL24_OUT
V2 U2
V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_N9 U3 YH2 EMI@
RH99 2 1 100K_0201_5% GPP_H15 CLKOUT_PCIE_P15 CLKOUT_PCIE_P9 24MHZ_18PF_XRCGB24M000F2P51R0 RH92
T2 AC9 33_0201_5%
T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_N10 AC11 1 3
#571182_CNL_PCH_H_EDS_V1_Rev0.7 CLKOUT_PCIE_P14 CLKOUT_PCIE_P10 1 3
External pull-up is required. Recommend 100K if pulled AA1 AE9 NC NC
up to 3.3V or 75K if pulled up to 1.8V. Y2 CLKOUT_PCIE_N13 CLKOUT_PCIE_N11 AE11 1 1
CLKOUT_PCIE_P13 CLKOUT_PCIE_P11 2 4
571007_CFL_MOW_Archive_WW22_2017 CLKIN_XTAL
RH1021 CH47 CH48
C AC7 R6 2 1 15P_0402_50V8J 15P_0402_50V8J C
STUFF R on GPP_H15 AC6 CLKOUT_PCIE_N12 CLKIN_XTAL
CLKOUT_PCIE_P12 7 OF 13
10mil 10K_0201_5%
2 2
CML-H_BGA874
@
+3V_PCH 1.5K_0201_5% 1 2 RH1 PCH_SPI_0_D0

<7> XDP_SPI_SI
RH1 close to UH4
+3VS
RH75 1 2 100K_0201_5% PCH_SPI_0_D2 UH1A
RH78 1 2 100K_0201_5% PCH_SPI_0_D3 BE36 AV29 PCH_PLTRST#

GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# PCH_PLTRST# <27,74> 1
CH201
RH1622 1 2 100K_0201_5% PCH_SPI_0_D0 R15
RSVD2 0.1U_0201_6.3V6K
R13 Y47
PCH_SPI_0_CLK RSVD1 GPP_K16/GSXCLK TBT_FORCE_PWR <42> 2
RH1625 1 2 100K_0201_5% Y46
GPP_K12/GSXDOUT Y48
GPP_K13/GSXSLOAD W46 UH3
GPP_K14/GSXDIN
5
AL37 AA45 TC7SH08FU_SSOP5
AN35 VSS247 GPP_K15/GSXSRESET# PCH_PLTRST# 1
P
+3V_PCH TP B 4
PCH_SPI_0_D0 AU41 AL47 2 Y PCIRST# <42,52,58,68,73>
<9> PCH_SPI_0_D0 SPI0_MOSI GPP_E3/CPU_GP0 A
1
G
PCH_SPI_0_D1 BA45 AM45
GPS_DISABLE# PCH_SPI_0_CS#0 SPI0_MISO GPP_E7/CPU_GP1 2
RH160 1 2 100K_0201_5% AY47 BF32 RH199
3
RH236 1 2 100K_0201_5% WWAN_RADIO_DIS# PCH_SPI_0_CLK AW47 SPI0_CS0# GPP_B3/CPU_GP2 BC33 100K_0201_5% CE241
PCH_SPI_0_CS#1 AW48 SPI0_CLK GPP_B4/CPU_GP3 +RTC_CELL 0.1U_0201_10V6K
SPI0_CS1# AE44 1 @ESD@
2
PCH_SPI_0_D2 AY48 GPP_H18/SML4ALERT# AJ46
+3V_PCH <7> PCH_SPI_0_D2 PCH_SPI_0_D3 BA46 SPI0_IO2 GPP_H17/SML4DATA AE43
SPI0_IO3 GPP_H16/SML4CLK RTD3_CIO_PWR_EN <42> close to UH3
2
AT40 AC47 GPP_H15
B
@ PAD~D T277 WWAN_GPIO_WAKE# BE19 SPI0_CS2# GPP_H15/SML3ALERT# AD48 RH531
B
RH100 1 @ 2 4.7K_0201_5% GPP_H12 WWAN_FULL_PWR_EN BF19 GPP_D1/SPI1_CLK/SBK1/BK1 GPP_H14/SML3DATA AF47 1M_0201_5%

<73> WWAN_FULL_PWR_EN WWAN_RADIO_DIS# GPP_D0/SPI1_CS#/SBK0/BK0 GPP_H13/SML3CLK GPP_H12
BF18 AB47
<73> WWAN_RADIO_DIS# GPS_DISABLE# BE18 GPP_D3/SPI1_MOSI/SBK3/BK3 GPP_H12/SML2ALERT# AD47
<73> GPS_DISABLE#
1
WWAN_GPIO_PERST# BC17 GPP_D2/SPI1_MISO/SBK2/BK2 GPP_H11/SML2DATA AE48
This signal has a weak internal pull-down. <52> WWAN_GPIO_PERST# WWAN_BB_RST# BD17 GPP_D22/SPI1_IO3 GPP_H10/SML2CLK BB44 INTRUDER#
0 = Master Attached Flash Sharing (MAFS) enabled (Default) <73> WWAN_BB_RST# GPP_D21/SPI1_IO2 1 OF 13 INTRUDER#
1 = Slave Attached Flash Sharing (SAFS) enabled. CML-H_BGA874 +3V_PCH
Notes:
1. This signal is in the primary well. 6/12 check with BIOS @
Warning: This strap must be configured to ‘ 0’ i f t he

eSPI or LPC strap is configured to ‘ 0’ 1
128@
CH49
PCH_SPI_0_CLK 4.99_0201_1% 2 EMI@ 1 RH1606 SPI_CLK_ROM0 33_0201_1% 2 128@ 1 RH40 SPI_CLK_ROM0_R .1U_0402_16V7K
PCH_SPI_0_D0 4.99_0201_1% 2 1 RH22 SPI_D0_ROM0 33_0201_1% 2 128@ 1 RH42 SPI_D0_ROM0_R 2
PCH_SPI_0_D1 4.99_0201_1% 2 1 RH23 SPI_D1_ROM0 33_0201_1% 2 128@ 1 RH43 SPI_D1_ROM0_R UH4 128@
PCH_SPI_0_D2 4.99_0201_1% 2 1 RH24 SPI_D2_ROM0 33_0201_1% 2 128@ 1 RH1604 SPI_D2_ROM0_R PCH_SPI_0_CS#0 1 8
PCH_SPI_0_D3 4.99_0201_1% 2 1 RH1605 SPI_D3_ROM0 33_0201_1% 2 128@ 1 RH41 SPI_D3_ROM0_R SPI_D1_ROM0_R 2 /CS VCC 7 SPI_D3_ROM0_R
SPI_D2_ROM0_R 3 DO(IO1) /HOLD(IO3) 6 SPI_CLK_ROM0_R
4 /WP(IO2) CLK 5 SPI_D0_ROM0_R
33_0201_1% 2 64@ 1 RH234 SPI_CLK_ROM1_R GND DI(IO0)
33_0201_1% 2 64@ 1 RH232 SPI_D0_ROM1_R W25Q128JVSIQ_SO8
33_0201_1% 2 64@ 1 RH235 SPI_D1_ROM1_R
SPI_D2_ROM1_R
SA00005VV20
33_0201_1% 2 64@ 1 RH230
33_0201_1% 2 64@ 1 RH231 SPI_D3_ROM1_R
128Mb Flash ROM +3V_PCH
ROM_0
UH6 64@ RH562
PCH_SPI_0_CS#1 1 8 1 64@ 2
SPI_D2_ROM1_R 3 CS# VCC 6 SPI_CLK_ROM1_R 0_0402_5%
SPI_CLK_ROM0 SPI_D3_ROM1_R WP# SCLK SPI_D0_ROM1_R 1
7 5 64@
4 HOLD# SI/SIO0 2 SPI_D1_ROM1_R CH4
GND SO/SIO1 0.1U_0201_10V6K
A W25Q64JVSSIQ_SO8 2 A
1
CH244
10P_0402_50V8J @EMI@
SA000039A40
64Mb Flash ROM
2
ROM_1
Close RH1606

PCH (2/7) CLK,SPI,PLTRST
5 4 3 2 1
5 4 3 2 1
+3V_PCH
RH1610 1 2 33_0201_5% HDA_SDOUT +3V_PCH
<73> HDA_SDOUT_R HDA_SYNC
RH1611 1 2 33_0201_5%
<73> HDA_SYNC_R HDA_RST#
RH1035 1 2 4.7K_0201_5% SML0ALERT# RH1612 1 2 33_0201_5%
<73> HDA_RST#_R
EC interface WAKE# RH453 1 2 10K_0201_5%

PCH_BATLOW# RH515 1 2 8.2K_0201_1%
Low(default) LPC
High eSPI 1 2 HDA_BIT_CLK AC_PRESENT RH533 1 2 8.2K_0201_1%
<73> HDA_BIT_CLK_R
RH1031
33_0201_5% WAKE_PCH# RH545 1 @ 2 10K_0201_5%
+3V_PCH
1 EMI@ SYS_RESET# RH571 1 2 8.2K_0201_1%
CH245
RH63 1 @ 2 150K_0201_5% PCH_SML1ALERT# 10P_0201_50V8J
D 2 D
@EMI@
This signal has an internal pull-down.
0 = Disable IntelR DCI-OOB (Default)
1 = Enable IntelR DCI-OOB
1. The internal pull-down is disabled after RSMRST# de-asserts.
2. When used as PCHHOT# and strap low, a 150K +1.8VALW
pull-up is needed to ensure it does not override the
internal pull-down strap sampling. UH1D 1 2 8.2K_0201_1%
CLKRUN# RH85 @
HDA_BIT_CLK BD11 BF36
BE11 HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AV32 CLKRUN# ME_SUS_PWR_ACK RH506 1 @ 2 1M_0201_5%
<73> HDA_SDIN 1 2 1K_0201_5% HDA_SDOUT BF12 HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN#
RH16
+3V_PCH <58> ME_EN HDA_SYNC HDA_SDO/I2S0_TXD
BG13 BF41
HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC
HDA_RST# BE10 BD42
RH95 1 @ 2 4.7K_0201_5% SMBALERT# BF10 HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN#
BE12 HDA_SDI1/I2S1_RXD BB46
I2S1_TXD/SNDW2_DATA DRAM_RESET# H_DRAMRST# <23> PM_SLP_S3#
This signal has a weak internal Pull-down. BD12 BE32 RH1623 1 2 100K_0201_5%
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33
0 = Disable Intel ME Crypto Transport Layer Security GPP_B1/GSPI1_CS1#/TIME_SYNC1 BE29 PM_SLP_S4# RH1624 1 2 100K_0201_5%
(TLS) cipher suite (no confidentiality). (Default) RH39 1 2 30_0201_5% CPU_DISPA_SDO_R AM2 GPP_B0/GSPI0_CS1# R47
<6> CPU_DISPA_SDO AN3 HDACPU_SDO GPP_K17/ADR_COMPLETE AP29 PM_SLP_S5#
1 = Enable Intel ME Crypto Transport Layer Security RH1627 1 @ 2 100K_0201_5%
<6> CPU_DISPA_SDI CPU_DISPA_BCLK_R HDACPU_SDI GPP_B11/I2S_MCLK
RH38 1 2 30_0201_5% AM3 AU3
(TLS) cipher suite (with confidentiality). Must be <6> CPU_DISPA_BCLK HDACPU_SCLK SYS_PWROK SYS_PWROK <58> AC_PRESENT RH1628 1 @ 2 10K_0201_5%
pulled up to support Intel AMT with TLS. WAKE#
BB47 WAKE# RH4 2 @ 1 0_0201_5%
PCIE_WAKE# <52,58,73>
Notes: AV18 BE40
AW18 GPP_D8/I2S2_SCLK GPD6/SLP_A# BF40
1. The internal Pull-down is disabled after RSMRST# BA17 GPP_D7/I2S2_RXD SLP_LAN# BC28
de-asserts. BE16 GPP_D6/I2S2_TXD/MODEM_CLKREQ GPP_B12/SLP_S0# BF42
GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPD4/SLP_S3# PM_SLP_S3# <42,58,62,78,85>
2. This signal is in the primary well. BF15
GPP_D20/DMIC_DATA0/SNDW4_DATA GPD5/SLP_S4#
BE42
PM_SLP_S4# <58,78,88>
BD16 BC42
AV16 GPP_D19/DMIC_CLK0/SNDW4_CLK GPD10/SLP_S5# PM_SLP_S5# <58,62>
LAN_DISABLE_N AW15 GPP_D18/DMIC_DATA1/SNDW3_DATA BE45
<73> LAN_DISABLE_N GPP_D17/DMIC_CLK1/SNDW3_CLK GPD8/SUSCLK PCH_BATLOW# SUSCLK <68,73>
BF44
GPD0/BATLOW# BE35 PCH_BATLOW# <42>
SUSACK# RH1016 2 1 0_0201_5%
GPP_A15/SUSACK# ME_SUS_PWR_ACK PCH_PWR_EN <58,78,89,97>
C BC37 @ C
PCH_RTCRST# BE47 GPP_A13/SUSWARN#/SUSPWRDNACK
<59> PCH_RTCRST# PCH_SRTCRST# RTCRST#
BD46
<59> PCH_SRTCRST# SRTCRST# WAKE_PCH#
BG44 @
AY42 GPD2/LAN_WAKE# BG42 AC_PRESENT 2 1 DH1
<58> PCH_PWROK EC_RSMRST# PCH_PWROK GPD1/ACPRESENT VCIN1_AC_IN <58,62,85,99,112>
BA47 BD39 RB751V40_SC76-2
+RTC_CELL <7,58> EC_RSMRST# RSMRST# SLP_SUS# BE46 PBTN_OUT#
RH1017 2 1 0_0201_5% PCH_DPWROK AW41 GPD3/PWRBTN# AU2 SYS_RESET# PBTN_OUT# <58>
PCH_SRTCRST# DSW_PWROK SYS_RESET# HDA_SPKR SYS_RESET# <7>
RH83 1 2 20K_0201_5% SMBALERT# BE25 AW29
PCH_SMBCLK BE26 GPP_C2/SMBALERT# GPP_B14/SPKR AE3 HDA_SPKR <73>
PCH_SMBDATA GPP_C0/SMBCLK CPUPWRGD H_CPUPWRGD <9>
1 BF26
SML0ALERT# BF24 GPP_C1/SMBDATA AL3
CH52 SML0CLK BF25 GPP_C5/SML0ALERT# ITP_PMODE AH4 XDP_ITP_PMODE <7>
1U_0201_6.3V6M <38,74> SML0CLK SML0DATA BE24 GPP_C3/SML0CLK PCH_JTAGX AJ4 PCH_JTAG_TCK <7,9>
2 <38,74> SML0DATA PCH_SML1ALERT# BD33 GPP_C4/SML0DATA PCH_JTAG_TMS AH3 XDP_TMS <7,9>
GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO XDP_TDO <7,9>
1 1 SML1CLK BF27 AH2 +3VS
SML1DATA BE27 GPP_C6/SML1CLK PCH_JTAG_TDI AJ3 XDP_TDI <7,9>
CH248 CH249 GPP_C7/SML1DATA PCH_JTAG_TCK XDP_TCK <7>
10P_0201_50V8J 10P_0201_50V8J 1 1
4 OF 13
@RF@ 2 2 @RF@ HDA_SPKR RH600 1 @ 2 1K_0201_5%
+RTC_CELL CH250 CH251 CML-H_BGA874
10P_0201_50V8J @
10P_0201_50V8J
RH84 1 2 20K_0201_5% PCH_RTCRST# @RF@ 2 2 @RF@
Top Swap Override
10/2 FR update Reserve
1 0 = Disable ,Top Swap mode. (Default)
1
CH53 CLRP1 1 = Enable, Top Swap mode.

1U_0201_6.3V6M SHORT PADS 10/2 FR update Reserve The internal Pull-down is disabled after PCH_PWROK is high.
2
2
CLRP1 in DIMM door
+3VS +3VS
+3VALW_EC
B B
9/12 DVT1 Modify
1
1
@
2
RH2 RH5
10K_0201_5% 1K_0201_5%
SML1CLK 6 1
EC_SMB_CK2 <30,34,58,64,74,77,102>
2
2
QH5A
5
L2N7002DW1T1G_SC88-6 PBTN_OUT# SYS_RESET#
SML1DATA 3 4
EC_SMB_DA2 <30,34,58,64,74,77,102>
1 1
QH5B
L2N7002DW1T1G_SC88-6 CH174 CH254
0.1U_0201_10V6K 0.1U_0201_10V6K
2 2 @
+3V_PCH
RH460 1 2 1K_0201_5% SML1CLK
RH461 1 2 1K_0201_5% SML1DATA
+3VS
RH501 1 2 499_0201_1% SML0CLK
RH502 1 2 499_0201_1% SML0DATA
A RH463 1 2 1K_0201_5% PCH_SMBCLK A
RH462 1 2 1K_0201_5% PCH_SMBDATA
1 1
10P_0402_50V8J
RH88 1 2 10K_0201_5% EC_RSMRST# CH252

CH253
10P_0402_50V8J
RH90 1 2 100K_0201_5% PCH_DPWROK @RF@ @RF@
2 2

PCH (3/7) PM,HDA,SMB,JTAG
10/2 FR update Reserve AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
UH1B
K34 J3
<6> DMI_CTX_PRX_N0 DMI0_RXN USB2N_1 USB20_N1 <73>
J35 J2 JUSB3 left side (Power Share,Debug Port)
<6> DMI_CTX_PRX_P0 C33 DMI0_RXP USB2P_1 N13 USB20_P1 <73>
<6> DMI_CRX_PTX_N0 DMI0_TXN USB2N_2 USB20_N2 <73>
B33 N15 JIO right side (IO/B) USB1_2.0
D <6> DMI_CRX_PTX_P0 DMI0_TXP USB2P_2 USB20_P2 <73> D
G33 K4
<6> DMI_CTX_PRX_N1 F34 DMI1_RXN USB2N_3 K3 USB20_N3 <74>
<6> DMI_CTX_PRX_P1
C32 DMI1_RXP USB2P_3 M10 USB20_P3 <74> Caldera
<6> DMI_CRX_PTX_N1 B32 DMI1_TXN USB2N_4 L9 USB20_N4 <62>
<6> DMI_CRX_PTX_P1
K32 DMI1_TXP USB2P_4 M1 USB20_P4 <62> AlienFX/ELC
J32 L2 Card reader
<6> DMI_CTX_PRX_P2 C31 DMI2_RXP USB2P_5 K7 USB20_P5 <73>
<6> DMI_CRX_PTX_N2 DMI2_TXN USB2N_6 USB20_N6 <73>
B31 K6 WWAN
<6> DMI_CRX_PTX_P2 G30 DMI2_TXP USB2P_6 L4 USB20_P6 <73>
F30 L3 Digital camera
<6> DMI_CTX_PRX_P3 DMI3_RXP USB2P_7 USB20_P7 <38>
C29 G4
<6> DMI_CRX_PTX_N3 B29 DMI3_TXN USB2N_8 G5 USB20_N8 <73>
<6> DMI_CRX_PTX_P3
A25 DMI3_TXP USB2P_8 M6 USB20_P8 <73> JIO right side (IO/B) USB2_2.0
B25 RSVD4 USB2N_9 N8 USB20_N9 <65>
P24 RSVD5 USB2P_9 H3 USB20_P9 <65> Tobii
R24 RSVD6 USB2N_10 H2 USB20_N10 <64>
C26 RSVD7 USB2P_10 R10 USB20_P10 <64> Per key
B26 RSVD8 USB2N_11 P9 USB20_N11 <44>
F26 RSVD9 USB2P_11 G1 USB20_P11 <44> PD CCG5C +3V_PCH
G26 RSVD10 USB2N_12 G2
B27 RSVD11 USB2P_12 N3 8/28 DVT1 del USB port12 signals
C27 RSVD12 USB2N_13 N2 USB_OC0# RH1019 1 2 10K_0201_5%
L26 RSVD13 USB2P_13 E5 USB_OC1# RH1020 1 2 10K_0201_5%
M26 RSVD14 USB2N_14 F6 USB20_N14 <73> USB_OC2# RH1607 1 2 10K_0201_5%
RSVD15 USB2P_14 USB20_P14 <73> BT
D29
E28 RSVD16 AH36 USB_OC0#
K29 RSVD17 GPP_E9/USB2_OC0# AL40 USB_OC1# USB_OC0# <73>
RSVD18 GPP_E10/USB2_OC1# USB_OC2# USB_OC1# <73>
M29 AJ44
RSVD19 GPP_E11/USB2_OC2# AL41 USB_OC2# <50>
G17 GPP_E12/USB2_OC3# AV47
F16 PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4# AR35
A17 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# AR37
B17 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# AV43
R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
P21 PCIE2_RXN/USB31_8_RXN F4 USB2_COMP RH109 1 2 113_0402_1%
PCIE2_RXP/USB31_8_RXP USB2_COMP +3V_PCH
B18 F3 RH580 1 2 1K_0201_5%
C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13
K18 PCIE2_TXP/USB31_8_TXP RSVD3 G3 RH581 1 2 1K_0402_5%
C C
PCIE3_RXN/USB31_9_RXN USB2_ID
1
J18
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD_7 RH594
C19 PCIE3_TXN/USB31_9_TXN GPD7 100K_0201_5%
N18 PCIE3_TXP/USB31_9_TXP G45 PCIE_PTX_DRX_P24 CH217 1 2 0.22U_0201_6.3V
PCIE4_RXN/USB31_10_RXN PCIE24_TXP PCIE_PTX_DRX_N24 PCIE_PTX_C_DRX_P24 <68>
R18 G46 CH216 1 2 0.22U_0201_6.3V
PCIE_PTX_C_DRX_N24 <68>
2
D20 PCIE4_RXP/USB31_10_RXP PCIE24_TXN Y41
PCIE4_TXN/USB31_10_TXN PCIE24_RXP PCIE_PRX_DTX_P24 <68> GPD_7
C20 Y40
PCIE4_TXP/USB31_10_TXP PCIE24_RXN PCIE_PTX_DRX_P23 PCIE_PRX_DTX_N24 <68>
F20 G48 CH215 1 2 0.22U_0201_6.3V
PCIE5_RXN PCIE23_TXP PCIE_PTX_C_DRX_P23 <68>
1
G20 G49 PCIE_PTX_DRX_N23 CH214 1 2 0.22U_0201_6.3V
PCIE5_RXP PCIE23_TXN PCIE_PTX_C_DRX_N23 <68>
B21 W44 RH11
A22 PCIE5_TXN PCIE23_RXP W43 PCIE_PRX_DTX_P23 <68>
M.2 SSD Slot#2 10K_0201_5%
PCIE5_TXP PCIE23_RXN PCIE_PTX_DRX_P22 PCIE_PRX_DTX_N23 <68>
K21 H48 CH213 2 1 0.22U_0201_6.3V @
PCIE6_RXN PCIE22_TXP PCIE_PTX_DRX_N22 PCIE_PTX_C_DRX_P22 <68>
J21 H47 CH212 2 1 0.22U_0201_6.3V
PCIE_PTX_C_DRX_N22 <68>
2
D21 PCIE6_RXP PCIE22_TXN U41
PCIE6_TXN PCIE22_RXP PCIE_PRX_DTX_P22 <68>
C21 U40
B23 PCIE6_TXP PCIE22_RXN F46 PCIE_PTX_DRX_P21 2 1 0.22U_0201_6.3V PCIE_PRX_DTX_N22 <68>
CH211
PCIE7_TXP PCIE21_TXP PCIE_PTX_DRX_N21 PCIE_PTX_C_DRX_P21 <68>
C23 G47 CH210 2 1 0.22U_0201_6.3V
PCIE7_TXN PCIE21_TXN PCIE_PTX_C_DRX_N21 <68>
J24 R44
L24 PCIE7_RXP PCIE21_RXP T43 PCIE_PRX_DTX_P21 <68>
F24 PCIE7_RXN PCIE21_RXN PCIE_PRX_DTX_N21 <68> X'tal Input:
G24 PCIE8_RXN High: Differential
B24 PCIE8_RXP Low: Single ended
C24 PCIE8_TXN
PCIE8_TXP 2 OF 13
CML-H_BGA874
@
UH1F
F9 BB39 PCH_ESPI_IO0 RH1631 1 2 15_0201_5%
USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 PCH_ESPI_IO1 ESPI_IO0 <58> +1.8VALW
F7 AW37 RH1632 1 2 15_0201_5%
B USB31_1_TXP GPP_A2/LAD1/ESPI_IO1 PCH_ESPI_IO2 ESPI_IO1 <58> B
D11 AV37 RH1633 1 2 15_0201_5%
C11 USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 BA38 PCH_ESPI_IO3 1 2 ESPI_IO2 <58> ESPI_SERIRQ 1 2
RH1634 15_0201_5% RH111 10K_0201_5%
USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 ESPI_IO3 <58>
C3
<73> USB3_PTX_DRX_N2 D4 USB31_2_TXN ESPI_KB_RST# 1 2
RH518 10K_0201_5%
<73> USB3_PTX_DRX_P2 USB31_2_TXP
Card reader B9 BE38
<73> USB3_PRX_DTX_N2 USB31_2_RXN GPP_A5/LFRAME#/ESPI_CS0# ESPI_SERIRQ ESPI_FRAME# <58>
C9 AW35
<73> USB3_PRX_DTX_P2 USB31_2_RXP GPP_A6/SERIRQ/ESPI_CS1# BA36 ESPI_SERIRQ <58>
C17 GPP_A7/PIRQA#/ESPI_ALERT0# BE39 ESPI_KB_RST#
<73> USB3_PTX_DRX_N6 C16 USB31_6_TXN GPP_A0/RCIN#/ESPI_ALERT1# BF38 ESPI_RST# ESPI_KB_RST# <58>
<73> USB3_PTX_DRX_P6 USB31_6_TXP GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RST# <58> +3V_PCH
JUSB1 G14
<73> USB3_PRX_DTX_N6 USB31_6_RXN
F14 BB36 RH89 2 EMI@ 1 22_0201_5%
<73> USB3_PRX_DTX_P6 C15 USB31_6_RXP GPP_A9/CLKOUT_LPC0/ESPI_CLK BB34 CLK_PCI_ESPI <58>
<73>
<73>
USB3_PTX_DRX_N5
USB3_PTX_DRX_P5
B15
J13
USB31_5_TXN
USB31_5_TXP
GPP_A10/CLKOUT_LPC1
T48
5/10 Need Check TBT_RTD3_WAKE# RH1603 2 1 100K_0201_5%
JUSB2 <73> USB3_PRX_DTX_N5 USB31_5_RXN GPP_K19/SMI#
K13 T47 0_0201_5% 2 RTD3@ 1 RT694 1
<73> USB3_PRX_DTX_P5 USB31_5_RXP GPP_K18/NMI# TBT_RTD3_WAKE# <42>
G12 CH246
<74> USB3_PTX_DRX_P3 USB31_3_TXP 10P_0201_50V8J
F11 AH40
<74> USB3_PTX_DRX_N3 C10 USB31_3_TXN GPP_E6/SATA_DEVSLP2 AH35 2
Caldera @EMI@
<74> USB3_PRX_DTX_P3
B10 USB31_3_RXP GPP_E5/SATA_DEVSLP1 AL48
DEVSLP1 <68> FOR SSD1
<74> USB3_PRX_DTX_N3 USB31_3_RXN GPP_E4/SATA_DEVSLP0 AP47
C14 GPP_F9/SATA_DEVSLP7 AN37
<73> USB3_PTX_DRX_P4 USB31_4_TXP GPP_F8/SATA_DEVSLP6
B14 AN46
<73> USB3_PTX_DRX_N4 J15 USB31_4_TXN GPP_F7/SATA_DEVSLP5 AR47
JIO left JUSB3 <73> USB3_PRX_DTX_P4
K16 USB31_4_RXP GPP_F6/SATA_DEVSLP4 AP48
<73> USB3_PRX_DTX_N4 USB31_4_RXN 6 OF 13 GPP_F5/SATA_DEVSLP3 PCH_LCD_TEST <38>
CML-H_BGA874
@
A A

PCH (4/7) DMI,PCIE,USB,LPC
5 4 3 2 1
5 4 3 2 1
+3VS
N18_ID2 N18_ID1 N18_ID0
Samsung_8G S_8G@ S_8G@ S_8G@ S_8G@ S_8G@ N18P-G0 N18PG0@ N18PG0@ N18PG0@ GPU_ID
RH1024 RH1025 RH1027 RH1029 RH1635 RH1609 RH26 RH27 (BF14) (AR18) (BF17)
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
BT_OFF#
10K_0201_5% 10K_0201_5% 10K_0201_5% N18E-G3 H L H
RH517 1 @ 2 8.2K_0201_5%
1 2 WL_OFF#
Samsung_16G S_16G@ S_16G@ S_16G@ S_16G@ S_16G@ RH520 @ 8.2K_0201_5%
EC_SCI#
N18E-G3 N18EG3@ N18EG3@ N18EG3@ N18E-G2 H L L
RH1024 RH1025 RH1028 RH1029 RH1635 RH521 1 2 10K_0201_5% RH1608 RH26 RH27
2 1 UART_2_PRXD_DTXD
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% RC62 49.9K_0201_1%
UART_2_PTXD_DRXD
10K_0201_5% 10K_0201_5% 10K_0201_5% N18E-G1 L H H
RC63 2 1 49.9K_0201_1%
1 2 SD_WP#
Samsung_32G S_32G@ S_32G@ S_32G@ S_32G@ S_32G@ RH1626 @ 10K_0201_5% N18E-G2 N18EG2@ N18EG2@ N18EG2@ N18E-G0 L H L
RH1024 RH1025 RH1027 RH1030 RH1635 RH1608 RH26 RH28
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% N18P-G0 L L H
Hynix_8G H_8G@ H_8G@ H_8G@ H_8G@ H_8G@ N18E-G1 N18EG1@ N18EG1@ N18EG1@ Navi 14 XTM L L L
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
+3V_PCH
Hynix_16G H_16G@ H_16G@ H_16G@ H_16G@ H_16G@ N18E-G0 N18EG0@ N18EG0@ N18EG0@
D D
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
2
H_32G@ H_32G@ H_32G@ H_32G@ H_32G@ AMD@ AMD@ AMD@
Hynix_32G RH1023 RH1025 RH1027 RH1030 RH1635 Navi 14 XTM RH1609 RH26 RH28 RH1608 RH25 RH27 RH29
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% @ 10K_0201_5% @ 10K_0201_5% @ 10K_0201_5% @ 10K_0201_5%
M_8G@ M_8G@ M_8G@ M_8G@ M_8G@
1
Micron_8G(ODIE) RH1024 RH1026 RH1027 RH1029 RH1635
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% DGPU_ID2
DGPU_ID1
M_8G1@ M_8G1@ M_8G1@ M_8G1@ M_8G1@ DGPU_ID0
RH1024 RH1026 RH1027 RH1029 RH1636 GSYNC_ID
Micron_8G(NDIE)
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
2
M_16G@ M_16G@ M_16G@ M_16G@ M_16G@
Micron_16G(ODIE) RH1024 RH1026 RH1028 RH1029 RH1635 RH1609 RH26 RH28 RH30
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% @ 10K_0201_5% @ 10K_0201_5% @ 10K_0201_5% 10K_0201_5%
M_16G1@ M_16G1@ M_16G1@ M_16G1@ M_16G1@
1
Micron_16G(NDIE) RH1024 RH1026 RH1028 RH1029 RH1636
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
M_32G@ M_32G@ M_32G@ M_32G@ M_32G@

Micron_32G(ODIE) RH1024 RH1026 RH1027 RH1030 RH1635
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
+3VS
DGPU_PWR_EN RH537 1 2 10K_0201_5%
+1.8VALW +3V_PCH
C
BOARD_ID RH21 1 NV@ 2 10K_0201_5% C
RH595 2 1 10K_0201_5% CNV_RGI_PTX_DRX
UH1K BOARD_ID RH1601 1 @ 2 10K_0201_5%
RH168 2 @ 1 10K_0201_5% BBS_BIT0 BA26
BD30 GPP_B22/GSPI1_MOSI BA20 BOARD_ID
<62> ELC_RESET EC_SCI# GPP_B21/GSPI1_MISO GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
AU26 BB20
<58> EC_SCI# AW26 GPP_B20/GSPI1_CLK GPP_D10/ISH_SPI_CLK/GSPI2_CLK BB16 PEX_RST#
M.2 CNV Mode Select <58> EC_INT# GPP_B19/GSPI1_CS0# GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO DGPU_PWR_EN PEX_RST# <27> +3VS
AN18
NRB_BIT GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI DGPU_PWR_EN <32,37,58>
BE30
BD29 GPP_B18/GSPI0_MOSI BF14 DGPU_ID2 I2C_0_SDA RH1617 1 2 10K_0201_5%
An external pull-up or pull-down is required. <62> ELC_BOOT_MODE
BF29 GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18 DGPU_ID1 I2C_0_SCL RH1618 1 2 10K_0201_5%
0 = Integrated CNVi enable. <30> GC6_FB_EN BB26 GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN BF17 DGPU_ID0
<30> GC6_EVENT# GPP_B15/GSPI0_CS0# GPP_D14/ISH_UART0_TXD/I2C2_SCL GSYNC_ID
1 = Integrated CNVi disable. GPP_D13/ISH_UART0_RXD/I2C2_SDA
BE17
Pulled down by CRF CNVi RGI_DT pin BB24
<38,58> EDP_SW BE23 GPP_C9/UART0A_TXD
WL_OFF# AP24 GPP_C8/UART0A_RXD +3V_PCH
<73> WL_OFF# BT_OFF# BA24 GPP_C11/UART0A_CTS#
<73> BT_OFF#
BD21 GPP_C10/UART0A_RTS# To G+Gyro sensor BBS_BIT0 RH130 2 @ 1 1K_0402_5%
+1.8VALW <40> HDMI_HPD_PCH GPP_C15/UART1_CTS#/ISH_UART1_CTS#
AW24 AG45
<39> DP_HPD_PCH AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_H20/ISH_I2C0_SCL1 AH46 ISH_I2C0_SCL <65>
<30> DP1_HPD_PCH GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H19/ISH_I2C0_SDA ISH_I2C0_SDA <65> Boot BIOS Strap Bit (internal PD)
AU24
<30> DP2_HPD_PCH GPP_C12/UART1_RXD/ISH_UART1_RXD AH47
AV21 GPP_H22/ISH_I2C1_SCL AH48
1 2 4.7K_0402_5% CNV_BRI_PTX_DRX <42> TBT_CIO_PLUG_EVENT#
AW21 GPP_C23/UART2_CTS# GPP_H21/ISH_I2C1_SDA HIGH LPC
RH603
UART_2_PTXD_DRXD BE20 GPP_C22/UART2_RTS# LOW(DEFAULT) SPI
<58> UART_2_PTXD_DRXD UART_2_PRXD_DTXD GPP_C21/UART2_TXD PCH_ACC1_INT1
This signal has a weak internal pull-down 20K. BD20 AV34
GPP_C20/UART2_RXD GPP_A23/ISH_GP5 AW32 PCH_GYRO_INT2 PCH_ACC1_INT1 <65>
0 = 38.4/19.2MHz XTAL frequency selected. I2C_1_SCL BE21 GPP_A22/ISH_GP4 BA33
PCH_GYRO_INT2 <65>
1 = 24MHz XTAL frequency selected. <58> I2C_1_SCL I2C_1_SDA BF21 GPP_C19/I2C1_SCL GPP_A21/ISH_GP3 BE34 +3V_PCH
<58> I2C_1_SDA I2C_0_SCL BC22 GPP_C18/I2C1_SDA GPP_A20/ISH_GP2 BD34 ISH_GP1
Notes: <63> I2C_0_SCL I2C_0_SDA GPP_C17/I2C0_SCL GPP_A19/ISH_GP1 ISH_GP1 <58> NRB_BIT
BF23 BF35 RH524 2 @ 1 1K_0201_5%
1. The internal pull-down is disabled after RSMRST# <63> I2C_0_SDA GPP_C16/I2C0_SDA GPP_A18/ISH_GP0 BD38
de-asserts. BE15 GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
<58,63> TP_INT# GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4/BK4
2. This signal is in the primary well. BE14
GPP_D23/ISH_I2C2_SCL/I2C3_SCL 11 OF 13 NO REBOOT mode (internal PD)
CML-H_BGA874
+1.8VALW
@ HIGH Enable
B LOW(DEFAULT) Disable B
RH218 2 @ 1 10K_0402_5% GPP_J9
The signal has a weak internal pull-down SD_READ_MODE SD_WP# DDRID STRAP +3VS
RH55 1 2 0_0201_5%
0 = VCCPSPI is connected to 3.3V rail <73> SD_READ_MODE
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin
strap must be a 1 for the proper functionality
1
of the SPI (Flash) I/Os DDRID_0
UH1M @ @ @ @ @ @
AW13 BD4 RH1023 RH1026 RH1028 RH1030 RH1636 RH1638
DDRID_1 BE9 GPP_G0/SD_CMD CNV_WR_CLKN BE3 10K_0201_5%
GPP_G1/SD_DATA0 CNV_WR_CLKP 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
DDRID_2 BF8
2
DDRID_3 BF9 GPP_G2/SD_DATA1 BB3 DDRID_0
+1.8VALW DDRID_4 BG8 GPP_G3/SD_DATA2 CNV_WR_D0N BB4 DDRID_1
DDRID_5 BE8 GPP_G4/SD_DATA3 CNV_WR_D0P BA3 DDRID_2
BD8 GPP_G5/SD_CD# CNV_WR_D1N BA2 DDRID_3
RH181 1 @ 2 20K_0402_1% CNV_BRI_PRX_DTX SD_WP# AV13 GPP_G6/SD_CLK CNV_WR_D1P DDRID_4
GPP_G7/SD_WP BC5 DDRID_5
RH182 1 @ 2 20K_0402_1% CNV_RGI_PRX_DTX RTC_DET# AP3 CNV_WT_CLKN BB6
<82> RTC_DET# GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP
1
AP2
<42> RTD3_USB_PWR_EN GPP_I12/M2_SKT2_CFG1
571391_CFL_H_PDG_Rev0p71 AN4 BE6 @ @ @ @ @ @
AM7 GPP_I13/M2_SKT2_CFG2 CNV_WT_D0N BD7 RH1024 RH1025 RH1027 RH1029 RH1635 RH1637
To avoid floating input at the I/O pin BRI_RSP and GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P BG6 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
RGI_RSP it is recommended to add a weak pull up AV6 CNV_WT_D1N BF6
2
GPP_J0/CNV_PA_BLANKING CNV_WT_D1P CNV_WT_RCOMP
resistor to the SoC pin with a recommended value of AY3
GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP
BA1 RH213 1 2 150_0201_1%
AR13
20K ohm. AV7 GPP_J11/A4WP_PRESENT B12 PCIE_RCOMPN RH193 1 2 100_0402_1%
AW3 GPP_J10 PCIE_RCOMPN A13 PCIE_RCOMPP
AT10 GPP_J2 PCIE_RCOMPP BE5 SD_RCOMP_1P8 RH214 1 2 200_0402_1%
CNV_BRI_PTX_DRX AV4 GPP_J3 SD_1P8_RCOMP BE4 SD_RCOMP_3P3 RH215 1 2 200_0402_1%
CNV_BRI_PRX_DTX AY2 GPP_J4/CNV_BRI_DT/UART0B_RTS# SD_3P3_RCOMP BD1
For BIOS UART debug CNV_RGI_PTX_DRX BA4 GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P81 BE1
CNV_RGI_PRX_DTX GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82 GPPJ_RCOMP_1P8
Vendo r DDRID_0 DDRID_1 Vendo r DDRID_2 DDRID_3 Vendo r DDRID_4 DDRID_5
AV3 BE2 RH216 1 2 200_0201_1%
AW2 GPP_J7/CNV_RGI_RSP/UART0B_CTS# GPPJ_RCOMP_1P83
A
GPP_J9 GPP_J8/CNV_MFUART2_RXD Samsung L L 8G L L 8G RSVD A
AU9 Y35 L(1st die)
+5VALW GPP_J9/CNV_MFUART2_TXD RSVD28 Y36
RSVD29 Hynix H L 16G H L 16G RSVD
H(2nd die)
BC1 Micron L H 32G L H 32G RSVD
JWDB RSVD30 AL35 T135 PAD~D @
1 13 OF 13 TP
1 2 UART_2_PTXD_DRXD
5 2 3 UART_2_PRXD_DTXD
6 G1 3 4 CML-H_BGA874
G2 4 @
ACES_88266-04001
CONN@ 2017/05/15 2018/02/05 Title
Issued Date Deciphered Date
PCH (5/7) I2C,GPIO
5 4 3 2 1
5 4 3 2 1
+1VALW +3V_PCH
UH1H
AA22 AW9
AA23 VCCPRIM_1P051 VCCPRIM_3P32
AB20 VCCPRIM_1P052 BF47
VCCPRIM_1P053 DCPRTC1 +VCCRTCEXT
AB22 BG47
+1VALW @ +1V_PCH AB23 VCCPRIM_1P054 DCPRTC2
AB27 VCCPRIM_1P055 V23
D JP1 VCCPRIM_1P056 VCCPRIM_3P35 D
AB28 AN44
1 2 AB30 VCCPRIM_1P057 VCCSPI
AD20 VCCPRIM_1P058 BC49 20mil
AD23 VCCPRIM_1P059 VCCRTC1 BD49 1 2 +RTC_CELL
PAD-OPEN 43x39
+1V_MPHY AD27 VCCPRIM_1P0510 VCCRTC2 20mil CH226 0.1U_0402_10V7K
AD28 VCCPRIM_1P0511 AN21
AD30 VCCPRIM_1P0512 VCCPGPPG_3P3 AY8
RH12 1 2 0_0805_5% AF23 VCCPRIM_1P0513 VCCPRIM_3P33 BB7
AF27 VCCPRIM_1P0516 VCCPRIM_3P34
AF30 VCCPRIM_1P0517 AC35
U26 VCCPRIM_1P0518 VCCPGPPHK1 AC36
U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35
V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36
+1.05V_VCCPRIM V27 VCCPRIM_1P0525 VCCPGPPEF2
V28 VCCPRIM_1P0526 AN24
V30 VCCPRIM_1P0527 VCCPGPPD AN26 +VCCDSW +1.8VALW
+1V_PCH V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26
VCCPRIM_1P0529 VCCPGPPBC2 +3VALW +3V_PCH
1
CH265 AD31 AN32
47U_0805_6.3V6M AE17 VCCPRIM_1P0514 VCCPGPPA
+1V_VCCDSW VCCPRIM_1P0515 AT44
2 20mil W22 VCCPRIM_3P31 BE48 15mil RH6 1 @ 2 0_0402_5%
20mil W23 VCCDUSB_1P051 VCCDSW_3P31 BE49 15mil RH7 1 2 0_0402_5%
+1V_MPHY VCCDUSB_1P052 VCCDSW_3P32
20mil BG45 BB14
VCCDSW_1P051 VCCHDA
10P_0402_50V8J
20mil BG46 AG19
W31 VCCDSW_1P052 VCCPRIM_1P81 AG20
Close to E1, D1 VCCPRIM_MPHY_1P05 VCCPRIM_1P82 1
CH231
@RF@
13.2A +1.05V_VCCPRIM AN15 +VCCPHVLDO +1.8VALW
+1.05V_VCCAMPHYPLL D1 VCCPRIM_1P83 AR15
LH2 VCCPRIM_1P0521 VCCPRIM_1P84
LH3 1 2 E1 BB11 1 2
1 2 2.2UH_FCI1608F-2R2K_10% C49 VCCPRIM_1P0522 VCCPRIM_1P85 2
2.2UH_FCI1608F-2R2K_10% D49 VCCAMPHYPLL_1P051 AF19 20mil RH599
+1.05V_XTAL +1.05V_VCCAMPHYPLL +1.05V_XTAL E49 VCCAMPHYPLL_1P052 VCCPHVLDO_1P81 AF20 20mil RH598 1 @ 2 0_0402_5% 0_0402_5%
LH1 VCCAMPHYPLL_1P053 VCCPHVLDO_1P82 +VCCPHVLDO
1 2 P2 AG31 20mil
+1VALW
2.2UH_FCI1608F-2R2K_10% P3 VCCA_XTAL_1P051 VCCPRIM_1P0520 AF31 20mil
W19 VCCA_XTAL_1P052 VCCPRIM_1P0519 AK22 10mil T145 PAD~D @
1 1 VCCA_SRC_1P051 VCCDPHY_1P243
C CH264 CH263 W20 AK23 10mil C
47U_0805_6.3V6M 47U_0805_6.3V6M VCCA_SRC_1P052 VCCDPHY_1P244 40mil
C1 AJ22 10mil
2 2 C2 VCCAPLL_1P054 VCCDPHY_1P241 AJ23 10mil
V19 VCCAPLL_1P055 VCCDPHY_1P242 BG5 T146 PAD~D @
VCCA_BCLK_1P05 VCCDPHY_1P245
B1 K47 15mil
VCCAPLL_1P051 VCCMPHY_SENSE
4.7U_0402_6.3V6M
B2 K46 1
B3 VCCAPLL_1P052 VSSMPHY_SENSE
Close to P2, P3 Close to C49, D49, E49 VCCAPLL_1P053
CH36
8 OF 13
CML-H_BGA874 2
@
+1V_MPHY +1VALW +1V_MPHY +1VALW +VCCPHVLDO +3V_PCH +3V_PCH

1U_0402_6.3V6K
22UF_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
1 1 1 1 1 1 1 1
CH82
CH181
CH180
CH187
CH188
CH176
CH190
CH192
2 2 2 2 2 2 2 2
B B
Close to B1,B2,B3,C1,C2 Close to U26,U29V25,V27,V28,V30,V31 Close to C49,D49,E49 Close to AF31,AG31,AD31,AA22,AA23 Close to AG19,AG20 Close to AE35,AE36 Close to AC35,AC36
,AB20,AB22,AB23,AB27,AB28,AB30 ,AR15,AN15,BB11
,AD20,AD23,AD27,AD28,AD30,AF23
,AF27,AF30,AE17
+VCCPHVLDO
+3V_PCH +3V_PCH +RTC_CELL +1VALW
4.7U_0603_6.3V6M
1U_0603_10V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
1
0.1U_0402_10V7K
CH233
1 1 1 1 1 @
CH182
CH80
CH173
CH186
CH259
4.7U_0402_10V6K 2
2 2 2 2 2
A A
Close to AG19,AG20
Close to AY8,BB7 Close to BE48,BE49 Close to BC49,BD49 Close to E1,D1 ,AR15,AN15,BB11

PCH (6/7) PWR
5 4 3 2 1
5 4 3 2 1
D D
UH1L
UH1I BG3 M24
A2 AL12 BG33 VSS145 VSS196 M32
A28 VSS1 VSS73 AL17 BG37 VSS146 VSS197 M34
A3 VSS2 VSS74 AL21 BG4 VSS147 VSS198 M49
A33 VSS3 VSS75 AL24 BG48 VSS148 VSS199 M5 UH1J
A37 VSS4 VSS76 AL26 C12 VSS149 VSS200 N12 Y14
A4 VSS5 VSS77 AL29 C25 VSS150 VSS201 N16 RSVD20 Y15
A45 VSS6 VSS78 AL33 C30 VSS151 VSS202 N34 RSVD21 U37
A46 VSS7 VSS79 AL38 C4 VSS152 VSS203 N35 RSVD22 U35
A47 VSS8 VSS80 AM1 C48 VSS153 VSS204 N37 RSVD23
A48 VSS9 VSS81 AM18 C5 VSS154 VSS205 N38 N32
A5 VSS10 VSS82 AM32 D12 VSS155 VSS206 P26 RSVD24 R32
A8 VSS11 VSS83 AM49 D16 VSS156 VSS207 P29 RSVD25
AA19 VSS12 VSS84 AN12 D17 VSS157 VSS208 P4 AH15
AA20 VSS13 VSS85 AN16 D30 VSS158 VSS209 P46 RSVD26 AH14
AA25 VSS14 VSS86 AN34 D33 VSS159 VSS210 R12 RSVD27
AA27 VSS15 VSS87 AN38 D8 VSS160 VSS211 R16
AA28 VSS16 VSS88 AP4 E10 VSS161 VSS212 R26
AA30 VSS17 VSS89 AP46 E13 VSS162 VSS213 R29 AL2
AA31 VSS18 VSS90 AR12 E15 VSS163 VSS214 R3 PREQ# AM5 XDP_PREQ# <7,9>
AA49 VSS19 VSS91 AR16 E17 VSS164 VSS215 R34 PRDY# AM4 XDP_PRDY# <7,9>
AA5 VSS20 VSS92 AR34 E19 VSS165 VSS216 R38 CPU_TRST# AK3 CPU_XDP_TRST# <7,9>
AB19 VSS21 VSS93 AR38 E22 VSS166 VSS217 R4 TRIGGER_OUT AK2 PCH_TRIGGER <10>
AB25 VSS22 VSS94 AT1 E24 VSS167 VSS218 T17 TRIGGER_IN CPU_TRIGGER <10>
AB31 VSS23 VSS95 AT16 E26 VSS168 VSS219 T18 10 OF 13
AC12 VSS24 VSS96 AT18 E31 VSS169 VSS220 T32
C AC17 VSS25 VSS97 AT21 E33 VSS170 VSS221 T4 CML-H_BGA874 C
AC33 VSS26 VSS98 AT24 E35 VSS171 VSS222 T49 @
AC46 VSS29 VSS101 AT32 E8 VSS174 VSS225 U12
AD1 VSS30 VSS102 AT34 F41 VSS175 VSS226 U15
AD19 VSS31 VSS103 AT45 F43 VSS176 VSS227 U17
AD2 VSS32 VSS104 AV11 F47 VSS177 VSS228 U21
AD22 VSS33 VSS105 AV39 G44 VSS178 VSS229 U24
AD25 VSS34 VSS106 AW10 G6 VSS179 VSS230 U33
AD49 VSS35 VSS107 AW4 H8 VSS180 VSS231 U38
AE12 VSS36 VSS108 AW40 J10 VSS181 VSS232 V20
AE33 VSS37 VSS109 AW46 J26 VSS182 VSS233 V22
AE38 VSS38 VSS110 B47 J29 VSS183 VSS234 V4
AE4 VSS39 VSS111 B48 J4 VSS184 VSS235 V46
AE46 VSS40 VSS112 B49 J40 VSS185 VSS236 W25
AF22 VSS41 VSS113 BA12 J46 VSS186 VSS237 W27
AG1 VSS44 VSS116 BA5 J9 VSS189 VSS240 Y10
AG22 VSS45 VSS117 BA6 K11 VSS190 VSS241 Y12
AG23 VSS46 VSS118 BB41 K39 VSS191 VSS242 Y17
AG25 VSS47 VSS119 BB43 M16 VSS192 VSS243 Y33
AG27 VSS48 VSS120 BB9 M18 VSS193 VSS244 Y38
AG28 VSS49 VSS121 BC10 M21 VSS194 VSS245 Y9
AG30 VSS50 VSS122 BC13 VSS195 VSS246
AG49 VSS51 VSS123 BC15 12 OF 13
AH12 VSS52 VSS124 BC19
AH17 VSS53 VSS125 BC24 CML-H_BGA874
AH33 VSS54 VSS126 BC26 @
AH38 VSS55 VSS127 BC31
AJ19 VSS56 VSS128 BC35
B AJ20 VSS57 VSS129 BC40 B
AJ28 VSS60 VSS132 BD43
AJ30 VSS61 VSS133 BE44
AJ31 VSS62 VSS134 BF1
AK19 VSS63 VSS135 BF2
AK28 VSS67 VSS139 BG17
VSS72 VSS144
9 OF 13
CML-H_BGA874
@
A A

PCH (7/7) VSS
0.2
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

0.2
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

0.2
5 4 3 2 1
5 4 3 2 1
DDR4 Memory Down_CHA <8,24>
<8,24>
DDR_A_MA[0..16]
DDR_A_DQS[0..7]
<8,24> DDR_A_DQS#[0..7]
Non-Interleave Memory <8,24> DDR_A_D[0..63]
DDR4 Memory Down_CHA

D D
+1.2V_DDR Closed to UD1

VDD DECAPS (1UF x3 / 10UF x1)
Closed to UD2 VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1)
VDDQ DECAPS (1UF x2 / 10UF x1) VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1) VDD DECAPS (1UF x3 / 10UF x1)
VDDQ DECAPS (1UF x2 / 10UF x1)
SOC side Memory side +1.2V_DDR +2.5V_MEM +0.6VS
1
+1.2V_DDR +2.5V_MEM +0.6VS

RD160
1.8K_0402_1%
@RF@ CD378
@RF@ CD379
@RF@ CD380
100P_0201_50V8J
CD265
CD266
CD267
CD268
CD269
10U_0402_6.3V6M
10U_0402_6.3V6M
CD279
CD280
10U_0402_6.3V6M
100P_0201_50V8J
CD285
CD286
10U_0402_6.3V6M
100P_0201_50V8J
@RF@ CD381
@RF@ CD382
@RF@ CD383
2
RD161
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
100P_0201_50V8J
CD270
CD271
CD272
CD274
CD302
10U_0402_6.3V6M
10U_0402_6.3V6M
CD282
CD283
10U_0402_6.3V6M
100P_0201_50V8J
CD288
CD289
10U_0402_6.3V6M
100P_0201_50V8J
1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD276
CD277
CD281
CD287
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
+0.6V_VREFCA +0.6V_DDR_VREFCA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD273
CD278
CD284
CD290
1 2.7_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CD291 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1
0.022U_0402_16V7K
2
RD162
1.8K_0402_1%
1
RD159
24.9_0402_1%
2
All VREF traces should

have 10 mil trace width
VREF traces should be at least 20 mils wide
with 20 mils spacing to other signals/planes. +0.6V_DDR_VREFCA
+0.6V_DDR_VREFCA
UD1
UD2
M1 G2 DDR_A_D16
VREFCA DQL0 F7 DDR_A_D22 M1 G2 DDR_A_D54
1 DQL1 H3 DDR_A_D17 VREFCA DQL0 F7 DDR_A_D52
0.047U_0402_25V7K
CD292
DDR_A_MA0 P3 DQL2 H7 DDR_A_D19 1 DQL1 H3 DDR_A_D50
0.047U_0402_25V7K
CD264
DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D20 DDR_A_MA0 P3 DQL2 H7 DDR_A_D51
DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D23 DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D49
2 DDR_A_MA3 A2 DQL5 DDR_A_D21 DDR_A_MA2 A1 DQL4 DDR_A_D53
C N7 J3 R3 H8 C
DDR_A_MA4 A3 DQL6 DDR_A_D18 2 DDR_A_MA3 A2 DQL5 DDR_A_D48
N3 J7 N7 J3
DDR_A_MA5 P8 A4 DQL7 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D55
DDR_A_MA6 P2 A5 DDR_A_MA5 P8 A4 DQL7
DDR_A_MA7 R8 A6 A3 DDR_A_D26 DDR_A_MA6 P2 A5
DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D31 DDR_A_MA7 R8 A6 A3 DDR_A_D62
DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D30 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D63
DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D27 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D59
DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D24 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D58
DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D28 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D57
DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D25 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D61
DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D29 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D60
A14/WE DQU7 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D56
DDR_A_BA0 +1.2V_DDR A14/WE DQU7
N2 +1.2V_DDR
<8,24> DDR_A_BA0 DDR_A_BA1 N8 BA0 B3 DDR_A_BA0 N2
+1.2V_DDR <8,24> DDR_A_BA1 BA1 VDD B9 DDR_A_BA1 N8 BA0 B3
VDD +1.2V_DDR BA1 VDD
40mil E2 D1 B9
E7 DMU/DBIU VDD G7 40mil E2 VDD D1
DML/DBIL VDD J1 E7 DMU/DBIU VDD G7
VDD J9 DML/DBIL VDD J1
VDD L1 VDD J9
DDR_A_CLK0 K7 VDD L9 VDD L1
UD1
<8,24> DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD DDR_A_CLK0 VDD
K8 R1 RD230 K7 L9
<8,24> DDR_A_CLK#0 DDR_A_CKE0 K2 CK_c VDD T9 DDR_A_CLK#0 K8 CK_t VDD R1
<8,24> DDR_A_CKE0 CKE VDD DDR_A_CKE0 K2 CK_c VDD T9
CKE VDD RD231
A1
VDDQ A9 A1
D4 512M16 MT40A512M16TB-062E:J S VDDQ VDDQ
SA0000CMS0L C1 0_0402_5% A9
MCN8G1@ VDDQ D9 SD028000080 VDDQ C1
VDDQ F2 SDP8G@ VDDQ D9
VDDQ F8 VDDQ F2
DDR_A_ODT0 VDDQ VDDQ 0_0402_5%
K3 G1 F8 SD028000080
<8,24> DDR_A_ODT0 DDR_A_CS#0 L7 ODT VDDQ G9 DDR_A_ODT0 K3 VDDQ G1
UD2 SDP8G@
<8,24> DDR_A_CS#0 DDR_A_MA16 L8 CS VDDQ J2 RD230 BOM control for DDP@ to 240R /SDP@ to 0R DDR_A_CS#0 L7 ODT VDDQ G9
DDR_A_MA15 M8 RAS VDDQ J8 DDR_A_MA16 L8 CS VDDQ J2 RD231 BOM control for DDP@ to 240R /SDP@ to 0R
CAS VDDQ DDR_A_MA15 M8 RAS VDDQ J8
RD230 CAS VDDQ
B2
VSS E1 240_0402_1% B2 RD231
VSS E9 15mil 2 DDP16G@1 VSS E1 15mil 240_0402_1%
D4 512M16 MT40A512M16TB-062E:J S VSS VSS DDP16G@
SA0000CMS0L G8 E9 2 1
DDR_A_DQS#3 A7 VSS K1 VSS G8
MCN8G1@
DDR_A_DQS3 B7 DQSU_c VSS K9 DDR_A_DQS#7 A7 VSS K1
DDP16G@
DDR_A_DQS#2 F3 DQSU_t VSS M9 DDR_A_BG1_R1 2 0_0201_5% DDR_A_BG1 DDR_A_DQS7 DQSU_c VSS
RD2381 B7 K9 DDP16G@
DDR_A_DQS2 G3 DQSL_c VSS N1 DDR_A_BG1 <8,24> DDR_A_DQS#6 F3 DQSU_t VSS M9 DDR_A_BG1_R2 2 0_0201_5% DDR_A_BG1
RD2401
DQSL_t VSS T1 DDR_A_DQS6 G3 DQSL_c VSS N1
SDP8G@
DDR_DRAMRST#_R P1 VSS DQSL_t VSS
RD2391 2 0_0201_5% T1 SDP8G@
RESET DDR_DRAMRST#_R P1 VSS
UD1 UD1 UD1 RD2411 2 0_0201_5%
RD157 2 1 240_0402_1% F9 RESET
15mil ZQ RD158 2 1 240_0402_1% F9
B 15mil ZQ B
DDR_A_ACT# L3 A2
<8,24> DDR_A_ACT# DDR_A_BG0 ACT VSSQ DDR_A_ACT#
M2 A8 L3 A2
<8,24> DDR_A_BG0 N9 BG0 VSSQ C9 DDR_A_BG0 M2 ACT VSSQ A8
D4 512M16/2666 H5AN8G6NCJR-VKC FBGA D4 8G/2666 MT40A512M16LY-075:E FBGA D4 512M16 K4A8G165WC-BCTD FBGA 96P DDR_A_ALERT# TEN VSSQ BG0 VSSQ
SA0000BMN0L SA0000ARD0L SA0000B6F0L P9 D2 N9 C9
<8,24> DDR_A_ALERT# DDR_A_PARITY ALERT VSSQ DDR_A_ALERT# TEN VSSQ
HYX8G@ MCN8G@ SAM8G@ T3 D8 P9 D2
<8,24> DDR_A_PARITY PAR VSSQ E3 DDR_A_PARITY T3 ALERT VSSQ D8
RD256 1 @ 2 0_0201_5% T7 VSSQ E8 PAR VSSQ E3
40mil B1 NC VSSQ F1 RD257 1 @ 2 0_0201_5% T7 VSSQ E8
UD2 UD2 UD2 R9 VPP VSSQ H1 40mil B1 NC VSSQ F1
RD256
+2.5V_MEM VPP VSSQ H9 R9 VPP VSSQ H1
96-BALL VSSQ +2.5V_MEM VPP VSSQ H9
SDRAM DDR4 96-BALL VSSQ
K4A8G165WB-BCPB_FBGA96 RD257 SDRAM DDR4
@ K4A8G165WB-BCPB_FBGA96
D4 512M16/2666 H5AN8G6NCJR-VKC FBGA D4 8G/2666 MT40A512M16LY-075:E FBGA D4 512M16 K4A8G165WC-BCTD FBGA 96P @
SA0000BMN0L SA0000ARD0L SA0000B6F0L 0_0201_5%
HYX8G@ MCN8G@ SAM8G@ SD043000080
HMO16S32@ 08/23, change PCP Footprint to MT40A2G16SKL-062E-B_FBGA_96P 08/23, change PCP Footprint to MT40A2G16SKL-062E-B_FBGA_96P
0_0201_5%
SD043000080
HMO16S32@
UD1 UD1 UD1 UD1
D4 16G/2666 H5ANAG6NCMR-VKC FBGA96P D4 16G/2666 MT40A1G16KNR-075:E D4 16G/2666 K4AAG165WB-MCTD FBGA96P D4 16G/3200 MT40A1G16KD-062E:E
SA0000BZJ0L SA0000BC70L SA0000B9K0L SA0000D3U0L
HYX16G@ MCN16G@ SAM16G@ MCN16G1@ +1.2V_DDR
DDR_DRAMRST#_R
UD2 UD2 UD2 UD2
1
2
RD35 CD111
470_0402_1% 0.1U_0402_10V6K
D4 16G/2666 H5ANAG6NCMR-VKC FBGA96P D4 16G/2666 MT40A1G16KNR-075:E D4 16G/2666 K4AAG165WB-MCTD FBGA96P D4 16G/3200 MT40A1G16KD-062E:E @ESD@
SA0000BZJ0L SA0000BC70L SA0000B9K0L SA0000D3U0L 1
2
HYX16G@ MCN16G@ SAM16G@ MCN16G1@
9/18 DVT1 Modify DDR_DRAMRST#_R 1 2

PLACE NEAR TO UD1,UD2
<24,25,26> DDR_DRAMRST#_R H_DRAMRST# <16>
.1U_0402_16V7K
RD31
UD1 UD1 1 0_0402_5%
CD69
@ESD@
A A
3
2 ESD@
DT16
D4 32G/3200 MT40A2G16SKL-062E:B FBGA 96P D4
S 32G/2666 K4ABG165WA-MCTD FBGA96P CEST523NC5VB_SOT-523-3
SA0000CYF0L SA0000CHM0L
MCN32G@ SAM32G@ SCA00004700
1
UD2 UD2
D4 32G/3200 MT40A2G16SKL-062E:B FBGA 96P S D4 32G/2666 K4ABG165WA-MCTD FBGA96P Compal Secret Data
SA0000CYF0L
MCN32G@
SA0000CHM0L
SAM32G@
Security Classification
2017/04/07 2018/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.2
5 4 3 2 1
5 4 3 2 1
DDR4 Memory Down_CHA <8,23> DDR_A_MA[0..16]
Non-Interleave Memory <8,23>
<8,23>
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
<8,23> DDR_A_D[0..63]
D D
Closed to UD3 Closed to UD4

VDD DECAPS (1UF x3 / 10UF x1) VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1) VDD DECAPS (1UF x3 / 10UF x1) VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1)
VDDQ DECAPS (1UF x2 / 10UF x1) VDDQ DECAPS (1UF x2 / 10UF x1)
+1.2V_DDR +2.5V_MEM +0.6VS +1.2V_DDR +2.5V_MEM +0.6VS
@RF@ CD384
@RF@ CD385
@RF@ CD386
@RF@ CD387
@RF@ CD388
@RF@ CD389
100P_0201_50V8J
CD307
CD309
CD317
CD299
CD308
10U_0402_6.3V6M
10U_0402_6.3V6M
CD305
CD314
10U_0402_6.3V6M
100P_0201_50V8J
CD300
CD303
10U_0402_6.3V6M
100P_0201_50V8J
100P_0201_50V8J
CD304
CD306
CD315
CD311
CD313
10U_0402_6.3V6M
10U_0402_6.3V6M
CD293
CD319
10U_0402_6.3V6M
100P_0201_50V8J
CD296
CD312
10U_0402_6.3V6M
100P_0201_50V8J
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD310
CD295
CD301
CD297
CD275
CD298
CD256
CD318
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+0.6V_DDR_VREFCA +0.6V_DDR_VREFCA
UD3 UD4
All VREF traces should DDR_A_D6 DDR_A_D38
C
have 10 mil trace width M1
VREFCA DQL0
G2
DDR_A_D3
M1
VREFCA DQL0
G2
DDR_A_D37 +0.6VS
C
F7 F7
1 DQL1 H3 DDR_A_D2 1 DQL1 H3 DDR_A_D39
0.047U_0201_10V6K
CD263
0.047U_0201_10V6K
CD316
DDR_A_MA0 P3 DQL2 H7 DDR_A_D5 DDR_A_MA0 P3 DQL2 H7 DDR_A_D32
DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D7 DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D34
DDR_A_MA0 1 2 36_0201_1%
DDR_A_MA2 A1 DQL4 DDR_A_D1 DDR_A_MA2 A1 DQL4 DDR_A_D33 RD166
2 R3 H8 2 R3 H8
DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D4 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D35 DDR_A_MA1 1 2 36_0201_1%
RD167
DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D0 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D36
DDR_A_MA2 1 2 36_0201_1%
DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7 RD168
DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA3 1 2 36_0201_1%
RD169
DDR_A_MA7 R8 A6 A3 DDR_A_D15 DDR_A_MA7 R8 A6 A3 DDR_A_D42
DDR_A_MA4 1 2 36_0201_1%
DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D10 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D41 RD170
DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D14 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D47 DDR_A_MA5 1 2 36_0201_1%
RD171
DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D11 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D45
DDR_A_MA6 1 2 36_0201_1%
DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D13 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D43 RD172
DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D8 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D40 DDR_A_MA7 1 2 36_0201_1%
RD173
DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D12 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D46
DDR_A_MA8 1 2 36_0201_1%
DDR_A_MA14 A13 DQU6 DDR_A_D9 DDR_A_MA14 A13 DQU6 DDR_A_D44 RD174
L2 D7 L2 D7
A14/WE DQU7 A14/WE DQU7 DDR_A_MA9 1 2 36_0201_1%
+1.2V_DDR +1.2V_DDR RD175
DDR_A_BA0 N2 DDR_A_BA0 N2 DDR_A_MA10 1 2 36_0201_1%
<8,23> DDR_A_BA0 DDR_A_BA1 BA0 DDR_A_BA1 BA0 RD176
+1.2V_DDR <8,23> N8 B3 +1.2V_DDR N8 B3
DDR_A_BA1 BA1 VDD B9 BA1 VDD B9 DDR_A_MA11 1 2 36_0201_1%
RD177
40mil E2 VDD D1 40mil E2 VDD D1 DDR_A_MA12 1 2 36_0201_1%
E7 DMU/DBIU VDD G7 E7 DMU/DBIU VDD G7 RD178
DML/DBIL VDD J1 DML/DBIL VDD J1 DDR_A_MA13 1 2 36_0201_1%
RD179
VDD J9 VDD J9
VDD L1 VDD L1
DDR_A_CLK0 K7 VDD L9 DDR_A_CLK0 K7 VDD L9 DDR_A_MA14 1 2 36_0201_1%
RD180
<8,23> DDR_A_CLK0 DDR_A_CLK#0 K8 CK_t VDD R1 DDR_A_CLK#0 K8 CK_t VDD R1 RD233 DDR_A_MA15 1 2 36_0201_1%
<8,23> DDR_A_CLK#0 DDR_A_CKE0 K2 CK_c VDD T9 DDR_A_CKE0 K2 CK_c VDD T9 RD181
<8,23> DDR_A_CKE0 CKE VDD CKE VDD DDR_A_MA16
RD182 1 2 36_0201_1% +1.2V_DDR
A1 A1
VDDQ A9 VDDQ A9
VDDQ C1 VDDQ C1 DDR_A_BA0 1 2 36_0201_1%
RD232 0_0402_5% RD183
VDDQ VDDQ
1
D9 D9 SD028000080 DDR_A_BA1 C2527
VDDQ VDDQ RD184 1 2 36_0201_1%
F2 F2 SDP8G@ 0.01U_0402_16V7K
VDDQ F8 VDDQ F8
2
DDR_A_ODT0 K3 VDDQ G1 DDR_A_ODT0 K3 VDDQ G1
<8,23> DDR_A_ODT0 DDR_A_CS#0 L7 ODT VDDQ G9 DDR_A_CS#0 L7 ODT VDDQ G9
<8,23> DDR_A_CS#0 DDR_A_MA16 CS VDDQ DDR_A_MA16 CS VDDQ DDR_A_CLK0
L8 J2 RD232 BOM control for DDP@ to 240R /SDP@ to 0R 0_0402_5% L8 J2 RD233 BOM control for DDP@ to 240R /SDP@ to 0R RD185 1 2 36_0201_1%
DDR_A_MA15 M8 RAS VDDQ J8 DDR_A_MA15 M8 RAS VDDQ J8
SD028000080
CAS VDDQ SDP8G@ CAS VDDQ
DDR_A_CLK#0 1 2 36_0201_1%
B2 RD232 B2 RD233 RD186
VSS E1 240_0402_1% VSS E1 15mil 240_0402_1%
VSS DDP16G@ VSS DDP16G@
E9 15mil 2 1 E9 2 1
VSS G8 VSS G8 DDR_A_CKE0
DDR_A_DQS#1 VSS DDR_A_DQS#5 VSS RD187 1 2 36_0201_1%
A7 K1 A7 K1
DDR_A_DQS1 B7 DQSU_c VSS K9 DDR_A_DQS5 B7 DQSU_c VSS K9
DDP16G@ DDP16G@
DDR_A_DQS#0 F3 DQSU_t VSS M9 DDR_A_BG1_R3 2 0_0201_5% DDR_A_BG1 DDR_A_DQS#4 DQSU_t VSS DDR_A_BG1_R4 DDR_A_BG1 DDR_A_CS#0
RD2421 F3 M9 RD244 1 2 0_0201_5% RD188 1 2 36_0201_1%
B DDR_A_DQS0 DQSL_c VSS DDR_A_BG1 <8,23> DDR_A_DQS4 DQSL_c VSS B
G3 N1 G3 N1
DQSL_t VSS T1 DQSL_t VSS T1 DDR_A_ODT0 1 2 36_0201_1%
SDP8G@ SDP8G@ RD189
P1 VSS DDR_DRAMRST#_R VSS
RD2431 2 0_0201_5% P1 RD245 1 2 0_0201_5%
<23,25,26> DDR_DRAMRST#_R RESET RESET DDR_A_ACT# 1 2 36_0201_1%
2 1 RD164 15mil F9 2 1 RD163 15mil F9 RD190
240_0402_1% ZQ 240_0402_1% ZQ DDR_A_BG0
RD191 1 2 36_0201_1%
DDR_A_ACT# L3 A2 DDR_A_ACT# L3 A2 DDR_A_PARITY 1 2 36_0201_1%
<8,23> DDR_A_ACT# DDR_A_BG0 M2 ACT VSSQ A8 DDR_A_BG0 M2 ACT VSSQ A8 RD192
<8,23> DDR_A_BG0 N9 BG0 VSSQ C9 N9 BG0 VSSQ C9
DDR_A_ALERT# P9 TEN VSSQ D2 DDR_A_ALERT# P9 TEN VSSQ D2
<8,23> DDR_A_ALERT# DDR_A_PARITY T3 ALERT VSSQ D8 DDR_A_PARITY T3 ALERT VSSQ D8
<8,23> DDR_A_PARITY PAR VSSQ PAR VSSQ +1.2V_DDR
E3 E3
RD258 1 @ 2 0_0201_5% T7 VSSQ E8 RD259 1 @ 2 0_0201_5% T7 VSSQ E8
40mil B1 NC VSSQ F1 RD259 40mil B1 NC VSSQ F1 DDR_A_ALERT#
VPP VSSQ VPP VSSQ RD193 2 1 49.9_0201_1%
R9 H1 R9 H1
+2.5V_MEM VPP VSSQ H9
96-BALL VSSQ 96-BALL VSSQ
RD258 SDRAM DDR4 SDRAM DDR4
K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96
@ 0_0201_5% @
SD043000080
HMO16S32@
08/23, change PCP Footprint to MT40A2G16SKL-062E-B_FBGA_96P 08/23, change PCP Footprint to MT40A2G16SKL-062E-B_FBGA_96P
0_0201_5%
SD043000080
HMO16S32@
UD3 UD3 UD3

UD3 UD3 UD3 UD3 UD3 UD3 UD3
D4 512M16/2666 H5AN8G6NCJR-VKC FBGA D4 8G/2666 MT40A512M16LY-075:E FBGA D4 512M16 K4A8G165WC-BCTD FBGA 96P
D4 16G/3200 MT40A1G16KD-062E:E D4 512M16 MT40A512M16TB-062E:J S SA0000BMN0L SA0000ARD0L SA0000B6F0L D4 16G/2666 H5ANAG6NCMR-VKC FBGA96P D4 16G/2666 MT40A1G16KNR-075:E D4 16G/2666 K4AAG165WB-MCTD FBGA96P D4 32G/3200 MT40A2G16SKL-062E:B FBGA 96P S D4 32G/2666 K4ABG165WA-MCTD FBGA96P
SA0000D3U0L SA0000CMS0L HYX8G@ MCN8G@ SAM8G@ SA0000BZJ0L SA0000BC70L SA0000B9K0L SA0000CYF0L SA0000CHM0L
MCN16G1@ MCN8G1@ HYX16G@ MCN16G@ SAM16G@ MCN32G@ SAM32G@
UD4 UD4
UD4 UD4 UD4 UD4 UD4 UD4 UD4 UD4
D4 32G/3200 MT40A2G16SKL-062E:B FBGA 96P S D4 32G/2666 K4ABG165WA-MCTD FBGA96P

A D4 16G/3200 MT40A1G16KD-062E:E D4 512M16 MT40A512M16TB-062E:J S D4 512M16/2666 H5AN8G6NCJR-VKC FBGA D4 8G/2666 MT40A512M16LY-075:E FBGA D4 512M16 K4A8G165WC-BCTD FBGA 96P D4 16G/2666 H5ANAG6NCMR-VKC FBGA96P D4 16G/2666 MT40A1G16KNR-075:E D4 16G/2666 K4AAG165WB-MCTD FBGA96P SA0000CYF0L SA0000CHM0L A
SA0000D3U0L SA0000CMS0L SA0000BMN0L SA0000ARD0L SA0000B6F0L SA0000BZJ0L SA0000BC70L SA0000B9K0L MCN32G@ SAM32G@
MCN16G1@ MCN8G1@ HYX8G@ MCN8G@ SAM8G@ HYX16G@ MCN16G@ SAM16G@
9/18 DVT1 Modify

5 4 3 2 1
5 4 3 2 1
DDR4 Memory Down_CHB <8,26> DDR_B_MA[0..16]
<8,26> DDR_B_DQS[0..7]
<8,26>
DDR_B_DQS#[0..7]
DDR_B_D[0..63]
D
DDR4 Memory Down_CHB D
+1.2V_DDR
Closed to UD5 Closed to UD6 VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1)
VDD DECAPS (1UF x3 / 10UF x1) VDD DECAPS (1UF x3 / 10UF x1)
SOC side Memory side
1
VDDQ DECAPS (1UF x2 / 10UF x1) VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1) VDDQ DECAPS (1UF x2 / 10UF x1)
RD226 +1.2V_DDR +2.5V_MEM +0.6VS +1.2V_DDR +2.5V_MEM +0.6VS
1.8K_0402_1%
2
RD228
@RF@ CD390
@RF@ CD391
@RF@ CD392
@RF@ CD393
@RF@ CD394
@RF@ CD395
1 2
100P_0201_50V8J
CD376
CD375
1U_0402_6.3V6K
CD368
1U_0402_6.3V6K
CD352
CD372
10U_0402_6.3V6M
10U_0402_6.3V6M
CD359
CD344
10U_0402_6.3V6M
100P_0201_50V8J
CD328
CD373
10U_0402_6.3V6M
100P_0201_50V8J
100P_0201_50V8J
CD350
CD338
1U_0402_6.3V6K
CD371
1U_0402_6.3V6K
CD374
CD332
10U_0402_6.3V6M
10U_0402_6.3V6M
CD331
CD333
10U_0402_6.3V6M
100P_0201_50V8J
CD341
CD349
10U_0402_6.3V6M
100P_0201_50V8J
+0.6V_B_VREFDQ +0.6V_DDR_B_VREFDQ
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2.7_0402_1% 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
CD329
CD354
CD366
CD351
CD353
CD357
CD365
CD348
CD324
1
0.022U_0402_16V7K 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2
RD227
1.8K_0402_1%
1
RD229
24.9_0402_1%
2
VREF traces should be at least 20 mils wide

with 20 mils spacing to other signals/planes.
+0.6V_DDR_B_VREFDQ
C C
+0.6V_DDR_B_VREFDQ
UD5
M1 G2 DDR_B_D29
All VREF traces should VREFCA DQL0 F7 DDR_B_D30
UD6
1 DQL1 DDR_B_D25
have 10 mil trace width H3
0.047U_0402_25V7K
CD321
DDR_B_MA0 P3 DQL2 H7 DDR_B_D31 M1 G2 DDR_B_D61
DDR_B_MA1 P7 A0 DQL3 H2 DDR_B_D28 1 VREFCA DQL0 F7 DDR_B_D58
0.047U_0402_25V7K
CD320
DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D26 DQL1 H3 DDR_B_D59
2 DDR_B_MA3 A2 DQL5 DDR_B_D24 DDR_B_MA0 DQL2 DDR_B_D63
N7 J3 P3 H7
DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D27 DDR_B_MA1 P7 A0 DQL3 H2 DDR_B_D57
DDR_B_MA5 A4 DQL7 2 DDR_B_MA2 A1 DQL4 DDR_B_D56
P8 R3 H8
DDR_DRAMRST#_R DDR_B_MA6 P2 A5 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D62
DDR_B_MA7 R8 A6 A3 DDR_B_D19 DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D60
DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D20 DDR_B_MA5 P8 A4 DQL7
DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D22 DDR_B_MA6 P2 A5
2 DDR_B_MA10 A9 DQU2 DDR_B_D21 DDR_B_MA7 A6 DDR_B_D48
CD112 M3 C7 R8 A3
DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D18 DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D50
0.1U_0402_10V6K
DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D17 DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D51
@ESD@
1 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D23 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D55
DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D16 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D52
A14/WE DQU7 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D53
DDR_B_BA0 +1.2V_DDR DDR_B_MA13 A12/BC DQU5 DDR_B_D54
N2 T8 D3
PLACE NEAR TO UD5,UD6 <8,26> DDR_B_BA0 DDR_B_BA1 N8 BA0 B3 DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D49
+1.2V_DDR <8,26> DDR_B_BA1 BA1 VDD A14/WE DQU7 +1.2V_DDR
B9
40mil E2 VDD D1 DDR_B_BA0 N2
DMU/DBIU VDD +1.2V_DDR DDR_B_BA1 BA0
E7 G7 N8 B3
DML/DBIL VDD J1 40mil BA1 VDD B9
VDD J9 E2 VDD D1
VDD L1 E7 DMU/DBIU VDD G7
DDR_B_CLK0 K7 VDD L9 DML/DBIL VDD J1
<8,26> DDR_B_CLK0 DDR_B_CLK#0 CK_t VDD VDD
K8 R1 J9
<8,26> DDR_B_CLK#0 DDR_B_CKE0 K2 CK_c VDD T9 VDD L1
<8,26> DDR_B_CKE0 CKE VDD DDR_B_CLK0 K7 VDD L9
RD234
DDR_B_CLK#0 K8 CK_t VDD R1
A1 DDR_B_CKE0 K2 CK_c VDD T9 RD235
VDDQ A9 CKE VDD
VDDQ C1
VDDQ D9 A1
VDDQ F2 VDDQ A9
VDDQ
0_0402_5% VDDQ
F8 SD028000080 C1
DDR_B_ODT0 K3 VDDQ G1 VDDQ D9
SDP8G@ 0_0402_5%
<8,26> DDR_B_ODT0 DDR_B_CS#0 L7 ODT VDDQ G9 VDDQ F2 SD028000080
<8,26> DDR_B_CS#0 DDR_B_MA16 L8 CS VDDQ J2 RD234 BOM control for DDP@ to 240R /SDP@ to 0R VDDQ F8 SDP8G@
+1.2V_DDR DDR_B_MA15 M8 RAS VDDQ J8 DDR_B_ODT0 K3 VDDQ G1
CAS VDDQ DDR_B_CS#0 L7 ODT VDDQ G9 RD235 BOM control for DDP@ to 240R /SDP@ to 0R
RD234 DDR_B_MA16 CS VDDQ
1 B2 L8 J2
VSS E1 240_0402_1% DDR_B_MA15 M8 RAS VDDQ J8
+ VSS E9 15mil 2 DDP16G@
1 CAS VDDQ RD235
CD330
B VSS 240_0402_1% B
330U_D3_2.5VY_R6M G8 B2
DDR_B_DQS#2 A7 VSS K1 VSS E1 15mil 2 DDP16G@
1
2 DDR_B_DQS2 B7 DQSU_c VSS K9 VSS E9
DDP16G@
DDR_B_DQS#3 F3 DQSU_t VSS M9 DDR_B_BG1_R5 2 0_0201_5% DDR_B_BG1 VSS
RD246 1 G8
DDR_B_DQS3 G3 DQSL_c VSS N1 DDR_B_BG1 <8,26> DDR_B_DQS#6 A7 VSS K1
DQSL_t VSS T1 DDR_B_DQS6 B7 DQSU_c VSS K9
SDP8G@ DDP16G@
DDR_DRAMRST#_R P1 VSS DDR_B_DQS#7 DQSU_t VSS DDR_B_BG1_R6 DDR_B_BG1
8/28 DVT1 change footprint to C_D3 RD247 1 2 0_0201_5% F3 M9 RD248 1 2 0_0201_5%
<23,24,26> DDR_DRAMRST#_R RESET DDR_B_DQS7 DQSL_c VSS
G3 N1 SDP8G@
2 1 RD195 15mil F9 DQSL_t VSS T1 RD249 1 2 0_0201_5%
ZQ DDR_DRAMRST#_R P1 VSS
240_0402_1%
2 1 RD194 15mil RESET
DDR_B_ACT# L3 A2 F9
240_0402_1%
<8,26> DDR_B_ACT# DDR_B_BG0 ACT VSSQ ZQ
M2 A8
<8,26> DDR_B_BG0 N9 BG0 VSSQ C9
DDR_B_ALERT# P9 TEN VSSQ D2 DDR_B_ACT# L3 A2
<8,26> DDR_B_ALERT# DDR_B_PARITY ALERT VSSQ DDR_B_BG0 ACT VSSQ
T3 D8 M2 A8
<8,26> DDR_B_PARITY PAR VSSQ E3 N9 BG0 VSSQ C9
1 2 0_0201_5% T7 VSSQ E8 DDR_B_ALERT# P9 TEN VSSQ D2
RD260 @
40mil B1 NC VSSQ F1 DDR_B_PARITY T3 ALERT VSSQ D8
R9 VPP VSSQ H1 PAR VSSQ E3
+2.5V_MEM VPP VSSQ H9 RD261 1 @ 2 0_0201_5% T7 VSSQ E8
RD260 96-BALL VSSQ RD261 40mil B1 NC VSSQ F1
SDRAM DDR4 R9 VPP VSSQ H1
K4A8G165WB-BCPB_FBGA96
96-BALL VSSQ
@
SDRAM DDR4
K4A8G165WB-BCPB_FBGA96
0_0201_5% 08/23, change PCP Footprint to MT40A2G16SKL-062E-B_FBGA_96P 0_0201_5% @
SD043000080 SD043000080
HMO16S32@ HMO16S32@
08/23, change PCP Footprint to MT40A2G16SKL-062E-B_FBGA_96P
UD5 UD5 UD5 UD5

UD5 UD5 UD5 UD5 UD5 UD5
D4 512M16/2666 H5AN8G6NCJR-VKC FBGA D4 32G/3200 MT40A2G16SKL-062E:B FBGA 96P S D4 32G/2666 K4ABG165WA-MCTD FBGA96P D4 16G/3200 MT40A1G16KD-062E:E
SA0000BMN0L D4 8G/2666 MT40A512M16LY-075:E FBGA D4 512M16 K4A8G165WC-BCTD FBGA 96P D4 512M16 MT40A512M16TB-062E:J S D4 16G/2666 H5ANAG6NCMR-VKC FBGA96P D4 16G/2666 MT40A1G16KNR-075:E D4 16G/2666 K4AAG165WB-MCTD FBGA96P SA0000CYF0L SA0000CHM0L SA0000D3U0L
HYX8G@ SA0000ARD0L SA0000B6F0L SA0000CMS0L SA0000BZJ0L SA0000BC70L SA0000B9K0L MCN32G@ SAM32G@ MCN16G1@
MCN8G@ SAM8G@ MCN8G1@ HYX16G@ MCN16G@ SAM16G@
UD6 UD6 UD6 UD6

UD6 UD6
UD6 UD6 UD6
A UD6 A
D4 8G/2666 MT40A512M16LY-075:E FBGA D4 16G/2666 H5ANAG6NCMR-VKC FBGA96P D4 16G/2666 MT40A1G16KNR-075:E D4 16G/2666 K4AAG165WB-MCTD FBGA96P
D4 512M16/2666 H5AN8G6NCJR-VKC FBGA SA0000ARD0L D4 512M16 K4A8G165WC-BCTD FBGA 96P SA0000BZJ0L SA0000BC70L SA0000B9K0L
SA0000BMN0L MCN8G@ SA0000B6F0L D4 512M16 MT40A512M16TB-062E:J S HYX16G@ MCN16G@ SAM16G@ D4 32G/3200 MT40A2G16SKL-062E:B FBGA 96P S D4 32G/2666 K4ABG165WA-MCTD FBGA96P
HYX8G@ SAM8G@ SA0000CMS0L SA0000CYF0L SA0000CHM0L D4 16G/3200 MT40A1G16KD-062E:E
MCN8G1@ MCN32G@ SAM32G@ SA0000D3U0L
MCN16G1@
9/18 DVT1 Modify

DDR4 Memory Down_CHB
5 4 3 2 1
5 4 3 2 1
DDR4 Memory Down_CHB <8,25> DDR_B_MA[0..16]
<8,25>
DDR_B_DQS[0..7]
DDR_B_DQS#[0..7]
<8,25> DDR_B_D[0..63]
D D
Closed to UD7 Closed to UD8

VDD DECAPS (1UF x3 / 10UF x1) VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1) VDD DECAPS (1UF x3 / 10UF x1) VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1)
VDDQ DECAPS (1UF x2 / 10UF x1) VDDQ DECAPS (1UF x2 / 10UF x1)
+1.2V_DDR +2.5V_MEM +0.6VS +1.2V_DDR +1.2V_DDR +2.5V_MEM +0.6VS
@RF@ CD396
@RF@ CD397
@RF@ CD398
@ESD@ CD407
@ESD@ CD406
@ESD@ CD405
@ESD@ CD404
@RF@ CD399
@RF@ CD400
@RF@ CD401
100P_0201_50V8J
CD355
CD356
CD335
CD334
CD367
10U_0402_6.3V6M
10U_0402_6.3V6M
CD377
CD370
10U_0402_6.3V6M
100P_0201_50V8J
CD364
CD336
10U_0402_6.3V6M
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
CD343
CD362
CD360
CD346
CD325
10U_0402_6.3V6M
10U_0402_6.3V6M
CD327
CD345
10U_0402_6.3V6M
100P_0201_50V8J
CD337
CD361
10U_0402_6.3V6M
100P_0201_50V8J
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD340
CD339
CD347
CD363
CD358
CD369
CD326
CD342
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+0.6V_DDR_B_VREFDQ
C C
+0.6V_DDR_B_VREFDQ
UD7
All VREF traces should DDR_B_D11
UD8
have 10 mil trace width M1
VREFCA DQL0
G2
DDR_B_D8 DDR_B_D43
F7 200mil M1 G2
1 DQL1 H3 DDR_B_D10 VREFCA DQL0 F7 DDR_B_D45
0.047U_0201_10V6K
CD323
DDR_B_MA0 P3 DQL2 H7 DDR_B_D9 1 DQL1 H3 DDR_B_D47
0.047U_0201_10V6K
CD322
DDR_B_MA1 P7 A0 DQL3 H2 DDR_B_D14 DDR_B_MA0 P3 DQL2 H7 DDR_B_D41 +0.6VS
DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D13 DDR_B_MA1 P7 A0 DQL3 H2 DDR_B_D42
2 DDR_B_MA3 A2 DQL5 DDR_B_D15 DDR_B_MA2 A1 DQL4 DDR_B_D44
N7 J3 2 R3 H8
DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D12 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D46
DDR_B_MA0 1 2 36_0201_1%
DDR_B_MA5 A4 DQL7 DDR_B_MA4 A3 DQL6 DDR_B_D40 RD206
P8 N3 J7
DDR_B_MA6 P2 A5 DDR_B_MA5 P8 A4 DQL7 DDR_B_MA1 1 2 36_0201_1%
RD198
DDR_B_MA7 R8 A6 A3 DDR_B_D2 DDR_B_MA6 P2 A5
DDR_B_MA2 1 2 36_0201_1%
DDR_B_MA8 A7 DQU0 DDR_B_D0 DDR_B_MA7 A6 DDR_B_D35 RD217
R2 B8 R8 A3
DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D6 DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D38 DDR_B_MA3 1 2 36_0201_1%
RD213
DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D1 DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D37
DDR_B_MA4 1 2 36_0201_1%
DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D3 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D34 RD205
DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D5 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D33 DDR_B_MA5 1 2 36_0201_1%
RD204
DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D7 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D32
DDR_B_MA6 1 2 36_0201_1%
DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D4 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D39 RD211
A14/WE DQU7 DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D36 DDR_B_MA7 1 2 36_0201_1%
+1.2V_DDR RD216
DDR_B_BA0 N2 A14/WE DQU7
+1.2V_DDR DDR_B_MA8 1 2 36_0201_1%
<8,25> DDR_B_BA0 DDR_B_BA1 N8 BA0 B3 DDR_B_BA0 N2 RD214
+1.2V_DDR <8,25> DDR_B_BA1 BA1 VDD DDR_B_BA1 BA0 DDR_B_MA9
B9 +1.2V_DDR N8 B3 RD224 1 2 36_0201_1%
40mil E2 VDD D1 BA1 VDD B9 DDR_B_MA10
DMU/DBIU VDD VDD RD209 1 2 36_0201_1%
E7 G7 40mil E2 D1
DML/DBIL VDD J1 E7 DMU/DBIU VDD G7 DDR_B_MA11 1 2 36_0201_1%
RD215
VDD J9 DML/DBIL VDD J1 DDR_B_MA12 1 2 36_0201_1%
VDD VDD RD219
L1 J9
DDR_B_CLK0 K7 VDD L9 VDD L1 DDR_B_MA13 1 2 36_0201_1%
RD236 RD221
<8,25> DDR_B_CLK0 DDR_B_CLK#0 CK_t VDD DDR_B_CLK0 VDD
K8 R1 K7 L9
<8,25> DDR_B_CLK#0 DDR_B_CKE0 K2 CK_c VDD T9 DDR_B_CLK#0 K8 CK_t VDD R1 RD237
<8,25> DDR_B_CKE0 CKE VDD DDR_B_CKE0 K2 CK_c VDD T9 DDR_B_MA14 1 2 36_0201_1%
RD203
CKE VDD DDR_B_MA15
RD223 1 2 36_0201_1%
A1
VDDQ A9 A1 DDR_B_MA16 1 2 36_0201_1%
VDDQ
0_0402_5% VDDQ
RD222
C1 SD028000080 A9
VDDQ D9 SDP8G@ VDDQ C1 +1.2V_DDR
VDDQ VDDQ
0_0402_5%
F2 D9 SD028000080
VDDQ F8 VDDQ F2 DDR_B_BA0 1 2 36_0201_1%
SDP8G@ RD218
DDR_B_ODT0 K3 VDDQ G1 VDDQ F8 DDR_B_BA1 1 2 36_0201_1%
<8,25> DDR_B_ODT0 DDR_B_CS#0 L7 ODT VDDQ G9 DDR_B_ODT0 K3 VDDQ G1 RD212
<8,25> DDR_B_CS#0 DDR_B_MA16 L8 CS VDDQ J2 RD236 BOM control for DDP@ to 240R /SDP@ to 0R DDR_B_CS#0 L7 ODT VDDQ G9
DDR_B_MA15 M8 RAS VDDQ J8 DDR_B_MA16 L8 CS VDDQ J2 RD237 BOM control for DDP@ to 240R /SDP@ to 0R
DDR_B_MA15
1
CAS VDDQ M8 RAS VDDQ J8 C2528
RD236 CAS VDDQ DDR_B_CLK0
B2 RD201 1 2 36_0201_1% 0.01U_0402_16V7K
VSS E1 240_0402_1% B2 RD237
2
VSS E9 15mil 2 DDP16G@
1 VSS E1 240_0402_1%
DDR_B_CLK#0 1 2 36_0201_1%
B VSS VSS DDP16G@ RD225 B
G8 E9 15mil 2 1
DDR_B_DQS#0 A7 VSS K1 VSS G8
DDR_B_DQS0 B7 DQSU_c VSS K9 DDR_B_DQS#4 A7 VSS K1
DDP16G@
DDR_B_DQS#1 F3 DQSU_t VSS M9 DDR_B_BG1_R7 2 0_0201_5% DDR_B_BG1 DDR_B_DQS4 DQSU_c VSS
RD2501 B7 K9 RD252 DDP16G@ DDR_B_CKE0 1 2 36_0201_1%
DDR_B_DQS1 G3 DQSL_c VSS N1 DDR_B_BG1 <8,25> DDR_B_DQS#5 F3 DQSU_t VSS M9 DDR_B_BG1_R8 1 2 0_0201_5% DDR_B_BG1 RD220
DQSL_t VSS T1 DDR_B_DQS5 G3 DQSL_c VSS N1
SDP8G@
DDR_DRAMRST#_R P1 VSS DQSL_t VSS DDR_B_CS#0
RD2511 2 0_0201_5% T1 SDP8G@ RD207 1 2 36_0201_1%
<23,24,25> DDR_DRAMRST#_R RESET DDR_DRAMRST#_R VSS
P1 RD2531 2 0_0201_5%
2 1 RD196 15milF9 RESET DDR_B_ODT0 1 2 36_0201_1%
RD199
240_0402_1% ZQ 2 1 RD197 15mil F9
240_0402_1% ZQ DDR_B_ACT#
DDR_B_ACT# RD200 1 2 36_0201_1%
L3 A2
<8,25> DDR_B_ACT# DDR_B_BG0 ACT VSSQ DDR_B_ACT#
M2 A8 L3 A2 DDR_B_BG0
<8,25> DDR_B_BG0 BG0 VSSQ DDR_B_BG0 ACT VSSQ RD210 1 2 36_0201_1%
N9 C9 M2 A8
DDR_B_ALERT# P9 TEN VSSQ D2 N9 BG0 VSSQ C9 DDR_B_PARITY 1 2 36_0201_1%
<8,25> DDR_B_ALERT# DDR_B_PARITY ALERT VSSQ DDR_B_ALERT# TEN VSSQ RD208
T3 D8 P9 D2
<8,25> DDR_B_PARITY PAR VSSQ E3 DDR_B_PARITY T3 ALERT VSSQ D8
VSSQ PAR VSSQ DDR_B_BG1 RD255
RD262 1 @ 2 0_0201_5% T7 E8 E3 1 2 36_0201_1%
40mil B1 NC VSSQ F1 RD263 1 @ 2 0_0201_5% T7 VSSQ E8
R9 VPP VSSQ H1 40mil B1 NC VSSQ F1 +1.2V_DDR
+2.5V_MEM VPP VSSQ H9 RD263 R9 VPP VSSQ H1
96-BALL VSSQ +2.5V_MEM VPP VSSQ H9
RD262 DDR_B_ALERT#
VSSQ RD202 2 1 49.9_0201_1%
SDRAM DDR4 96-BALL
K4A8G165WB-BCPB_FBGA96 SDRAM DDR4
@ K4A8G165WB-BCPB_FBGA96
@
08/23, change PCP Footprint to MT40A2G16SKL-062E-B_FBGA_96P 0_0201_5%
0_0201_5% SD043000080
08/23, change PCP Footprint to MT40A2G16SKL-062E-B_FBGA_96P
SD043000080 HMO16S32@
HMO16S32@
UD7 UD7
UD7 UD7 UD7 UD7 UD7 UD7 UD7 UD7
D4 16G/2666 H5ANAG6NCMR-VKC FBGA96P D4 16G/2666 MT40A1G16KNR-075:E

A D4 16G/3200 MT40A1G16KD-062E:E D4 512M16 MT40A512M16TB-062E:J S D4 512M16/2666 H5AN8G6NCJR-VKC FBGA D4 8G/2666 MT40A512M16LY-075:E FBGA D4 512M16 K4A8G165WC-BCTD FBGA 96P SA0000BZJ0L SA0000BC70L D4 16G MT40A1G16KNR-075:E YAM A31! D4 32G/3200 MT40A2G16SKL-062E:B FBGA 96P S D4 32G/2666 K4ABG165WA-MCTD FBGA96P A
SA0000D3U0L SA0000CMS0L SA0000BMN0L SA0000ARD0L SA0000B6F0L HYX16G@ MCN16G@ SA0000B9K0L SA0000CYF0L SA0000CHM0L
MCN16G1@ MCN8G1@ HYX8G@ MCN8G@ SAM8G@ SAM16G@ MCN32G@ SAM32G@
UD8 UD8 UD8

UD8 UD8 UD8 UD8 UD8 UD8 UD8
D4 512M16/2666 H5AN8G6NCJR-VKC FBGA D4 8G/2666 MT40A512M16LY-075:E FBGA D4 16G MT40A1G16KNR-075:E YAM A31!
D4 16G/3200 MT40A1G16KD-062E:E D4 512M16 MT40A512M16TB-062E:J S SA0000BMN0L SA0000ARD0L D4 512M16 K4A8G165WC-BCTD FBGA 96P D4 16G/2666 H5ANAG6NCMR-VKC FBGA96P D4 16G/2666 MT40A1G16KNR-075:E SA0000B9K0L D4 32G/3200 MT40A2G16SKL-062E:B FBGA 96P S D4 32G/2666 K4ABG165WA-MCTD FBGA96P
SA0000D3U0L SA0000CMS0L HYX8G@ MCN8G@ SA0000B6F0L SA0000BZJ0L SA0000BC70L SAM16G@ SA0000CYF0L SA0000CHM0L
MCN16G1@ MCN8G1@ SAM8G@ HYX16G@ MCN16G@ MCN32G@ SAM32G@

9/18 DVT1 Modify Issued Date 2017/04/07 Deciphered Date 2018/12/31 Title
DDR4 Memory Down_CHB
5 4 3 2 1
A B C D E
UG1
N18E-G1R-A1 FCBGA 2228 QS

SA0000D4N0L
N18EG1@
UG1
+1V8_AON
@
RG1522
GC OFF 1.0 GPU Power ON/OFF
1 10K_0201_5% SA0000D4M0L 1
PEX_RST# 1 2 N18EG2@
+1V8_AON
UG1
1 2 1
CG6824
RG3 0.1U_0201_6.3V6K
10K_0201_5%
5
2
GND VCC
PEX_RST# 1 SA0000D4L0L
<18> PEX_RST# IN B 4 1 2 N18EG3@
2 OUT Y RG537 0_0201_5%
IN A
1
<15,74> PCH_PLTRST#
UG10 RG562
NL17SZ08DFT2G_SC70-5 100K_0201_5% UG1
3
@
2
N18E-G0-A1 BGA 2228
SA0000CK43L
N18EG0@
<30,39,40> DGPU_PEX_RST#
+1V8_AON
+PEX_VDD
Under GPU PEX_DVDD

PEX_CVDD
4.7U_0402_4V_M
4.7U_0402_4V_M
4.7U_0402_4V_M
1 1 1
0710, add CG8395 4.7uF, ref NV HWDG.
CG7206
CG7207
CG8395
1
CG483
2 2 2
0.1U_0201_6.3V6K
5
2 +1V8_AON
GND VCC
1 UG1A
<37,108> +1.35VS_VGA_PGOOD IN B 4 2 1
NVVDD_PGOOD OUT Y
2
2 RG1 0_0201_5% 1/22 PCI_EXPRESS
<30,32,39,98,102> NVVDD_PGOOD IN A RG2
PEX_WAKE# doesn’ t appl yi n not ebook MBD. +PEX_VDD
UG29
NL17SZ08DFT2G_SC70-5
10K_0201_5% @ T14 PAD~D
PEX_WAKE# BK44 PEX_WAKE
PEX_DVDD BB35 +PEX_VDD Near GPU
3
DGPU_PEX_RST# DGPU_PEX_RST#_R BK26
2
1 2 BB36
G
PEX_RST PEX_DVDD
1
2 RG4 0_0201_5% PEX_DVDD BC35 2
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1 3 CLKREQ_PEG#0_R BL26 BC36
PEX_CLKREQ PEX_DVDD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
22U_0603_4V_M
22U_0603_4V_M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
<15> CLKREQ_PEG#0
PEX_DVDD BD33
D
S
2 2 2 1 1
QG510 BM26 BD36
CG7847
CG7848
CG7849
CG7850
CG7851
CG7852
CG7853
CG7854
CG7855
CG7856
CG7857
CG7858
CG7859
CG7860
CG7861
CG7862
PEX_REFCLK PEX_DVDD
BSS138W_SOT-323-3 <15> CLK_PEG_P0 BM27
CG8396
CG8397
CG8398
CG8399
CG8400
PEX_REFCLK
<15> CLK_PEG_N0 BB33 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PEG_CRX_GTX_P0 PEG_CRX_C_GTX_P0 PEX_CVDD
2 1 BG26 BC33 1 1 1 2 2
<6> PEG_CRX_GTX_P0 PEG_CRX_GTX_N0 PEG_CRX_C_GTX_N0 PEX_TX0 PEX_CVDD
0.22U_0201_6.3V 2 1 CC50 BH26 PEX_TX0
<6> PEG_CRX_GTX_N0 0.22U_0201_6.3V CC51
BL27 PEX_RX0 0726, change CG7847-CG7862 to 1u, ref NV HWDG.
<6> PEG_CTX_C_GRX_P0
BK27 PEX_RX0
<6> PEG_CTX_C_GRX_N0
PEG_CRX_GTX_P1 2 1 PEG_CRX_C_GTX_P1 BF26
<6> PEG_CRX_GTX_P1 PEG_CRX_GTX_N1 PEG_CRX_C_GTX_N1 PEX_TX1
0.22U_0201_6.3V 2 1 CC48 BE26 BB26
<6> PEG_CRX_GTX_N1 0.22U_0201_6.3V CC43
PEX_TX1 PEX_HVDD 0710, add 3pcs10uF CG8396-CG8398 and 2pcs CG8399-CG8400, ref NV HWDG.
PEX_HVDD BB27
BK29 PEX_RX1 PEX_HVDD BB29
<6> PEG_CTX_C_GRX_P1 BL29 BB32
<6> PEG_CTX_C_GRX_N1 PEX_RX1 PEX_HVDD
PEX_HVDD BC26
PEG_CRX_GTX_P2 2 1 PEG_CRX_C_GTX_P2 BF27 BC27
<6> PEG_CRX_GTX_P2 PEG_CRX_GTX_N2 PEG_CRX_C_GTX_N2 PEX_TX2 PEX_HVDD
0.22U_0201_6.3V 2 1 CC45 BG27 PEX_TX2 PEX_HVDD BC29
<6> PEG_CRX_GTX_N2 0.22U_0201_6.3V CC44 PEX_HVDD BC30
BM29 PEX_RX2 PEX_HVDD BC32
BM30 PEX_RX2 PEX_HVDD BD27
<6> PEG_CTX_C_GRX_N2 BD30
PEG_CRX_GTX_P3 PEG_CRX_C_GTX_P3 PEX_HVDD
2 1 BG29 PEX_TX3
<6> PEG_CRX_GTX_P3 PEG_CRX_GTX_N3 0.22U_0201_6.3V PEG_CRX_C_GTX_N3
2 1 CC49 BH29 PEX_TX3
<6> PEG_CRX_GTX_N3 0.22U_0201_6.3V CC41
BL30 PEX_RX3
<6> PEG_CTX_C_GRX_P3 BK30 PEX_RX3
Under GPU PEX_HVDD Place between GPU and PS

PEG_CRX_GTX_P4 2 1 PEG_CRX_C_GTX_P4 BF29
0.22U_0201_6.3V 2 1 CC47 BE29
<6> PEG_CRX_GTX_N4 0.22U_0201_6.3V CC53
BK32
PEX_TX4
PEX_RX4
PEX_PLL_HVDD +1V8_MAIN
BL32 PEX_RX4 0726, change CG7863-CG7874 to 1u, ref NV HWDG.

22U_0603_4V_M
22U_0603_4V_M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
PEG_CRX_GTX_P5 2 1 PEG_CRX_C_GTX_P5 BF30 +1V8_MAIN
<6> PEG_CRX_GTX_P5 PEG_CRX_GTX_N5 PEG_CRX_C_GTX_N5 PEX_TX5 2 2 2 1 1
0.22U_0201_6.3V 2 1 CC52 BG30 PEX_TX5
<6> PEG_CRX_GTX_N5 0.22U_0201_6.3V CC40 BB30
CG8
CG8391
CG8392
CG8393
CG8394
PEX_PLL_HVDD
BM32 PEX_RX5
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
<6> PEG_CTX_C_GRX_P5 1 1 1 2 2
BM33 PEX_RX5 1 1 1 1 1 1 1 1 1 1 1 1
PEG_CRX_GTX_P6 2 1 PEG_CRX_C_GTX_P6 BG32
CG7863
CG7864
CG7865
CG7866
CG7867
CG7868
CG7869
CG7870
CG7871
CG7872
CG7873
CG7874
0.22U_0201_6.3V 2 1 CC42 BH32 PEX_TX6
<6> PEG_CRX_GTX_N6 0.22U_0201_6.3V CC55 2 2 2 2 2 2 2 2 2 2 2 2
BL33 PEX_RX6
<6> PEG_CTX_C_GRX_P6 BK33
<6> PEG_CTX_C_GRX_N6 PEX_RX6
PEG_CRX_GTX_P7 PEG_CRX_C_GTX_P7 0710, add 2X10uF CG8391-CG8392 and 2X22uF CG8393-CG8394, ref NV HWDG.
0.22U_0201_6.3V 2 1 CC54 BF32 PEX_TX7
<6> PEG_CRX_GTX_P7 PEG_CRX_GTX_N7 2 1 CC46 PEG_CRX_C_GTX_N7 BE32 +1V8_MAIN
0.22U_0201_6.3V PEX_TX7
3 <6> PEG_CRX_GTX_N7 3
BK35 PEX_RX7
BL35 PEX_RX7
4.7U_0402_4V_M
4.7U_0402_4V_M
4.7U_0402_4V_M
BF33 PEX_TX8 1 1 1
BG33 PEX_TX8
CG7211
CG7212
CG7213
BM35 PEX_RX8
BM36 2 2 2
PEX_RX8
BG35 PEX_TX9
BH35 PEX_TX9
BL36 PEX_RX9
BK36 PEX_RX9
BF35 PEX_TX10
BE35 PEX_TX10
22uF 10uF 4.7uF 1uF 0.47uF
BK38 PEX_RX10
BL38 PEX_RX10
BF36 PEX_TX11 PEX_DVDD 2 3 3 16 0

BG36 PEX_TX11
BM38
BM39
PEX_RX11
PEX_RX11 PEX_HVDD 2 3 3 12 0
BG38 PEX_TX12
BH38 PEX_TX12
BL39 PEX_RX12
BK39 PEX_RX12
BF38 PEX_TX13
BE38 PEX_TX13
BK41 PEX_RX13
BL41 PEX_RX13
BF39 PEX_TX14
BG39 PEX_TX14
BM41 PEX_RX14
BM42 PEX_RX14
BH41 PEX_TX15
BG41 PEX_TX15
BL42 BL44 PEX_TERMP 2 1

PEX_RX15 PEX_TERMP
4 BK42 PEX_RX15 4
RG23
2.49K_0201_1%

NV(1/6) PCI EXPRESS
A B C D E
A B C D E
UG1N
7/22 IFPAB
Place Near GPU +IFP_PLLVDD
DL-DVI DVI/HDMI DP
SD A SD A IFPA_AUX BH11
BG11 GPU_DPA_AUXN <42>
+1V8_MAIN
Under GPU UG1V
13/22 XTAL/PLL
SC L SC L IFPA_AUX GPU_DPA_AUXP <42> 1 2 BD12 SP_PLLVDD
22U_0603_4V_M
1U_0201_4V6M
1U_0201_4V6M
4.7U_0402_4V_M
RG1502
1K_0201_1% IFPA_L3 BF21 LG8 1 1 1 1 BC12 VID_PLLVDD
IFPAB_RSET TX C TX C GPU_DPA_N3 <42>
CG8387
CG7223
CG7224
2 1 BD23 IFPAB_RSET IFPA_L3 BG21 PBY160808T-300Y-N_2P
TX C TX C GPU_DPA_P3 <42>
CG7222
1 1
100MHz 2 2 2 2
BG23
TXD 0 TXD 0 IFPA_L2
BH23
GPU_DPA_N2 <42> 30ohm, Bead
+IFP_PLLVDD BD21 IFPAB_PLLVDD
TXD 0 TXD 0 IFPA_L2 GPU_DPA_P2 <42>
FOR TBT DDI1
1U_0201_4V6M
IFPA_L1 BF23
TXD 1 TXD 1 GPU_DPA_N1 <42>
8/28 DVT1 change net name from 1 IFPA_L1 BE23
TXD 1 TXD 1 GPU_DPA_P1 <42>
CG312
U42 GPCPLL_AVDD0
+1V8_MAIN to +IFP_PLLVDD
TXD 2 TXD 2 IFPA_L0 BF24 0710, add CG8387 22uF, ref NV HWDG. AF11 GPCPLL_AVDD1
2 GPU_DPA_N0 <42>
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
TXD 2 TXD 2 IFPA_L0 BG24
GPU_DPA_P0 <42>
1 1 1 BB24 XSN_PLLVDD
CG7225
CG7226
CG7227
2 2 2
XTALOUTBUFF : 100K ohm pull down only.
Under GPU SD A IFPB_AUX BG12
BH12 GPU_DPB_AUXN <42> +1V8_AON
SC L IFPB_AUX GPU_DPB_AUXP <42>
0710, change CG7223-CG7227 to 1uF, ref NV HWDG. RG1497
0710, add CG8389 4.7uF, ref NV HWDG. XTALOUTBUFF_R
IFPB_L3 BL18 BJ6 EXT_REFCLK_FL XTALOUTBUFF BK6 1 @ 2
TX C GPU_DPB_N3 <42>
+PEX_VDD
BB18 IFP_IOVDD IFPB_L3 BK18
GPU_DPB_P3 <42> XTALIN_R BL6 BM6 XTALOUT_R
TX C
BB17 IFP_IOVDD XTALIN XTALOUT 100K_0201_5%
1
1U_0201_4V6M
4.7U_0402_4V_M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
FOR TBT DDI2
2
1 1 1 1 1 BB20 IFP_IOVDD IFPB_L2 BK20 RG1498 RG1496 RG98
TXD 3 TXD 0 GPU_DPB_N2 <42>
CG7214
CG7138
CG7139
CG7140
BB21 IFP_IOVDD IFPB_L2 BL20 10K_0201_5% 10K_0201_5% RG30 @ RG31 100K_0201_5%

TXD 3 TXD 0 GPU_DPB_P2 <42>
CG8389
0_0201_5% 0_0201_5%
EMI@ RG99 EMI@
2
2 2 2 2 2 BM20 10M_0201_5%
IFPB_L1 GPU_DPB_N1 <42>
1
TXD 4 TXD 1
IFPB_L1 BM21 1 2
TXD 4 TXD 1 GPU_DPB_P1 <42>
1
YG1
TXD 5 TXD 2 IFPB_L0 BL21 CG6825
GPU_DPB_N0 <42> 18P_0201_50V8J
TXD 5 TXD 2 IFPB_L0 BK21 XTALIN 1 3 XTALOUT
Near GPU IFPAB

GPU_DPB_P0 <42> 2
2
1
NC1 NC2
3
2
Under GPU 1
CG75
22P_0201_50V8J 2 4
1
CG8366
22P_0201_50V8J
@
2 27MHZ_10PF_XRCGB27M000F2P18R0 2
RG1499
1K_0201_1%
2 1
HDMI 2.0
UG1O
8/22 IFPC
IFPCD_RSET BD20 IFPCD_RSET

+IFP_PLLVDD
Under GPU BD18

DVI/HDMI DP
BL9 eDP
IFPCD_PLLVDD SDA IFPC_AUX GPU_HDMI_CTRL_DAT <40>
IFPC_AUX BK9
SCL GPU_HDMI_CTRL_CLK <40>
1U_0201_4V6M
UG1P
1 9/22 IFPD
CG7108
IFPC_L3 BF17
TXC GPU_HDMI_CLKN <40>
IFPC_L3 BE17
TXC GPU_HDMI_CLKP <40>
DVI/HDMI DP
2 BF18
TXD0 IFPC_L2 GPU_HDMI_TX_N0 <40>
IFPC_L2 BG18
TXD0 GPU_HDMI_TX_P0 <40>
BF11
IFPC IFPD_AUX
Near GPU TXD1
TXD1
IFPC_L1
IFPC_L1
BG20
BH20 GPU_HDMI_TX_N1
GPU_HDMI_TX_P1
<40>
<40>
SDA
SCL IFPD_AUX BE11 GPU_EDP_AUXN
GPU_EDP_AUXP
<38>
<38>
IFPC_L0 BF20 TXC IFPD_L3 BM14

TXD2 GPU_HDMI_TX_N2 <40> GPU_EDP_TXN3 <38>
IFPC_L0 BE20 TXC IFPD_L3 BM15
TXD2 GPU_HDMI_TX_P2 <40> GPU_EDP_TXP3 <38>
IFPD_L2 BL15
TXD0 GPU_EDP_TXN2 <38>
+PEX_VDD BB23 IFP_IOVDD IFPD_L2 BK15
TXD0 GPU_EDP_TXP2 <38>
BC17 IFP_IOVDD IFPD
1U_0201_4VAM
1U_0201_4VAM
4.7U_0402_4V_M
TXD1 IFPD_L1 BK17

GPU_EDP_TXN1 <38>
1 1 1 TXD1 IFPD_L1 BL17
GPU_EDP_TXP1 <38>
CG7126
CG6502
@
CG7216
IFPD_L0 BM17
2 2 2 Under GPU TXD2
TXD2 IFPD_L0 BM18
GPU_EDP_TXN0
GPU_EDP_TXP0
<38>
<38>
+PEX_VDD
BC18 IFP_IOVDD
BC20 IFP_IOVDD
1U_0201_4VAM
1
Near GPU Under GPU
CG7130
3 @ 3
0710, remove CG7127 , ref NV HWDG. 2
UG1Q
mini DP
10/22 IFPE
DVI/HDMI DP
RG1500
1K_0201_1%
2 1 IFPEF_RSET BD17 BL8
IFPE_RSET SDA IFPE_AUX GPU_DP_AUXN <39>
SCL IFPE_AUX BK8
GPU_DP_AUXP <39>
+IFP_PLLVDD
IFPE_L3 BG14
BD15 TXC
BH14 GPU_DP_N3 <39>
IFPE_PLLVDD TXC IFPE_L3 GPU_DP_P3 <39>
1U_0201_4V6M
IFPE_L2 BF14
TXD0 GPU_DP_N2 <39>
0710, change CG7220 to 1uF, ref NV HWDG. 1 TXD0 IFPE_L2 BE14
GPU_DP_P2 <39>
CG7220
TXD1 IFPE_L1 BF15

GPU_DP_N1 <39>
TXD1 IFPE_L1 BG15
2 GPU_DP_P1 <39>
IFPE
IFPE_L0 BG17
TXD2 GPU_DP_N0 <39>
TXD2 IFPE_L0 BH17
GPU_DP_P0 <39>
+PEX_VDD
BC21 IFP_IOVDD
BC23 IFP_IOVDD
4.7U_0402_4V_M
1U_0201_4VAM
1 1
CG8388
CG8390
@
2 2
4
Near GPU Under GPU 4
0710, add CG8388 1uF and CG8390 4.7uF, ref NV HWDG.

NV(2/6) IFP_ABCDEF_DAC_XTAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
A B C D E
5 4 3 2 1
UG1K +1V8_AON
20/22 NC/1V8
1V8_AON BA10
UG1F UG1G
1V8_AON BB14
UG1H
15/22 GND_1/3 16/22 GND_2/3 1V8_AON BC14
21/22 GND_3/3
A2 GND GND AH6 AR20 GND GND B52 +1V8_AON
A26 GND GND AH8 AR21 GND GND B7 BL40 GND GND N51 +NVVDD +NVVDD +NVVDD +NVVDD +NVVDD +NVVDD
A29 GND GND AJ14 AR22 GND GND BA48 BL43 GND GND N6 UG9
UG1I UG1J UG1M FP_FUSE_GPU
A3 GND GND AJ15 AR23 GND GND BA9 BL5 GND GND N8 6 1 BD14 NC BD24
FP_FUSE_SRC
A32 GND GND AJ16 AR24 GND GND BB49 BL7 GND GND P14 17/22 VDD_1/3 18/22 VDD_2/3 22/22 VDD_3/3 5 VIN1 VOUT1 2 NC BM44
VIN2 VOUT2
2
A50 AJ17 AR25 BC13 BM2 P15 BM45
2.2U_0201_6.3V6M
D GND GND GND GND GND GND 2 NC D
CG7117
A51 AJ18 AR26 BC16 BM3 P16 AA13 AE28 AH39 AP23 4 3 RG1559
2.2U_0201_6.3V6M
GND GND GND GND GND GND VDD VDD VDD VDD 2 VSS EN
CG270
AA49 GND GND AJ19 AR27 GND GND BC19 C1 GND GND P17 AA14 VDD VDD AE29 AH40 VDD VDD AP24 BG45 VDD VDD R23 2.21K_0402_1%
AA8 GND GND AJ2 AR28 GND GND BC2 C29 GND GND P18 AA15 VDD VDD AE30 AJ13 VDD VDD AP25 BG46 VDD VDD R24 GS7616SC-R_SOT363-6
AB10 AJ20 AR29 BC22 C33 P19 AA16 AE31 AJ40 AP26 BG47 R25 1
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD
1
AB14 AJ21 AR30 BC25 C5 P20 AA17 AE32 AK13 AP27 BG48 R26 1
AB15 GND GND AJ22 AR31 GND GND BC28 C51 GND GND P21 AA18 VDD VDD AE33 AK14 VDD VDD AP28 BG49 VDD VDD R27
AB16 GND GND AJ23 AR32 GND GND BC31 C52 GND GND P22 AA19 VDD VDD AE34 AK15 VDD VDD AP29 BG50 VDD VDD R28 @
AB17 GND GND AJ24 AR33 GND GND BC34 D10 GND GND P23 AA20 VDD VDD AE35 AK16 VDD VDD AP30 BG51 VDD VDD R29
AB18
AB19
GND
GND
GND
GND
AJ25
AJ26
AR34
AR35
GND
GND
GND
GND
BC37
BC4
D12
D13
GND
GND
GND
GND
P24
P25
AA21
AA22
VDD
VDD
VDD
VDD
AE36
AE37
AK17
AK18
VDD
VDD
VDD
VDD
AP31
AP32
BG52
BH44
VDD
VDD
VDD
VDD
R30
R31
<30> FP_FUSE
20190425
2
AB2 AJ27 AR36 BC51 D16 P26 AA23 AE38 AK19 AP33 BH45 R32
AB20
AB21
GND
GND
GND
GND
GND
GND
AJ28
AJ29
AR37
AR38
GND
GND
GND
GND
GND
GND
BC6
BC8
D19
D22
GND
GND
GND
GND
GND
GND
P27
P28
AA24
AA25
VDD
VDD
VDD
VDD
VDD
VDD
AE39
AE40
AK20
AK21
VDD
VDD
VDD
VDD
VDD
VDD
AP34
AP35
BH47
BH48
VDD
VDD
VDD
VDD
VDD
VDD
R33
R34
RG1558
10K_0201_1%
change capacitor refer to NV
AB22 GND GND AJ30 AR39 GND GND BD26 D24 GND GND P29 AA26 VDD VDD AF13 AK22 VDD VDD AP36 BH49 VDD VDD R35
Under GPU
1
AB26 GND GND AJ34 AT4 GND GND BD38 D31 GND GND P33 AA30 VDD VDD AF17 AK26 VDD VDD AP40 BJ44 VDD VDD R39 +1V8_AON
AB27 GND GND AJ35 AT5 GND GND BD52 D34 GND GND P34 AA31 VDD VDD AF18 AK27 VDD VDD AR13 BJ45 VDD VDD R40
AB28 GND GND AJ36 AT51 GND GND BE10 D37 GND GND P35 AA32 VDD VDD AF24 AK28 VDD VDD AR40 BJ46 VDD VDD T13
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
AB29 GND GND AJ37 AT52 GND GND BE13 D4 GND GND P36 AA33 VDD VDD AF25 AK29 VDD VDD AT13 BJ47 VDD VDD T40
AB30 GND GND AJ38 AT8 GND GND BE15 D40 GND GND P37 AA34 VDD VDD AF26 AK30 VDD VDD AT14 BJ48 VDD VDD U13 1 1 1
CG7245
CG7875
CG7876
AB31 GND GND AJ39 AU10 GND GND BE16 D43 GND GND P38 AA35 VDD VDD AF30 AK31 VDD VDD AT15 BJ49 VDD VDD U14
AB32 GND GND AJ9 AU14 GND GND BE18 D46 GND GND P39 AA36 VDD VDD AF31 AK32 VDD VDD AT16 BJ50 VDD VDD U15 +1.35VS_VGA +1.35VS_VGA
AB33 AK1 AU15 BE19 D49 P51 AA37 AF32 AK33 AT17 BJ51 U16 UG1L
AB34 AK44 AU16 BE21 D7 R49 AA38 AF33 AK34 AT18 BJ52 U17 2 2 2
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD 19/22 FBVDDQ
AB35 GND GND AK47 AU17 GND GND BE22 E2 GND GND R52 AA39 VDD VDD AF34 AK35 VDD VDD AT19 BK47 VDD VDD U18
AB36 GND GND AL10 AU18 GND GND BE24 E4 GND GND T10 AA40 VDD VDD AF40 AK36 VDD VDD AT20 BK48 VDD VDD U19 AA10 FBVDDQ FBVDDQ AT43
AB37 GND GND AL14 AU19 GND GND BE25 E48 GND GND T14 AB13 VDD VDD AG13 AK37 VDD VDD AT21 BK49 VDD VDD U20 AA11 FBVDDQ FBVDDQ K12 0710, change CG7245, CG7875, CG7876 to 1uF, ref NV HWDG.
AB38 GND GND AL15 AU2 GND GND BE27 E5 GND GND T15 AB40 VDD VDD AG19 AK38 VDD VDD AT22 BK50 VDD VDD U21 AA42 FBVDDQ FBVDDQ K14
AB39 GND GND AL16 AU20 GND GND BE28 E51 GND GND T16 AC13 VDD VDD AG20 AK39 VDD VDD AT23 BK51 VDD VDD U22 AA43 FBVDDQ FBVDDQ K15
AB4 GND GND AL17 AU21 GND GND BE30 E8 GND GND T17 AC14 VDD VDD AG21 AK40 VDD VDD AT24 BK52 VDD VDD U23 AC10 FBVDDQ FBVDDQ K17
AB43 GND GND AL18 AU22 GND GND BE31 F10 GND GND T18 AC15 VDD VDD AG22 AL13 VDD VDD AT25 BL46 VDD VDD U24 AC11 FBVDDQ FBVDDQ K18
AB45
AB47
AB49
GND
GND
GND
GND
AL19
AL2
AL20
AU23
AU24
AU25
GND
GND
GND
GND
BE33
BE34
BE36
F13
F16
F17
GND
GND
GND
GND
T19
T2
T20
AC16
AC17
AC18
VDD
VDD
VDD
VDD
AG23
AG27
AG28
AL40
AM13
AM14
VDD
VDD
VDD
VDD
AT26
AT27
AT28
BL47
BL48
BL49
VDD
VDD
VDD
VDD
U25
U26
U27
AC42
AC43
AD10
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
K20
K21
K23
+1V8_AON
Near GPU
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD FBVDDQ FBVDDQ
AB51 GND GND AL21 AU26 GND GND BE37 F19 GND GND T21 AC19 VDD VDD AG29 AM15 VDD VDD AT29 BL50 VDD VDD U28 AD11 FBVDDQ FBVDDQ K24
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
4.7U_0402_4V_M
4.7U_0402_4V_M
4.7U_0402_4V_M
C AB6 GND GND AL22 AU27 GND GND BE39 F21 GND GND T22 AC20 VDD VDD AG35 AM16 VDD VDD AY26 BL51 VDD VDD U29 AD42 FBVDDQ FBVDDQ K26 C
AB8 GND GND AL23 AU28 GND GND BE40 F22 GND GND T23 AC21 VDD VDD AG36 AM17 VDD VDD AY27 BL52 VDD VDD U30 AD43 FBVDDQ FBVDDQ K27 1 1 1 1 1 1
CG7877
CG7878
CG7879
AD14 GND GND AL24 AU29 GND GND BF2 F25 GND GND T24 AC22 VDD VDD AG37 AM18 VDD VDD AY28 BM47 VDD VDD U31 AF10 FBVDDQ FBVDDQ K29
CG8401
CG8402
CG8403
AD15 GND GND AL25 AU30 GND GND BF4 F28 GND GND T25 AC23 VDD VDD AG38 AM19 VDD VDD AY29 BM48 VDD VDD U32 AF43 FBVDDQ FBVDDQ K30
AD16 GND GND AL26 AU31 GND GND BF41 F31 GND GND T26 AC24 VDD VDD AG39 AM20 VDD VDD AY30 BM49 VDD VDD U33 AG10 FBVDDQ FBVDDQ K32
AD17 AL27 AU32 BF6 F34 T27 AC25 AG40 AM21 AY31 BM50 U34 AG11 K33 2 2 2 2 2 2
AD18 GND GND AL28 AU33 GND GND BG10 F35 GND GND T28 AC26 VDD VDD AH13 AM22 VDD VDD AY32 BM51 VDD VDD U35 AG42 FBVDDQ FBVDDQ K35
AD19 GND GND AL29 AU34 GND GND BG13 F37 GND GND T29 AC27 VDD VDD AH14 AM23 VDD VDD AY33 N13 VDD VDD U36 AG43 FBVDDQ FBVDDQ K36
AD20 GND GND AL30 AU35 GND GND BG16 F40 GND GND T30 AC28 VDD VDD AH15 AM24 VDD VDD AY34 N14 VDD VDD U37 AJ10 FBVDDQ FBVDDQ K38
AD21 GND GND AL31 AU36 GND GND BG19 F43 GND GND T31 AC29 VDD VDD AH16 AM25 VDD VDD AY35 N15 VDD VDD U38 AJ11 FBVDDQ FBVDDQ K39 0710, change CG7877-CG7879 to 1uF, ref NV HWDG.
AD22 GND GND AL32 AU37 GND GND BG22 F44 GND GND T32 AC30 VDD VDD AH17 AM26 VDD VDD AY36 N16 VDD VDD U39 AJ42 FBVDDQ FBVDDQ K41 0710, remove CG7880-CG7882, ref NV HWDG.
AD23 GND GND AL33 AU38 GND GND BG25 F46 GND GND T33 AC31 VDD VDD AH18 AM27 VDD VDD AY37 N17 VDD VDD U40 AJ43 FBVDDQ FBVDDQ L14 0710, add CG8401-CG8403 4.7uF, ref NV HWDG.
AD24 GND GND AL34 AU39 GND GND BG28 F52 GND GND T34 AC32 VDD VDD AH19 AM28 VDD VDD AY38 N18 VDD VDD V13 AK10 FBVDDQ FBVDDQ L15
AD25 GND GND AL35 AU4 GND GND BG31 F7 GND GND T35 AC33 VDD VDD AH20 AM29 VDD VDD AY39 N19 VDD VDD V40 AK11 FBVDDQ FBVDDQ L18
AD26 AL36 AU45 BG34 G2 T36 AC34 AH21 AM30 AY40 N20 W13 AK42 L20 FB_GND_SENSE_R 1 2
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD FBVDDQ FBVDDQ FB_GND_SENSE <108>
AD27 GND GND AL37 AU47 GND GND BG37 G38 GND GND T37 AC35 VDD VDD AH22 AM31 VDD VDD AY43 N21 VDD VDD W14 AK43 FBVDDQ FBVDDQ L21 RG7 2_0201_1%
AD28 GND GND AL38 AU49 GND GND BG40 G4 GND GND T38 AC36 VDD VDD AH23 AM32 VDD VDD AY45 N22 VDD VDD W15 AM42 FBVDDQ FBVDDQ L23
AD29 GND GND AL39 AU51 GND GND BG42 G47 GND GND T39 AC37 VDD VDD AH24 AM33 VDD VDD BA43 N23 VDD VDD W16 AM43 FBVDDQ FBVDDQ L24
AD30 GND GND AL4 AU6 GND GND BG7 G49 GND GND T4 AC38 VDD VDD AH25 AM34 VDD VDD BA44 N24 VDD VDD W17 AN43 FBVDDQ FBVDDQ L26
AD31 GND GND AL43 AU8 GND GND BH15 G51 GND GND T43 AC39 VDD VDD AH26 AM35 VDD VDD BA45 N25 VDD VDD W18 AR42 FBVDDQ FBVDDQ L27
AD32 GND GND AL45 AV4 GND GND BH18 G6 GND GND T45 AC40 VDD VDD AH27 AM36 VDD VDD BA46 N26 VDD VDD W19 AR43 FBVDDQ FBVDDQ L30
AD33
AD34
AD35
GND
GND
GND
GND
AL47
AL49
AL51
AV45
AV9
AW14
GND
GND
GND
GND
BH2
BH21
BH24
H1
H10
H13
GND
GND
GND
GND
T47
T49
T51
AD13
AD40
AE13
VDD
VDD
VDD
VDD
AH28
AH29
AH30
AM37
AM38
AM39
VDD
VDD
VDD
VDD
BA47
BB38
BB39
N27
N28
N29
VDD
VDD
VDD
VDD
W20
W21
W22
R42
R43
U10
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
L32
L33
L35
RG7 near GPU
AD36 GND GND AL6 AW15 GND GND BH27 H16 GND GND T6 AE14 VDD VDD AH31 AM40 VDD VDD BB45 N30 VDD VDD W23 U11 FBVDDQ FBVDDQ L36
AD37 GND GND AL8 AW16 GND GND BH30 H19 GND GND T8 AE15 VDD VDD AH32 AN13 VDD VDD BB46 N31 VDD VDD W24 U43 FBVDDQ FBVDDQ L39
AD38 GND GND AM4 AW17 GND GND BH33 H22 GND GND U7 AE16 VDD VDD AH33 AN40 VDD VDD BB47 N32 VDD VDD W25 V10 FBVDDQ FBVDDQ M10
AD39 GND GND AM9 AW18 GND GND BH36 H25 GND GND U9 AE17 VDD VDD AH34 AP13 VDD VDD BB48 N33 VDD VDD W26 V42 FBVDDQ FBVDDQ M43
AD44 GND GND AN14 AW19 GND GND BH39 H28 GND GND V14 AE18 VDD VDD AH35 AP14 VDD VDD BC38 N34 VDD VDD W27 V43 FBVDDQ FBVDDQ P10
AE10 GND GND AN15 AW20 GND GND BH42 H31 GND GND V15 AE19 VDD VDD AH36 AP15 VDD VDD BC39 N35 VDD VDD W28 Y10 FBVDDQ FBVDDQ P11
AE2 GND GND AN16 AW21 GND GND BH5 H34 GND GND V16 AE20 VDD VDD AH37 AP16 VDD VDD BC40 N36 VDD VDD W29 Y11 FBVDDQ FBVDDQ P42
AE4 GND GND AN17 AW22 GND GND BJ10 H37 GND GND V17 AE21 VDD VDD AH38 AP17 VDD VDD BC41 N37 VDD VDD W30 Y42 FBVDDQ FBVDDQ P43
AE43 GND GND AN18 AW23 GND GND BJ12 H40 GND GND V18 AE22 VDD VDD AV28 AP18 VDD VDD BC45 N38 VDD VDD W31 Y43 FBVDDQ FBVDDQ R10
AE45 GND GND AN19 AW24 GND GND BJ13 H43 GND GND V19 AE23 VDD VDD AV29 AP19 VDD VDD BC47 N39 VDD VDD W32 FBVDDQ R11
AE47 GND GND AN20 AW25 GND GND BJ14 J1 GND GND V20 AE24 VDD VDD AV30 AP20 VDD VDD BC49 N40 VDD VDD W33
AE49 GND GND AN21 AW26 GND GND BJ15 J12 GND GND V21 AE25 VDD VDD AV31 AP21 VDD VDD BD39 P13 VDD VDD W34
AE51 GND GND AN22 AW27 GND GND BJ16 J17 GND GND V22 AE26 VDD VDD AV32 AP22 VDD VDD BE48 P40 VDD VDD W35
AE6 GND GND AN23 AW28 GND GND BJ17 J20 GND GND V23 AE27 VDD VDD AV33 BD41 VDD VDD BE49 R13 VDD VDD W36
B
AE8 AN24 AW29 BJ18 J38 V24 AT30 AV34 BD46 BE50 R14 W37 E52 FB_VDDQ_SENSE_R 1 2 B
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD FBVDDQ_SENSE FB_VDDQ_SENSE <108>
AF1 GND GND AN25 AW30 GND GND BJ19 J49 GND GND V25 AT31 VDD VDD AV35 BD47 VDD VDD BE51 R15 VDD VDD W38 RG35 2_0201_1%
AF19 GND GND AN26 AW31 GND GND BJ20 J52 GND GND V26 AT32 VDD VDD AV36 BD48 VDD VDD BE52 R16 VDD VDD W39
AF20 GND GND AN27 AW32 GND GND BJ21 K13 GND GND V27 AT33 VDD VDD AV37 BD49 VDD VDD BF42 R17 VDD VDD W40
AF21 AN28 AW33 BJ22 K16 V28 AT34 AV38 BD50 BF44 R18 Y13 P45 FB_VREF
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD FB_VREF
AF22 GND GND AN29 AW34 GND GND BJ23 K19 GND GND V29 AT35 VDD VDD AV39 BD51 VDD VDD BF45 R19 VDD VDD Y40
AF23 GND GND AN30 AW35 GND GND BJ24 K2 GND GND V30 AT36 VDD VDD AV40 BE41 VDD VDD BF47 R20 VDD
+1.35VS_VGA
AF29 GND GND AN33 AW38 GND GND BJ27 K28 GND GND V33 AT39 VDD VDD AV44 BE46 VDD VDD BG43
AF35 GND GND AN34 AW39 GND GND BJ28 K31 GND GND V34 AT40 VDD VDD AW13 BE47 VDD VDD BG44 FB_CAL_PD_VDDQ R44 FBCAL_VDDQ RG67 1 2 40.2_0402_1%
AF36 GND GND AN35 AW4 GND GND BJ29 K34 GND GND V35 AT42 VDD VDD AW40
AF37 AN36 AW46 BJ30 K37 V36 AU13 AW42 P44 FBCAL_GND RG68 1 2 40.2_0402_1%
GND GND GND GND GND GND VDD VDD FB_CAL_PU_GND
AF38 GND GND AN37 AW5 GND GND BJ31 K4 GND GND V37 AU40 VDD VDD AW43 NVVDD_SENSE BK45
AF39 AN38 AW52 BJ32 K40 V38 AU43 AW44 BL45 NVVDD_VCC_SENSE <102> R45 FBCAL_TERM
GND GND GND GND GND GND VDD VDD GND_SENSE FB_CALTERM_GND RG69 1 2 40.2_0402_1%
NVVDD_VSS_SENSE <102>
AF45 GND GND AN39 AW8 GND GND BJ33 K45 GND GND V39 AV13 VDD VDD AW45
AF5 GND GND AN4 AY10 GND GND BJ34 K47 GND GND V49 AV14 VDD VDD AY13
AG14 GND GND AN5 AY2 GND GND BJ35 K49 GND GND V52 AV15 VDD VDD AY14
AG15 GND GND AN8 AY4 GND GND BJ36 K51 GND GND W10 AV16 VDD VDD AY15 @ @
AG16 GND GND AP10 AY47 GND GND BJ37 K6 GND GND W2 AV17 VDD VDD AY16 @
AG17 GND GND AP2 AY49 GND GND BJ38 K8 GND GND W4 AV18 VDD VDD AY17 Refer to the GPU-specific Partner Guidelines document for
AG18 GND GND AP4 AY51 GND GND BJ39 M52 GND GND W43 AV19 VDD VDD AY18
AG24 GND GND AP43 AY6 GND GND BJ40 M6 GND GND Y9 AV20 VDD VDD AY19 the final Driver Calibration values. Only 1% resistors should
AG25 GND GND AP45 AY8 GND GND BJ41 N10 GND AV21 VDD VDD AY20 be used for driver calibration.
AG26 GND GND AP47 B1 GND GND BJ42 N2 GND AV22 VDD VDD AY21
AG3 GND GND AP49 B10 GND GND BJ43 N4 GND AV23 VDD VDD AY22
AG30 AP51 B13 BJ7 N43 AV24 AY23 FB_VREF
GND GND GND GND GND VDD VDD
AG31 GND GND AP6 B16 GND GND BK1 N45 GND AV25 VDD VDD AY24
AG32 GND GND AP8 B19 GND GND BL1 N47 GND AV26 VDD VDD AY25
1
AG33 GND GND AR14 B2 GND GND BL10 N49 GND
AV27 VDD 1
AG34 GND GND AR15 B22 GND GND BL13 BL37 GND RG59 CG6826
AG44 GND GND AR16 B25 GND GND BL16 49.9_0402_1% 3.9P_0402_50V8C
AH10 GND GND AR17 B28 GND GND BL19
AH2 AR18 B31 BL2 @ @ 2
GND GND GND GND
2
AH4 GND GND AR19 B34 GND GND BL22
AH43 GND GND BL34 B37 GND GND BL25
AH45 GND GND BC24 B40 GND GND BL28
A AH47 GND B43 GND GND BL31 A
AH49 GND B46 GND GND B5
AH51 GND B48 GND GND B51
@ @

NV(3/6) Power_GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
0.2
5 4 3 2 1
A B C D E
Main Func = GPU

+1V8_AON +3VS DGPU_PEX_RST#
DGPU_PEX_RST#
+1V8_AON
GPIO
1
@ QG526B
5
GC6_FB_EN: RG561 QG6B DMN53D0LDW-7 2N SOT363-6
5
100K_0201_5% DMN53D0LDW-7 2N SOT363-6 I2CB_SCL
requires a 10kohm pulled-down
2
G
VGA_SMB_CK2 4 3
UG1T 4 3 SCL_EDP <38>
GPU_GC6_FB_EN GC6_EVENT#_D
2
3 1 EC_SMB_CK2 <16,34,58,64,74,77,102> @ QG526A RG8 1 2 10K_0201_5%
12/22 MISC 1 GPU_EVENT# GC6_FB_EN <18>
2
S
D
QG6A I2CB_SDA DMN53D0LDW-7 2N SOT363-6
reqires a 10 kohm pulled-up to 1V8_AON. DMN53D0LDW-7 2N SOT363-6 1 6 OVERT# RG9 1 2 10K_0201_5%
VGA_SMB_CK2 VGA_SMB_DA2 SDA_EDP <38>
OVERT# BG5 OVERT I2CS_SCL BJ8 VGA_SMB_DA2 PCH/EC pin connected to GPU_EVENT# must be QG511 1 6
BH8 EC_SMB_DA2 <16,34,58,64,74,77,102>
I2CS_SDA open-drain for output function to prevent back drive if BSS138W_SOT-323-3 EC_AC_BAT#
RG16 1 2 10K_0201_5%
BF12 +1V8_AON diode is not used.
TS_VREF I2CC_SCL VGA_SMB_CK2
I2CC_SCL
BG9 I2CC_SDA RG17 1 2 1.8K_0402_5%
BH9
I2CC_SDA 1V8_MAIN_EN: VGA_SMB_DA2
1 2
RG18 1.8K_0402_5%
is an open-drain GPIO. +3VS
I2CB_SCL 1V8_MAIN_EN
I2CB_SCL
BG8 I2CB_SDA RG19 1 2 2.2K_0201_1% It requires a 10 kohm pull-up to the 1V8_AON power domain. RG27 1 2 10K_0201_5%
BF8 RG20 1 2 2.2K_0201_1% +1V8_AON
I2CB_SDA THERM_ALERT#
+3VS RG504 1 2 10K_0201_5%
FRAME_LOCK#:
is an assert-low signal and is required to pull-
1
BJ1 THERMDN DP_CBL_DET#
up to 1V8_AON with a 10K? resistor. 1V8_AON is required to be +1V8_AON RG1627 RG501 1 2 10K_0201_5%
BJ2 THERMDP powered up while the GPU is resident in GC6, and must be 10K_0201_5%
1
powered on at all times while the panel is powered. OC_WARN#
2
RG1624 DGPU_BL_EN RG522 1 2 10K_0201_5%
2
DG2 RG530 RG29 RG28 DGPU_PEX_RST# 100K_0201_5% SWAPRDY_IN
BD6 DGPU_BL_EN <38> 1 2
GPIO0 GPU_GC6_FB_EN RB751S-40_SOD523-2 10K_0201_5% 1.8K_0201_1% 1.8K_0201_1% RG526 2.2K_0201_5%
NVVDD_PWM_VID <102>
6
BB5 @ UV26A D
External current sense for power monitoring GPIO1 GC6_EVENT#_D GPU_GC6_FB_EN <32>2 DGPU_ENBKL
2
GPIO2
BD1 MUX_CTL_INTERNAL 1 QG7B 2 RG1617 1 @ 2 2.2K_0201_5%
GC6_EVENT# <18>
5
BJ9 ADC_IN GPIO3 BE4 1V8_MAIN_EN DP_CBL_DET# DMN53D0LDW-7 2N SOT363-6 G PWM_SW_SEL
<34> ADC_IN_P MUX_CTL_INTERNAL <38>
3
BJ11 BE1 1 @ 2 UV26B D RG1618 1 @ 2 2.2K_0201_5%
<34> ADC_IN_N ADC_IN GPIO4 FRAME_LOCK# 1V8_MAIN_EN <32,34,37> I2CC_SCL LCD_BLEN
GPIO5 BG2 GPU_NVVDD_PSI# RG540 0_0201_5% 4 3 5 S LBSS139DW1T1G_SOT363-6 MUX_CTL_INTERNAL
1
BD2 SCL_GPU <102> G RG1619 1 @ 2 2.2K_0201_5%
GPIO6 LCD_BL_PWM
2
1
GPIO7
BD7 QG7A 1
BH4 2
D
GPIO8 THERM_ALERT# QG500B G
I2CC_SDA DMN53D0LDW-7 2N SOT363-6 S LBSS139DW1T1G_SOT363-6
MEM_VDD_CTL <108> DP_CBL_DET <39>
4
GPIO9 BJ3 MEM_VREF_CTL L2N7002DW1T1G_SC88-6 S 1 6
BD3 SDA_GPU <102>
JTAG_TCLK GPIO10 LCD_VDD_EN MEM_VREF_CTL <35,36> RASTER_SYNC1
3
@ T10 PAD~D JTAG_TMS BK24 JTAG_TCK GPIO11
BH3 EC_AC_BAT# RG527 1 2 100K_0201_5%
BL23 BE6 LCD_VDD_EN <38> 5
D
+3VS
@ T11 PAD~D JTAG_TDI JTAG_TMS GPIO12 DGPU_ENBKL
G
QG500A LCD_BLEN
BM23 BB1 EC_AC_BAT# <58> 1 2
@ T12 PAD~D JTAG_TDO JTAG_TDI GPIO13 GPU_DPA_HPD# S
L2N7002DW1T1G_SC88-6 RG525 100K_0201_5%
BM24 BG4 DGPU_ENBKL <38>
@ T13 PAD~D JTAG_TRST# JTAG_TDO GPIO14 GPU_DPB_HPD# NB_FGC6
4
@ T16 BL24 BG1 +3VS RG21 1 2 10K_0201_5%
JTAG_TRST GPIO15 PWM_SW_SEL
PAD~D GPIO16
BE2 GPU_EDP_HPD# GPU_GC6_FB_EN
1
GPIO17
BH1 RG22 1 2 10K_0201_5%
GPIO18 BE3 RG1628 MEM_VREF_CTL
BK23 BD4 GPU_DP_HPD# <39> 1 2
@ T15 NVJTAG_SEL GPIO19 NB_FGC6 PAD~D T22 @ 10K_0201_5% RG24 1K_0201_5%
1
PAD~D GPIO20
BE5 LCD_BLEN DDS@ DGPU_PEX_RST#
BA5 NB_FGC6 <32> 1 2
GPIO21 SWAPRDY_IN RG1625 DGPU_LCD_EN RG25 1M_0201_1%
1
2
GPIO22
BB6 RASTER_SYNC1 100K_0201_5% LCD_BL_PWM
BG3 DGPU_LCD_EN <38> 1 2
RG518 RG26 GPIO23 DP_CBL_DET# DDS@ RG150 100K_0201_5%
6
10K_0201_5% 10K_0201_5% BD5 +1V8_AON UV27A D
GPIO24 GPU_FBVDD_PSI LCD_VDD_EN
2
GPIO25
BB2 FP_FUSE RG1595 2 RG40 1 2 10K_0201_5%
GPIO26
BE7 0_0201_5% G FP_FUSE
2
FP_FUSE <29>
3
BA4 2 1 UV27B D RG528 1 @ 2 10K_0201_5%
GPIO27 OC_WARN# GPU_HDMI_HPD# <40> LCD_VDD_EN
GPIO28 BB4 IDLE_IN_SW 5 S LBSS139DW1T1G_SOT363-6 DGPU_ENBKL
OC_WARN# <34>
1
GPIO29
BA3 G DDS@ RG1620 1 @ 2 10K_0201_5%
GPIO30
BB3 PAD~D T24 @ RG15 PWM_SW_SEL
10K_0201_5% S LBSS139DW1T1G_SOT363-6 RG1621 1 @ 2 10K_0201_5%
4
1 @ 2 DDS@ MUX_CTL_INTERNAL
1
NVVDD_PSI# <102>
RG1579 RG1622 1 @ 2 10K_0201_5%
1
Pin Name Default Functio n RG1504 10K_0201_1% C 300K_0201_1%
GPU_NVVDD_PSI#
@ 10K_0201_5% 1 @ 2 2 QX4 RG1580 +3VS
JTAG_ T RS T L JTAG module will drive signal. B
GPU side need to pull low as default
E MMBT3904WH_SOT323-3
3
+3VS
NVJTAG _ S E L L Test Mode --> Disable @
1
1
RG1578 @ RG1629
H Test Mode --> Enable CG7141 10K_0201_5%
10K_0201_5%
1
0.1U_0201_10V6K DDS@
2 RG1626 DGPU_PWM_SEL
2
100K_0201_5%
DGPU_PWM_SEL <38>
DDS@
6
UV28A D
2
2
G
3
UV28B D
PWM_SW_SEL
+3VS 5 S LBSS139DW1T1G_SOT363-6
1
G DDS@
QX6 +1V8_AON
LMBT3904WT1G_SC70-3 RG1596 S LBSS139DW1T1G_SOT363-6
4
C GPU_DPA_HPD 0_0201_5% DDS@
+1V8_AON 2 1 2 2 1
B GPU_DPA_HPD <42>
2
E RX42
3
150K_0201_5% 1 RG1581
1
<18> DP1_HPD_PCH
10K_0201_5%
RX40 CX3 1 @ 2
1
+1.8VALW PSI_FBVDDQ <108>
10K_0201_5% 0.1U_0201_16V6K RG1583
1
CV70 RX41 2 10K_0201_1% C 300K_0201_1%
GPU_FBVDD_PSI
1 2 10K_0201_5% 1 @ 2 2 QX5 RG1584
GPU_DPA_HPD#
2
B MMBT3904WH_SOT323-3
0.1U_0201_16V6K E +3VS
3
3
@
QV98B
VCC
2
DMN53D0LDW-7 2N SOT363-6 1 1 RG1555
1
5 4 IN B RG1582 @ +1V8_AON 0_0201_5%
OUT Y DGPU_PEX_RST# GPU_OVERT# <59> NVVDD_ENP
2 CG8367 RG534 1 @ 2
GND
IN A 20K_0201_5% NVVDD_ENP <32>

0.1U_0201_10V6K 10K_0201_1%
4
2 RB751S-40_SOD523-2
1
UX4 @ DG7
3
2
NL17SZ08DFT2G_SC70-5 RG533 GPU_OVERT# 1V8_MAIN_EN
100K_0201_5% 1 2 2 1
+3VS NVVDD_EN <34,98,102>
6
QX7 D DG3
DGPU_PEX_RST#
LMBT3904WT1G_SC70-3 RG568 1 2 100K_0201_5% 2 UG23A RB751S-40_SOD523-2
1
C <27,39,40> DGPU_PEX_RST# G PJT138KA_SOT363-6 1 2

GPU_DPB_HPD
+1V8_AON 2 1 2 RG549
GPU_DPB_HPD <42>
3
B D 100K_0201_5%
S 1
1
E RX45 OVERT# 5 UG23B
3
150K_0201_5% 1 G PJT138KA_SOT363-6 CG481

1
<18> DP2_HPD_PCH 2200P_0201_25V7K

2 RX43 CX4 S 2 2
1
4
10K_0201_5% +1.8VALW 0.1U_0201_16V6K
CV71 RX44 2 +3VS
1 2 10K_0201_5% +1V8_AON
GPU_DPB_HPD#
2
+3VS
6
0.1U_0201_16V6K +1V8_AON
1
QV98A
VCC
DMN53D0LDW-7 2N SOT363-6 1 RG201 RG516

2 4 IN B 10K_0201_5% 10K_0201_5%
DGPU_PEX_RST#
1
OUT Y 2
GND
IN A RG200 1
1
2
100K_0201_5% CG246
DGPU_BL_PWM <38>
UX5 0.1U_0201_6.3V6K
3
6
NL17SZ08DFT2G_SC70-5 UV22A D
2
2 2 +3VS
3
G
3
UV22B D QG521B
LCD_BL_PWM DGPU_PEX_RST#
VCC
5 S LBSS139DW1T1G_SOT363-6 1 DMN53D0LDW-7_SOT363-6
1
G IN B 4 1 2 5
2 OUT Y RG554 0_0201_5% RG506
GND
+1V8_AON LBSS139DW1T1G_SOT363-6 IN A 10K_0201_5%
S
4
UG22
6
QG502A NL17SZ08DFT2G_SC70-5 DG4
2
GPU_GC6_FB_EN RG553 DMN53D0LDW-7_SOT363-6 QG521A RB751S-40_SOD523-2
1
1 2 2 DMN53D0LDW-7_SOT363-6 NVVDD_PGOOD
RX46 2 2 1
3
10K_0201_5% 0_0201_5% NVVDD_PGOOD <27,32,39,98,102>
1
QG502B
1
GPU_EDP_HPD# LCD_VDD_EN DMN53D0LDW-7_SOT363-6
2
5
6
4
QV99A +1V8_AON
DMN53D0LDW-7 2N SOT363-6 GPU_EDP_HPD
2 1 2 +1V8_AON +3VS
GPU_EDP_HPD <38>
RX48 1
1
1
0_0201_5% CG476
3
1
RX47 RG202 0.1U_0201_6.3V6K
QV99B 100K_0201_5% RG203 10K_0201_5%
10K_0201_5% 2
DMN53D0LDW-7 2N SOT363-6
2
G
5
2
5
FRAME_LOCK#
2
3 1 1 VCC
4
GSYNC# <38> B 4
D
2 Y FBVDD/Q_EN <32,34,108>
<98> +1.0VS_VGA_PGOOD A
G
1
QV4
3
MESS138W-G_SOT323-3 UG27 RG557
74LVC1G32GW_TSSOP5 10K_0201_1%
2
BIOS_STRAP
3 +1V8_AON 3
+1V8_AON
RG78
2
2
UG1U
14/22 MISC 2
RG78 RG79 RG80 RG81 RG82 RG83 RG84 RG85 RG86
@ ROM_CS#
100K_0201_1% 100K_0201_1% 100K_0201_1% 100K_0201_1% 100K_0201_1% 100K_0201_1% BJ4 100K_0201_1% 100K_0201_1% 100K_0201_1%
ROM_CS
100K_0201_1% @ @ @ ROM_SI @ @ @
1
VRAM_M@ ROM_SI
BK2 ROM_SO
SD041100380 ROM_SO
BK4 ROM_SCLK_R ROM_SCLK
STRAP0 BL3 BK3 RG32 1 EMI@ 2 33_0201_5%
STRAP0 ROM_SCLK
STRAP1 BL4 STRAP1
RG90 STRAP2 BM4 STRAP2 1
STRAP3 BM5 STRAP3
2
STRAP4 BK5 STRAP4 CG895

STRAP5 BJ5 STRAP5 220P_0201_50V7K RG88
@EMI@ 2 RG87 RG89
100K_0201_1% 10K_0201_1% 100K_0201_1%
2
100K_0201_1% GPU_BUFRST# @
1
VRAM_S@ BUFRST
BF9 T6
SD041100380 RG90 RG91 RG92 RG93 RG94 RG95 PAD~D
@ 100K_0201_1% 100K_0201_1% 100K_0201_1% @ 100K_0201_1% 100K_0201_1% 100K_0201_1%
@
1
STRAP3_PCH Discrete/MSHybrid STRAP5_PCH GPU DID

Strap to PCH L Without display head L NON-GSYNC
H With display head H GSYNC GSYNC VBIOS ROM
1 2 STRAP3 1 2 STRAP5
<14> STRAP3_PCH <14> STRAP5_PCH
@ +1V8_AON
DG8 DG9 +1V8_AON
RB751S40T1G_SOD523-2 RB751S-40_SOD523-2
1
RG74 1
GPU have display out then set to PCI class code = 0x300h; 10K_0201_5%
STRAP5 CG66
Discrete/MSHybrid with display head. 0.1U_0201_16V6K
2
GPU didn’ t have any di s pl ay out t hen set PCI cl ass code = 2
0x302h. Pure Optimus W/O display head. ROM_CS# DGUP_ROM_CS#_R UG34
ROM_SO RG75 1 2 33_0201_5% DGPU_ROM_SO_R 1 8
GDDR6 VRAM Strap0 Strap1 Strap2 Strap3 RAMCFG
RG76 1 2 0_0201_5% 2 CS# VCC 7
DO(IO1) HOLD#(IO3) DGPU_ROM_SCLK ROM_SCLK
3 6 DGPU_ROM_SI RG100 1 2 0_0201_5% ROM_SI Samsung , K4Z80325BC-HC14 L L L H 0X0
1 2 4 WP#(IO2) CLK 5 RG77 1 2 33_0201_5%
GND DI(IO0)
Micron , MT61K256M32JE-14:A H L L H 0X1
RG1495 W25Q80EWSSIG_SO8
2.2K_0201_1%
SA00009QP00
1
D
QG516 2
GPU_STRAP5_EC <58>
L2N7002WT1G_SC-70-3 G
S
3
4 4

NV(4/6) GPIO_BIOS_STRAP
Si ze Document Number Rev
Dat e: Tuesday, September 24, 2019 Sheet 30 of 115
A B C D E
A B C D E
UG1D UG1E
UG1B UG1C
4/22 FBC 5/22 FBD
1 2/22 FBA 3/22 FBB 1
C6 FBC_D0 FBC_CMD0 C11 FB_C_CMD1 AK8 FBD_D0 FBD_CMD0 AD2 FB_D_CMD1
U51 Y51 FB_A_CMD1 H32 B35 <36> FB_C_D0 D6 B11 FB_C_CMD0 <36> <36> FB_D_D0 AK4 AD1 FB_D_CMD0 <36>
<35> FB_A_D0 FBA_D0 FBA_CMD0 FB_A_CMD0 <35> <35> FB_B_D0 FBB_D0 FBB_CMD0 FB_B_CMD1 FB_B_CMD0 <35> <36> FB_C_D1 FBC_D1 FBC_CMD1 FB_C_CMD1 <36> <36> FB_D_D1 FBD_D1 FBD_CMD1 FB_D_CMD1 <36>
U48 FBA_D1 FBA_CMD1
Y52 D32 FBB_D1 FBB_CMD1
A35 A6 FBC_D2 FBC_CMD2
A11 AK2 FBD_D2 FBD_CMD2
AD4
<35> FB_A_D1 U50 Y49 FB_A_CMD1 <35> <35> FB_B_D1 A33 D35 FB_B_CMD1 <35> <36> FB_C_D2 B6 D11 FB_C_CMD2 <36> <36> FB_D_D2 AK3 AC1 FB_D_CMD2 <36>
<35> FB_A_D2 FBA_D2 FBA_CMD2 FB_A_CMD2 <35> <35> FB_B_D2 FBB_D2 FBB_CMD2 FB_B_CMD2 <35> <36> FB_C_D3 FBC_D3 FBC_CMD3 FB_C_CMD3 <36> <36> FB_D_D3 FBD_D3 FBD_CMD3 FB_D_CMD3 <36>
U49 FBA_D3 FBA_CMD3
AA52 B32 FBB_D3 FBB_CMD3
A36 B4 FBC_D4 FBC_CMD4
A12 AK5 FBD_D4 FBD_CMD4
AC2
<35> FB_A_D3 R51 AA51 FB_A_CMD3 <35> <35> FB_B_D3 E32 B36 FB_B_CMD3 <35> <36> FB_C_D4 A4 B12 FB_C_CMD4 <36> <36> FB_D_D4 AK6 AC3 FB_D_CMD4 <36>
R50 FBA_D5 FBA_CMD5 AA50 G32 FBB_D5 FBB_CMD5 C36 B3 FBC_D6 FBC_CMD6 C12 AK9 FBD_D6 FBD_CMD6 AA3
<35> FB_A_D5 R47 AC50 FB_A_CMD5 <35> <35> FB_B_D5 J30 C38 FB_B_CMD5 <35> <36> FB_C_D6 C4 C14 FB_C_CMD6 <36> <36> FB_D_D6 AK7 AA2 FB_D_CMD6 <36>
U46 FBA_D7 FBA_CMD7
AC51 F32 FBB_D7 FBB_CMD7
B38 D9 FBC_D8 FBC_CMD8
B14 AG4 FBD_D8 FBD_CMD8
AA1
<35> FB_A_D7 V46 AC52 FB_A_CMD7 <35> <35> FB_B_D7 H36 A38 FB_B_CMD7 <35> <36> FB_C_D8 C9 A14 FB_C_CMD8 <36> <36> FB_D_D8 AF9 AA4 FB_D_CMD8 <36>
Y45 FBA_D9 FBA_CMD9 AC49 G36 FBB_D9 FBB_CMD9 D38 E9 FBC_D10 FBC_CMD10 D14 AG6 FBD_D10 FBD_CMD10 Y1
<35> FB_A_D9 Y47 AD52 FB_A_CMD9 <35> <35> FB_B_D9 J36 A39 FB_B_CMD9 <35> <36> FB_C_D10 B9 A15 FB_C_CMD10 <36> <36> FB_D_D10 AG7 Y2 FB_D_CMD10 <36>
Y46 FBA_D11 FBA_CMD11
AD51 F36 FBB_D11 FBB_CMD11
B39 B8 FBC_D12 FBC_CMD12
B15 FB_C_CMD13 AJ4 FBD_D12 FBD_CMD12
Y3 FB_D_CMD13
<35> FB_A_D11 V50 AD50 FB_A_CMD13 FB_A_CMD11 <35> <35> FB_B_D11 F33 C39 FB_B_CMD11 <35> <36> FB_C_D12 A8 C15 FB_C_CMD12 <36> <36> FB_D_D12 AJ5 V3 FB_D_CMD12 <36>
V47 FBA_D13 FBA_CMD13
AF50 D33 FBB_D13 FBB_CMD13
C41 F6 FBC_D14 FBC_CMD14
C17 AJ6 FBD_D14 FBD_CMD14
V2
<35> FB_A_D13 U52 AF51 FB_A_CMD13 <35> <35> FB_B_D13 J32 B41 FB_B_CMD13 <35> <36> FB_C_D14 E6 B17 FB_C_CMD14 <36> <36> FB_D_D14 AG5 V1 FB_D_CMD14 <36>
V51 FBA_D15 FBA_CMD15
AF52 G33 FBB_D15 FBB_CMD15
A41 F18 FBC_D16 FBC_CMD16
B24 FB_C_CMD17 Y6 FBD_D16 FBD_CMD16
L3 FB_D_CMD17
<35> FB_A_D15 AJ44 AN50 FB_A_CMD17 FB_A_CMD15 <35> <35> FB_B_D15 E45 B49 FB_B_CMD15 <35> <36> FB_C_D16 G18 A24 FB_C_CMD16 <36> <36> FB_D_D16 Y5 L2 FB_D_CMD16 <36>
AG48 FBA_D17 FBA_CMD17
AN51 D45 FBB_D17 FBB_CMD17
A49 E18 FBC_D18 FBC_CMD18
D23 V5 FBD_D18 FBD_CMD18
L1
<35> FB_A_D17 AJ45 AN52 FB_A_CMD17 <35> <35> FB_B_D17 F45 A48 FB_B_CMD17 <35> <36> FB_C_D18 H18 A23 FB_C_CMD18 <36> <36> FB_D_D18 Y4 M4 FB_D_CMD18 <36>
AG49 FBA_D19 FBA_CMD19 AM49 G45 FBB_D19 FBB_CMD19 D47 D15 FBC_D20 FBC_CMD20 B23 AA6 FBD_D20 FBD_CMD20 M1
<35> FB_A_D19 AF46 AM52 FB_A_CMD19 <35> <35> FB_B_D19 D42 A47 FB_B_CMD19 <35> <36> FB_C_D20 E15 C23 FB_C_CMD20 <36> <36> FB_D_D20 AA5 M2 FB_D_CMD20 <36>
AF47 FBA_D21 FBA_CMD21
AM51 E42 FBB_D21 FBB_CMD21
B47 G17 FBC_D22 FBC_CMD22
C21 AC5 FBD_D22 FBD_CMD22
M3
<35> FB_A_D21 AF48 AM50 FB_A_CMD21 <35> <35> FB_B_D21 F42 C47 FB_B_CMD21 <35> <36> FB_C_D22 H17 B21 FB_C_CMD22 <36> <36> FB_D_D22 AC4 P3 FB_D_CMD22 <36>
AD47 FBA_D23 FBA_CMD23
AK50 H41 FBB_D23 FBB_CMD23
C45 J15 FBC_D24 FBC_CMD24
A21 AD7 FBD_D24 FBD_CMD24
P2
<35> FB_A_D23 AD49 AK51 FB_A_CMD23 <35> <35> FB_B_D23 E41 B45 FB_B_CMD23 <35> <36> FB_C_D24 H15 D20 FB_C_CMD24 <36> <36> FB_D_D24 AC6 P1 FB_D_CMD24 <36>
AD48 FBA_D25 FBA_CMD25
AK52 F39 FBB_D25 FBB_CMD25
A45 E14 FBC_D26 FBC_CMD26
A20 AF6 FBD_D26 FBD_CMD26
R4
<35> FB_A_D25 AC46 AJ49 FB_A_CMD25 <35> <35> FB_B_D25 E39 D44 FB_B_CMD25 <35> <36> FB_C_D26 F14 B20 FB_C_CMD26 <36> <36> FB_D_D26 AD6 R1 FB_D_CMD26 <36>
AC47 FBA_D27 FBA_CMD27
AJ52 D39 FBB_D27 FBB_CMD27
A44 H11 FBC_D28 FBC_CMD28
C20 FB_C_CMD29 AF7 FBD_D28 FBD_CMD28
R2 FB_D_CMD29
<35> FB_A_D27 AA47 AJ51 FB_A_CMD29 FB_A_CMD27 <35> <35> FB_B_D27 F38 B44 FB_B_CMD27 <35> <36> FB_C_D28 G11 C18 FB_C_CMD28 <36> <36> FB_D_D28 AF8 R3 FB_D_CMD28 <36>
AA46 FBA_D29 FBA_CMD29 AJ50 E38 FBB_D29 FBB_CMD29 C44 F11 FBC_D30 FBC_CMD30 B18 AF2 FBD_D30 FBD_CMD30 U3
<35> FB_A_D29 AA45 AG50 FB_A_CMD29 <35> <35> FB_B_D29 D36 C42 FB_B_CMD29 <35> <36> FB_C_D30 E11 A18 FB_C_CMD30 <36> <36> FB_D_D30 AF3 U2 FB_D_CMD30 <36>
Y44 FBA_D31 FBA_CMD31 AG51 E36 FBB_D31 FBB_CMD31 B42 J29 FBC_D32 FBC_CMD32 A17 F4 FBD_D32 FBD_CMD32 V4
<35> FB_A_D31 AW51 AF49 FB_A_CMD31 <35> <35> FB_B_D31 M50 D41 FB_B_CMD31 <35> <36> FB_C_D32 F30 D17 FB_C_CMD32 <36> <36> FB_D_D32 E1 U1 FB_D_CMD32 <36>
BA52 FBA_D33 FBA_CMD33
AG52 P48 FBB_D33 FBB_CMD33
A42 H29 FBC_D34 FBC_CMD34
A9 F3 FBD_D34 FBD_CMD34
AD3
<35> FB_A_D33 AW50 Y50 FB_A_CMD33 <35> <35> FB_B_D33 M51 C35 FB_B_CMD33 <35> <36> FB_C_D34 G30 C24 <36> FB_D_D34 F5 J3
<35> FB_A_D34 FBA_D34 FBA_CMD34 <35> FB_B_D34 FBB_D34 FBB_CMD34 <36> FB_C_D35 FBC_D35 FBC_CMD35 <36> FB_D_D35 FBD_D35 FBD_CMD35
BA51 FBA_D35 FBA_CMD35 AR50 M49 FBB_D35 FBB_CMD35 B50 B30 FBC_D36 D2 FBD_D36
<35> FB_A_D35 BA50 <35> FB_B_D35 P47 <36> FB_C_D36 A30 <36> FB_D_D36 D1
<35> FB_A_D36 FBA_D36 <35> FB_B_D36 FBB_D36 <36> FB_C_D37 FBC_D37 <36> FB_D_D37 FBD_D37
BB50 FBA_D37 P52 FBB_D37 H30 FBC_D38 C3 FBD_D38
<35> FB_A_D37 BA49 <35> FB_B_D37 R46 <36> FB_C_D38 C30 J14 <36> FB_D_D38 C2 AC9
<35> FB_A_D38 FBA_D38 <35> FB_B_D38 FBB_D38 <36> FB_C_D39 FBC_D39 FBC_DBG_RFU1 <36> FB_D_D39 FBD_D39 FBD_DBG_RFU1
AW49 FBA_D39 FBA_DBG_RFU1 AA44 P46 FBB_D39 FBB_DBG_RFU1 J35 D27 FBC_D40 FBC_DBG_RFU2 J23 J5 FBD_D40 FBD_DBG_RFU2 P9
<35> FB_A_D39 AV48 AN44 <35> FB_B_D39 L50 J41 <36> FB_C_D40 J26 <36> FB_D_D40 J4
<35> FB_A_D40 FBA_D40 FBA_DBG_RFU2 <35> FB_B_D40 FBB_D40 FBB_DBG_RFU2 <36> FB_C_D41 FBC_D41 <36> FB_D_D41 FBD_D41
AT49 FBA_D41 L51 FBB_D41 F27 FBC_D42 L8 FBD_D42
<35> FB_A_D41 AT47 <35> FB_B_D41 L52 <36> FB_C_D42 G27 <36> FB_D_D42 J2
AT48 FBA_D43
L49 FBB_D43
C27 FBC_D44 FBC_CLK0
G15 F1 FBD_D44 FBD_CLK0
Y8
<35> FB_A_D43 AT46 AG45 <35> FB_B_D43 M46 H42 <36> FB_C_D44 B27 F15 FB_C_CLK0 <36> <36> FB_D_D44 F2 Y7 FB_D_CLK0 <36>
<35> FB_A_D44 FBA_D44 FBA_CLK0 FB_A_CLK0 <35> <35> FB_B_D44 FBB_D44 FBB_CLK0 FB_B_CLK0 <35> <36> FB_C_D45 FBC_D45 FBC_CLK0 FB_C_CLK#0 <36> <36> FB_D_D45 FBD_D45 FBD_CLK0 FB_D_CLK#0 <36>
AV51 FBA_D45 FBA_CLK0 AG46 L47 FBB_D45 FBB_CLK0 G42 A27 FBC_D46 FBC_CLK1 H21 H4 FBD_D46 FBD_CLK1 R8
<35> FB_A_D45 AV52 AK46 FB_A_CLK#0 <35> <35> FB_B_D45 M48 F47 FB_B_CLK#0 <35> <36> FB_C_D46 G29 J21 FB_C_CLK1 <36> <36> FB_D_D46 H5 R7 FB_D_CLK1 <36>
<35> FB_A_D46 FBA_D46 FBA_CLK1 FB_A_CLK1 <35> <35> FB_B_D46 FBB_D46 FBB_CLK1 FB_B_CLK1 <35> <36> FB_C_D47 FBC_D47 FBC_CLK1 FB_C_CLK#1 <36> <36> FB_D_D47 FBD_D47 FBD_CLK1 FB_D_CLK#1 <36>
AV49 FBA_D47 FBA_CLK1 AK45 M47 FBB_D47 FBB_CLK1 E47 H20 FBC_D48 V7 FBD_D48
<35> FB_A_D47 AJ48 FB_A_CLK#1 <35> <35> FB_B_D47 D48 FB_B_CLK#1 <35> <36> FB_C_D48 D18 <36> FB_D_D48 V8
AJ46 FBA_D49 C50 FBB_D49 G20 FBC_D50 V6 FBD_D50
<35> FB_A_D49 AJ47 <35> FB_B_D49 C48 <36> FB_C_D50 E20 <36> FB_D_D50 V9
AK49 FBA_D51 C49 FBB_D51 F23 FBC_D52 U4 FBD_D52
<35> FB_A_D51 AM47 <35> FB_B_D51 E49 <36> FB_C_D52 E21 <36> FB_D_D52 R5
AM46 FBA_D53
E50 FBB_D53
D21 FBC_D54
R6 FBD_D54
<35> FB_A_D53 AN48 <35> FB_B_D53 F49 <36> FB_C_D54 E23 <36> FB_D_D54 U8
AN49 FBA_D55 F48 FBB_D55 G24 FBC_D56 FBC_WCK01 F8 P6 FBD_D56 FBD_WCK01 AJ8
<35> FB_A_D55 AM44 U45 <35> FB_B_D55 F50 J33 <36> FB_C_D56 H26 G8 FB_C_WCK01 <36> <36> FB_D_D56 R9 AJ7 FB_D_WCK01 <36>
<35> FB_A_D56 FBA_D56 FBA_WCK01 FB_A_WCK01 <35> <35> FB_B_D56 FBB_D56 FBB_WCK01 FB_B_WCK01 <35> <36> FB_C_D57 FBC_D57 FBC_WCK01 FB_C_WCK#01 <36> <36> FB_D_D57 FBD_D57 FBD_WCK01 FB_D_WCK#01 <36>
AM45 FBA_D57 FBA_WCK01 U44 D52 FBB_D57 FBB_WCK01 H33 F24 FBC_D58 FBC_WCKB01 G9 P4 FBD_D58 FBD_WCKB01 AG8
<35> FB_A_D57 AN45 V45 FB_A_WCK#01 <35> <35> FB_B_D57 J50 G35 FB_B_WCK#01 <35> <36> FB_C_D58 G26 F9 FB_C_WCKB01 <36> <36> FB_D_D58 P5 AG9 FB_D_WCKB01 <36>
<35> FB_A_D58 FBA_D58 FBA_WCKB01 FB_A_WCKB01 <35> <35> FB_B_D58 FBB_D58 FBB_WCKB01 FB_B_WCKB01 <35> <36> FB_C_D59 FBC_D59 FBC_WCKB01 FB_C_WCKB#01 <36> <36> FB_D_D59 FBD_D59 FBD_WCKB01 FB_D_WCKB#01 <36>
AN46 FBA_D59 FBA_WCKB01 V44 H48 FBB_D59 FBB_WCKB01 H35 F26 FBC_D60 FBC_WCK23 H12 L7 FBD_D60 FBD_WCK23 AD8
<35> FB_A_D59 AR48 AC45 FB_A_WCKB#01 <35> <35> FB_B_D59 H51 J39 FB_B_WCKB#01 <35> <36> FB_C_D60 D26 G12 FB_C_WCK23 <36> <36> FB_D_D60 L6 AD9 FB_D_WCK23 <36>
<35> FB_A_D60 FBA_D60 FBA_WCK23 FB_A_WCK23 <35> <35> FB_B_D60 FBB_D60 FBB_WCK23 FB_B_WCK23 <35> <36> FB_C_D61 FBC_D61 FBC_WCK23 FB_C_WCK#23 <36> <36> FB_D_D61 FBD_D61 FBD_WCK23 FB_D_WCK#23 <36>
AN47 FBA_D61 FBA_WCK23 AC44 J51 FBB_D61 FBB_WCK23 H39 B26 FBC_D62 FBC_WCKB23 G14 L4 FBD_D62 FBD_WCKB23 AC7
<35> FB_A_D61 AR47 AD46 FB_A_WCK#23 <35> <35> FB_B_D61 H49 F41 FB_B_WCK#23 <35> <36> FB_C_D62 C26 H14 FB_C_WCKB23 <36> <36> FB_D_D62 L5 AC8 FB_D_WCKB23 <36>
<35> FB_A_D62 FBA_D62 FBA_WCKB23 FB_A_WCKB23 <35> <35> FB_B_D62 FBB_D62 FBB_WCKB23 FB_B_WCKB23 <35> <36> FB_C_D63 FBC_D63 FBC_WCKB23 FB_C_WCKB#23 <36> <36> FB_D_D63 FBD_D63 FBD_WCKB23 FB_D_WCKB#23 <36>
AR46 FBA_D63 FBA_WCKB23
AD45 H52 FBB_D63 FBB_WCKB23
G41 FBC_WCK45
J27 FBD_WCK45
J6
<35> FB_A_D63 AV47 FB_A_WCKB#23 <35> <35> FB_B_D63 L46 FB_B_WCKB#23 <35> H27 FB_C_WCK45 <36> J7 FB_D_WCK45 <36>
FBA_WCK45 FB_A_WCK45 <35> FBB_WCK45 FB_B_WCK45 <35> FBC_WCK45 FB_C_WCK#45 <36> FBD_WCK45 FB_D_WCK#45 <36>
FBA_WCK45 AV46 FBB_WCK45 L45 A5 FBC_DQM0 FBC_WCKB45 E29 AJ1 FBD_DQM0 FBD_WCKB45 H7
U47 AW48 FB_A_WCK#45 <35> C32 M44 FB_B_WCK#45 <35> <36> FB_C_DBI0 C8 F29 FB_C_WCKB45 <36> <36> FB_D_DBI0 AG1 H6 FB_D_WCKB45 <36>
<35> FB_A_DBI0 FBA_DQM0 FBA_WCKB45 FB_A_WCKB45 <35> <35> FB_B_DBI0 FBB_DQM0 FBB_WCKB45 FB_B_WCKB45 <35> <36> FB_C_DBI1 FBC_DQM1 FBC_WCKB45 FB_C_WCKB#45 <36> <36> FB_D_DBI1 FBD_DQM1 FBD_WCKB45 FB_D_WCKB#45 <36>
Y48 FBA_DQM1 FBA_WCKB45 AW47 E33 FBB_DQM1 FBB_WCKB45 M45 J18 FBC_DQM2 FBC_WCK67 G23 AA7 FBD_DQM2 FBD_WCK67 P8
<35> FB_A_DBI1 AG47 AR45 FB_A_WCKB#45 <35> <35> FB_B_DBI1 E44 H47 FB_B_WCKB#45 <35> <36> FB_C_DBI2 F12 H23 FB_C_WCK67 <36> <36> FB_D_DBI2 AD5 P7 FB_D_WCK67 <36>
<35> FB_A_DBI2 FBA_DQM2 FBA_WCK67 FB_A_WCK67 <35> <35> FB_B_DBI2 FBB_DQM2 FBB_WCK67 FB_B_WCK67 <35> <36> FB_C_DBI3 FBC_DQM3 FBC_WCK67 FB_C_WCK#67 <36> <36> FB_D_DBI3 FBD_DQM3 FBD_WCK67 FB_D_WCK#67 <36>
AC48 FBA_DQM3 FBA_WCK67 AR44 G39 FBB_DQM3 FBB_WCK67 H46 D29 FBC_DQM4 FBC_WCKB67 H24 D3 FBD_DQM4 FBD_WCKB67 M7
<35> FB_A_DBI3 BB51 AT45 FB_A_WCK#67 <35> <35> FB_B_DBI3 P49 J47 FB_B_WCK#67 <35> <36> FB_C_DBI4 E27 J24 FB_C_WCKB67 <36> <36> FB_D_DBI4 H3 M8 FB_D_WCKB67 <36>
<35> FB_A_DBI4 FBA_DQM4 FBA_WCKB67 FB_A_WCKB67 <35> <35> FB_B_DBI4 FBB_DQM4 FBB_WCKB67 FB_B_WCKB67 <35> <36> FB_C_DBI5 FBC_DQM5 FBC_WCKB67 FB_C_WCKB#67 <36> <36> FB_D_DBI5 FBD_DQM5 FBD_WCKB67 FB_D_WCKB#67 <36>
AV50 FBA_DQM5 FBA_WCKB67 AT44 L48 FBB_DQM5 FBB_WCKB67 J46 F20 FBC_DQM6 U5 FBD_DQM6
<35> FB_A_DBI5 AM48 FB_A_WCKB#67 <35> <35> FB_B_DBI5 D50 FB_B_WCKB#67 <35> <36> FB_C_DBI6 E26 <36> FB_D_DBI6 M9
<35> FB_A_DBI6 FBA_DQM6 <35> FB_B_DBI6 FBB_DQM6 <36> FB_C_DBI7 FBC_DQM7 <36> FB_D_DBI7 FBD_DQM7
AR49 FBA_DQM7
H50 FBB_DQM7
<35> FB_A_DBI7 <35> FB_B_DBI7
D5 FBC_DQS_WP0 AJ3 FBD_DQS_WP0
R48 B33 <36> FB_C_EDC0 D8 <36> FB_D_EDC0 AG2
<35> FB_A_EDC0 FBA_DQS_WP0 <35> FB_B_EDC0 FBB_DQS_WP0 <36> FB_C_EDC1 FBC_DQS_WP1 <36> FB_D_EDC1 FBD_DQS_WP1
V48 E35 E17 +FBX_PLLAVDD AA9 +FBX_PLLAVDD
2 AF44 +FBX_PLLAVDD +1V8_MAIN G44 +FBX_PLLAVDD E12 AF4 2
AA48 FBA_DQS_WP3 H38 FBB_DQS_WP3 E30 FBC_DQS_WP4 E3 FBD_DQS_WP4
<35> FB_A_EDC3 BB52 <35> FB_B_EDC3 P50 <36> FB_C_EDC4 B29 <36> FB_D_EDC4 H2
<35> FB_A_EDC4 FBA_DQS_WP4 100MHz <35> FB_B_EDC4 FBB_DQS_WP4 <36> FB_C_EDC5 FBC_DQS_WP5 <36> FB_D_EDC5 FBD_DQS_WP5
AT50 J48 G21 U6
<35> FB_A_EDC5 AK48
FBA_DQS_WP5 30ohm, Bead <35> FB_B_EDC5 D51
FBB_DQS_WP5 <36> FB_C_EDC6 E24
FBC_DQS_WP6
L17 <36> FB_D_EDC6 M5
FBD_DQS_WP6
V11
<35> FB_A_EDC6 FBA_DQS_WP6 <35> FB_B_EDC6 FBB_DQS_WP6 <36> FB_C_EDC7 FBC_DQS_WP7 FBC_PLL_AVDD <36> FB_D_EDC7 FBD_DQS_WP7 FBD_PLL_AVDD
AR51 FBA_DQS_WP7 FBA_PLL_AVDD
AN42 1 2 F51 FBB_DQS_WP7 FBB_PLL_AVDD
L38
22U_0603_6.3V6M
<35> FB_A_EDC7 <35> FB_B_EDC7

4.7U_0402_4V_M
4.7U_0402_4V_M
1U_0201_4VAM
1U_0201_4VAM
LG6 Y24 GND 1 Y32 GND 1
1U_0201_4VAM
1U_0201_4VAM
CG7233
CG7234
W45 GND 1 1 1 1 PBY160808T-300Y-N_2P Y16 GND 1 Y25 GND Y33 GND
CG7231
CG7228
CG7232
W47 GND Y17 GND Y26 GND Y34 GND
CG7229
CG7230
W49 GND
Y18 GND
Y27 GND
Y35 GND
W51 Y19 Y28 2 Y36 2
GND GND GND GND
W6 2 2 2 2 Y20 2 Y29 Y37
GND GND GND GND
W8 GND Y21 GND Y30 GND Y38 GND
Y14 GND Y22 GND Y31 GND Y39 GND
+FBX_PLLAVDD Y15 Y23
GND GND
N18E-G3
AF42
L29
FB_REFPLL_AVDD0 Under GPU Near GPU Under GPU Under GPU N18E-G2 N18E-G1
Under GPU
FB_REFPLL_AVDD1 0710, change CG7233 to 1uF, ref NV HWDG. 0710, change CG7234 to 1uF, ref NV HWDG.
1U_0201_4VAM
1U_0201_4VAM
1 1 0710, change CG7231 to 1uF, ref NV HWDG. 0710, change CG7232 to 1uF, ref NV HWDG. FBD N/A
CG7248
CG7249
@ @
@ @
2 2
Under GPU
0710, change CG7248-CG7249 to 1uF, ref NV HWDG.
+1.35VS_VGA +1.35VS_VGA
10K_0201_1%
10K_0201_1%
10K_0201_1%
10K_0201_1%
1
10K_0201_1%
10K_0201_1%
10K_0201_1%
10K_0201_1%
1
1
RG1479
RG1480
RG1483
RG1484
For CKE_A
RG1487
RG1488
RG1491
RG1492
For CKE_A
2
FB_A_CMD10 FB_B_CMD10
2
FB_C_CMD10 FB_D_CMD10
FB_A_CMD2 FB_B_CMD2
FB_C_CMD2 FB_D_CMD2
10K_0201_1%
10K_0201_1%
10K_0201_1%
10K_0201_1%
2
10K_0201_1%
10K_0201_1%
10K_0201_1%
10K_0201_1%
RG1481
RG1482
RG1486
RG1485
2
RG1490
RG1489
RG1494
RG1493
For Reset For Reset
1
1
3 3
4 4

NV(5/6) MEMORY_FB_ABCD
A B C D E
A B C D E
UG1S
NVLink Interface
11/22 NVHS
NVHS_RX0 AM1
NVHS_RX0 AN1
NVHS_RX1 AN2
UG1R USB-C Display Interface NVHS_RX1 AN3
AR3
6/22 IFPF/USB-C NVHS_RX2
NVHS_RX2 AR2
USB-C DP
1 NVHS_RX3 AR1 1
NVHS_RX3 AT1
USB_DVDD1 BB15
10K_0201_5% 2 1 RG1505 USB_DVDD SBU2 IFPF_AUX BM9
USB_DVDD2 BC15 BM8 +NVHS_DVDD1
USB_DVDD SBU1 IFPF_AUX 10K_0201_5% 2 1 RG1523 AT10 NVHS_DVDD NVHS_RX4 AT2
+NVHS_DVDD2 AT9 AT3
+NVHS_DVDD3 NVHS_DVDD NVHS_RX4
AV10 NVHS_DVDD
BK11 +NVHS_DVDD4 AV11 AV3
RX1 IFPF_L3 NVHS_DVDD NVHS_RX5
RX1 IFPF_L3 BL11 NVHS_RX5 AV2
+NVHS_CVDD1 AR10
+PEX_VDD +NVHS_CVDD2 NVHS_CVDD
TX1 IFPF_L2 BM11 AT11 NVHS_CVDD NVHS_RX6 AV1
TX1 IFPF_L2 BM12 NVHS_RX6 AW1
TX2 IFPF_L1 BL12 NVHS_RX7 AW2

IFPF_L1 BK12 NVHS_RX7 AW3
USB_HVDD1 AW10 TX2
10K_0201_5% 2 1 RG1507 USB_HVDD
USB_HVDD2 AW11 BK14 AM7
USB_HVDD RX2 IFPF_L0 NVHS_TX0
RX2 IFPF_L0 BL14 NVHS_TX0 AM8
AW9 USB_PLL_HVDD
+1V8_AON
NVHS_TX1 AN7
NVHS_TX1 AN6
USB_L0 BA1
BA2 +NVHS_HVDD1
USB_L0 10K_0201_5% 2 1 RG1529 AM10 NVHS_HVDD NVHS_TX2 AR6
+NVHS_HVDD2 AM11 AR5
+NVHS_HVDD3 NVHS_HVDD NVHS_TX2
USB_L1 BA7 AN10 NVHS_HVDD
BA8 +NVHS_HVDD4 AN11 AR7
USB_L1 +NVHS_HVDD5 NVHS_HVDD NVHS_TX3
AR11 NVHS_HVDD NVHS_TX3
AR8
USB_VDDP
10K_0201_5% 2 1 RG1509 BE12 USB_VDDP +NVHS_PLL_HVDD AN9
10K_0201_5% 2 1 RG1534 NVHS_PLL_HVDD NVHS_TX4
AT7
AT6
NVHS_TX4
NVHS_TX5
AV6
AV5
If it’ s no US Bt ype C desi gni n and no I FPF used, t hen NVHS_TX5
USB_VDDP,USB_DVDD and USB_HVDD pull to GND with a AV7
NVHS_TX6
10K resistor. But USB_PLL_HVDD must connect to 1.8V_AON NVHS_TX6
AV8
power rails even no USB/IFPF used.
USB_SCL BB8 NVHS_TX7 AW7
USB_SDA BB7 NVHS_TX7 AW6
BG6 USB_TERMP0
BH6 USB_TERMP1 AM3 NVHS_TERMP NVHS_REFCLK AM6

NVHS_REFCLK AM5
BA6 USB_RBIAS
IFPF/USB-C
EXT_REFCLK_SLI
AM2
@ N18E-G2
N18E-G3 N18E-G1
2 2
NVHS RX/TX N/A
N18E GPU does not support NVLink. Pull down NVHS_DVDD,

NVHS_CVDD, NVHS_HVDD, NVHS_PLL_HVDD rails to GND
with 10K Resistor. Do not use any decoupling or filtering capacitor for NVHS_DVDD, NVHS_CVDD,
NVHS_HVDD,NVHS_PLL_HVDD rails. Leave NVHS_TERMP, EXT_REFCLK_SLI, NVHS_REFCLK, NVHS_TX and NVHS_RX
signals floating (NC)."
Reference board power seq. will handle by PMU

FGC6 Reserved Therefore demo circuit will have other power path to control the
FGC6 or other GPU power seq.
ODM must associate FGC6 power circuit includes power on/off
into its owned circuit.
Note: GC6 3.0 is mandatory for N18x GeForce GPU. GC6 2.1
+1V8_AON +1V8_AON BOM option is recom-mended for N18x GeForce GPU.
3 To 1V8_MAIN 3
+1V8_AON +1V8_MAIN +1V8_AON
1
RG1518 1 @
1
10K_0201_5% CG7085 1 @
@ 0.1U_0201_6.3V6K CG7088 RG1519 1 @
0.1U_0201_6.3V6K 10K_0201_5% CG7091
2
2 @ 0.1U_0201_6.3V6K
RG1510 2
GND VCC
2
5
5
1 0_0201_5% 2
IN B 4 1 2 1V8_MAIN_AON_EN 1
@ VCC
To NVVDD
GND VCC
1V8_MAIN_EN 2 OUT Y B 4 1V8_MAIN_ENP 1
<30,34,37> 1V8_MAIN_EN IN A Y 1V8_MAIN_ENP <37> IN B NVVDD_ENP
1 2 A 4
G 1V8_MAIN_EN 2 OUT Y NVVDD_ENP <30>
UG40 UG39
NL17SZ08DFT2G_SC70-5 CG7089 74LVC1G32GW_TSSOP5 IN A
3
@ 2200P_0201_25V7K @ UG42
2 @ NL17SZ08DFT2G_SC70-5
3
NVVDD_PGOOD 1 2
+1V8_AON 0_0201_5%
RG1602
2/10 change to NVVDD_PGOOD SQE +1V8_AON +1V8_AON
1 @ RB751S40T1G_SOD523-2
CG7087 1 DG10
0.1U_0201_6.3V6K @ CG7092 @ 1
0.1U_0201_6.3V6K 2 1 1203 CHANGE CG7106
5
2
0.1U_0201_6.3V6K
RG1511 2
GND VCC
GPU_GC6_FB_EN
5
5
1 0_0201_5% RG1512 2
<30> GPU_GC6_FB_EN IN B 4 1 2 GPU_GC6_FB_FGC6_EN 1
@ VCC 0_0201_5% RG1521
To PEX_VDD
GND VCC
NB_FGC6 2 OUT Y B 4 1 2 PEX_VDD_RC_ENP 1
Y 0_0201_5%
<30> NB_FGC6 IN A NVVDD_PGOOD 2 IN B 4 1 2 PEX_VDD_ENP
1 <27,30,39,98,102> NVVDD_PGOOD A OUT Y PEX_VDD_ENP <34,98>
UG41 G UG43 2
1 IN A 1
NL17SZ08DFT2G_SC70-5 CG7090 74LVC1G32GW_TSSOP5
3
@ 2200P_0201_25V7K @ CG7094 UG47 CG7107

2 @ 2200P_0201_25V7K NL17SZ08DFT2G_SC70-5 0.22U_0201_10V6K
3
2 2 @
12/18 Update
RG1520
0_0201_5%
DGPU_PWR_EN 1 2 12/03 ADD UG47 , RG1521
<18,37,58> DGPU_PWR_EN
1
+1V8_AON
2/10 ADD 0ohm CG7159
4 2200P_0201_25V7K 4
@ 2 @
1
CG7093
0.1U_0201_6.3V6K
2
5
RG1513
NVVDD_PGOOD 1
B
VCC 0_0201_5% To FBVDD
FBVDD/Q_EN
4 1 @ 2
GPU_GC6_FB_EN Y FBVDD/Q_EN <30,34,108>
2 A
G UG44 1
74LVC1G32GW_TSSOP5
3
@ CG7095
2200P_0201_25V7K
2 @

NV(6/6) USB-C_NVLink_GC6
A B C D E
A
B
C
D
+1.35VS_VGA
+1.35VS_VGA
+1.35VS_VGA
+1.35VS_VGA
+1.35VS_VGA
5
5
2
1
2
1
2
1
2
1
2
1
CG7918 CG7911 CG7894 CG7250
CG7306 1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
22U_0603_6.3V X5R
2
1
CG7307
2
1
2
1
2
1
2
1
22U_0603_6.3V X5R
CG7919 CG7910 CG7895 CG7883
1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
Part i t on C
2
1
Part i t on B
Part i t on A
Part i t on D
CG7308
22U_0603_6.3V X5R
FBVDDQ_GPU
2
1
2
1
2
1
2
1
2
1
CG7309 CG7920 CG7909 CG7896 CG7884

22U_0603_6.3V X5R 1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
2
1
CG7310
22U_0603_6.3V X5R
2
1
2
1
2
1
2
1
CG7921 CG7908 CG7897 CG7885
2
1
CG7311
22U_0603_6.3V X5R
GPU Decoupling - NV Spec Recommendation
Place Close to GPU
2
1
2
1
2
1
2
1
2
1
CG8380
22U_0603_6.3V X5R CG7922 CG7907 CG7898 CG7886
2
1
CG8381
22U_0603_6.3V X5R
Place under GPU

Place under GPU
Place under GPU
Place under GPU
2
1
2
1
2
1
2
1
2
1
CG7923 CG7906 CG7899 CG7887
CG8382 1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
0710, remove 6pcs 1uF, ref NV HWDG.
22U_0603_6.3V X5R

2 1

1
2
1
2
1
2
1
2
CG8383
8 x 10uF (0603)
24 x 1uF (0201)
10U_0603_4VAM CG7298 CG7284 CG7270 CG7256

10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
2 1
CG8384
1
2
1
2
1
2
1
2
4
4
10U_0603_4VAM
9 x 22uF (0603, Near GPU)
4 x 10uF (0603, Near GPU)
CG7299 CG7285 CG7271 CG7257

2 1 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
CG8385
10U_0603_4VAM
2 1
CG8386
10U_0603_4VAM
0710, add 3pcs 22uF and 4pcs 10uF, ref NV HWDG.

+NVVDD
2
1
2
1
2
1
2
1
2
1
2
1
2
1
CG7950 CG7949 CG7930 CG7312

CG7989 CG7979 CG7960 1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM 22U_0603_6.3V X5R
1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
2
1
2
1
2
1
NVVDD_GPU
2
1
2
1
2
1
CG7951 CG7948 CG7931

2
1
CG7988 CG7978 CG7961 1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
3
3
1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM CG7313

22U_0603_6.3V X5R
2
1
2
1
2
1
2
1
2
1
2
1
CG7952 CG7947 CG7932

1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
2
1
2
1
2
1
2
1
CG7314
2
1
2
1
2
1
CG7953 CG7946 CG7933 22U_0603_6.3V X5R

1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
2
1
2
1
2
1
2
1
2
1
2
1
2
1
CG7954 CG7945 CG7934

CG7985 CG7975 CG7964 1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM CG7315
1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM 22U_0603_6.3V X5R
2
1
2
1
2
1
2
1
2
1
2
1
CG7955 CG7944 CG7935

1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
4 x 22uF (0603)
93 x 1uF (0201)
2
1
2
1
2
1
2
1
2
1
2
1
CG7956 CG7943 CG7936

1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
2
1
2
1
2
1
2
1
2
1
2
1
CG7957 CG7942 CG7937

1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
2
1
2
1
2
1
2
1
2
1
2
1
CG7958 CG7941 CG7938

1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
2
1
2
1
2
1
2
1
2
1
2
1
CG7959 CG7940 CG7939

1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
Issued Date
Security Classification
+NVVDD
2
2
2
1
2
1
2
1
2
1
CG8372 CG8011 CG7992 CG8365

NVVDD_GPU
2018/08/07
2
1
2
1
2
1
2
1
CG8373 CG8010 CG7993 CG8364

2
1
2
1
2
1
2
1
CG8374 CG8009 CG7994 CG8363

2
1
2
1
2
1
2
1
CG8375 CG8008 CG7995 CG7991

Compal Secret Data
2
1
2
1
2
1
2
1
Deciphered Date
CG8376 CG8007 CG7996 CG7990

2
1
2
1
2
1
CG8377 CG8006 CG7997

1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
2
1
2
1
2
1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
0710, add 8pcs 1uF, ref NV HWDG.
CG8378 CG8005 CG7998

2019/08/07
1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM

2
1
2
1
2
1
CG8379 CG8004 CG7999

1U_0201_4VAM 1U_0201_4VAM 1U_0201_4VAM
2
1
2
1
CG8003 CG8000
1U_0201_4VAM 1U_0201_4VAM
Size
Title
Date:
2
1
2
1
CG8002 CG8001
1U_0201_4VAM 1U_0201_4VAM
1
1
Document Number
LA-J521P
Tuesday, September 24, 2019
GPU DECOUPLING
Sheet
33
Compal Electronics, Inc.
of
115
Re v
0.2
A
B
C
D
A B C D E
RG1563 G0G1G3Q@ RG1564 G0G1G3Q@
+3VALW +3V3_SYS RG1575

0_0402_5%
1 2
287_0402_1% 287_0402_1%
2
RG1576 SD034287080 SD034287080
RG1609 @ RG1608 0_0402_5%
0_0402_5% 0_0402_5% 1 2 RG1542 CG7115
649_0402_1% 1000P_0402_50V RG1563 G2@ RG1564 G2@
2 1 1 2
1
RG1501 +3V_OC_PWR
1U_0402_25V6K
100_0402_1% 20mil RG1543 CG7116
CG6802
1
CSSP_B+ 2 1 649_0402_1% 1000P_0402_50V
<103> CSSP_B+
2 1 1 2 191_0402_1% 191_0402_1%
1 1
SD034191080 SD034191080
2
UG37 RG1540
75K_0402_1%
27 3 2 1 CSSP_B+
RG62 VCC BS_IN1 6 2 1 CSSP_NVVDD
0_0402_5% VIN1P 2 BS_IN2 11 75K_0402_1%
CSSN_B+ 1 2 VIN1N 1 SH_IN_P1 BS_IN3 14 RG1541
<103> CSSN_B+ CSSP_NVVDD SH_IN_N1 BS_IN4
2 1 VIN2P 5
<103> CSSP_NVVDD 4 SH_IN_P2
RG64 VIN2N @
100_0402_1% SH_IN_P3 12 SH_IN_N2 9 1 2 CG7120
SH_IN_N3 13 SH_IN_P3 GND_FET 0.015U_0402_25V7K
SH_IN_P4 15 SH_IN_N3 0_0402_5% 1 2
SH_IN_N4 16 SH_IN_P4 32 SH_O1 RG1539
RG66 SH_IN_N4 SH_O1 7 SH_O2 SH_O1 RG1563 2 G3P@ 1 174_0402_1%
0_0402_5% ADC_IN_P 20 SH_O2 10
CSSN_NVVDD 1 2 ADC_IN_N 19 DIFF_OUT_P SH_O3 17 SH_O2 RG1564 2 G3P@ 1 174_0402_1%
<103> CSSN_NVVDD DIFF_OUT_N SH_O4
CG7118 RG1560
47P_0402_50V8J 0_0402_5% BS_OK 30 RG1537 1 2
+3V_OC_PWR 1 2 ADC_IN_P_RC 1 2 BS_OK 0_0402_5%
RG1562 8 29 ADC_MUX_SEL 1 2 0.015U_0402_25V7K
10K_0402_5% NC MUX_SEL OC_WARN# <30> CG7121
18
2 1 BS_OK <30> ADC_IN_P 21 NC
<30> ADC_IN_N NC
31 28
RG135 1 2 ADC_IN_N_RC 1 2 NC ENABLE
1K_0402_1% BG_REF_OUT 23
2 1 SKIP 47P_0402_50V8J 0_0402_5% BS_REF 24 BG_REF_OUT 25 SKIP
CG7119 RG1561 CM_REF_IN 22 BS_REF SKIP
RG1570 CM_REF_IN
2K_0201_1% 33 26 MODE_SEL CG7122
GND MODE_SEL
2
1 2 SH_IN_P3 1000P_0402_50V
1 2
RG1571 NCP45492XMNTWG_QFN32_4X4 10K_0402_5%
2K_0201_1% RG1538 RG1566 RG1567
1 2 SH_IN_N3 SA0000CQX00 243K_0402_1% 10K_0402_5%
1
2 1 2 1
RG1572
2K_0201_1% GPU Power OVRM value RG1563 // Raw1 (SH_O1) RG1564 // Raw2 (SH_O2) CG7123
2 1 2 SH_IN_P4 1000P_0402_50V 2
N18E-G0 80W 287 ohm N/A N/A 1 2
RG1573
2K_0201_1% N18E-G1 90W 287 ohm N/A N/A RG1568 RG1569
1 2 SH_IN_N4 BS_REF 365K_0402_1% 681K_0402_1%
N18E-G2 115W 191 ohm N/A N/A 2 1 2 1
RG1565
10K_0402_5% BG_REF_OUT CG7124
2 1 MODE_SEL N18E-G3 MQ 80W 287 ohm N/A N/A
1000P_0402_50V
@ CM_REF_IN 1 2
N18E-G3 MP 200W 169 ohm 174 // 5.9K ohm 174 // 5.9K ohm
UG49
+3V3_SYS G2G3P@
RG1591 1 16
0_0402_5% INDET ADDR0
R value Control Address Data 1 2 2 15
RESET ADDR1
5.9K ohm 0010 0000 01101001 3 14
GND SDI EC_SMB_DA2 <16,30,58,64,74,77,102>
+3V3_SYS
SH_O1 4 13
+NVVDD +1V8_AON Raw1 2.35K ohm 0010 0000 11000100 A1 SCLK EC_SMB_CK2 <16,30,58,64,74,77,102>
10mil 1.85K ohm 0010 0000 11010001 5 12
10mil W1 VLOGIC
0.1U_0201_6.3V6K
10U_0603_6.3V6M
1
5.9K ohm 0010 0001 01101001 6 11
B1 VDD
1
RG510 +3V3_SYS
1 1
+5VALW RG544 +5VALW 10_0402_1% 2.35K ohm 0010 0001 11000100 7 10
Raw2
G2G3P@
G2G3P@
CG8371
CG8370
0.1U_0201_6.3V6K
VSS B2
10U_0603_6.3V6M
10K_0201_5%
SH_O2 8 9
@ 1.85K ohm 0010 0001 11010001
G2G3P@
1 1
2
A2 W2 2 2
G2G3P@
CG8369
CG8368
2
1
RG543 RG509
2 2
10K_0201_5% 10K_0402_5% AD5142ABRUZ10-RL7_TSSOP16

SA0000CX900
3
3 3
2
G2G3P@
QG508B
QG503B
5 5
4
4
6
6
QG508A
QG503A
2 1V8_AON_EN 2
<30,98,102> NVVDD_EN <37> 1V8_AON_EN
1
+1V8_MAIN +3V3_SYS
10mil
10mil
1
+PEX_VDD +5VALW RG512 +5VALW RG514
+1.35VS_VGA 51_0201_5% 10_0402_1%
10mil 10mil
2
1
1
1
RG511 RG513
+5VALW +5VALW
RG1605 RG1607 10K_0402_5% 10K_0402_5%
10_0201_1% 3_0402_5%
3
2
2
QG520B
QG505B
2
2
1
RG1604 RG1606 5 5
10K_0201_5% 10K_0201_5%
4
4
3
3
2
6
QG522B
QG523B
QG520A
QG505A
4 5 5 4
1V8_MAIN_EN 2 3V3_SYS_EN 2
<30,32,37> 1V8_MAIN_EN <37> 3V3_SYS_EN
4
1
6
6
QG522A
QG523A
2 2
<30,32,108> FBVDD/Q_EN <32,98> PEX_VDD_ENP
1

OC, Discharging
A B C D E
A B C D E
@
UG11
@
UG12
C2 B4 @ @
<31> FB_A_EDC0 C13 EDC0_A DQ0_A A3 FB_A_D7 <31>
UG13 UG14
<31> FB_A_EDC1 T2 EDC1_A DQ1_A B3 FB_A_D5 <31> C2 B4
<31> FB_A_EDC3 T13 EDC0_B DQ2_A B2 FB_A_D6 <31> <31> FB_A_EDC4 C13 EDC0_A DQ0_A A3 FB_A_D36 <31>
<31> FB_A_EDC2 EDC1_B DQ3_A E3 FB_A_D4 <31> <31> FB_A_EDC5 T2 EDC1_A DQ1_A B3 FB_A_D37 <31> C2 B4 C2 B4
DQ4_A E2 FB_A_D2 <31> <31> FB_A_EDC7 T13 EDC0_B DQ2_A B2 FB_A_D38 <31> <31> FB_B_EDC0 C13 EDC0_A DQ0_A A3 FB_B_D0 <31> <31> FB_B_EDC4 C13 EDC0_A DQ0_A A3 FB_B_D36 <31>
D2 DQ5_A F2 FB_A_D0 <31> <31> FB_A_EDC6 EDC1_B DQ3_A E3 FB_A_D39 <31> <31> FB_B_EDC1 T2 EDC1_A DQ1_A B3 FB_B_D6 <31> <31> FB_B_EDC5 T2 EDC1_A DQ1_A B3 FB_B_D37 <31>
1 <31> FB_A_DBI0 D13 DBI0#_A DQ6_A G2 FB_A_D3 <31> DQ4_A E2 FB_A_D35 <31> <31> FB_B_EDC3 T13 EDC0_B DQ2_A B2 FB_B_D2 <31> <31> FB_B_EDC7 T13 EDC0_B DQ2_A B2 FB_B_D33 <31> 1
<31> FB_A_DBI1 R2 DBI1#_A DQ7_A B11 FB_A_D1 <31> D2 DQ5_A F2 FB_A_D33 <31> <31> FB_B_EDC2 EDC1_B DQ3_A E3 FB_B_D3 <31> <31> FB_B_EDC6 EDC1_B DQ3_A E3 FB_B_D38 <31>
<31> FB_A_DBI3 R13 DBI0#_B DQ8_A A12 FB_A_D12 <31> <31> FB_A_DBI4 D13 DBI0#_A DQ6_A G2 FB_A_D34 <31> DQ4_A E2 FB_B_D4 <31> DQ4_A E2 FB_B_D39 <31>
<31> FB_A_DBI2 DBI1#_B DQ9_A B12 FB_A_D14 <31> <31> FB_A_DBI5 R2 DBI1#_A DQ7_A B11 FB_A_D32 <31> D2 DQ5_A F2 FB_B_D1 <31> D2 DQ5_A F2 FB_B_D34 <31>
DQ10_A B13 FB_A_D13 <31> <31> FB_A_DBI7 R13 DBI0#_B DQ8_A A12 FB_A_D44 <31> <31> FB_B_DBI0 D13 DBI0#_A DQ6_A G2 FB_B_D7 <31> <31> FB_B_DBI4 D13 DBI0#_A DQ6_A G2 FB_B_D32 <31>
J10 DQ11_A E12 FB_A_D15 <31> <31> FB_A_DBI6 DBI1#_B DQ9_A B12 FB_A_D41 <31> <31> FB_B_DBI1 R2 DBI1#_A DQ7_A B11 FB_B_D5 <31> <31> FB_B_DBI5 R2 DBI1#_A DQ7_A B11 FB_B_D35 <31>
<31> FB_A_CLK0 K10 CK_T DQ12_A E13 FB_A_D8 <31> DQ10_A B13 FB_A_D42 <31> <31> FB_B_DBI3 R13 DBI0#_B DQ8_A A12 FB_B_D12 <31> <31> FB_B_DBI7 R13 DBI0#_B DQ8_A A12 FB_B_D42 <31>
<31> FB_A_CLK#0 G10 CK_C DQ13_A F13 FB_A_D10 <31> J10 DQ11_A E12 FB_A_D43 <31> <31> FB_B_DBI2 DBI1#_B DQ9_A B12 FB_B_D13 <31> <31> FB_B_DBI6 DBI1#_B DQ9_A B12 FB_B_D43 <31>
<31> FB_A_CMD10 M10 CKE#_A DQ14_A G13 FB_A_D11 <31> <31> FB_A_CLK1 K10 CK_T DQ12_A E13 FB_A_D40 <31> DQ10_A B13 FB_B_D15 <31> DQ10_A B13 FB_B_D40 <31>
CKE#_B DQ15_A FB_A_D9 <31> <31> FB_A_CLK#1 G10 CK_C DQ13_A F13 FB_A_D46 <31> J10 DQ11_A E12 FB_B_D14 <31> J10 DQ11_A E12 FB_B_D45 <31>
U4 <31> FB_A_CMD26 M10 CKE#_A DQ14_A G13 FB_A_D45 <31> <31> FB_B_CLK0 K10 CK_T DQ12_A E13 FB_B_D11 <31> <31> FB_B_CLK1 K10 CK_T DQ12_A E13 FB_B_D41 <31>
DQ0_B V3 FB_A_D30 <31> CKE#_B DQ15_A FB_A_D47 <31> <31> FB_B_CLK#0 G10 CK_C DQ13_A F13 FB_B_D9 <31> <31> FB_B_CLK#1 G10 CK_C DQ13_A F13 FB_B_D46 <31>
DQ1_B U3 FB_A_D29 <31> U4 <31> FB_B_CMD10 M10 CKE#_A DQ14_A G13 FB_B_D8 <31> <31> FB_B_CMD26 M10 CKE#_A DQ14_A G13 FB_B_D47 <31>
J5 DQ2_B U2 FB_A_D28 <31> DQ0_B V3 FB_A_D59 <31> CKE#_B DQ15_A FB_B_D10 <31> CKE#_B DQ15_A FB_B_D44 <31>
<31> FB_A_CMD6 K5 CABI#_A DQ3_B P3 FB_A_D31 <31> DQ1_B U3 FB_A_D56 <31> U4 U4
CABI#_B DQ4_B P2 FB_A_D26 <31> J5 DQ2_B U2 FB_A_D58 <31> DQ0_B V3 FB_B_D29 <31> DQ0_B V3 FB_B_D57 <31>
DQ5_B N2 FB_A_D27 <31> <31> FB_A_CMD22 K5 CABI#_A DQ3_B P3 FB_A_D57 <31> DQ1_B U3 FB_B_D31 <31> DQ1_B U3 FB_B_D56 <31>
DQ6_B M2 FB_A_D24 <31> CABI#_B DQ4_B P2 FB_A_D61 <31> J5 DQ2_B U2 FB_B_D28 <31> J5 DQ2_B U2 FB_B_D62 <31>
DQ7_B U11 FB_A_D25 <31> DQ5_B N2 FB_A_D60 <31> <31> FB_B_CMD6 K5 CABI#_A DQ3_B P3 FB_B_D30 <31> <31> FB_B_CMD22 K5 CABI#_A DQ3_B P3 FB_B_D59 <31>
DQ8_B V12 FB_A_D19 <31> DQ6_B M2 FB_A_D62 <31> CABI#_B DQ4_B P2 FB_B_D26 <31> CABI#_B DQ4_B P2 FB_B_D60 <31>
2 1 J14 DQ9_B U12 FB_A_D18 <31> DQ7_B U11 FB_A_D63 <31> DQ5_B N2 FB_B_D27 <31> DQ5_B N2 FB_B_D63 <31>
RG101 121_0402_1%
2 1 K14 ZQ_A DQ10_B U13 FB_A_D17 <31> DQ8_B V12 FB_A_D49 <31> DQ6_B M2 FB_B_D25 <31> DQ6_B M2 FB_B_D61 <31>
RG102 121_0402_1%
ZQ_B DQ11_B P12 FB_A_D16 <31> 2 1 J14 DQ9_B U12 FB_A_D48 <31> DQ7_B U11 FB_B_D24 <31> DQ7_B U11 FB_B_D58 <31>
RG573 121_0402_1%
DQ12_B P13 FB_A_D21 <31> 2 1 K14 ZQ_A DQ10_B U13 FB_A_D51 <31> DQ8_B V12 FB_B_D23 <31> DQ8_B V12 FB_B_D52 <31>
RG574 121_0402_1%
DQ13_B N13 FB_A_D22 <31> ZQ_B DQ11_B P12 FB_A_D50 <31> 2 1 J14 DQ9_B U12 FB_B_D21 <31> 2 1 J14 DQ9_B U12 FB_B_D48 <31>
RG103 121_0402_1% RG575 121_0402_1%
DQ14_B M13 FB_A_D20 <31> DQ12_B P13 FB_A_D52 <31> 2 1 K14 ZQ_A DQ10_B U13 FB_B_D20 <31> 2 1 K14 ZQ_A DQ10_B U13 FB_B_D51 <31>
RG104 121_0402_1% RG576 121_0402_1%
DQ15_B FB_A_D23 <31> DQ13_B N13 FB_A_D53 <31> ZQ_B DQ11_B P12 FB_B_D22 <31> ZQ_B DQ11_B P12 FB_B_D50 <31>
DQ14_B M13 FB_A_D55 <31> DQ12_B P13 FB_B_D17 <31> DQ12_B P13 FB_B_D53 <31>
N5 H3 DQ15_B FB_A_D54 <31> DQ13_B N13 FB_B_D16 <31> DQ13_B N13 FB_B_D49 <31>
F10 TCK CA0_A G11 FB_A_CMD0 <31> DQ14_B M13 FB_B_D18 <31> DQ14_B M13 FB_B_D54 <31>
N10 TDI CA1_A G4 FB_A_CMD9 <31> N5 H3 DQ15_B FB_B_D19 <31> DQ15_B FB_B_D55 <31>
F5 TDO CA2_A H12 FB_A_CMD8 <31> F10 TCK CA0_A G11 FB_A_CMD20 <31>
TMS CA3_A FB_A_CMD7 FB_A_CMD32 <31> TDI CA1_A FB_A_CMD28 <31>
H5 FB_A_CMD11 N10 G4 N5 H3 N5 H3
CA4_A H10 FB_A_CMD7 <31> F5 TDO CA2_A H12 FB_A_CMD21 <31> F10 TCK CA0_A G11 FB_B_CMD0 <31> F10 TCK CA0_A G11 FB_B_CMD20 <31>
CA5_A FB_A_CMD15 FB_A_CMD11 <31> TMS CA3_A FB_A_CMD23 FB_A_CMD29 <31> TDI CA1_A FB_B_CMD9 <31> TDI CA1_A FB_B_CMD28 <31>
J12 FB_A_CMD14 H5 FB_A_CMD27 N10 G4 N10 G4
D4 CA6_A J11 FB_A_CMD15 <31> CA4_A H10 FB_A_CMD23 <31> F5 TDO CA2_A H12 FB_B_CMD7 FB_B_CMD8 <31> F5 TDO CA2_A H12 FB_B_CMD23 FB_B_CMD21 <31>
<31> FB_A_WCK01 WCK0_T_A CA7_A FB_A_CMD3 FB_A_CMD14 <31> CA5_A FB_A_CMD30 FB_A_CMD27 <31> TMS CA3_A FB_B_CMD32 <31> TMS CA3_A FB_B_CMD29 <31>
D5 J4 FB_A_CMD1 J12 FB_A_CMD31 H5 FB_B_CMD11 H5 FB_B_CMD27
<31> FB_A_WCK#01 D11 WCK0_C_A CA8_A J3 FB_A_CMD3 <31> D4 CA6_A J11 FB_A_CMD30 <31> CA4_A H10 FB_B_CMD15 FB_B_CMD7 <31> CA4_A H10 FB_B_CMD30 FB_B_CMD23 <31>
<31> FB_A_WCKB01 WCK1_T_A CA9_A FB_A_CMD1 <31> <31> FB_A_WCK45 WCK0_T_A CA7_A FB_A_CMD19 FB_A_CMD31 <31> CA5_A FB_B_CMD11 <31> CA5_A FB_B_CMD27 <31>
D10 D5 J4 FB_A_CMD17 J12 FB_B_CMD14 J12 FB_B_CMD31
<31> FB_A_WCKB#01 WCK1_C_A L3 <31> FB_A_WCK#45 D11 WCK0_C_A CA8_A J3 FB_A_CMD19 <31> D4 CA6_A J11 FB_B_CMD3 FB_B_CMD15 <31> D4 CA6_A J11 FB_B_CMD19 FB_B_CMD30 <31>
CA0_B M11 FB_A_CMD4 <31> <31> FB_A_WCKB45 D10 WCK1_T_A CA9_A FB_A_CMD17 <31> <31> FB_B_WCK01 D5 WCK0_T_A CA7_A J4 FB_B_CMD14 <31> <31> FB_B_WCK45 D5 WCK0_T_A CA7_A J4 FB_B_CMD31 <31>
CA1_B FB_A_CMD12 <31> <31> FB_A_WCKB#45 WCK1_C_A <31> FB_B_WCK#01 WCK0_C_A CA8_A FB_B_CMD1 FB_B_CMD3 <31> <31> FB_B_WCK#45 WCK0_C_A CA8_A FB_B_CMD17 FB_B_CMD19 <31>
R4 M4 L3 D11 J3 D11 J3
<31> FB_A_WCKB23 R5 WCK0_T_B CA2_B L12 FB_A_CMD5 <31> CA0_B M11 FB_A_CMD16 <31> <31> FB_B_WCKB01 D10 WCK1_T_A CA9_A FB_B_CMD1 <31> <31> FB_B_WCKB45 D10 WCK1_T_A CA9_A FB_B_CMD17 <31>
<31> FB_A_WCKB#23 WCK0_C_B CA3_B FB_A_CMD7 FB_A_CMD13 <31> CA1_B FB_A_CMD25 <31> <31> FB_B_WCKB#01 WCK1_C_A <31> FB_B_WCKB#45 WCK1_C_A
R11 L5 FB_A_CMD11 R4 M4 L3 L3
<31> FB_A_WCK23 R10 WCK1_T_B CA4_B L10 <31> FB_A_WCKB67 R5 WCK0_T_B CA2_B L12 FB_A_CMD24 <31> CA0_B M11 FB_B_CMD4 <31> CA0_B M11 FB_B_CMD16 <31>
<31> FB_A_WCK#23 WCK1_C_B CA5_B FB_A_CMD15 <31> FB_A_WCKB#67 WCK0_C_B CA3_B FB_A_CMD23 FB_A_CMD33 <31> CA1_B FB_B_CMD12 <31> CA1_B FB_B_CMD25 <31>
K12 FB_A_CMD14 R11 L5 FB_A_CMD27 R4 M4 R4 M4
CA6_B K11 <31> FB_A_WCK67 R10 WCK1_T_B CA4_B L10 <31> FB_B_WCKB23 R5 WCK0_T_B CA2_B L12 FB_B_CMD7 FB_B_CMD5 <31> <31> FB_B_WCKB67 R5 WCK0_T_B CA2_B L12 FB_B_CMD23 FB_B_CMD24 <31>
CA7_B FB_A_CMD3 <31> FB_A_WCK#67 WCK1_C_B CA5_B FB_A_CMD30 <31> FB_B_WCKB#23 WCK0_C_B CA3_B FB_B_CMD13 <31> <31> FB_B_WCKB#67 WCK0_C_B CA3_B FB_B_CMD33 <31>
K4 FB_A_CMD1 K12 FB_A_CMD31 R11 L5 FB_B_CMD11 R11 L5 FB_B_CMD27
CA8_B K3 CA6_B K11 <31> FB_B_WCK23 R10 WCK1_T_B CA4_B L10 FB_B_CMD15 <31> FB_B_WCK67 R10 WCK1_T_B CA4_B L10 FB_B_CMD30
+FBA_VREFC CA9_B CA7_B FB_A_CMD19 <31> FB_B_WCK#23 WCK1_C_B CA5_B <31> FB_B_WCK#67 WCK1_C_B CA5_B
K1 +1.35VS_VGA K4 K12 FB_B_CMD14 K12 FB_B_CMD31
VREFC CA8_B FB_A_CMD17 CA6_B CA6_B
+FBA_VREFC K3 K11 FB_B_CMD3 K11 FB_B_CMD19
C1 K1 CA9_B +1.35VS_VGA CA7_B K4 FB_B_CMD1 CA7_B K4 FB_B_CMD17
J1 VDDQ1 E1 VREFC CA8_B K3 CA8_B K3
<31> FB_A_CMD2 RESET# VDDQ2 +FBB_VREFC CA9_B +FBB_VREFC CA9_B
H1 C1 K1 +1.35VS_VGA K1 +1.35VS_VGA
VDDQ3 L1 J1 VDDQ1 E1 VREFC VREFC
B1 VDDQ4 P1 <31> FB_A_CMD18 RESET# VDDQ2 H1 C1 C1
D1 VSS1 VDDQ5 T1 VDDQ3 L1 J1 VDDQ1 E1 J1 VDDQ1 E1
F1 VSS2 VDDQ6 J2 B1 VDDQ4 P1 <31> FB_B_CMD2 RESET# VDDQ2 H1 <31> FB_B_CMD18 RESET# VDDQ2 H1
G1 VSS3 VDDQ7 K2 D1 VSS1 VDDQ5 T1 VDDQ3 L1 VDDQ3 L1
M1 VSS4 VDDQ8 C4 F1 VSS2 VDDQ6 J2 B1 VDDQ4 P1 B1 VDDQ4 P1
N1 VSS5 VDDQ9 F4 G1 VSS3 VDDQ7 K2 D1 VSS1 VDDQ5 T1 D1 VSS1 VDDQ5 T1
R1 VSS6 VDDQ10 N4 M1 VSS4 VDDQ8 C4 F1 VSS2 VDDQ6 J2 F1 VSS2 VDDQ6 J2
U1 VSS7 VDDQ11 T4 N1 VSS5 VDDQ9 F4 G1 VSS3 VDDQ7 K2 G1 VSS3 VDDQ7 K2
A2 VSS8 VDDQ12 B5 R1 VSS6 VDDQ10 N4 M1 VSS4 VDDQ8 C4 M1 VSS4 VDDQ8 C4
V2 VSS9 VDDQ13 U5 U1 VSS7 VDDQ11 T4 N1 VSS5 VDDQ9 F4 N1 VSS5 VDDQ9 F4
C3 VSS10 VDDQ14 B10 A2 VSS8 VDDQ12 B5 R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4
D3 VSS11 VDDQ15 U10 V2 VSS9 VDDQ13 U5 U1 VSS7 VDDQ11 T4 U1 VSS7 VDDQ11 T4
F3 VSS12 VDDQ16 C11 C3 VSS10 VDDQ14 B10 A2 VSS8 VDDQ12 B5 A2 VSS8 VDDQ12 B5
G3 VSS13 VDDQ17 F11 D3 VSS11 VDDQ15 U10 V2 VSS9 VDDQ13 U5 V2 VSS9 VDDQ13 U5
M3 VSS14 VDDQ18 N11 F3 VSS12 VDDQ16 C11 C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
N3 VSS15 VDDQ19 T11 G3 VSS13 VDDQ17 F11 D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10
R3 VSS16 VDDQ20 J13 M3 VSS14 VDDQ18 N11 F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
T3 VSS17 VDDQ21 K13 N3 VSS15 VDDQ19 T11 G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
A4 VSS18 VDDQ22 C14 R3 VSS16 VDDQ20 J13 M3 VSS14 VDDQ18 N11 M3 VSS14 VDDQ18 N11
E4 VSS19 VDDQ23 E14 T3 VSS17 VDDQ21 K13 N3 VSS15 VDDQ19 T11 N3 VSS15 VDDQ19 T11
H4 VSS20 VDDQ24 H14 A4 VSS18 VDDQ22 C14 R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13
L4 VSS21 VDDQ25 L14 E4 VSS19 VDDQ23 E14 T3 VSS17 VDDQ21 K13 T3 VSS17 VDDQ21 K13
P4 VSS22 VDDQ26 P14 H4 VSS20 VDDQ24 H14 A4 VSS18 VDDQ22 C14 A4 VSS18 VDDQ22 C14
V4 VSS23 VDDQ27 T14 L4 VSS21 VDDQ25 L14 E4 VSS19 VDDQ23 E14 E4 VSS19 VDDQ23 E14
C5 VSS24 VDDQ28 +1.35VS_VGA P4 VSS22 VDDQ26 P14 H4 VSS20 VDDQ24 H14 H4 VSS20 VDDQ24 H14
2 T5 VSS25 V4 VSS23 VDDQ27 T14 L4 VSS21 VDDQ25 L14 L4 VSS21 VDDQ25 L14 2
C10 VSS26 A1 C5 VSS24 VDDQ28 +1.35VS_VGA P4 VSS22 VDDQ26 P14 P4 VSS22 VDDQ26 P14
T10 VSS27 VDD1 V1 T5 VSS25 V4 VSS23 VDDQ27 T14 V4 VSS23 VDDQ27 T14
A11 VSS28 VDD2 H2 C10 VSS26 A1 C5 VSS24 VDDQ28 +1.35VS_VGA C5 VSS24 VDDQ28 +1.35VS_VGA
E11 VSS29 VDD3 L2 T10 VSS27 VDD1 V1 T5 VSS25 T5 VSS25
H11 VSS30 VDD4 E5 A11 VSS28 VDD2 H2 C10 VSS26 A1 C10 VSS26 A1
L11 VSS31 VDD5 P5 E11 VSS29 VDD3 L2 T10 VSS27 VDD1 V1 T10 VSS27 VDD1 V1
P11 VSS32 VDD6 E10 H11 VSS30 VDD4 E5 A11 VSS28 VDD2 H2 A11 VSS28 VDD2 H2
V11 VSS33 VDD7 P10 L11 VSS31 VDD5 P5 E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2
C12 VSS34 VDD8 H13 P11 VSS32 VDD6 E10 H11 VSS30 VDD4 E5 H11 VSS30 VDD4 E5
D12 VSS35 VDD9 L13 V11 VSS33 VDD7 P10 L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5
F12 VSS36 VDD10 A14 C12 VSS34 VDD8 H13 P11 VSS32 VDD6 E10 P11 VSS32 VDD6 E10
G12 VSS37 VDD11 V14 D12 VSS35 VDD9 L13 V11 VSS33 VDD7 P10 V11 VSS33 VDD7 P10
M12 VSS38 VDD12 +1V8_AON F12 VSS36 VDD10 A14 C12 VSS34 VDD8 H13 C12 VSS34 VDD8 H13
N12 VSS39 G12 VSS37 VDD11 V14 D12 VSS35 VDD9 L13 D12 VSS35 VDD9 L13
R12 VSS40 A5 M12 VSS38 VDD12 +1V8_AON F12 VSS36 VDD10 A14 F12 VSS36 VDD10 A14
T12 VSS41 VPP1 V5 N12 VSS39 G12 VSS37 VDD11 V14 G12 VSS37 VDD11 V14
A13 VSS42 VPP2 A10 R12 VSS40 A5 M12 VSS38 VDD12 +1V8_AON M12 VSS38 VDD12 +1V8_AON
V13 VSS43 VPP3 V10 T12 VSS41 VPP1 V5 N12 VSS39 N12 VSS39
B14 VSS44 VPP4 A13 VSS42 VPP2 A10 R12 VSS40 A5 R12 VSS40 A5
D14 VSS45 V13 VSS43 VPP3 V10 T12 VSS41 VPP1 V5 T12 VSS41 VPP1 V5
F14 VSS46 G5 B14 VSS44 VPP4 A13 VSS42 VPP2 A10 A13 VSS42 VPP2 A10
G14 VSS47 NC1 M5 D14 VSS45 V13 VSS43 VPP3 V10 V13 VSS43 VPP3 V10
M14 VSS48 NC2 F14 VSS46 G5 B14 VSS44 VPP4 B14 VSS44 VPP4
N14 VSS49 G14 VSS47 NC1 M5 D14 VSS45 D14 VSS45
R14 VSS50 M14 VSS48 NC2 F14 VSS46 G5 F14 VSS46 G5
U14 VSS51 N14 VSS49 G14 VSS47 NC1 M5 G14 VSS47 NC1 M5
180-B A LL
VSS52 SGRAM GDDR6 R14 VSS50 M14 VSS48 NC2 M14 VSS48 NC2
U14 VSS51 N14 VSS49 N14 VSS49
180-B A LL
VSS52 SGRAM GDDR6 R14 VSS50 R14 VSS50
MT61K256M32JE-13-A_FBGA180~D U14 VSS51 U14 VSS51
180-B A LL 180-B A LL
VSS52 SGRAM GDDR6 VSS52 SGRAM GDDR6
MT61K256M32JE-13-A_FBGA180~D
MT61K256M32JE-13-A_FBGA180~D MT61K256M32JE-13-A_FBGA180~D
UG11 UG12 UG13 UG14 UG15 UG16 UG17 UG18

UG11 UG12 UG13 UG14 UG15 UG16
GDDR6 CMD Mapping x16 Mode D6 256M32 MT61K256M32JE-14:A 1.2V D6 256M32 MT61K256M32JE-14:A 1.2V D6 256M32 MT61K256M32JE-14:A 1.2V D6 256M32 MT61K256M32JE-14:A 1.2V D6 256M32 MT61K256M32JE-14:A 1.2V D6 256M32 MT61K256M32JE-14:A 1.2V D6 256M32 MT61K256M32JE-14:A 1.2V D6 256M32 MT61K256M32JE-14:A 1.2V GDDR6 CMD Mapping x16 Mode
Lower 0..31 Upper 32..63 D6 256M32 MT61K256M32JE-14:A D6 256M32 MT61K256M32JE-14:A D6 256M32 MT61K256M32JE-14:A D6 256M32 MT61K256M32JE-14:A D6 256M32 MT61K256M32JE-14:A D6 256M32 MT61K256M32JE-14:A MCNGD8A@ MCNGD8A@ MCNGD8A@ MCNGD8A@ MCNGD8A@ MCNGD8A@ MCNGD8A@ MCNGD8A@ Lower 0..31 Upper 32..63
DRAM1 DRAM2 MCNGD6A@ MCNGD6A@ MCNGD6A@ MCNGD6A@ MCNGD6A@ MCNGD6A@ SA0000BND6L SA0000BND6L SA0000BND6L SA0000BND6L SA0000BND6L SA0000BND6L SA0000BND6L SA0000BND6L DRAM1 DRAM2
CHA-Byte 0,1 CHA-Byte 4,5 SA0000BND0L SA0000BND0L SA0000BND0L SA0000BND0L SA0000BND0L SA0000BND0L CHA-Byte 0,1 CHA-Byte 4,5
UG11 UG12 UG13 UG14 UG15 UG16 UG17 UG18
CA0_A CMD 0 CMD20 UG11 UG12 UG13 UG14 UG15 UG16 CA0_A CMD 0 CMD20
CA1_A CMD 9 CMD28 CA1_A CMD 9 CMD28
CA3_A CMD32 CMD29 CA3_A CMD32 CMD29
CA5_A CMD 11 CMD27 D6 256M32 K4Z80325BC-HC14 FBGA 1.2V D6 256M32 K4Z80325BC-HC14 FBGA 1.2V D6 256M32 K4Z80325BC-HC14 FBGA 1.2V D6 256M32 K4Z80325BC-HC14 FBGA 1.2V D6 256M32 K4Z80325BC-HC14 FBGA 1.2V D6 256M32 K4Z80325BC-HC14 FBGA 1.2V D6 256M32 K4Z80325BC-HC14 FBGA 1.2V D6 256M32 K4Z80325BC-HC14 FBGA 1.2V CA5_A CMD 11 CMD27
CA6_A CMD15 CMD30 D6 256M32 K4Z80325BC-HC14 FBGA D6 256M32 K4Z80325BC-HC14 FBGA D6 256M32 K4Z80325BC-HC14 FBGA D6 256M32 K4Z80325BC-HC14 FBGA D6 256M32 K4Z80325BC-HC14 FBGA D6 256M32 K4Z80325BC-HC14 FBGA SAMGD8A@ SAMGD8A@ SAMGD8A@ SAMGD8A@ SAMGD8A@ SAMGD8A@ SAMGD8A@ SAMGD8A@ CA6_A CMD15 CMD30
CA7_A CMD14 CMD31 SAMGD6A@ SAMGD6A@ SAMGD6A@ SAMGD6A@ SAMGD6A@ SAMGD6A@ SA0000C625L SA0000C625L SA0000C625L SA0000C625L SA0000C625L SA0000C625L SA0000C625L SA0000C625L CA7_A CMD14 CMD31
CA8_A CMD 3 CMD19 SA0000C620L SA0000C620L SA0000C620L SA0000C620L SA0000C620L SA0000C620L CA8_A CMD 3 CMD19
CABI_A CMD 6 CMD22 CABI_A CMD 6 CMD22
CKE_A CMD10 CMD26
VRAM 6G VRAM 8G CKE_A CMD10 CMD26
CHB-Byte 2,3 CHB-Byte 6,7 CHB-Byte 2,3 CHB-Byte 6,7

CA0_B CMD 4 CMD16 CA0_B CMD 4 CMD16
CA1_B CMD12 CMD25 CA1_B CMD12 CMD25
CA6_B CMD15 CMD30
+1.35VS_VGA CA6_B CMD15 CMD30
CA7_B CMD14 CMD31
+1.35VS_VGA CA7_B CMD14 CMD31
1
1
CABI_B CMD 6 CMD22 RG121 CABI_B CMD 6 CMD22

CKE_B CMD10 CMD26 RG110 549_0402_1% CKE_B CMD10 CMD26
549_0402_1% @
3 RESET * CMD 2 CMD18 @ RESET * CMD 2 CMD18
3
2
W=16mils +FBB_VREFC
W=16mils
2
+FBA_VREFC 1 2
1 2
820P_0402_25V7
1K_0402_1%
1
RG123
CG571
RG122 1
820P_0402_25V7
1K_0402_1%
1
RG112
CG78
RG111 1 931_0402_1%
931_0402_1% @ @
1
@ D
@ MEM_VREF_CTL
1
D 2 QG3 2
2
2 QG2 2 G MESS138W-G_SOT323-3
<30,36> MEM_VREF_CTL
2
G MESS138W-G_SOT323-3 S @
3
S @
3
UG11 UG12 UG13

Close to DRAM UG11 +1.35VS_VGA +1V8_AON
Close to DRAM UG14 +1.35VS_VGA
UG14 +1V8_AON
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
4.7U_0402_4V_M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
4.7U_0402_4V_M
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
4.7U_0402_4V_M
2 2 2 2 1 1 1 1 1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
4.7U_0402_4V_M
2 2 2 2 1 1 1 1 1 2 2 2 2 1 1 1 1 1
CG7487
CG7488
CG7479
CG7485
CG8095
CG8096
CG8097
CG8098
CG8405
2 2 2 2 1 1 1 1 1
CG7398
CG7399
CG7400
CG7401
CG8404
CG8015
CG8016
CG8017
CG8018
CG7599
CG7600
CG7597
CG7596
CG8183
CG8184
CG8185
CG8186
CG8407
CG7543
CG7541
CG7540
CG7539
CG8103
CG8104
CG8105
CG8106
CG8406
1 1 1 1 2 2 2 2 2
1 1 1 1 2 2 2 2 2 1 1 1 1 2 2 2 2 2
1 1 1 1 2 2 2 2 2

0710, add CG8404 4.7uF, ref NV HWDG. 0726, change CG8095-CG8098 to 1uF, ref NV HWDG.
0710, remove CG7402-CG7403, 0726, change CG8015-CG8018 to 1uF, ref NV HWDG. 0710, remove CG7484, CG7482, 0710, add CG8406 4.7uF, ref NV HWDG. 0710, remove CG7592, CG7595, 0710, add CG8407 4.7uF, ref NV HWDG.
and CG7404, CG8012-CG8014 ref NV HWDG. and CG8091-CG8094 ref NV HWDG. 0710, remove CG7536, CG7544, 0726, change CG8103-CG8106 to 1uF, ref NV HWDG. and CG8179-CG8182 ref NV HWDG. 0726, change CG8183-CG8186 to 1uF, ref NV HWDG.
and CG8099-CG8102 ref NV HWDG.
Around DRAM Right under DRAM Around DRAM Right under DRAM +1.35VS_VGA
Around DRAM Right under DRAM
+1.35VS_VGA +1.35VS_VGA +1.35VS_VGA
+1.35VS_VGA
Around DRAM +1.35VS_VGA
Right under DRAM +1.35VS_VGA +1.35VS_VGA +1.35VS_VGA
+1.35VS_VGA
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG8411
CG8410
CG7456
CG7457
CG7458
CG7459
CG7460
CG7461
CG8083
CG8084
CG8085
CG8086
CG8087
CG8088
CG8089
CG8090
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG8408
CG8409
CG7408
CG7409
CG7410
CG7411
CG7412
CG7413
CG8019
CG8020
CG8021
CG8022
CG8023
CG8024
CG8025
CG8026
CG8415
CG8414
CG7568
CG7569
CG7570
CG7571
CG7572
CG7573
CG8171
CG8172
CG8173
CG8174
CG8175
CG8176
CG8177
CG8178
CG8413
CG8412
CG7512
CG7513
CG7514
CG7515
CG7516
CG7517
CG8107
CG8108
CG8109
CG8110
CG8111
CG8112
CG8113
CG8114
1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0710, add CG8410-CG8411 ref NV HWDG.

0710, add CG8408-CG8409 ref NV HWDG. 0710, add CG8412-CG8413 ref NV HWDG.
Right under DRAM Right under DRAM +1.35VS_VGA Close to DRAM UG12 +1.35VS_VGA
Right under DRAM Close to DRAM UG14
+1.35VS_VGA
Right under DRAM +1.35VS_VGA Close to DRAM UG13 +1.35VS_VGA
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
4 4
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG8055
CG8056
CG8057
CG8058
CG8059
CG8060
CG8061
CG8062
CG8063
CG8064
CG8065
CG8066
CG8067
CG8068
CG8069
CG8070
CG8071
CG8072
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG8027
CG8028
CG8029
CG8030
CG8031
CG8032
CG8033
CG8034
CG8035
CG8036
CG8037
CG8038
CG8039
CG8040
CG8041
CG8042
CG8043
CG8044
CG8153
CG8154
CG8155
CG8156
CG8157
CG8158
CG8159
CG8160
CG8161
CG8162
CG8163
CG8164
CG8165
CG8166
CG8167
CG8168
CG8169
CG8170
CG8132
CG8131
CG8130
CG8129
CG8128
CG8127
CG8126
CG8125
CG8124
CG8123
CG8122
CG8121
CG8120
CG8119
CG8118
CG8117
CG8116
CG8115
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Close to DRAM UG11 Close to DRAM UG12 +1.35VS_VGA

Close to DRAM UG14
+1.35VS_VGA
+1.35VS_VGA
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1 1 1 1 1 1 1 1 1 1
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG8082
CG8081
CG8080
CG8079
CG8078
CG8077
CG8076
CG8075
CG8074
CG8073
1 1 1 1 1 1 1 1 1 1
CG8045
CG8046
CG8047
CG8048
CG8049
CG8050
CG8051
CG8052
CG8053
CG8054
CG8143
CG8144
CG8145
CG8146
CG8147
CG8148
CG8149
CG8150
CG8151
CG8152
CG8133
CG8134
CG8135
CG8136
CG8137
CG8138
CG8139
CG8140
CG8141
CG8142
2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2

0726, change CG8019-CG8054 to 1uF, ref NV HWDG. 0726, change CG8107-CG8142 to 1uF, ref NV HWDG.
VRAM_GDDR6_AB
A B C D E
A B C D E
@
UG15 @
UG16 @
UG17 @
C2 B4 UG18
<31> FB_C_EDC0 C13 EDC0_A DQ0_A A3 FB_C_D6 <31> C2 B4
<31> FB_C_EDC1 T2 EDC1_A DQ1_A B3 FB_C_D7 <31> <31> FB_C_EDC4 C13 EDC0_A DQ0_A A3 FB_C_D32 <31> C2 B4
<31> FB_C_EDC3 T13 EDC0_B DQ2_A B2 FB_C_D5 <31> <31> FB_C_EDC5 T2 EDC1_A DQ1_A B3 FB_C_D36 <31> <31> FB_D_EDC0 C13 EDC0_A DQ0_A A3 FB_D_D6 <31> C2 B4
<31> FB_C_EDC2 EDC1_B DQ3_A E3 FB_C_D4 <31> <31> FB_C_EDC7 T13 EDC0_B DQ2_A B2 FB_C_D39 <31> <31> FB_D_EDC1 T2 EDC1_A DQ1_A B3 FB_D_D0 <31> <31> FB_D_EDC4 C13 EDC0_A DQ0_A A3 FB_D_D34 <31>
DQ4_A E2 FB_C_D2 <31> <31> FB_C_EDC6 EDC1_B DQ3_A E3 FB_C_D37 <31> <31> FB_D_EDC3 T13 EDC0_B DQ2_A B2 FB_D_D2 <31> <31> FB_D_EDC5 T2 EDC1_A DQ1_A B3 FB_D_D36 <31>
D2 DQ5_A F2 FB_C_D3 <31> DQ4_A E2 FB_C_D33 <31> <31> FB_D_EDC2 EDC1_B DQ3_A E3 FB_D_D7 <31> <31> FB_D_EDC7 T13 EDC0_B DQ2_A B2 FB_D_D33 <31>
1 <31> FB_C_DBI0 D13 DBI0#_A DQ6_A G2 FB_C_D0 <31> D2 DQ5_A F2 FB_C_D35 <31> DQ4_A E2 FB_D_D1 <31> <31> FB_D_EDC6 EDC1_B DQ3_A E3 FB_D_D39 <31> 1
<31> FB_C_DBI1 R2 DBI1#_A DQ7_A B11 FB_C_D1 <31> <31> FB_C_DBI4 D13 DBI0#_A DQ6_A G2 FB_C_D34 <31> D2 DQ5_A F2 FB_D_D3 <31> DQ4_A E2 FB_D_D37 <31>
<31> FB_C_DBI3 R13 DBI0#_B DQ8_A A12 FB_C_D15 <31> <31> FB_C_DBI5 R2 DBI1#_A DQ7_A B11 FB_C_D38 <31> <31> FB_D_DBI0 D13 DBI0#_A DQ6_A G2 FB_D_D4 <31> D2 DQ5_A F2 FB_D_D38 <31>
<31> FB_C_DBI2 DBI1#_B DQ9_A B12 FB_C_D14 <31> <31> FB_C_DBI7 R13 DBI0#_B DQ8_A A12 FB_C_D46 <31> <31> FB_D_DBI1 R2 DBI1#_A DQ7_A B11 FB_D_D5 <31> <31> FB_D_DBI4 D13 DBI0#_A DQ6_A G2 FB_D_D32 <31>
DQ10_A B13 FB_C_D13 <31> <31> FB_C_DBI6 DBI1#_B DQ9_A B12 FB_C_D44 <31> <31> FB_D_DBI3 R13 DBI0#_B DQ8_A A12 FB_D_D12 <31> <31> FB_D_DBI5 R2 DBI1#_A DQ7_A B11 FB_D_D35 <31>
J10 DQ11_A E12 FB_C_D12 <31> DQ10_A B13 FB_C_D45 <31> <31> FB_D_DBI2 DBI1#_B DQ9_A B12 FB_D_D13 <31> <31> FB_D_DBI7 R13 DBI0#_B DQ8_A A12 FB_D_D47 <31>
<31> FB_C_CLK0 K10 CK_T DQ12_A E13 FB_C_D11 <31> J10 DQ11_A E12 FB_C_D40 <31> DQ10_A B13 FB_D_D8 <31> <31> FB_D_DBI6 DBI1#_B DQ9_A B12 FB_D_D41 <31>
<31> FB_C_CLK#0 G10 CK_C DQ13_A F13 FB_C_D9 <31> <31> FB_C_CLK1 K10 CK_T DQ12_A E13 FB_C_D41 <31> J10 DQ11_A E12 FB_D_D14 <31> DQ10_A B13 FB_D_D43 <31>
<31> FB_C_CMD10 M10 CKE#_A DQ14_A G13 FB_C_D8 <31> <31> FB_C_CLK#1 G10 CK_C DQ13_A F13 FB_C_D42 <31> <31> FB_D_CLK0 K10 CK_T DQ12_A E13 FB_D_D15 <31> J10 DQ11_A E12 FB_D_D42 <31>
CKE#_B DQ15_A FB_C_D10 <31> <31> FB_C_CMD26 M10 CKE#_A DQ14_A G13 FB_C_D43 <31> <31> FB_D_CLK#0 G10 CK_C DQ13_A F13 FB_D_D10 <31> <31> FB_D_CLK1 K10 CK_T DQ12_A E13 FB_D_D46 <31>
U4 CKE#_B DQ15_A FB_C_D47 <31> <31> FB_D_CMD10 M10 CKE#_A DQ14_A G13 FB_D_D11 <31> <31> FB_D_CLK#1 G10 CK_C DQ13_A F13 FB_D_D40 <31>
DQ0_B V3 FB_C_D31 <31> U4 CKE#_B DQ15_A FB_D_D9 <31> <31> FB_D_CMD26 M10 CKE#_A DQ14_A G13 FB_D_D44 <31>
DQ1_B U3 FB_C_D29 <31> DQ0_B V3 FB_C_D58 <31> U4 CKE#_B DQ15_A FB_D_D45 <31>
J5 DQ2_B U2 FB_C_D30 <31> DQ1_B U3 FB_C_D61 <31> DQ0_B V3 FB_D_D28 <31> U4
<31> FB_C_CMD6 K5 CABI#_A DQ3_B P3 FB_C_D28 <31> J5 DQ2_B U2 FB_C_D56 <31> DQ1_B U3 FB_D_D30 <31> DQ0_B V3 FB_D_D58 <31>
CABI#_B DQ4_B P2 FB_C_D27 <31> <31> FB_C_CMD22 K5 CABI#_A DQ3_B P3 FB_C_D57 <31> J5 DQ2_B U2 FB_D_D31 <31> DQ1_B U3 FB_D_D59 <31>
DQ5_B N2 FB_C_D26 <31> CABI#_B DQ4_B P2 FB_C_D59 <31> <31> FB_D_CMD6 K5 CABI#_A DQ3_B P3 FB_D_D26 <31> J5 DQ2_B U2 FB_D_D57 <31>
DQ6_B M2 FB_C_D24 <31> DQ5_B N2 FB_C_D60 <31> CABI#_B DQ4_B P2 FB_D_D29 <31> <31> FB_D_CMD22 K5 CABI#_A DQ3_B P3 FB_D_D56 <31>
DQ7_B U11 FB_C_D25 <31> DQ6_B M2 FB_C_D63 <31> DQ5_B N2 FB_D_D27 <31> CABI#_B DQ4_B P2 FB_D_D62 <31>
DQ8_B V12 FB_C_D23 <31> DQ7_B U11 FB_C_D62 <31> DQ6_B M2 FB_D_D24 <31> DQ5_B N2 FB_D_D63 <31>
2 1 J14 DQ9_B U12 FB_C_D21 <31> DQ8_B V12 FB_C_D48 <31> DQ7_B U11 FB_D_D25 <31> DQ6_B M2 FB_D_D61 <31>
RG105 121_0402_1%
2 1 K14 ZQ_A DQ10_B U13 FB_C_D20 <31> 2 1 J14 DQ9_B U12 FB_C_D49 <31> DQ8_B V12 FB_D_D23 <31> DQ7_B U11 FB_D_D60 <31>
RG106 121_0402_1% RG577 121_0402_1%
ZQ_B DQ11_B P12 FB_C_D22 <31> 2 1 K14 ZQ_A DQ10_B U13 FB_C_D51 <31> 2 1 J14 DQ9_B U12 FB_D_D20 <31> DQ8_B V12 FB_D_D51 <31>
RG578 121_0402_1% RG107 121_0402_1%
DQ12_B P13 FB_C_D18 <31> ZQ_B DQ11_B P12 FB_C_D50 <31> 2 1 K14 ZQ_A DQ10_B U13 FB_D_D22 <31> 2 1 J14 DQ9_B U12 FB_D_D49 <31>
RG108 121_0402_1% RG579 121_0402_1%
DQ13_B N13 FB_C_D16 <31> DQ12_B P13 FB_C_D53 <31> ZQ_B DQ11_B P12 FB_D_D21 <31> 2 1 K14 ZQ_A DQ10_B U13 FB_D_D50 <31>
RG580 121_0402_1%
DQ14_B M13 FB_C_D17 <31> DQ13_B N13 FB_C_D54 <31> DQ12_B P13 FB_D_D17 <31> ZQ_B DQ11_B P12 FB_D_D48 <31>
DQ15_B FB_C_D19 <31> DQ14_B M13 FB_C_D55 <31> DQ13_B N13 FB_D_D19 <31> DQ12_B P13 FB_D_D55 <31>
DQ15_B FB_C_D52 <31> DQ14_B M13 FB_D_D16 <31> DQ13_B N13 FB_D_D52 <31>
N5 H3 DQ15_B FB_D_D18 <31> DQ14_B M13 FB_D_D53 <31>
F10 TCK CA0_A G11 FB_C_CMD0 <31> N5 H3 DQ15_B FB_D_D54 <31>
N10 TDI CA1_A G4 FB_C_CMD9 <31> F10 TCK CA0_A G11 FB_C_CMD20 <31> N5 H3
F5 TDO CA2_A H12 FB_C_CMD8 <31> N10 TDI CA1_A G4 FB_C_CMD28 <31> F10 TCK CA0_A G11 FB_D_CMD0 <31> N5 H3
TMS CA3_A FB_C_CMD7 FB_C_CMD32 <31> TDO CA2_A FB_C_CMD21 <31> TDI CA1_A FB_D_CMD9 <31> TCK CA0_A FB_D_CMD20 <31>
H5 FB_C_CMD11 F5 H12 FB_C_CMD23 N10 G4 F10 G11
CA4_A H10 FB_C_CMD7 <31> TMS CA3_A H5 FB_C_CMD27 FB_C_CMD29 <31> F5 TDO CA2_A H12 FB_D_CMD8 <31> N10 TDI CA1_A G4 FB_D_CMD28 <31>
CA5_A FB_C_CMD15 FB_C_CMD11 <31> CA4_A FB_C_CMD23 <31> TMS CA3_A FB_D_CMD7 FB_D_CMD32 <31> TDO CA2_A FB_D_CMD21 <31>
J12 FB_C_CMD14 H10 FB_C_CMD30 H5 FB_D_CMD11 F5 H12 FB_D_CMD23
D4 CA6_A J11 FB_C_CMD15 <31> CA5_A J12 FB_C_CMD31 FB_C_CMD27 <31> CA4_A H10 FB_D_CMD7 <31> TMS CA3_A H5 FB_D_CMD27 FB_D_CMD29 <31>
<31> FB_C_WCK01 WCK0_T_A CA7_A FB_C_CMD3 FB_C_CMD14 <31> CA6_A FB_C_CMD30 <31> CA5_A FB_D_CMD15 FB_D_CMD11 <31> CA4_A FB_D_CMD23 <31>
D5 J4 FB_C_CMD1 D4 J11 FB_C_CMD19 J12 FB_D_CMD14 H10 FB_D_CMD30
<31> FB_C_WCK#01 D11 WCK0_C_A CA8_A J3 FB_C_CMD3 <31> <31> FB_C_WCK45 D5 WCK0_T_A CA7_A J4 FB_C_CMD31 <31> D4 CA6_A J11 FB_D_CMD15 <31> CA5_A J12 FB_D_CMD31 FB_D_CMD27 <31>
<31> FB_C_WCKB01 WCK1_T_A CA9_A FB_C_CMD1 <31> <31> FB_C_WCK#45 WCK0_C_A CA8_A FB_C_CMD17 FB_C_CMD19 <31> <31> FB_D_WCK01 WCK0_T_A CA7_A FB_D_CMD3 FB_D_CMD14 <31> CA6_A FB_D_CMD30 <31>
D10 D11 J3 D5 J4 FB_D_CMD1 D4 J11 FB_D_CMD19
<31> FB_C_WCKB#01 WCK1_C_A L3 <31> FB_C_WCKB45 D10 WCK1_T_A CA9_A FB_C_CMD17 <31> <31> FB_D_WCK#01 D11 WCK0_C_A CA8_A J3 FB_D_CMD3 <31> <31> FB_D_WCK45 D5 WCK0_T_A CA7_A J4 FB_D_CMD31 <31>
CA0_B FB_C_CMD4 <31> <31> FB_C_WCKB#45 WCK1_C_A <31> FB_D_WCKB01 WCK1_T_A CA9_A FB_D_CMD1 <31> <31> FB_D_WCK#45 WCK0_C_A CA8_A FB_D_CMD17 FB_D_CMD19 <31>
M11 L3 D10 D11 J3
R4 CA1_B M4 FB_C_CMD12 <31> CA0_B M11 FB_C_CMD16 <31> <31> FB_D_WCKB#01 WCK1_C_A L3 <31> FB_D_WCKB45 D10 WCK1_T_A CA9_A FB_D_CMD17 <31>
<31> FB_C_WCKB23 R5 WCK0_T_B CA2_B L12 FB_C_CMD5 <31> R4 CA1_B M4 FB_C_CMD25 <31> CA0_B M11 FB_D_CMD4 <31> <31> FB_D_WCKB#45 WCK1_C_A L3
<31> FB_C_WCKB#23 WCK0_C_B CA3_B FB_C_CMD7 FB_C_CMD13 <31> <31> FB_C_WCKB67 WCK0_T_B CA2_B FB_C_CMD24 <31> CA1_B FB_D_CMD12 <31> CA0_B FB_D_CMD16 <31>
R11 L5 FB_C_CMD11 R5 L12 FB_C_CMD23 R4 M4 M11
<31> FB_C_WCK23 R10 WCK1_T_B CA4_B L10 <31> FB_C_WCKB#67 R11 WCK0_C_B CA3_B L5 FB_C_CMD33 <31> <31> FB_D_WCKB23 R5 WCK0_T_B CA2_B L12 FB_D_CMD5 <31> R4 CA1_B M4 FB_D_CMD25 <31>
<31> FB_C_WCK#23 WCK1_C_B CA5_B FB_C_CMD15 <31> FB_C_WCK67 WCK1_T_B CA4_B FB_C_CMD27 <31> FB_D_WCKB#23 WCK0_C_B CA3_B FB_D_CMD7 FB_D_CMD13 <31> <31> FB_D_WCKB67 WCK0_T_B CA2_B FB_D_CMD24 <31>
K12 FB_C_CMD14 R10 L10 FB_C_CMD30 R11 L5 FB_D_CMD11 R5 L12 FB_D_CMD23
CA6_B K11 <31> FB_C_WCK#67 WCK1_C_B CA5_B K12 FB_C_CMD31 <31> FB_D_WCK23 R10 WCK1_T_B CA4_B L10 <31> FB_D_WCKB#67 R11 WCK0_C_B CA3_B L5 FB_D_CMD33 <31>
CA7_B FB_C_CMD3 CA6_B <31> FB_D_WCK#23 WCK1_C_B CA5_B FB_D_CMD15 <31> FB_D_WCK67 WCK1_T_B CA4_B FB_D_CMD27
K4 FB_C_CMD1 K11 FB_C_CMD19 K12 FB_D_CMD14 R10 L10 FB_D_CMD30
CA8_B K3 CA7_B K4 FB_C_CMD17 CA6_B K11 <31> FB_D_WCK#67 WCK1_C_B CA5_B K12 FB_D_CMD31
+FBC_VREFC CA9_B CA8_B CA7_B FB_D_CMD3 CA6_B
K1 +1.35VS_VGA K3 K4 K11 FB_D_CMD19
VREFC +FBC_VREFC CA9_B CA8_B FB_D_CMD1 CA7_B
K1 +1.35VS_VGA K3 K4 FB_D_CMD17
VREFC +FBD_VREFC CA9_B CA8_B
C1 K1 +1.35VS_VGA K3
VDDQ1 VREFC +FBD_VREFC CA9_B
J1 E1 C1 K1 +1.35VS_VGA
<31> FB_C_CMD2 RESET# VDDQ2 H1 J1 VDDQ1 E1 C1 VREFC
VDDQ3 L1 <31> FB_C_CMD18 RESET# VDDQ2 H1 J1 VDDQ1 E1 C1
B1 VDDQ4 P1 VDDQ3 L1 <31> FB_D_CMD2 RESET# VDDQ2 H1 J1 VDDQ1 E1
D1 VSS1 VDDQ5 T1 B1 VDDQ4 P1 VDDQ3 L1 <31> FB_D_CMD18 RESET# VDDQ2 H1
F1 VSS2 VDDQ6 J2 D1 VSS1 VDDQ5 T1 B1 VDDQ4 P1 VDDQ3 L1
G1 VSS3 VDDQ7 K2 F1 VSS2 VDDQ6 J2 D1 VSS1 VDDQ5 T1 B1 VDDQ4 P1
M1 VSS4 VDDQ8 C4 G1 VSS3 VDDQ7 K2 F1 VSS2 VDDQ6 J2 D1 VSS1 VDDQ5 T1
N1 VSS5 VDDQ9 F4 M1 VSS4 VDDQ8 C4 G1 VSS3 VDDQ7 K2 F1 VSS2 VDDQ6 J2
R1 VSS6 VDDQ10 N4 N1 VSS5 VDDQ9 F4 M1 VSS4 VDDQ8 C4 G1 VSS3 VDDQ7 K2
U1 VSS7 VDDQ11 T4 R1 VSS6 VDDQ10 N4 N1 VSS5 VDDQ9 F4 M1 VSS4 VDDQ8 C4
A2 VSS8 VDDQ12 B5 U1 VSS7 VDDQ11 T4 R1 VSS6 VDDQ10 N4 N1 VSS5 VDDQ9 F4
V2 VSS9 VDDQ13 U5 A2 VSS8 VDDQ12 B5 U1 VSS7 VDDQ11 T4 R1 VSS6 VDDQ10 N4
C3 VSS10 VDDQ14 B10 V2 VSS9 VDDQ13 U5 A2 VSS8 VDDQ12 B5 U1 VSS7 VDDQ11 T4
D3 VSS11 VDDQ15 U10 C3 VSS10 VDDQ14 B10 V2 VSS9 VDDQ13 U5 A2 VSS8 VDDQ12 B5
F3 VSS12 VDDQ16 C11 D3 VSS11 VDDQ15 U10 C3 VSS10 VDDQ14 B10 V2 VSS9 VDDQ13 U5
G3 VSS13 VDDQ17 F11 F3 VSS12 VDDQ16 C11 D3 VSS11 VDDQ15 U10 C3 VSS10 VDDQ14 B10
M3 VSS14 VDDQ18 N11 G3 VSS13 VDDQ17 F11 F3 VSS12 VDDQ16 C11 D3 VSS11 VDDQ15 U10
N3 VSS15 VDDQ19 T11 M3 VSS14 VDDQ18 N11 G3 VSS13 VDDQ17 F11 F3 VSS12 VDDQ16 C11
R3 VSS16 VDDQ20 J13 N3 VSS15 VDDQ19 T11 M3 VSS14 VDDQ18 N11 G3 VSS13 VDDQ17 F11
T3 VSS17 VDDQ21 K13 R3 VSS16 VDDQ20 J13 N3 VSS15 VDDQ19 T11 M3 VSS14 VDDQ18 N11
A4 VSS18 VDDQ22 C14 T3 VSS17 VDDQ21 K13 R3 VSS16 VDDQ20 J13 N3 VSS15 VDDQ19 T11
E4 VSS19 VDDQ23 E14 A4 VSS18 VDDQ22 C14 T3 VSS17 VDDQ21 K13 R3 VSS16 VDDQ20 J13
H4 VSS20 VDDQ24 H14 E4 VSS19 VDDQ23 E14 A4 VSS18 VDDQ22 C14 T3 VSS17 VDDQ21 K13
L4 VSS21 VDDQ25 L14 H4 VSS20 VDDQ24 H14 E4 VSS19 VDDQ23 E14 A4 VSS18 VDDQ22 C14
P4 VSS22 VDDQ26 P14 L4 VSS21 VDDQ25 L14 H4 VSS20 VDDQ24 H14 E4 VSS19 VDDQ23 E14
V4 VSS23 VDDQ27 T14 P4 VSS22 VDDQ26 P14 L4 VSS21 VDDQ25 L14 H4 VSS20 VDDQ24 H14
C5 VSS24 VDDQ28 +1.35VS_VGA V4 VSS23 VDDQ27 T14 P4 VSS22 VDDQ26 P14 L4 VSS21 VDDQ25 L14
2 T5 VSS25 C5 VSS24 VDDQ28 +1.35VS_VGA V4 VSS23 VDDQ27 T14 P4 VSS22 VDDQ26 P14 2
C10 VSS26 A1 T5 VSS25 C5 VSS24 VDDQ28 +1.35VS_VGA V4 VSS23 VDDQ27 T14
T10 VSS27 VDD1 V1 C10 VSS26 A1 T5 VSS25 C5 VSS24 VDDQ28 +1.35VS_VGA
A11 VSS28 VDD2 H2 T10 VSS27 VDD1 V1 C10 VSS26 A1 T5 VSS25
E11 VSS29 VDD3 L2 A11 VSS28 VDD2 H2 T10 VSS27 VDD1 V1 C10 VSS26 A1
H11 VSS30 VDD4 E5 E11 VSS29 VDD3 L2 A11 VSS28 VDD2 H2 T10 VSS27 VDD1 V1
L11 VSS31 VDD5 P5 H11 VSS30 VDD4 E5 E11 VSS29 VDD3 L2 A11 VSS28 VDD2 H2
P11 VSS32 VDD6 E10 L11 VSS31 VDD5 P5 H11 VSS30 VDD4 E5 E11 VSS29 VDD3 L2
V11 VSS33 VDD7 P10 P11 VSS32 VDD6 E10 L11 VSS31 VDD5 P5 H11 VSS30 VDD4 E5
C12 VSS34 VDD8 H13 V11 VSS33 VDD7 P10 P11 VSS32 VDD6 E10 L11 VSS31 VDD5 P5
D12 VSS35 VDD9 L13 C12 VSS34 VDD8 H13 V11 VSS33 VDD7 P10 P11 VSS32 VDD6 E10
F12 VSS36 VDD10 A14 D12 VSS35 VDD9 L13 C12 VSS34 VDD8 H13 V11 VSS33 VDD7 P10
G12 VSS37 VDD11 V14 F12 VSS36 VDD10 A14 D12 VSS35 VDD9 L13 C12 VSS34 VDD8 H13
M12 VSS38 VDD12 +1V8_AON G12 VSS37 VDD11 V14 F12 VSS36 VDD10 A14 D12 VSS35 VDD9 L13
N12 VSS39 M12 VSS38 VDD12 +1V8_AON G12 VSS37 VDD11 V14 F12 VSS36 VDD10 A14
R12 VSS40 A5 N12 VSS39 M12 VSS38 VDD12 +1V8_AON G12 VSS37 VDD11 V14
T12 VSS41 VPP1 V5 R12 VSS40 A5 N12 VSS39 M12 VSS38 VDD12 +1V8_AON
A13 VSS42 VPP2 A10 T12 VSS41 VPP1 V5 R12 VSS40 A5 N12 VSS39
V13 VSS43 VPP3 V10 A13 VSS42 VPP2 A10 T12 VSS41 VPP1 V5 R12 VSS40 A5
B14 VSS44 VPP4 V13 VSS43 VPP3 V10 A13 VSS42 VPP2 A10 T12 VSS41 VPP1 V5
D14 VSS45 B14 VSS44 VPP4 V13 VSS43 VPP3 V10 A13 VSS42 VPP2 A10
F14 VSS46 G5 D14 VSS45 B14 VSS44 VPP4 V13 VSS43 VPP3 V10
G14 VSS47 NC1 M5 F14 VSS46 G5 D14 VSS45 B14 VSS44 VPP4
M14 VSS48 NC2 G14 VSS47 NC1 M5 F14 VSS46 G5 D14 VSS45
N14 VSS49 M14 VSS48 NC2 G14 VSS47 NC1 M5 F14 VSS46 G5
R14 VSS50 N14 VSS49 M14 VSS48 NC2 G14 VSS47 NC1 M5
U14 VSS51 R14 VSS50 N14 VSS49 M14 VSS48 NC2
180-B A LL
VSS52 SGRAM GDDR6 U14 VSS51 R14 VSS50 N14 VSS49
180-B A LL
VSS52 SGRAM GDDR6 U14 VSS51 R14 VSS50
180-B A LL
VSS52 SGRAM GDDR6 U14 VSS51
180-B A LL
MT61K256M32JE-13-A_FBGA180~D VSS52 SGRAM GDDR6
+1.35VS_VGA
1
GDDR6 CMD Mapping x16 Mode

Lower 0..31 Upper 32..63 RG132 +1.35VS_VGA
DRAM1 DRAM2 549_0402_1%
CHA-Byte 0,1 CHA-Byte 4,5 @
1
2
RG155 GDDR6 CMD Mapping

CA0_A
CA1_A
CMD 0
CMD 9
CMD20
CMD28 1 2
+FBC_VREFC
W=16mils 549_0402_1% Lower 0..31
x16 Mode
Upper 32..63
CA2_A CMD 8 CMD21 @ DRAM1 DRAM2
820P_0402_25V7
1K_0402_1%
1
RG134
CG148
CA3_A CMD32 CMD29 RG133 1 CHA-Byte 0,1 CHA-Byte 4,5
2
931_0402_1%
CA4_A
CA5_A
CMD 7
CMD 11
CMD23
CMD27
@ @ 1 2
+FBD_VREFC
W=16mils CA0_A CMD 0 CMD20
1
D
CA6_A CMD15 CMD30 CA1_A CMD 9 CMD28
820P_0402_25V7
1K_0402_1%
1
2
RG154
CG256
CA7_A CMD14 CMD31 2 QG4 RG156 1 CA2_A CMD 8 CMD21
<30,35> MEM_VREF_CTL
2
CA8_A CMD 3 CMD19 G MESS138W-G_SOT323-3 931_0402_1% CA3_A CMD32 CMD29

CA9_A CMD 1 CMD17 S @ @ @ CA4_A CMD 7 CMD23
3
1
D
CABI_A CMD 6 CMD22 MEM_VREF_CTL CA5_A CMD 11 CMD27
CKE_A CMD10 CMD26 2 QG8 2 CA6_A CMD15 CMD30
2
G MESS138W-G_SOT323-3 CA7_A CMD14 CMD31
CHB-Byte 2,3 CHB-Byte 6,7 S @ CA8_A CMD 3 CMD19
3
CA0_B CMD 4 CMD16 CA9_A CMD 1 CMD17
CA1_B CMD12 CMD25 CABI_A CMD 6 CMD22
CA2_B CMD 5 CMD24 CKE_A CMD10 CMD26
CA3_B CMD13 CMD33
CA4_B CMD 7 CMD23 CHB-Byte 2,3 CHB-Byte 6,7
CA7_B CMD14 CMD31 CA2_B CMD 5 CMD24
3 CA8_B CMD 3 CMD19 CA3_B CMD13 CMD33
3
CABI_B CMD 6 CMD22 CA5_B CMD 11 CMD27
CKE_B CMD10 CMD26 CA6_B CMD15 CMD30
CA7_B CMD14 CMD31
RESET * CMD 2 CMD18 CA8_B CMD 3 CMD19
CA9_B CMD 1 CMD17
CABI_B CMD 6 CMD22
CKE_B CMD10 CMD26
RESET * CMD 2 CMD18
UG15 UG16 Close to DRAM UG18 UG18

Close to DRAM UG15 Close to DRAM UG16 Close to DRAM UG17
UG17 +1.35VS_VGA +1V8_AON
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
4.7U_0402_4V_M
+1.35VS_VGA +1V8_AON
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
+1.35VS_VGA +1V8_AON +1.35VS_VGA 2 2 2 2 1 2 2 2 2
CG8191
CG8192
CG8193
CG8194
+1V8_AON
CG7802
CG7796
CG7801
CG7800
CG8427
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
4.7U_0402_4V_M
1 1 1 1 2 1 1 1 1
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
4.7U_0402_4V_M
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
2 2 2 2 1 2 2 2 2
4.7U_0402_4V_M
CG8425
CG8278
CG8277
CG8276
CG8275
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
2 2 2 2 1 2 2 2 2 2 2 2 2
CG8424
CG8358
CG8357
CG8356
CG8355
CG7689
CG7685
CG7682
CG7681
1 2 2 2 2
CG7784
CG7760
CG7765
CG7764
CG7715
CG7700
CG7709
CG7707
CG8426
CG8270
CG8269
CG8268
CG8267
1 1 1 1 2 1 1 1 1 0710, add CG8427 4.7uF, ref NV HWDG.
1 1 1 1 2 1 1 1 1 1 1 1 1
2 1 1 1 1
0710, remove CG7804, CG7798,
0710, add CG8424 4.7uF, ref NV HWDG. 0710, remove CG7690, CG7675, 0726, change CG8275-CG8278 to 1uF, ref NV HWDG.
0710, remove CG7771/CG7766, 0726, change CG8355-CG8358 to 1uF, ref NV HWDG. and CG8279-CG8282 ref NV HWDG. 0710, add CG8426 4.7uF, ref NV HWDG.
and CG8359-CG8362 ref NV HWDG. 0710, remove CG7712, CG7706,
+1.35VS_VGA
Around DRAM +1.35VS_VGA
Right under DRAM +1.35VS_VGA
Around DRAM Right under DRAM Around DRAM Right under DRAM
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
+1.35VS_VGA
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
Around DRAM Right under DRAM 2 2 1 1 1 1 1 1 2 2 2 2 2 2 2 2
CG8202
CG8201
CG8200
CG8199
CG8198
CG8197
CG8196
CG8195
CG8423
CG8422
CG7770
CG7772
CG7773
CG7774
CG7775
CG7776
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
2 2 1 1 1 1 1 1 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
22U_0603_6.3V X5R
CG8290
CG8289
CG8288
CG8287
CG8286
CG8285
CG8284
CG8283
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
2 2 1 1 1 1 1 1 2 2 2 2 2 2 2 2
CG8354
CG8353
CG8352
CG8351
CG8350
CG8349
CG8348
CG8347
CG8419
CG8418
CG7632
CG7634
CG7635
CG7636
CG7637
CG7638
2 2 1 1 1 1 1 1 2 2 2 2 2 2 2 2
CG8417
CG8416
CG7625
CG7626
CG7627
CG7628
CG7629
CG7630
CG8266
CG8265
CG8264
CG8263
CG8262
CG8261
CG8260
CG8259
CG8421
CG8420
CG7644
CG7647
CG7649
CG7651
CG7655
CG7656
1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1
1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1
1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1

0710, add CG8420-CG8421 ref NV HWDG. Right under DRAM +1.35VS_VGA
Right under DRAM Right under DRAM +1.35VS_VGA Close to DRAM UG16 +1.35VS_VGA
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
+1.35VS_VGA
Right under DRAM Close to DRAM UG17 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CG8203
CG8204
CG8205
CG8206
CG8207
CG8208
CG8209
CG8210
CG8211
CG8212
CG8213
CG8214
CG8215
CG8216
CG8217
CG8218
CG8219
CG8220
4 4
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CG8318
CG8317
CG8316
CG8315
CG8314
CG8313
CG8312
CG8311
CG8300
CG8299
CG8298
CG8297
CG8296
CG8295
CG8294
CG8293
CG8292
CG8291
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CG8346
CG8345
CG8344
CG8343
CG8342
CG8341
CG8340
CG8339
CG8338
CG8337
CG8336
CG8335
CG8334
CG8333
CG8332
CG8331
CG8330
CG8329
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CG8258
CG8257
CG8256
CG8255
CG8254
CG8253
CG8252
CG8251
CG8250
CG8249
CG8248
CG8247
CG8246
CG8245
CG8244
CG8243
CG8242
CG8241
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Close to DRAM UG15 Close to DRAM UG16 +1.35VS_VGA
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
+1.35VS_VGA
Close to DRAM UG17 2 2 2 2 2 2 2 2 2 2
CG8230
CG8229
CG8228
CG8227
CG8226
CG8225
CG8224
CG8223
CG8222
CG8221
+1.35VS_VGA
1 1 1 1 1 1 1 1 1 1
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
2 2 2 2 2 2 2 2 2 2
CG8310
CG8309
CG8308
CG8307
CG8306
CG8305
CG8304
CG8303
CG8302
CG8301
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
2 2 2 2 2 2 2 2 2 2
CG8328
CG8327
CG8326
CG8325
CG8324
CG8323
CG8322
CG8321
CG8320
CG8319
2 2 2 2 2 2 2 2 2 2
CG8240
CG8239
CG8238
CG8237
CG8236
CG8235
CG8234
CG8233
CG8232
CG8231
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 0726, change CG8195-CG8230 to 1uF, ref NV HWDG.
1 1 1 1 1 1 1 1 1 1

0726, change CG8319-CG8354 to 1uF, ref NV HWDG. 0726, change CG8283-CG8318 to 1uF, ref NV HWDG. Issued Date 2018/08/07 Deciphered Date 2019/08/07 Title
VRAM_GDDR6_CD
A B C D E
5 4 3 2 1
D D
+1V8_AON
+1V8_AON / +1V8_MAIN
1
+3VS
RG1516
100K_0201_5%
1
1
CG7105 RG1514
2
0.1U_0201_6.3V6K 10K_0402_5%
+1.8VALW +1V8_AON
2 UG45
2
1 14
VIN1 VOUT1
5
2 13
VIN1 VOUT1
10U_0603_6.3V6M
1 VCC CG7099
<27,108> +1.35VS_VGA_PGOOD B 4 1V8_AON_EN 3 12 1 2 220P_0402_50V8J
Y ON1 CT1 1
CG7100
2 A
<18,32,58> DGPU_PWR_EN G UG46 +5VS 4 11
74LVC1G32GW_TSSOP5 VBIAS GND CG7097
3
1V8_MAIN_ENR 5 10 1 2 220P_0402_50V8J 2
ON2 CT2 Near UG45.13
6 9
+1V8_AON VIN2 VOUT2 +1V8_MAIN
1 7 8
VIN2 VOUT2
10U_0603_6.3V6M
CG7103
22U_0603_4V_M
10U_0402_6.3V6M
0.1U_0402_10V7K
0.1U_0402_16V7K 15 1
GPAD
CG7098
@ 1 1
1
2
CG7104
CG7101
CG7096
AOZ1331DI_DFN14-10
<34> 1V8_AON_EN 2
Near UG45.8
2
2 2
Near UG45.1
@
1 2
<32> 1V8_MAIN_ENP
0_0402_5%
RG1556
Near UG45.6 Near UG45.4
C 1 2 C
<30,32,34> 1V8_MAIN_EN
0_0402_5%
RG1557
+1V8_MAIN +1V8_AON +1V8_MAIN +3VS

NV_3V3 +3V3_SYS
UG36
1 1
VIN1
1
1
CG478 1 2
RG1517 RG515 CG322 VIN2
0.1U_0201_6.3V6K
10K_0201_5% 10K_0201_5% 1U_0402_6.3V6K 7 6
VIN thermal VOUT
5
@ 2 @
RG545 2 3 1 1
VCC
+5VALW
2
2
DGPU_PWR_EN 1 2.2K_0201_1% VBIAS CG323 CG385
IN B 4 1 2 3V3_SYS_EN 4 5 .1U_0402_16V7K 10U_0402_6.3V6M
1V8_MAIN_EN 1 2 2 OUT Y ON GND
GND
0_0201_5% IN A @ 2 2
1 1
RG1544 UG26 CG240 CG384
NL17SZ08DFT2G_SC70-5 0.1U_0402_16V7K 0.1U_0402_10V7K AOZ1334DI-01_DFN8-7_3X3
1
3
0.047U_0201_10V6K
CD402
2 2
2
B B
<34> 3V3_SYS_EN
A A

DGPU_DC/DC Interface
5 4 3 2 1
A B C D E
Main Func = LCD Main Func = CAM 4

LV2
EMI@
3 USB20_P7_R
9/12 DVT1 Modify <17> USB20_P7 4 3
+LCDVDD_OUT +LCDVDD USB20_N7_R

LCD power control
1 2
+3VALW CAMERA POWER <17> USB20_N7 1 2
UV4 FV8 Place close to JEDP DLM0NSN900HY2D_4P

W=80 mils 1
IN OUT
6 W=80 mils 1 2
SW_EDP_TXP0 SW_EDP_TXP0_C
JEDP
2
+3VS +3VS_CAMERA
CV1078
CV1079
CV1080
CV1081
2 0.1U_0201_6.3V6K 2 1 CV1 1
IN SW_EDP_TXN0 SW_EDP_TXN0_C 1
10P_0402_50V8J
10U_0603_6.3V6M
10U_0603_6.3V6M
CV17
CV18
3 7 3A_32V_F0603FA3000V032T 0.1U_0201_6.3V6K 2 1 CV2 2 DV4
2
+5VALW VBIAS VCC_PAD 2
1 1 1 ENVDD 4 5 1 1 1 1 3 AZC199-02S.R7G_SOT23-3
ON GND SW_EDP_TXP1 SW_EDP_TXP1_C 3
1
CV1075
RF@
CV1076
CV1077
@EMI@
0.1U_0201_6.3V6K 2 1 CV3 4 FV7 @ESD@
SW_EDP_TXN1 SW_EDP_TXN1_C 4
1
RF@
AOZ1334DI-02_DFN8-7_3X3 0.1U_0201_6.3V6K 2 1 CV4 5 1 2 82P_0201_25V8J
5
47U_0603_6.3V6M
10P_0402_50V8J
2200P_0402_25V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
6 1 1 1
SA000070V00
1
2 2 2 2 2 2 2 SW_EDP_TXP2 SW_EDP_TXP2_C 6
10U_0603_6.3V6M
0.1U_0201_6.3V6K 2 1 CV8 7 0.5A_65V_T0603FF0500TM @ CV7163
SW_EDP_TXN2 0.1U_0201_6.3V6K 2 1 CV6 SW_EDP_TXN2_C 8 7 CV7160 RF@ CV7161
8
1
1 9 9/8 DVT1 Modify .1U_0402_16V7K 4.7U_0402_6.3V6M
CV7162 RV687 SW_EDP_TXP3 0.1U_0201_6.3V6K 2 1 CV7 SW_EDP_TXP3_C 10 9 2 2 2
0.1U_0201_10V6K 100K_0201_5% SW_EDP_TXN3 0.1U_0201_6.3V6K 2 1 CV11 SW_EDP_TXN3_C 11 10
12 11
2 SW_EDP_AUXP 0.1U_0201_6.3V6K 2 1 CV12 SW_EDP_AUXP_C 13 12
1 1
2 SW_EDP_AUXN 0.1U_0201_6.3V6K 2 1 CV13 SW_EDP_AUXN_C 14 13
15 14
16 15
USB20_N7_R 17 16
USB20_P7_R 18 17
SW_EDP_HPD
DISP_OFF#
19
20
18
19
20
Main Func = DDS
DV1 2 1 RB751V40_SC76-2 21
<58> BKOFF EDP_PWM 21
22
EDP_LCD_TEST 23 22
LCD backlight power control +INV_PWR_SRC +INV_PWR_LCD
24
25
23
24 +3VALW
+19VB <73> MIC_DATA 26 25
<73> MIC_CLK 27 26 DDS@
FV4 SCL_EDP 28 27 RV691
W=80 mils <30> SCL_EDP SDA_EDP 28
1
6 1 2 29 1 2
<30> SDA_EDP GSYNC_DET 29 <30> DGPU_ENBKL
5 RV679 30 0_0201_5%
<58> GSYNC_DET 30
5
2 1.5A_24V_SMD1812P150TF-24 0_0201_5% GSYNC# 31
W=80 mils <30> GSYNC# 31 ENBKL_PCH
1
4 1 @EMI@ 0.5A 32 1 VCC
S
+3VS_CAMERA 32 B
RV697 33 4 ENBKL
1 W=60 mils Y
2
33 DGPU_BL_EN
0.47U_0402_25V6K
100K_0402_5%
RV9
820_0603_1% +LCDVDD 34 2 A
34
1
CV14 FV5 35 G
G
1 1 +5VS_AW 35
CV15
QV1 0.1U_0402_25V7K 1 2 36
+5VS
3
3
SI3457CDV-T1-GE3_TSOP6 2 CV1071 0.5A_65V_T0603FF0500TM 37 36 UG50
10P_0201_50V8J 38 37 74LVC1G32GW_TSSOP5
2 2 39 38
+INV_PWR_LCD_R
@RF@ +INV_PWR_LCD DDS@
2
40 39 +3VALW
40
PWR_SRC_ON 41 +3VALW
42 GND
GND
1
43
GND
5
RV12 44
100K_0402_5% GND Panel RST
9/12 DVT1 Modify
VCC
5
ACES_50473-0400M-P01 1
ENVDD_PCH <58> EC_EDP_RESET IN B
CONN@ 1 VCC 4 ENVDD
2
OUT Y
3
B
4 2
GND
Y IN A
SP01001VP00 2 A
<30> DGPU_LCD_EN G
QV2B UG52
6
5 L2N7002DW1T1G_SC88-6 NL17SZ08DFT2G_SC70-5
3
UG51 DDS@
QV2A 74LVC1G32GW_TSSOP5
2 L2N7002DW1T1G_SC88-6 DDS@
<58> EN_INVPWR
4
2 <58> EC_PWM_EN <58> EC_EDP_PWM 2
1
DISP_OFF#
+3VALW
9/12 DVT1 Add discharge circuit to meet LCD sequence +INV_PWR_LCD
1
UG53
BIA_PWM_PCH
2
G
RV1 1 5
+LCDVDD 10K_0201_5% NO V+
DGPU_BL_PWM EDP_PWM
1
@RF@ 3 4 3 1 1 RV690 2
RV682 1 @ 2 0_0201_5% EDP_LCD_TEST CV375 NC COM
D
<17> PCH_LCD_TEST
2
RV692 2 @ 1 2.2K_0201_5% SCL_EDP 10P_0402_50V8J 6 2 0_0402_1%
<30> DGPU_PWM_SEL
2
RV693 2 @ 1 2.2K_0201_5% SDA_EDP RV254 1 2 0_0201_5% IN GND QV100
<58> EC_LCD_TEST DDS@
LCDTESTEC@ TS5A3159ADCKR_SC70-6 L2N7002WT1G_SC-70-3
DDS@ DDS@
Main Func = eDP MUX +3VS

+3VS +3VS
1 1
CV61 CV62
2
0.1U_0201_6.3V6K 0.1U_0201_6.3V6K
UV20 RV117 RV124 RV123
2 2 21 100K_0201_5%
VDD33 4.7K_0201_5% 4.7K_0201_5%
26 @ @
35 VDD33
1
49 VDD33 32 SW_EDP_AUXP I2C_CTL_EN
60 VDD33 OUT_AUXp_SCL 31 SW_EDP_AUXN PD
VDD33 OUT_AUXn_SDA
IN2_PEQ
1
SML0CLK RV110 1 @ 2 0_0201_5% 51
<16,74> SML0CLK IN1_PEQ IN2_PEQ/SCL_CTL I2C_CTL_EN
2
SML0DATA RV111 1 @ 2 0_0201_5% 52 53 RV118
<16,74> SML0DATA RV108 2 1 4.7K_0201_5% 59 IN1_PEQ/SDA_CTL I2C_CTL_EN 100K_0201_5% RV106 RV119
+3VS IN1_AEQ#
RV109 2 1 4.7K_0201_5% 58 4.7K_0201_5% 4.7K_0201_5%
IN2_AEQ# 56 PI0 @
2
PI0 38 PC0
1
GPU_EDP_TXP0 0.1U_0201_6.3V6K 2 1 CV40 GPU_EDP_TXP0_C 1 PC0 55 PC1
<28> GPU_EDP_TXP0 GPU_EDP_TXN0 GPU_EDP_TXN0_C IN1_D0p PC1
0.1U_0201_6.3V6K 2 1 CV41 2
<28> GPU_EDP_TXN0 GPU_EDP_TXP1 GPU_EDP_TXP1_C IN1_D0n
0.1U_0201_6.3V6K 2 1 CV42 4
<28> GPU_EDP_TXP1 GPU_EDP_TXN1 GPU_EDP_TXN1_C IN1_D1p
0.1U_0201_6.3V6K 2 1 CV43 5
0.1U_0201_6.3V6K 2 1 CV44 6 48 RV116 1 2 1M_0201_5%
GPU IFPD
<28> GPU_EDP_TXP2 GPU_EDP_TXN2 GPU_EDP_TXN2_C IN1_D2p CA_DET
0.1U_0201_6.3V6K 2 1 CV45 7
0.1U_0201_6.3V6K 2 1 CV46 9 +3VS
<28> GPU_EDP_TXP3 GPU_EDP_TXN3 GPU_EDP_TXN3_C IN1_D3p SW_EDP_TXP0
3 0.1U_0201_6.3V6K 2 1 CV47 10 46 3
<28> GPU_EDP_TXN3 IN1_D3n OUT_D0p SW_EDP_TXN0
RF@ 45
0.1U_0201_6.3V6K 2 1 CV48 GPU_EDP_AUXP_C 1 RV694 2 5.6_0402_5% GPU_EDP_AUXP_C_R 28 OUT_D0n 43 SW_EDP_TXP1
<28> GPU_EDP_AUXP 0.1U_0201_6.3V6K 2 1 CV49 GPU_EDP_AUXN_C 1 RV695 2 5.6_0402_5% GPU_EDP_AUXN_C_R 27 IN1_AUXp OUT_D1p 42 SW_EDP_TXN1
<28> GPU_EDP_AUXN RF@ 23 IN1_AUXn OUT_D1n 40 SW_EDP_TXP2
IN1_SCL OUT2_D2p SW_EDP_TXN2
2
RV120 2 1 100K_0201_5% 22 39
RV121 2 1 100K_0201_5% IN1_SDA OUT2_D2n 37 SW_EDP_TXP3 RV100 RV101 RV102
OUT_D3p 36 SW_EDP_TXN3
4.7K_0201_5% 4.7K_0201_5% 4.7K_0201_5%
EDP_TXP0 0.1U_0201_6.3V6K 2 1 CV50 EDP_TXP0_C 11 OUT_D3n @ @ @
<6> EDP_TXP0 EDP_TXN0 EDP_TXN0_C IN2_D0p
0.1U_0201_6.3V6K 2 1 CV51 12 RV689 1 @ 2 0_0201_5%
<6> EDP_TXN0 MUX_CTL_INTERNAL <30>
1
EDP_TXP1 0.1U_0201_6.3V6K 2 1 CV58 EDP_TXP1_C 14 IN2_D0n 54 EDP_SW_R RV688 1 2 0_0201_5% EDP_SW
<6> EDP_TXP1 EDP_TXN1 EDP_TXN1_C IN2_D1p SW
0.1U_0201_6.3V6K 2 1 CV54 15 PI0
<6> EDP_TXN1 EDP_TXP2 EDP_TXP2_C IN2_D1n SW_EDP_HPD
0.1U_0201_6.3V6K 2 1 CV52 16 44 PC0
CPU
<6> EDP_TXP2 EDP_TXN2 EDP_TXN2_C IN2_D2p OUT_HPD
0.1U_0201_6.3V6K 2 1 CV59 17 PC1
<6> EDP_TXN2 EDP_TXP3 EDP_TXP3_C IN2_D2n
0.1U_0201_6.3V6K 2 1 CV53 19
<6> EDP_TXP3 EDP_TXN3 EDP_TXN3_C IN2_D3p
0.1U_0201_6.3V6K 2 1 CV55 20
<6> EDP_TXN3 IN2_D3n
2
34 RV107 1 2 4.99K_0201_1%
EDP_AUXP 0.1U_0201_6.3V6K 2 1 CV57 EDP_AUXP_C 30 REXT 47 CV60 2 1 2.2U_0201_6.3V6M RV103 RV104 RV105
<6> EDP_AUXP EDP_AUXN 0.1U_0201_6.3V6K 2 1 CV56 EDP_AUXN_C 29 IN2_AUXp CEXT
<6> EDP_AUXN IN2_AUXn 4.7K_0201_5% 4.7K_0201_5% 4.7K_0201_5%
25 @ @ @
24 IN2_SCL 8
1
IN2_SDA GND 18
RF@ GND 33
GPU_EDP_HPD 1 RV696 2 5.6_0402_5% GPU_EDP_HPD_R 3 GND 41
<30> GPU_EDP_HPD EDP_HPD 13 IN1_HPD GND 57
<14> EDP_HPD IN2_HPD GND 61
Epad 50 PD
PD
PS8331BQFN60GTR-A2_QFN60_5X9 +3VS
SA000060U10
2
RV112 RV113
+5VS 4.7K_0201_5% 4.7K_0201_5%
S1 OE Output Function
1
IN1_PEQ
L L A=B1 DGPU 1 IN2_PEQ
CV63
H L A=B2 IGPU 0.1U_0201_10V6K
+3VS
2 UV21
X H
2
4 4
16
Vcc 4 EDP_PWM RV114 RV115
1A
1
2 7 ENVDD 4.7K_0201_5% 4.7K_0201_5%

<30> DGPU_BL_PWM 1B1 2A
3 9 ENBKL RV122
<14> BIA_PWM_PCH 1B2 3A ENBKL <58>
5 12 10K_0201_5%
<30> LCD_VDD_EN
1
6 2B1 4A
<14> ENVDD_PCH 2B2
11 15
<30> DGPU_BL_EN
2
10 3B1 OE# 1 EDP_SW

<14> ENBKL_PCH 3B2 S EDP_SW <18,58>
14
13 4B1 8
4B2 GND
SN74CBT3257CPWR_TSSOP16
SA00002KE00
5/10:Connect EC &PCH
eDP/Camera/TS
A B C D E
A B C D E
+5VS +3VS
1 1
JDP
1
2.2K_0201_5%
2.2K_0201_5%
CV23 1
GND
1
0.1U_0201_6.3V6K GPU_DP_HPD_R 2
GPU_DP_P0_C HPD
RV671
RV672
RV16 CV26 1 2 0.1U_0201_6.3V6K 3
2 <28> GPU_DP_P0 DP_CBL_DET 4 LANE0_P
100K_0201_5% <30> DP_CBL_DET CONFIG1
CV27 1 2 0.1U_0201_6.3V6K GPU_DP_N0_C 5
<28> GPU_DP_N0 1 2 5.1M_0402_5% DISP_CEC 6 LANE0_N
UV3 RV18
2
16 7 CONFIG2
Vcc 4 DISP_CLK_AUXP_CONN 8 GND
GPU_DP_AUXP_R 0.1U_0201_6.3V6K 2 1 CV24 GPU_DP_AUXP_C 2 1A 7 DISP_DAT_AUXN_CONN CV28 1 2 0.1U_0201_6.3V6K GPU_DP_P1_C 9 GND
GPU_DP_AUXP 3 1B1 2A 9 <28> GPU_DP_P1 1 2 GPU_DP_P3_C 10 LANE1_P
CV29 0.1U_0201_6.3V6K
GPU_DP_AUXN_R 0.1U_0201_6.3V6K 2 1 CV25 GPU_DP_AUXN_C 5 1B2 3A 12 <28> GPU_DP_P3 1 2 GPU_DP_N1_C 11 LANE3_P
CV30 0.1U_0201_6.3V6K
2B1 4A <28> GPU_DP_N1 LANE1_N
2
GPU_DP_AUXN 6 CV31 1 2 0.1U_0201_6.3V6K GPU_DP_N3_C 12
11 2B2 15 <28> GPU_DP_N3 13 LANE3_N
RV15
10 3B1 OE# 1 DP_CBL_DET 14 GND
3B2 S 100K_0201_5% GND
14 CV32 1 2 0.1U_0201_6.3V6K GPU_DP_P2_C 15
4B1 <28> GPU_DP_P2 LANE2_P
1
13 8 DISP_CLK_AUXP_CONN 16
1
4B2 GND RV17 CV33 1 2 0.1U_0201_6.3V6K GPU_DP_N2_C 17 AUX_CH_P 21
<28> GPU_DP_N2 DISP_DAT_AUXN_CONN 18 LANE2_N GND1 22
SN74CBT3257CPWR_TSSOP16 1M_0201_1%
19 AUX_CH_N GND2 23
SA00002KE00 20 GND GND3 24
2
DP_PWR GND4
+3VS +3VS_DP ACON_MAR2A-2061801
CONN@
+5VS 1 2
10U_0402_6.3V6M
0.1U_0201_6.3V6K
390P_0402_50V7K
FV2
1
1.1A_6V_SPR-P110 1 1
1
CV34
CV35
CV66
@EMI@
RX39 @
10K_0201_5%
2 2
2
2 2
2
1
D
QV3 2
NVVDD_PGOOD <27,30,32,98,102>
L2N7002WT1G_SC-70-3 G
S
3
UX3
5 1
IN OUT
2
GND
1 2 4 3 1 2
+1V8_MAIN EN OC +3VS_DP
GPU_DP_AUXP RX3 SY6288C20AAC_SOT23-5 RX9
10K_0201_5% 10K_0201_5%
@
GPU_DP_AUXN
+3VS
QX2
LMBT3904WT1G_SC70-3
1
C
+1V8_AON 2 1 2 GPU_DP_HPD_R
B
E RX2
3
150K_0201_5% 1
<18> DP_HPD_PCH
1
3 3
RX5 CX1
1
10K_0201_5% +1.8VALW 0.1U_0201_16V6K
CV20 2
RX4
1 2 GPU_DP_AUXP_R 1 2 10K_0201_5%
2
<28> GPU_DP_AUXP RV619 0_0201_5%
<30> GPU_DP_HPD#
0.1U_0201_16V6K
2
3
5
QV97B
VCC
1 2 GPU_DP_AUXN_R 1
<28> GPU_DP_AUXN DMN53D0LDW-7 2N SOT363-6 IN B
RV618 0_0201_5% 5 4
OUT Y 2
GND
IN A DGPU_PEX_RST# <27,30,40>
4
UX1
3
1
RV664 RV665
100K_0201_5% 100K_0201_5%
2
4 4

Mini DP
0.2
A B C D E
5 4 3 2 1
9/18 DVT1 Modify.
1 EMI@ 2 HDMI_L_CLKN 1 2 HDMI_CLKN

RV641 5.6_0402_1%
5.6_0201_1%
2
CV1057 2 1 0.1U_0201_6.3V6K HDMI_C_CLKN RV673
<28> GPU_HDMI_CLKN
RV500
150_0201_1%
CV1058 2 1 0.1U_0201_6.3V6K HDMI_C_CLKP +HDMI_5V_OUT
<28> GPU_HDMI_CLKP @EMI@ +5VS
5.6_0201_1%
1
D RV674 FV3 D
1 EMI@ 2 HDMI_L_CLKP 1 2 HDMI_CLKP 1 2 +3V3_SYS
RV640 5.6_0402_1%
390P_0402_50V7K
10U_0603_6.3V6M
0.1U_0201_6.3V6K
1.1A_6V_SPR-P110
1 1
1
HDMI_L_TX_N0 HDMI_TX_N0
CV67
@EMI@
CV1068
CV1069
1 EMI@ 2 1 2 @
RV643 5.6_0402_1% RV655
5.6_0201_1% 10K_0402_5%
2
2
CV1060 2 1 0.1U_0201_6.3V6K HDMI_C_TX_N0 RV27 2 2
<28> GPU_HDMI_TX_N0
RV501
2
150_0201_1%
CV1059 2 1 0.1U_0201_6.3V6K HDMI_C_TX_P0
<28> GPU_HDMI_TX_P0 @EMI@
5.6_0201_1%
1
RV28
1 EMI@ 2 HDMI_L_TX_P0 1 2 HDMI_TX_P0
RV646 5.6_0402_1%
JHDMI
1 EMI@ 2 HDMI_L_TX_N1 1 2 HDMI_TX_N1
RV642 5.6_0402_1% HDMI_TX_P2 1
5.6_0201_1% 2 D2+
D2_Shield
2
CV1062 2 1 0.1U_0201_6.3V6K HDMI_C_TX_N1 RV29 HDMI_TX_N2 3
<28> GPU_HDMI_TX_N1 HDMI_TX_P1 4 D2-
RV502
5 D1+
150_0201_1% D1_Shield
CV1061 2 1 0.1U_0201_6.3V6K HDMI_C_TX_P1 HDMI_TX_N1 6
<28> GPU_HDMI_TX_P1 @EMI@ HDMI_TX_P0 D1-
5.6_0201_1% 7
1
RV30 8 D0+
1 EMI@ 2 HDMI_L_TX_P1 1 2 HDMI_TX_P1 HDMI_TX_N0 9 D0_Shield
RV639 5.6_0402_1% HDMI_CLKP 10 D0-
11 CK+
HDMI_CLKN 12 CK_Shield
13 CK- 20
1 EMI@ 2 HDMI_L_TX_N2 1 2 HDMI_TX_N2 14 CEC GND 21
RV645 5.6_0402_1% HDMI_CTRL_CLK 15 Reserved GND 22
5.6_0201_1% HDMI_CTRL_DAT 16 SCL GND 23
SDA GND
2
CV1064 2 1 0.1U_0201_6.3V6K HDMI_C_TX_N2 RV33 17
<28> GPU_HDMI_TX_N2 18 DDC/CEC GND
RV503
HDMI_HPD 19 +5V
C 150_0201_1% HPD C
CV1063 2 1 0.1U_0201_6.3V6K HDMI_C_TX_P2
<28> GPU_HDMI_TX_P2 @EMI@
5.6_0201_1%
1
RV34 ACON_HMRF5-AK1L0C
1 EMI@ 2 HDMI_L_TX_P2 1 2 HDMI_TX_P2
CONN@
RV638 5.6_0402_1%
HDMI_C_TX_N0 RX31 1 2 499_0201_1% LX1 1 2 PBY100505T-601Y-N_2P

HDMI_C_TX_P0 RX32 1 2 499_0201_1% LX2 1 2 PBY100505T-601Y-N_2P
HDMI_C_CLKN RX33 1 2 499_0201_1% LX3 1 2 PBY100505T-601Y-N_2P
HDMI_C_CLKP RX34 1 2 499_0201_1% LX4 1 2 PBY100505T-601Y-N_2P

+3V3_SYS HDMI_Down
1
D
2 QX1
G BSS138_1N_SOT-23-3
1
S
3
RX1
100K_0402_5%
B B
2
+HDMI_5V_OUT
DGPU_PEX_RST#
RB751S-40_SOD523-2
RB751S-40_SOD523-2
2
+1V8_AON
DV12
DV13
+3VS
1
QX3
LMBT3904WT1G_SC70-3
1
C
1
+1V8_AON 2 1 2 HDMI_HPD
10K_0201_5%
10K_0201_5%
2
RV652
RV648
B
3.3K_0201_1%
3.3K_0201_1%
RV653
E RX6
RV649
3
150K_0201_5% 1
<18> HDMI_HPD_PCH
1
2
CX2
1
1
RX7 +1.8VALW 0.1U_0201_16V6K
CV1056
5
10K_0201_5% 2
1 2 RX8
2
4 3 HDMI_CTRL_CLK_R 2 1 HDMI_CTRL_CLK 10K_0201_5%
<28> GPU_HDMI_CTRL_CLK <30> GPU_HDMI_HPD#
0.1U_0201_16V6K
2
6
5
QV96B RV651
2
DMN53D0LDW-7 2N SOT363-6 33_0201_1% QV97A
VCC
DMN53D0LDW-7 2N SOT363-6 1
1 6 HDMI_CTRL_DAT_R 2 1 HDMI_CTRL_DAT 2 4 IN B
<28> GPU_HDMI_CTRL_DAT OUT Y 2 DGPU_PEX_RST#
GND
QV96A RV650 IN A DGPU_PEX_RST# <27,30,39>
1
DMN53D0LDW-7 2N SOT363-6 33_0201_1%
UX2
3
A A

HDMI
0.2
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

0.2
5 4 3 2 1
5 4 3 2 1
+3.3V_TBT_SX
+3.3V_TBT_FLASH_R +3.3V_TBT_LC
UT1A TBT_FORCE_PWR RT94 2 @ 1 10K_0201_5%
Y23 V23 PCIE_PRX_C_DTX_P17 0.22U_0201_6.3V 2 1 CT14 PM_SLP_S3#_TBT RT86 2 @ 1 10K_0201_5%
<14> PCIE_PTX_C_DRX_P17 PCIE_RX0_P PCIE_TX0_P PCIE_PRX_C_DTX_N17 PCIE_PRX_DTX_P17 <14> CLKREQ_PCIE#3_R
Y22 V22 0.22U_0201_6.3V 2 1 CT16 RT20 2 1 10K_0201_5%
<14> PCIE_PTX_C_DRX_N17 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_DTX_N17 <14> TDOCK_BATLOW#
RT41 1 2 0.01_0402_1% RT31 2 1 10K_0201_5%
T23 P23 PCIE_PRX_C_DTX_P18 0.22U_0201_6.3V 2 1 CT12 RTD3_CIO_PWR_EN_R RT36 2 RTD3@ 1 10K_0201_5%
<14> PCIE_PTX_C_DRX_P18 PCIE_RX1_P PCIE_TX1_P PCIE_PRX_C_DTX_N18 PCIE_PRX_DTX_P18 <14> DG_GPIO8
T22 P22 0.22U_0201_6.3V 2 1 CT2 RT30 2 1 10K_0201_5%
<14> PCIE_PTX_C_DRX_N18 PCIE_PRX_DTX_N18 <14>
PCIE TX
PCIE_RX1_N PCIE_TX1_N GPIO_0 RT21 1 @ 2 150K_0201_5%
PCIe GEN3
M23 K23 PCIE_PRX_C_DTX_P19 0.22U_0201_6.3V 2 1 CT109 GPIO_1 RT32 1 @ 2 150K_0201_5%
D <14> PCIE_PTX_C_DRX_P19 PCIE_RX2_P PCIE_TX2_P PCIE_PRX_C_DTX_N19 PCIE_PRX_DTX_P19 <14> GPIO_3 D
M22 K22 0.22U_0201_6.3V 2 1 CT108 RT33 1 @ 2 150K_0201_5%
<14> PCIE_PTX_C_DRX_N19 PCIE_RX2_N PCIE_TX2_N PCIE_PRX_DTX_N19 <14> TBT_PCIE_WAKE# RT34 2 1 10K_0201_5%
H23 F23 PCIE_PRX_C_DTX_P20 0.22U_0201_6.3V 2 1 CT111 TBT_RESET_N_EC RT74 2 @ 1 10K_0201_5%
<14> PCIE_PTX_C_DRX_P20 PCIE_RX3_P PCIE_TX3_P PCIE_PRX_C_DTX_N20 PCIE_PRX_DTX_P20 <14> TBT_RTD3_RST#
H22 F22 0.22U_0201_6.3V 2 1 CT110 RT81 2 RTD3@ 1 10K_0201_5%
<14> PCIE_PTX_C_DRX_N20 PCIE_RX3_N PCIE_TX3_N PCIE_PRX_DTX_N20 <14>
T4 TBT_RST#_R
CLK_PCIE_P3 V19 PERST#
<15> CLK_PCIE_P3
PCIE CLK
CLK_PCIE_N3 T19 REFCLK_100_IN_P N16 PCIE_RBIAS RT3 1 2 3.01K_0201_1%
<15> CLK_PCIE_N3 CLKREQ_PCIE#3_R REFCLK_100_IN_N PCIE_RBIAS PCIE_WAKE#_TR
2 1 Y6 Y2 RT10 1 RTD3@ 2 0_0201_5%
<15> CLKREQ_PCIE#3 PCIE_CLKREQ# PEWAKE# TBT_RTD3_WAKE# <17>
RT2 0_0201_5%
CT6 1 2 0.1U_0201_6.3V6K GPU_DPA_P0_R RT1457 1 @ 2 0_01005_5% GPU_DPA_P0_C AC7 AB21 RT186 1 @RTD3@2 0_0201_5% TBT_PCIE_WAKE# +3V_PCH
<28> GPU_DPA_P0 GPU_DPA_N0_R GPU_DPA_N0_C DPSNK1_ML0_P DPSRC_ML0_P TBT_PCIE_WAKE# <58>
CT7 1 2 0.1U_0201_6.3V6K RT1458 1 @ 2 0_01005_5% AB7 AC21
<28> GPU_DPA_N0 DPSNK1_ML0_N DPSRC_ML0_N TBT_CIO_PLUG_EVENT# RT723 2 1 10K_0201_5%
CT8 1 2 0.1U_0201_6.3V6K GPU_DPA_P1_R RT1459 1 @ 2 0_01005_5% GPU_DPA_P1_C AB9 AC19
<28> GPU_DPA_P1 GPU_DPA_N1_R GPU_DPA_N1_C DPSNK1_ML1_P DPSRC_ML1_P
CT9 1 2 0.1U_0201_6.3V6K RT1460 1 @ 2 0_01005_5% AC9 AB19
<28> GPU_DPA_N1 DPSNK1_ML1_N DPSRC_ML1_N
SOURCE PORT 0
CT10 1 2 0.1U_0201_6.3V6K GPU_DPA_P2_R RT1461 1 @ 2 0_01005_5% GPU_DPA_P2_C AC11 AB17
SINK PORT 1
<28> GPU_DPA_P2 GPU_DPA_N2_R GPU_DPA_N2_C DPSNK1_ML2_P DPSRC_ML2_P
CT23 1 2 0.1U_0201_6.3V6K RT1462 1 @ 2 0_01005_5% AB11 AC17
<28> GPU_DPA_N2
GPU IFPA
DPSNK1_ML2_N DPSRC_ML2_N
CT11 1 2 0.1U_0201_6.3V6K GPU_DPA_P3_R RT1463 1 @ 2 0_01005_5% GPU_DPA_P3_C AB13 AC15 PCIE_WAKE#_TR RT40 2 @RTD3@1 1M_0201_1%
<28> GPU_DPA_P3 GPU_DPA_N3_R GPU_DPA_N3_C DPSNK1_ML3_P DPSRC_ML3_P TBT_FORCE_PWR
CT24 1 2 0.1U_0201_6.3V6K RT1464 1 @ 2 0_01005_5% AC13 AB15 RT35 1 2 100K_0201_5%
<28> GPU_DPA_N3 DPSNK1_ML3_N DPSRC_ML3_N DG_GPIO8 RT47 1 @ 2 150K_0201_5%
CT25 1 2 0.1U_0201_6.3V6K GPU_DPA_AUXP_R RT1465 1 @ 2 0_01005_5% GPU_DPA_AUXP_C N1 N4 TBT_RESET_N_EC RT80 1 2 100K_0201_5%
<28> GPU_DPA_AUXP CT26 1 2 0.1U_0201_6.3V6K GPU_DPA_AUXN_R RT1466 1 @ 2 0_01005_5% GPU_DPA_AUXN_C N2 DPSNK1_AUX_P DPSRC_AUX_P N5 TBTA_HPD RT45 1 2 100K_0201_5%
<28> GPU_DPA_AUXN DPSNK1_AUX_N DPSRC_AUX_N RTD3_USB_PWR_EN_R RT37 1 2 100K_0201_5%
RT200 1 2 0_0201_5% GPU_DPA_HPD_R AA2 GPIO_0 RT46 1 2 150K_0201_5%
<30> GPU_DPA_HPD DPSNK1_HPD TBT_SRC_HPD GPIO_1
R5 RT4 1 2 1M_0201_1% RT28 1 2 150K_0201_5%
DPSRC_HPD GPIO_3 RT29 1 2 150K_0201_5%

VIPER - N18E LA-J521PR02 - X01 - Final

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A B C D E

Layout Dell logo

PCB 2VR LA-J521P REV0 M/B NVIDIA N18E S

(Viper Comet Lake H with nVIDIA N18E)

Security Classification Compal Secret Data Compal Electronics, Inc.

P.40 IFPC PEGx8

P.50 Port 4~7 P.6-13

G-Sensor USB3.1 por5

P.73 Kill 1650W SIP

SSD2 M.2 Key-M 2280 PCIEx4

SSD1 M.2 Key-M 2280 SATAx1/PCIEx4

3V/5V Charger Touch pad KC3810

Security Classification Compal Secret Data Compal Electronics, Inc.

Board ID Table for AD channel

Date: Tuesday, September 24, 2019 Sheet 3 of 114

8880mA (PJP200 PJP201) APE8937GN2

PCH_PW R_EN TPS51212DSCR 9410mA (PJP300 PJP302) SYSON TPS22961

RM34 +3VS_WLAN_NGFF NGFF Conn.

PCH_ENVDD JEDP Conn.

(PJP1301) SY8003DFC (PJP1300)

SYSON TPS22961DNYR +VCCST

SYSON 8 +1.2VP BH29

SUSP# AOZ1331 +3VS

SUSP# SY8286RAC +NVVDD2 G5

for power down sequence VR_PWRGD

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

RC9 1 2 1.5K_0201_5% XDP_SPI_SI

2 1 51_0201_5% XDP_TCK <9> CFG17 T292 PAD~D @

<9> CFG19 T302 PAD~D @

<9,20> XDP_PREQ# T304 PAD~D @

<15> XDP_SPI_SI T306 PAD~D @

XDP_SPI_IO2 RC354 1 @ 2 1K_0201_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

RH156 1 @ 2 51_0201_5% XDP_PREQ# B31 BN25

CFG6 1 2 RH489,RH493 close to UH4

RH493 1 2 2.2K_0201_5% PCH_SYS_PWROK_XDP

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

RH494 1 @ 2 51_0201_5% XDP_TMS

RH496 1 CMC@ 2 51_0201_5% XDP_TDO

Security Classification Compal Secret Data Compal Electronics, Inc.

UC1M K14 W35

Security Classification Compal Secret Data Compal Electronics, Inc.

+VCCIO +VCCSTG +VCCST

VCCPLL_OC is allowed to be turned off

during S3 and DS3 if it is not powered directly from VDDQ

J17 VCCIO15 VCCPLL2 2 2 2 2 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils

3. RC1, RC2 should be placed within 2 inches (50.8 mm) of CPU

Security Classification Compal Secret Data Compal Electronics, Inc.

FHSSKU_MBL QS64 A0 FCBGA 874P S

@ This signal has a weak internal Pull-down.

Security Classification Compal Secret Data Compal Electronics, Inc.

+3V_PCH 1.5K_0201_5% 1 2 RH1 PCH_SPI_0_D0

RH75 1 2 100K_0201_5% PCH_SPI_0_D2 UH1A

RH78 1 2 100K_0201_5% PCH_SPI_0_D3 BE36 AV29 PCH_PLTRST#