Q3ZMC La-8481p R1a - 0412

A B C D E
fix
ina
v Compal Confidential
Model Name : Q3ZMC
File Name : LA-8481P
1 1
Compal Confidential
2 2
Q3ZMC UMA M/B Schematics Document

Intel Ivy/Sandy Bridge SFF BGA 1023p Processor
/Panther Point 989p PCH
/ DDR3L Memory Down *8
3 2012-04-11 3
REV:1.0(MP SMT)
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

2012/4/6 2013/4/6 Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Q3ZMC M/B LA-8481P Schematic
http://vinafix.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 12, 2012 Sheet 1 of 51
A B C D E
A B C D E
f ix
ina
PCB
v
ZZZ1
LA-8481P
DAZ0NS00100
1
DDR3L-ON BOARD 1
Memory BUS(DDR3L)
Fan Control eDP Conn. Intel
page 34 Two Channel
page 22 Ivy Bridge ULV
1.35V DDR3L 1333Mhz
eDP 120MHz Processor
BGA1023 page 11,12
page 4~10
FDI x8 DMI x4 USB 3.0 conn x2 Debug Port Camera Bluetooth mSATA
USB3.0 port 1,2 (Reserve)
Thunderbolt HDMI Conn. USB2.0 port 0,1 USB port 9 USB port 10 USB port 8 USB port 12
100MHz 100MHz
page 31 page 31 page 22 page 28 page 28
page 24~27 page 23 2.7GT/s 1GB/s x4
USBx14 3.3V 48MHz

2
Intel 2
TMDS HD Audio 3.3V 24MHz
DP Panther Point-M
PCH SPI D/B
PCI-Express x 8 (PCIE2.0 5GT/s) 100MHz HDA Codec
989pin BGA ALC271X-VB6/ALC281X
port 5~8 port 2 port 1 100MHz page 32
page 13~21 LPC
Thunderbolt WLAN Card reader SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
page 22 port 0 TPM SPI ROM x2 Int. Speaker x 2 Int. DMIC x 1 Phone Jack x 1
page 24~27 page 28
page 30 page 13
page 32 page 32 page 32
mSATA
LPC BUS
page 29
3 3
33MHz
ENE
KB930/KB9012
page 33
RTC CKT. LS-8481P Audio/B

page 13 page 32
Touch Pad Int.KBD
page 33 page 33
Power On/Off CKT. LS-8482P Card Reader/B

page 33 page 22
EC ROM x1
DC/DC Interface CKT. LS-8483P LED/B @ for page
KB93033
page 35 page 32
4 4
Power Circuit DC/DC LS-8484P Battery/B

page 36~45
2012/4/6 2013/4/6 Title
Issued Date Deciphered Date Block Diagrams
Custom 1.0
http://vinafix.vn
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Voltage Rails
v Power Plane
VIN
Description
Adapter power supply (19V)
S1
N/A
S3
N/A
S5
N/A
STATE
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
BATT+ Battery power supply (12.6V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON
B+ AC or battery power rail for power circuit. N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON*
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+1.05VS_VTT +1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU ON OFF OFF
+1.05VS_PCH +1.05VS_VTT to +1.05VS_PCH power for PCH ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.35V +1.35VP to +1.35V power rail for DDR3L ON ON OFF
+1.35VS +1.35V to +1.35VS switched power rail ON OFF OFF
+0.675VS +0.675VSP to +0.675VS switched power rail for DDR3L terminator ON OFF OFF Board ID / SKU ID Table for AD channel
+1.5VS +1.5VSP to +1.5VS power rail for PCH ON OFF OFF Vcc 3.3V +/- 5%
+1.8VS +3VALW to 1.8VS switched power rail for PCH ON OFF OFF Ra/Rc/Re 100K +/- 5%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VALW +3VALWP to +3VALW always on power rail ON ON ON* 0 0 0 V 0 V 0 V
+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Resistor) ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VS +3VALW to +3VS power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VALW +5VALWP to +5VALW always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VS +5VALW to +5VS switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
2 2
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+RTCVCC RTC power ON ON ON 7 NC 2.500 V 3.300 V 3.300 V
BOARD ID Table BTO Option Table

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BTO Item BOM Structure
Board ID PCB Revision
Unpop @
0 0.1,0.2
EC SM Bus1 address EC SM Bus2 address Connector CONN@
1 0.3 DVT:unknown MCU+MKS Motor,With TB IC
UMA UMA@
2 0.4 PVT1:PADAUK MCU+MKS Motor,Without TB IC
Device Address Device Address CPU IVB@
3 0.4 PVT2:PADAUK MCU+MKS Motor,With TB IC
Smart Battery 0001 011X b PCH HM77@
4 1.0
PCH SM Bus address DDR3 DDR3@
5
DDR3L DDR3L@
6
Device Address On Board DRAM X76@
ChannelA
7
A0 1010 000X 128bit RAM 128@
ChannelB A4 1010 010X eDP eDP@
3 LVDS LVDS@ 3
USB Port Table

BOM Config 2 External
USB 2.0 USB 1.1 Port USB Port
4319HNBOL01:UMA@/DDR3L@/eDP@/USB3.0@/9012@/TB@/IVB@/HM77@/DS3@/TXM@/TPM@/128@/
4319HNBOL02:UMA@/DDR3L@/eDP@/USB3.0@/9012@/TB@/IVB@/HM77@/DS3@/TXM@/TPM@ USB2.0 Conn USB2.0@
0 USB port (Rear side 3.0)
UHCI0 USB3.0 Conn USB3.0@
1 USB port (Rear side 3.0)
Thunderbolt TB@
2
UHCI1
3
EHCI1 KB930 930@
4
UHCI2 KB9012 9012@
5
6
UHCI3 Normal S3 S3@
7
Deep S3 DS3@
8
UHCI4
9 Debug Port
TPM+TCM TXM@
10 Camera
EHCI2 UHCI5 TPM TPM@
11
4 TCM TCM@ 4
12 mSATA(Reserve)
UHCI6
13 BlueTooth

2012/4/6 2013/4/6 Title
Issued Date Deciphered Date Notes List
Custom 1.0
http://vinafix.vn
A B C D E
A B C D E
fix
vina +1.05VS_VTT
PEG_ICOMPI and RCOMPO signals should be shorted and routed
with - max length = 500 mils - typical impedance = 43 mohms
1
R532
24.9_0402_1%
PEG_ICOMPO signals should be routed with - max length = 500 mils-
UCPU1A
typical impedance = 14.5 mohms
2
1 G3 PEG_COMP 1
PEG_ICOMPI G1
M2 PEG_ICOMPO G4
<15> DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO G3,W=4mil,S=15mil,L=500mil
<15> DMI_CRX_PTX_N1 P6 G1,W=12mil,S=15mil,L=500mil
P1 DMI_RX#[1]
<15> DMI_CRX_PTX_N2 DMI_RX#[2] G4,W=4mil,S=15mil,L=500mil
<15> DMI_CRX_PTX_N3 P10 H22
DMI_RX#[3] PEG_RX#[0] J21
N3 PEG_RX#[1] B22
UMA only=>PEG NC
<15> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2]
<15> DMI_CRX_PTX_P1 P7 D21
DMI_RX[1] PEG_RX#[3]
DMI
<15> DMI_CRX_PTX_P2 P3 A19
P11 DMI_RX[2] PEG_RX#[4] D17
<15> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] B14
K1 PEG_RX#[6] D13
<15> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7]
M8 A11
N4 B10
R2 G8
<15> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] A8
K3 PEG_RX#[11] B6
<15> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12]
M7 H8
P4 E5
T3 K7
K22
PEG_RX[0] K19
PEG_RX[1] C21
U7 PEG_RX[2] D19
<15> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
W11 C19
W1 D16
AA6 C13
2 W6 D12 2
V4 C11
PCI EXPRESS -- GRAPHICS

Y2 C9
AC9 F8
Intel(R) FDI
C8
PEG_RX[11] C5
U6 PEG_RX[12] H6
<15> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
W10 F6
W3 K6
AA7
<15> FDI_CTX_PRX_P3 FDI0_TX[3]
W7 G22
<15> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
T4 C23
AA3 D23
AC8 F21
<15> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] H19
+1.05VS_VTT AA11 PEG_TX#[4] C17
<15> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
eDP_COMPIO and ICOMPO signals <15> FDI_FSYNC1 AC12 K15
FDI1_FSYNC PEG_TX#[6] F17
should be shorted near balls and U11 PEG_TX#[7] F14
<15> FDI_INT FDI_INT PEG_TX#[8]
routed with typical impedance PEG_TX#[9]
A15
1
AA10 J14
<25 mohms R118
<15> FDI_LSYNC0
AG8 FDI0_LSYNC PEG_TX#[10] H13
<15> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
should not be left floating 24.9_0402_1% M10
PEG_TX#[12] F10
,even if disable eDP function... PEG_TX#[13] D9
2
PEG_TX#[14] J4
W=4mil,S=15mil,L=500mil PEG_TX#[15]
EDP_COMP AF3
AD2 eDP_COMPIO F22
W=12mil,S=15mil,L=500mil eDP_ICOMPO PEG_TX[0]
EDP_HPD# AG11 A23
3 eDP_HPD# PEG_TX[1] D24 3
PEG_TX[2] E21
AG4 PEG_TX[3] G19
<22> EDP_AUXN eDP_AUX# PEG_TX[4]
AF4 B18
Add eDP circuit <22> EDP_AUXP eDP_AUX PEG_TX[5] K17
PEG_TX[6]
eDP
G17
+1.05VS_VTT AC3 PEG_TX[7] E14
<22> EDP_TXN0 eDP_TX#[0] PEG_TX[8]
AC4 C15
<22> EDP_TXN1 eDP_TX#[1] PEG_TX[9]
AE11 K13
eDP_TX#[2] PEG_TX[10]
1
AE7 G13
R809 eDP_TX#[3] PEG_TX[11] K10
eDP@ 1K_0402_5% AC1 PEG_TX[12] G10
<22> EDP_TXP0 eDP_TX[0] PEG_TX[13]
AA4 D8
<22> EDP_TXP1 eDP_TX[1] PEG_TX[14]
AE10 K4
2
AE6 eDP_TX[2] PEG_TX[15]

EDP_HPD# eDP_TX[3]
<22> EDP_HPD#
IVY-BRIDGE_BGA1023
IVB@
ULV type P/N:

1.SA00005B000:S IC AV8063801057400 QBP7 K0 1.7G BGA
2.SA00005AZ30:S IC AV8063801057401 QBTP K0 1.5G BGA
4 4

2012/4/6 2013/4/6 Title
Issued Date Deciphered Date PROCESSOR(1/7) DMI,FDI,PEG
Custom 1.0
http://vinafix.vn
A B C D E
A B C D E
f ix
v ina
1 1
UCPU1B
2 2
PROC_SELECT# J3
非外外外
PCH->CPU Future platforms,PH VCPLL and connect to PCH DF_TVS BCLK H2 CLK_CPU_DMI <14>
UNCOREPWRGOOD: CORE OK BCLK# CLK_CPU_DMI# <14> +1.05VS_VTT
MISC
CLOCKS
F49
都後後做
SM_DRAMPWROK:DRAM power ok <17> H_SNB_IVB# PROC_SELECT# AG3 CLK_CPU_DPLL CLK_CPU_DPLL# R116 2 @ 1 1K_0402_5%
DPLL_REF_CLK CLK_CPU_DPLL <14>
RESET#: ok CPU reset AG1 CLK_CPU_DPLL#
偵偵CPU有有有有
C57 DPLL_REF_CLK# CLK_CPU_DPLL# <14>
CLK_CPU_DPLL R117 2 @ 1 1K_0402_5%
PROC_DETECT#
Follow DG 1.2 & CRB1.0 Checklist1.0 P.64 Processor Graphis Disable Guide
XBOX 三三三三
@
T1 PAD H_CATERR# C49 DIS only SKU or UMA eDP disable
CATERR#
DPLL_REF_SSCLK PD 1K_5% to GND
THERMAL
C784 2 1 0.1U_0402_10V7K H_CPUPWRGD DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT
@ Processor Pullups follow CRB1.0 H_PECI A48 AT30 SM_DRAMRST#
<18,32> H_PECI PECI SM_DRAMRST# SM_DRAMRST# <6>
R223 2 1 10K_0402_5% H_CPUPWRGD R220 2 1 62_0402_5% R216
+1.05VS_VTT
56_0402_5% BF44 SM_RCOMP0 R149 2 1 140_0402_1%
SM_RCOMP[0]
DDR3
MISC
H_PROCHOT# 1 2 H_PROCHOT#_R C45 BE43 SM_RCOMP1 R486 2 1 25.5_0402_1%
<32> H_PROCHOT# PROCHOT# SM_RCOMP[1] BG43 SM_RCOMP2 R484 2 1 200_0402_1%
SM_RCOMP[2]
D45 DDR3 Compensation Signals

<18> H_THRMTRIP# THERMTRIP#
Trace:10mil ,Spacing:13mil, Max.Length:500mil
Follow DG 1.2 & CRB1.0 Use open drain MOS: N53
Buffered reset to CPU +1.05VS_VTT PH pop 75ohm PRDY# N55
PREQ#
+3VS series resister pop 43ohm L56 XDP_TCK @ PAD T2
TCK L55 XDP_TMS @ PAD T3
+1.05VS_VTT TMS
PWR MANAGEMENT
3 J58 XDP_TRST# @ PAD T4 3
TRST#
1
JTAG & BPM

C396 C48 M60 XDP_TDI @ PAD T5
<15> H_PM_SYNC PM_SYNC TDI
1
0.1U_0201_10V6K L59 XDP_TDO @ PAD T6

R226 @ R80 TDO
2 75_0402_5% 0_0402_5% +3VS
1 2 H_CPUPWRGD_R B46
<18> H_CPUPWRGD UNCOREPWRGOOD
5
除除CPU_CORE以以以以OK
U15 R227 K58 XDP_DBRESET# XDP_DBRESET# R569 2 1 1K_0402_5%
XDP_DBRESET# <15>
2
1 43_0402_1% DBR#
UNCOREPWRGOOD:
P
NC 4 BUFO_CPU_RST# 1 2 BUF_CPU_RST#
2 Y PM_DRAM_PWRGD_R BE45 G58 1 2
CRB1.0 PH 1K +3VS
<17,22,24,30,32> PLT_RST# A SM_DRAMPWROK BPM#[0] Check list 1.0 PH 5K +3VS
G
E55
@ BPM#[1] E59 C102
SM_DRAMPWROK:DRAM power ok Check list 1.2 PH 10K +3VS
3
SN74LVC1G07DCKR_SC70-5 R225 BPM#[2] G55 100P_0201_25V8J

0_0402_5% BPM#[3] G59 Debug port DG1.1-1.2 50~5K ohm
都ok後後CPU做reset
BUF_CPU_RST# D44 BPM#[4] H60
For EMI
2
RESET# BPM#[5] J59

RESET#: BPM#[6] J61
BPM#[7]
Follow DG 1.2 & CRB1.0 +3VALW
Use open drain MOS:
+1.35VS +1.35VS PH pop 200ohm
C101
1 series resister pop 130ohm IVY-BRIDGE_BGA1023
1
0.1U_0402_16V4Z IVB@
R88
2 200_0402_5%
2
5
U5
2
P
4 <15> SYS_PWROK B 4
4 PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R
1 Y R97 130_0402_5%
<15> PM_DRAM_PWRGD A
G
MC74VHC1G09DFT2G_SC70-5 R829 PM_DRAM_PWRGD

3
39_0402_5%
@ 1
2
C787
100P_0201_25V8J 2012/4/6 2013/4/6 Title
Issued Date Deciphered Date PROCESSOR(2/7) PM,XDP,CLK
1
D Q74 2
SUSP 2 SSM3K7002FU_SC70-3
<35,40> SUSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
G @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
S Custom 1.0
3
http://vinafix.vn
A B C D E
A B C D E
fix
vina
UCPU1C UCPU1D
<11> DDR_A_D[0..63] <12> DDR_B_D[0..63]
DDR_A_D0 AG6 DDR_B_D0 AL4
DDR_A_D1 AJ6 SA_DQ[0] AU36 DDR_B_D1 AL1 SB_DQ[0] BA34
DDR_A_D2 AP11 SA_DQ[1] SA_CK[0] AV36 DDR_A_CLK0 <11> DDR_B_D2 AN3 SB_DQ[1] SB_CK[0] AY34 DDR_B_CLK0 <12>
DDR_A_D3 AL6 SA_DQ[2] SA_CK#[0] AY26 DDR_A_CLK0# <11> DDR_B_D3 AR4 SB_DQ[2] SB_CK#[0] AR22 DDR_B_CLK0# <12>
AJ10 SA_DQ[3] SA_CKE[0] DDR_A_CKE0 <11> AK4 SB_DQ[3] SB_CKE[0] DDR_B_CKE0 <12>
DDR_A_D4 DDR_B_D4
1 DDR_A_D5 AJ8 SA_DQ[4] DDR_B_D5 AK3 SB_DQ[4] 1
DDR_A_D6 AL8 SA_DQ[5] DDR_B_D6 AN4 SB_DQ[5]
DDR_A_D7 AL7 SA_DQ[6] DDR_B_D7 AR1 SB_DQ[6]
SA_DQ[7] SB_DQ[7]
1
DDR_A_D8 AR11 DDR_B_D8 AU4
DDR_A_D9 AP6 SA_DQ[8] AT40 DDR_A_CLK1 R263 DDR_B_D9 AT2 SB_DQ[8] BA36 DDR_B_CLK1 R264
DDR_A_D10 AU6 SA_DQ[9] SA_CK[1] AU40 DDR_A_CLK1# 75_0402_1% DDR_B_D10 AV4 SB_DQ[9] SB_CK[1] BB36 DDR_B_CLK1# 75_0402_1%
DDR_A_D11 AV9 SA_DQ[10] SA_CK#[1] BB26 DDR_B_D11 BA4 SB_DQ[10] SB_CK#[1] BF27
DDR_A_D12 AR6 SA_DQ[11] SA_CKE[1] DDR_B_D12 AU3 SB_DQ[11] SB_CKE[1]
2
DDR_A_D13 AP8 SA_DQ[12] DDR_B_D13 AR3 SB_DQ[12]
DDR_A_D14 AT13 SA_DQ[13] DDR_B_D14 AY2 SB_DQ[13]
DDR_A_D15 AU13 SA_DQ[14] DDR_B_D15 BA3 SB_DQ[14]
DDR_A_D16 BC7 SA_DQ[15] DDR_B_D16 BE9 SB_DQ[15]
DDR_A_D17 BB7 SA_DQ[16] BB40 DDR_B_D17 BD9 SB_DQ[16] BE41
BA13 SA_DQ[17] SA_CS#[0] BC41 DDR_A_CS0# <11> BD13 SB_DQ[17] SB_CS#[0] BE47 DDR_B_CS0# <12>
DDR_A_D18 DDR_B_D18
DDR_A_D19 BB11 SA_DQ[18] SA_CS#[1] DDR_B_D19 BF12 SB_DQ[18] SB_CS#[1]
DDR_A_D20 BA7 SA_DQ[19] DDR_B_D20 BF8 SB_DQ[19]
DDR_A_D21 BA9 SA_DQ[20] DDR_B_D21 BD10 SB_DQ[20]
DDR_A_D22 BB9 SA_DQ[21] DDR_B_D22 BD14 SB_DQ[21]
DDR_A_D23 AY13 SA_DQ[22] DDR_B_D23 BE13 SB_DQ[22]
DDR_A_D24 AV14 SA_DQ[23] AY40 DDR_B_D24 BF16 SB_DQ[23] AT43
AR14 SA_DQ[24] SA_ODT[0] BA41 DDR_A_ODT0 <11> BE17 SB_DQ[24] SB_ODT[0] BG47 DDR_B_ODT0 <12>
DDR_A_D25 DDR_B_D25
DDR_A_D26 AY17 SA_DQ[25] SA_ODT[1] DDR_B_D26 BE18 SB_DQ[25] SB_ODT[1]
DDR_A_D27 AR19 SA_DQ[26] DDR_B_D27 BE21 SB_DQ[26]
DDR_A_D28 BA14 SA_DQ[27] DDR_B_D28 BE14 SB_DQ[27]
DDR_A_D29 AU14 SA_DQ[28] DDR_B_D29 BG14 SB_DQ[28]
DDR_A_D30 BB14 SA_DQ[29] DDR_B_D30 BG18 SB_DQ[29]
DDR_A_D31 BB17 SA_DQ[30] AL11 DDR_A_DQS#0 DDR_A_DQS#[0..7] <11> DDR_B_D31 BF19 SB_DQ[30] AL3 DDR_B_DQS#0 DDR_B_DQS#[0..7] <12>
DDR_A_D32 BA45 SA_DQ[31] SA_DQS#[0] AR8 DDR_A_DQS#1 DDR_B_D32 BD50 SB_DQ[31] SB_DQS#[0] AV3 DDR_B_DQS#1
DDR_A_D33 AR43 SA_DQ[32] SA_DQS#[1] AV11 DDR_A_DQS#2 DDR_B_D33 BF48 SB_DQ[32] SB_DQS#[1] BG11 DDR_B_DQS#2
DDR_A_D34 AW48 SA_DQ[33] SA_DQS#[2] AT17 DDR_A_DQS#3 DDR_B_D34 BD53 SB_DQ[33] SB_DQS#[2] BD17 DDR_B_DQS#3
DDR_A_D35 BC48 SA_DQ[34] SA_DQS#[3] AV45 DDR_A_DQS#4 DDR_B_D35 BF52 SB_DQ[34] SB_DQS#[3] BG51 DDR_B_DQS#4
DDR_A_D36 BC45 SA_DQ[35] SA_DQS#[4] AY51 DDR_A_DQS#5 DDR_B_D36 BD49 SB_DQ[35] SB_DQS#[4] BA59 DDR_B_DQS#5
2 DDR_A_D37 AR45 SA_DQ[36] SA_DQS#[5] AT55 DDR_A_DQS#6 DDR_B_D37 BE49 SB_DQ[36] SB_DQS#[5] AT60 DDR_B_DQS#6 2
DDR SYSTEM MEMORY A

SA_DQ[37] SA_DQS#[6] SB_DQ[37] SB_DQS#[6]
DDR SYSTEM MEMORY B

DDR_A_D38 AT48 AK55 DDR_A_DQS#7 DDR_B_D38 BD54 AK59 DDR_B_DQS#7
DDR_A_D39 AY48 SA_DQ[38] SA_DQS#[7] DDR_B_D39 BE53 SB_DQ[38] SB_DQS#[7]
DDR_A_D40 BA49 SA_DQ[39] DDR_B_D40 BF56 SB_DQ[39]
DDR_A_D41 AV49 SA_DQ[40] DDR_B_D41 BE57 SB_DQ[40]
DDR_A_D42 BB51 SA_DQ[41] DDR_B_D42 BC59 SB_DQ[41]
DDR_A_D43 AY53 SA_DQ[42] DDR_B_D43 AY60 SB_DQ[42]
DDR_A_D44 BB49 SA_DQ[43] DDR_B_D44 BE54 SB_DQ[43]
DDR_A_D45 AU49 SA_DQ[44] AJ11 DDR_A_DQS0 DDR_A_DQS[0..7] <11> DDR_B_D45 BG54 SB_DQ[44]
DDR_A_D46 BA53 SA_DQ[45] SA_DQS[0] AR10 DDR_A_DQS1 DDR_B_D46 BA58 SB_DQ[45] AM2 DDR_B_DQS0 DDR_B_DQS[0..7] <12>
DDR_A_D47 BB55 SA_DQ[46] SA_DQS[1] AY11 DDR_A_DQS2 DDR_B_D47 AW59 SB_DQ[46] SB_DQS[0] AV1 DDR_B_DQS1
DDR_A_D48 BA55 SA_DQ[47] SA_DQS[2] AU17 DDR_A_DQS3 DDR_B_D48 AW58 SB_DQ[47] SB_DQS[1] BE11 DDR_B_DQS2
DDR_A_D49 AV56 SA_DQ[48] SA_DQS[3] AW45 DDR_A_DQS4 DDR_B_D49 AU58 SB_DQ[48] SB_DQS[2] BD18 DDR_B_DQS3
DDR_A_D50 AP50 SA_DQ[49] SA_DQS[4] AV51 DDR_A_DQS5 DDR_B_D50 AN61 SB_DQ[49] SB_DQS[3] BE51 DDR_B_DQS4
DDR_A_D51 AP53 SA_DQ[50] SA_DQS[5] AT56 DDR_A_DQS6 DDR_B_D51 AN59 SB_DQ[50] SB_DQS[4] BA61 DDR_B_DQS5
DDR_A_D52 AV54 SA_DQ[51] SA_DQS[6] AK54 DDR_A_DQS7 DDR_B_D52 AU59 SB_DQ[51] SB_DQS[5] AR59 DDR_B_DQS6
DDR_A_D53 AT54 SA_DQ[52] SA_DQS[7] DDR_B_D53 AU61 SB_DQ[52] SB_DQS[6] AK61 DDR_B_DQS7
DDR_A_D54 AP56 SA_DQ[53] DDR_B_D54 AN58 SB_DQ[53] SB_DQS[7]
DDR_A_D55 AP52 SA_DQ[54] DDR_B_D55 AR58 SB_DQ[54]
DDR_A_D56 AN57 SA_DQ[55] DDR_B_D56 AK58 SB_DQ[55]
DDR_A_D57 AN53 SA_DQ[56] DDR_B_D57 AL58 SB_DQ[56]
DDR_A_D58 AG56 SA_DQ[57] DDR_B_D58 AG58 SB_DQ[57]
DDR_A_D59 AG53 SA_DQ[58] DDR_B_D59 AG59 SB_DQ[58]
DDR_A_D60 AN55 SA_DQ[59] DDR_B_D60 AM60 SB_DQ[59]
DDR_A_D61 AN52 SA_DQ[60] BG35 DDR_A_MA0 DDR_A_MA[0..15] <11> DDR_B_D61 AL59 SB_DQ[60] BF32 DDR_B_MA0 DDR_B_MA[0..15] <12>
DDR_A_D62 AG55 SA_DQ[61] SA_MA[0] BB34 DDR_A_MA1 DDR_B_D62 AF61 SB_DQ[61] SB_MA[0] BE33 DDR_B_MA1
DDR_A_D63 AK56 SA_DQ[62] SA_MA[1] BE35 DDR_A_MA2 DDR_B_D63 AH60 SB_DQ[62] SB_MA[1] BD33 DDR_B_MA2
SA_DQ[63] SA_MA[2] BD35 DDR_A_MA3 SB_DQ[63] SB_MA[2] AU30 DDR_B_MA3
SA_MA[3] AT34 DDR_A_MA4 SB_MA[3] BD30 DDR_B_MA4
SA_MA[4] AU34 DDR_A_MA5 SB_MA[4] AV30 DDR_B_MA5
SA_MA[5] BB32 DDR_A_MA6 SB_MA[5] BG30 DDR_B_MA6
BD37 SA_MA[6] AT32 DDR_A_MA7 BG39 SB_MA[6] BD29 DDR_B_MA7
3 <11> DDR_A_BS0 BF36 SA_BS[0] SA_MA[7] AY32 <12> DDR_B_BS0 BD42 SB_BS[0] SB_MA[7] BE30 3
DDR_A_MA8 DDR_B_MA8
<11> DDR_A_BS1 BA28 SA_BS[1] SA_MA[8] AV32 <12> DDR_B_BS1 AT22 SB_BS[1] SB_MA[8] BE28
DDR_A_MA9 DDR_B_MA9
<11> DDR_A_BS2 SA_BS[2] SA_MA[9] BE37 DDR_A_MA10 <12> DDR_B_BS2 SB_BS[2] SB_MA[9] BD43 DDR_B_MA10
SA_MA[10] BA30 DDR_A_MA11 SB_MA[10] AT28 DDR_B_MA11
SA_MA[11] BC30 DDR_A_MA12 SB_MA[11] AV28 DDR_B_MA12
BE39 SA_MA[12] AW41 DDR_A_MA13 AV43 SB_MA[12] BD46 DDR_B_MA13
<11> DDR_A_CAS# BD39 SA_CAS# SA_MA[13] AY28 <12> DDR_B_CAS# BF40 SB_CAS# SB_MA[13] AT26
DDR_A_MA14 DDR_B_MA14
<11> DDR_A_RAS# AT41 SA_RAS# SA_MA[14] AU26 DDR_A_MA15 <12> DDR_B_RAS# BD45 SB_RAS# SB_MA[14] AU22 DDR_B_MA15
<11> DDR_A_WE# SA_WE# SA_MA[15] <12> DDR_B_WE# SB_WE# SB_MA[15]
Address 0~13:For 128*16

IVY-BRIDGE_BGA1023 IVY-BRIDGE_BGA1023 Address 0~14:For 256*16
IVB@ IVB@
Address 0~15:For 512*16
Follow CRB1.0 +1.35V
1
R78
CPU 通通DIMM做reset 0_0402_5%

1 @ 2
R66
1K_0402_5%
R63
2
1K_0402_5% DIMM_DRAMRST# SM_DRAMRST#

3 1 1 2
S
<5> SM_DRAMRST# SM_DRAMRST# DIMM_DRAMRST#_R

DIMM_DRAMRST# <11,12>
1 1 1
2
Q6
R79 BSS138-G_SOT23-3 S0 C785 C786 C788
G
2
4.99K_0402_1% 100P_0201_25V8J 100P_0402_50V8J 100P_0402_50V8J

DRAMRST_CNTRL_PCH hgih ,MOS ON 2 2 2
SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH
1
4 Dimm not reset 4
R418 1 2 0_0402_5%
S3
<11,12,14> DRAMRST_CNTRL_PCH
DRAMRST_CNTRL_PCH Low ,MOS OFF
<32> DRAMRST_CNTRL_EC R413 1 DS3@ 2 0_0402_5%
SM_DRAMRST# Low,DDR3 DRAMRST# HIGH
2
Dimm not reset

1
@ S4,S5
C78 R416 2012/4/6 2013/4/6 Title
.047U_0402_16V7K
2
0_0402_5% DRAMRST_CNTRL_PCH Low ,MOS OFF Issued Date Deciphered Date PROCESSOR(3/7) DDRIII
SM_DRAMRST# Low,DDR3 DRAMRST# Low
1
Dimm reset Custom 1.0
http://vinafix.vn
A B C D E
A B C D E
fix Default "1",EDS R1.0 P.88
ina
CFG Straps for Processor
v UCPU1E PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane # definition matches
T72 PAD @ CFG0 B50 N59 CFG2 socket pin map definition
C51 CFG[0] BCLK_ITP N58
CFG2 B54 CFG[1] BCLK_ITP#
0:Lane Reversed
+CPU_CORE CFG4
D53
A51
C53
CFG[2]
CFG[3]
CFG[4] RSVD30
N42
L42
*
CFG5
1 CFG6 C55 CFG[5] RSVD31 L45 CFG2 1
CFG[6] RSVD32
2
CFG7 H49 L47

CFG[7] RSVD33
1
R810 A55
@ H51 CFG[8]
49.9_0402_1% K49 CFG[9] M13 R234
K53 CFG[10] RSVD34 M14 1K_0402_1%
1
VCC_VAL_SENSE F53 CFG[11] RSVD35 U14
2
G53 CFG[12] RSVD36 W14
VSS_VAL_SENSE L51 CFG[13] RSVD37 P13
F51 CFG[14] RSVD38
CFG[15]
2
D52
R812 L53 CFG[16] AT49
@ CFG[17] RSVD39 K24
RSVD40 eDP enable
49.9_0402_1%
VCC_VAL_SENSE H43
RESERVED
1
VSS_VAL_SENSE K43 VCC_VAL_SENSE AH2 1:Disable

H45
VSS_VAL_SENSE RSVD41
RSVD42
RSVD43
AG13
AM14
AM15
CFG4 * 0:Enable
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE K45 VAXG_VAL_SENSE RSVD44
+VGFX_CORE VSSAXG_VAL_SENSE
N50
T56 PAD @ F48 RSVD45
VCC_DIE_SENSE
2
R811 H48
@ K48 RSVD6
49.9_0402_1% RSVD7 A4 CFG4
DC_TEST_A4 C4
1
DC_TEST_C4
1
VAXG_VAL_SENSE BA19 D3 DC_TEST_C4_D3
AV19 RSVD8 DC_TEST_D3 D1 eDP@
VSSAXG_VAL_SENSE AT21 RSVD9 DC_TEST_D1 A58 R204
2 BB21 RSVD10 DC_TEST_A58 A59 1K_0402_1% 2
RSVD11 DC_TEST_A59
2
BB19 C59 DC_TEST_A59_C59
2
R813 AY21 RSVD12 DC_TEST_C59 A61
@ BA22 RSVD13 DC_TEST_A61 C61 DC_TEST_A61_C61
49.9_0402_1% AY22 RSVD14 DC_TEST_C61 D61
AU19 RSVD15 DC_TEST_D61 BD61 PCIE Port Bifurcation Straps
1
AU21 RSVD16 DC_TEST_BD61 BE61

BD21 RSVD17 DC_TEST_BE61 BE59 DC_TEST_BE59_BE61
BD22 RSVD18 DC_TEST_BE59 BG61
BD25
BD26
BG22
RSVD19
RSVD20
RSVD21
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
BG59
BG58
BG4
DC_TEST_BG59_BG61
CFG[6:5]
*11: (Default) 1x16 PCI Express
10: 2x8 PCI Express
BE22 RSVD22 DC_TEST_BG4 BG3
BG26 RSVD23 DC_TEST_BG3 BE3 DC_TEST_BE3_BG3
01: Reserved
BE26 RSVD24 DC_TEST_BE3 BG1
BF23 RSVD25 DC_TEST_BG1 BE1 DC_TEST_BE1_BG1
00: 1x8,2x4 PCI Express
BE24 RSVD26 DC_TEST_BE1 BD1
RSVD27 DC_TEST_BD1
These pins are for solder joint CFG6
reliability and non-critical to
CFG5
IVY-BRIDGE_BGA1023
function. For BGA only.
1
IVB@
R230 R228
1K_0402_1% @ @ 1K_0402_1%
2
3 3
PEG DEFER TRAINING CRB1.0 P.12
1: (Default) PEG Train immediately following

CFG7 xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG7
1
R224
@ 1K_0402_1%
2
4 4

2012/4/6 2013/4/6 Title
Issued Date Deciphered Date PROCESSOR(4/7) RSVD,CFG
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
http://vinafix.vn MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D E
A B C D E
fix POWER
ina
UCPU1F
ULV SC/DC 33A 8.5A
v
+1.05VS_VTT
AF46
+CPU_CORE VCCIO[1] AG48
VCCIO[3] AG50
INTEL Recommend VCC A26 VCCIO[4] AG51
A29 VCC[1] VCCIO[5] AJ17 INTEL Recommend VCCIO
3*330uF,12*22uF(0805),16*2.2uF(0402) A31 VCC[2] VCCIO[6] AJ21
A34 VCC[3]
VCC[4]
VCCIO[7]
VCCIO[8]
AJ25 PD 0.9
PD0.9 A35
A38 VCC[5] VCCIO[9]
AJ43
AJ47
A39 VCC[6] VCCIO[10] AK50
1 VCC[7] VCCIO[11] 1
A42 AK51
C26 VCC[8] VCCIO[12] AL14
C27 VCC[9]
VCC[10]
VCCIO[13]
VCCIO[14]
AL15 330uF 1+1
C32 AL16
C34
C37
VCC[11]
VCC[12]
VCCIO[15]
VCCIO[16]
AL20
AL22
10uF (0603) *5
VCC[13] VCCIO[17]
C39
C42 VCC[14] VCCIO[18]
AL26
AL45
1uF (0201) *16
D27 VCC[15] VCCIO[19] AL48
D32 VCC[16] VCCIO[20] AM16
PEG IO AND DDR IO

E26 VCC[21] VCCIO[25] AN20
E37 VCC[25] VCCIO[29]
E38 VCC[26]
VCC[27]
CORE SUPPLY
F25
F26 VCC[28]
F28 VCC[29]
F32 VCC[30] +1.05VS_VTT
F34 VCC[31]
F37 VCC[32] AA14
F38 VCC[33] VCCIO[30] AA15
F42 VCC[34] VCCIO[31] AB17
G42 VCC[35] VCCIO[32] AB20
H25 VCC[36] VCCIO[33] AC13
H26 VCC[37]
VCC[38]
VCCIO[34]
VCCIO[35]
AD16 330uF 1
H28 AD18
2
H29
H32
VCC[39]
VCC[40]
VCCIO[36]
VCCIO[37]
AD21
AE14
10uF (0603) *5 2
VCC[41] VCCIO[38]
H34
H35 VCC[42] VCCIO[39]
AE15
AF16
1uF (0201) *10
H37 VCC[43] VCCIO[40] AF18
H38 VCC[44] VCCIO[41] AF20
H40 VCC[45] VCCIO[42] AG15
J25 VCC[46] VCCIO[43] AG16
J26 VCC[47] VCCIO[44] AG17 +3VALW
J32 VCC[50] VCCIO[47] AJ14
VCCIO_SEL For 2012 CPU support
2
J34 VCC[51] VCCIO[48] AJ15
J35 VCC[52] VCCIO[49] R521 1 : +1.05VS_VTT
J37
J38
VCC[53]
VCC[54]
VCC[55]
10K_0402_5% A19 * 0: +1.0VS_VTT
J40
1
J42 VCC[56] +1.05VS_VTT
K26 VCC[57] W16 VCCIO_SEL
K27 VCC[58] VCCIO50 W17
VCC[59] VCCIO51
1
K29
K32 VCC[60] R520
K34 VCC[61] 10K_0402_5% @
K35 VCC[62]
K37 VCC[63]
2
K39 VCC[64]
K42 VCC[66] BC22 VCCIO_SEL_R R582 1 @ 2 0_0402_5%
L25 VCC[67] VCCIO_SEL
L28 VCC[68]
L33 VCC[69]
L36 VCC[70] +1.05VS_VTT
L40 VCC[71]
N26 VCC[72] +1.05VS_VTT
N30 VCC[73] AM25
QUIET
RAILS
N34 VCC[74] VCCPQE[1] AN22
3
VCC[75] VCCPQE[2] Check List R1.5 3
1
N38
VCC[76] VIDALERT#:75ohm ±5% pull-up to VCCIO close to IMVP7
1
C951
1U_0201_4V6M R574 VIDSCLK: 55ohm ±5% pull-up to VCCIO close to IMVP7
2
130_0402_5% VIDSOUT: 130ohm ±5% pull-up to VCCIO close to CPU
130ohm ±5% pull-up to VCCIO close to IMVP7
2
A44 H_CPU_SVIDALRT# R576 1 2 43_0402_1%
VIDALERT# VR_SVID_ALRT# <43>
B43 H_CPU_SVIDCLK R577 1 @ 2 0_0402_5%
VIDSCLK VR_SVID_CLK <43>
SVID
C44 H_CPU_SVIDDAT R578 1 @ 2 0_0402_5%
VIDSOUT VR_SVID_DAT <43>
+CPU_CORE
1
Place the PU,PD R588
resistors close to CPU 100_0402_1%
2
F43 VCCSENSE_R R579 1 @ 2 0_0402_5%
SENSE LINES VCC_SENSE VCCSENSE <43>
G43 VSSSENSE_R R581 1 @ 2 0_0402_5%
VSS_SENSE VSSSENSE <43>
+1.05VS_VTT
1
1 2 Check List R1.5
R107 10_0402_5% R589
AN16 VCCIO_SENSE
VCCSENSE:100ohm ±1% pull-up to VCC near processor.
VCCIO_SENSE <41> 100_0402_1%
VCCIO_SENSE AN17 VSSIO_SENSE VSSSENSE:100ohm ±1% pull-down to GND near processor.
VSS_SENSE_VCCIO
2
1
R105
10_0402_5%
4 IVY-BRIDGE_BGA1023 4
2
IVB@ Should change to connect from
power cirucit & layout differential
with VCCIO_SENSE.

2012/4/6 2013/4/6 Title
Issued Date Deciphered Date PROCESSOR(5/7) PWR,BYPASS
http://vinafix.vn
Custom 1.0
A B C D E
A B C D E
f ix SA_DIMM_VREFDQ
ina
SB_DIMM_VREFDQ +1.35VS
For Future CPU M3 support,
v POWER
1
ULV SC/DC GT1: 18A Sandey bridge not support M3, +V_SM_VREF should
UCPU1G R534
Check list1.0 & CRB say can NC have 20 mil trace width
GT2: 33A 1K_0402_5%
INTEL Recommend VAXG +VGFX_CORE
2
AY43 +V_SM_VREF
2*330uF,5*22uF(0805),6*10uF(0603),6*1uF(0402) AA46 SM_VREF
VREF
1
AB47 VAXG[1]
VAXG[2] 1
PD 0.9 AB50
AB51 VAXG[3] SA_DIMM_VREFDQ
BE7
BG7
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
SA_DIMM_VREFDQ <11> C647
0.1U_0201_10V6K
R540
1K_0402_5%
VAXG[4] SB_DIMM_VREFDQ SB_DIMM_VREFDQ <12>
AB52
1 VAXG[5] 2 1
AB53
2
1
1
AB55 VAXG[6]
AB56 VAXG[7] @ @
AB58 VAXG[8] R69 R68
AB59 VAXG[9] 1K_0402_1% 1K_0402_1%
AC61 VAXG[10]
2
AD47 VAXG[11]
AD48 VAXG[12]
VAXG[13] 5A INTEL Recommend VDDQ
AD50
AD51 VAXG[14]
VAXG[15] VDDQ[1]
AJ28 1*330uF,8*10uF(0603) ,10*1uF(0402)
- 1.5V RAILS
AD52 AJ33
VAXG[16] VDDQ[2]
AD53
AD55 VAXG[17] VDDQ[3]
AJ36
AJ40
PD0.9
AD56 VAXG[18] VDDQ[4] AL30
AD58 VAXG[19] VDDQ[5] AL34
AD59 VAXG[20] VDDQ[6] AL38 Short for +1.35VS to +1.35V_CPU_VDDQ +1.35VS
AE46 VAXG[21] VDDQ[7] AL42
N45 VAXG[22] VDDQ[8] AM33
P47 VAXG[23] VDDQ[9] AM36 C977 C978 C979 C980 C981 C982 C983 C984 C988 C991
VAXG[24] VDDQ[10]
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
P48 AM40 1
P50 VAXG[25] VDDQ[11] AN30
1
P51 VAXG[26] VDDQ[12] AN34 + C599
P52 VAXG[27] VDDQ[13] AN38 330U_B2_2VM_R15M
P53 VAXG[28] VDDQ[14] AR26 SGA00004400
DDR3
2
P55 VAXG[29] VDDQ[15] AR28 2
GRAPHICS
P56 VAXG[30] VDDQ[16] AR30
P61 VAXG[31] VDDQ[17] AR32
T48 VAXG[32] VDDQ[18] AR34
Place BOT OUT Conn C990 C989 C987 C970
VAXG[35] VDDQ[21]
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
T61 AV41
1
U46 VAXG[36] VDDQ[22] AW26
V47 VAXG[37] VDDQ[23] BA40
2 V48 VAXG[38] VDDQ[24] BB28 2
2
V50 VAXG[39] VDDQ[25] BG33
V51 VAXG[40] VDDQ[26]
V52 VAXG[41]
V53 VAXG[42]
V55 VAXG[43]
V56 VAXG[44]
V58 VAXG[45]
V59 VAXG[46]
W50 VAXG[47] C1002 C986 C1010 C1007 C1008 C1006 C994 C1009 C992 C993
VAXG[48]
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
W51
W52 VAXG[49]
VAXG[50]
1
W53
W55 VAXG[51]
W56 VAXG[52]
2
W61 VAXG[53]
Check List R1.5 Y48 VAXG[54]
VCCAXG_SENSE:100ohm ±5% pull-up to VCC near processor. Y61 VAXG[55]
VAXG[56]
VSSAXG_SENSE:100ohm ±5% pull-down to GND near processor.
+VGFX_CORE R381
1 2 +1.35VS
QUIET RAILS
100_0402_5% AM28
INTEL Recommend VCCPLL
SENSE
LINES
F45 VCCDQ[1] AN26
<43> VCC_AXG_SENSE VAXG_SENSE VCCDQ[2]
G45
1*330uF,2*1uF(0402) <43> VSS_AXG_SENSE
1
VSSAXG_SENSE
R396
C985
PD 0.9 1 2 1U_0201_4V6M
2
+1.8VS R477 100_0402_5%
1.2A
1.8V RAIL
0_0805_5%
1 2 +1.8VS_VCCPLL BB3
3 BC1 VCCPLL[1] 3
VCCPLL[2]
1U_0201_4V6M
C583
1U_0201_4V6M
C584
1 1 1 BC4
VCCPLL[3]
+ C606
220U_B2_2.5VM_R15M
SGA00004I00 2 2 BC43
2 VDDQ_SENSE BA43
VSS_SENSE_VDDQ
SENSE LINES
6A L17
VCCSA_VID
L21 VCCSA[1]
N16 VCCSA[2] For 2012 future CPU
N20 VCCSA[3] VCCSA voltage select
N22 VCCSA[4]
SA RAIL
P17 VCCSA[5]
+VCCSA P20 VCCSA[6] U10
VCCSA
VCCSA[7] VCCSA_SENSE VCCSA_SENSE <42>
R16 CPU EDS1.3 P.93 VID0 VID1 Vout SNB IVB ULV
+VCCSA R18 VCCSA[8]
R21 VCCSA[9] VCCSA_VID0 Must PD
C998 C999 C1181 C1180 C1179 U15 VCCSA[10] 0 0 0.9V V V V
1
VCCSA VID
VCCSA[11]
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
V16 0 1 0.8V V V
1
+ C607 V17 VCCSA[12] D48 H_VCCSA_VID0

VCCSA[13] VCCSA_VID[0] H_VCCSA_VID0 <42>
lines
330U_B2_2VM_R15M V18 D49 H_VCCSA_VID1 0.85V V

VCCSA[14] VCCSA_VID[1] H_VCCSA_VID1 <42>
SGA00004400 V21
2
2 W20 VCCSA[15]
VCCSA[16] 1 0 0.725V X V V
1
R129
0_0402_5% 1 1 0.675V X V V
@
IVY-BRIDGE_BGA1023
2
IVB@
4 INTEL Recommend VCCSA C995 C996 C997 4

10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1*330uF,5*10uF(0603) ,5*1uF(0402)
1
PD0.9
2

2012/4/6 2013/4/6 Title
Issued Date Deciphered Date PROCESSOR(6/7) PWR
http://vinafix.vn
Custom 1.0
A B C D E
A B C D E
fix
vina
UCPU1H
UCPU1I
1 A13 AM38 1
A17 VSS[1] VSS[91] AM4
A21 VSS[2] VSS[92] AM42 BG17 M4
A25 VSS[3] VSS[93] AM45 BG21 VSS[181] VSS[250] M58
A28 VSS[4] VSS[94] AM48 BG24 VSS[182] VSS[251] M6
A33 VSS[5] VSS[95] AM58 BG28 VSS[183] VSS[252] N1
A37 VSS[6] VSS[96] AN1 BG37 VSS[184] VSS[253] N17
AA1 VSS[12] VSS[102] AN40 C29 VSS[190] VSS[259] N40
AA51 VSS[15] VSS[105] AN50 D10 VSS[193] VSS[262] N48
AA52 VSS[16] VSS[106] AN54 D14 VSS[194] VSS[263] N51
AA53 VSS[17] VSS[107] AP10 D18 VSS[195] VSS[264] N52
AA8 VSS[20] VSS[110] AP7 D29 VSS[198] VSS[267] P14
AB16 VSS[21] VSS[111] AR13 D35 VSS[199] VSS[268] P16
AB61
AC10
VSS[25]
VSS[26]
VSS[27]
VSS[115]
VSS[116]
VSS[117]
AR48
AR61
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[272]
VSS[273]
VSS[274]
P59
P9
AC14 AR7 D54 R17
AC46 VSS[28] VSS[118] AT14 D58 VSS[206] VSS[275] R20
AC6 VSS[29] VSS[119] AT19 D6 VSS[207] VSS[276] R4
AD17 VSS[30] VSS[120] AT36 E25 VSS[208] VSS[277] R46
AD20 VSS[31] VSS[121] AT4 E29 VSS[209] VSS[278] T1
2 AD4 VSS[32] VSS[122] AT45 E3 VSS[210] VSS[279] T47 2
AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
E35
E40
VSS[211]
VSS[212]
VSS[213]
VSS[280]
VSS[281]
VSS[282]
T50
T51
AE8 AU1 F13 T52
AF1 VSS[36] VSS[126] AU11 F15 VSS[214] VSS[283] T53
AF47 VSS[39] VSS[129] AU51 F35 VSS[217] VSS[286] U13
AF48 VSS[40] VSS[130] AU7 F40 VSS[218] VSS[287] U8
AF50 VSS[41] VSS[131] AV17 F55 VSS[219] VSS[288] V20
AF51 VSS[42] VSS[132] AV21 G51 VSS[220] VSS[289] V61
AF52 VSS[43] VSS[133] AV22 G6 VSS[221] VSS[290] W13
AF53 VSS[44] VSS[134] AV34 G61 VSS[222] VSS[291] W15
AF55 VSS[45] VSS[135] AV40 H10 VSS[223] VSS[292] W18
AF59 VSS[48] VSS[138] AW13 H21 VSS[226] VSS[295] W8
AG10 VSS[49] VSS[139] AW43 H4 VSS[227] VSS[296] Y4
AG47 VSS[52] VSS[142] AY14 J1 VSS[230] VSS[299] Y59
AG52 VSS[53] VSS[143] AY19 J49 VSS[231] VSS[300] G48
AG61 VSS[54] VSS[144] AY30 J55 VSS[232] VSS[301]
AG7 VSS[55] VSS[145] AY36 K11 VSS[233]
AH4 VSS[56] VSS[146] AY4 K21 VSS[234]
AH58 VSS[57] VSS[147] AY41 K51 VSS[235]
AJ13 VSS[58] VSS[148] AY45 K8 VSS[236] A5 @ PAD T58
AJ16 VSS[59] VSS[149] AY49 L16 VSS[237] VSS_NCTF_1 A57 @ PAD T59
AJ20 VSS[60] VSS[150] AY55 L20 VSS[238] VSS_NCTF_2 BC61 @ PAD T60
AJ22 VSS[61] VSS[151] AY58 L22 VSS[239] VSS_NCTF_3 BD3 @ PAD T61
AJ26 VSS[62] VSS[152] AY9 L26 VSS[240] VSS_NCTF_4 BD59 @ PAD T62
AJ30 VSS[63] VSS[153] BA1 L30 VSS[241] VSS_NCTF_5 BE4 @ PAD T63
NCTF
3 AJ34 VSS[64] VSS[154] BA11 L34 VSS[242] VSS_NCTF_6 BE58 @ PAD T64 3
AJ38 VSS[65] VSS[155] BA17 L38 VSS[243] VSS_NCTF_7 BG5 @ PAD T65
AJ42 VSS[66] VSS[156] BA21 L43 VSS[244] VSS_NCTF_8 BG57 @ PAD T66
AJ45 VSS[67] VSS[157] BA26 L48 VSS[245] VSS_NCTF_9 C3 @ PAD T67
AJ48 VSS[68] VSS[158] BA32 L61 VSS[246] VSS_NCTF_10 C58 @ PAD T68
AJ7 VSS[69] VSS[159] BA48 M11 VSS[247] VSS_NCTF_11 D59 @ PAD T69
AK1 VSS[70] VSS[160] BA51 M15 VSS[248] VSS_NCTF_12 E1 @ PAD T70
AK52 VSS[71] VSS[161] BB53 VSS[249] VSS_NCTF_13 E61 @ PAD T71
AL10 VSS[72] VSS[162] BC13 VSS_NCTF_14
AL13 VSS[73] VSS[163] BC5
AL17 VSS[74] VSS[164] BC57
CR CheckList Rev1.5
AL21 VSS[75] VSS[165] BD12
AL25 VSS[76] VSS[166] BD16
AL28 VSS[77] VSS[167] BD19 IVY-BRIDGE_BGA1023
AL33 VSS[78] VSS[168] BD23 IVB@
AL36 VSS[79] VSS[169] BD27
AL40 VSS[80] VSS[170] BD32
AL43 VSS[81] VSS[171] BD36
AL47 VSS[82] VSS[172] BD40
AL61 VSS[83] VSS[173] BD44
AM13 VSS[84] VSS[174] BD48
AM20 VSS[85] VSS[175] BD52
AM22 VSS[86] VSS[176] BD56
AM26 VSS[87] VSS[177] BD8
AM30 VSS[88] VSS[178] BE5
AM34 VSS[89] VSS[179] BG13
VSS[90] VSS[180]
IVY-BRIDGE_BGA1023
4 IVB@ 4

2012/4/6 2013/4/6 Title
Issued Date Deciphered Date PROCESSOR(7/7) VSS
Custom 1.0
http://vinafix.vn
A B C D E
A B C D E
fix A
a
Channel
v i n
<6> DDR_A_MA[0..15]
<6> DDR_A_DQS#[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
<6> DDR_A_DQS[0..7]
DDR_A_D[0..63]
<6> DDR_A_D[0..63]
U56 U57 U58 U59

+VREFCA_A +VREFCA_A +VREFCA_A +VREFCA_A
M8 E3 DDR_A_D8 M8 E3 DDR_A_D16 M8 E3 DDR_A_D32 M8 E3 DDR_A_D52
H1 VREFCA DQL0 F7 DDR_A_D10 H1 VREFCA DQL0 F7 DDR_A_D19 H1 VREFCA DQL0 F7 DDR_A_D34 H1 VREFCA DQL0 F7 DDR_A_D54
1 VREFDQ DQL1 F2 DDR_A_D13 VREFDQ DQL1 F2 DDR_A_D20 VREFDQ DQL1 F2 DDR_A_D33 VREFDQ DQL1 F2 DDR_A_D48
1
1 DQL2 1 DQL2 1 DQL2 1 DQL2
C1252
0.1U_0402_16V4Z
C1255
0.1U_0402_16V4Z
C1256
0.1U_0402_16V4Z
C1257
0.1U_0402_16V4Z
DDR_A_MA0 N3 F8 DDR_A_D11 DDR_A_MA0 N3 F8 DDR_A_D18 DDR_A_MA0 N3 F8 DDR_A_D35 DDR_A_MA0 N3 F8 DDR_A_D50
DDR_A_MA1 P7 A0 DQL3 H3 DDR_A_D12 DDR_A_MA1 P7 A0 DQL3 H3 DDR_A_D22 DDR_A_MA1 P7 A0 DQL3 H3 DDR_A_D37 DDR_A_MA1 P7 A0 DQL3 H3 DDR_A_D53
2 DDR_A_MA3 N2 A2 DQL5 G2 DDR_A_D9 2 DDR_A_MA3 N2 A2 DQL5 G2 DDR_A_D17 2 DDR_A_MA3 N2 A2 DQL5 G2 DDR_A_D36 2 DDR_A_MA3 N2 A2 DQL5 G2 DDR_A_D49
DDR_A_MA5 P2 A4 DQL7 DDR_A_MA5 P2 A4 DQL7 DDR_A_MA5 P2 A4 DQL7 DDR_A_MA5 P2 A4 DQL7
DDR_A_MA6 R8 A5 DDR_A_MA6 R8 A5 DDR_A_MA6 R8 A5 DDR_A_MA6 R8 A5
DDR_A_MA7 R2 A6 D7 DDR_A_D3 DDR_A_MA7 R2 A6 D7 DDR_A_D25 DDR_A_MA7 R2 A6 D7 DDR_A_D42 DDR_A_MA7 R2 A6 D7 DDR_A_D63
DDR_A_MA8 T8 A7 DQU0 C3 DDR_A_D1 DDR_A_MA8 T8 A7 DQU0 C3 DDR_A_D29 DDR_A_MA8 T8 A7 DQU0 C3 DDR_A_D45 DDR_A_MA8 T8 A7 DQU0 C3 DDR_A_D61
+VREFDQ_A DDR_A_MA9 R3 A8 DQU1 C8 DDR_A_D2 +VREFDQ_A DDR_A_MA9 R3 A8 DQU1 C8 DDR_A_D27 +VREFDQ_A DDR_A_MA9 R3 A8 DQU1 C8 DDR_A_D47 +VREFDQ_A DDR_A_MA9 R3 A8 DQU1 C8 DDR_A_D58
DDR_A_MA10 L7 A9 DQU2 C2 DDR_A_D4 DDR_A_MA10 L7 A9 DQU2 C2 DDR_A_D28 DDR_A_MA10 L7 A9 DQU2 C2 DDR_A_D44 DDR_A_MA10 L7 A9 DQU2 C2 DDR_A_D60
DDR_A_MA11 R7 A10/AP DQU3 A7 DDR_A_D7 DDR_A_MA11 R7 A10/AP DQU3 A7 DDR_A_D31 DDR_A_MA11 R7 A10/AP DQU3 A7 DDR_A_D46 DDR_A_MA11 R7 A10/AP DQU3 A7 DDR_A_D59
@ DDR_A_MA12 N7 A11 DQU4 A2 DDR_A_D0 @ DDR_A_MA12 N7 A11 DQU4 A2 DDR_A_D30 DDR_A_MA12 N7 A11 DQU4 A2 DDR_A_D40 DDR_A_MA12 N7 A11 DQU4 A2 DDR_A_D56
1 A12 DQU5 1 A12 DQU5 1 A12 DQU5 1 A12 DQU5
1
1
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
C1258
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
C1259
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
C1261
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
C1263
DDR_A_MA13 T3 B8 DDR_A_D6 DDR_A_MA13 T3 B8 DDR_A_D26 DDR_A_MA13 T3 B8 DDR_A_D43 DDR_A_MA13 T3 B8 DDR_A_D62
A13 DQU6 A13 DQU6 A13 DQU6 A13 DQU6
C1253
C1254
C1260
C1262
DDR_A_MA14 T7 A3 DDR_A_D5 DDR_A_MA14 T7 A3 DDR_A_D24 DDR_A_MA14 T7 A3 DDR_A_D41 DDR_A_MA14 T7 A3 DDR_A_D57
DDR_A_MA15 M7 A14 DQU7 DDR_A_MA15 M7 A14 DQU7 DDR_A_MA15 M7 A14 DQU7 DDR_A_MA15 M7 A14 DQU7
2
2
2 A15/BA3 +1.35V 2 A15/BA3 +1.35V 2 A15/BA3 +1.35V 2 A15/BA3 +1.35V
DDR_A_BS0 M2 B2 DDR_A_BS0 M2 B2 DDR_A_BS0 M2 B2 DDR_A_BS0 M2 B2

DDR_A_BS1 N8 BA0 VDD D9 DDR_A_BS1 N8 BA0 VDD D9 DDR_A_BS1 N8 BA0 VDD D9 DDR_A_BS1 N8 BA0 VDD D9
DDR_A_BS2 M3 BA1 VDD G7 DDR_A_BS2 M3 BA1 VDD G7 DDR_A_BS2 M3 BA1 VDD G7 DDR_A_BS2 M3 BA1 VDD G7
BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
DDR_A_CLK0 J7 VDD N9 DDR_A_CLK0 J7 VDD N9 DDR_A_CLK0 J7 VDD N9 DDR_A_CLK0 J7 VDD N9
DDR_A_CLK0# K7 CK VDD R1 DDR_A_CLK0# K7 CK VDD R1 DDR_A_CLK0# K7 CK VDD R1 DDR_A_CLK0# K7 CK VDD R1
DDR_A_CKE0 K9 CK VDD R9 DDR_A_CKE0 K9 CK VDD R9 DDR_A_CKE0 K9 CK VDD R9 DDR_A_CKE0 K9 CK VDD R9
CKE/CKE0 VDD CKE/CKE0 VDD CKE/CKE0 VDD CKE/CKE0 VDD
DDR_A_ODT0 K1 A1 DDR_A_ODT0 K1 A1 DDR_A_ODT0 K1 A1 DDR_A_ODT0 K1 A1

DDR_A_CS0# L2 ODT/ODT0 VDDQ A8 DDR_A_CS0# L2 ODT/ODT0 VDDQ A8 DDR_A_CS0# L2 ODT/ODT0 VDDQ A8 DDR_A_CS0# L2 ODT/ODT0 VDDQ A8
DDR_A_RAS# J3 CS/CS0 VDDQ C1 DDR_A_RAS# J3 CS/CS0 VDDQ C1 DDR_A_RAS# J3 CS/CS0 VDDQ C1 DDR_A_RAS# J3 CS/CS0 VDDQ C1
DDR_A_CAS# K3 RAS VDDQ C9 DDR_A_CAS# K3 RAS VDDQ C9 DDR_A_CAS# K3 RAS VDDQ C9 DDR_A_CAS# K3 RAS VDDQ C9
DDR_A_WE# L3 CAS VDDQ D2 DDR_A_WE# L3 CAS VDDQ D2 DDR_A_WE# L3 CAS VDDQ D2 DDR_A_WE# L3 CAS VDDQ D2
WE VDDQ E9 WE VDDQ E9 WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
DDR_A_DQS1 F3 VDDQ H2 DDR_A_DQS2 F3 VDDQ H2 DDR_A_DQS4 F3 VDDQ H2 DDR_A_DQS6 F3 VDDQ H2
DDR_A_DQS0 C7 DQSL VDDQ H9 DDR_A_DQS3 C7 DQSL VDDQ H9 DDR_A_DQS5 C7 DQSL VDDQ H9 DDR_A_DQS7 C7 DQSL VDDQ H9
2
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ 2
E7 A9 E7 A9 E7 A9 E7 A9
D3 DML VSS B3 D3 DML VSS B3 D3 DML VSS B3 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
DDR_A_DQS#1 G3 VSS J2 DDR_A_DQS#2 G3 VSS J2 DDR_A_DQS#4 G3 VSS J2 DDR_A_DQS#6 G3 VSS J2
DDR_A_DQS#0 B7 DQSL VSS J8 DDR_A_DQS#3 B7 DQSL VSS J8 DDR_A_DQS#5 B7 DQSL VSS J8 DDR_A_DQS#7 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
DIMM_DRAMRST# T2 VSS P9 DIMM_DRAMRST# T2 VSS P9 DIMM_DRAMRST# T2 VSS P9 DIMM_DRAMRST# T2 VSS P9
<12,6> DIMM_DRAMRST# RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
1 R992 2 L8 VSS T9 1 R993 2 L8 VSS T9 1 R994 2 L8 VSS T9 1 R995 2 L8 VSS T9
240_0402_1% ZQ/ZQ0 VSS 240_0402_1% ZQ/ZQ0 VSS 240_0402_1% ZQ/ZQ0 VSS 240_0402_1% ZQ/ZQ0 VSS
J1 B1 J1 B1 J1 B1 J1 B1
L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1
1 R996 2 L9 NC/CE1 VSSQ D8 1 R997 2 L9 NC/CE1 VSSQ D8 1 R998 2 L9 NC/CE1 VSSQ D8 1 R999 2 L9 NC/CE1 VSSQ D8
240_0402_1% NCZQ1 VSSQ E2 240_0402_1% NCZQ1 VSSQ E2 240_0402_1% NCZQ1 VSSQ E2 240_0402_1% NCZQ1 VSSQ E2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96
X76@ X76@ X76@ X76@
+0.675VS
10U_0603_6.3V6M
C1519
1
2
3 DDR3 CTL/ADD Termination 3

C1458 DDR3 CLK Termination
+0.675VS
Delete U70 SPD EEROM circuit
1 2
+0.675VS SA00004KS00
+1.35V 1 2 DDR_A_RAS# 0.1U_0402_16V4Z
DDR_A_RAS# <6> S IC EE 2K AT24C02C-XHM-T TSSOP 8P
R284 36_0201_1%
1
1
1 2 DDR_A_CAS# DDR_A_CAS# <6>
1U_0201_4V6M
C1462
0.1U_0201_10V6K
C1461
1U_0201_4V6M
C1460
0.1U_0201_10V6K
C1459
1U_0201_4V6M
C1514
0.1U_0201_10V6K
C1513
0.1U_0201_10V6K
C1512
1U_0201_4V6M
C1511
M3 support @ R1105 R1106 R290 36_0201_1% R1102 R1103

0_0402_5% 1K_0402_1% 1 2 DDR_A_ODT0 30.1_0402_1% 30.1_0402_1%
DDR_A_ODT0 <6>
1
1 2 R291 36_0201_1%
<9> SA_DIMM_VREFDQ +VREFDQ_A 1 2 DDR_A_CKE0
DDR_A_CKE0 <6>
2
2
R294 36_0201_1%
2
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
1 2 DDR_A_WE# END topology

DDR_A_WE# <6>
C1480
C1481
S
3 1 R295 36_0201_1%
<6> DDR_A_CLK0
1
Q78 1 2 DDR_A_MA10
1
1
BSS138_NL_SOT23-3 @ R296 36_0201_1% C1457
R1104 1 2 DDR_A_CS0# 1.8P_0201_50V8C
G
DDR_A_CS0# <6>
2
<12,14,6> DRAMRST_CNTRL_PCH 1K_0402_1% R297 36_0201_1%

2
2
1 2 DDR_A_BS2 DDR_A_BS2 <6>
External DDR Thermal Sensor
2
<6> DDR_A_CLK0#
R298 36_0201_1%
Layout Note: 1 2 DDR_A_BS0
DDR_A_BS0 <6>
R301 36_0201_1% +3VS
+1.35V Place near each memory part 1 2 DDR_A_MA12 1.CAD Note: Cterm= 1.6pF should be kept C97
R303 36_0201_1% 0.1U_0402_16V4Z
+1.35V 1 2 DDR_A_MA0 near feeding point of first SDRAM 1 2
R304 36_0201_1%
1 2 DDR_A_BS1 DDR_A_BS1 <6> 2.CAD Note: Rtt= 30.1ohms, Ctt= 0.1uF
0.1U_0201_10V6K
C1466
1U_0402_6.3V6K
C1476
1U_0402_6.3V6K
C1477
0.1U_0201_10V6K
C1467
0.1U_0201_10V6K
C1470
1U_0402_6.3V6K
C1471
1U_0402_6.3V6K
C1478
1U_0402_6.3V6K
C1468
R306 36_0201_1%
1
1 2 DDR_A_MA3 should be kept within 600mils from last SDRAM

1
R1108 R309 36_0201_1% U4

1K_0402_1% 1 2 DDR_A_MA1 1 8
VDD SCLK EC_SMB_CK2 <14,24,32>
R311 36_0201_1%
2
1 2 DDR_A_MA2 2 7
2
+VREFCA_A D+ SDATA EC_SMB_DA2 <14,24,32>

R312 36_0201_1%
1 2 DDR_A_MA4 3 6 1 2
D- ALERT# +3VS
R313 36_0201_1% R546 10K_0402_5%
2.2U_0603_6.3V6K
1 2 DDR_A_MA5 4 5
THERM# GND
C1483
0.1U_0402_16V4Z
C1482
R315 36_0201_1%
1
+1.35V 1 2 DDR_A_MA11
1
4 R1107 R317 36_0201_1% W83L771AWG-2 TSSOP8P 4

1K_0402_1% 1 2 DDR_A_MA9 SA00003PU00
R318 36_0201_1%
2
2
10U_0603_6.3V6M
C1469
10U_0603_6.3V6M
C1479
10U_0603_6.3V6M
C1463
10U_0603_6.3V6M
C1475
10U_0603_6.3V6M
C1465
10U_0603_6.3V6M
C1473
10U_0603_6.3V6M
C1472
10U_0603_6.3V6M
C1474
330U_D2_2V_Y
@ 1 2 DDR_A_MA14 SA00003PU00
2
1
C1464
R319 36_0201_1%
S IC W83L771AWG-2 TSSOP 8P SENSOR
1
+ 1 2 DDR_A_MA13
R323 36_0201_1%
1 2 DDR_A_MA6
2
R325 36_0201_1%
1 2 DDR_A_MA7
R332 36_0201_1%
1 2 DDR_A_MA8 Security Classification Compal Secret Data Compal Electronics, Inc.
R333 36_0201_1% 2012/4/6 2013/4/6 Title
1 2 DDR_A_MA15
Issued Date Deciphered Date DDRIII DIMMA
R342 36_0201_1%
near U56 near U57 near U58 near U59 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
http://vinafix.vn
A B C D E
A B C D E
a fix B
in
Channel DDR_B_DQS#[0..7] <6>
v
DDR_B_DQS[0..7] <6>
DDR_B_D[0..63] <6>
DDR_B_MA[0..15] <6>
U60 U61 U62 U63

+VREFCA_B +VREFCA_B +VREFCA_B +VREFCA_B
M8 E3 DDR_B_D12 M8 E3 DDR_B_D16 M8 E3 DDR_B_D37 M8 E3 DDR_B_D61
H1 VREFCA DQL0 F7 DDR_B_D10 H1 VREFCA DQL0 F7 DDR_B_D23 H1 VREFCA DQL0 F7 DDR_B_D39 H1 VREFCA DQL0 F7 DDR_B_D58
VREFDQ DQL1 F2 DDR_B_D13 VREFDQ DQL1 F2 DDR_B_D17 VREFDQ DQL1 F2 DDR_B_D36 VREFDQ DQL1 F2 DDR_B_D60
1 1 1 1 1 1
DQL2 DQL2 DQL2 DQL2
C1294
0.1U_0402_16V4Z
C1295
0.1U_0402_16V4Z
C1296
0.1U_0402_16V4Z
C1297
0.1U_0402_16V4Z
DDR_B_MA0 N3 F8 DDR_B_D11 DDR_B_MA0 N3 F8 DDR_B_D22 DDR_B_MA0 N3 F8 DDR_B_D38 DDR_B_MA0 N3 F8 DDR_B_D62
128@ DDR_B_MA1 P7 A0 DQL3 H3 DDR_B_D8 128@ DDR_B_MA1 P7 A0 DQL3 H3 DDR_B_D21 128@ DDR_B_MA1 P7 A0 DQL3 H3 DDR_B_D32 128@ DDR_B_MA1 P7 A0 DQL3 H3 DDR_B_D56
DDR_B_MA2 P3 A1 DQL4 H8 DDR_B_D15 DDR_B_MA2 P3 A1 DQL4 H8 DDR_B_D18 DDR_B_MA2 P3 A1 DQL4 H8 DDR_B_D34 DDR_B_MA2 P3 A1 DQL4 H8 DDR_B_D59
2 DDR_B_MA3 N2 A2 DQL5 G2 DDR_B_D9 2 DDR_B_MA3 N2 A2 DQL5 G2 DDR_B_D20 2 DDR_B_MA3 N2 A2 DQL5 G2 DDR_B_D33 2 DDR_B_MA3 N2 A2 DQL5 G2 DDR_B_D57
DDR_B_MA4 P8 A3 DQL6 H7 DDR_B_D14 DDR_B_MA4 P8 A3 DQL6 H7 DDR_B_D19 DDR_B_MA4 P8 A3 DQL6 H7 DDR_B_D35 DDR_B_MA4 P8 A3 DQL6 H7 DDR_B_D63
DDR_B_MA5 P2 A4 DQL7 DDR_B_MA5 P2 A4 DQL7 DDR_B_MA5 P2 A4 DQL7 DDR_B_MA5 P2 A4 DQL7
DDR_B_MA6 R8 A5 DDR_B_MA6 R8 A5 DDR_B_MA6 R8 A5 DDR_B_MA6 R8 A5
DDR_B_MA7 R2 A6 D7 DDR_B_D1 DDR_B_MA7 R2 A6 D7 DDR_B_D30 DDR_B_MA7 R2 A6 D7 DDR_B_D42 DDR_B_MA7 R2 A6 D7 DDR_B_D55
DDR_B_MA8 T8 A7 DQU0 C3 DDR_B_D2 DDR_B_MA8 T8 A7 DQU0 C3 DDR_B_D25 DDR_B_MA8 T8 A7 DQU0 C3 DDR_B_D41 DDR_B_MA8 T8 A7 DQU0 C3 DDR_B_D52
+VREFDQ_B DDR_B_MA9 R3 A8 DQU1 C8 DDR_B_D7 +VREFDQ_B DDR_B_MA9 R3 A8 DQU1 C8 DDR_B_D27 +VREFDQ_B DDR_B_MA9 R3 A8 DQU1 C8 DDR_B_D47 +VREFDQ_B DDR_B_MA9 R3 A8 DQU1 C8 DDR_B_D51
DDR_B_MA10 L7 A9 DQU2 C2 DDR_B_D5 DDR_B_MA10 L7 A9 DQU2 C2 DDR_B_D28 DDR_B_MA10 L7 A9 DQU2 C2 DDR_B_D44 DDR_B_MA10 L7 A9 DQU2 C2 DDR_B_D49
@ DDR_B_MA11 R7 A10/AP DQU3 A7 DDR_B_D6 @ DDR_B_MA11 R7 A10/AP DQU3 A7 DDR_B_D26 DDR_B_MA11 R7 A10/AP DQU3 A7 DDR_B_D46 128@ DDR_B_MA11 R7 A10/AP DQU3 A7 DDR_B_D54
DDR_B_MA12 N7 A11 DQU4 A2 DDR_B_D4 DDR_B_MA12 N7 A11 DQU4 A2 DDR_B_D29 DDR_B_MA12 N7 A11 DQU4 A2 DDR_B_D45 DDR_B_MA12 N7 A11 DQU4 A2 DDR_B_D48
1 A12 DQU5 1 A12 DQU5 1 A12 DQU5 1 A12 DQU5
1
1
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
C1292
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
C1293
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
C1291
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
C1302
DDR_B_MA13 T3 B8 DDR_B_D3 DDR_B_MA13 T3 B8 DDR_B_D31 DDR_B_MA13 T3 B8 DDR_B_D43 DDR_B_MA13 T3 B8 DDR_B_D50
A13 DQU6 A13 DQU6 A13 DQU6 A13 DQU6
C1298
C1299
C1300
C1301
128@ DDR_B_MA14 T7 A3 DDR_B_D0 128@ DDR_B_MA14 T7 A3 DDR_B_D24 128@ DDR_B_MA14 T7 A3 DDR_B_D40 128@ DDR_B_MA14 T7 A3 DDR_B_D53
DDR_B_MA15 M7 A14 DQU7 DDR_B_MA15 M7 A14 DQU7 DDR_B_MA15 M7 A14 DQU7 DDR_B_MA15 M7 A14 DQU7
2
2
2 A15/BA3 +1.35V 2 A15/BA3 +1.35V 2 A15/BA3 +1.35V 2 A15/BA3 +1.35V
DDR_B_BS0 M2 B2 DDR_B_BS0 M2 B2 DDR_B_BS0 M2 B2 DDR_B_BS0 M2 B2

DDR_B_BS1 N8 BA0 VDD D9 DDR_B_BS1 N8 BA0 VDD D9 DDR_B_BS1 N8 BA0 VDD D9 DDR_B_BS1 N8 BA0 VDD D9
DDR_B_BS2 M3 BA1 VDD G7 DDR_B_BS2 M3 BA1 VDD G7 DDR_B_BS2 M3 BA1 VDD G7 DDR_B_BS2 M3 BA1 VDD G7
BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
DDR_B_CLK0 J7 VDD N9 DDR_B_CLK0 J7 VDD N9 DDR_B_CLK0 J7 VDD N9 DDR_B_CLK0 J7 VDD N9
DDR_B_CLK0# K7 CK VDD R1 DDR_B_CLK0# K7 CK VDD R1 DDR_B_CLK0# K7 CK VDD R1 DDR_B_CLK0# K7 CK VDD R1
DDR_B_CKE0 K9 CK VDD R9 DDR_B_CKE0 K9 CK VDD R9 DDR_B_CKE0 K9 CK VDD R9 DDR_B_CKE0 K9 CK VDD R9
CKE/CKE0 VDD CKE/CKE0 VDD CKE/CKE0 VDD CKE/CKE0 VDD
DDR_B_ODT0 K1 A1 DDR_B_ODT0 K1 A1 DDR_B_ODT0 K1 A1 DDR_B_ODT0 K1 A1

DDR_B_CS0# L2 ODT/ODT0 VDDQ A8 DDR_B_CS0# L2 ODT/ODT0 VDDQ A8 DDR_B_CS0# L2 ODT/ODT0 VDDQ A8 DDR_B_CS0# L2 ODT/ODT0 VDDQ A8
DDR_B_RAS# J3 CS/CS0 VDDQ C1 DDR_B_RAS# J3 CS/CS0 VDDQ C1 DDR_B_RAS# J3 CS/CS0 VDDQ C1 DDR_B_RAS# J3 CS/CS0 VDDQ C1
DDR_B_CAS# K3 RAS VDDQ C9 DDR_B_CAS# K3 RAS VDDQ C9 DDR_B_CAS# K3 RAS VDDQ C9 DDR_B_CAS# K3 RAS VDDQ C9
DDR_B_WE# L3 CAS VDDQ D2 DDR_B_WE# L3 CAS VDDQ D2 DDR_B_WE# L3 CAS VDDQ D2 DDR_B_WE# L3 CAS VDDQ D2
WE VDDQ E9 WE VDDQ E9 WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
DDR_B_DQS1 F3 VDDQ H2 DDR_B_DQS2 F3 VDDQ H2 DDR_B_DQS4 F3 VDDQ H2 DDR_B_DQS7 F3 VDDQ H2
DDR_B_DQS0 C7 DQSL VDDQ H9 DDR_B_DQS3 C7 DQSL VDDQ H9 DDR_B_DQS5 C7 DQSL VDDQ H9 DDR_B_DQS6 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
E7 A9 E7 A9 E7 A9 E7 A9
D3 DML VSS B3 D3 DML VSS B3 D3 DML VSS B3 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
2
DDR_B_DQS#1 G3 VSS J2 DDR_B_DQS#2 G3 VSS J2 DDR_B_DQS#4 G3 VSS J2 DDR_B_DQS#7 G3 VSS J2 2
DDR_B_DQS#0 B7 DQSL VSS J8 DDR_B_DQS#3 B7 DQSL VSS J8 DDR_B_DQS#5 B7 DQSL VSS J8 DDR_B_DQS#6 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
DIMM_DRAMRST# T2 VSS P9 DIMM_DRAMRST# T2 VSS P9 DIMM_DRAMRST# T2 VSS P9 DIMM_DRAMRST# T2 VSS P9
<11,6> DIMM_DRAMRST# RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
1 R1005 2 L8 VSS T9 1 R1006 2 L8 VSS T9 1 R1007 2 L8 VSS T9 1 R1008 2 L8 VSS T9
240_0402_1% ZQ/ZQ0 VSS 240_0402_1% ZQ/ZQ0 VSS 240_0402_1% ZQ/ZQ0 VSS 240_0402_1% ZQ/ZQ0 VSS
128@ 128@ 128@ 128@
J1 B1 J1 B1 J1 B1 J1 B1
L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1
1 R1009 2 L9 NC/CE1 VSSQ D8 1 R1010 2 L9 NC/CE1 VSSQ D8 1 R1011 2 L9 NC/CE1 VSSQ D8 1 R1012 2 L9 NC/CE1 VSSQ D8
240_0402_1% NCZQ1 VSSQ E2 240_0402_1% NCZQ1 VSSQ E2 240_0402_1% NCZQ1 VSSQ E2 240_0402_1% NCZQ1 VSSQ E2
128@ VSSQ E8 128@ VSSQ E8 128@ VSSQ E8 128@ VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96
X76@ X76@ X76@ X76@
+1.35V
+0.675VS
1
128@ DDR3 CTL/ADD Termination
M3 support @ R1122 R1123
0_0402_5% 1K_0402_1%
+0.675VS
1U_0201_4V6M
C1504
1U_0201_4V6M
C1503
0.1U_0201_10V6K
C1502
1U_0201_4V6M
C1501
0.1U_0201_10V6K
C1518
1U_0201_4V6M
C1517
0.1U_0201_10V6K
C1516
0.1U_0201_10V6K
C1515
<9> SB_DIMM_VREFDQ 1 2
+VREFDQ_B
2
1
3 1 128@ 2 DDR_B_RAS# DDR_B_RAS# <6> Delete U71 SPD EEROM circuit 3
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ R380 36_0201_1%
SA00004KS00
C1509
C1510
S
3 1 1 128@ 2 DDR_B_CAS# DDR_B_CAS# <6>

2
Q79 R308 36_0201_1% S IC EE 2K AT24C02C-XHM-T TSSOP 8P
1
BSS138_NL_SOT23-3 @ 128@ 1 128@ 2 DDR_B_ODT0 DDR_B_ODT0 <6>
R1121 R339 36_0201_1%
G
2
<11,14,6> DRAMRST_CNTRL_PCH 1K_0402_1%

2 1 128@ 2 DDR_B_CKE0 DDR_B_CKE0 <6>
2
128@ 128@ R349 36_0201_1%
2
1 128@ 2 DDR_B_WE# DDR_B_WE# <6>

R343 36_0201_1%
Layout Note: 1 128@ 2 DDR_B_MA10
R348 36_0201_1%
Place near each memory part 1 128@ 2 DDR_B_CS0# DDR_B_CS0# <6>
+1.35V R354 36_0201_1%
+1.35V 1 128@ 2 DDR_B_BS2 DDR_B_BS2 <6>
R370 36_0201_1%
1 128@ 2 DDR_B_BS0 DDR_B_BS0 <6>
1
128@ R340 36_0201_1%

R1120 1 128@ 2 DDR_B_MA12
0.1U_0201_10V6K
C1487
0.1U_0201_10V6K
C1497
0.1U_0201_10V6K
C1498
0.1U_0201_10V6K
C1488
1U_0402_6.3V6K
C1491
1U_0402_6.3V6K
C1492
1U_0402_6.3V6K
C1499
0.1U_0201_10V6K
C1489
1K_0402_1% R352 36_0201_1%

1 128@ 2 DDR_B_MA0
1
R407 36_0201_1% DDR3 CLK Termination

C1506
2
128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ +VREFCA_B 1 128@ 2 DDR_B_BS1 128@
DDR_B_BS1 <6>
R351 36_0201_1% 1 2
2
1 128@ 2 DDR_B_MA3
2.2U_0603_6.3V6K
R392 36_0201_1% 0.1U_0402_16V4Z

C1508
0.1U_0402_16V4Z
C1507
1 128@ 2 DDR_B_MA1
1
1
128@ R398 36_0201_1% 128@ 128@
1
R1119 1 128@ 2 DDR_B_MA2 R1117 R1118

1K_0402_1% 128@ 128@ R377 36_0201_1% 30.1_0402_1% 30.1_0402_1%
+1.35V 1 128@ 2 DDR_B_MA4
2
R356 36_0201_1%
2
2
1 128@ 2 DDR_B_MA5
R355 36_0201_1% END topology
10U_0603_6.3V6M
C1490
10U_0603_6.3V6M
C1500
10U_0603_6.3V6M
C1485
10U_0603_6.3V6M
C1496
10U_0603_6.3V6M
C1486
10U_0603_6.3V6M
C1494
10U_0603_6.3V6M
C1493
10U_0603_6.3V6M
C1495
330U_D2_2V_Y
1 128@ 2 DDR_B_MA11
1
C1484
R359 36_0201_1%
<6> DDR_B_CLK0
1
+ 1 128@ 2 DDR_B_MA9
1
128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ R367 36_0201_1% C1505
1 128@ 2 DDR_B_MA14 128@ 1.8P_0201_50V8C
2
R408 36_0201_1%
2
1 128@ 2 DDR_B_MA13
<6> DDR_B_CLK0#
R335 36_0201_1%
1 128@ 2 DDR_B_MA6
R350 36_0201_1% 1.CAD Note: Cterm= 1.6pF should be kept
1 128@ 2 DDR_B_MA7
4
R336 36_0201_1% near feeding point of first SDRAM 4
1 128@ 2 DDR_B_MA8
near U60 near U61 near U62 near U63 R344 36_0201_1%
1 128@ 2 DDR_B_MA15 2.CAD Note: Rtt= 30.1ohms, Ctt= 0.1uF
R390 36_0201_1% should be kept within 600mils from last SDRAM

2012/4/6 2013/4/6 Title
Issued Date Deciphered Date DDRIII DIMMB
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic
http://vinafix.vn
A B C D E
A B C D E
f ix
ina
PCH_RTCX1 +RTCBATT
1 2 PCH_RTCX2
1
1 R638 10M_0402_5%
R568
+RTCVCC C516 0_0603_5%
1U_0402_6.3V6K @ X1
2 2 1
1
1 2 PCH_RTCRST# 32.768KHZ_12.5PF_9H03200019
R338 20K_0402_5% SJ100004Z00
1 2 PCH_SRTCRST# 1 1 D5
R337 20K_0402_5% C756 C757 BAS40-04_SOT23-3
1 18P_0402_50V8J 18P_0402_50V8J +RTCVCC
1 1
2
C502 2 2
+CHGRTC
1U_0402_6.3V6K 1
2 C197
20MIL
0.1U_0402_16V4Z
2
RTC Battery:Chargeable
+RTCVCC
R353 1 2 1M_0402_5% SM_INTRUDER#
R347 1 2 330K_0402_5% PCH_INTVRMEN

INTVRMEN
* H ：Integrated VRM enable
L ：Integrated VRM disable
(INTVRMEN should always be pull high.)
U37A
+3VS PCH_RTCX1 A20 C38 LPC_AD0

RTCX1 FWH0 / LAD0 A38 LPC_AD0 <30,32>
@ LPC_AD1 CRB:10K ohm
LPC
FWH1 / LAD1 LPC_AD1 <30,32> +3VS
R405 1 2 1K_0402_5% PCH_SPKR PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 C37 LPC_AD3
LPC_AD2 <30,32> Check List 1.0:8.2K ohm
HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature PCH_RTCRST# D20 FWH3 / LAD3 LPC_AD3 <30,32>
SERIRQ R403 2 1 10K_0402_5%
RTCRST# D36 LPC_FRAME#
* LOW= Disable (Default internal PD) PCH_SRTCRST# G22 FWH4 / LFRAME# LPC_FRAME# <30,32>
PCH_SATALED# R662 2 1 10K_0402_5%
SRTCRST# E36
RTC
+VCCSUS3_3 @ R322 SM_INTRUDER# K22 LDRQ0# K36 PCH_GPIO23
2 INTRUDER# LDRQ1# / GPIO23 PCH_GPIO23 <18> 2
1K_0402_5%
2 1 HDA_SDOUT_PCH PCH_INTVRMEN C17 V5 SERIRQ
INTVRMEN SERIRQ SERIRQ <30,32>
<32> HDA_SDO 2 @ 1 AM3 SATA_PRX_DTX_N0 <29>

R320 0_0402_5% HDA_BITCLK_PCH N34 SATA0RXN AM1
HDA_BCLK SATA0RXP SATA_PRX_DTX_P0 <29>
SATA 6G
AP7
HDA_SDO HDA_SYNC_PCH L34 SATA0TXN AP5 SATA_PTX_DRX_N0 <29>
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 <29>
ME debug mode,this signal has a weak internal PD
Low = Disabled (Default) PCH_SPKR T10 AM10
* High = Enabled [Flash Descriptor Security Overide]
<33> PCH_SPKR SPKR SATA1RXN
SATA1RXP
AM8
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
<29>
<29>
HDA_RST_PCH# K34 AP11
HDA_RST# SATA1TXN AP10 SATA_PTX_DRX_N1 <29>
+VCCSUS3_3 SATA1TXP SATA_PTX_DRX_P1 <29>
<33> HDA_SDIN0 HDA_SDIN0 E34 AD7

R328 2 1 1K_0402_5% HDA_SYNC_PCH HDA_SDIN0 SATA2RXN AD5
G34 SATA2RXP AH5
This signal has a weak internal pull-down HDA_SDIN1 SATA2TXN AH4
C34 SATA2TXP
IHDA
HDA_SDIN2 AB8 +3VS
On Die PLL VR Select is supplied by A34 SATA3RXN AB10
Prevent back drive issue. HDA_SDIN3 SATA3RXP AF3
1.5V when smapled high
* SATA3TXN
1
+5VS AF1
HDA_SDOUT_PCH A36 SATA3TXP R687
1.8V when sampled low
SATA
HDA_SDO Y7 10K_0402_5%
Needs to be pulled High for Huron River platfrom SATA4RXN Y5
SATA4RXP
2
G
Q20 C36 AD3
2
BSS138W-7-F_SOT323-3 HDA_DOCK_EN# / GPIO33 SATA4TXN AD1 PCH_GPIO21
3 1 HDA_SYNC_PCH N32 SATA4TXP Switchable Graph
HDA_DOCK_RST# / GPIO13
2
1 R677 2 HDA_BITCLK_PCH Y3
S
<33> HDA_BITCLK_AUDIO
33_0402_5% R672 SATA5RXN Y1 R688 @
GPIO21
R302 51_0402_5% SATA5RXP AB3 10K_0402_5%
3 1 R676 2 HDA_SYNC_PCH_R 1 2 2 1 PCH_JTAG_TCK J3 SATA5TXN AB1
Switchable 0 3
<33> HDA_SYNC_AUDIO JTAG_TCK SATA5TXP
33_0402_5% @ 0_0402_5%
* Non SG 1
1
1
PCH_JTAG_TMS H7 Y11 R389 +1.05VS_PCH
JTAG
1 R673 2 HDA_RST_PCH# R468 JTAG_TMS SATAICOMPO 37.4_0402_1%
<33> HDA_RST_AUDIO#
33_0402_5% 1M_0402_5% PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
JTAG_TDI SATAICOMPI
<33> HDA_SDOUT_AUDIO 1 R665 2 HDA_SDOUT_PCH PCH_JTAG_TDO H1

2
33_0402_5% JTAG_TDO AB12 R388 +1.05VS_PCH

SATA3RCOMPO 49.9_0402_1%
AB13 SATA3_COMP 1 2
+3VALW_PCH +3VALW_PCH +3VALW_PCH PCH_SPI_CLK_0 2 1 SATA3COMPI +3VS
R739 33_0402_5%
1
PCH_SPI_CLK_1 2 1 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2

SPI_CLK SATA3RBIAS
1
R660 R659 R658 R704 33_0402_5% R650 750_0402_1%
@ 200_0402_5% @ 200_0402_5% @ 200_0402_5% PCH_SPI_CS0# Y14 R674
SPI_CS0# 4.7K_0402_5%
PCH_SPI_CS1# 2 1 PCH_SPI_CS1#_R T1
SPI
2
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI R733 0_0402_5% SPI_CS1# P3 PCH_SATALED#
2
PCH_SPI_MOSI_0 2 1 SATALED# PCH_GPIO19
1
R737 33_0402_5% V4 V14 PCH_GPIO21 No use PH 10K +3VS

R670 R669 PCH_SPI_MOSI_1 2 1 PCH_SPI_MOSI SPI_MOSI SATA0GP / GPIO21
@ @
R671
@ R734 33_0402_5% U3 P1 PCH_GPIO19
Debug Port DG 1.2 PH 4.7K +3VS
100_0402_1% 100_0402_1% 100_0402_1%
SPI_MISO SATA1GP / GPIO19 GPIO19 has internal Pull up
PCH_SPI_MISO_0 2 1 PCH_SPI_MISO
2
R736 33_0402_5% COUGARPOINT_FCBGA989~D Boot BIOS Strap

PCH_SPI_MISO_1 2 1 SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!
R738 33_0402_5% HM77@ Boot BIOS GPIO51 GPIO19
+3VS
U40
4MB=32Mb LPC 0 0
PCH_SPI_CS0# 1 8
R699 1 2 3.3K_0402_5% SPI_WP0# 3 CS# VCC 6 PCH_SPI_CLK_0
Reserved 0 1
+3VS
R700 1 2 3.3K_0402_5% SPI_HOLD0# 7 WP# SCLK 5 PCH_SPI_MOSI_0
Reserve for EMI @
4
4 HOLD# SI 2 PCH_SPI_MISO_0 @ C1216
- 1 0 4
GND SO PCH_SPI_CLK 1 R977 2 1 2
MX25L3206EM2I-12G_SO8 * SPI 1 1
SA00003K800 22_0402_5% 22P_0402_50V8J
+3VS
U42
2MB=16Mb Security Classification Compal Secret Data Compal Electronics, Inc.
PCH_SPI_CS1# 1 8 2012/4/6 2013/4/6 Title
PCH_SPI_MISO_1 2 CS#
SO
VCC
HOLD#
7 SPI_HOLD1# R701 2 1 3.3K_0402_5% +3VS
Issued Date Deciphered Date PCH (1/8) SATA,HDA,SPI, LPC, XDP
+3VS R703 1 2 3.3K_0402_5% SPI_WP1# 3 6 PCH_SPI_CLK_1
WP# SCLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
4 5 PCH_SPI_MOSI_1 Size Document Number Rev
GND SI AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
MX25L1606EM2I-12G_SO8
http://vinafix.vn
SA00003FO10 Date: Thursday, April 12, 2012 Sheet 13 of 51
A B C D E
A B C D E
f ix
ina
U37B +VCCSUS3_3
PCIE_PRX_DTX_N1 BG34 No use PH 10K +3VALW SMB_ALERT# R383 1 2 10K_0402_5%
v
<22> PCIE_PRX_DTX_N1 PERN1
PCIE_PRX_DTX_P1 BJ34 E12 SMB_ALERT#
<22> PCIE_PRX_DTX_P1 PERP1 SMBALERT# / GPIO11 SMB_ALERT# <33>
Card Reader C617 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_N1 AV32
<22> PCIE_PTX_C_DRX_N1 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_P1 AU32 PETN1 H14 PCH_SMBCLK PCH_SMBCLK 1 2
C678 R668 2.2K_0402_5%
<22> PCIE_PTX_C_DRX_P1 PETP1 SMBCLK
PH 2.2K +3VALW
PCIE_PRX_DTX_N2 BE34 C9 PCH_SMBDATA PCH_SMBDATA R664 1 2 2.2K_0402_5%
<28> PCIE_PRX_DTX_N2 PERN2 SMBDATA
Mini Card 1 PCIE_PRX_DTX_P2 BF34
<28> PCIE_PRX_DTX_P2 PERP2
C573 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_N2 BB32
On Board WLAN <28> PCIE_PTX_C_DRX_N2
C572 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_P2 AY32 PETN2 DRAMRST_CNTRL_PCH R648 1 2 1K_0402_5%
SMBUS
<28> PCIE_PTX_C_DRX_P2 PETP2 A12 DRAMRST_CNTRL_PCH
BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <11,12,6> 1 2
PCH_GPIO74 R647 10K_0402_5%
BJ36 PERN3 C8
1
AV34 PERP3 SML0CLK S3 reduse No use PH 10K +3VALW 1
AU34 PETN3 G12 PCH_SML1CLK R375 1 2 2.2K_0402_5%
PETP3 SML0DATA
BF36 PCH_SML1DATA R369 1 2 2.2K_0402_5%
BE36 PERN4
AY34 PERP4 C13 PCH_GPIO74 S3 reduse
BB34 PETN4 SML1ALERT# / PCHHOT# / GPIO74 No use PH 10K +3VALW PCH_GPIO47 1 2
R683 10K_0402_5%
PETP4 E14 PCH_SML1CLK
PCI-E*
PCIE_PRX_DTX_N5 BG37 SML1CLK / GPIO58
<24> PCIE_PRX_DTX_N5 BH37 PERN5 M16
PCIE_PRX_DTX_P5 PCH_SML1DATA PH 2.2K +3VALW
<24> PCIE_PRX_DTX_P5 PERP5 SML1DATA / GPIO75 +3VS
C681 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_N5 AY36 For TP
<24> PCIE_PTX_C_DRX_N5 1 2 0.1U_0201_10V6K BB36 PETN5
C682 PCIE_PTX_DRX_P5
<24> PCIE_PTX_C_DRX_P5 PETP5 R427
PCIE_PRX_DTX_N6 BJ38 4.7K_0402_5%
<24> PCIE_PRX_DTX_N6 PERN6
5
PCIE_PRX_DTX_P6 BG38 1 2
+3VS
Controller
<24> PCIE_PRX_DTX_P6 1 2 0.1U_0201_10V6K AU36 PERP6 M7
Thunderbolt C684 PCIE_PTX_DRX_N6
G
<24> PCIE_PTX_C_DRX_N6 1 2 0.1U_0201_10V6K AV36 PETN6 CL_CLK1 3 4
C683 PCIE_PTX_DRX_P6 PCH_SMBDATA D_CK_SDATA
<24> PCIE_PTX_C_DRX_P6 PETP6 D_CK_SDATA <33>
S
Q27A
Link
PCIE_PRX_DTX_N7 BG40 T11 DMN66D0LDW-7_SOT363-6
<24> PCIE_PRX_DTX_N7 PCIE_PRX_DTX_P7 BJ40 PERN7 CL_DATA1 R415
<24> PCIE_PRX_DTX_P7 1 2 0.1U_0201_10V6K AY40 PERP7
C686 PCIE_PTX_DRX_N7 4.7K_0402_5%
<24> PCIE_PTX_C_DRX_N7 PETN7
2
C685 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_P7 BB40 P10 1 2
<24> PCIE_PTX_C_DRX_P7 PETP7 CL_RST1# +3VS
G
PCIE_PRX_DTX_N8 BE38 PCH_SMBCLK 6 1 D_CK_SCLK
<24> PCIE_PRX_DTX_N8 PERN8 D_CK_SCLK <33>
S
PCIE_PRX_DTX_P8 BC38 Q27B
<24> PCIE_PRX_DTX_P8 1 2 0.1U_0201_10V6K AW 38 PERP8
C688 PCIE_PTX_DRX_N8 DMN66D0LDW-7_SOT363-6
<24> PCIE_PTX_C_DRX_N8 1 2 0.1U_0201_10V6K AY38 PETN8
C687 PCIE_PTX_DRX_P8
<24> PCIE_PTX_C_DRX_P8 PETP8
M10 PCH_GPIO47 +3VS
Y40 PEG_A_CLKRQ# / GPIO47 No use PH 10K +3VALW
Y39 CLKOUT_PCIE0N Pull up at EC side.
2 No use PH 10K +3VALW
CLKOUT_PCIE0P AB37 For DDR,EC 2
CLOCKS
CLKOUT_PEG_A_N
5
PCH_GPIO73 J2 AB38
PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P
G
PCH_SML1DATA 3 4 EC_SMB_DA2 EC_SMB_DA2 <11,24,32>
S
AB49 AV22 CLK_CPU_DMI# Q22A
<28> CLK_PCIE_MINI1# AB47 CLKOUT_PCIE1N CLKOUT_DMI_N AU22 CLK_CPU_DMI# <5>
Mini Card 1 CLK_CPU_DMI DMN66D0LDW-7_SOT363-6
<28> CLK_PCIE_MINI1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <5>
(On Board WLAN)
2
MINI1_CLKREQ# M1
<28> MINI1_CLKREQ# PCIECLKRQ1# / GPIO18 AM12 CLK_CPU_DPLL#
G
CLKOUT_DP_N / CLKOUT_BCLK1_N CLK_CPU_DPLL# <5>
No use PH 10K +3VS AM13 CLK_CPU_DPLL 120MHz for eDP. PCH_SML1CLK 6 1 EC_SMB_CK2 EC_SMB_CK2 <11,24,32>
CLKOUT_DP_P / CLKOUT_BCLK1_P CLK_CPU_DPLL <5>
S
AA48 Q22B
AA47 CLKOUT_PCIE2N DMN66D0LDW-7_SOT363-6
CLKOUT_PCIE2P BF18 CLK_BUF_CPU_DMI# R357 1 2 10K_0402_5%
TB_SMB_DA_GPIO6 V10 CLKIN_DMI_N BE18 CLK_BUF_CPU_DMI R358 1 2 10K_0402_5%
<24> TB_SMB_DA_GPIO6 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
No use PH 10K +3VS Y37 BJ30
CLKIN_GND1_N CLKIN_DMI2_N CLKIN_GND1# R330 1 2 10K_0402_5%
Y36 CLKOUT_PCIE3N BG30 CLKIN_GND1 R331 1 2 10K_0402_5%
CLKOUT_PCIE3P CLKIN_GND1_P CLKIN_DMI2_P
No use PH 10K +3VALW LAN_CLKREQ# A8
PCIECLKRQ3# / GPIO25 G24 CLK_BUF_DREF_96M# R346 1 2 10K_0402_5%
CLKIN_DOT_96N E24 CLK_BUF_DREF_96M R345 1 2 10K_0402_5%
Y43 CLKIN_DOT_96P Pull down 10K ohm
<22> CLK_PCIE_CARD# Y45 CLKOUT_PCIE4N for using internal Clock
Card Reader <22> CLK_PCIE_CARD CLKOUT_PCIE4P AK7 CLK_BUF_PCIE_SATA# R387 1 2 10K_0402_5%
CARD_CLKREQ# L12 CLKIN_SATA_N / CKSSCD_N AK5 CLK_BUF_PCIE_SATA R393 1 2 10K_0402_5%
<22> CARD_CLKREQ# PCIECLKRQ4# / GPIO26 CLKIN_SATA_P / CKSSCD_P
V45 K45 CLK_BUF_ICH_14M R292 1 2 10K_0402_5%

V46 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P
No use PH 10K +3VALW MINI2_CLKREQ# L14 H45 CLK_PCI_LPBACK
3 PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <17> 3
2 1 1 2
R293 33_0402_5% C421 22P_0402_50V8J
AB42 V47 XTAL25_IN @ @
AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT
CLKOUT_PEG_B_P XTAL25_OUT Reserve for EMI please close to PCH
No use PH 10K +3VALW PEG_CLKREQ# E6 +1.05VS_PCH
R289
PEG_B_CLKRQ# / GPIO56 90.9_0402_1%
Y47 XCLK_RCOMP 1 2
V40 XCLK_RCOMP
V42 CLKOUT_PCIE6N
CLKOUT_PCIE6P +3VS
No use PH 10K +3VALW PCH_GPIO45 T13
PCIECLKRQ6# / GPIO45
1
CLK_TB_REFCLK# V38 K43 CLK_FLEX0 @
<24> CLK_TB_REFCLK# CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 T52 PAD
CLK_TB_REFCLK V37 R610
FLEX CLOCKS
<24> CLK_TB_REFCLK CLKOUT_PCIE7P F47 CLK_FLEX1 @ UMA@ 10K_0402_5%

CLKOUTFLEX1 / GPIO65 T53 PAD
TB_CLKREQ# K12
<24> TB_CLKREQ# PCIECLKRQ7# / GPIO46 H47 CLK_FLEX2 @ PAD
T21
2
AK14 CLKOUTFLEX2 / GPIO66 DGPU_PRSNT#
AK14:CLKOUT_ITPXDP_N CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK13:CLKOUT_ITPXDP_P AK13 K49 DGPU_PRSNT#
CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67
1
XTAL25_IN
No use PH 10K +3VALW R628
COUGARPOINT_FCBGA989~D @ 10K_0402_5% XTAL25_OUT 1 2
SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! R611 1M_0402_5%
HM77@
2
+3VS 25MHZ_10PF_7V25000014
R424 2 1 10K_0402_5% MINI1_CLKREQ# 3 1

3 1
R686 2 1 10K_0402_5% TB_SMB_DA_GPIO6
GPIO67 1
GND GND
1
DGPU_PRSNT# 4 2
4 +VCCSUS3_3 C744 Y1 C745 4
Check List R1.0 p.37 DIS,Optimus 0 8.2P_0402_50V8D
2 2
8.2P_0402_50V8D
R652 2 1 10K_0402_5% PCH_GPIO73
Clock Req# pull high power source
R399 2 1 10K_0402_5% LAN_CLKREQ#
UMA 1
R684 2 1 10K_0402_5% CARD_CLKREQ#
R410 2 1 10K_0402_5% MINI2_CLKREQ# 2012/4/6 2013/4/6 Title
Issued Date Deciphered Date PCH (2/8) PCIE, SMBUS, CLK
R400 2 1 10K_0402_5% PEG_CLKREQ#
R414 2 1 10K_0402_5% PCH_GPIO45 Custom 1.0
http://vinafix.vn
R425 2 1 10K_0402_5% TB_CLKREQ# Date: Thursday, April 12, 2012 Sheet 14 of 51
A B C D E
A B C D E
f ix U37C
ina
DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0
+VCCSUS3_3 <4> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <4>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
v
<4> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <4>
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
R378 2 1 10K_0402_5% PCH_GPIO30 BC12 FDI_CTX_PRX_N4
FDI_RXN4 FDI_CTX_PRX_N4 <4>
DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5
<4> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <4>
R402 2 1 10K_0402_5% PCH_GPIO72 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
R649 2 1 10K_0402_5% RI# DMI_CTX_PRX_P3 BJ20
<4> DMI_CTX_PRX_P3 DMI3RXP BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 <4>
R373 2 1 200_0402_5% PM_DRAM_PWRGD DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1
<4> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <4>
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
+3VALW_PCH <4> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <4>
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3
1 <4> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <4> 1
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4
DMI
FDI
<4> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <4>
R341 2 @ 1 10K_0402_5% PCH_ACIN BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <4>
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6
<4> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <4>
R634 2 1 10K_0402_5% PCH_RSMRST# DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7
<4> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <4>
DMI_CRX_PTX_P2 AY18
<4> DMI_CRX_PTX_P2 AU18 DMI2TXP
DMI_CRX_PTX_P3
<4> DMI_CRX_PTX_P3 DMI3TXP AW16 FDI_INT +RTCVCC
FDI_INT FDI_INT <4>
+1.05VS_PCH BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <4> 2 1 330K_0402_5%
DSWODVREN R361
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <4> 2 1 330K_0402_5%
R625 49.9_0402_1% R360 @
1 2 DMI2RBIAS BH21 AV14 FDI_LSYNC0
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <4>
：
R632 750_0402_1% DSWODVREN - On Die DSW VR Enable
BB10 FDI_LSYNC1 H Enable internal DSW +1.05VS
FDI_LSYNC1 FDI_LSYNC1 <4> *
4mil width and place
within 500mil of the PCH ：
L Disable
Must always PH at +RTCVCC
A18 DSWODVREN
DSWVRMEN
System Power Management

1 S3@ 2 PCH_RSMRST# not support Deep S4,S5 DPWROK mux with RSMRST#
not support Deep S4,S5 mux 1 @ 2 SUSACK#_R C12 E22 R426 0_0402_5%
<32> SUSACK# SUSACK# DPWROK
R372 0_0402_5% 1 @ 2 DPWROK
DPWROK <32>
check list1.0 P.42
with SUS_PWR_DN_ACK R421 0_0402_5%
1 @ 2 XDP_DBRESET#_R K3 B9 PCH_PCIE_WAKE#
<5> XDP_DBRESET# SYS_RESET# WAKE# PCH_PCIE_WAKE# <24,28>
R661 0_0402_5%
CRB=>1k ohm
SYS_PWROK P12 N3 CLKRUN# +VCCSUS3_3
SYS_PWROK CLKRUN# / GPIO32 CLKRUN# <30> No use PH 10K +3VS Follow Check List R1.5
not support AMT APWROK can mux PCH_PCIE_WAKE# R656 1 2 10K_0402_5%
with PWROK (check list1.0 P.40) PCH_PWROK 1 @ 2 PCH_PWROK_R L22 G8 SUS_STAT# T15 PAD
R382 0_0402_5% PWROK SUS_STAT# / GPIO61 @
2 @ R973 PCH_GPIO29 R395 1 @ 2 10K_0402_5% 2
L10 N14 SUSCLK_R 1 2 0_0402_5%
APWROK SUSCLK / GPIO62 SUSCLK <32> +3VS
PM_DRAM_PWRGD B13 D10 PM_SLP_S5# CLKRUN# R653 1 2 8.2K_0402_5%

<5> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <32>
PCH_RSMRST# C21 H4 PM_SLP_S4#

<32> PCH_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <32>
Can be left NC
<32> SUSWARN#
1 @ 2 PCH_GPIO30 K16 F4 PM_SLP_S3#
PM_SLP_S3# <32>
when IAMT is not DPWROK
R412 0_0402_5% SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3#
support on the
1
<32> PBTN_OUT#
PBTN_OUT# E20
PWRBTN# SLP_A#
G10 SLP_A# T51 PAD platfrom
@ R463
not support 100K_0402_5%
1 2 PCH_ACIN 1 @ 2 PCH_ACIN H20 G16 SLP_SUS#
<32> ACPRESENT <32,35,38,39> ACIN SLP_SUS# <32>
R456 0_0402_5% D19 RB751V-40_SOD323-2 ACPRESENT / GPIO31 SLP_SUS# Deep S4,S5 can NC
2
PCH_GPIO72 E10 AP14 H_PM_SYNC
PCH EDS1.2 P.74
No use PH 10K +3VALW BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <5>
Ring Indicator CRB1.0 PH 10K +3VALW RI# A10 K14 PCH_GPIO29 No use PH 10K +3VALW
是是是是NC
RI# SLP_LAN# / GPIO29
COUGARPOINT_FCBGA989~D
SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!
HM77@
3 3
+3VS ALL power OK

tell PCH all power ok
but cpu core
5
U39
2
P
<32> PCH_PWROK B 4 SYS_PWROK

1 Y SYS_PWROK <5> SYS_PWROK
<43> VGATE A
G
1
MC74VHC1G08DFT2G_SC70-5 1 1
3
R680 R681 C603

10K_0402_5% 10K_0402_5% C789
.047U_0402_16V7K 100P_0402_50V8J
@ 2 2
2
4 4
VGATE VGATE
1 1
C790 C791
100P_0402_50V8J 100P_0201_25V8J Security Classification Compal Secret Data Compal Electronics, Inc.
2 2
2012/4/6 2013/4/6 Title
Issued Date Deciphered Date PCH (3/8) DMI,FDI,PM
Custom 1.0
http://vinafix.vn
A B C D E
A B C D E
f ix
ina
UMA Panel Backlight ON/OFF
v <32> ENBKL
ENBKL R612 2 @ 1 0_0402_5% IGPU_BKLT_EN
U37D
PD 100K IGPU_BKLT_EN J47 AP43
at EC side M45 L_BKLTEN SDVO_TVCLKINN AP45
<22> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
P45 AM42
<22> DPST_PWM L_BKLTCTL SDVO_STALLN AM40
T40 SDVO_STALLP
1 K47 L_DDC_CLK AP39 1
Delete LVDS function L_DDC_DATA SDVO_INTN AP40
T45 SDVO_INTP SDVO_CTRLDATA strap pull high
P39 L_CTRL_CLK at level shift page
L_CTRL_DATA
AF37 P38 SDVO_SCLK
LVD_IBG SDVO_CTRLCLK SDVO_SCLK <23>
AF36 M39 SDVO_SDATA
LVD_VBG SDVO_CTRLDATA SDVO_SDATA <23>
AE48
AE47 LVD_VREFH AT49
LVD_VREFL DDPB_AUXN AT47
DDPB_AUXP AT40 PCH_DPB_HPD
DDPB_HPD PCH_DPB_HPD <23>
AK39
LVDS
AK40 LVDSA_CLK# AV42 PCH_DPB_N0
LVDSA_CLK DDPB_0N PCH_DPB_N0 <23>
AV40 PCH_DPB_P0 PCH_DPB_P0 <23> HDMI D2
AN48 DDPB_0P AV45 PCH_DPB_N1
LVDSA_DATA#0 DDPB_1N PCH_DPB_N1 <23>
AM47 AV46 PCH_DPB_P1 HDMI D1
Digital Display Interface

LVDSA_DATA#1 DDPB_1P PCH_DPB_P1 <23>
AK47 AU48 PCH_DPB_N2 PCH_DPB_N2 <23>
AJ48 LVDSA_DATA#2 DDPB_2N AU47 PCH_DPB_P2
LVDSA_DATA#3 DDPB_2P AV47 PCH_DPB_N3
PCH_DPB_P2 <23> HDMI D0
DDPB_3N PCH_DPB_N3 <23>
AN47 AV49 PCH_DPB_P3 PCH_DPB_P3 <23> HDMI CLK
AM49 LVDSA_DATA0 DDPB_3P
AK49 LVDSA_DATA1
AJ47 LVDSA_DATA2 P46
LVDSA_DATA3 DDPC_CTRLCLK P42
DDPC_CTRLDATA
AF40
AF39 LVDSB_CLK# AP47
2 LVDSB_CLK DDPC_AUXN 2
AP49
AH45 DDPC_AUXP AT38
AH47 LVDSB_DATA#0 DDPC_HPD
LVDS disable: AF49 LVDSB_DATA#1 AY47
DATA/Clock/Control can NC AF45 LVDSB_DATA#2 DDPC_0N AY49
LVDSB_DATA#3 DDPC_0P AY43
VCC_TX_LVDS,VCCA_LVDS connected to GND AH43 DDPC_1N AY45
AH49 LVDSB_DATA0 DDPC_1P BA47
AF47 LVDSB_DATA1 DDPC_2N BA48
AF43 LVDSB_DATA2 DDPC_2P BB47
LVDSB_DATA3 DDPC_3N BB49
DDPC_3P
N48 M43 PCH_DPD_CLK

CRT_BLUE DDPD_CTRLCLK PCH_DPD_CLK <25>
P49 M36 PCH_DPD_DAT
CRT_GREEN DDPD_CTRLDATA PCH_DPD_DAT <25>
T49
CRT_RED
CRT disable: AT45 PCH_DPD_AUXN PCH_DPD_AUXN <24>
CRT
T39 DDPD_AUXN AT43 PCH_DPD_AUXP
CRT_DDC_CLK DDPD_AUXP PCH_DPD_AUXP <24>
DATA/Clock/Control can NC M40 BH41 DPD_HPD
DPD_HPD <24>
CRT_DDC_DATA DDPD_HPD
DAC_IREF still need PD BB43 PCH_DPD_N0
DDPD_0N PCH_DPD_N0 <24>
VCCADAC connected to +3VS M47 BB45 PCH_DPD_P0 PCH_DPD_P0 <24>
M49 CRT_HSYNC DDPD_0P BF44 PCH_DPD_N1
CRT_VSYNC DDPD_1N PCH_DPD_N1 <24>
BE44 PCH_DPD_P1
DDPD_1P BF42 PCH_DPD_N2
PCH_DPD_P1 <24> Thunderbolt
DDPD_2N PCH_DPD_N2 <24>
CRT_IREF T43 BE42 PCH_DPD_P2 PCH_DPD_P2 <24>
T42 DAC_IREF DDPD_2P BJ42 PCH_DPD_N3
3 PCH_DPD_N3 <24> 3
CRT_IRTN DDPD_3N BG42 PCH_DPD_P3
DDPD_3P PCH_DPD_P3 <24>
1
For CRT diable
R307 COUGARPOINT_FCBGA989~D
=>Change 1K 0.5% to 5% 1K_0402_5% SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!
HM77@
+3VS
R252 1 2 2.2K_0402_5% PCH_DPD_CLK
R254 1 2 2.2K_0402_5% PCH_DPD_DAT
4 4

2012/4/6 2013/4/6 Title
Issued Date Deciphered Date PCH (4/9) LVDS,CRT,DP,HDMI
http://vinafix.vn
Custom 1.0
A B C D E
A B C D E
f ix
v ina +3VS
U37E
NV_CE#0
NV_CE#1
AY7
AV7
BG26 AU3
R423 1 2 8.2K_0402_5% PCI_PIRQC# BJ26 TP1 NV_CE#2 BG4
R428 1 2 8.2K_0402_5% PCI_PIRQB# BH25 TP2 NV_CE#3
R431 1 2 8.2K_0402_5% PCI_PIRQA# BJ16 TP3 AT10
R432 1 2 8.2K_0402_5% PCI_PIRQD# BG16 TP4 NV_DQS0 BC8
AH38 TP5 NV_DQS1
AH37 TP6 AU2
DMI,FDI Termination Voltage
AK43 TP7 NV_DQ0 / NV_IO0 AT4
1 AK45 TP8 NV_DQ1 / NV_IO1 AT3
Set to Vcc when HIGH 1
1 2 C18 TP9 NV_DQ2 / NV_IO2 AT1
DF_TVS
R433 8.2K_0402_5% PCH_GPIO55 Set to Vss when LOW
R434 1 2 8.2K_0402_5% PCH_GPIO53 N30 TP10 NV_DQ3 / NV_IO3 AY3
R435 1 2 8.2K_0402_5% PCH_GPIO52 H3 TP11 NV_DQ4 / NV_IO4 AT5
R439 1 2 8.2K_0402_5% PCH_GPIO5 AH12 TP12 NV_DQ5 / NV_IO5 AV3 DG1.2 CRB1.0 PH 2.2K series 1K
NVRAM
AM4 TP13 NV_DQ6 / NV_IO6 AV1
AM5 TP14 NV_DQ7 / NV_IO7 BB1 For 2012 support
Y13 TP15 NV_DQ8 / NV_IO8 BA3
K24 TP16 NV_DQ9 / NV_IO9 BB5 +1.8VS
R442 1 2 8.2K_0402_5% PCH_GPIO51 L24 TP17 NV_DQ10 / NV_IO10 BB3
R443 1 2 8.2K_0402_5% PCH_GPIO2 AB46 TP18 NV_DQ11 / NV_IO11 BB7
TP19 NV_DQ12 / NV_IO12
1
R444 1 2 8.2K_0402_5% ODD_DA# AB45 BE8
RSVD
R445 1 2 8.2K_0402_5% PCH_GPIO4 TP20 NV_DQ13 / NV_IO13 BD4 R651
NV_DQ14 / NV_IO14 BF6 2.2K_0402_5%
+3VS NV_DQ15 / NV_IO15
B21 AV5
2
R267 1 2 10K_0402_5% DGPU_PWR_EN M20 TP21 NV_ALE AY1 DF_TVS 2 1
TP22 NV_CLE H_SNB_IVB# <5>
AY16 R654 1K_0402_5%
+3VS BG46 TP23 AV10
TP24 NV_RCOMP
AT8
CLOSE TO THE BRANCHING POINT
R310 1 2 8.2K_0402_5% DGPU_HOLD_RST# NV_RB#
PCH_USB3_RX1_N BE28 BE28:USB3Rn1 AY5
<31> PCH_USB3_RX1_N TP25 BC30:USB3Rn2 NV_RE#_WRB0
PCH_USB3_RX2_N BC30 BA2
<31> PCH_USB3_RX2_N TP26 BE32:USB3Rn3 NV_RE#_WRB1
BE32
BJ32 TP27 BJ32:USB3Rn4 AT12
PCH_USB3_RX1_P BC28 TP28 BC28:USB3Rp1 NV_WE#_CK0 BF3
<31> PCH_USB3_RX1_P TP29 BE30:USB3Rp2 NV_WE#_CK1
PCH_USB3_RX2_P BE30
<31> PCH_USB3_RX2_P TP30 BF32:USB3Rp3
BF32
BG32 TP31 BG32:USB3Rp4 C24 USB20_N0
USB3.0 PCH_USB3_TX1_N AV26 TP32 AV26:USB3Tn1 USBP0N A24 USB20_P0 USB20_N0 <31> USB3 ( side)
<31> PCH_USB3_TX1_N PCH_USB3_TX2_N BB26 TP33 BB26:USB3Tn2 USBP0P C25 USB20_N1 USB20_P0 <31>
2 <31> PCH_USB3_TX2_N AU28 TP34 AU28:USB3Tn3 USBP1N B25 USB20_P1 USB20_N1 <31> USB3 ( side) 2
AY30 TP35 AY30:USB3Tn4 USBP1P C26 USB20_P1 <31>
Boot BIOS Strap PCH_USB3_TX1_P AU26 TP36 AU26:USB3Tp1 USBP2N A26
USB3 ( side)
<31> PCH_USB3_TX1_P AY26 TP37 AY26:USB3Tp2 USBP2P K28
GPIO19 GPIO51 Boot BIOS PCH_USB3_TX2_P USB3 ( side)
<31> PCH_USB3_TX2_P AV28 TP38 AV28:USB3Tp3 USBP3N H28
TP39 AW30:USB3Tp4 USBP3P
Bit11 Bit10 Destination AW30
TP40 USBP4N
E28
D28
EHCI 1
GNT1#/ USBP4P C28
GPIO51 0 1 Reserved USBP5N A28
USBP5P C29
1 0 PCI USBP6N B29
Internal PCI_PIRQA# K40 USBP6P N28
1 1 SPI * PCI_PIRQB# K38 PIRQA# USBP7N M28
Some PCH config not support USB port 6 & 7.
PH PCI Interrupt Requests
PCI
PCI_PIRQC# H38 PIRQB# USBP7P L30 USB20_N8
0 0 LPC PCI_PIRQD# G38 PIRQC# USBP8N K30 USB20_P8 USB20_N8 <28>
PIRQD# USBP8P G30 USB20_N9 USB20_P8 <28> WLAN USB(Bluetooth)
C46 USBP9N E30 USB20_N9 <31>
Used as GPIO only. External pull-up of DGPU_HOLD_RST# USB20_P9 Debug Port
USB
C44 REQ1# / GPIO50 USBP9P C30 USB20_P9 <31>
PCH_GPIO52 USB20_N10
8.2 kOhms to 10 kOhms to +V3.3S required. E40 REQ2# / GPIO52 USBP10N A30 USB20_N10 <22>
DGPU_PWR_EN USB20_P10 CMOS Camera (LVDS)
REQ3# / GPIO54 USBP10P L32 USB20_P10 <22>
Only GPIO USBP11N
EHCI 2
PCH_GPIO51 D47 K32
無無如如GPIO PH +3VS
function Used as GPIO only. PCH_GPIO53 E42 GNT1# / GPIO51 USBP11P G32
PH(Internal PH), PCH_GPIO55 F46 GNT2# / GPIO53 USBP12N E32 Mini Card (mSATA)
GNT3# / GPIO55 USBP12P C32
USBP13N A32
PCH_GPIO2 G42 USBP13P
ODD_DA# G40 PIRQE# / GPIO2
PCH_GPIO4 C42 PIRQF# / GPIO3 C33 USBRBIAS 1 2
PCH_GPIO5 D44 PIRQG# / GPIO4 USBRBIAS# R620 22.6_0402_1%
PIRQH# / GPIO5
B33
Within 500 mils
PAD T13 @ K10 USBRBIAS +VCCSUS3_3
3 PME# 3
PLT_RST# C6 A14 USB_OC0# USB_OC0# 2 1
<22,24,30,32,5> PLT_RST# PLTRST# OC0# / GPIO59 K20 USB_OC1# USB_OC0# <31>
R384 10K_0402_5%
OC1# / GPIO40 B17 USB_OC2# USB_OC2# 2 1
CLK_PCI_LPBACK R604 2 1 22_0402_5% CLK_PCI0 H49 OC2# / GPIO41 C16 USB_OC3# R401 10K_0402_5%
<14> CLK_PCI_LPBACK CLK_PCI_LPC 1 2 22_0402_5% CLK_PCI1 H43 CLKOUT_PCI0 OC3# / GPIO42 L16 USB_OC4# USB_OC7# 2 1
R316
<32> CLK_PCI_LPC 1 2 22_0402_5% J48 CLKOUT_PCI1 OC4# / GPIO43 A16
CLK_PCI_TXM R327 CLK_PCI2 USB_OC5# R374 10K_0402_5%
<30> CLK_PCI_TXM CLKOUT_PCI2 OC5# / GPIO9
PAD T7 @ CLK_PCI3 K42 D14 USB_OC6# USB_OC5# 2 1
PAD T8 @ CLK_PCI4 H40 CLKOUT_PCI3 OC6# / GPIO10 C14 USB_OC7# R379 10K_0402_5%
CLKOUT_PCI4 OC7# / GPIO14
COUGARPOINT_FCBGA989~D +VCCSUS3_3
HM77@ USB_OC1# 2 1
R448 10K_0402_5%
R371 USB_OC4# 2 1
0_0402_5% R447 10K_0402_5%
2 1 USB_OC3# 2 1
@ R386 10K_0402_5%
USB_OC6# 2 1
+3VS R446 10K_0402_5%
5
U26
PLT_RST# 2
P
B 4
1 2 IRST_RST_R# 1 Y PLT_RST_BUF# <28>
A
G
R462 @ 0_0402_5%
R376
3
<32> IRST_RST#
IRST_RST# R461 1 2 0_0402_5% 100K_0402_5%
MC74VHC1G08DFT2G_SC70-5
2
4 4

2012/4/6 2013/4/6 Title
Issued Date Deciphered Date PCH (5/9) PCI, USB, NVRAM
Custom 1.0
http://vinafix.vn
A B C D E
A B C D E
f ix
HDA_SYNC PH(PLL =+1.5VS)
ina
+3VS +3VS +3VS Project ID GPIO69 GPIO70
LVDS/eDP GPIO71
GPIO28 * x 0 0
v LVDS 1
1
On-Die PLL Voltage Regulator @
R615 @R616
@ R616 @R617
@ R617 x 0 1
eDP 0
：：
This signal has a weak internal pull up 10K_0402_5% 10K_0402_5% 10K_0402_5%
H On-Die PLL voltage regulator enable
x 1 0
* L On-Die PLL Voltage Regulator disable x 1 1
2
PCH_GPIO71 PCH_GPIO69 PCH_GPIO70
不不不
For eDP only,
2
+VCCSUS3_3 eDP or LVDS @
R618 R619 R621
10K_0402_5% 10K_0402_5% 10K_0402_5%
1
1 1
R422
1
4.7K_0402_5%
2
PCH_GPIO28 U37F
2
No use PH 10K +3VS TB_PLUG_EVENT T7 C40 ODD_EN#

<24> TB_PLUG_EVENT BMBUSY# / GPIO0 TACH4 / GPIO68
R417
@ 1K_0402_5% No use PH 10K +3VS PCH_GPIO1 A42 B41 PCH_GPIO69
TACH1 / GPIO1 TACH5 / GPIO69
DGPU_HPD_INT# H36 C41 PCH_GPIO70 +3VS
No use PH 10K +3VS
1
TACH2 / GPIO6 TACH6 / GPIO70

Debug Port DG 1.2 PH 4.7K +3VALW_PCH EC_SCI# E38 A40 PCH_GPIO71
<32> EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71
2
EC_SMI# C10 R419
<32> EC_SMI# GPIO8
10K_0402_5%
Deep S4,S5 wake event signal No use PH +3VALW TB_FORCE_PWR C4
<24> TB_FORCE_PWR LAN_PHY_PWR_CTRL / GPIO12
1
RTC alarm,Power BTN,GPIO27 EC LID SW OUT <32> EC_LID_OUT#
EC_LID_OUT# G2 P4
GATEA20 <32>
GPIO15 A20GATE
PCH_GPIO27 (Have internal Pull-High) No use PH +3VALW AU16 PCH_PECI_R 1 2
@ PECI CPU-EC
CPU/MISC
Deep S4,S5 wake event signal MSATA_DET# U2 PECI H_PECI <32,5>
No use PH +3VS <29> MSATA_DET# 0_0402_5% R248
SATA4GP / GPIO16 P5 EC_KBRST#
No use PD to GND,HR Check list1.0 P.70 RCIN# EC_KBRST# <32> CTRL+ALT+DEL
GPIO
DGPU_PWROK D40 AY11 non CPU power ok
1 2 10K_0402_5% PCH_GPIO27 TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <5>
R362
No use PH 10K +3VS PCH_GPIO22 T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP# 130c shut sown
SCLOCK / GPIO22 THRMTRIP# H_THRMTRIP# <5>
HR Check List R385 390_0402_5%
CRB1.0 PH 10K +3VALW PCH_GPIO24 E8 T14
GPIO24 / MEM_LED INIT3_3V#
PCH_GPIO27 E16
2
No use PD 10K to GND GPIO27 INIT3_3V Check list1.0 P.59 +3VS 2
No use PH 10K +3VALW PCH_GPIO28 P8 This signal has weak internal

R363 1 2 10K_0402_5% ODD_DETECT# GPIO28 AH8
No use PH 10K +3VS PCH_GPIO34 K1 NC_1 PU, can't pull low,leave NC ODD_EN# R324 1 2 10K_0402_5%
STP_PCI# / GPIO34 AK11
R364 1 2 10K_0402_5% WWAN_OFF# RAID0_DET K4 NC_2 EC_KBRST# R420 1 2 10K_0402_5%
No use can NC(+3VS power plane) <29> RAID0_DET GPIO35 AH10
ODD_DETECT# V8 NC_3 TS_VSS1~4
Can't PH SATA2GP / GPIO36 AK10 PD to GND
WWAN_OFF# M5 NC_4
Can't PH SATA3GP / GPIO37 P37
OPTIMUS_EN# N2 NC_5
SATA2GP/GPIO36,SATA3GP/GPIO37 No use PH 10K +3VS Optimus(L)/ non optimus(H) SLOAD / GPIO38
1.Used as for Mechanical Presence detect - PCH_GPIO39 M3
Use a weak external pull-up (150K-200k Ohms) to Vcc3_3 No use PH 10K +3VS SDATAOUT0 / GPIO39
or use 10K external pull-up that is enabled only No use PH 10K +3VS PCH_GPIO48 V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
after PLTRST# de-assertion.
SATA5GP&TEMP_ALERT# CRB PH 10K +3VS TB_SMB_CK_GPIO7 V3 BG48
<24> TB_SMB_CK_GPIO7 SATA5GP / GPIO49 VSS_NCTF_16
2.Used as GP Input (Pin HW default) - PCH_GPIO57 D6 BH3
No use PH +3VALW GPIO57 VSS_NCTF_17
Ensure GPI is not driven high during strap sampling window
BH47
VSS_NCTF_18
3.Unused as GPIO or SATA*GP - A4 BJ4
Use 8.2K-10K pull-down to ground. +3VS VSS_NCTF_1 VSS_NCTF_19
A44 BJ44
UMA@ VSS_NCTF_2 VSS_NCTF_20
+3VS R429 1 2 10K_0402_5% OPTIMUS_EN# A45 BJ45
VSS_NCTF_3 VSS_NCTF_21
NCTF
R406 1 @ 2 10K_0402_5% TB_PLUG_EVENT @ A46 BJ46
R430 1 2 10K_0402_5% VSS_NCTF_4 VSS_NCTF_22
R614 1 2 10K_0402_5% PCH_GPIO1 A5 BJ5
3 VSS_NCTF_5 VSS_NCTF_23 3
R326 1 2 10K_0402_5% DGPU_HPD_INT# A6 BJ6
VSS_NCTF_6 VSS_NCTF_24 GPIO39 GPIO23 GPIO22
R663 1 2 10K_0402_5% MSATA_DET# B3 C2
GPIO38 VSS_NCTF_7 VSS_NCTF_25 Elpida DDP 1GB*8 (Ch A,B) 0 0 0
R305 1 2 10K_0402_5% DGPU_PWROK B47 C48
OPTIMUS_EN# VSS_NCTF_8 VSS_NCTF_26 Elpida DDP 1GB*4 (Ch A) 0 0 1
BD1 D1
Muxless 0 VSS_NCTF_9 VSS_NCTF_27 Elpida Mono 512MB*8(Ch A,B) 0 1 0
BD49 D49
* nonMuxless 1 VSS_NCTF_10 VSS_NCTF_28 Hynix Mono 512MB*8(Ch A,B) 0 1 1
BE1 E1
R675 1 2 10K_0402_5% PCH_GPIO34 VSS_NCTF_11 VSS_NCTF_29
BE49 E49
R679 1 2 10K_0402_5% PCH_GPIO48
Define Q5LJ1(DDR3) or Q3ZMC(DDR3L) VSS_NCTF_12 VSS_NCTF_30
+VCCSUS3_3 BF1 F1 +3VS
R404 1 2 10K_0402_5% TB_SMB_CK_GPIO7 VSS_NCTF_13 VSS_NCTF_31 R274 1 X76@ 2 10K_0402_5% PCH_GPIO22
R458 1 2 10K_0402_5% PCH_GPIO24 BF49 F49
DDR3@ VSS_NCTF_14 VSS_NCTF_32
R275 1 X76@ 2 10K_0402_5%
R457 1 2 10K_0402_5% COUGARPOINT_FCBGA989~D
DDR3L@ SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!
HM77@ R278 1 X76@ 2 10K_0402_5% PCH_GPIO23
PCH_GPIO23 <13>
+VCCSUS3_3 GPIO24
PCH_GPIO24 R279 1 X76@ 2 10K_0402_5%
Remove NCTF test point
R657 1 @ 2 10K_0402_5% TB_FORCE_PWR
* DDR3L(Q3ZMC) 0 2011/9/23
R281 1 X76@ 2 10K_0402_5% PCH_GPIO39
R391 1 2 1K_0402_5% EC_LID_OUT# DDR3 1
4 R397 1 2 10K_0402_5% PCH_GPIO57 R282 1 X76@ 2 10K_0402_5% 4
GPIO36/GPIO37 is Strap functionality

that requires internal pull down to be sampled at rising PWROK.
When uses as SATA2GP/SATA3GP for mechanical presence detect
GPIO24 Unmultiplexed -use a external pull up 150K-200K ohm to Vcc3_3
NOTE: GPIO24 configuration When used as GP input Security Classification Compal Secret Data Compal Electronics, Inc.
register bits are not cleared by -ensure GPI is not driven high during strap sampling window 2012/4/6 2013/4/6 Title
When Unused as GPIO or SATA*GP
Issued Date Deciphered Date PCH (6/9) GPIO, CPU, MISC
CF9h reset event. -use 8.2K-10K pull-down THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRB1.0 PH10K to +3VALW Size Document Number Rev
check list page 47 Custom 1.0
http://vinafix.vn
A B C D E
A B C D E
f ix
ina
Thermal Senser share with VCCADAC power rail
so can't remove this power
v
+1.05VS_VCCPP U37G
PPT:1700mA
POWER
PPT:63mA L23
+3VS
J3 @ Place Near U48 MBK1608221YZF_2P

2 1 +1.05VS_PCH AA23 CPT:1300mA CPT:1mA U48 +VCCADAC 2 1
AC23 VCCCORE[1] VCCADAC
VCCCORE[2] 1 1 1
10U_0603_6.3V6M
C754
1U_0201_4V6M
C519
1U_0201_4V6M
C517
0.1U_0201_10V6K
C505
CRT
1 1 1 AD21 C419 C420 C418
PAD-OPEN 4x4m VCCCORE[3]
1
AD23 U47 10U_0603_6.3V6M
JUMP_43X79 AF21 VCCCORE[4] VSSADAC 0.01U_0402_16V7K .1U_0402_16V7K
VCC CORE
AF23 VCCCORE[5] 2 2 2
1 2 2 2 2 AG21 VCCCORE[6] +3VS 1
AG23 VCCCORE[7]
AG24 VCCCORE[8] AK36 +VCCA_LVDS R272 1 LVDS@ 2 0_0402_5%
AG26 VCCCORE[9] 1mA VCCALVDS
VCCCORE[10]
1
Place Near AA23 AG27 AK37
AG29 VCCCORE[11] VSSALVDS R270
AJ23 VCCCORE[12] 0_0402_5%
LVDS
AJ26 VCCCORE[13] AM37 eDP@
AJ27 VCCCORE[14] VCCTX_LVDS[1]
2
AJ29 VCCCORE[15] AM38 +1.8VS
AJ31 VCCCORE[16] VCCTX_LVDS[2]
VCCCORE[17] AP36
Place Near AM37 +VCCTX_LVDS R271 1 LVDS@ 2 0_0402_5%
+1.05VS_PCH 40mA VCCTX_LVDS[3]
1
AP37
AN19 VCCTX_LVDS[4] R280
VCCIO[28] 0_0402_5%
eDP@
PAD T33 @ +VCCAPLLEXP BJ22 +3VS
2
VCCAPLLEXP
On-Die PLL Voltage Regulator V33
HVCMOS
：On-Die PLL voltage regulator enable
AN16 VCC3_3[6]
VCCIO[15] Place Near V33
H AN17 228mA 1
VCCIO[16] V34
I/O Buffer Voltage
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 PPT:3711mA C449
VCC3_3[7]
0.1U_0201_10V6K
,VCCAPLLSATA AN21 CPT:3709mA 2
VCCIO[17]
AN26
PCH Power Rail Table
VCCIO[18] PPT:167mA
CPT:175mA S0 Iccmax
AN27 AT16 Voltage Rail Voltage
VCCIO[19] VCCVRM[3] +VCCAFDI_VRM Current(A)
+1.05VS_PCH AP21 +1.05VS_PCH
Internal PLL and VRM(+1.5VS)
2 VCCIO[20] PPT:47mA 2
AP23 CPT:42mA AT20
V_PROC_IO 1.05 0.001 Processor I/F
VCCIO[21] VCCDMI[1] Trace 20mil
1 DMI buffer logic
DMI
+1.05VS_PCH
10U_0603_6.3V6M
C543
1U_0201_4V6M
C496
1U_0201_4V6M
C486
1U_0201_4V6M
C474
1U_0201_4V6M
C492
1 1 1 1 1 AP24 C477 V5REF 5 0.001 PCH Core Well Reference Voltage

VCCIO
VCCIO[22] 1U_0201_4V6M
@ AP26 AB36
VCCIO[23] VCCIO[1] 2
2 2 2 2 2 1 place V5REF_Sus 5 0.001 Suspend Well Reference Voltag
AT24 C480 Core Well I/O Buffer
VCCIO[24] 1U_0201_4V6M near AT20
2
place Vcc3_3 3.3 0.266 I/O Buffer Voltage
AN33
VCCIO[25] near AB36
Place Near AN16,AN21,AN33 AN34 AG16
Display DAC Analog Power. This power is
+3VS VCCIO[26] 2mA VCCPNAND[1] +1.8VS
VccADAC 3.3 0.001 supplied by the core well.
VccDFTERM should PH +1.8VS or +3VS
NAND / SPI
BH29 AG17 VccADPLLA 1.05 0.08 Display PLL A power

VCC3_3[3] VCCPNAND[2]
1 1
C749 C523
0.1U_0201_10V6K AJ16 0.1U_0201_10V6K VccADPLLB 1.05 0.08 Display PLL B power
VCCPNAND[3]
Place Near 2 AP16 2
+VCCAFDI_VRM VCCVRM[2] place
BH29 AJ17 VccCore 1.05 1.3 Internal Logic Voltage
VCCPNAND[4] near AG16
@ +1.05VS_VCCAPLL_FDI BG6
PAD T14 VCCFDIPLL VCCPNAND change to VccDFTERM
+1.05VS_PCH +3VS
VccDMI 1.05 0.042 DMI Buffer Voltage
AP17
VCCIO[27]
FDI
V1 For SPI control logi VccIO 1.05 2.925 Core Well I/O buffers
10mA VCCSPI
AU20
1
C491 VCCDMI[2] 1 1.05 V Supply for Intel R Management
VccASW 1.05 1.01 Engine and Integrated LAN
1U_0201_4V6M C770
3 COUGARPOINT_FCBGA989~D 1U_0402_6.3V6K 3
2 SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! 2
Near VccSPI 3.3 0.02 3.3 V Supply for SPI Controller Logic
HM77@
AU20
Trace 20mil VccDSW 3.3 0.003 3.3v supply for Deep S4/S5 well
On-Die PLL Voltage Regulator
H ：On-Die PLL voltage regulator enable VccpNAND 1.8 0.19 1.8V power supply for DF_TVS
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA VccRTC 3.3 6 uA Battery Voltage
+VCCAFDI_VRM
+1.5VS
VccSus3_3 3.3 0.266 Suspend Well I/O Buffer Voltage
High Definition Audio Controller Suspend
R394 1 @ 2 0_0402_5% +VCCAFDI_VRM VccSusHDA 3.3 / 1.5 0.01 Voltage
1.8 V Internal PLL and VRMs (1.8 V for
VCCVRM==>1.5V FOR MOBILE VccVRM 1.8 / 1.5 0.16 Desktop)
VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec VccCLKDMI 1.05 0.02 DMI Clock Buffer Voltage
配HDA_SYNC PH(PLL =+1.5VS) VccSSC 1.05 0.095 Spread Modulators Power Supply
VccDIFFCLKN 1.05 0.055 Differential Clock Buffers Power Supply

Analog power supply for LVDS (Mobile
4
VccALVDS 3.3 0.001 Only) 4
Analog power supply for LVDS (Mobile

VccTX_LVDS 1.8 0.06 Only)

2012/4/6 2013/4/6 Title
Issued Date Deciphered Date PCH (7/9) PWR
Custom 1.0
http://vinafix.vn
A B C D E
A B C D E
ix
For Deep SX turn off +V5REF_SUS,+VCCSUS3_3
f
ina
+1.05VS_PCH 20mil 10mil
+3VS +1.05V analog +3VALW +VCCSUS3_3 +5VALW +V5REF_SUS
@ R273
v
internal clock PLL 1 2 +VCCACLK
Can NC 0_0402_5%
+3VALW_PCH
L26
10UH_LB2012T100MR_20% 3 1 3 1
1 2 +3VS_VCC_CLKF33 1 U37J POWER +1.05VS_PCH
1
.1U_0402_16V7K
C817
20K_0402_5%
R755
.1U_0402_16V7K
C816
20K_0402_5%
R752
1 1 Not support Deep S4,S5 C520 Q68 1 Q64 1
1U_0402_6.3V6K
C440
C465 0.1U_0201_10V6K AD49 N26 AP2301GN-HF_SOT23-3 DS3@ AP2301GN-HF_SOT23-3 DS3@
10U_0603_6.3V6M connect to +3VALW VCCACLK VCCIO[29]
1
2
2 P26 1 R756 2 PCH_PWR_EN# 1 R757 2
2 2 T16 VCCIO[30] <35> PCH_PWR_EN# 2 2
Near T16 C468 2.2K_0402_5% 1K_0402_5%
1mA 1 1
2
1 VCCDSW3_3 P28 1U_0201_4V6M 1
VCCIO[31] 2 C819 C820
Near T38 suppied by internal PAD T12 @ +PCH_VCCDSW V12 T27 Near N26 0.01U_0402_16V7K 0.01U_0402_16V7K
DCPSUSBYP VCCIO[32] 2 2
1.05V VR must NC T29
+3VS_VCC_CLKF33 T38 VCCIO[33] +VCCSUS3_3
VCC3_3[5]
GPIO28 T23
Deep S3 VCCSUS3_3[7]
On-Die PLL Voltage Regulator PAD T32 @ +VCCAPLL_CPY_PCH BH23

VCCAPLLDMI2 PPT:126mA T24 1 1
H +1.05VS_PCH
AL29
VCCIO[14] CPT:119mA VCCSUS3_3[8] C490 C497
V23 0.1U_0201_10V6K 0.1U_0201_10V6K
USB
VCCSUS3_3[9]
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 +VCCSUS1 AL24 V24 2 Near T23 2 Near P24 +VCCSUS3_3 +V5REF_SUS
suppied by internal PAD T9 @
,VCCAPLLSATA DCPSUS[3] VCCSUS3_3[10]
1.05V VR must NC P24
VCCSUS3_3[6]
1
+1.05VS_PCH
AA19 D16 R334
VCCASW[1] T26 RB751V-40_SOD323-2 100_0402_5%
+1.05VS_PCH AA21 903mA VCCIO[34]
Near M26
VCCASW[2]
2
AA24 M26 +PCH_V5REF_SUS
1 1
VCCASW[3] 1mA V5REF_SUS 1 2
+3VS +5VS
22U_0805_6.3V6M
C547
22U_0805_6.3V6M
C552
AA26
Clock and Miscellaneous

C484
VCCASW[4] AN23 +VCCA_USBSUS T11 0.1U_0402_16V4Z
AA27 DCPSUS[4] PAD @
VCCASW[5]
1
2 2 AN24
AA29 VCCSUS3_3[1] +VCCSUS3_3 suppied by internal D14 R321
VCCASW[6] 1.05V VR Must NC RB751V-40_SOD323-2 100_0402_5%
AA31
VCCASW[7]
2
AC26 P34 +PCH_V5REF_RUN
2
1 1 1
VCCASW[8] 1mA V5REF +VCCSUS3_3
1
2
1U_0201_4V6M
C518
1U_0201_4V6M
C478
1U_0201_4V6M
C513
AC27
VCCASW[9] N20 C470
VCCSUS3_3[2]
PCI/GPIO/LPC
@ AC29 1 1U_0603_10V6K
2 2 2 VCCASW[10] N22 C501 2
AC31 VCCSUS3_3[3] 0.1U_0201_10V6K
VCCASW[11] P20
AD29 VCCSUS3_3[4] 2 Near P34
+1.05VS_PCH VCCASW[12] P22
Near N20 +3VS
L54
10UH_LB2012T100MR_20% AD31 VCCSUS3_3[5]
1 2 +1.05VS_VCCA_A_DPL
Near AA19 VCCASW[13]
W21 AA16
VCCASW[14] VCC3_3[1]
1U_0201_4V6M
C426
1 1 1
1 1 W23 W16 C771 C522 C471
VCCASW[15] VCC3_3[8]
22U_0805_6.3V6M
C751
Near BD47 0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K

W24 T34
VCCASW[16] VCC3_3[4] 2 Place near 2 Place near 2 Place near
2 2 W26 AJ2 AA16,W16 T34
VCCASW[17]
W29
VCCASW[18]
1 2 +1.05VS_VCCA_B_DPL W31 AJ2 +1.05VS_PCH
L49 VCCASW[19] VCC3_3[2]
1U_0201_4V6M
C429
10UH_LB2012T100MR_20% W33
VCCASW[20] AF13
1 1 Near N16 VCCIO[5] Near AH13,AH14,AF13
22U_0805_6.3V6M
C752
Near BF47 2 1 +VCCRTCEXT N16

1
C521 0.1U_0201_10V6K DCPRTC AH13 C533
2 2 VCCIO[12] 1U_0201_4V6M
Y49 AH14 2
+VCCAFDI_VRM VCCVRM[4] VCCIO[13]
3 AF14
GPIO28 3
+1.05VS_VCCA_A_DPL BD47 VCCIO[6]
VCCADPLLA PPT:80mA On-Die PLL Voltage Regulator
SATA
AK1 +VCCSATAPLL @ T48 PAD
+1.05VS_PCH +1.05VS_VCCA_B_DPL BF47 CPT:75mA VCCAPLLSATA
H
VCCADPLLB
AF11 VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
+1.05VS_PCH VCCVRM[1] +VCCAFDI_VRM
AF17
AF33 VCCIO[7] ,VCCAPLLSATA
AF34 VCCIO[8] AC16 +1.05VS_PCH
1 C524 VCCIO[9] 55mA VCCIO[2]
1U_0201_4V6M AG34
+1.05VS_PCH VCCIO[11] AC17
1 C467 VCCIO[8,9,11] change to VccDIFFCLKN VCCIO[3] Near AC16
2
Place 1U_0201_4V6M VCCIO[10] change to VccSSC
AG33 AD17
near AF17 1 C476
VCCIO[10] 95mA VCCIO[4] 1
C482
2 Place 1U_0201_4V6M 1U_0201_4V6M
near AF33, Near V16 2 1 +VCCSST V16 +1.05VS_PCH
DCPSST 2
AF34,AG34 2
Place C526 0.1U_0201_10V6K
near AG33 PAD T10 +1.05VM_VCCSUS T17 T21
V19 DCPSUS[1] VCCASW[22]
DCPSUS[2]
MISC
suppied by internal @
+1.05VS_PCH V21
1.05V VR Must NC VCCASW[23]
1mA
CPU
isolation between SSC (AG33) BJ8

V_PROC_IO T19
and DIFFCLKN(AF33,AF34,AG34) 1 1 1
VCCASW[21]
+RTCVCC +VCCSUS3_3
4.7U_0603_6.3V6K
C544
0.1U_0201_10V6K
C537
0.1U_0201_10V6K
C541
18mil width(DIFFCLKN)
10mil (SSC)
RTC
A22 10mA P32 Need +3VALW and 0.1U close PCH

HDA
2 2 2 VCCRTC VCCSUSHDA
1U_0402_6.3V6K
C493
0.1U_0201_10V6K
C494
0.1U_0201_10V6K
C495
1 1 1 1
COUGARPOINT_FCBGA989~D C473
4 SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! 0.1U_0201_10V6K 4
HM77@
2 2 2 2
Place
near BJ8 Near P32
Near A22 Security Classification Compal Secret Data Compal Electronics, Inc.
2012/4/6 2013/4/6 Title
Issued Date Deciphered Date PCH (8/9) PWR
Custom 1.0
http://vinafix.vn
A B C D E
A B C D E
fix
vina
U37I
AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
1 U37H B15 VSS[163] VSS[263] K7 1
H5 B19 VSS[164] VSS[264] L18
VSS[0] B23 VSS[165] VSS[265] L2
AA17 AK38 B27 VSS[166] VSS[266] L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
AB11 VSS[5] VSS[84] AL16 F45 VSS[171] VSS[271] M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
AC48 VSS[18] VSS[97] AM14 BC2 VSS[184] VSS[284] N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
AD11 VSS[20] VSS[99] AM39 BC26 VSS[186] VSS[286] N47
AD19 VSS[23] VSS[102] AM46 BC36 VSS[189] VSS[289] T33
AD26 VSS[25] VSS[104] AN2 BC42 VSS[191] VSS[291] P43
AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
AD34 VSS[28] VSS[107] AN31 BD5 VSS[194] VSS[294] R2
2 AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48 2
AD37 VSS[30] VSS[109] AP19 BE26 VSS[196] VSS[296] T12
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
AD40 VSS[34] VSS[113] AP38 BF16 VSS[200] VSS[300] W34
AD46 VSS[38] VSS[117] AP8 BF26 VSS[204] VSS[304] V11
AD8 VSS[39] VSS[118] AR2 BF28 VSS[205] VSS[305] V17
AE2 VSS[40] VSS[119] AR48 BD3 VSS[206] VSS[306] V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
AF12 VSS[43] VSS[122] AT18 BF40 VSS[209] VSS[309] V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
AD16 VSS[45] VSS[124] AT26 BG17 VSS[211] VSS[311] V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
AF24 VSS[48] VSS[127] AT32 BG44 VSS[214] VSS[314] W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
AF27 VSS[50] VSS[129] AT39 BH11 VSS[216] VSS[316] W2
AF38 VSS[53] VSS[132] AT7 BH19 VSS[219] VSS[319] Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
AF42 VSS[55] VSS[134] AU30 BH27 VSS[221] VSS[321] Y4
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF8 VSS[59] VSS[138] AV30 BH39 VSS[225] VSS[325] BG29
AG19 VSS[60] VSS[139] AV38 BH43 VSS[226] VSS[328] N24
3 AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3 3
AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47
AG48 VSS[63] VSS[142] AV8 D12 VSS[229] VSS[331] B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
AH3 VSS[65] VSS[144] AW18 D18 VSS[231] VSS[334] BG41
AH36 VSS[66] VSS[145] AW2 D22 VSS[232] VSS[335] G14
AH39 VSS[67] VSS[146] AW22 D24 VSS[233] VSS[337] H16
AH40 VSS[68] VSS[147] AW26 D26 VSS[234] VSS[338] T36
AH7 VSS[71] VSS[150] AW34 D34 VSS[237] VSS[343] C22
AJ19 VSS[72] VSS[151] AW36 D38 VSS[238] VSS[344] AP13
AJ21 VSS[73] VSS[152] AW40 D42 VSS[239] VSS[345] M14
AJ24 VSS[74] VSS[153] AW48 D8 VSS[240] VSS[346] AP3
AJ33 VSS[75] VSS[154] AV11 E18 VSS[241] VSS[347] AP1
AJ34 VSS[76] VSS[155] AY12 E26 VSS[242] VSS[348] BE16
AK12 VSS[77] VSS[156] AY22 G18 VSS[243] VSS[349] BC16
AK3 VSS[78] VSS[157] AY28 G20 VSS[244] VSS[350] BG28
VSS[79] VSS[158] G26 VSS[245] VSS[351] BJ28
COUGARPOINT_FCBGA989~D G28 VSS[246] VSS[352]
SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! G36 VSS[247]
HM77@ G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
4 4
COUGARPOINT_FCBGA989~D
HM77@

2012/4/6 2013/4/6 Title
Issued Date Deciphered Date PCH (9/9) VSS
Custom 1.0
http://vinafix.vn
A B C D E
5 4 3 2 1
f ix Panel POWER CIRCUIT

vina +LCDVDD +3VALW +3VS
SM010014520 3000ma
220ohm@100mhz
W=60mils DCR 0.04 W=40mils
1
R6 B+ L1 +INVPWR_B+
1
2
R5 10K_0402_5% C479 FBMA-L11-201209-221LMA30T_0805
300_0603_5% 4.7U_0603_6.3V6K 2 1
2
2
D D
R2
1
3
3
1K_0402_5%
Q1A
D
5 2 1 2 AP2301GN-HF_SOT23-3
1 1
G
DMN66D0LDW-7_SOT363-6 S C7 C11
Q28 68P_0402_50V8J 680P_0402_50V7K
1
4
C2 +LCDVDD
.047U_0402_16V7K 2 2
W=60mils
1
6
2 G
D
2
<16> PCH_ENVDD S Q1B 1 1
DMN66D0LDW-7_SOT363-6 C562 C10
1
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
1
2 2
R4
100K_0402_5% eDP panel + Card Reader Conn.

2
+INVPWR_B+ W=40mils
JLVDS1
1
2 1
3 2
4 3
5 4
C 20mils +3VALW
6 5 C
7 6
ON/OFFBTN# 8 7
<33> ON/OFFBTN# 8
<32> LID_SW# LID_SW# 9
10 9
11 10
40mils +3VS
12 11
DPST_PWM C5 1 2 100P_0201_25V8J PLT_RST# 13 12
<16> DPST_PWM <17,24,30,32,5> PLT_RST# 13
CARD_CLKREQ# 14
<14> CARD_CLKREQ# 14
R86 1 2 10K_0402_5% 15
PCIE_PTX_C_DRX_P1 16 15
<14> PCIE_PTX_C_DRX_P1 16
<14> PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_N1 17
18 17
PCIE_DTX_C_PRX_P1 19 18
<14> PCIE_PRX_DTX_P1 19
PCIE_DTX_C_PRX_N1 20
<14> PCIE_PRX_DTX_N1 20
21
CLK_PCIE_CARD 22 21
<14> CLK_PCIE_CARD 22
BKOFF# C8 1 2 100P_0201_25V8J @ D15 <14> CLK_PCIE_CARD# CLK_PCIE_CARD# 23
6 3 USB20_P10 24 23
R18 1 2 10K_0402_5% I/O4 I/O2 USB20_P10 25 24
<17> USB20_P10 25
USB20_N10 26
<17> USB20_N10 26
+3VS 27
5 2 BKOFF# 28 27
+3VS VDD GND <32> BKOFF# 28
DPST_PWM 29
EDP_HPD 30 29
31 30
USB20_N10 4 1 32 31
B I/O3 I/O1 32 B
60mils +LCDVDD 33
AZC099-04S.R7G_SOT23-6 34 33
0.1U_0201_10V6K 1 2eDP@ C912 EDP_TXP1_C 35 34
<4> EDP_TXP1 35
0.1U_0201_10V6K 1 2eDP@ C913 EDP_TXN1_C 36 41
<4> EDP_TXN1 36 G1
0.1U_0201_10V6K 1 2eDP@ C910 EDP_TXP0_C 37 42
<4> EDP_TXP0 37 G2
0.1U_0201_10V6K 1 2eDP@ C911 EDP_TXN0_C 38 43
<4> EDP_TXN0 38 G3
<4> EDP_AUXP 0.1U_0201_10V6K 1 2eDP@ C914 EDP_AUXP_C 39 44
0.1U_0201_10V6K 1 2eDP@ C915 EDP_AUXN_C 40 39 G4 45
<4> EDP_AUXN 40 G5
ACES_50398-04071-001
CONN@
<4> EDP_HPD#
To LED/B Conn.
1
eDP@ D
Q29 2 EDP_HPD
SSM3K7002FU_SC70-3 G ACES_88058-060N
1
S 8
3
eDP@ 7 GND
R480 GND
100K_0402_5% 20mils +3VALW 6
BATT_BLUE_LED# 5 6
<32> BATT_BLUE_LED#
2
BATT_AMB_LED# 4 5
<32> BATT_AMB_LED# 4
<32> PWR_LED# PWR_LED# 3
PWR_SUSP_LED# 2 3
<32> PWR_SUSP_LED# 2
A 1 A
1
JLED1
CONN@

Issued Date 2012/4/6 Deciphered Date 2013/4/6 Title
LVDS Connector
Custom 1.0
http://vinafix.vn
5 4 3 2 1
5 4 3 2 1
f ix
vina W=40mils
+HDMI_5V_OUT
F1
+5VS 1 2
1
1.1A_6VDC_FUSE
C345
0.1U_0402_16V4Z
2
D D
<16> PCH_DPB_N0 C280 2 1 .1U_0402_16V7K HDMI_TX2-

<16> PCH_DPB_P0 C281 2 1 .1U_0402_16V7K HDMI_TX2+


<16> PCH_DPB_N3 C285 2 1 .1U_0402_16V7K HDMI_CLK-

<16> PCH_DPB_P3 C284 2 1 .1U_0402_16V7K HDMI_CLK+
+HDMI_5V_OUT
C C
+3VS
+3VS
R250 1 2 2.2K_0402_5% SDVO_SCLK
2
R253 1 2 2.2K_0402_5% SDVO_SDATA @

R785 HDMI_TX2- R592 1 2 680_0402_5% HDMI_GND
0_0402_5% HDMI_TX2+ R594 1 2 680_0402_5%
Pull high at connector side
2
2
1
2.2K_0402_5% HDMI_TX1- R583 1 2 680_0402_5%
2.2K_0402_5%
HDMI_TX1+ R587 1 2 680_0402_5%
R257
R255
HDMI_TX0- R564 1 2 680_0402_5%
5
HDMI_TX0+ R570 1 2 680_0402_5%

1
1
G
SDVO_SCLK 4 3 HDMI_SCLK HDMI_CLK- R573 1 2 680_0402_5%

<16> SDVO_SCLK
S
HDMI_CLK+ R590 1 2 680_0402_5%

2
Q16A
DMN66D0LDW-7_SOT363-6
G
6
SDVO_SDATA 1 6 HDMI_SDATA
<16> SDVO_SDATA
S
2
D
+3VS
G Q14B
Q16B S
1
B Place closed to JHDMI1 B
HDMI connector
+3VS JHDMI1
HDMI_HPD 19
18 HP_DET
+HDMI_5V_OUT +5V
17
HDMI_SDATA 16 DDC/CEC_GND
SDA
1
HDMI_SCLK 15
R198 14 SCL
1M_0402_5% 13 Reserved
HDMI_CLK- 12 CEC
CK-
5
Q14A 11
2
DMN66D0LDW-7_SOT363-6 HDMI_CLK+ 10 CK_shield

G
4 3 HDMI_HPD HDMI_TX0- 9 CK+

<16> PCH_DPB_HPD D0-
S
8
HDMI_TX0+ 7 D0_shield
1 D0+
1
C324 HDMI_TX1- 6
R219 100P_0201_25V8J 5 D1-
100K_0402_5% HDMI_TX1+ 4 D1_shield 20
2 HDMI_TX2- 3 D1+ GND 21
2 D2- GND 22
2
HDMI_TX2+ 1 D2_shield GND 23

D2+ GND
A CONCR_099AMAC19CBACNF A
CONN@

HDMI Connector
Custom
Q3ZMC M/B LA-8481P Schematic 1.0
http://vinafix.vn
5 4 3 2 1
fix
+3VS_LC +3VS_LC CRYSTAL_P
+3VS_LC
a
CRYSTAL_N +3VS_POC
n
TB@
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
1 2 1 @ 2 2.2K_0402_5%
0.1U_0402_16V4Z
TB_SMB_DA R1036
1
R1101 1M_0402_5% R1066 2 @ 1 10K_0402_5% TB_SMB_CK R1037 1 @ 2 2.2K_0402_5%
1
1 3.3K_0402_5%
R1024
R1025
R1026
25MHZ_10PF_7V25000014 TB_GO2SX R1048 2 TB@ 1 10K_0402_5% TB_SMB_DA R1046 1 TB@ 2 2.2K_0402_5%
C1331
TB_SMB_CK R1047 1 TB@ 2 2.2K_0402_5%

R1023
U65 TB@ 3 1
2
2 3 1
6.8P_0402_50V8C
6.8P_0402_50V8C
TB@ TB@ TB@
2
TB@ 8 1 EE_CS_N GND GND intra pair skew: 5 mil.

VCC CS# 1 1
TB@ 7 2 EE_DO TB@ TB@ inter pair skew: 10 mil +3VS_LC
EE_CLK 6 HOLD# SO 3 C1338 4 Y2 2 C1340
EE_DI 5 SCK WP# 4 TB@
SI GND 2 2 U66A TMU_CLK_IN R1033 2 TB@ 1 10K_0402_5%
2
@ AD23 N6 PCIE_RST_0_N @ PAD T76

R1018 AT25512N-SH-T_SO8 AC24 MONDC0 PCIe_RST_0_N T1 PCIE_RST_1_N @ PAD T77 TB_CLKREQ#_R R1031 2 TB@ 1 10K_0402_5%
0_0402_5% SA00005G500 MONDC1 PCIe_RST_1_N Y5 PCIE_RST_2_N @ PAD T78
W18 PCIe_RST_2_N U2 PCIE_RST_3_N @ PAD T79
W16 MONOBS_P PCIe_RST_3_N W6 TB_CLKREQ#_R +3VS_POC
INTEL Recommend 32K EEPROM
1
MONOBS_N PCIE_CLKREQ_OD_N
0.01U_0402_16V7K
1 EE_DI R4 AA4
ATMEL: AT25512(64KB):SA000055T00 EE_DI TMU_CLK_OUT
C1330
EE_DO P5 Y3 TMU_CLK_IN EN_CIO_PWR# R1034 2 TB@ 1 10K_0402_5%

AT25256B(32KB):SA00005G500
EE_CLK 2 TB@
EE_CS_N
1 EE_CLK_R
AD3
W4
EE_DO
EE_CS_N
MISC TMU_CLK_IN
G2 PA_HV_EN
TB_OK2GO2SX#
PA_DP_PWRDN
R1029
R1035
2
2
TB@
TB@
1
1
10K_0402_5%
10K_0402_5%
2
CAT:CAT25256VI-GT3(32KB):SA00005DB00 EE_CLK GPIO_0__PA_HV_EN__BYP0 PA_HV_EN <45>
@ R1038 0_0402_5% M1 TB_GPIO1 TB_GPIO13 R1028 2 TB@ 1 10K_0402_5%
N4 GPIO_1__PB_HV_EN__BYP0 Y1 TB_GO2SX
AB5 TEST_EN GPIO_2__GO2SX W2 TB_GO2SX <32> 2 TB@ 1 1K_0402_5%
TB_FORCE_PWR_R PA_HV_EN R1040
TEST_PWR_GOOD GPIO_3 J4 TB_WAKE# R1097 2 TB@ 1 0_0402_5% TB_GPIO1 R1027 2 TB@ 1 10K_0402_5%
GPIO_4_WAKE_OD_N TB_FORCE_PWR <18>
R1032 1 TB@ 2 1K_0402_1% U20 AA2 CIO_PLUG_EVENT
W20 RSENSE GPIO_5_CIO_PLUG_EVENT AB1 TB_SMB_DA R1039 2 TB@ 1 0_0402_5% TB_FORCE_PWR_R R1041 2 TB@ 1 10K_0402_5%
RBIAS GPIO_6_OD__CIO_SDA_OD AC2 TB_SMB_CK PCH_PCIE_WAKE# <15,28>
CRYSTAL_P AA24 GPIO_7_OD__CIO_SCL_OD P3 EN_CIO_PWR#
+3VS_LC AB23 XTAL_25_IN GPIO__8_EN_CIO_PWR_N_OD M5 EN_CIO_PWR# <27> 2 1
CRYSTAL_N TB_OK2GO2SX# TB_GPIO11 R1042 TB@ 10K_0402_5%
XTAL_25_OUT GPIO_9__OK2GO2SX_N_OD M3 PA_CIO_SEL TB_OK2GO2SX# <32> TB_GPIO14 2 1
R1043 TB@ 10K_0402_5%
1 2 CR_JTCK AA6 GPIO_10__PA_CIO_SEL__BYP1 L2 TB_GPIO11 PA_CIO_SEL <25> TB_GPIO15 2 1
10K_0402_5% TB@ R1019 R1044 TB@ 10K_0402_5%
10K_0402_5% 1 TB@ 2 R1020 CR_JTMS AB3 TCK GPIO_11__PB_CIO_SEL__BYP1 H3 PA_DP_PWRDN EN_LC_PWR R1045 1 TB@ 2 100K_0402_5%
1 2 V1 TMS GPIO_12__PA_DP_PWRDN__BYP2 L4 PA_DP_PWRDN <25>
10K_0402_5% TB@ R1021 CR_JTDI TB_GPIO13
10K_0402_5% 1 TB@ 2 R1022 CR_TDO R2 TDI GPIO_13__PB_DP_PWRDN__BYP2 T3 TB_GPIO14
TDO GPIO_14 V5 TB_GPIO15
Y7 GPIO_15 J2 TB_PWRON_POC_RST# EC control~~ trig after SUSP# asserted for 30ms
U4 THERMDA PWR_ON_POC_RSTN K5 EN_LC_PWR TB_PWRON_POC_RST# <32>
NC EN_LC_PWR EN_LC_PWR <42>
<16> PCH_DPD_P3
PCH_DPD_P3 C1332 TB@2 1 0.1U_0201_10V6K PCH_DPD_P3_C E14 A14
PCH_DPD_N3 C1333 TB@2 1 0.1U_0201_10V6K PCH_DPD_N3_C D13 DPSNK0_3_P DPSRC_3_P B15
<16> PCH_DPD_N3 DPSNK0_3_N DPSRC_3_N TB_SMB_CK R1129 2 TB@ 1 0_0402_5%
TB_SMB_CK_GPIO7 <18>
<16> PCH_DPD_P2
PCH_DPD_N2 C1335 TB@2 1 0.1U_0201_10V6K PCH_DPD_N2_C D15 DPSNK0_2_P DPSRC_2_P B13 TB_SMB_DA R1128 2 TB@ 1 0_0402_5%
<16> PCH_DPD_N2 DPSNK0_2_N DPSRC_2_N TB_SMB_DA_GPIO6 <14>
<16> PCH_DPD_P1
PCH_DPD_N1 C1337 TB@2 1 0.1U_0201_10V6K PCH_DPD_N1_C D17 DPSNK0_1_P DPSRC_1_P B11
<16> PCH_DPD_N1
SOURCE PORT 0
DPSNK0_1_N DPSRC_1_N
SINK PORT 0
TB_SMB_CK R1131 2 @ 1 0_0402_5%
EC_SMB_CK2 <11,14,32>
<16> PCH_DPD_P0 PCH_DPD_P0 C1339 TB@2 1 0.1U_0201_10V6K PCH_DPD_P0_C E20 A8
PCH_DPD_N0 C1341 TB@2 1 0.1U_0201_10V6K PCH_DPD_N0_C D19 DPSNK0_0_P DPSRC_0_P B9 TB_SMB_DA R1130 2 @ 1 0_0402_5%
<16> PCH_DPD_N0 DPSNK0_0_N DPSRC_0_N EC_SMB_DA2 <11,14,32>
Display Port
<16> PCH_DPD_AUXP
PCH_DPD_AUXP C1342 TB@2 1 0.1U_0201_10V6K PCH_DPD_AUXP_C A6 C2
PCH_DPD_AUXN C1343 TB@2 1 0.1U_0201_10V6K PCH_DPD_AUXN_C B5 DPSNK0_AUX_P DPSRC_AUX_P D3
<16> PCH_DPD_AUXN DPSNK0_AUX_N DPSRC_AUX_N
DPD_HPD U6 V3
<16> DPD_HPD DPSNK0_HPD DPSRC_HPD_OD
TO PCH +3VS_POC +3VS_POC
2
E6 TB@ TB@
TB@ D5 DPSNK1_3_P R1050 C1344
DPSNK1_3_N
1
R1049 10K_0402_5% TB@ 2 1
100K_0402_5% E8 R1051
D7 DPSNK1_2_P 10K_0402_5% 0.1U_0402_16V4Z
2
1
DPSNK1_2_N TB@
5
E10 U67
2
D9 DPSNK1_1_P 2
P
DPSNK1_1_N B
SINK PORT 1
4 TB_PLUG_EVENT
Y TB_PLUG_EVENT <18>
3
E12 TB@ CIO_PLUG_EVENT 1
DPSNK1_0_P A
G
D11 5
D
EN_CIO_PWR# G Q89A
DPSNK1_0_N MC74VHC1G08DFT2G_SC70-5
S
3
A4
4
B3 DPSNK1_AUX_P
DPSNK1_AUX_N
T75PAD @ DPSNK1_HPD T5
DPSNK1_HPD
PCIE_PRX_DTX_P5 C1345 TB@2 1 0.1U_0201_10V6K PCIE_PRX_C_DTX_P5 AD5 AB9 PCIE_PTX_C_DRX_P5

<14> PCIE_PRX_DTX_P5 PETP_0 PERP_0 PCIE_PTX_C_DRX_P5 <14>
PCIE_PRX_DTX_N5 C1346 TB@2 1 0.1U_0201_10V6K PCIE_PRX_C_DTX_N5 AD7 AA10 PCIE_PTX_C_DRX_N5
<14> PCIE_PRX_DTX_N5 PETN_0 PERN_0 PCIE_PTX_C_DRX_N5 <14>
PCIE_PRX_DTX_P6 C1347 TB@2 1 0.1U_0201_10V6K PCIE_PRX_C_DTX_P6 AD9 AA12 PCIE_PTX_C_DRX_P6 +3VS_LC
<14> PCIE_PRX_DTX_P6 PETP_1 PERP_1 PCIE_PTX_C_DRX_P6 <14>
PCIE_PRX_DTX_N6 C1348 TB@2 1 0.1U_0201_10V6K PCIE_PRX_C_DTX_N6 AD11 AB13 PCIE_PTX_C_DRX_N6
TRANSMIT
<14> PCIE_PRX_DTX_P7
PCIE_PRX_DTX_P7 C1349 TB@2 1 0.1U_0201_10V6K PCIE_PRX_C_DTX_P7 AD13
PETP_2
PCIe PERP_2
AB15 PCIE_PTX_C_DRX_P7
PCIE_PTX_C_DRX_P7 <14>
2
RECEIVE
PCIE_PRX_DTX_N7 C1350 TB@2 1 0.1U_0201_10V6K PCIE_PRX_C_DTX_N7 AD15 AA16 PCIE_PTX_C_DRX_N7 TB@
G
PCIE_PRX_DTX_P8 C1351 TB@2 1 0.1U_0201_10V6K PCIE_PRX_C_DTX_P8 AD17 AA18 PCIE_PTX_C_DRX_P8 TB_CLKREQ#_R 1 6 TB_CLKREQ#
<14> PCIE_PRX_DTX_P8 PETP_3 PERP_3 PCIE_PTX_C_DRX_P8 <14> TB_CLKREQ# <14>
PCIE_PRX_DTX_N8 C1352 TB@2 1 0.1U_0201_10V6K PCIE_PRX_C_DTX_N8 AD19 AB19 PCIE_PTX_C_DRX_N8
D
Q89B
1 2 PERST# R6 AB21 CLK_TB_REFCLK DMN66D0LDW-7_SOT363-6
<17,22,30,32,5> PLT_RST# PERST_N REFCLK_100_IN_P AD21 CLK_TB_REFCLK# CLK_TB_REFCLK <14>
R1052 0_0402_5%
REFCLK_100_IN_N CLK_TB_REFCLK# <14>
TB@ R1053
2 1
CACTUS-RIDGE_FCBGA288 @
TB@ SA00005QT20 0_0402_5%

Intel Thunderbolt(1/4)
Size Document Number
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Q3ZMC M/B LA-8481P Schematic
http://vinafix.vn
fix
SEL/HPD_SEL PA_CFG1_LSEO0 PA_CFG1_LSEO0
Function /AUX_SEL
2
+3VS_POC
a
U68
Port A is active L TB@ TB@ TB@ TB@
G
n
G
i
3 31 PA_DPSRC_3P_C PA_AUX_N_C 4 3 6 1 PCH_DPD_DAT PA_AUX_P_C 4 3 6 1 PCH_DPD_CLK +3VS_POC
VDD D0+A PCH_DPD_DAT <16> PCH_DPD_CLK <16>
S
9 30
D
Port B is active H VDD D0-A
PA_DPSRC_3N_C
Q81A Q81B
12 27 PA_DPSRC_1P_C Q82A Q82B
VDD D1+A
1
16 26 PA_DPSRC_1N_C DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
+3VS_POC 20 VDD D1-A TB@
29 VDD 19 PA_AUX_P_C R1124
VDD AUX+A
S
18 PA_AUX_N_C 6 5 2 4 6 5 2 4 1K_0402_5%
D
S
S
D
D
AUX-A 17 TB@
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
2
PA_SRC_3P 1 HPD_A TB@ Q91A Q91B TB@ Q92A Q92B TB@
1 1 1 1 D0+
PA_SRC_3N 2 25 D0+B NTGD4161PT1G_TSOP6~D NTGD4161PT1G_TSOP6~D NTGD4161PT1G_TSOP6~D NTGD4161PT1G_TSOP6~D
G
G
G
1
3
D0- D0+B
1
PA_LSTX_SRC_1P 4 24 D0-B TB@ D
C1367
C1368
C1369
C1370
PA_LSRX_SRC_1N 5 D1+ D0-B 23 PA_LSTX_LSEO1_R Q32 2 PA_CFG1_LSEO0
2 2 2 2 D1- D1+B 22 PA_LSRX_LSOE1_U SSM3K7002FU_SC70-3 G
TB@ TB@ TB@ TB@ DPA_AUX_P 6 D1-B
S
3
DPA_AUX_N 7 AUX+ 15
DPA_AUX_HPD 8 AUX- AUX+B 14
HPD AUX-B 13
PA_DP_PWRDN 10 HPD_B U66B
49.9_0402_1%
49.9_0402_1%
<24> PA_DP_PWRDN SEL
2
11 21 PA_DPSRC_3P_C C1353 TB@1
TB@ 2 0.22U_0402_10V6K PA_DPSRC_3P A18 A22
1K_0402_5%
1K_0402_5%
PA_CIO_SEL 32 HPD_SEL GND 28 PA_DPSRC_3N_C C1358 TB@1
TB@ 2 0.22U_0402_10V6K PA_DPSRC_3N B19 PA_DPSRC_3_P PB_DPSRC_3_P B23
+3VS_POC <24> PA_CIO_SEL AUX_SEL GND PA_DPSRC_3_N PB_DPSRC_3_N
33
R1054
R1055
R1056
R1057
GPAD PA_DPSRC_1P_C C1359 TB@1
TB@ 2 0.22U_0402_10V6K PA_DPSRC_1P A16 A20
DPSRC Port A
DPSRC Port B
PI3VEDP212ZLEX_TQFN32_6X3~D PA_DPSRC_1N_C C1360 TB@1
TB@ 2 0.22U_0402_10V6K PA_DPSRC_1N B17 PA_DPSRC_1_P PB_DPSRC_1_P B21
1
TB@ @ @ PA_DPSRC_1_N PB_DPSRC_1_N
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 TB@ TB@ PA_AUX_P_C C1361 TB@1

TB@ 2 0.22U_0402_10V6K PA_AUX_P F3 D1
PA_AUX_N_C C1354 TB@1
TB@ 2 0.22U_0402_10V6K PA_AUX_N F1 PA_AUX_P PB_AUX_P E2
PA_AUX_N PB_AUX_N
C1371
C1373
C1372
PA_DPSRC_HPD H1 K3
2 2 2 PA_DPSRC_HPD PB_DPSRC_HPD
TB@ TB@ TB@ +3VS_POC TB_CIO_TX_P0 C1355 TB@1
TB@ 2 0.22U_0402_10V6K TB_CIO_TX_P0_C G24 R24
TB_CIO_TX_N0 C1362 TB@1
TB@ 2 0.22U_0402_10V6K TB_CIO_TX_N0_C E24 PA_CIO0_TX_P__DPSRC_0_P PB_CIO2_TX_P__DPSRC_0_P N24
PA_CIO0_TX_N__DPSRC_0_N PB_CIO2_TX_N__DPSRC_0_N
TB_CIO_RX_P0_C C1363 TB@1
TB@ 2 0.22U_0402_10V6K TB_CIO_RX_P0 G22 R22
PA_CIO0_RX_P PB_CIO2_RX_P
1
TB@ TB@ TB_CIO_RX_N0_C C1356 TB@1
TB@ 2 0.22U_0402_10V6K TB_CIO_RX_N0 E22 N22
PORT0
PA_CIO0_RX_N PB_CIO2_RX_N
PORT2
R1115 R1116
10K_0402_5% PA_CFG1_LSEO0 K1 P1
CIO
10K_0402_5% PA_CONFIG1__CIO_0_LSEO PB_CONFIG1__CIO_2_LSEO
+3VS_POC PA_CFG2_LSOE0 G4 H5
PA_DPSRC_HPD PA_CONFIG2__CIO_0_LSOE PB_CONFIG2__CIO_2_LSOE
3 2
1 TB@ 2 DPA_AUX_N
R1059 100K_0402_5% TB_CIO_TX_P1 C1357 TB@1
TB@ 2 0.22U_0402_10V6K TB_CIO_TX_P1_C L24 W24
5 G
D
TB_CIO_TX_N1 C1364 TB@1
TB@ 2 0.22U_0402_10V6K TB_CIO_TX_N1_C J24 PA_CIO1_TX_P__DPSRC_2_P PB_CIO3_TX_P__DPSRC_2_P U24
1 TB@ 2 PA_LSTX_LSEO1_R S TB@ PA_CIO1_TX_N__DPSRC_2_N PB_CIO3_TX_N__DPSRC_2_N
R1061 10K_0402_5% Q86A TB_CIO_RX_P1_C C1365 TB@1
TB@ 2 0.22U_0402_10V6K TB_CIO_RX_P1 L22 W22
4
PA_CIO1_RX_P PB_CIO3_RX_P
6
DMN66D0LDW-7_SOT363-6 TB_CIO_RX_N1_C C1366 TB@1
TB@ 2 0.22U_0402_10V6K TB_CIO_RX_N1 J22 U22
PORT1
PA_CIO1_RX_N PB_CIO3_RX_N
PORT3
D
MDP_HPD 2 G PAD
S TB@ PA_LSTX_LSEO1_R R1058 1 TB@ 2 0_0402_5% PA_LSTX_LSEO1 N2 L6 @ T80
1 TB@ 2 PA_LSRX_LSOE1_U Q86B PA_LSRX_LSOE1_R R1060 1 TB@ 2 0_0402_5% PA_LSRX_LSOE1 J6 PA_LSTX__CIO_1_LSEO PB_LSTX__CIO_3_LSEO G6
1
R1067 1M_0402_5% DMN66D0LDW-7_SOT363-6 PA_LSRX__CIO_1_LSOE PB_LSRX__CIO_3_LSOE
1 TB@ 2 DPA_AUX_P
2
R1068 100K_0402_5% CACTUS-RIDGE_FCBGA288
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1 TB@ 2 DPA_AUX_HPD HPD CFG1 CFG2 LSrx Mode Comments TB@ SA00005QT20
R1069 10K_0402_5% All Thunderbolt TX traces have pi filter
R1062
R1063
R1064
R1065
1 TB@ 2 TB_CIO_TX_P0 1 0 0 X DP
R1070 470K_0402_5%
when embedded capacitors before and after
1
1 TB@ 2 TB_CIO_TX_N0 U3 TB@ 1 1 X X HDMI inductor should be 0.45pF
R1071 470K_0402_5% +3VS_POC TB@ TB@ TB@ TB@
1 TB@ 2 TB_CIO_TX_P1 1 TB@ 2 1 0 0 1 0 TBT TBT cable but no TBT link Route Thunderbolt traces as 85 Ohm control impedance.
R1072 470K_0402_5% R1075 100K_0402_5% OE# 5
1 2 VCC Match inside pair 2 mil.Match between lanes NA
TB@ TB_CIO_TX_N1 TB@ 0 0 1 1 TBT TBT mode
R1073 470K_0402_5% PA_LSRX_LSOE1_U 2 C1374 2 1 0.1U_0201_10V6K Thunderbolt lenght must be between 0.8 inch to 2 inch
IN
0 X 0 X None Cable is disconnected
4
3 OUT
GND PA_LSRX_LSOE1_R
D42 @ D43 @ D44 @
74AHC1G125GW_SOT353-5 TB_CIO_RX_P0_C 1 1 10 9 TB_CIO_RX_P0_C PA_LSTX_SRC_1P 1 1 10 9 PA_LSTX_SRC_1P TB_CIO_TX_P1 1 1 10 9 TB_CIO_TX_P1
PA_CIO_SEL
TB_CIO_RX_N0_C 2 2 9 8 TB_CIO_RX_N0_C PA_LSRX_SRC_1N 2 2 9 8 PA_LSRX_SRC_1N TB_CIO_TX_N1 2 2 9 8 TB_CIO_TX_N1
1.5K_0402_5%
1.5K_0402_5%
1
TB_CIO_TX_P0 4 4 7 7 TB_CIO_TX_P0 PA_SRC_3P 4 4 7 7 PA_SRC_3P AUX_CHP 4 4 7 7 AUX_CHP

D0+B
R1076
R1077
TB_CIO_TX_N0 5 5 6 6 TB_CIO_TX_N0 PA_SRC_3N 5 5 6 6 PA_SRC_3N AUX_CHN 5 5 6 6 AUX_CHN

1
TB@ D LEGO@ 3 3 3 3 3 3
2
TB@ TB@ D47 BAR90-02LRH_TSLP-2-7-2 2 Q30

<32> TB_LED
TB_CIO_RX_P1_C 2 1 AUX_CHP G SSM3K7002FU_SC70-3 8 8 8
TB_CIO_RX_N1_C 2 1 AUX_CHN S
3
TB@ BAR90-02LRH_TSLP-2-7-2 L05ESDL5V0NA-4 SLP2510P8 L05ESDL5V0NA-4 SLP2510P8 L05ESDL5V0NA-4 SLP2510P8

1
D46
+3VS_POC
TB@ TB@
L63 L64
1
650NH +-5% LQW18CNR65J00D 650NH +-5% LQW18CNR65J00D Pull High +3VS at PCH side LEGO@ JTB1
R1125 C1376
2
DPA_AUX_N 10K_0402_5% 0.01U_0402_50V7K

<32> TB_EJECT_BTN
DPA_AUX_P R1083 1 TB@ 1 2 0_0402_5%
2
1
LEGO@ D TB@ 1
1 1
2
GND
TB@ TB@ Q31 2 D0-B MDP_HPD R1078 1 TB@ 2 mDP_HPD_R 2
HPD
C1379 C1380 SSM3K7002FU_SC70-3 G 60mil 40mil 0_0402_5% TB_CIO_TX_P0 3
LANE0_P
30P_0402_50V8J 30P_0402_50V8J S TB_CIO_RX_P0_C 4
0.01U_0402_50V7K
3
2 2 +3VS_POC +HV_12V TB_CIO_TX_N0 5 CONFIG1
100K_0402_5%
LANE0_N
2
1 0_0402_5% C1377 TB_CIO_RX_N0_C 6
CONFIG2
C1378
R1089 1 TB@ 2 1 2 0.01U_0402_50V7K 7
0.1U_0402_16V4Z
150U_B2_6.3VM_R35M
GND
R1080 1 TB@ 2 TB@ 8
R1079
1
0.1U_0402_16V4Z
GND
1 1 0_0402_5% PA_LSTX_SRC_1P 9
2 LANE1_P
+ PA_SRC_3P 10
C1000
C1001
C1003
1
+3VS_POC LANE3_P
PA_LSRX_SRC_1N 11
LANE1_N
TB@ TB@ PA_SRC_3N 12
TB@ 2 TB@ 2 TB@ 2 R1081 1 TB@ 2 0_0402_5% 13 LANE3_N
GND
1
R1082 1 TB@ 2 0_0402_5% 14

GND
TB@ 40mil TB_CIO_TX_P1 15
LANE2_P
1
R711 TB@ AUX_CHP 16

19
20
AUX_CHP
6
7
10K_0402_5% R712 U2 +VCC_DP_L TB_CIO_TX_N1 17
+3VS_POC +VCC_DP LANE2_N
10K_0402_5% TB@ 40mil AUX_CHN 18
VHV
VHV
V3P3
V3P3
2
AUX_CHN
TB_CIO_RX_P0_C Q84 TB@ L65 RETURN 19
RETURN
TB_CIO_RX_N0_C BC846B_SOT23-3 +3VS_POC R1074 1 TB@ 2 10K_0402_5% 5 12 1 2 +VCC_DP 20
2
BLM31PG500SN1L 1206
1 HV_EN HV_EN 11 EN OUT 14 FBMA-L11-201209-221LMA30T_0805
DP_PWR
0.01U_0402_16V7K
HV_EN OUT
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
2 R1084 1 TB@ 2 0_0402_5% 17 40mil 21
0_0402_5%
+3VS_POC S0
2
1
R1127 R1126 +HV_12V 3 18 +VCC3V3_PA @ 22
1K_0402_5%
1K_0402_5%
V3P3OUT 1 1 1
L66
10K_0402_5% R1112 1 TB@ 2 36.5K_0402_1% 8 TB@ 23
C1004
C1005
C1417
R1086
10K_0402_5%
GND
TB@ TB@ R1113 R1110 1 TB@ 2 35.7K_0402_1% 9 ISET_V3P3 15 @ R1088 24
R1085
R1087
10K_0402_5% 1 R1111 1 TB@ 2 35.7K_0402_1% 10 ISET_S3 RSVD 16 T73 TB@ 0_0402_5%

1
2
1 2 2 ISET_S0 RSVD PAD 2 2 2
1
2
TB@ TB@ TB@ 3 Current limited: TB@ TB@ TB@ JAE_SP11-11986-T01
TPad
1
GND
GND
GND
GND
GND
6
TB@ TB@
2.05K_0402_1%
D
2 PA_CFG1_LSEO0_A Q85 Ilim = 40Kohm/Rset C1381
R1114
S Q88B PA_CFG2_LSOE0 BC846B_SOT23-3 0.01U_0402_50V7K

1
2
3
4
13
21
DMN66D0LDW-7_SOT363-6 TB@ 2
TB@
1
TB@ EN HV_EN OUT TPS22980RGPR_VQFN20_4X4

330P_0402_50V7K
330P_0402_50V7K
1
2
2
1M_0402_5%
1M_0402_5%
1 1
PA_CFG1_LSEO0 0 0 0V VCC_DP@3V , max current 500mA
C1386
C1387
3
TB@ VCC_DP@12V, max current 0.8A

R1090
R1091
D
G 5 0 1 0V
Q88A 2 2
S
1
DMN66D0LDW-7_SOT363-6 TB@ TB@ 1 0 3.3V

4
PA_CFG1_LSEO0, PA_CFG2_LSOE0 Issued Date 2012/4/6 Deciphered Date 2013/4/6 Title

TB@ TB@ 1 1 12V
should be used by GPU as the
DP CONFIG1/CONFIG2 inputs, THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
if required AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
http://vinafix.vn
fix
vina +1.05VS_LC
U66C
+1.05VS_CIO
J8 W10
VCC1P0_ON VCC1P0
1000P_0201_16V7K
1000P_0201_16V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0201_10V7K
0.01U_0201_10V7K
J10 V11
J12 VCC1P0_ON VCC1P0 U10
2 2 VCC1P0_ON VCC1P0 1 1 1 1 1 1
TB@ TB@ J14 T11 TB@ TB@ TB@ TB@ TB@ TB@
VCC1P0_ON VCC1P0
C1397
C1398
C1406
C1407
C1408
C1409
C1412
C1413
J16 R14
K17 VCC1P0_ON VCC1P0 R10
1 1 T15 VCC1P0_ON VCC1P0 P15 2 2 2 2 2 2
U14 VCC1P0_ON VCC1P0 P11
V7 VCC1P0_ON VCC1P0 N14
W8 VCC1P0_ON VCC1P0 N10
G10 VCC1P0_ON VCC1P0 M15
G12 VCC1P0_PE VCC1P0 M11
VCC1P0_PE VCC1P0
VCC
0.01U_0201_10V7K
0.01U_0201_10V7K
G14 L14
G16 VCC1P0_PE VCC1P0 L10
1 1 VCC1P0_PE VCC1P0 +3VS_LC
TB@ TB@ G18 K15
VCC1P0_PE VCC1P0
C1415
C1416
H19 K11
K19 VCC1P0_PE VCC1P0
2 2 M19 VCC1P0_PE M7
VCC1P0_PE VCC3P3
1000P_0201_16V7K
0.1U_0201_10V6K
0.01U_0201_10V7K
.1U_0402_16V7K
.1U_0402_16V7K
P19 P7
T19 VCC1P0_PE VCC3P3 T7
VCC1P0_PE VCC3P3 1 1 1 1 2
V15 L18 TB@ TB@ TB@ TB@ TB@
VCC1P0_PE VCC3P3_CIO
C1424
C1425
C1427
C1428
C1433
V19 N18
W12 VCC1P0_PE VCC3P3_CIO R18
VCC1P0_PE VCC3P3_CIO 2 2 2 2 1
0.1U_0201_10V6K
0.1U_0201_10V6K
W14 H11
G8 VCC1P0_PE VCC3P3_DP H13
1 1 VCC1P0_DPAUX VCC3P3_DP
TB@ TB@ H9 H15
VCC1P0_DPAUX VCC3P3_DP
C1434
C1435
H17
VCC3P3_DP H7
2 2 VCC3P3_DPAUX K7
VCC3P3_POC +3VS_POC
CACTUS-RIDGE_FCBGA288
0.1U_0201_10V6K
TB@ SA00005QT20
1
0.1U_0201_10V6K
0.1U_0201_10V6K
TB@
C1445
1 1
TB@ TB@
2
C1443
C1444
2 2
U66D
A2 K9
A24 VSSPE VSS K13
B1 VSSPE VSS L8
B7 VSSPE VSS L12
C4 VSSPE VSS L16
C6 VSSPE VSS M9
C8 VSSPE VSS M13
C10 VSSPE VSS M17
C12 VSSPE VSS N8
C14 VSSPE VSS N12
C16 VSSPE VSS N16
C18 VSSPE VSS P9
C20 VSSPE VSS P13
C22 VSSPE VSS P17
C24 VSSPE VSS R8
D21 VSSPE VSS R12
D23 VSSPE VSS R16
E4 VSSPE VSS T9
F5 VSSPE VSS T13
F7 VSSPE VSS T17
F9
F11
VSSPE
VSSPE
GND VSS
VSS
U8
U12
F13 VSSPE VSS U16
F15 VSSPE VSS V9
F17 VSSPE VSS AD1
F19 VSSPE VSS Y11
F21 VSSPE VSSPE Y13
F23 VSSPE VSSPE Y15
G20 VSSPE VSSPE Y17
H21 VSSPE VSSPE Y19
H23 VSSPE VSSPE Y21
J18 VSSPE VSSPE Y23
J20 VSSPE VSSPE AA8
K21 VSSPE VSSPE AA14
K23 VSSPE VSSPE AA20
L20 VSSPE VSSPE AA22
M21 VSSPE VSSPE AB7
M23 VSSPE VSSPE AB11
N20 VSSPE VSSPE AB17
P21 VSSPE VSSPE AC4
P23 VSSPE VSSPE AC6
R20 VSSPE VSSPE AC8
T21 VSSPE VSSPE AC10
T23 VSSPE VSSPE AC12
U18 VSSPE VSSPE AC14
V13 VSSPE VSSPE AC16
Y9 VSSPE VSSPE
VSSPE
CACTUS-RIDGE_FCBGA288
TB@ SA00005QT20

Rev
Custom 1.0
http://vinafix.vn
f ix
vina +3VS_POC to +3VS_LC
40mil
VCC3V3_LC max current 350mA
40mil
+3VALW to +3VS_POC
60mil
Discharge circuit
TB@
+3VS_POC Q70 +3VS_LC +3VALW +3VS_POC
AP2301GN-HF_SOT23-3 +3VS_LC +1.05VS_LC +1.05VS_CIO
3 1 J2
1 1 2 1
2 1
1
+5VALW TB@ TB@ TB@ TB@ TB@
C1446 C1447 +3VS JUMP_43X79 +3VS_POC R1092 R1093 R1094
1U_0402_6.3V6K 1U_0402_6.3V6K 220_0402_5% 220_0402_5% 220_0402_5%
2
2 2 J4
2 1
2
2 1
1
1.05VS_CIO_CHG
3VS_LC_GATE
TB@ JUMP_43X79
3VS_LC_CHG
1.05LC_CHG
R1095
100K_0402_5%
VCC3V3POC, IC CONN max current 500mA ,
2
TB@ VCC3V3POC, DP CONN max current 500mA ,

EN_3VLC_PWR# 1 R1096 2 VCC3V3POC to VCC3V3 max current 350mA ,
100K_0402_5%
1 TB@
3
TB@ C1448
6
5 G
D
Q71A .1U_0603_25V7K D
<42> 1.05VS_LC_PG
2 EN_3VLC_PWR# 2 2
D D
S DMN66D0LDW-7_SOT363-6 EN_3VLC_PWR# G
TB@ TB@ EN_CIO_PWR# G
TB@
2 S Q71B G Q72 S Q75B
4
DMN66D0LDW-7_SOT363-6 S SSM3K7002FU_SC70-3 DMN66D0LDW-7_SOT363-6
1
_VCC1V05_LC,max current 750mA VCC1V05_LC, max current 750mA
+1.05VS_LC to +1.05VS_CIO
_VCC1V05_CIO,max current 1.5A 80mil 80mil
VCC1V05_CIO, max current 1.5A
_VCC3V3POC,max current 5mA +1.05VS_LC
U74
TB@ +1.05VS_CIO
_VCC3V3_LC,max current 350mA Rds=2.6mΩ(Typ) SI7716ADN-T1-GE3_POWERPAK8-5
3.2mΩ(Max) 1
_VCC_DP@3V,max current 500mA 2
_VCC_DP@12V,max current 0.8A
0.1U_0402_16V4Z
10U_0603_6.3V6M
10U_0603_6.3V6M
5 3
TB@ 1 TB@ 1
in the case of 12V min power should be 10W
C1453
C1454
1
TB@
4
+VSB C1452
2 2
2
2
TB@
R1099 TB@
100K_0402_5% R1100
10K_0402_5%
1
1.05CIO_GATE
1
@
3
TB@ R1109 1 TB@
5
D
EN_CIO_PWR# G Q75A 1M_0402_5% C1456
<24> EN_CIO_PWR# S DMN66D0LDW-7_SOT363-6 .1U_0603_25V7K
2
2
A1
+3VS_POC 1.05VS_LC_PG
A3 S4
V
EN_LC_PWR
Q70, +3VS_LC
V
PU11, +1.05VS_LC
+3VS_POC T1? A2
U66
TB_PWRON_POC_RST# EN_CIO_PWR# A4 S2
CACTUS RIDGE U74, +1.05VS_CIO
V
V
TB_PWRON_POC_RST#
H1
V
PA_HV_EN PU16, PQ47

U68
V
PA_DP_PWRDN VV +12VS_TB
PA_CIO_SEL
T2 1=TB
+1.05VS_LC 0=DP
S1 TB_GO2SX
PCH_PCIE_WAKE#
V V
+3VS_LC TB_PLUG_EVENT S3 TB_OK2GO2SX#

EC
PCH
V

Rev
Custom 1.0
http://vinafix.vn
5 4 3 2 1
a fix Wireless LAN

vin For
60mil
+3VS +3VS_W LAN +3VS_W LAN Mini Card Power Rating
+3VS_W LAN U1
J10
1 2 1 1 1 +3VS_W LAN F12 A1
C403 C735 C387 G4 3V3 GND[18] A2
3.3VAUX Power GND[19]
JUMP_43X79 4.7U_0805_10V4Z 0.1U_0201_10V6K 0.1U_0201_10V6K A3
@ GND[20] A4
D D
2 2 2 L4 GND[21] A5
<14> CLK_PCIE_MINI1# REFCLK- GND[22]
L5 A6
<14> CLK_PCIE_MINI1 REFCLK+ GND[23]
<14> MINI1_CLKREQ# F1 Clock A7
CLKREQ_L GND[24] A8
L6 GND[25] A9
<14> PCIE_PRX_DTX_N2 PERN0 GND[26]
<14> PCIE_PRX_DTX_P2 L7 A10
L8 PERP0 GND[27] A11
<14> PCIE_PTX_C_DRX_P2 PETN0 PCIE signal GND[28]
L9 A12
<14> PCIE_PTX_C_DRX_N2 PETP0 GND[29] B1
+3VALW +3VS_W LAN G9 GND[30] B2
<17> USB20_P8 USB_D+ GND[31]
Q47 G10 USB signal B11
<17> USB20_N8 USB_D- GND[32]
AP2301GN-HF_SOT23-3 B12
D1 GND[33] C1
<17> PLT_RST_BUF# PERST_L GND[34]
3 1 R702 1 @ 2 0_0402_5% PCH_PCIE_W AKE#_R E1 GND C4
<15,24> PCH_PCIE_W AKE# WAKE_L GND[35]
40mil(1A) R490 1 2 0_0402_5% G6 C5
<32> EC_PME# WIFI_DISABLE GND[36]
G7 Control C6
E12 WIFI_LED GND[37] C7
<32> W L_OFF# BT_DISABLE GND[38]
G8 C8
2
BT_CTRL R491 1 2 0_0402_5% BT_CTRL_R BT_LED GND[39] C9
1 2 3VSW LAN_GATE_R 1 2 3VSW LAN_GATE BT_LED R492 1 @ 2 0_0402_5% BT_LED_R GND[40] C10
+3VALW <32> BT_LED GND[41]
R451 100K_0402_5% R472 1K_0402_5% F4 C12
NC GND[42] D3
GND[43] D4
GND[44]
1
R185 C539 D5
D GND[45]
1
1K_0402_5% 0.1U_0201_10V6K D6
1 2 2 Q61 G1 GND[46] D7
<32> AOAC_ON
2
G SSM3K7002FU_SC70-3 +3VS_W LAN G3 GND[1] GND[47] D8
GND[2] GND[48]
1
C500 S G5 D9
3
C .1U_0402_16V7K G12 GND[3] GND[49] D10 C

H1 GND[4] GND[50] D12
2
R962 1 2 10K_0402_5% PCH_PCIE_W AKE#_R H2 GND[5] GND[51] E3

H11 GND[6] GND[52] E4
H12 GND[7] GND[53] E5
L1 GND[8] GND[54] E6
L2 GND[9] GND[55] E7
L3 GND[10] GND[56] E8
L10 GND[11] GND[57] E9
L11 GND[12] GND[58] E10
BT BT GND[13] GND[59]
Enable Disable L12 F3
F10 GND[14] GND[60] F5
F9 GND[15] GND[61] F6
F8 GND[16] GND[62] F7
BT_ON# L H GND[17] GND[63]
BT_CTRL H L
BT_CTRL T77H281.01_81P
D
1
2 Q62
<32> BT_ON#
G SSM3K7002FU_SC70-3
S
3
B B
A A

On Board WLAN
Custom 1.0
http://vinafix.vn
5 4 3 2 1
A B C D E
x
ForfimSATA
i n a Function RAID0_DET
v+3VS
40mil
+3VS_FULL +3VS_FULL
20mil
+1.5VS
Port0,1
Port0
H
L
J8 @
1 2 1 1 1 1@ 1
1 2 C455 C475 C466 C442 C441
JUMP_43X39 4.7U_0603_6.3V6K 0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 +1.5VS +3VS_FULL
1 1
JMINI1
1 2
C625 1 2 0.01U_0201_10V7K SATA_PTX_C_DRX_N1 3 1 2 4
<13> SATA_PTX_DRX_N1 3 4
<13> SATA_PTX_DRX_P1 C627 1 2 0.01U_0201_10V7K SATA_PTX_C_DRX_P1 5 6
7 5 6 8
9 7 8 10
9 10 RAID0_DET <18>
C628 1 2 0.01U_0201_10V7K SATA_PRX_C_DTX_P1 11 12
<13> SATA_PRX_DTX_P1 11 12
1
C626 1 2 0.01U_0201_10V7K SATA_PRX_C_DTX_N1 13 14
<13> SATA_PRX_DTX_N1 13 14
15 16 R329
15 16 100K_0402_5%
17 18
2
19 17 18 20
From DG=>Change to 0.01u 19 20
21 22
C621 1 2 0.01U_0201_10V7K SATA_PRX_C_DTX_P0 23 21 22 24
<13> SATA_PRX_DTX_P0 23 24
C622 1 2 0.01U_0201_10V7K SATA_PRX_C_DTX_N0 25 26
<13> SATA_PRX_DTX_N0 25 26
27 28
29 27 28 30
C623 1 2 0.01U_0201_10V7K SATA_PTX_C_DRX_N0 31 29 30 32
<13> SATA_PTX_DRX_N0 31 32
<13> SATA_PTX_DRX_P0 C624 1 2 0.01U_0201_10V7K SATA_PTX_C_DRX_P0 33 34
35 33 34 36
37 35 36 38
39 37 38 40
41 39 40 42
+3VS_FULL 41 42
43 44
45 43 44 46
47 45 46 48
R299 1 2 0_0402_5% E51TXD_P80DATA_R 49 47 48 50
<32> E51TXD_P80DATA 49 50
2 R287 1 2 0_0402_5% E51RXD_P80CLK_R 51 52 2
<32> E51RXD_P80CLK 51 52
G1
G2
G3
G4
1
1
R300 R288 BELLW _80060-1021
53
54
55
56
1K_0402_5%
100K_0402_5%
2
MSATA_DET#
MSATA_DET# <18>
3 3
4 4

mSATA HDD Connector
Custom 1.0
http://vinafix.vn
A B C D E
5 4 3 2 1
fix
MOTOR/RTC
a
n
vi
40mils 40mils
+3VALW +3V_MCU
JMR1
1 10mils
1 +MT_VCC
2
D 2 3
+3V_MCU
MOTOR_PPS_L
40mil +3VALW +VSB D
3 MOTOR_PPS_L <32>
D
4 MOTOR_PPS_R 6
S
4 5 MOTOR_PPS_R <32> 5 4
5
2
6 VR_LEFT 2
6 7 VR_RIGHT VR_LEFT <32> 1 Q87
7 8 VR_RIGHT <32>
R21 R789 SI3456DDV-T1-GE3_TSOP6
G
8 +RTCBATT_R
9 10K_0402_5% 470K_0402_5%
20mil
3
GND 10
1
GND
E-T_4260K-Q08N-13L MOTOR_PWR_ON# MOTOR_GATE
3
CONN@ 1
C811
0.1U_0603_25V7K
2 Q93A 5
<32,45> MOTOR_PWR_ON 2
Q93B
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
4
C C
TPM
+3VALW
10mil 10mil
J17 @
1 2 +3V_TXM +3VALW +3VALW_TPM
1 2
JUMP_43X39
+3VS J15 @ J16 @
1 2 1 2
1 2 1 2
JUMP_43X39 1 1 JUMP_43X39 1
1
TXM@ TXM@ TXM@ TPM@ TPM@

C1 C3 C4 C6 C9
10U_0603_6.3V6M 0.1U_0201_10V6K 0.1U_0201_10V6K 10U_0603_6.3V6M 0.1U_0201_10V6K
2
2 2 2
B B
near pin24 near pin19 near pin5
U7 TPM@
1
GPIO0/XOR_OUT VSB
5 +3VALW_TPM_R R966 1 TPM@ 2 0_0402_5%
+3VALW_TPM
TPM -Address:
2 19
R963 1 @ 2 10K_0402_5% BADD_BA0

6
9
GPIO1
GPIO2/GPX
VDD1
VDD2
24
+3V_TXM
Pin9 BADD
<15> CLKRUN#
CLKRUN# 15 GPIO3/BADD
GPIO4/CLKRUN# 8
1: 7Eh-7Fh (Default)
TEST
<13,32> LPC_AD0
LPC_AD0
LPC_AD1
26
23 LAD0 0: EEh-EFh
<13,32> LPC_AD1 20 LAD1 3
LPC_AD2
<13,32> LPC_AD2 LPC_AD3 17 LAD2 NC 10
<13,32> LPC_AD3 LAD3 NC 11
NC 12
28 NC 13
CLK_PCI_TXM 21 LPCPD# NC 14
<17> CLK_PCI_TXM 22 LCLK NC
LPC_FRAME#
<13,32> LPC_FRAME# 16 LFRAME#
PLT_RST#
<17,22,24,32,5> PLT_RST# SERIRQ 27 LRESET# 4
<13,32> SERIRQ 7 SERIRQ VSS1 18
PP VSS2 25
VSS3
NPCT42XAA0WX_TSSOP28
SA00005PH00
@ @C724
@ C724
A CLK_PCI_TXM 1 R716 2 1 2 A
33_0402_5% 22P_0402_50V8J

TPM
Rev
Custom 1.0
http://vinafix.vn
5 4 3 2 1
5 4 3 2 1
f ix
ina
For ESD request +5VALW +USB3_VCCA
R9 1 @ 2 0_0402_5%
v <17> PCH_USB3_TX1_P 2
C424
USB3.0@
1 PCH_USB3_TX1_P_C
0.1U_0201_10V6K
2
USB3.0@
2 1
1 U3TXDP1 U3TXDP1
D35
1 1
@
10 9 U3TXDP1
C432
0.01U_0402_16V7K
1 2
1
2
U17
GND
VIN
VOUT
VOUT
8
7 @ R314
USB3.0@ U3TXDN1 2 2 9 8 U3TXDN1 3 6 0_0402_5%
VIN VOUT
EPAD
<17> PCH_USB3_TX1_N 2 1 PCH_USB3_TX1_N_C 3 4 U3TXDN1 4 5 1 2
3 4 <32> USB_EN# EN FLG USB_OC0# <17>
C422 0.1U_0201_10V6K U3RXDP1 4 4 7 7 U3RXDP1
L3 OCE2012120YZF_4P
R10 1 @ 2 0_0402_5% U3RXDN1 5 5 6 6 U3RXDN1 AP2301MPG-13_MSOP8
9
1
D 3 3 C417 D
@
R11 1 @ 2 0_0402_5% 8 0.1U_0402_16V4Z
2
USB3.0@ +USB3_VCCA
PCH_USB3_RX1_P 2 1 U3RXDP1 L05ESDL5V0NA-4 SLP2510P8 W=80mils
<17> PCH_USB3_RX1_P 2 1
2
470P_0402_50V7K
C393
PCH_USB3_RX1_N 3 4 U3RXDN1 For USB2.0 ESD request SGA00001E00
<17> PCH_USB3_RX1_N 3 4
L4 OCE2012120YZF_4P D24 S POLY C 150U 6.3V M B2LESR45M PSL H1.9
R12 1 @ 2 0_0402_5% U2DP0 6 3 1
I/O4 I/O2
USB3.0 Conn.
JUSB1
1 2 USB20_P0P9 1 @ 2 +USB3_VCCA 5 2 1
<17> USB20_P0 VDD GND +3VALW VBUS
R710 0_0402_5% R691 0_0402_5% U2DN0 2
1 2 USB20_N0N9 USB3.0@ U2DP0 3 D-
<17> USB20_N0 D+
R713 0_0402_5% USB20_N0N9 2 1 U2DN0 4
2 1 GND
1
4 1 U2DN0 U3RXDN1 5
I/O3 I/O1 R744 U3RXDP1 6 SSRX- 11
USB20_P0P9 3 4 U2DP0 AZC099-04S.R7G_SOT23-6 100K_0402_5% 7 SSRX+ GND 12
1 @ 2 USB20_P0P9 3 4 U3TXDN1 8 GND GND 13
<17> USB20_P9 SSTX- GND
R715 0_0402_5% L52 W CM2012F2S-900T04_0805 U3TXDP1 9 14
2
1 @ 2 USB20_N0N9 1 @ 2 10 SSTX+ GND
<17> USB20_N9 <32> USB_HPD# DET
R714 0_0402_5% R689 0_0402_5%
TAIW I_USB005-107CRL-TW
Resister overlap with L52
CONN@
C C
R20 1 @ 2 0_0402_5% For ESD request +USB3_VCCA
D36
W=80mils
USB3.0@ USB3.0@ @
150U_B2_6.3VM_R35M
<17> PCH_USB3_TX2_P 2 1 PCH_USB3_TX2_P_C 2 1 U3TXDP2 U3TXDP2 1 1 10 9 U3TXDP2 1 2
2 1
470P_0402_50V7K
C391
C428 .1U_0402_16V7K SGA00001E00
C394
USB3.0@ U3TXDN2 2 2 9 8 U3TXDN2 +
<17> PCH_USB3_TX2_N 2 1 PCH_USB3_TX2_N_C 3 4 U3TXDN2 S POLY C 150U 6.3V M B2LESR45M PSL H1.9
3 4 4 4 1
C427 .1U_0402_16V7K U3RXDP2 7 7 U3RXDP2
L6 OCE2012120YZF_4P 2
R15 1 @ 2 0_0402_5% U3RXDN2 5 5 6 6 U3RXDN2 USB3.0 Conn.
3 3 JUSB2
1
R16 1 @ 2 0_0402_5% 8 +3VALW U2DN1 2 VBUS
U2DP1 3 D-
USB3.0@ 4 D+
GND
1
PCH_USB3_RX2_P 2 1 U3RXDP2 L05ESDL5V0NA-4 SLP2510P8 U3RXDN2 5
<17> PCH_USB3_RX2_P 2 1 SSRX-
R745 U3RXDP2 6 11
100K_0402_5% 7 SSRX+ GND 12
PCH_USB3_RX2_N 3 4 U3RXDN2 U3TXDN2 8 GND GND 13
<17> PCH_USB3_RX2_N 3 4 SSTX- GND
U3TXDP2 9 14
2
L5 OCE2012120YZF_4P USB_HPD# 10 SSTX+ GND
R17 1 @ 2 0_0402_5% DET
B B
For USB2.0 ESD request TAIW I_USB005-107CRL-TW
CONN@
1 @ 2 D33
R743 0_0402_5% U2DP1 6 3
USB3.0@ I/O4 I/O2
2 1 U2DN1
<17> USB20_N1 2 1
+USB3_VCCA 5 2
3 4 U2DP1 VDD GND
<17> USB20_P1 3 4
L53 W CM2012F2S-900T04_0805
1 @ 2 4 1 U2DN1
R693 0_0402_5% I/O3 I/O1
AZC099-04S.R7G_SOT23-6
A A
Security Classification Compal Secret Data

USB3.0
Custom 1.0
http://vinafix.vn
5 4 3 2 1
A B C D E
ix
af
+3VALW
L56
vin
@ C1205 @ R933 +3VALW J9 @ FBMA-L11-160808-800LMT_0603 LID_SW# R948 2 1 100K_0402_5%
22P_0402_50V8J 33_0402_5% 1 2 +3VALW_EC 1 2 +EC_VCCA FAN_SPEED1 FAN_PWM
2 1 2 1 CLK_PCI_LPC 1 2
1 1 1 1 2 2 1
+3VS
0.1U_0201_10V6K
C1198
0.1U_0201_10V6K
C1199
0.1U_0201_10V6K
C1200
0.1U_0201_10V6K
C1201
1000P_0201_16V7K
C1202
1000P_0201_16V7K
C1203
JUMP_43X39 1 1
C1204
+3VLP J11 @ 0.1U_0201_10V6K C451 C450 EC_MUTE# R928 2 @ 1 10K_0402_5%
2 2 2 2 1 1 2
ECAGND
1 2 1000P_0201_16V7K 1000P_0201_16V7K
1 2 +EC_VCC 2 2 BKOFF# R934 1 @ 2 10K_0402_5%
+EC_VCC <37>
JUMP_43X39
+3VALW_EC R938 2 1 47K_0402_5% EC_RST#
111
125
22
33
96
67
U53
9
C1208 2 1 0.1U_0201_10V6K +3VS
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
1 TP_CLK R929 1 2 4.7K_0402_5% 1
TP_DATA R931 1 2 4.7K_0402_5%

+3VALW_EC GATEA20 1 21 MOTOR_PWR_ON
<18> GATEA20 EC_KBRST# 2 GATEA20/GPIO00 GPIO0F 23 BEEP# MOTOR_PWR_ON <30,45>
<18> EC_KBRST# 3 KBRST#/GPIO01 BEEP#/GPIO10 26 BEEP# <33>
SERIRQ FAN_PWM
R939 1 @ 2 1K_0402_5% EC_SMI# <13,30> SERIRQ LPC_FRAME# 4 SERIRQ GPIO12 27 ACOFF FAN_PWM <34>
<13,30> LPC_FRAME# LPC_AD3 5 LPC_FRAME# ACOFF/GPIO13 ACOFF <36>
1 2 2.2K_0402_5% <13,30> LPC_AD3 7 LPC_AD3
R941 EC_SMB_DA1 LPC_AD2 PWM Output C1206 2 1 100P_0402_50V8J ECAGND R935 2 930@ 1 200K_0402_5%
+3VALW
<13,30> LPC_AD2 8 LPC_AD2 63 ECAGND <37>
LPC_AD1 BATT_TEMP
<13,30> LPC_AD1 LPC_AD0 10 LPC_AD1 BATT_TEMP/GPIO38 64 BATT_TEMP <37> 2 9012@ 1 200K_0402_5%
<13,30> LPC_AD0 LPC_AD0LPC & MISC GPIO39 TB_EJECT_BTN <25>
R1017 +3VLP
R942 1 2 2.2K_0402_5% EC_SMB_CK1 65 ADP_I
CLK_PCI_LPC 12 ADP_I/GPIO3A 66 AD_BID0 ADP_I <37,38>
<17> CLK_PCI_LPC CLK_PCI_EC AD Input GPIO3B
PLT_RST# 13 75 VR_RIGHT 2 1
<17,22,24,30,5> PLT_RST# PCIRST#/GPIO05 GPIO42 VR_RIGHT <30> ACIN <15,35,38,39>
R943 1 @ 2 10K_0402_5% EC_PME# EC_RST# 37 76 TB_OK2GO2SX# D37 RB751V-40_SOD323-2
20 EC_RST# IMON/GPIO43 TB_OK2GO2SX# <24>
EC_SCI#
+3VS <18> EC_SCI# AOAC_ON 38 EC_SCII#/GPIO0E EC_ACIN 2 1 100P_0402_50V8J
C1207
<28> AOAC_ON GPIO1D 68 SUSACK#
1 2 2.2K_0402_5% DAC_BRIG/GPIO3C 70 SUSACK# <15>
R944 EC_SMB_CK2 TB_GO2SX
EN_DFAN1/GPIO3D 71 WL_OFF# TB_GO2SX <24>
DA Output IREF/GPIO3E WL_OFF# <28>
R945 1 2 2.2K_0402_5% EC_SMB_DA2 KSI0 55 72 TB_PWRON_POC_RST#
KSI1 56 KSI0/GPIO30 CHGVADJ/GPIO3F TB_PWRON_POC_RST# <24>
KSI2 57 KSI1/GPIO31
R946 1 2 10K_0402_5% EC_SCI# KSI3 58 KSI2/GPIO32 83 EC_MUTE# R940
KSI4 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 SLP_SUS# EC_MUTE# <33> 0_0402_5%
60 KSI4/GPIO34 USB_EN#/GPIO4B 85 SLP_SUS# <15> 2 1
KSI5 MOTOR_PPS_L VR_HOT# @ H_PROCHOT# <5>
KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 EAPD MOTOR_PPS_L <30> <43> VR_HOT#
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D EAPD <33>
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <33>
1
R949 1 2 100K_0402_5% PLT_RST# KSI[0..7] KSO0 39 88 TP_DATA D
<33> KSI[0..7] 40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <33> 2
KSO1 H_PROCHOT#_EC Q60
C1209 1 2 0.01U_0402_16V7K KSO[0..15] KSO2 41 KSO1/GPIO21 G SSM3K7002FU_SC70-3
<33> KSO[0..15] KSO3 42 KSO2/GPIO22 97 USB_HPD#
ESD request USB_HPD# <31> S
3
2 @ KSO4 43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 DRAMRST_CNTRL_EC 2
KSO5 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 HDA_SDO DRAMRST_CNTRL_EC <6>
KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109 VCIN0_PH_R HDA_SDO <13>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 Latest design guide suggest change to 74LVC1G06.
KSO7/GPIO27 SPI Device Interface
KSO8 47
KSO9 48 KSO8/GPIO28 119 BT_LED
49 KSO9/GPIO29 SPIDI/GPIO5B 120 BT_LED <28>
KSO10 EC_SPOK KB930&9012 Co-Layout Item
50 KSO10/GPIO2A SPIDO/GPIO5C 126 EC_SPOK <37>
KSO11 SPI Flash ROM MOTOR_VID0
KSO12 51 KSO11/GPIO2B SPICLK/GPIO58 128 MOTOR_VID1 MOTOR_VID0 <45>
KSO12/GPIO2C SPICS#/GPIO5A MOTOR_VID1 <45> Pin 111 is a power source for HW operation of KB9012.
KSO13 52 2 1
KSO14 53 KSO13/GPIO2D So, power plan will be different between KB930 and KB9012.
R950 100K_0402_5%
KSO15 54 KSO14/GPIO2E 73 ENBKL
KSO15/GPIO2F ENBKL/GPIO40 ENBKL <16>
R951 2 1 0_0402_5% USB_EN#_R 81 74 VR_LEFT +EC_VCC 1 930@ 2
+3VALW
KSO16/GPIO48 PECI_KB930/GPIO41 VR_LEFT <30>
R952 2 @ 1 0_0402_5% ACPRESENT 82 89 FSTCHG R930 0_0402_5%
<31> USB_EN# <15> ACPRESENT KSO17/GPIO49 FSTCHG/GPIO50 90 BATT_BLUE_LED# FSTCHG <38> 1 9012@ 2
SYSON# <35> BATT_CHG_LED#/GPIO52 BATT_BLUE_LED# <22> +3VLP
91 MOTOR_PPS_R R932 0_0402_5%
77 CAPS_LED#/GPIO53 92 MOTOR_PPS_R <30>
EC_SMB_CK1 GPIO PWR_LED#
<37,38> EC_SMB_CK1 78 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 93 PWR_LED# <22>
EC_SMB_DA1 BATT_AMB_LED# Pin74(KB930),Pin118(KB9012) are with different PECI pin location,
<37,38> EC_SMB_DA1 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 BATT_AMB_LED# <22>
EC_SMB_CK2 SM Bus SYSON
<11,14,24> EC_SMB_CK2 EC_SMB_DA2 80 EC_SMB_CK2/GPIO46 SYSON/GPIO56 121 VR_ON SYSON <35,40> so HW must co-layout for it.
<11,14,24> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 PM_SLP_S4# VR_ON <43> Please make sure which EC pin will be connected to PECI circuit.
PM_SLP_S4#/GPIO59 PM_SLP_S4# <15>
PM_SLP_S3# 6 100 PCH_RSMRST#

<15> PM_SLP_S3# PM_SLP_S5# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_LID_OUT# PCH_RSMRST# <15>
<15> PM_SLP_S5# EC_SMI# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 VCIN1_PROCHOT_R EC_LID_OUT# <18> KB9012_PECI 1 2
<18> EC_SMI# 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 H_PECI <18,5>
PCH_PWR_EN H_PROCHOT#_EC R958 9012@ 43_0402_1%
<35> PCH_PWR_EN 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104
MOTOR_BTN GPXIOA07
+3VALW_EC <33> MOTOR_BTN DPWROK 18 GPIO0B VCOUT0_PH/GPXIOA07 105 BKOFF#
<15> DPWROK GPIO0C GPO BKOFF#/GPXIOA08 BKOFF# <22> Pin104 co-layout circuit is for power fail function of KB930 and KB9012.
IRST_RST# 19 GPIO 106 PBTN_OUT#
<17> IRST_RST# GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# <15> At KB930, PCH_PWROK will be connected to pin 104.
R965 1 2 10K_0402_5% IRST_RST# BI_DET 25 107 SUSWARN#
SUSWARN# <15>
<33> BI_DET FAN_SPEED1 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 SA_PGOOD At KB9012,PCH_PWROK will be connected to pin 32,
<34> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 SA_PGOOD <42>
3
<28> EC_PME#
EC_PME# 29 and VCOUT0_PH will be connected to pin 104. 3
E51TXD_P80DATA 30 EC_PME#/GPIO15
<29> E51TXD_P80DATA E51RXD_P80CLK 31 EC_TX/GPIO16 110 EC_ACIN 9012_PCH_PWROK 2 1
@
<29> E51RXD_P80CLK 9012_PCH_PWROK 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112 EC_ON R956 0_0402_5%
34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <39> 2 1
PWR_SUSP_LED# ON/OFF GPXIOA07
<22> PWR_SUSP_LED# MOTOR_LED# 36 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 115 LID_SW# ON/OFF <33> PCH_PWROK <15>
Board ID <33> MOTOR_LED# NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04 LID_SW# <22>
R955 930@ 0_0402_5%
116 SUSP# 2 1
+3VALW SUSP#/GPXIOD05 117 BT_ON# SUSP# <35,38,40,41> MAINPWON <39>
Analog Board ID definition, R954 9012@ 0_0402_5%
GPXIOD06 118 KB9012_PECI BT_ON# <28>
Please see page 3. <25> TB_LED PECI_KB9012/GPXIOD07
AGND/AGND
TB_LED 122
XCLKI/GPIO5D
2
1 @ 2 EC_XCLK0 123 124 +V18R VCIN0_PH_R 1 @ 2

GND/GND
GND/GND
GND/GND
GND/GND
<15> SUSCLK XCLKO/GPIO5E V18R VCIN0_PH <37>

R957 R959 0_0402_5% 2 R947 0_0402_5%
GND0
Ra 100K_0402_5%
C1214 VCIN1_PROCHOT_R 1 @ 2
VCIN1_PROCHOT <37>
4.7U_0603_6.3V6K R953 0_0402_5%
1
AD_BID0 R961 2 1 100K_0402_5% KB9012QF-A3_LQFP128_14X14 1 +3VALW_EC

11
24
35
94
113
69
9012@ 20mil
2
1 L57 KSO1 R936 2 930@ 1 47K_0402_5%

R960 C1213 1 2 ECAGND 2 1
Rb 56K_0402_5% 0.1U_0201_10V6K FBMA-L11-160808-800LMT_0603 KSO2 R937 2 930@ 1 47K_0402_5%
C1215 20P_0402_50V8
2
1
Follow KB930 checking List

+3VALW_EC
TB_EJECT_BTN R976 1 2 2.2K_0402_5%
4 4
VR_RIGHT VR_LEFT
2
R454 R455
100K_0402_1% 100K_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
EC ENE-KB930/KB9012
1
Custom 1.0
http://vinafix.vn
A B C D E
1 2 3 4 5 6 7 8
x
KBafiConn. TP Conn. ON/OFF BTN
vin
+3VALW +3VLP
+3VS
Motor BTN
2
KSI[0..7] 930@ 9012@
KSI[0..7] <32>
JKB1 R144 R907
2
1 KSI0 KSO[0..15] 100K_0402_5% 100K_0402_5%
G
1 2 KSI1 KSO[0..15] <32> +3VS
2 3 KSI2 1 3 SMB_ALERT#_R
<14> SMB_ALERT#
1
3 4 KSO0
S
4
1
5 KSO1 CONN@
5 6 KSO2 JTP1 R971
6 7 KSI3 10 10K_0402_5% Q9 ON/OFFBTN# R967 1 @ 2 0_0402_5%
7 8 G 9 <22> ON/OFFBTN# ON/OFF <32>
KSO3 SSM3K7002FU_SC70-3
A 8 9 KSO4 G 8 A
2
9 10 KSO5 8 7 SMB_ALERT#_R
10 11 KSO6 7 6
11 6 D_CK_SCLK <14>
12 KSO7 5
12 5 D_CK_SDATA <14>
13 KSO8 4
13 14 KSI4 4 3
14 15 KSO9 3 2 TP_DATA <32>
15 16 KSI5 2 1 TP_CLK <32>
16 1 +3VS 1 1
17 KSI6
17 18 KSO10 E-T_6701K-Q08N-00R C217 C216
18 19 KSO11 100P_0402_50V8J 100P_0402_50V8J +3VALW_EC +3VLP
19
2
20 KSI7 2 2
20 21 KSO12 R974
21 22 KSO13 0_0402_5%
22
2
23 KSO14 @
23 24 KSO15 R908 R909
1
24 100K_0402_5% 100K_0402_5%
D_CK_SCLK TP_DATA D22
2
1
25 +3VS D_CK_SDATA TP_CLK MOTOR_BTN_SW# 1
GND1 26 3
GND2 MOTOR_BTN <32>
3
@ D6 @ D4
@D4
ACES_85208-24071 1 AZ5125-02S.R7G_SOT23-3 AZ5125-02S.R7G_SOT23-3 BAV70W_SOT323-3
CONN@ C196
0.1U_0201_10V6K R975 1 @ 2 0_0402_5%
BOT side EMI request 2
KSO15 C260 1 @ 2 100P_0201_25V8J KSO7 C252 1 @ 2 100P_0201_25V8J
1
KSO14 C259 1 @ 2 100P_0201_25V8J KSO6 C251 1 @ 2 100P_0201_25V8J
B KSO13 C258 1 @ 2 100P_0201_25V8J KSO5 C250 1 @ 2 100P_0201_25V8J B
KSO12 C271 1 @ 2 100P_0201_25V8J KSO4 C249 1 @ 2 100P_0201_25V8J
KSI0 C263 1 @ 2 100P_0201_25V8J KSO3 C248 1 @ 2 100P_0201_25V8J
KSO11 C256 1 @ 2 100P_0201_25V8J KSI4 C267 1 @ 2 100P_0201_25V8J +3VS
KSO10 C255 1 @ 2 100P_0201_25V8J KSO2 C247 1 @ 2 100P_0201_25V8J Audio/B 20pin
1
KSI1 C272 1 @ 2 100P_0201_25V8J KSO1 C246 1 @ 2 100P_0201_25V8J
JAUDIO R968
1
1 HDA_BITCLK_AUDIO <13>
KSI2 C265 1 @ 2 100P_0201_25V8J KSO0 C245 1 @ 2 100P_0201_25V8J 2 10K_0402_5%
2 3
2
KSO9 C254 1 @ 2 100P_0201_25V8J KSI5 C268 1 @ 2 100P_0201_25V8J 3 4
4 5
KSI3 C266 1 @ 2 100P_0201_25V8J KSI6 C269 1 @ 2 100P_0201_25V8J 5 6
6 7 HDA_RST_AUDIO# <13>
KSO8 C253 1 @ 2 100P_0201_25V8J KSI7 C270 1 @ 2 100P_0201_25V8J 7 8 C1224 1 2 1 R970 2 BEEP
8 HDA_SYNC_AUDIO <13> <32> BEEP#
9
9 HDA_SDOUT_AUDIO <13>
10 1U_0402_6.3V6K 560_0402_5%
10 HDA_SDIN0 <13>
11 BEEP
11 12 C1227 1 2 1 R972 2
12 13 EAPD <32> <13> PCH_SPKR
13 EC_MUTE# <32>
1
14 BI_GATE# 1U_0402_6.3V6K 560_0402_5%
14 15 MOTOR_BTN_SW#
15 16 D41
16 17 MOTOR_LED# <32>
+3VALW 10mil RB751V-40_SOD323-2
17 18
+3VS 20mil
2
18 19
C 19 20
+5VS 60mil C
20
G1
G2
21
22
Battery Reset
23
G3 24
G4
10mil
ACES_50406-02071-001 +RTCVCC
CONN@
1
R850 1 2 510K_0402_5%
BI_DET <32>
R969
BI <37>
1K_0402_5%
1
D
BI_GATE# 2 Q8
S
3
Need Check Gate Threshold Voltage
Battery BI Low voltage is 0.8V
D D

BIOS, I/O Port & K/B Connector
Custom 1.0
http://vinafix.vn
1 2 3 4 5 6 7 8
fix
vina FAN Conn
20mil
+5VS C585
10U_0805_25V6K FD1 FD2 FD3 FD4
1 2
C587 @ @ @ @
1
1000P_0402_50V7K
1 2 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
+3VS
1
R489 Stand-Off
10K_0402_5%
H1 H2 H3 H4 H5
JFAN1 H_5P2 H_5P2 H_5P2 H_5P2 H_5P2
2
4 6
FAN_SPEED1 3 4 G2 5
<32> FAN_SPEED1 2 3 G1
FAN_PWM @ @ @ @ @
1
<32> FAN_PWM 1 2
1 1
C579
@ 1000P_0402_50V7K ACES_88266-04001
CONN@
2
Thermal module
H6 H7 H8 H9
H_4P0 H_4P0 H_4P0 H_4P0
@ @ @ @
1
定定定 H10 H11
H_2P5x3P0 H_4P0N
@ @

Step Motor,FAN,Screw Hole
Rev
Custom 1.0
http://vinafix.vn
A B C D E
f ix
ina
+5VALW to +5VS +3VALW to +3VALW_PCH(PCH AUX Power)
v Rds=13.5mΩ(Typ)
16.5mΩ(Max)
+5VALW
U22
+5VS
SI7716ADN-T1-GE3_POWERPAK8-5 20mil +5VALW

1 +3VALW +3VALW_PCH
2
2
4.7U_0603_10V6K
C464
4.7U_0603_10V6K
C498
1U_0603_10V6K
C469
2 5 3 2 1 R629 2 @ 1 0_0402_5%
4.7U_0603_6.3V6K
C701
R440 2 R246
470_0603_5% 100K_0402_5%
4
1 1 2
1
1 1 SUSP 1
<40,5> SUSP
10mil
3
D
2 1 5VS_GATE G 2 SUSP
+VSB DMN66D0LDW-7_SOT363-6
5
D
R437 S G
<32,38,40,41> SUSP# Q59A
20mil 20K_0402_5% 1 Q19B S
1
C499 DMN66D0LDW-7_SOT363-6
4
3 .1U_0603_25V7K R251
10K_0402_5%
SUSP 5 G
D
2
S
2
Q19A
4
+3VALW to +3VS
Rds=13.5mΩ(Typ) +3VALW +3VS
U21
16.5mΩ(Max) SI7716ADN-T1-GE3_POWERPAK8-5
1
2
2
10U_0603_6.3V6M
C375
4.7U_0603_6.3V6K
C461
1U_0402_6.3V6K
C458
5 3 2 1
1
R436
470_0603_5%
+5VALW
2
1 2
1
2 2
2
R368 10mil R441
47K_0402_5% 6 100K_0402_5%
2 1 2
D
3VS_GATE G SUSP
+VSB
S
1
20mil 1 Q25B
1
C463 DMN66D0LDW-7_SOT363-6
.1U_0603_25V7K
3
SUSP 5 G
D
2 SYSON#
S
<32> SYSON#
Q25A
4
6
2
D
SYSON G
Q59B
<32,40> SYSON S DMN66D0LDW-7_SOT363-6
1
R438
+1.35V to +1.35VS 100K_0402_5%
Rds=2.6mΩ(Typ) +1.35V +1.35VS
3.2mΩ(Max)
2
U12
SI7716ADN-T1-GE3_POWERPAK8-5
1
2
2
10U_0603_6.3V6M
C460
0.1U_0402_16V4Z
C377
0.1U_0402_16V4Z
C376
4.7U_0603_6.3V6K
C339
1U_0402_6.3V6K
C338
1 1 5 3 2 1
1
R245
470_0603_5%
2
2 2 1 2
1
3 3
10mil
6
2 1 2
D
1.35VS_GATE G SUSP
+VSB
R269 S
200K_0402_5% Q15B +5VALW

20mil
1
1
@ @ 1 DMN66D0LDW-7_SOT363-6
510K_0402_5%
R268
1M_0402_5%
R277
C380
.1U_0603_25V7K
3
2
SUSP 5 G
D
2 R449
2
S 100K_0402_5%
Q15A
4
1
1
D @
<20> PCH_PWR_EN#
<15,32,38,39> ACIN ACIN 2 Q21
1
D
S
3
2 Q26
<32> PCH_PWR_EN
1
S
3
R450
100K_0402_5%
2
+1.35V +0.675VS +1.05VS_VTT +1.8VS
2
4 4
@ R365 R366 R29 R508
470_0603_5% 22_0603_5% 470_0603_5% 470_0603_5%
1 1
1 2
1 1
1 1
Q24
D @ D Q23 D Q5 D Q34
2 SYSON# 2 SUSP 2 SUSP 2 SUSP Security Classification Compal Secret Data Compal Electronics, Inc.
G G G G Issued Date 2012/4/6 Deciphered Date 2013/4/6 Title
SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3
S S S S
DC Interface
3
Rev
Custom 1.0
http://vinafix.vn
A B C D E
A B C D
f ix
vina
VIN
1
PL1 Pre_CHG 1
PJP1 SMB3025500YA_2P
1 DC_IN_S1 1 2 PR1
1 2 1K_1206_5%
2 3 1 2
3 4 PQ1
4 5 PR2 PD1 TP0610K-T1-E3_SOT23-3
GND
1
6 PC3 VIN 1K_1206_5% LL4148_LL34-2
GND PC1 PC2 100P_0402_50V8J PC4 1 2 2 1 3 1 B+
ACES_88266-04001 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K
2
PR3
1K_1206_5%
1 2
100K_0402_5%
100K_0402_5%
1
1
PR4
PR5
PR6
1K_1206_5%
2
1 2
1
PR7
1
100K_0402_5%
0_0402_5% PD2 PQ2
PR22 BAS40CW _SOT323-3 PDTC115EU_SOT323-3
1 2
<32> ACOFF 2 1 2 <BOM Structure>
1 2
2
+5VALWP 3 PQ3 2
PDTC115EU_SOT323-3
<BOM Structure>
2
3
PJ1 PJ2
1 2 1 2
+3VALWP 1 2 +3VALW +5VALWP 1 2 +5VALW
JUMP_43X79 JUMP_43X79
PJ8 PJ10
1 2 1 2
1 2 1 2
PJ4
PJ3
1 2 +1.35VP 1 2 +1.35V
@ PD4 +VSBP 1 2 +VSB 1 2
3
LL4148_LL34-2 JUMP_43X39 JUMP_43X79 3
2 1 PJ5
BATT+ VS 1
1 2
2
JUMP_43X79
PJ7
PJ6
1 2 1 2
+1.8VSP 1 2 +1.8VS +1.05VS_VCCPP 1 2 +1.05VS_VTT
PJ9
1 2
+0.675VSP 1 2 +0.675VS
JUMP_43X39
PJ12
1 2
+HV_12VP 1 2 +HV_12V
PJ11 JUMP_43X39
1 2
+VCCSAP 1 2 +VCCSA
+3VLP
JUMP_43X118
PR57 PR102 PR12 PJ15

4
560_0603_5% 560_0603_5% 0_0402_5% 1 2 4
1 2 1 2 1 2 +1.05VS_LCP 1 2 +1.05VS_LC
+RTCBATT
+RTCBATT_R +CHGRTC JUMP_43X39

DCIN/PRECHARGE
http://vinafix.vn
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Chief River VC 1.0
A B C D
A B C D
f ix
v ina CONN@
ACES_88231-08001
1
1 2
2 3 EC_SMDA
3 4 EC_SMCA
4 5 TH
5 6 BI+
6
1
7
1
7 8 PR15
1
8 9 100_0402_1%
GND1 10
<40,41>
GND2
1
VMB
2
PJP2 PR17
100_0402_1%
EC_SMB_DA1 <32,38>
PL2
SMB3025500YA_2P
<40,41>
2
BATT_S1 1 2 BATT+
1
EC_SMB_CK1 <32,38>
1
1
PC8 PC9 PR19
1000P_0402_50V7K 0.01U_0402_25V7K 1K_0402_5%
2
2
PR20 G718 ENE9012
6.49K_0402_1%
2 1
+3VALW
65W 3.92K 2.21K ADP_I <32,38>
1
65W @ PR33
PR21 1.65K_0402_1%
1K_0402_1% 90W 8.87K 6.98K
1
BI <33>
2
1.456V 1.2V
BATT_TEMP <32> VCIN1 1.148V 0.925V 90W @ PR33
6.98K_0402_1%
2
2 2
VCIN1_PROCHOT <32>
For 65W adapter==>action 70W , Recovery 54W
For 90W adapter==>action 97W , Recovery 75W
1
PR38
For 40W thunder bolt adapter==>action 50W , Recovery 38W 10K_0402_1%
VCIN1=0.9V recover = 0.683V
2
PQ6
TP0610K-T1-E3_SOT23-3
3 1
PH1 under CPU botten side :
B+ +VSBP
CPU thermal protection at 92 degree C for reference
0.22U_0603_25V7K
0.1U_0603_25V7K
1
1
PC12
PC13
PR26
<32> EC_SPOK 100K_0402_1%
+EC_VCC <32>
2
3 3
PR27 @
2
VL 22K_0402_1%
2 1
1
1
PC14 PR29
@ PR28 .1U_0402_16V7K 12.4K_0402_1%
2
100K_0402_1%
2
@ PR34
2
1K_0402_5% D
1 2 2 PQ7
<39> SPOK G SSM3K7002FU_SC70-3 VCIN0_PH <32>
S
3
1
@ PC15
1
1U_0402_6.3V6K
2
PC17
.1U_0402_16V7K
2
EC side
1
PH1
100K_0201_1%_TSMAB104F4251RZ
2
ECAGND
4
ECAGND <32> 4

BATTERY CONN / OTP
http://vinafix.vn
A B C D
A B C D
f ix
ina
for reverse input protection
v D
1
2 PQ8
G SI1304BDL-T1-E3_SC70-3
S
3
1 2 1 2
1 PR39 PR40 1
1M_0402_5% 3M_0402_5%
VIN PQ9 P1 PQ10 P2 PR41 B+ CHG_B+ PQ11

SIS412DN-T1-GE3_POW ERPAK8-5 SIS412DN-T1-GE3_POW ERPAK8-5 0.02_1206_1% SIS412DN-T1-GE3_POW ERPAK8-5
PJ21
1 1 1 4 1 2 1
1 2
2200P_0402_50V7K
2 2 2
0.1U_0402_25V6
5 3 3 5 2 3 JUMP_43X79 5 3
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
0.01U_0402_50V7K
PC21
PC22
PC23
PC24
0_0402_5%
PR42
1
VIN
0_0402_5%
PC16
PR43
4
4
PC26
PC27
2
1
@ 2 0.1U_0402_25V6 <BOM STRUCTURE>
1
1 2 @
PC25
2
0.1U_0402_25V6
PD6
2
BAS40CW_SOT323-3
1
BQ24725_BATDRV 1 2
PC28
PR44
1
4.12K_0603_1%
4.12K_0603_1%
PC29 4.12K_0603_1%
0.047U_0402_25V7K
1
1 2
PR45
PR46
5
10_1206_1%
2.2_0603_5%
1
PR48
PR47
0.1U_0603_25V7K
2
2 PR50 PQ12 2
1
0_0402_5% SIS412DN-T1-GE3_POW ERPAK8-5
BQ24725_ACN
PC30
BQ24725_BST 2
BQ24725_ACP
1
DH_CHG 1 2DH_CHG-1 4
2
PC31 PD7
BQ24725_LX
2
1 2 RB751V-40_SOD323-2 BATT+
DH_CHG
1U_0603_25V6K PC33 PL4 PR52
3
2
1
1 2 4.7UH_FDSD0630-H-4R7M-P3_5.5A_20% 0.01_1206_1%
BQ24725_LX 1 2 CHG 1 4
1U_0603_25V6K
5
2 3
20
19
18
17
16
CSOP1
SIS412DN-T1-GE3_POWERPAK8-5
PU4
4.7_1206_5%
CSON1
2200P_0402_50V7K
1
0.01U_0402_50V7K
VCC
REGN
PHASE
HIDRV
BTST
PR53
10U_0805_25V6K
10U_0805_25V6K
21
PAD
0.1U_0402_25V6
0.1U_0402_25V6
PC39
PC36
PC34
PC35
1
1
1 15 4
PQ13
DL_CHG @
ACN LODRV
PC37
PC38
2
2
2 14
ACP GND
680P_0402_50V7K
PR54
3
2
1
2
1
BQ24725RGRR_VQFN20_3P5X3P5 10_0603_5%
PC40
BQ24725_CMSRC 3 13 SRP 1 2 CSOP1
CMSRC SRP
2
0.1U_0603_25V7K
BQ24725_ACDRV 4 12 SRN 1 2 CSON1 @
2
ACDRV SRN PR55
PC41
6.8_0603_5%
+3VLP 1 2 ACOK 5 11 BQ24725_BATDRV
PR56 ACOK ACDET BATDRV
100K_0402_1%
IOUT
3 3
SDA
SCL
ILIM
<15,32,35,39> ACIN
Pre_CHG +3VALW
6
10
ACDET
1
1 2
0.01U_0402_25V7K
PD9 PR58
1
100K_0402_1%
RB751V-40_SOD323-2 316K_0402_1%
1
PR59 VIN PR60
PC42
PR61
1
2M_0402_1% 280K_0603_0.1%
2
battery 4.35/cell *4 =17.4, battery voltage --> 1 2

back to back --> Vin
Vin Dectector
2
2
2
1
1
PR63
PR62 154K_0603_0.1%
Min. Typ Max.
2M_0402_1% L-->H 17.852V 18.063V 18.275V
2
H-->L 17.476V 17.687V 17.898V

1 2
ACDET
PQ14
ILIM and external DPM
0.1U_0402_16V7K
EC_SMB_CK1 <32,37>
1
PR64 PDTC115EU_SOT323-3
PC43
100K_0402_1% <BOM Structure> PR65

1 2 2 66.5K_0603_0.1%
<32> FSTCHG Min. Typ Max.
2
EC_SMB_DA1 <32,37>
PR66 3.906A 4.006A 4.108A
2
0_0402_5%
D
1
4 2 1 1 2 4
ADP_I <32,37>
3
2 PQ15
<32,35,40,41> SUSP#
1
G SSM3K7002FU_SC70-3 PC44 @ PC45

S 100P_0402_50V8J 0.1U_0402_16V7K
3
Close EC
2

PWR DCIN / Pre-charge
http://vinafix.vn
Custom 1.0
A B C D
5 4 3 2 1
f ix
v ina
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
2VREF_8205
1U_0603_10V6K
D D
1
PC46
2
PR67 PR68
13.7K_0402_1% 30K_0402_1%
1 2 2 1
PR69 PR70
RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
2 1 1 2
PJ17 Typ: 175mA
B+ 1 2 +3VLP
1 2
ENTRIP2
ENTRIP1
JUMP_43X79 PR71 PR72
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
147K_0402_1% 147K_0402_1%
PC49
2 1 1 2
PC57
4.7U_0805_10V6K
1
1
PC50
PC51
PC52
PC55
PC56
PC53
5
5
PU5
2
2
PC54
PQ16 PQ17
ENTRIP2
FB2
TONSEL
REF
FB1
ENTRIP1
1
25
P PAD
2
C 4 4 C
7 24
VOUT2 VOUT1 SPOK <37>
8 23 PR74 PC59
SIS412DN-T1-GE3_POW ERPAK8-5 PR73 VREG3 RT8205LZQW (2)_W QFN24_4X4
PGOOD 2.2_0603_5% 0.1U_0603_25V7K SIS412DN-T1-GE3_POW ERPAK8-5
1
2
3
3
2
1
2 1 2 1 BST_3V 9 22 BST_5V 1 2 1 2
2.2_0603_5% BOOT2 <BOM Structure> BOOT1
PL6 PC58 UG_3V 10
VFB=2.0V 21 UG_5V PL7
3.3UH_FDSD0630-H-3R3M-P3_6.6A_20% 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1
1
LG_3V 12 19 LG_5V
4.7_1206_5%
4.7_1206_5%
LGATE2 LGATE1
5
PR75
PR76
SKIPSEL
PQ18
VREG5
SECFB
SI7716ADN-T1-GE3_POW ERPAK8-5
GND
VIN
@ @
EN
1 1
2
2
4
PC60 + 4 +
13
14
15
16
17
18
1
1
PC61
150U_B2_6.3VM_R35M PD10 PR77 PC62

680P_0402_50V7K
680P_0402_50V7K
PC63
RLZ5.1B_LL34 499K_0402_1% PQ19 150U_B2_6.3VM_R35M
2 1 2 1 2 2
B+
2
1
2
3
2
@ SI7716ADN-T1-GE3_POW ERPAK8-5
3
2
1
Typ 13.5m ohm @
1
150K_0402_1%
1U_0603_10V6K
max 16.5m ohm VL
1
PC64
Typ 13.5m ohm
1
PR78
PC65
Typ: 175mA
4.7U_0805_10V6K
max 16.5m ohm
2
ENTRIP1 ENTRIP2
2
2
RT8205_B+
1
B RT8205 B
2VREF_8205
0.1U_0603_25V7K
TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
6
D D
2
2 5 (2)SMPS2=375KHZ(+3VALWP)
PC66
PQ20A PQ20B
DMN66D0LDW -7_SOT363-6 G G DMN66D0LDW -7_SOT363-6
TPS51125A
S S TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP)
1
(2)SMPS2=305KHZ(+3VALWP)
3.3VALWP Delta I = 2.709A (Freq=305KHz)
PR79 Iocp = 8.7746A ~ 10.42
100K_0402_1% 5VALWP Delta I = 3.199A (Freq=245KHz)
2 1
VL 9012@ PR100 Iocp = 9.0195A ~ 10.673A
2.2K_0402_1%
1 2
<32> EC_ON
PR80
0_0402_5% +3.3VALWP Ipeak=7A ; Imax=4.9A +5VALWP Ipeak=7A ; Imax=4.9A
1
1 2
<32> MAINPWON PQ21 Delta I=2.2036A=>1/2Delta I=1.1017A (F=375K Hz) Delta I=2.6129A=>1/2Delta I=1.3064A (F=300K Hz)
930@ PD11 930@ PR81 PDTC115EU_SOT323-3 Rds(on)=16.5m ohm(max) ; Rds(on)=13.5m ohm(typical) Rds(on)=16.5m ohm(max) ; Rds(on)=13.5m ohm(typical)
LL4148_LL34-2 1M_0402_1% <BOM Structure>
2 1 1 2 2 Ilimit_min=(147K*10uA)/(10*16.5m*1.2)=7.42A Ilimit_min=(147K*10uA)/(10*16.5m*1.2)=7.42A
VIN Ilimit_max=(147K*10uA)/(10*13.5m*1.2)=9.07A Ilimit_max=(147K*10uA)/(10*13.5m*1.2)=9.074A
ACIN
Iocp=Ilimit+1/2Delta I=8.52A~10.174A Iocp=Ilimit+1/2Delta I=8.7264A ~ 10.38A

1
930@ PR82
402K_0402_1%
1U_0603_10V6K
1
PC67
930@ PR83
3
316K_0402_1%
1 2
VS
2
930@ PR84
2
1
930@ PR85
10K_0402_1%
A 1M_0402_1% A
1 2
VL
1
D
3 2
2
VS G D
5 930@ PQ23B
2 S 930@ PQ23A G DMN66D0LDW -7_SOT363-6 Security Classification Compal Secret Data Compal Electronics, Inc.
1
DMN66D0LDW -7_SOT363-6 2012/4/6 2013/4/6 Title

Issued Date Deciphered Date
S
3VALW/5VALW
4
930@ PQ22
PDTC115EU_SOT323-3 Size Document Number Rev
http://vinafix.vn
3
5 4 3 2 1
A B C D
fix
ina
Ipeak = 9.8A, Imax = 6.86A
v
PJ18
Delta I = 2.88A, F= 290KHz, Rton= 887K ohm 1.5V_B+ 1 2 B+
Rtrip = 19.6K ohm 1 2
OCP= 13.45~16.56A JUMP_43X79
10U_0805_25V6K
+1.35VS +1.35VP
PC68
5
2
1
1
1 1
PJ13
1
PJ24 PQ24
JUMP_43X39 JUMP_43X39 4 SIS412DN-T1-GE3_POW ERPAK8-5
2
2
3
2
1
PL9
PR86 PC71 1.5UH_MMD-06CZ-1R5M-V1_9A_20%
BST_1.5V
2.2_0603_5% 0.1U_0603_25V7K
UG_1.5V
LX_1.5V
1 2 BST_1.5V-1 1 2 2 1
+0.675VSP
靠靠Output Cap PAD +1.35VP
10U_0805_25V6K
10U_0805_25V6K
1
5
20
19
18
17
16
1
1
PC72
PC73
PU6 @ PR87
4.7_1206_5% 1
VTT
VLDOIN
BOOT
UGATE
PHASE
21
2
2
PAD + PC74
1 15 LG_1.5V 4 330U_B2_2.5VM_R15M
VTTGND LGATE
1
@ PC75 2
2 14 680P_0402_50V7K
2
VTTSNS PGND PR88
3
2
1
19.6K_0402_1%
3 13 2 1 PQ25
GND RT8207MZQW _W QFN20_3X3 CS SI7716ADN-T1-GE3_POW ERPAK8-5
Rds=13.5mΩ(Typ)
4 12
+VTT_REFP VTTREF VDDP 16.5mΩ(Max)
2 2
5 11 2 1
+1.35VP VDDQ VDD
+5VALW
PGOOD
PR89
+3VALW
1
5.1_0603_5% need change OCP setting
1U_0603_10V6K
TON
PC76
FB
S3
S5
0.033U_0402_16V7K
2
1
PC77
10K_0402_5%
6
10
PR90
PC78
1U_0603_10V6K
S3_1.5V
S5_1.5V
2
PR91
680K_0402_1% @
2
<32,35,38,41> SUSP# 1 2 PGOOD_1.5V
PR92 PR93
0_0402_5% 887K_0402_1%
<32,35> SYSON 1 2 2 1 1.5V_B+
PC325 PR94
1
.1U_0402_16V7K <BOM Structure>

@ PC79 4.64K_0402_1%
0.1U_0402_16V7K 2 1
2
FB=0.75V
1
To GND = 1.5V
PR95 To VDD = 1.35V
5.76K_0402_1%
1
D
2
<35,5> SUSP 2
G
PQ26
SSM3K7002FU_SC70-3
S FB=0.6V
3
Note:Iload(max)=3.5A
3 3
PU7 PL10
4
PJ14 1UH_PH041H-1R0MS_3.8A_20%
+3VALW 1 2 10 2 LX_1.8V 1 2
PG
1 2 PVIN LX +1.8VSP
JUMP_43X39 9 3
68P_0402_50V8J
PVIN LX
1
4.7_0805_5%
1
8
PC81
PC80
22U_0805_6.3VAM
SVIN
1
PR96
22U_0805_6.3VAM PR97
2
6
PC82
20K_0402_1%
2
5 FB
2
EN
NC
NC
PR257
TP
100K_0402_1% FB_1.8V
SUSP# 1<BOM Structure>
2 +1.8VSP_ON
11
1
0.1U_0402_16V7K
1
1
PC84
680P_0402_50V7K
1
PC85
PR98 SY8033BDBC_DFN10_3X3 PR99
47P_0402_50V8J
1
PC87
1M_0402_5% 10K_0402_1%
2
2
2
2
2
@
STATE S3 S5 1.35VP VTT_REFP 0.675VSP
S0 Hi Hi On On On
Off SY8033B enable pin without internal pull down, and
S3 Lo Hi On On (Hi-Z) RT8061or other 2nd source has 500K pull down resistor!So
please review your application if R1>249K will cause
enable pin logic high level is not enough
4
S4/S5 Lo Lo Off Off Off 4
(Discharge) (Discharge) (Discharge)
Note: S3 - sleep ; S5 - power off

1.5VP/0.75VSP/1.8VSP
http://vinafix.vn
A B C D
5 4 3 2 1
fix
ina
+3VS
VFB= 0.704V
v
Vo=VFB*(1+PR116/PR119)= 1.05V
Freq= 266~314KHz , 290KHz(typ)
1
PR261
10K_0402_1% PJ19
Cesr= 15m ohm +1.05VS_VTTP_B+ 1 2
Ipeak= 15.24A Imax= 10.668A 1 2 B+
2
PR101 Delta I= 3.306A ==>1/2 Delta I= 1.653A JUMP_43X79
0_0402_5% Vtrip=Rtrip*10uA= 0.523V
5
2 1
<42> VCCPPWRGOOD Iocp= 18.74A~22.66A
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
D D
1
PC95
PC96
PC97
@ PR274
0_0402_5% 4
2
PQ29
2
PR111 PC99 MDV1525URH_PDFN33-8-5
3
2
1
PU9 2.2_0603_5% 0.1U_0603_25V7K <BOM Structure>
PR112 1 10 BST_+1.05VS_VTTP 1 2 1 2
52.3K_0402_1% PGOOD VBST
PR113 2 1 TRIP_+1.05VS_VTTP2 9 UG_+1.05VS_VTTP PL14
330K_0402_1% TRIP DRVH 1UH_VMPI0703AR-1R0M-Z01_11A_20%
SUSP# 1 2 EN_+1.05VS_VTTP 3
EN SW
8 SW_+1.05VS_VTTP 1 2 +1.05VS_VCCPP
5
FB_+1.05VS_VTTP 4 7
PC100 VFB V5IN +5VALW
1
0.1U_0402_16V7K RF_+1.05VS_VTTP 5 6 LG_+1.05VS_VTTP 1
2
TST DRVL PQ30
1
11 MDU1511RH_POWERDFN56-8-5 @ PR115 + PC102
TP PC101 4 4.7_1206_5% PC103 330U_B2_2.5VM_R15M
PR114 TPS51212DSCR_SON10_3X3 1U_0603_10V6K .1U_0402_16V7K
1
470K_0402_1% 2
1
@ PC104
等改改之之改之
3
2
1
2
680P_0402_50V7K
Rds=2.6mΩ(Typ)
2
C 3.2mΩ(Max) IVB ES2 1.05V 0.1U_0402_16V7K C
PR116
VFB=0.7V 4.87K_0402_1%
2 1
PC105 PR117 PR118

1000P_0402_50V7K 1.2K_0402_1% 100_0402_1%
1
2 1 2 1 1 2
VCCIO_SENSE <8>
等改改之之之之
PR119
10K_0402_1%
IVB ES2 1.05V
2
+1.8VS
+5VALW
2
PJ20
2
JUMP_43X39
B B
@
1
PC86
1U_0402_6.3V6K
1
2
6
5 PC91
VCNTL
7 VIN 4.7U_0805_6.3V6K
POK 4
2
VOUT
PR106 3
100K_0402_5% VOUT
+1.5VS
1
1 2 8 2
<32,35,38,40> SUSP# EN FB
1
GND
9 PR105 PC90
VIN
1
1.54K_0402_1% 0.01U_0402_25V7K
2
PR103 PC89 PC88

1
47K_0402_5% 0.1U_0402_16V7K PU8 22U_0805_6.3V6M

2
APL5915KAI-TRL_SO8
2
1
2
PR104
1.74K_0402_1%
2
A A

+1.05VS_VTTP/+1.0VSP
5 4 3 2 1
http://vinafix.vn
5 4 3 2 1
fix
vina VID [0]
0
VID[1]
0
VCCSA Vout
0.9V
+VCC_SAP
TDC 4.2A 0 1 0.8V
Peak Current 6A 1 0 0.725V
OCP current 7.2A
1 1 0.675V
D output voltage adjustable network D
<BOM Structure>
PU10 SY8037DCC_DFN12_3X3 PL15

PJ23
0.47UH +-20% PCMC042T-R47MN 6A
+3VALW 1 2 +VCCSA_PWR_SRC 12 1 +VCCSA_PHASE 1 2 +VCCSAP
2200P_0402_50V7K
0.1U_0603_25V7K
1 2 PVIN LX
22U_0805_6.3V6M
11 2
JUMP_43X79 PVIN LX
1
PC118
PC119
1
22U_0805_6.3V6M
22U_0805_6.3V6M
.1U_0402_16V7K
2200P_0402_50V7K
SA_PGOOD <32>
2
PC106 10 3 PR120 @ PR126
@PR126
PC120
SVIN LX
1
68P_0402_50V8J 100K_0402_5% 4.7_0805_5%
PC112
PC113
PC114
PC115
2 1 9 4 +VCCSA_PWRGD 1 2
+3VS
1
2 FB PG
2
8 5 +VCCSA_EN 1 2
VOUT EN VCCPPWRGOOD <41>
PR124 <BOM Structure> <BOM Structure>
GND
1
7 6 0_0402_5% @ PC109
VID1 VID0 680P_0402_50V7K
2
13
2
+VCCSA_VID0
+VCCSA_VID1
@ PC107
.1U_0402_16V7K
1
H_VCCSA_VID0 <9>
PR122
1K_0402_5%
2 1 The 1k PD on the VCCSA VIDs are empty.
PR121 These should be stuffed to ensure that
1K_0402_5% VCCSA VID is 00 prior to VCCIO stability.
C 2 1 C
PR128
H_VCCSA_VID1 <9>
100_0402_5%
2 1
PR130
0_0402_5%
2 1
VCCSA_SENSE <9>
+3VALW
1
PC92
22U_0805_6.3VAM PR123
100K_0402_5%
2 1
PL8
2
PJ16 1UH_PH041H-1R0MS_3.8A_20%
+3VALW 1 2 4 3 LX_1.05TPP 1 2
1 2 IN LX +1.05VS_LCP
JUMP_43X39 5 2
68P_0402_50V8J
PG GND
1
6 1
PC94
22U_0805_6.3VAM
22U_0805_6.3VAM
<27> 1.05VS_LC_PG FB EN
1
PR109
1
7.5K_0402_1%
PC93
PC108
2
PR258 FB=0.6V PR110
2
0_0402_5% 4.7_0805_5%
EN_LC_PWR 1 2 +1.05TPP_ON
B <24> EN_LC_PWR B
2
PU11
0.1U_0402_16V7K
1
SY8032ABC_SOT23-6
PC117
1
PR107 FB_1.05TPP
1M_0402_1%
2
@
2
PC111
680P_0402_50V7K PR108
2
10K_0402_1%
2
A A

Title
Compal Electronics, Inc.
Issued Date 2012/4/6 Deciphered Date 2013/4/6
VCC_SAP/+1.5VSDGPUP/+1.05VS_DGPU
http://vinafix.vn
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C Chief River VC 1.0
5 4 3 2 1
5 4 3 2 1
ix
1
f
@ PC125
ina
1000P_0402_50V7K
<9> VCC_AXG_SENSE
2 2
local sense revese HW <9> VSS_AXG_SENSE
v PC127
0.01UF_0402_25V7K
1
PC133 PC134
68P_0402_50V8J 470P_0402_50V7K
2 1 2 1 2 1
PR134
PH3 PR135 PC135 499_0402_1%
10K_0402_1%_ERTJ0EG103FA 523_0402_1% 150P_0402_50V8J CPU_B+
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
VSUMG- 2 1 2 1 2 1 2 1
2
PR136 PR137
D 137K_0402_1% 2.61K_0402_1% D
1
PC181
PC182
PC183
PC184
5
36.5K_0402_1%
.1U_0402_16V7K
0.1U_0603_25V7K
1
1
1000P_0402_50V7K
PC137
PR143
PQ38
2 1
2
2
11K_0402_1%
MDV1525URH_PDFN33-8-5 @ <BOM Structure>
2.61K_0402_1%
1
PR142
PC140
@ PC141
+3VS
PR141
UGATE1G 4
2
1.91K_0402_1%
DCR: 1.19mΩ±5%
1
1
VSUMG+ PL23
3
2
1
<BOM Structure> 0.24UH_FDUE0630J-H-R24M-P3_22A_20%
PHASE1G <BOM1 Structure> 2
+VGFX_CORE
2
LGATE1G
4.7_1206_5%
1
PR147
PR200
PHASE1G
3.65K_0603_1%
UGATE1G PC189
1
0.22U_0603_16V7K
1 1
680P_0402_50V7K
1_0402_5%
PR203
PR204
BOOT1G 4
1 2
PC190
PR206
LGATE1G
2.2_0603_5%
+5VS
VSUMG+ 1
2
3
2
1
VSUMG-
40
39
38
37
36
35
34
33
32
31
<BOM Structure>
2
PU13 BOOT1G
ISUMNG
RTNG
FBG
COMPG
PGOODG
PWM2G
LGATE1G
PHASE1G
UGATE1G
BOOT1G
1
PR152
1
27.4K_0402_1%
2 1 PR155 1 30 PR159 PR162 PQ40
PR158 0_0402_5% 2 ISUMPG BOOT2 29 0_0603_5% 1_0603_5% MDU1511RH_POWERDFN56-8-5
3.83K_0402_1% PH4 +5VS 1 2 ISEN2G 3 ISEN1G UGATE2 28
2
ISEN2G PHASE2
1U_0603_10V6K
PC155
1 2 2 1 NTCG 4 27 Rds(on)typ : 2.4m ohm
2
C
1
470K_0402_5%_ 2
TSM0B474J4702RE SCLK 5 NTCG LGATE2 26 C
<8> VR_SVID_CLK SCLK VCCP max: 3.3m ohm
1
1 2 PR160 0_0402_5% ALERT# 6 25
<8> VR_SVID_ALRT# ALERT# VDD
PR161 0_0402_5%1 2 SDA 7 24 For ULV 17W 1+1
<8> VR_SVID_DAT SDA PWM3
1U_0603_10V6K
PR164 0_0402_5% 8 23 LGATE1
<32> VR_HOT# CPU_CORE LL= -2.9mΩ,
2
VR_HOT# LGATE1
PC154
1 2 9 22
<32> VR_ON VR_ON PHASE1
1
54.9_0402_1%
PR165 0_0402_5% 10 21 PHASE1 GFX_CORE LL= -3.9mΩ,

NTC UGATE1
2
2
0_0402_5%
130_0402_1%
75_0402_5%
ISEN3/FB2
PR168
PR169
PR170
PR171
1
470K_0402_5%_ TSM0B474J4702RE
27.4K_0402_1%
PGOOD
@ PC156 UGATE1
BOOT1
ISUMN
ISUMP
2
COMP
ISEN2
ISEN1
47P_0402_50V8J 41
RTN
TP
1
@ BOOT1
FB
2
PR172
1
PH5
ISL95836HRTZ-T_TQFN40_5X5~D
11
12
13
14
15
16
17
18
19
20
<BOM Structure>
CPU_B+ 2 1
+5VS B+
2
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
1 PL16
2
+1.05VS_VTT
33U_D_25VM_R60M
PR196 PQ37 FBMA-L11-322513-151LMA50T_1210
VGATE <15>
1
3.83K_0402_1%
PC157
0_0402_5% MDV1525URH_PDFN33-8-5 +
1
1
PC176
PC177
PC178
PC179
@ PC126 1 2 PR174 1.91K_0402_1%
+3VS
PR173
0.1U_0402_16V7K 2 1 PR192
2
0_0603_5% 2
2
UGATE1 1 2 UGATE1-1 4
2
DCR: 1.19mΩ±5%
PL21
3
2
1
<BOM Structure> 0.24UH_FDUE0630J-H-R24M-P3_22A_20%
VSUM+ PHASE1 <BOM1 Structure> 2
PC162 PR176 PR177 +CPU_CORE
11K_0402_1%
2.61K_0402_1%
4.7_1206_5%
470P_0402_50V7K 2K_0402_1% 42.2K_0402_1% PR194
1
1000P_0402_50V7K
0.1U_0603_25V7K
2 1 2 1 2 1 2.2_0603_5%
PR180
PR195
BOOT1 2 1 1 2
523_0402_1%
@ PC169
<BOM Structure>
680P_0402_50V7K
PC166
PC187
PR187
PC167 PC170 0.22U_0603_16V7K @
12
1 2
2
PC188
B 470P_0402_50V7K 68P_0402_50V8J LGATE1 4 1
VSUM+ 2 B
2
PR184
2 1 2 1 2 1 PH6 PR198
PR183 3.65K_0603_1%
2
499_0402_1% 10K_0402_1%_ERTJ0EG103FA
2
@
1
3
2
1
VSUM-
<BOM Structure>
PR189 PC174
1.91K_0402_1% 150P_0402_50V8J
Close Phase 1 choke
1
.1U_0402_16V7K
2 1 2 1 2 1 PC175 PQ39 VSUM- 2 1
PR190 MDU1511RH_POWERDFN56-8-5 PR201
137K_0402_1% 1_0402_5%
2
Rds(on)typ : 2.4m ohm

max: 3.3m ohm
@ PC180
330P_0402_50V7K
2 1
<8> VCCSENSE
<8> VSSSENSE
2 1
PC186
0.01UF_0402_25V7K
local sense revese HW
A A
Security Classification
2012/4/6
Compal Secret Data
2013/4/6 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
CPU_CORE
http://vinafix.vn
5 4 3 2 1
5 4 3 2 1
fix PWR Rule

ina CPU LL=2.9m ohm dedign 330uF/9m *4, 22uF *12, 2.2uF*16 +CPU_CORE
v +VGFX_CORE GFX LL=3.9m ohm design 330uF/9m *2, 22uF*6, 10uF*6 , 1uF*11
1.05V 330uF*2 10uF*10, 1u*26
1
1U_0201_4V6M
PC225
1U_0201_4V6M
PC226
1U_0201_4V6M
PC227
1U_0201_4V6M
PC228
1U_0201_4V6M
PC229
1U_0201_4V6M
PC275
1U_0201_4V6M
PC317
1U_0201_4V6M
PC319
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
2
1
1
PC230
PC231
PC232
PC233
PC234
PC235
PC258
PC264
PC292
PC293
PC294
D D
For BOT side
1
1U_0201_4V6M
PC236
2.2U_0402_6.3V6M
PC237
1U_0201_4V6M
PC238
2.2U_0402_6.3V6M
PC239
1U_0201_4V6M
PC240
1U_0201_4V6M
PC316
2.2U_0402_6.3V6M
PC318
2.2U_0402_6.3V6M
PC320
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
PC247
PC242
PC243
PC244
PC245
PC246
2
2
+CPU_CORE
1 1 1
1
22U_0805_6.3V6M
PC249
22U_0805_6.3V6M
PC250
22U_0805_6.3V6M
PC251
47U_0805_6.3V6M
PC252
47U_0805_6.3V6M
PC253
47U_0805_6.3V6M
PC254
47U_0805_6.3V6M
47U_0805_6.3V6M
47U_0805_6.3V6M
2
2 2 2
330U_D2_2V_Y
1 1
1
PC256
PC259
PC260
PC261
PC255 + +
330U_B_2.5VM_R9M
2
2
2 2
For TOP side
C C
1 1 1
22U_0805_6.3V6M
PC265
22U_0805_6.3V6M
PC266
22U_0805_6.3V6M
PC267
2 2 2
Vaxg
‧ Can connect to GND if motherboard only
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
‧ VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from +CPU_CORE
floating) if the VR is stuffed +1.05VS_VTT
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1 1 1 PC273 need link SGA00006J00.
1
1
+ PC271 + @PC272 + PC273
330U_D2_2V_Y 330U_D2_2V_Y 560U 2V M D2
PC353
PC352
PC351
PC334
PC333
PC332
PC331
PC330
PC329
PC328
PC327
PC354
PC356
2
2
2 2 2
B B
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1
1
PC326
PC324
PC323
PC322
PC321
PC289
PC288
PC287
PC286
PC285
PC284
PC355
PC357
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
PC279
PC283
PC282
PC281
PC280
2
330U_B2_2.5VM_R15M
1
PC291
A A
INTEL Recommend
3*330uF(1 in other page),12*22uF, 5 no stuff Security Classification Compal Secret Data Compal Electronics, Inc.
from PDDG 1.0 Issued Date 2012/4/6 Deciphered Date 2013/4/6 Title
CPU_CORE_CAP
5 4 3 2 1
http://vinafix.vn
5 4 3 2 1
fix
ina
PQ47
AON7403L_DFN8-5 PL27
v
4.7UH_MMD-04BZ-4R7M-S1L_2.4A_20%
PJ22 1 PD15
<BOM Structure>
1 2 2 5 1 2 LX_12VSP 2 1
+5VALW 1 2 +HV_12VP
3
JUMP_43X39
SX34 SMA
0.01U_0402_16V7K
0.01U_0402_16V7K
1U_0402_6.3V6K
PC358
PC359
4
2
10U_0805_25V6K
10U_0805_25V6K
PC360
PR288 PR289
100K_0402_5% 86.6K_0402_1%
1
PC361
PC362
D D
2
2
PR290
10K_0402_5%
2
PR291
1 1
10K_0402_1%
D
<BOM Structure>
2 PQ48
1
S
7
PU16
LX
LX
8 2 FB_12VSP
PR294 Vin FB FB =1.24V
0_0402_5%
1 2 FREQ_12VSP9 10 SS_12VSP
+5VALW FREQ SS
1
1 2 EN_12VSP 3 1COMP_12VSP
<24> PA_HV_EN EN COMP PC365
PR292 0.01U_0402_16V7K
2
2
2
10K_0402_5%
GND
GND
PAD
PR295
C 1 10K_0402_1% C
PC363
11
5
PR293 0.1U_0402_10V7K
1
1
100K_0402_5%
1
PC364
RT9297GQW_WDFN10_3X3 4700P_0402_25V7K
2
L/RDC=C*R
Rdc=40ohm(max) 2.2uL/40mohm=0.00022uF*250Kohm
3V3/2V JACKET
PL28 <BOM Structure>
2.2UH_1231AS-H-2R2M-P3_1.9A_20%
1 2
+MT_VCC
1
PC366
1U_0402_16V6K PR296 PC367
1
300K_0402_1% 470P_0402_50V7K
2
PU17 1 2 Motor_Compensate2 1
5V_BST# MP2334DD-LF-Z_QFN12_2X3 PR297
1
1
11 PC368 12K_0402_1%
PR298 1 GND 12 0.01U_0402_25V7K
2
GND GND
10_0402_5% 1
2
2 13 PC369
SW SW Motor_FB 22U_0805_6.3V6M
2
Motor_BST 3 10 Motor_SW PJ26

B <30,32> MOTOR_PWR_ON BST SW JUMP_43X39 2 B
2 1 Motor_VCC4 9 Motor_IN 1 2 B+
PC371 4.7U_0603_10V6K VCC IN 1 2
1
1 2 Motor_EN 5 8 Motor_FREQ 2 1
EN FREQ PR300 432K_0402_1%
>1.6V ENABLE
1
6 7 Motor_FB PC372 PR301
10K_0402_5% PG FB
1
@ PC373 10U_0805_25V6K 8.45K_0402_1%

1
PR299 PC374 1000P_0402_25V8J
2
0.1U_0201_10V6K
2
100K_0402_5%
2
PR302
2
1 Motor_FB
FB=0.815V
1Motor_FB
PR303
VID0 VID1 +MT_VCC
7.68K_0402_1% +3VALW PR304
5.76K_0402_1% +3VALW
2
0 0 2
2
<BOM
PR305
Structure>
2
10K_0402_5% PR306
10K_0402_5%
PR307
MOTOR_VID0 <32> 1 0 3.3
1
6
D 100K_0402_5% PR308
MOTOR_VID1 <32>
1
3
PQ49A 2 1 2 D 100K_0402_5%
DMN66D0LDW-7_SOT363-6 G PQ49B 5 1 2
DMN66D0LDW-7_SOT363-6 G
0 1 reserve
1
S
1
PC375 S
4
0.1U_0402_25V6 PC376
2
A 0.1U_0402_25V6 A
1 1 5
2
@ PR309
2
10K_0402_5% @ PR310
@PR310
2
10K_0402_5%

12V & MOTOR Power
Size
Document Number Rev
1.0
http://vinafix.vn
5 4 3 2 1
5 4 3 2 1
fix
vina
(PU1000)
VR_ON +CPU_CORE
ISL6266ACRZ-T +1.5VS_DMC
D D
TQFN48 Page 55
VGA_ON (U13) VGA_ON# (U40)

(PU998) SUSP
+VGA_CORE SI4800BDY-T1-GE3 +1.5VS AO4430L +1.5VSDGPU
APW7138NITRL Page 44
SO8 Page 44
SSOP16 Page 54
ADAPTER
SYSON (PU5) SUSP (PU8)
+1.5V
RT8209BGQW APL5331KAC-TRL +0.75VS
SO8 Page 53
B+ WQFN14 Page 51
(PU6) PJP25 L76

BATTERY VS_ON +1.05V_VCCP +1.05VS_PCH +CLK_1.05VS
RT8209BGQW
(SUSP#)
WQFN14 Page 53
U38
+1.05VSDGPU
(PU3)
VCCPWRGOOD +VCCSA
RT8205EGQW
C C
CHARGER WQFN24 Page 49
(PU3)
RT8205EGQW
WQFN24 Page 49
+5VALW +3VALW
SUSP SYSON# SUSP PCH_PWR_EN# SUSP SUSP
(U49) (U46) (PU6) (U14) (U68) (UB1)

SI4800BDY TPS2062ADR SY8033BDBC SI4800BDY R599 (RE1) SI4800BDY RT9701-PB
SO8 Page 44 DFN10 Page 51 SO8 Page 44 SO8 Page 44 SOT23-5 Page 45
B B
+5VS +USB_VCCB +1.8VS +3VALW_PCH +3V_LAN +3VALW_EC +3VS +3V
(U39) ENVDD ENVDD VGA_ON

+CRT_VCC
BCM57780 (Q51) (Q30) (Q34)
+3VS_CK505
AO3413L AO3413L AO3413L
SO23-3 Page 37 SO23-3 Page 30 SO23-3 Page 24
+HDMI_5V_OUT
+1.2V_LAN +DVDD_AUDIO
+BT_VCC +LCDVDD +3VSDGPU
+5VS_HDD1
+3V_WLAN
+5VS_ODD
+3V_DMC
A A
+5VAMP +VDDA

Power Rail
5 4 3 2 1
5 4 3 2 1
fix
vina
D D
PCH_PWR_EN# 2
U14,+3VALW_PCH
V
AC A1
MODE VIN QH4,+5VALW_PCH
V V
A2 A3 B5
VV
PU4 A5 2
V
PU6
V
B+ +3VALW_PCH
+3VALW B7 2 3
BATT V +5VALW_PCH
BATT
MODE
B1
B2
B+ B4 V
V
V
EC 4 SYS_PWROK
13
PQ4 PCH_RSMRST# PM_DRAM_PWRGD
V
V V PCH
B3 A5 B7 5 14
PBTN_OUT# H_CPUPWRGD
CPU
V V
V
51ON# EC_ON
PM_SLP_S3#
PM_SLP_S4# PLT_RST# 15
C C
PM_SLP_S5#
A4 B6 PM_SLP_A# 6
PM_SLP_SUS#
V
V
ON/OFF
SYSON 7 SYSON# +1.35V
V
PU6
8
SUSP#,SUSP U22 11
V
+5VS
VGATE
V
U21
+3VS
B B
V
U12
+1.35VS
V
PU6
+0.675V
VCCPPWRGOOD
V
V
PU9 PU10
+1.05VS_VCCP +VCCSA
VR_ON 9 PU13
V
+CPU_CORE
A A

Power sequence
5 4 3 2 1
5 4 3 2 1
f ix
vina Version change list (P.I.R. List) Page 1 of 2
for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
Add PU1 SA003310280 (S IC LMV331IDCKRG4 SC70 5P COMPARATORS)
Add PQ27 SB000009Q80(S TR 2N7002KW 1N SOT323-3)
Acer will add pull down resistor in adapter to 0.1 36 Add PR13 PR16 SD034100280(S RES 1/16W 10K +-1% 0402) 2011/12/05 EVT2
D
1 Add ADP_ID circuit detect ADP_ID. Add PR14 SD034100380(S RES 1/16W 100K +-1% 0402) D
Add PU3 SA00003K300 (S IC G718TM1U SOT23 8P OTP)

Add PR30 SD000009R00(S RES 1/16W 46.4K +-1% 0402)
Acer request add a thermistor on jack of Add PR35 SD034953180(S RES 1/16W 9.53K +-1% 0402)
2 Add Jack_TEMP and PH1 circuit DC in cable to protect jack. 0.1 37 Add PR37 SD034232280(S RES 1/16W 23.2K +-1% 0402) 2011/12/05 EVT2
Del PR127 SD028000080(S RES 1/16W 0 +-5% 0402)
Adjust 1.35V ocp setting and Adjust 1.35V ocp setting Change PR88 to SD000003580(S RES 1/16W 19.6K +-1% 0402)
3 add boost resistor Add boost resistor 0.1 40 Change PR86 to SD013220B80(S RES 1/10W 2.2 +-5% 0603) 2011/12/05 EVT2
Change PR111 to SD013220B80(S RES 1/10W 2.2 +-5% 0603)

Add 1.05V boost resistor and Change PR116 to SD034487100(S RES 1/16W 4.87K +-1% 0402 (LF))
Add 1.05V boost resistor and adjust output voltage 0.1 41 Change PL14 to SH00000KS00(S COIL 1UH +-20% 2011/12/05 EVT2
4 adjust output voltage
Change choke to 1uH for efficiency of heavy load VMPI0703AR-1R0M-Z01 11A)
Change choke to 1uH
Adjust GFX frequence Adjust GFX frequence to 400kHz for reduce ripple 0.1 43 Change PR143 to SD034365280(S RES 1/16W 36.5K +-1% 0402) 2011/12/05 EVT2
5
Change PC273 to SGA00006J00(S POLY C 560U 2V M
D2 LESR4.5M SX H1.9)
Adjust CPU output cap Adjust CPU output cap for transient 0.1 44 unpop PC272 SGA20331E10(S POLY C 330U 2V Y D2 2011/12/05 EVT2
6 LESR9M EEFSX H1.9)
C C
7 Adjust 0.675V enable timing Adjust 0.675V enable timing 0.1 40 Change PC325 to SE076104K80(S CER CAP .1U 16V K X7R 0402) 2011/12/05 EVT2
Change PU11 to SA000055100(S IC SY8032ABC SOT23 6P PWM)

Change PR107 to SD034100480(S RES 1/16W 1M +-1% 0402)
8 Change 1.05VS_LCP from APL5930 to SY8032 for Add PL8 to SH00000MN00(S COIL 1UH +-20% PH041H-1R0MS 3.8A)
Adjust 1.05VS_LCP sequence thoundbolt sequence. 0.2 42 Add PR110 to SD002470B80(S RES 1/8W 4.7 +-5% 0805) 2012/01/05 DVT
Change PC111 to SE074681K80(S CER CAP 680P 50V K X7R 0402)
Change PC92 to SE000008L80(S CER CAP 22U 6.3V M X6S 0805 H1.25)
Add PR123 to SD028100380(S RES 1/16W 100K +-5% 0402)
Change PR108 to SD034100280(S RES 1/16W 10K +-1% 0402)
9 Change PR109 to SD034750180(S RES 1/16W 7.5K +-1% 0402)
Change PC94 to SE071680J80(S CER CAP 68P 50V J NPO 0402)
10 add boost resistor add Charger boost resistor 0.2 38

Change PR48 to SD013220B80(S RES 1/10W 2.2 +-5% 0603) 2012/01/05 DVT
11 add boost resistor add 3V5V boost resistor 0.2 39 Change PR73 and PR74 to SD013220B80(S RES 1/10W 2.2 +-5% 0603) 2012/01/05 DVT
B B
12 add boost resistor add CPU and GFX boost resistor 0.2 43 Change PR194 and PR206 to SD013220B80(S RES 1/10W 2.2 +-5% 0603) 2012/01/05 DVT
13 Change main source Change main source for reduce component kind 0.2 39 Change PL7 to SH00000MB00(S COIL 4.7UH +-20% 2012/01/05 DVT
FDSD0630-H-4R7M=P3 5.5A (7*7*3))
change PR30 to SD034442280(S RES 1/16W 44.2K +-1% 0402)

14 Adjust Jack_TEMP resistor Adjust Jack_TEMP resistor, because PCCP change 0.2 37 change PR37 to SD034215280(S RES 1/16W 21.5K +-1% 0402) 2012/01/05 DVT
thermistor to 0603 size(TSM1A104F4361RZ)
Add PR23 to SD028000080(S RES 1/16W 0 +-5% 0402)

Add ADP_ID circuit Add ADP_ID circuit(65W) 0.2 36 change PR16 to SD034270280(S RES 1/16W 27K +-1% 0402) 2012/01/05 DVT
15 Add PC142 to SE074102K80(S CER CAP 1000P 50V K X7R 0402)
16 Change main source Change main source for 不不不不不 with HW 0.2
change PQ7,PQ26,PQ15,PQ27,PQ48 from SB000009Q80
to SB000009610(S TR SSM3K7002FU 1N SC70-3) 2012/01/31 DVT
A A
17

PIR (PWR)
http://vinafix.vn
Custom 1.0
5 4 3 2 1
5 4 3 2 1
f ix
vina Version change list (P.I.R. List) Page 2 of 2
for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
D
18 Del ADP_ID circuit
Acer will change adapter type to
so del ADP_ID circuit.
音音音 from PoGo, 0.3 36
Del
Del
Del
PU1 SA003310280 (S IC LMV331IDCKRG4 SC70 5P COMPARATORS)
PQ27 SB000009Q80(S TR 2N7002KW 1N SOT323-3)
PR13 SD034100280(S RES 1/16W 10K +-1% 0402)
2012/03/13 PVT
D
Del PR14 SD034100380(S RES 1/16W 100K +-1% 0402)
Del PR23 to SD028000080(S RES 1/16W 0 +-5% 0402)
Del PR16 to SD034270280(S RES 1/16W 27K +-1% 0402)
Del PC142 to SE074102K80(S CER CAP 1000P 50V K X7R 0402)
19
Del PU3 SA00003K300 (S IC G718TM1U SOT23 8P OTP)
音音音 from PoGo,

Del PR30 to SD034442280(S RES 1/16W 44.2K +-1% 0402)
Del PR35 SD034953180(S RES 1/16W 9.53K +-1% 0402)
Acer will change adapter type to
20 Del jack_temp circuit so del jack_temp protect circuit. 0.3 37
Del PR37 to SD034215280(S RES 1/16W 21.5K +-1% 0402)
Add PC17 SE076104K80(S CER CAP .1U 16V K X7R 0402)
2012/03/13 PVT
Change PR29 to SD00000AJ80(S RES 1/16W 12.4K +-1% 0402)
SPOK change to EC_SPOK For reduce power consumption of DS3, so close +VSB 0.3 37 Del PR28 SD034100380(S RES 1/16W 100K +-1% 0402) 2012/03/13 PVT
21 power in DS3, DS4, DS5. Del PR34 SD028100180(S RES 1/16W 1K +-5% 0402)
Del PC15 SE000000K80(S CER CAP 1U 6.3V K X5R 0402)
Change PU10 to SA00005O000(S IC SY8037DDCC DFN 12P PWM)

change VCCSA IC version SY8037C IC version change to SY8037D for accord with 0.3 42 2012/03/13 PVT
22 intel VCCSA spec.
Add snubber Add snubber of GFX by hw request. 0.3 43 Add PR200 SD001470B80(S RES 1/4W 4.7 +-5% 1206) 2012/03/13 PVT
23 Add PC190 SE074681K80(S CER CAP 680P 50V K X7R 0402)
C C
Add PU17 SA00005NY00(S IC MP2334DD-LF-Z QFN 12P PWM)
Add PL28 SH00000N000(S COIL 2.2UH +-20% 1231AS-H-2R2M=P3 1.9A)
HW change motor power solution to PWM. 0.3 45 Add PC366 SE00000OU00(S CER CAP 1U 16V K X5R 0402)
24 Add MOTOR POWER Add PC367 SE074471K80(S CER CAP 470P 50V K X7R 0402) 2012/03/13 PVT
Add PC368 SE075103K80(S CER CAP .01U 25V K X7R 0402)
Add PC369, PC371 SE00000MA00(S CER CAP 4.7U 10V K X5R 0603)
Add PC372 SE00000QK00(S CER CAP 10U 25V K X5R 0805 H1.25)
Add PC373 SE068102J80(S CER CAP 1000P 25V J NPO 0402)
25 Add PC375, PC376 SE00000G880(S CER CAP 0.1U 25V K X5R 0402)
Add PR296 SD034300380(S RES 1/16W 300K +-1% 0402)
Add PR297 SD034120280(S RES 1/16W 12K +-1% 0402)
Add PR298 SD028100A00(S RES 1/16W 10 +-5% 0402)
Add PR300 SD034432380(S RES 1/16W 432K +-1% 0402)
Add PR301 SD000000680(S RES 1/16W 8.45K +-1% 0402)
26 Add PR302, PR307, PR308 SD028100380(S RES 1/16W 100K +-5% 0402)
Add PR303 SD000002300(S RES 1/16W 7.68K +-1% 0402)
Add PR304 SD034576180(S RES 1/16W 5.76K +-1% 0402)
Add PR299, PR305, PR306 SD028100280(S RES 1/16W 10K +-5% 0402)
27 Add PQ49 SB00000DH00(S TR DMN66D0LDW-7 2N SOT363-6)
Because thunder bolt adapter is 40W, OCP 130%

28 adjust HW throttling to 125% 50W
Adjust HW throttling point 0.3 37 Change PR33 to SD034165180(S RES 1/16W 1.65K +-1% 0402) 2012/03/13 PVT
recover point 38W
B B
29
30
31
32
33
A A
34

PIR (PWR)
http://vinafix.vn
Custom 1.0
5 4 3 2 1
5 4 3 2 1
fix
vina Version Change List ( P. I. R. List )
Request
Page 1
Item Page# Title Date Issue Description Solution Description Rev.
Owner
D
0919(In Layout) 0928 1013 D
1.Update R,C 0201,0402,0603,0805,1206 PCB footprint to small size 1.Change RTC cap from 1U 0603 to 1U 0402:C502,C516 1.Add Step Motor circuit
2.Swap DDR Data BUS 2.Remove FAN some parts:R753,C788,D51,D52 2.On Board iSSD:i100 change to mSATA SSD
3.Change USB connector foot print to TAIWI_USB005-107CRL-TW_10P-T 3.WLAN change to on board:MD225
0920 4.Change C196,C387,C735,C102 to 0.1uF_0201_10V6K:SE00000SV00 4.Change Card Reader
1.Change U74,U21,U22 mos to 3*3 thermal pad package:SB00000GW00 5.Remove L2 PCIE from Port4 to Port1
CLK from Port5 to Port4
0921 0929 5.Change mSATA SATA port from Port1 to Port0
1.TB chip:U66 footprint add "-NH" for Non HDI 1.Remove C510,C511 6.Add USB port 12 for mSATA
2.1.8p_0402:C402,C404 change to 75ohm_0402:R263,R264 2.Remove Camera Choke:L7,R13,R14 7.Remove D11,D12 and C357,C358 (HDMI RF request)
3.Q1,Q2 change to DMN66D0LDW-7_SOT363-6:SB00000DH00 8.C396,C324 change to 0201
0922 4.R273,R394 change from 0_0603 to 0_0402 9.Remove C472 for +5VALW source cap
1.Change C1457,C1505 form 1.8P 0402 to 0201:SE00000HB80 5.Remove Step Motor SW1
2.Del DDR CHA,B no use CLK1,CLK1# circuit 6.Change LED/B connector from 8 pin to 4 pin 1014
3.Change C606,C607 from D2 330uF to B2 330uF 2.5V ESR 15mohm:SGA00004400 7.Change Jumper from 43*118 to 43*79 1.Remove DPST_PWM buffer:U13,R783,R85
4.Swap total KB connector:JKB1 pin define =>J2,J8,J10,J11 2.Change +3VS_FULL cap:C475,C466 from 0.1uF_0402 to 0201
3.Change SATA cap:C621,C622,C623,C624 from 0.01uF_0402 to 0201
0923 0930
1.Add DS3 function:SUSWARN#,SUSACK#,EC_DRAMRST_GATE 1.Remove +VCCSA cap:C1182,C1183 1017
2.Add Motor function:Motor_IN1,Motor_IN2,Motor_IN3,Motor_IN4, 2.Remove +USB3_VCCA cap:C390 1.Add power source of +VCCAFDI_VRM at P.20
Door_Det_L,Button: KSI0 & KSO10 3.Change C427,C428 to 0.1U_0201_10V6K 2.Update DS3,AOAC control signal connected to EC
3.Remove PCH NCTF test point 4.Add ESD diode:D6 for TP SMBUS
C
4.HDMI Fuse:F1 change to P5WS5 use footprint:F_1812 5.Change L65 to 220ohm 3A 0805 1018~1021 C
5.Remove HDMI common mode choke:L36,L38,L39,L40 6.Swap DDR ChB Data,DQS# 6,7
6.Change 0.1uF_0402_16V7K to 0.1uF_0201_10V6K:SE00000SV00 7.Change U12 mos to 3*3 thermal pad package:SB00000GW00 1024
=>C521,C520,C526,C449,C523,C537,C541,C494,C495,C490,C497,C771,C522,C471,C473 8.Remove X2,C1361,C1362 1.Remove R130
7.Change 0.01uF_0402_16V7K to 0.01uF_0201_10V7K:SE172103K80 9.C378+C375 change to 10uF*1 2.Define DRAM ID
=>C425,C462 10.C460+C459 change to 10uF*1 3.Update TB schematic
8.Change C751,C752 to B2 220uF 2.5V ESR 15mohm:SGA00004500 11.Remove C986,C987,C989,C990 4.Swap USB2.0 ESD pin
=>Add 1uF 0201*10 5.Add on/off BTN for debug
0924
1.Make MB to Audio/B connector pin define 1003 1027
2.Change RP 8.2K:R256,R262,R276,R386 to 8.2K_0402 1.Change EC side GPIO:PWR_LED to PWR_LED#,Remove Q32,R512 1.Swap JTP1 pin for new module
3.Change RP 10K:R386 to 10K_0402 2.For separate coaxial and wire,update eDP MB connector pin define 2.Gerber schematic
4.Update TB schematic p.24,25,27 3.Remove JLED1 connector
5.Change Q64,Q68 from AO3419L:SB000006R10 to AP2301GN-HF:SB000007H10 4.Change C427:0.1U_0402_16V4Z to 0.1U_0201_10V6K:SE00000VS00 1028
6.Integration of all 2N7002 SOT23 parts to SSM3K7002F_SC59-3:SB000009080 For Load BOM
=>Q74,Q20,Q1,Q2,Q32,Q16,Q17,Q14,Q37,Q7,Q21,Q23,Q24,Q5,Q34,Q29,Q60,Q66,Q67,Q72 1005 1.Update Block Diagram
Not yet=>Q6,Q78,Q79 1.Swap DDR ChB Data,DQS# 6,7 2.Update CPU,PCH part number
2.Change PCH PCIE 0.1U_0402_16V7K to 0.1U_0201_10V6K:SE00000SV00 3.Update BOM config
0925 =>C572,C573,C617,C618,C681,C682,C683,C684,C685,C686,C687,C688
1.Delete LVDS function,Combine eDP,Card Reader function to JLVDS1
Remove:R259,R260,R285,R286,R156,R157,TXCLK+-,TX0+1,TX1+-,TX2+-,DDC CLK,DATA
Remove:C462,C425,C412,L20,only place PU:R271,R272,PD:R270,R280
2.Change eDP cap from 0.1U_0402_16V7K to 0.1U_0201_10V6K:SE00000SV00
=>C910,C911,C912,C913,C914,C915
3.Add R80:0ohm of H_CPU_PWRGD for ESD request
1101
1.For 整整整
2.Combine PWR schematic
B
2.Change all SSM3K7002F_SC59-3:SB000009080 to SSM37K002FU_SC70-3:SB000009610 4.Remove On Board WLAN:MD225 3.A test SMT schematic B
=>Q74,Q20,Q1,Q2,Q32,Q16,Q17,Q14,Q37,Q7,Q21,Q23,Q24,Q5,Q34,Q29,Q60,Q66,Q67,Q72 5.Add Motor parts(Not Ready)
Not yet=>Q6,Q78,Q79 6.Add iSSD i100 parts(Not Ready)
3.Change 10U_0805_6.3V6M:SE093106M80 to 10U_0603_6.3V6M:SE000005T80
=>C754,C543,C418,C465 1006
4.Remove 0_0603_5%:R416,R421,R426,R327 1.Change R754,R751 0ohm from 0603 to 0402
2.Change C484 0.1U from 0603 to 0402
0926 3.For DS3,Change power source from +3VALW_PCH to +VCCSUS3_3
1.Change HDMI level shift Q16,Q17 to DMN66D0LDW-7_SOT363-6:SB00000DH00 4.Change R629 from 0_0805 to 0_0402
2.Modify TB schematic 0402 cap to 0201 5.Change SATA cap from 0.1U_0402_16V7K to 0.01U_0201_10V7K
=>C621~C628
0927
1.Remove J7 1010
2.Change C599 330U D2 2V ESR 9mohm to 330U B2 2.5V ESR 15mohm:SGA00004400 1.Add BATT_RST#,VR_LEFT,VR_RIGHT pin
3.Change EC +3VALW_EC 2.Add iSSD i100 128GB*2 schematic
0.1U_0402_16V4Z to 0.1U_0201_10V6K:SE00000SV00 3.Add USB_HPD# pin
=>C1198,C1199,C1200,C1201,C1204
1000P_0402_50V7K to 1000P_0201_16V7K:SE000007U80 1011
=>C1202,C1203
4.Remove R329
5.Change C751,C752 to 22U_0805_6.3V6M:SE000000I10
1.Add Battery Reset function
2.Swap USB2.0,3.0 choke for connector side 順順
6.Remove J4(one of +1.05VS_VTT to +1.05VS_PCH jumper)
A A

EE P.I.R
5 4 3 2 1
5 4 3 2 1
f ix
ina
Version Change List ( P. I. R. List ) Page 2
vItem Page# Title Date
Request
Issue Description Solution Description Rev.
Owner
1201(EVT2 Gerber) 0303 (PVT) 0402 Modify for 1.0 layout
1.Modify EVT1 SMT memo into Schematic Modify DVT SMT memo for BOM 1.Add soft start R756,C819 of Q68:+VCCSUS3_3 and R757,C820 of Q64:+V5REF_SUS
2.Add 1U_0201_4V_6M *4(C1511,C1512,C1513,C1514) for ChA 1.C744,C745 change from 10P 25V J NPO 0402:SE00000F180 2.Add TB GPIO7(R1129) to PCH GPIO49,GPIO6(R1128) to PCH GPIO20
D D
3.Add 1U_0201_4V_6M *4(C1515,C1516,C1517,C1518) for ChB to 10P 50V J NPO 0402:SE071100J80 3.Add TB wake# colay:R1098 to U53.64(EC GPIO49),PH R976 to +3VALW_EC
4.Delete ChA,ChB SPD ROM(U70,U72) circuit 2.For INTEL TB review,pop R1036,R1037,R1048,unpop R1046,R1047,R1066 4.Add TB +3VS_POC jumper colay +3VS(J4) and +3VALW(J2)
5.JLVDS.15 change from VR_LEFT to GND 3.TB,C1424,C1425 change from SE000000K80:1U_0402_6.3V6K 5.Delete colay J13(+3VALW to +VCCSUS3_3),R751(+5VALW to +V5REF_SUS)
6.TB,pull high PCH_DPD_CLK,PCH_DPD_DAT to +3VS(R252,R254) to SE076104K80:.1U_0402_16V7K 6.Add C1519:10U_0603 for +0.675VS
7.TB,add Buffer:U3 EN pin pull down resistor:R1075 4.For USB enable pin change from SYSON#:R952 to USB_EN#:R951 7.Change C1468,C1471,C1476,C1477,C1478,C1491,C1492,C1499 from
8.TB,Change R1067 pull down form PA_LSRX_LSOE1_R to PA_LSRX_LSOE1_U Modify PVT layout 0.1U_0201_10V6K to 1U_0402_6.3V6K
9.WLAN,Modify PCIE TX,RX,change P/N of RX signal 0.Remove on/off# BTN SW1 footprint 8.Add R277,R1109 for MOS Vgs(th) reserve.
10.WL_OFF# connected to EC_Pin71 1.Change BT port from Port13 to Port8 9.Change Motor BTN SW:R974 from 0ohm_short to normal 0ohm
BT_ON# connected to EC_Pin117 2.Remove TCM parts:U8,R964,R965,C12,C1225 10.Add C790,C791 of VGATE for ESD team
11.mSATA,+3VS_FULL:Change C455 to 4.7U_0603_6.3V_6K,+1.5VS:Delete C433 3.Remove EC 930 SPI ROM:U38,R694,R690,R698,R705,R692,C722,R695,C727 11.Reduce Jumper size from 43*118 to 43*79:PJ17,PJ7,J3
12.Update Motor circuit,P.30 4.Remove SUS_PWR_DN_ACK for S3:EC U53.19,R409,R411 Change Jumper sixe from 43*118(PJ1) to 43*79(PJ1)+43*39(PJ8)
13.Add TPM/TCM co-layout circuit,P.30 5.Update JLVDS1 pin define for +3VALW short issue Change Jumper sixe from 43*118(PJ2) to 43*79(PJ2)+43*39(PJ10)
14.USB PWR SW IC enable pin co-lay SYSON# and USB_EN#_R(EC_Pin81) 6.Add JLED1 connector
15.EC,P.32 7.Remove JMT1,JMT2,JRTC1 and Change to JMR1 8pin conn. 0411 Modify for PreMP SMT
(1)power source co-lay +3VALW/+3VLP 8.Add EC U53.19:IRST_RST# (R461) to U26.1 for IOAC+IRST issue update PVT SMT memo
(2)DC mode S4/S5 turn on +3VALW,+5VALW for Motor, MOTOR_BTN(EC_Pin17) 9.Change 0ohm to 0ohm_short:R80,R314,R320,R372,R382,R394,R412,R421, 1.Add C787:100P_0201_25V8J for PM_DRAM_PWRGD
(3)PPS_L connected to MOTOR_PPS_L(EC_Pin85) R577,R578,R579,R581,R582,R612,R629,R661,R785,R940,R947,R953,R956, 2.Add C785:100P_0201_25V8J and C786:100P_0402_50V8J for DIMM_DRAMRST#
(4)PPS_R connected to MOTOR_PPS_R(EC_Pin91)
(5)Turn on/off Motor +5VALW connected to MOTOR_PWR_ON(EC_Pin21)
(6)Audio/B add Motor LED connected to MOTOR_LED#(EC_Pin36)
10.For WLAN漏漏
R959,R967,R973,R974
issue,Change PCH_PCIE_WAKE#_R(EC_PME#) pull high
from +3VALW to +3VS_WLAN.Add R962,Remove R943
3.Add C788:100P_0402_50V8J for SM_DRAMRST#
4.Add C789:100P_0402_50V8J for SYS_PWROK
5.For TB GPIO6,GPIO7,change PH to PL,unpop R1036,R1037,pop R1046,R1047
(7)BI_DET changed to EC_Pin25 11.Change Motor Power source from PMOS to NMOS 6.Delete Q65 for TB GPIO6,GPIO7
(8)Adapter ID pin connected to ADP_ID(EC_Pin64) Remove:R452,R453,Q69,C818,R754,J14 7.Add TB_FORCE_PWR_R to PCH,pop R1097,unpop PH:R657 at PCH side
16.Update JAUDIO connector type and pin define,P.33 Add:U23,Q90,R459,C472,C503,C504,C481,R460 8.For TB_PLUG_EVENT,unpop PCH side PH:R406
17.Add Motor BTN circuit,P.33 12.Remove net :ADP_ID update for PreMP
1207 13.For TB ref. design,Add dual PMOS Q91,Q92,NMOS Q32,R1124 1.Add C790:100P_0402_50V8J,C791:100P_0201_25V8J for VGATE
C C
1.PCH_ACIN pull high R341 Change from 200K to 10K 0306 2.Change Board ID to "4" for 1.0=>R960:56K
14.Add DPWROK PL:R463 for INTEL suggestion 3.Change PCH from SA00005AG00:HM77 QPRG to MP version SA00005AGI0:HM77 SLJ8C
15.Remove JP1 EC debug port 4.TB chip change to MP version:NA
16.Remove MDP_HPD ESD:D45 5.Change LA8481P from DA6:DAA00003N00 to DAZ:DAZ0NS00100
17.Add H11:H_4P0N for eDP connector 6.Change Y1:25MHz cap:C744,C745 from 10P to 8.2P_0402_50V8D
18.Add EC_SPOK(U53.120) to control +VSBP 7.For VR,change R454,R455 from 100K_5% to 100K_1%
0108(DVT) 19.add BT_LED U53.119 control pin,R492 8.Add C1261,C1291 2.2U_0603_6.3V6K for DDR Memory test issue
1.For DS3,change P.18 PCH power source from +3VALW_PCH to +VCCSUS3_3 20.add TB_FORCE_PWR:R1097 to PCH_GPIO12 9.Change C1504,C1501,C1517,C1503,C1511,C1460,C1462,C1514
(R422,R657,R391,R397,R458) 21.Add WLAN discharge circuit:Q62B,R473=>Remove from 0.1uF 0201 to 1uF 0201
2.Change TB_CLKREQ#_R power source from +3VS_POC to +3VS_LC (Q67,R1031) 22.For ACER TB request,add PH R1125 to +3VS_POC 10.Change TB R1083,R1078,R1089,R1080,R1081,R1082,R1088,R1086
3.Change Q67 direction 0308 from 12.1ohm to 0ohm,R1086 change to @
4.Change TB_SMB_DA,TB_SMB_CLK from PH +3VS_LC(R1036,R1037) to PL(R1046,R1047) 23.Remove ME RST# 0ohm:R561
5.Change Q71 +3VS_LC enable pin from EN_LC_PWR to 1.05VS_LC_PG 24.Add C785,C786,C787,C788,C789 for ESD request 0412 Modify for 1A layout
6.Change R1110 from 348K_0402_1% to 35.7K_0402_1% 25.Add Q69 group(Q69,Q62B,R452,R453,R754,C818,R474,C540) for +3V_MCU 11.For Motor_BTN,add PH:R909 to +3VLP
7.Change TB_GO2SX from PL to PH +3VS_POC(R1066) 26.Change +3VS_FULL:J8 from 43*79 to 43*39 12.Remove EC_TB_WAKE#:R1098
8.Add TCM (U8) package into board file 0309 13.For LEGO,Change control pin from PCH to EC
9.For EC_PME#,R490 change to pop 27.Change Q62 dual 2N7002 to normal 2N7002 (1)LED:PCH_GPIO34 change to EC_GPIO122(TB_LED)
10.For Motor BTN,R974 change to pop 28.Add IRST_RST# PH:R965 to +3VALW_EC (2)Eject:PCH_GPIO48 change to EC_GPIO64,pop R976(TB_EJECT_BTN)
11.Add MSATA RAID0 function (C625,C627,C626,C628) 29.Motor +3V_MCU design: (3)pop Q30,Q31,R1125,unpop R1056,R1057
12.Add PCH:GPIO35 to RAID0_DET,external pull down(R329) Delete PMOS:Q69 group(Q69,Q62B,R452,R453,R754,C818,R474,C540)
13.Change TP from 6 pin to 8 pin,Add level shift Q9 Add NMOS:Q87 group(Q87,Q93,R21,R789,C811)
14.Combine Q66,Q67 to Q89 dual package
15.For DS3,Add EC.82 ACPRESENT to PCH_ACIN(pop R456,unpop D19)
16.For eDP only,PCH_GPIO71 change from PL to NC(unpop R618)
17.For Motor VR,change from PH to PL 100K(R454,R455)
B 0113 B
0312 Modify for PVT SMT
1.Remove mSATA USB port12
1.For EC_SMI#,R939 change to @
2.For ESD request,Reserve 0.1uf for FAN_SPEED1,FAN_PWM (C451,C450)
2.For PCH_ACIN,R341 change to @
0117 (Final Schematic for Gerber)
3.For ACER only,TPM change from SA00005EG00 to SA00005PH00
1.Add Q30,Q31 for "LED" TB cable
4.Change SPOK control function from PWR to EC_SPOK
2.Add MD222 BT_LED test point:T74
5.Change HDMI cap form SE076103K80:0.01u to SE076104K80:0.1u:C280~C287
3.Add test point T75,T76,T77,T78,T79,T80 for TB boundary scan
6.Change Board ID form 1 to 2,R960 chnage to 18K_0402_5%
0120
7.For Vgs(th) issue,change Q20 from 2N7002 to BSS138(SB000002X00)
1.Unpop Power BTN(SW1)
8.For Q5LJ1 RTC issue,
2.For change BID from 0 to 1,pop R957:8.2K
change X1 from SJ10000DM00:S CRYSTAL 32.768KHZ 12.5PF 9H03200019 to
3.For DS3,S3,Change R418 BOM config from S3@ to normal
缺缺缺
SJ100004Z00:S CRYSTAL 32.768K 12.5PF 1TJF125DP1A000D
0131
統
統統
9.Remove KB cap 100P_0201*24pcs
1.For ,Change C394,C1000 from SGA00001E00 to SGA00002N80
統缺
C245,C246,C247,C248,C249,C250,C251,C252,C253,C254,C255,C256,C258,C259,
2.For ,Change C599,C607 main source:SGA00004700,2nd source:SGA00004400
C260,C263,C265,C266,C267,C268,C269,C270,C271,C272
3.For ,Change C1484,C1464 main source from SGA20331E10 to SGA19331D10
10.For ME PE review,remove C442
4.For Vendor Report,
11.For cost,Change DDR C1464 to @
Change Y1,Y2 from SJ10000DJ00:25MHZ 20PF +-30PPM 7V25000016 to
12.For cost,Change DDR C1258,C1259,C1261,C1291,C1292,C1293 to @
SJ10000E800:25MHZ 10PF +-20PPM 7V25000014
13.For cost,Change DDR cap from 1uF_0201 to 0.1uF_0201
Change C744,C745 form 27pf to 10pf
C1462,C1461,C1460,C1459,C1514,C1513,C1512,C1511,
Change C1338,C1340 from 20pf to 6.8pf
C1466,C1476,C1477,C1467,C1470,C1471,C1478,C1468
5.For cost,C496,C478 change to unpop
C1504,C1503,C1502,C1501, C1518,C1517,C1516,C1515,
6.For cost,Change C505 from 1uF 0201 to 0.1uF 0201
C1487,C1497,C1498,C1488,C1491,C1492,C1499,C1489
7.For cost,Change C993,C992,C1009,C994,C1006,C1008,C1007,C1010,C986,C1002
14.For cost,Change TB C1406,C1407,C1443,C1444 from 1uF_0201 to 0.1uF_0201
from 1uF 0201 to 0.1uF 0201
0314
8.For ESD request,pop 1000pf for FAN_SPEED1,FAN_PWM (C451,C450)
15.For HF parts,change Q6 from SB501380020 to SB501380050
A and Unpop C579 1000p of FAN_SPEED1 A
16.For HF parts,change Q87 from SB534560020 to SB534560030
9.For IOAC power control by EC,pop Q47
0315
17.Combine Power latest schematic

EE P.I.R
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Q3ZMC UMA M/B Schematics Document

Security Classification Compal Secret Data Compal Electronics, Inc.

USBx14 3.3V 48MHz

TMDS HD Audio 3.3V 24MHz

Thunderbolt WLAN Card reader SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)

RTC CKT. LS-8481P Audio/B

Power On/Off CKT. LS-8482P Card Reader/B

Power Circuit DC/DC LS-8484P Battery/B

BOARD ID Table BTO Option Table

USB Port Table

Security Classification Compal Secret Data Compal Electronics, Inc.

PCI EXPRESS -- GRAPHICS

AE6 eDP_TX[2] PEG_TX[15]

ULV type P/N:

Security Classification Compal Secret Data Compal Electronics, Inc.

D45 DDR3 Compensation Signals

JTAG & BPM

0.1U_0201_10V6K L59 XDP_TDO @ PAD T6

SN74LVC1G07DCKR_SC70-5 R225 BPM#[2] G55 100P_0201_25V8J

RESET# BPM#[5] J59

MC74VHC1G09DFT2G_SC70-5 R829 PM_DRAM_PWRGD

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY B

Address 0~13:For 128*16

CPU 通通DIMM做reset 0_0402_5%

1K_0402_5% DIMM_DRAMRST# SM_DRAMRST#

<5> SM_DRAMRST# SM_DRAMRST# DIMM_DRAMRST#_R

4.99K_0402_1% 100P_0201_25V8J 100P_0402_50V8J 100P_0402_50V8J

4 Dimm not reset 4

Dimm not reset

fix Default "1",EDS R1.0 P.88

CFG7 H49 L47

VCC_VAL_SENSE F53 CFG[11] RSVD35 U14

VSS_VAL_SENSE K43 VCC_VAL_SENSE AH2 1:Disable

BB19 C59 DC_TEST_A59_C59

AU21 RSVD16 DC_TEST_BD61 BE61

PEG DEFER TRAINING CRB1.0 P.12

1: (Default) PEG Train immediately following

Security Classification Compal Secret Data Compal Electronics, Inc.

PEG IO AND DDR IO

Security Classification Compal Secret Data Compal Electronics, Inc.

For Future CPU M3 support,

INTEL Recommend VAXG +VGFX_CORE

+ C607 V17 VCCSA[12] D48 H_VCCSA_VID0

330U_B2_2VM_R15M V18 D49 H_VCCSA_VID1 0.85V V

4 INTEL Recommend VCCSA C995 C996 C997 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

U56 U57 U58 U59

DDR_A_BS0 M2 B2 DDR_A_BS0 M2 B2 DDR_A_BS0 M2 B2 DDR_A_BS0 M2 B2

DDR_A_ODT0 K1 A1 DDR_A_ODT0 K1 A1 DDR_A_ODT0 K1 A1 DDR_A_ODT0 K1 A1

3 DDR3 CTL/ADD Termination 3

M3 support @ R1105 R1106 R290 36_0201_1% R1102 R1103

1 2 DDR_A_WE# END topology

<12,14,6> DRAMRST_CNTRL_PCH 1K_0402_1% R297 36_0201_1%

1 2 DDR_A_MA3 should be kept within 600mils from last SDRAM

R1108 R309 36_0201_1% U4

+VREFCA_A D+ SDATA EC_SMB_DA2 <14,24,32>