Philips Dvdr985
Philips Dvdr985
Philips Dvdr985
Service
Service 2022
Service
Contents
1.
ServiceManual
Technical Specifications 00
Contents
Analog Board CBA (Bottom View)
Diagram PWB
53
2. Safety & Maintenance Instructions, Warnings and Notes 00 DVIO Front Board CBA (Top View) 54
4. Mechanical Instructions 00 DVIO Board CBA (Top View) 55
5. Service Modes, Error Codes and Faultfinding 00 DVIO Board CBA (Bottom View) 56
6. Block Diagrams and Testpoints 00 Digital Board CBA (Top View) 57
Digital Board CBA (Bottom View) 58
7. Electrical Diagrams and PWB's Diagram PWB Layout Servo Board 43015: (Top Side) 59
Set Wiring Diagram 1 Layout Servo Board 43015: (Bottom Side) 60
Set Block Diagram 2 Layout Servo Board 43353: (Top Side) 61
Basic Engine Block Diagram 3 Layout Servo Board 43353: (Bottom Side) 62
Power Supply (Page 1) Schematic 4 35 Layout Analog Board (Testlands Top View) 63
Power Supply (Page 2) Schematic 5 35 Layout Analog Board (Testlands Bottom View) 64
Display Panel Schematic 6 37 Layout DVIO Board (Testlands Bottom View) 65
Front AV Panel Schematic 7 39 Layout Digital Board (Testlands Bottom View) 66
IR and Standby Panel Schematic 8 Test Point Overview Servo Board 43015 67
Analog Board: All in One 1 Schematic 9 41 Test Point Overview Servo Board 43353 68
Analog Board: All in One 2 Schematic 10 41 8. Adjustments 00
Analog Board: Tuner / Demodulator Schematic 11 41 9. Circuit Description 00
Analog Board: In / Out 1 Schematic 12 41 10. Spare Parts List 00
Analog Board: In / Out 2 Schematic 13 41
Analog Board: In / Out 3 Schematic 14 41
Analog Board: Sound Processing Schematic 15 41
Analog Board: Power Supply Schematic 16 41
Analog Board: Converter Schematic 17 41
Analog Board: RGB-YUV Converter Schematic 18 41
Analog Board: Digital In / Out Schematic 19 41
Analog Board: Fan Control Schematic 20 41
DVIO Front Board Schematic 21 43
DVIO Board: 1394 Interface Schematic 22 44
DVIO Board: Microprocessor Schematic 23 44
DVIO Board: Fifo & Control Schematic 24 44
DVIO Board: DVCODEC Schematic 25 44
DVIO Board: Audio & Video Output Schematic 26 44
Digital Board: VSM, Buffer Mem & Bit Engine Interface Schematic 27 46
Digital Board: AV Decoder STI5508 Schematic 28 46
Digital Board: AV Decoder Memory 29 46
Digital Board: Video Encoder, Empress 30 46
Digital Board: VIP CVBS Y/C Video Input 31 46
Digital Board: Analog Board Cons. Video In / Output 32 46
Digital Board: Progressive Scan - 1 33 46
Digital Board: Progressive Scan - 2 34 46
Digital Board: Power, Clock, and Reset Audio Clock 35 46
Servo Board 43015: Pre- Processor Schematic 36 58
Servo Board 43015: MACE3 Schematic 37 58
Servo Board 43015: Driver Schematic 38 58
Servo Board 43015: Decoder / Encoder Schematic 39 58
Servo Board 43015: Power Schematic 40 58
Servo Board 43353: Pre- Processor Schematic 41 60
Servo Board 43353: MACE3 Schematic 42 60
Servo Board 43353: Driver Schematic 43 60
Servo Board 43353: Decoder / Encoder Schematic 44 60
Servo Board 43353: Power Schematic 45 60
Power Supply CBA (Top View) 46
Power Supply CBA (Bottom View) 47
Display Panel CBA (Top View) 48
Display Panel CBA (Bottom View) 49
Front AV Panel CBA (Top) 50
Front AV Panel CBA (Bottom) 51
Analog Board CBA (Top View) 52
Safety Instructions
General Safety
Safety regulations require that after a repair, you must return the unit in its original condition.
Pay, in particular, attention to the following points:
z Route thewires/cables correctly, and fix them with the mounted cable clamps.
z Check the insulation of the mains lead for external damage.
z Check the electrical DC resistance between themains plug and the secondary side:
1. Unplug themains cord, and connect a wire between the two pins of the mains plug.
2. Set the mains switch to the "on" position(keep the mains cord unplugged!).
3. Measure the resistance value between the mainsplug and the front panel, controls,
and chassis bottom.
4. Repair or correct unit when the resistance measurementis less than 1 MΩ.
5. Verify this, before you return the unit to the customer/user (ref. UL-standard no.
1492).
6. Switch the unit ‘off’, and remove the wire between the two pins of the mains plug.
Laser Safety
This unit employs a laser. Only qualified service personnel may remove the cover, or attempt
to service this device(due to possible eye injury).
Feature Data
z Type : Semiconductor laser GaAlAs
z Wavelength : 650 nm (DVD)
: 780 nm (VCD/CD)
z Output Power : 20 mW(DVD+RW writing)
: 0.8 mW(DVD reading)
: 0.3 mW(VCD/CD reading)
z Beam divergence : 60 degree
Figure:
Note: Use ofcontrols or adjustments or performance of procedure other than those specified
herein, may result in hazardous radiation exposure. Avoid direct exposure to beam.
Warnings
General
z AllICs and many other semiconductors are susceptible to electrostatic discharges (ESD,
w).Careless handling during repair can reduce life drastically. Make sure that, during
repair, you are at the same potential as the mass of the set by a wrist band with
resistance. Keep components and tools at this same potential. Available ESD protection
equipment:
Complete kit ESD3 (small tablemat, wristband, connection box, extension cable
z Be careful during measurements in the live voltage section. The primary side of the
power supply (pos. 1005), including the heatsink, carries live mains voltage when you
connect the player to the mains (even when the player is "off"!). It is possible to touch
copper tracks and/or components in this unshielded primary area, when you service the
player. Service personnel must take precautions to prevent touching this area or
components in this area. A "lightning stroke" and a stripe-marked printing on the printed
wiring board, indicate the primary side of the power supply.
z Never replace modules, or components, while the unit is ‘on’.
Laser
z Theuse of optical instruments with this product, will increase eye hazard.
z Only qualified service personnel may removethe cover or attempt to service this device,
due to possible eye injury.
z Repair handling should take place as much aspossible with a disc loaded inside the
player.
z Text below is placed inside the unit, on the laser cover shield:
Figure:
Notes
Dolby
Manufactered under licence from Dolby Laboratories. “Dolby”, “ProLogic” and the double-D
symbol are trademarks of Dolby Laboratories. Confidential Unpublished Works.©1992-1997
Dolby Laboratories, Inc. All rights reserved.
Figure:
Trusurround
TRUSURROUND, SRS and symbol (fig 2-4) are trademarks of SRS Labs, Inc.
TRUSURROUND technology is manufactured under licence frm SRS labs, Inc.
Figure:
Video Plus
“Video Plus+” and “PlusCode” are registered trademarks of the Gemstar Development
Corporation. The “VideoPlus+” system is manufactored under licence from the Gemstar
Development Corporation.
Figure:
Macrovision
This product incorporates copyright protection technology that is protected by method claims of
certain U.S. patents and other intellectual property rights owned by Macrovision Corporation
and other rights owners.
Use of this copyright protection technology must be autorized by Macrovision Corporation, and
is intended for home and other limited viewing uses only unless otherwise authorized by
Macrovision Corporation. Reverse engineering or disassembly is prohibited.
TechnicalSpecifications and Connection
Facilities
General:
Feature Data
z Mains voltage : 120V (90 -140VAC)
z Mains frequency : 50 Hz - 60Hz
z Power consumption mains : 32 W (typical, record)
z Power consumption standby :<7W
z Power consumption low power
:<3W
stand-by
RF Tuner
Test equipment : Fluke 54200 TV Signal generator
Test streams : PAL BG Philips Standard test pattern
System:
NTSC-M (USA/BTSC-Stereo+SAP)
Rf - Loop Through:
Feature Data
z Frequency range : 45 MHz - 860 MHz
z Gain: (ANT IN - ANT OUT) : -4 dB /±2 dB
Radio Interference:
Feature Data
z input voltage /3tone method
: typ. 80 dBμV at 75 Ω
(+40 dB min)
Receiver:
PLL tuning with AFC for optimum reception
Feature Data
z Frequency range: : 45.25 MHz - 860 MHz
z Sensitivity at 40 dB S/N : ≥ 60dBμV at 75 Ω (video unweighted)
Video Performance:
Audio Performance:
Audio-BTSC:
Feature Data
z Frequency responseat audio
: 40 Hz - 15 kHz / ± 1,5 dB
cinch output:
z S/N according to DIN 45405,
:
7,1967
z and PHILIPS standard test
: ≥ -50 dB unweighted
pattern videosignal:
z Harmonic distortion ( 1 kHz, ±
: ≤ 0.5 %
25 kHzdeviation ):
Audio-SAP:
Feature Data
z Frequency responseat audio
: 40 Hz - 15 kHz ± 1,5 dB
cinch output:
z S/N according to DIN 45405,
:
7,1967
z and PHILIPS standard test
: ≥ -60 dB unweighted
pattern videosignal
z Harmonic distortion (1 kHz): : ≤ 0.5 %
Tuning
Feature Data
z scanning time withoutantenna : ≤ 2,5 min
z stop level (vision carrier) : ≥ 65dBμV, 75 Ω
z Maximum tuning error of a
: ± 62,5 kHz
recalled program
z Maximum tuning error during
: ± 100 kHz
operation
Tuning Principle
Automatic detection
Manual channel activation
Analogue inputs
Audio
Feature Data
z Input voltage : 2 Vrms
z Input impedance : >10k Ω
Video - Cinch
Feature Data
z Input voltage : 1 Vpp ± 0.1V
z Input impedance : 75 Ω
Video - YC (Hosiden)
Feature Data
z Input voltage Y : 1Vpp ± 0.1V (with sync)
z Input impedance Y : 75 Ω
z Input voltage C : burst 286 mVpp ± {x} dB
z Input impedance C : 75 Ω
Feature Data
z Input voltage : 2 Vrms
z Input impedance : >10k Ω
Video (EXT2-USA)
Feature Data
z Input voltage : 1 Vpp ± 0.1V (with sync)
z Input impedance : 75 Ω
Feature Data
z Input voltage Y : 1Vpp ± 0.1 (with sync)
z Input voltage Pr : 0.7 Vpp
z Input voltage Pb : 0.7 Vpp
z Input impedance : 75 Ω
Video Performance
All outputs loaded with 75 Ohm
SNR measurements over full bandwidth without weighting.
Feature Data
z SNR Luminance : > -65 dB
z SNR Chrominance AM : > -65 dB
z SNR Chrominance PM : > -65 dB
z Bandwidth Luminance : 5 MHz ± 1dB
Feature Data
z SNR : > -65 dB
z SNR Chrominance AM : > -65 dB
z SNR Chrominance PM : > -65 dB
z Bandwidth Luminance : 5 MHz ± 1dB
Feature Data
z SNR : > -65 dB
z Bandwidth : 5 MHz ± 1dB
Audio Performance
Feature Data
z Output voltage 2channel mode : 2Vrms ± 1.5dB
z Output voltage 5.1 channel
: 1.41Vrms ± 1.5dB
Dolby
z Channel unbalance (1kHz) : <0.85dB
z Crosstalk 1kHz : >105dB
z Crosstalk 20Hz-20kHz : > 95dB
z Frequency response 20Hz-
: ± 0.1dB max
20kHz
z Signal to noise ratio : >100 dB
z Dynamic range 1kHz : >90dB
z Dynamic range 20Hz-20kHz : >88dB
z Distortion and noise 1kHz : >90dB
z Distortion and noise 20Hz-
: >80dB
20kHz
z Intermodulation distortion : >87dB
z Phase non linearity : ± 1( max.
z Level non linearity : ± 0.5dB max.
z Mute (spin-up, pause, access) : >100dB
z Outband attenuation: : > 50dB above 25kHz
Feature Data
z Output voltage 2channel mode : 2Vrms ± 1.5dB
z Output voltage 5.1 channel
: 1.41Vrms ± 1.5dB
Dolby
z Channel unbalance (1kHz) : <0.85dB
z Crosstalk 1kHz : >105dB
z Crosstalk 20Hz-20kHz : > 95dB
z Frequency response 20Hz-
: ± 0.1dB max
20kHz
z Signal to noise ratio : >100 dB
z Dynamic range 1kHz : >90dB
z Dynamic range 20Hz-20kHz : >88dB
z Distortion and noise 1kHz : >90dB
z Distortion and noise 20Hz-
: >80dB
20kHz
z Intermodulation distortion : >87dB
z Phase non linearity : ± 1( max
z Level non linearity : ± 0.5dB max
z Mute (spin-up, pause, access) : >100dB
z Outband attenuation: : > 50dB above 25kHz
Digital Output
Coaxial Output
Feature Data
z CDDA/LPCM(incl. MPEG1) : According IEC958
z MPEG2, AC3 audio : According IEC1937
z DTS : According IEC1937
Optical output
Identical to coaxial
Applicable Standards
Implementation according:
IEEE Std 1394-1995
IEC 61883 - Part 1
IEC 61883 - Part 2 SD-DVCR (02-01-1997)
Specification of consumer use digital VCR’s using6.3 mm magnetic tape - dec.1994
Mechanical connection according:
Annex A of 61883-1
Audio Quality
Feature Data
z Output voltage 2channel mode : 2Vrms +/- 1.5dB
z Channel unbalance (1kHz) : Tbd
z Crosstalk 1kHz : > 95 dB
z Crosstalk 20Hz-20kHz : > 85 dB
z Frequency response 20Hz-
: +/- 1dB max
12kHz
z Signal to noise ratio : >95 dB
z Dynamic range 1kHz : Tbd
z Dynamic range 20Hz-20kHz : Tbd
z Distortion and noise 1kHz : >65dB
z Distortion and noise 20Hz-
: >65dB
20kHz
z Intermodulation distortion : >80dB
z Phase non linearity : +/- 1 degree
z Level non linearity : Tbd
z Mute (spin-up, pause, access) : Tbd
z Outband attenuation : Tbd
DVD
Feature Data
z Output power duringreading : 0.8mW
z Output power during writing : 20mW
z Wavelength : 660nm
CD
Feature Data
z Output power : 0,3mW
z Wavelength : 780nm
Complete Set Exploded View
Front Assembly ExplodedView
Basic Engine Exploded View
Loader Exploded View
DVM Exploded View
(2022)
Vsource(stby Vsource.tif
Alignments
The settings 1,2 and 3 are stored in the NVM during the production of the analog board.
The slash version is stored at the end of the production line of the set.
In case of failure, the NVM must be replaced by an empty device. By way of commands via the
Diagnostic Software or via ComPair, the factory settings must be restored in the NVM.
For an exact functionality of the bar graph in the display, a correction factor for the left and the
right channel is stored in the NVM.
Procedure:
To guarantee an exact function of the real time clock, an adjustment of the clock frequency is
possibe and stored in the NVM.
Procedure:
This function stores the reference voltage for the tuner in the NVM. Before this value can be
stored, the AFC adjustment, described in the adjustment instructions of the analog board, must
be carried out.
Procedure:
Slash Version
The slash version is stored with command 715 followed by the slash version as parameter.
The slash versions used in DVDR1000 and DVDR1500 are the following:
z DVDR980/17X: 103
z DVDR985/17X: 104
Example:
DD:>715 1
Use command 729 to reset the analog board to the default setting.
Procedure:
Scope:
The procedure describes how to upgrade sets with a unique number after repair. This unique
number is stored in the NVRAM (item 7201) of the digital board at the end of the production
line.
This procedure is only valid or necessary when:
In all other cases the repaired set retains its unique number.
The procedure defines several means to re-assure the unique number, depending on the
possibilities of repair or the state the faulty set is in.
Handling:
1. The digital board starts up in Diagnostics Mode: follow procedure A to retrieve the valid
unique number
2. The digital board does NOT start up in Diagnostics Mode: follow procedure B.
Procedure A
1. Connect defective digital board to PC via serial cable (3122 785 90017)
2. start up hyper terminal or any other serial terminal via the correct settings (DSW
command mode interface)
3. read out existing unique number via nucleus 403 example:DD:> 40340300: DV Unique
ID = 00D7A1FC6CTest OK @
4. note read out
5. program new digital board via nucleus 410 example: DD:> 410 00D7A1FC6C41000:Test
OK @
Procedure B
1. Notethe serial number of the set example: AH050136130156
AH = production center Hasselt. According to UAW-500: A=1 and H=8
01 = YEAR
36 = Production WEEK
2. Calculate the unique number: this number always exists out of 10 hexadecimal numbers.
3. First 5 numbers: First we calculate a decimal number according to the formula below:
35828*YEAR + 676* WEEK + 26*A + H + 8788The figures are fixed, YEAR + WEEK +
factory code( A + H) are variable Example: 35828*01+676*36+26*1+8+8788 = 68986
(decimal)Then we translate the decimal number to a hexadecimal number.example:
68986 (decimal)= 10D7A (hex)
4. Last 5 numbers: The last 5 numbers exist out of the Lot and SERIAL number. We have
to translate the decimal number to the next 5 hexadecimal numbers: Example: 130156
(decimal) = 1FC6C (hex)
5. Program new digital board via nucleus 410 Therefore we use the 10 hexadecimal
numbers we calculated above: example:DD:> 410 10D7A1FC6C41000:Test OK @
Service Positions
Front
Figure: Front
DVIO Board
To put the DVIO board in a service position,an extender board must be used. This extender
board can be orderedwith codenumber 3104 128 07770.
Figure: DVIO Extender
Figure: DVIO 1
Figure: DVIO 2
Digital Board
After demounting of DVIO board, the top sideof the digital board is in reach. To reach the
bottom side of thedigital board, the DVDR module must be demounted together with thedigital
board. Connected to each other, the assembly can be setin a service position. In this position,
the bottom side of thedigital board and the servo board are in reach to be serviced.
Figure: Digital 1
Figure: Digital 2
Analog Board
To put the analog board in service position,demount the assembly of analog board and
backplate as follows:
Turn the assembly of the backplate and the analog board againstthe loader.
Figure: Analog Europe
Mechanical Instructions
Index of this chapter:
1. General
2. Disassembly
3. Re-assembly
Note: Figures below can deviate slightly from the actual situation, due to the different set
executions.
General
z Follow the disassemble instructions in described order.
z Do not place the unit with its PWB on a hard surface (e.g. table), as it could damage the
components on it. Always place something soft (a towel or foam cushion) under it.
z Never touch the lens of the laser.
z Take sufficient ESD measures during (dis)assembly.
Disassembly
You can divide the Basic Engine into the following parts:
Loader
PWB
DVD-M
Caution: Never try to align the DVD-Module! ! ! Only the factory can do this properly. Service
engineers are only allowed to exchange the sledge motor assy.
1. Slide the 'tray pin' in the direction of the arrow [1], in order to release the disc tray.
2. Flip the module180 degrees and pull out the tray [2]. Now you can access the DVD-
Module.
3. Remove the four screws [3] with a Torx 6 screwdriver, and lift the DVD-M upwards [4] at
the side of the disc-motor. It hinges in the bracket at the side of the tilt-motor.
Sledge-motor Assy
Caution: Never try to align the DVD-Module! ! ! Only the factory can do this properly. Service
engineers are only allowed to exchange the sledge motor assy.
1. Place the DVD-Module, with the laser facing downwards, on a soft surface.
2. Remove the three screws [1] that hold the sledge-motor assy, and lift the assy upwards.
You can replace it now.
3. If necessary, it is now also possible to replace the sledge-rack [2] that is hinged in the
sledge assy.
Re-assembly
To re-assemble the module, do all processes in reverse order.
Be sure to:
z Sledge-motor assy: Mesh the teeth of the sledge motor and sledge rack properly, during
mounting of the sledge-motor assy.
z DVD-M: Point the laser up (towards the tray), when you mount the DVD-M in the bracket.
z Complete module: Place all wires/cables in their original positions
Diagnostic Software and Faultfinding Trees
Supporting Overviews
z Test points overview Analog Board (Top View)
z Test points overview Analog Board (Bottom View)
z Test points overview DVIO Board (Bottom View)
z Test points overview Digital Board (Bottom View)
z Test points overview Servo Board 43015
z Test points overview Servo Board 43353
z Wiring diagram
General
z Impedance of measuring-equipment should be > 1 MOhm.
z For testing the Basic Engine, connect it to a DVD-recorder of the DVDR1000, 900, or 800
series.
z Most tests are done by software commands. Together with the software command you
will find a Ref.# nbr. This is the number of the diagnostic nucleus used for this test. You
can find information that is more detailed in the chapter 'Diagnostic Nuclei'.
Due to the complexity of the DVD recorder,the time to find a defect in the recorder can
become long. To reducethis time, the recorder has been equipped with Diagnostic and
Service software(DS). The DS offers functionality to diagnose the DVDR hardwareand
tests the following:
{ Interconnectionsbetween components
{ Accessibility of components
Description
The End user/Dealer script interfacegives a diagnosis on a stand alone DVD recorder; no
other equipmentis needed. During this mode, a number of hardware tests (nuclei)are
automatically executed to check if the recorder is faulty. The diagnosisis simply a "fail" or
"pass" message. If the message "FAIL" appearson the display, there is apparently a
failure in the recorder. Ifthe message "PASS" appears, the nuclei in this mode have been
executedsuccessfully. There can be still a failure in the recorder becausethe nuclei in this
mode don"t cover the complete functionalityof the recorder.
Contents
Figure:
The End use/Dealer script executesall diagnostic nuclei that do not need any user
interaction andare meaningful on a standalone DVD recorder. The nuclei called inthe
End user/Dealer script are the following:
Description
The Player script will give the opportunityto perform a test that will determine which of the
DVD recorder"smodules are faulty, to read the error log and to perform an
enduranceloop test. To successfully perform the tests, the DVD recorder mustbe
connected to a TV set.
To be able to check results of certain nuclei, the playerscript expects some interaction of
the user (i.e. to approve a test pictureor a test sound). Some nuclei (e.g. nuclei that test
functionalityof the DVDR module) require that a DVD+RW disc is inserted.
Only tests within the scope of the diagnostic softwarewill be executed hence only faults
within this scope can be detected.
The player script consists of a set of nucleitesting the hardware modules in the DVD
recorder: the Display PWB,the Digital PWB, the Analogue In/Out PWB and the DVDR
module.
Nuclei run by the player test need some user interaction;in the next table this interaction
is described. The player testis done in two phases:
{ Interactivetests: this part of the player test depends strongly on user interactionand
input to determine nucleus results and to progress through thefull test. Reading the
error log information can be useful to determineany errors that occurred recently
during normal operation of theDVD player.
{ The loop test will perform the same nuclei asthe dealer test, but it will loop through
Remark
In case of failure, the display shows " FAIL XXXXXX ".The description of the shown error
code can be retrieved in the surveyof Nuclei Error Codes (paragraph 5.4). Once an error
occurs, itis not possible to continue the player script. Unplug the set andrestart the player
script. By pressing the STOP key, it is possibleto jump over the failure and to continue
the player script.
Player Script
Player Script Continued
Error Log
Explanation:
The application errors will be logged in theNVRAM. The maximum number of error bytes
that will be visible is19. The last reported error is shown as DN D0000000, the
oldestvisible error as D0000000 UP and the errors in between as DN D0000000UP. DN
stands for DOWN, UP stands for UPWARDS. The shown
D error codes are identical to the Nuclei Error Codes (paragraph5.4).
Trade Mode
Figure:
Virgin Mode
If you want that the recorder starts up inVirgin mode, follow this procedure:
{ Unplug therecorder
{ plug the recorder again while you keep the STANDBY/ON key pressed
Nuclei Numeration
Each nucleus has a unique number of four digits.This number is the input of the
command mode.
Figure:
Error Handling
Each nucleus returns an error code. This codecontains six numerals, which means:
Figure:
The nucleus group numbers and nucleus numbers are the sameas above.
Hardware required:
{ Service PC
Activation
Plug the recorder to the mains and the followingtext will appear on the screen of the
terminal (program):
Figure:
The first line indicates that the Diagnostic softwarehas been activated and contains the
version number. The next linesare the successful result of the SDRAM interconnection
test and thebasic SDRAM test. The last line allows the user to choose betweenthe three
possible interface forms. If pressing C has made a choicefor Command Interface, the
prompt ("DD>") will appear.The diagnostic software is now ready to receive commands.
The commandsthat can be given are the numbers of the nuclei.
Command Overview
We provide an overview of the nuclei and theirnumbers. This overview is preliminary and
subject to modifications.
Host Decoder [01]
VSM [03]
[xx yy] Number Nuclei
300 Register Access
301 SDRAM Access
302 SDRAM Write Read
303 Interrupt lines
304 VSM Interconnection
305 UART
NVRAM [04]
DVIO [08]
Miscellanious [14]
Activation
Plug the recorder to the mains and the followingtext will appear on the screen of the
terminal (program):
Figure:
The first line indicates that the Diagnostic softwarehas been activated and contains the
version number. The next linesare the successful result of the SDRAM interconnection
test and thebasic SDRAM test. The last line allows the user to choose betweenthe three
possible interface forms. If pressing M has made a choicefor Menu Interface, the Main
Menu will appear.
Menu Structure
The following menu structure is given afterstarting up the DVD recorder in menu mode.
The symbol -> indicatesthat the current menu choice will invoke the display of a
submenu.
Main Menu
1. DigitalBoard ->
2. Analogue Board ->
3. Front Panel ->
4. Basic Engine ->
5. DVIO ->
6. Progressive Scan Board ->
7. Loop Tests ->
8. Log ->
9. Scripts ->
1. HostDecoder ->
2. VSM ->
3. AVENC ->
4. NVRAM ->
1. FlashChecksum
2. Flash1 Write Access
3. Flash2 Write Access
4. Flash Write/Read
5. Host SDRAM Write/Read
6. Host SDRAM Fast Write/Read
7. Host DRAM Write/Read
8. Host DRAM Fast Write/Read
9. I2C NVRAM
10. NVRAM Write/Read
11. Engine S2B Echo
12. Versions ->
13. Audio Mute ->
14. Colourbar ->
15. Pink Noise ->
16. Sine Generate ->
Digital Board Versions Menu
1. HardwareVersion
2. Bootcode version
3. Applications Version
4. Diagnostics Version
5. Download Version
1. AudioMute On
2. Audio Mute Off
Colourbar Menu
1. ColourbarOn
2. Colourbar Off
1. PinkNoise On
2. Pink Noise Off
1. SineOn
2. Sine Burst 1kHz
3. Sine Burst 12kHz
VSM Menu
1. RegisterAccess
2. SDRAM Access
3. VSM SDRAM Write/Read
4. Interrupt Lines
5. VSM Interconnection
6. UART
AVENC Menu
1. Empress ->
2. Video Input Processors ->
Empress Menu
1. Versionnumber
1. SAA7118I2C Access
NVRAM Menu
1. ReadError Log
2. Reset Error Log
3. Read DVIO Unique ID
1. Echo
2. Obsolete
3. Route Video Input back to Digital board
4. Route Audio Input back to Digital board
5. Flash Checksum
6. Versions ->
7. Components ->
8. Re-virginize Recorder ->
1. HardwareVersion
2. Bootcode version
3. Application version
4. Diagnostics version
5. Download version
1. Tuner
2. Data Slicer
3. Sound Processor
4. AV Selector
5. NVRAM
1. Re-virginizeRecorder
2. Set Virgin-bit
3. Clear Virgin-bit
4. Store external presets
1. Echo
2. Version
3. Flap Control ->
4. Segment Test ->
5. Light Labels
6. Led test
7. Keyboard test
8. Remote Control
9. Beep
10. Disc Bar
11. Disc Bar Dots
12. Vu Grid
13. Dimmer
14. Blink
15. Light All Segments
1. OpenFlap
2. Close Flap
1. Starburst
2. Light Horizontal Segments
3. Light Vertical Segments
4. Light All Segments
1. Reset
2. S2B Pass-through
3. S2B Echo
4. Focus On
5. Focus Off
6. Version
7. Self Test
8. Get Self Test Result
9. Basic Engine Test
10. Laser Test
11. Focus Test
12. Tilt Test
13. Optimise Jitter
14. Statistics Info
15. Log ->
16. Spindle Motor ->
17. Radial ->
18. Sledge ->
19. Tray ->
1. ReadError Log
2. Reset Error Log
1. SpindleMotor On
2. Spindle Motor Off
3. Spindle Motor Test
1. RadialOn
2. Radial Off
3. Radial Initialisation
4. Radial ATLS Calibration
1. Sledgetest
2. Sledge test slow
1. TrayIn
2. Tray Out
DVIO Menu
1. CheckPresence
2. Reset
3. Access
4. Error Codes
5. Module Identifiers
6. Led ->
1. LedOn
2. Led Off
1. I2CAccess
2. Test Image On
3. Test Image Off
1. Obsolete
2. Digital Video Loop
3. Digital Video Loop VBI
1. User/DealerAudio Loop
2. User/Dealer Video Loop
3. User/Dealer Video Loop VBI
1. SystemVideo Loop
2. System Video Loop VBI
3. System Audio Loop SCART(EURO)
4. System Audio Loop CINCH (NAFTA)
1. ReadError Log
2. Reset Error Log
Script Menu
1. User/DealerScript
2. Player Script
Error
Error String
Nr
10000 "Checksum is OK"
"segment name Checksum doesn"t match"or "segment name
10001
segment not found"
10100 ""
10101 "FLASH 1 Write access test failed"
10200 ""
10201 "FLASH 2 Write access test failed"
10300 ""
10301 "FLASH write test failed"
10302 "FLASH write command failed"
10303 "FLASH write test done max. number of times"
10400 ""
10401 "HostDec SDRAM Memory data bus test goes wrong."
10402 " HostDec SDRAM Memory address bus test goes wrong."
10403 " HostDec SDRAM Physical memory device test goeswrong."
10500 ""
10501 " HostDec SDRAM Memory data bus test goes wrong."
10502 " HostDec SDRAM Memory address bus test goes wrong."
10503 " HostDec SDRAM Physical memory device test goeswrong."
10600 ""
10601 "HostDec DRAM Memory data bus test goes wrong."
10602 "HostDec DRAM Memory address bus test goes wrong."
10603 "HostDec DRAM Physical memory device test goeswrong."
10700 ""
10701 "HostDec DRAM Memory data bus test goes wrong."
10702 "HostDec DRAM Memory address bus test goes wrong."
10703 "HostDec DRAM Physical memory device test goeswrong."
"Host Decoder version(cut) number: version
10800
number""Digitalhardware version"
10801 "Can not find version in FLASH."
10900 ""
10901 "Error muting audio"
11000 ""
11001 "Error demuting audio"
11500 ""
11501 "Init of I2C failed"
11502 "The selection of the clock source failed"
11504 "The demute of the audio failed"
11600 ""
11601 "Init of I2C failed"
11602 "The mute of the audio failed"
11700 ""
11701 "Init of I2C failed"
11702 "The muting of the audio failed"
11703 "The demute of the audio failed"
11704 "The selection of the clock source failed"
11707 "Setup of Front panel failed"
11708 "Sine on Front panel keyboard failed"
11800 ""
11801 "Init of I2C failed"
11802 "The muting of the audio failed"
11803 "The demute of the audio failed"
11804 "The selection of the clock source failed"
11805 "Error cannot start VSM audio in port"
11900 ""
11901 "Init of I2C failed"
11902 "The muting of the audio failed"
11903 "The demute of the audio failed"
11904 "The selection of the clock source failed"
11905 "Error cannot start VSM audio in port"
12000 ""
12001 "Invalid input
12100 ""
12200 ""
12201 "I2C bus busy before start"
12202 "NVRAM access time-out"
12203 "No NVRAM acknowledge"
12204 "NVRAM time-out"
12205 "NVRAM Write/Read back failed"
12300 ""
12301 "I2C bus busy before start"
12302 "NVRAM read access time-out"
12303 "No NVRAM read acknowledge"
12304 "NVRAM read failed"
13000 "Bootcode application version : bootversion"
13001 "Can not find version in FLASH."
13100 "Recorder application version : recorderversion"
13101 "Can not find version in FLASH."
13200 "Diagnostics application version : diagversion"
13201 "Can not find version in FLASH."
13300 "Download application version : downloadversion"
13301 "Can not find version in FLASH."
13700 ""
13701 "Turning off MacroVision failed"
20000 ""
20001 "I2C bus busy before start"
20002 "Video Encoder access time-out"
20003 "No acknowledge from Video Encoder"
20004 "No data send/received to or fromVideo Encoder"
20005 "SAA7118 VIP can not be initialised"
20200 ""
20201 "I2C bus busy before start"
20202 "SAA7118 VIP access time-out"
20203 "No acknowledge from SAA7118 VIP"
20204 "No data received from SAA7118 VIP"
20300 ""
20301 "Error audio encoder SRAM access cannot initialiseI2C"
"Error audio encoder SRAM access cannot reset
20302
DSPthrough I2C"
20303 "Error audio encoder SRAM access cannot downloadboot"
20304 "Error audio encoder cannot download test code"
20305 "Error audio encoder cannot obtain result oftest"
20306 "Error audio encoder SRAM access stuck-at-zero dataline "
20307 "Error audio encoder SRAM access stuck-at-one dataline "
"Error audio encoder SRAM access stuck-at-one addressline
20308
"
"Error audio encoder SRAM access address line address line
20309
x is connected to data line data line y"
"Error audio encoder SRAM access address lines
20310
addressline x and address line y are connected "
"Error audio encoder SRAM access data linesdata line x and
20311
data line y are connected "
20312 "Error audio encoder SRAM access illegal datareceived"
20400 ""
20401 "Error audio encoder access cannot initialiseI2C"
20402 "Error audio encoder access cannot reset DSP throughI2C"
20403 "Error audio encoder accessing ICR register"
20404 "Error audio encoder access stuck-at-zero ofdata line "
20405 "Error audio encoder access stuck-at-one ofdata line "
"Audio encoder access data lines data linex and data line y
20406 are interconnected "
20500 ""
20501 "Error audio encoder SRAM WRR cannot initialise I2C"
"Error audio encoder SRAM WRR cannot reset DSPthrough
20502
I2C"
20503 "Error audio encoder WRR cannot download boot"
20504 "Error audio encoder cannot download test code"
20505 "Error audio encoder SRAM WRR cannot obtain resultof test"
20506 "Error audio encoder WRR SRAM stuck-at-zero databit "
20507 "Error audio encoder WRR SRAM stuck-at-one databit "
"Error audio encoder WRR SRAM data lines data linex and
20508
data line y are connected"
20509 "Error audio encoder WRR SRAM illegal datareceived"
20600 ""
20601 "Error audio encoder interrupt cannot initialiseI2C"
20602 "Error audio encoder interrupt cannot resetDSP through I2C"
20603 "Error audio encoder cannot download test code"
20604 "Error occurred accessing VSM"
20605 "Audio encoder interrupt not received"
20606 "Error occurred while activating the encoder"
20607 "Error audio encoder interrupt cannot initialiseempress"
20608 "Error occurred while getting interrupt reason"
20700 ""
20701 "Error audio encoder I2C cannot reset DSP throughI2C"
20702 "Error audio encoder cannot download boot"
20703 "Error audio encoder cannot download TEST code"
20704 "Error audio encoder I2C bus busy"
20705 "Error audio encoder I2C cannot write slaveaddress"
20706 "Error audio encoder I2C no acknowledge received"
20707 "Error audio encoder I2C cannot send/receivedata"
20708 "Error audio encoder received data throughI2C was invalid"
20800 ""
20801 "I2C access failed."
20802 "SAA7118 VIP can not be initialised."
20803 "Invalid input"
20900 "B1.B2. B3.B4. B5.B6. B7.B8. B9.B10. B11.B12."
20901 "Firmware download of EMPRESS failed"
20902 "I2C bus busy before start"
20903 "EMPRESS access time-out"
20904 "No acknowledge from the EMPRESS"
20905 "No data send to the EMPRESS"
20906 "No data received from the EMPRESS"
30000 ""
30001 "VSM SDRAM Bank1 Memory databus test goes wrong."
30002 "VSM SDRAM Bank1 Memory addressbus test goeswrong."
"VSM SDRAM Bank1 Physical memory device test
30003
goeswrong."
30004 " VSM SDRAM Bank2 Memory databus test goes wrong."
30005 " VSM SDRAM Bank2 Memory addressbus test goeswrong."
" VSM SDRAM Bank2 Physical memory device testgoes
30006
wrong."
"VSM SDRAM Bank1 VSM interrupt register A has a-stuck
30007
at- error for value:"
"VSM SDRAM Bank2 VSM interrupt register A has a-stuck
30008
at- error for value:"
30100 ""
30101 "VSM SDRAM Bank1 Memory databus test goes wrong."
30102 "VSM SDRAM Bank1 Memory addressbus test goeswrong."
"VSM SDRAM Bank1 Physical memory device test
30103
goeswrong."
30104 " VSM SDRAM Bank2 Memory databus test goes wrong."
30105 " VSM SDRAM Bank2 Memory addressbus test goeswrong."
" VSM SDRAM Bank2 Physical memory device testgoes
30106
wrong."
30200 ""
30201 "VSM SDRAM Bank1 Memory databus test goes wrong."
30202 "VSM SDRAM Bank1 Memory addressbus test goeswrong."
"VSM SDRAM Bank1 Physical memory device test
30203
goeswrong."
30204 " VSM SDRAM Bank2 Memory databus test goes wrong."
30205 " VSM SDRAM Bank2 Memory addressbus test goeswrong."
" VSM SDRAM Bank2 Physical memory device testgoes
30206
wrong."
30300 ""
30301 "VSM interrupt register A has a -stuck at-error for value:"
30302 "VSM interrupt register B has a -stuck at-error for value:"
30303 "Interrupt A wasn"t raised."
30304 "Interrupt B wasn"t raised."
30305 "Interrupts A and B were raised."
30400 ""
30401 "VSM SDRAM Bank1 Memory databus test goes wrong."
30402 "VSM SDRAM Bank1 Memory addressbus test goeswrong."
"VSM SDRAM Bank1 Physical memory device test
30403
goeswrong."
30404 " VSM SDRAM Bank2 Memory databus test goes wrong."
30405 " VSM SDRAM Bank2 Memory addressbus test goeswrong."
" VSM SDRAM Bank2 Physical memory device testgoes
30406
wrong."
30500 ""
30501 "Communication with the analogue board fails."
30502 "Echo test to analogue board returned wrong string."
40000 ""
40001 "NVRAM Reset; I2C failed"
40100 "NVRAM address = 0xaddress -> Bytevalue = 0xvalue"
40101 "NVRAM Read; I2C failed"
40102 "NVRAM Read; Invalid input"
40200 ""
40201 "NVRAM Modify; I2C failed"
40202 "NVRAM Modify; Invalid input"
40300 "DV Unique ID = id"
40301 "NVRAM Read DV Unique ID; I2C failed"
40400 "\r\n Error log:\r\n errorString \r\n Ö "
40401 "NVRAM error log; I2C failed"
40402 "NVRAM error log is invalid"
40403 "Front panel failed"
40700 ""
40701 "NVRAM error log reset; I2C failed"
40900 "Region code Change counter is reset"
40901 "NVRAM region code reset; I2C failed"
41000 ""
41001 "NVRAM Store DV Unique ID; I2C failed"
41002 "NVRAM Store DV Unique ID; Invalid input"
50000 ""
50007 "Execution of the command on the analogue board failed."
"The frontpanel could not be accessed by theanalogue
50008
board."
50009 "The echo from the frontpanel processor wasnot correct."
50100 " Front panel version: FPversion "
50102 "Execution of the command on the analogue board failed."
"The frontpanel could not be accessed by theanalogue
50103
board."
50200 ""
50204 "Execution of the command on the analogue board failed."
"The frontpanel could not be accessed by theanalogue
50205
board."
50206 "The frontpanel did not show a starburst."
50207 "The user skipped the FP-which pattern test."
50208 "The user returned an unknown confirmation:confirmation "
50209 "The frontpanel did not show horizontal segments."
50210 "The frontpanel did not show vertical segments."
50300 ""
50304 "Execution of the command on the analogue board failed."
50305
"The frontpanel could not be accessed by theanalogue
board."
50306 "The frontpanel did not light all labels."
50307 "The user skipped the rest of the FP-labeltest."
50308 "The user returned an unknown confirmation: confirmation"
50400 ""
50404 "Execution of the command on the analogue board failed."
"The frontpanel could not be accessed by theanalogue
50405
board."
50406 "The LED"s could not be turned on."
50407 "The user skipped the rest of the FP-LED test."
50408 "The user returned an unknown confirmation: confirmation"
50500 ""
50502 "Front panel Keyboard; test failed"
50503 "Front panel Keyboard; test aborted"
50504 "Front panel Keyboard; not all keys were pressed"
50505 "Front panel keyboard I2C connection failed"
50506 "Unable to get slashversion"
50600 ""
50602 "Front panel Remote control; test failed"
50603 "Front panel Remote control; test aborted"
50604 "Front panel remote control; can not accessFP"
50605 "Front panel remote control; no user inputreceived"
50700 ""
50701 "Execution of the command on the analogue board failed."
"The frontpanel could not be accessed by theanalogue
50702
board."
50703 "The frontpanel did not show a starburst."
50704 "The user skipped the FP-starburst test."
50705 "The user returned an unknown confirmation:confirmation "
50800 ""
50801 "Execution of the command on the analogue board failed."
"The frontpanel could not be accessed by theanalogue
50802
board."
50803 "The frontpanel did not show vertical segments."
50804 "The user skipped the FP-vertical segmentstest."
50805 "The user returned an unknown confirmation:confirmation "
50900 ""
50901 "Execution of the command on the analogue board failed."
"The frontpanel could not be accessed by theanalogue
50902
board."
50903 "The frontpanel did not show horizontal segments."
50904 "The user skipped the FP-horizontal segments test."
50905 "The user returned an unknown confirmation:confirmation "
51400 ""
51401 "Execution of the command on the analogue board failed."
"The frontpanel could not be accessed by theanalogue
51402
board."
51403 "The beeper did not sound."
51404 "The user skipped the FP-Beep test."
51405 "The user returned an unknown confirmation:confirmation"
51500 ""
51501 "Execution of the command on the analogue board failed."
"The frontpanel could not be accessed by theanalogue
51502
board."
51503 "The discbar did not display properly."
51504 "The user skipped the discbar test."
51505 "The user returned an unknown confirmation: confirmation"
51600 ""
51601 "Execution of the command on the analogue board failed."
"The frontpanel could not be accessed by theanalogue
51602
board."
51603 "The discbar dots did not display properly."
51604 "The user skipped the discbar dots test."
51605 "The user returned an unknown confirmation: confirmation"
51700 ""
51701 "Execution of the command on the analogue board failed."
"The frontpanel could not be accessed by theanalogue
51702
board."
51703 "The VU grid did not display properly."
51704 "The user skipped the VU gridtest."
51705 "The user returned an unknown confirmation: confirmation"
51800 ""
51801 "Execution of the command on the analogue board failed."
"The frontpanel could not be accessed by theanalogue
51802
board."
51803 "The frontpanel could not be dimmed."
51804 "The user skipped the FP-Dim test."
51805 "The user returned an unknown confirmation: confirmation"
51900 ""
51901 "Execution of the command on the analogue board failed."
"The frontpanel could not be accessed by theanalogue
51902
board."
51903 "The frontpanel did not show segments blinking."
51904 "The user skipped the FP-blinking test."
51905 "The user returned an unknown confirmation: confirmation"
52000 ""
52001 "Execution of the command on the analogue board failed."
"The frontpanel could not be accessed by theanalogue
52002
board."
52003 "The frontpanel did not show all segments lit."
52004 "The user skipped the FP-light all segmentstest."
52005 "The user returned an unknown confirmation: confirmation"
52200 ""
52201 "Communication with Analogue Board fails."
52202 "Frontpanel can not be accessed by the Analogue Board."
52300 ""
52301 "Communication with Analogue Board fails."
52302 "Frontpanel can not be accessed by the Analogue Board."
60000 ""
60100 ""
60101 "Basic Engine returned error number 0xerrornumber"
60102 "Parity error from Basic Engine to Serial"
60103 "Communication time-out error"
60104 "Unexpected response from Basic Engine"
60105 "Echo loop could not be closed"
60106 "Wrong echo pattern received"
60200 "Version: nr1.nr2.nr3"
60201 "Basic Engine returned error number 0xerrornumber"
60202 "Parity error from Basic Engine to Serial"
60203 "Communication time-out error"
60204 "Unexpected response from Basic Engine"
60205 "Front Panel failed."
60300 ""
60301 "Basic-Engine time-out error"
60400 ""
60401 "Basic Engine returned error number 0xerrornumber"
60402 "Parity error from Basic Engine to Serial"
60403 "Communication time-out error"
60404 "Unexpected response from Basic Engine"
60405 "Focus loop could not be closed"
60500 ""
60501 "Basic Engine returned error number 0xerrornumber"
60502 "Parity error from Basic Engine to Serial"
60503 "Communication time-out error"
60504 "Unexpected response from Basic Engine"
60600 ""
60601 "Basic Engine returned error number 0xerrornumber"
60602 "Parity error from Basic Engine to Serial"
60603 "Communication time-out error"
60604 "Unexpected response from Basic Engine"
60700 ""
60701 "Basic Engine returned error number 0xerrornumber"
60702 "Parity error from Basic Engine to Serial"
60703 "Communication time-out error"
60704 "Unexpected response from Basic Engine"
60800 ""
60801 "Basic Engine returned error number 0xerrornumber"
60802 "Parity error from Basic Engine to Serial"
60803 "Communication time-out error"
60804 "Unexpected response from Basic Engine"
60805 "Radial loop could not be closed"
60900 ""
60901 "Basic Engine returned error number 0xerrornumber"
60902 "Parity error from Basic Engine to Serial"
60903 "Communication time-out error"
60904 "Unexpected response from Basic Engine"
61500 ""
61501 "Basic Engine returned error number 0xerrornumber"
61502 "Parity error from Basic Engine to Serial"
61503 "Communication time-out error"
61504 "Unexpected response from Basic Engine"
61600 ""
61601 "Basic Engine returned error number 0xerrornumber"
61602 "Parity error from Basic Engine to Serial"
61603 "Communication time-out error"
61604 "Unexpected response from Basic Engine"
61700 ""
61701 "BE tray-in command failed"
61702 "BE read-TOC command failed"
61703 "BE VSM interrupt initialisation failed"
61704 "BE set irq command failed"
61705 "BE no disc or wrong disc inserted"
61706 "BE rec-pause command failed"
61707 "BE VSM BE out DMA initialisation failed"
61708 "BE VSM BE out initialisation failed"
61709 "BE VSM BE out DMA start failed"
61710 "BE VSM BE out start failed"
61711 "BE rec command failed"
61712 "BE VSM out underrun error occurred"
61713 "BE record complete interrupt not raised"
61714 "BE get irq command failed"
61715 "BE no interrupt was raised by BE"
61716 "BE VSM DMA out not finished"
61717 "BE stop command after writing failed"
61718 "BE VSM Sector processor initialisation failed"
61719 "BE VSM sector processor DMA initialisation failed"
61720 "BE VSM sector processor DMA start failed"
61721 "BE VSM sector processor start failed"
61722 "BE seek command failed"
61723 "BE VSM sector processor error occurred"
61724 "BE read timeout occurred"
61725 "BE stop command after reading failed"
61726 "BE difference found in data at disc sector 0xdiscsector"
"This nucleus cannot be executed because the Self-
61727
Testfailed"
61800 ""
61801 "BE i2c initialisation failed"
"This nucleus cannot be executed because the Self-
61802
Testfailed"
61900 ""
61901 "The SelfTest failed with result: 0xnr1 0xnr20xnr3"
61902 "Basic Engine returned error number 0xerrornumber"
61903 "Parity error from Basic Engine to Serial"
61904 "Communication time-out error"
61905 "Unexpected response from Basic Engine"
62000 ""
Loop tests
The following loops can be distinguished:
{ Loops performedon the digital board only
{ User Dealer loops performed on the digital andanalogue board
{ System loops performed via an external connection: outputsare looped back to the
inputs.
Figure:
A PCM audio sine of 12kHz is generated in theHost Decoder for a while and sent to the
analogue board. The signalcoming from the analogue board is encoded again and sent
to the memoryof the host decoder for comparison. This nucleus tests the componentson
the audio signal path:
{ Host decoder
Figure:
A colourbar generated in the host decoder islooped through the VIP, Empire, and VSM
and checked again in thehost decoder. The following components are tested on the
video signalpath:
{ VIP
{ Empire
{ VSM
{ Host decoder
Figure:
{ The VSM
This is done by using the internal test signal source(digital board only)
Remark: thistest is only successful if nucleus 121 is carried out first.
Figure:
{ The VSM
On the analogue board the video signal will be routedto the SCART (EUROPE) or
CINCH (NAFTA). There it will be looped backexternally by means of the proper cable
Figure:
{ The VSM
The video CVBS signal is routed to the output of the analogue boardwhere it will be
looped back by means of an external cable
Remark: thistest is only successful if nucleus 121 is carried out first.
Figure:
{ The VSM
On the analogue board, the video signal is internallyrouted back to the digital board.
Figure:
{ The VSM
{ The VSM
On the analogue board, audio is passed to the SCART connector,where a SCART cable
needs to be used to loop back the audio signalto the digital board
Figure:
{ The VSM
On the analogue board the audio is passed to the CINCH connector,where a CINCH
cable needs to be used to loop back the audio signalto the digital board
Figure:
Figure:
Figure:
Power Part Check
PATH
DESCRIPTION
ID
Input signal is VIDEO(CVBS) from digital board andwill be re-
00
routed back to the digital board.
Input signal is from FRONT VIDEO(CVBS) IN and willbe
01
routed to the digital board.
Input signal is from REAR VIDEO(CVBS) IN and willbe routed
02
to the digital board.
Input signal is from FRONT S-VIDEO(Y/C)and will be routed
03
to the digital board.
Input signal is from REAR S-VIDEO(Y/C)and will be routed to
04
the digital board.
Input signal is CVBS from SCART1 and will be routedto the
05
digital board.
Input signal is CVBS from SCART2 and will be routedto the
06
digital board.
07 No routing.
Input signal is VIDEO(CVBS) from ANTENNA IN andwill be
08
routed to SCART1.
Input signal is VIDEO(CVBS) from SCART1 and willbe routed
09
to SCART2.
Input signal is VIDEO(CVBS) from SCART2 and willbe routed
10
to SCART1.
11 No routing.
The paths that are available for video routing and their description(Nafta region)
PATH
DESCRIPTION
ID
Input signal is VIDEO(CVBS) from digital board andwill be re-
00
routed back to the digital board.
Input signal is from FRONT VIDEO(CVBS) IN and willbe
01
routed to the digital board.
Input signal is from REAR VIDEO(CVBS) IN and willbe routed
02
to the digital board.
Input signal is from FRONT S-VIDEO(Y/C)IN and the signal
03
received will be routed to the digital board.
Input signal is from REAR S-VIDEO(Y/C)IN and will be routed
04
to the digital board.
Input signal is from YUV IN and will be routedto the digital
05
board.
06 No routing.
07 No routing.
Input signal is VIDEO(CVBS) from ANTENNA IN andwill be
08
routed to VIDEO(CVBS) OUT and .
09 Input signal is from YUV IN and will be routedto YUV OUT.
10 No routing.
11 No routing.
Input signal is from REAR VIDEO(CVBS) IN and willbe routed
12
to REAR VIDEO(CVBS) OUT.
Input signal is from FRONT VIDEO(CVBS) IN and willbe
13
routed to REAR VIDEO(CVBS) OUT.
Input signal is from REAR S-VIDEO(Y/C)IN and will be routed
14
to REAR S-VIDEO(Y/C) OUT.
Input signal is from FRONT S-VIDEO(Y/C)IN and will be
15
routed to REAR S-VIDEO(Y/C) OUT.
16 No routing.
Signal path is routed from digital board RGBto REAR VIDEO
(YUV) OUT and from REAR VIDEO(YUV) IN to digital
17
boardYUV and from digital board CVBS to digital board
CVBS.
Signal path is routed from digital board CVBSto REAR VIDEO
18 (CVBS) OUT and from REAR VIDEO(CVBS) IN to
digitalboard CVBS.
Signal path is routed from digital board YCto REAR S-VIDEO
19 (YC) OUT and from REAR S-VIDEO(YC) IN to digitalboard
YC.
Example
DD:> 712 01
71200: Video routing on the Analogue Board OK.
Test OK @
Route Audio
PATH
DESCRIPTION
ID
Input signal is VIDEO(CVBS) from digital board andwill be
00
re-routed back to the digital board.
Input signal is from FRONT AUDIO IN and willbe routed to
01
the digital board.
Input signal is from REAR AUDIO IN and willbe routed to the
02
digital board.
Input signal is AUDIO from SCART1 and willbe routed to the
03
digital board.
Input signal is AUDIO from SCART2 and willbe routed to the
04
digital board.
05 No routing.
06 No routing.
07 No routing.
Input signal is VIDEO(CVBS) and AUDIO fromANTENNA IN
08
and will be routed to SCART1.
Input signal is VIDEO(CVBS) and AUDIO from SCART1and
09
will be routed to SCART2.
Input signal is VIDEO(CVBS) and AUDIO from SCART2and
10
will be routed to SCART1.
Input signal is AUDIO from dvio board and willbe routed to
11
SCART1.
12 No routing.
13 No routing.
14 No routing.
15 No routing.
16 No routing.
Input signal is from REAR AUDIO IN and willbe routed to
17
SCART1.
Input signal is from FRONT AUDIO IN and willbe routed to
18 SCART1.
The paths that are available for audio routing and their description(Nafta region)
PATH
DESCRIPTION
ID
Input signal is VIDEO(CVBS) from digital board andwill be re-
00
routed back to the digital board.
Input signal is from FRONT AUDIO IN and willbe routed to
01
the digital board.
Input signal is from REAR AUDIO IN 2 and willbe routed to
02
the digital board.
Input signal is from FRONT AUDIO IN and willbe routed to
03
the digital board.
04 No routing.
05 No routing.
06 No routing.
07 No routing.
Input signal is VIDEO(CVBS) and AUDIO fromANTENNA IN
08 and will be routed to VIDEO(CVBS) OUT and REAR
CINCHOUT 2.
09 No routing.
Input signal is from REAR AUDIO CINCH IN 2and will be
10
routed to REAR AUDIO CINCH OUT 2.
Input signal is from FRONT AUDIO CINCH IN and willbe
11
routed to REAR AUDIO CINCH OUT 2.
12 No routing.
13 No routing.
14 No routing.
15 No routing.
Input signal is AUDIO from dvio board and willbe routed to
16
AUDIO CINCH OUT 2.
17 No routing.
18 No routing.
19 No routing.
Input signal is from digital board and willbe routed to the
20 REAR AUDIO OUT 1 and input signal is from REARAUDIO
IN 2 and will be routed to the digital board.
Input signal is from digital board and willbe routed to the
21 REAR AUDIO OUT 1 and input signal is from REARAUDIO
IN 1 and will be routed to the digital board.
Input signal is from digital board and willbe routed to the
22 REAR AUDIO OUT 2 and input signal is from REARAUDIO
IN 1 and will be routed to the digital board.
EXAMPLE
DD:> 713 00
71300: Audio routing on the Analogue Board OK.
Test OK @
z Levels: Most measurements are digital measurements. The signal levels specification in
this document are defined as follows:
low < 0.3V
The module operates in power 'off' and power 'on' only. There is no standby mode at module
level. In power 'off', the module does not respond to any communication or signal.
Before starting the measurement, connect the power supply to the mono board via connector
1000, and the PC interface cable to the Service Interface connector of the 'test recorder'.
Oscillator Check
On the mono board, there are two external oscillators (OSCOUT and CROUT), which are the
reference for all clock signals derived in several ICs.
To check whether the program (in the MACE microprocessor) is running after power 'on', you
can monitor the PSEN (OEn of Flash ROM) on I223 (see test point overview in chapter 6).
You can measure the Servo clocks at I326 (RAdial), I334 (FOcus), and I343 (SLedge).
Diagnostic Software
Due to the complexity of a DVD recorder, the time to find a defect in the recorder can become
long. To reduce this time, the recorder has been equipped with Diagnostic and Service
software (DS). The DS offers functionality to diagnose the DVDR hardware and tests the
following:
This part describes all interfaces from the outside world to the diagnostic software, how to use
these interfaces, and how to access them.
z Diagnostic Nucleus. Part of the Diagnostic Software. Each nucleus contains an atomic
and software independent diagnostic test, testing a functional part of the DVD player
hardware on component level.
z Script. Part of the Diagnostic Software. Each script contains a sequence of Diagnostic
Nuclei to be executed.
z Service PC. PC used by a service or repair person to communicate with the Diagnostic
Software in the DVD player.
The End user/Dealer script interface gives a diagnosis on a stand-alone DVD recorder; no
other equipment is needed.
During this mode, a number of hardware tests (nuclei) are automatically executed to check if
the recorder is faulty. The diagnosis is simply a 'fail' or 'pass' message. If the message 'FAIL'
appears on the display, there is apparently a failure in the recorder. If the message 'PASS'
appears, the nuclei in this mode have been executed successfully. There can be still a failure
in the recorder because the nuclei in this mode do not cover the complete functionality of the
recorder.
Note: As this mode is meant for a complete DVD Recorder, and does not add much for testing
the Basic Engine, reference is made to the appropriate DVD Recorder Service Manual for a
detailed description:
The Player script will give the opportunity to perform a test that will determine which of the
DVD recorder's modules are faulty, to read the error log and to perform an endurance loop
test. To successfully perform the tests, connect the DVD recorder to a TV set. To be able to
check results of certain nuclei, the player script expects some interaction of the user (i.e. to
approve a test picture or a test sound). Some nuclei (e.g. nuclei that test functionality of the
DVDR module) require that a DVD+RW disc is inserted. Only tests within the scope of the
diagnostic software will be executed hence only faults within this scope can be detected.
Each nucleus contains an atomic and independent diagnostic test, testing a functional part of
the DVD player hardware on component level. Each Nucleus returns a result message to its
caller. Some tests (e.g. generating a colour bar) can only return an "OK" result. Internal
communication will be done via a uniform interface between the diagnostic Engine, Scripts,
and the Diagnostic Nuclei.
The Diagnostic Engine can only operate if a certain (minimal) set of hardware is functioning
properly. To test this set of hardware, a set of basic diagnostic nuclei is embedded in the DVD
player. Each basic diagnostic nucleus will only test that part of the hardware which is required
for execution of the diagnostic Engine, e.g. a RAM test will only test that part of RAM that is
used by the diagnostic engine. After the Diagnostic Engine is operational, it is possible to do a
full RAM diagnostic.
All basic diagnostic nuclei start with prefix 'Basic'. In the overview, each Diagnostic Nucleus
consists of a reference number, a reference name, and remarks. Reference number and name
are coupled and one of them is enough for unique identification.
Nuclei Numeration
Each nucleus has a unique number of four digits. This number is the input of the command
mode.
Error handling
Each nucleus returns an error code. This code contains six numerals, which means:
The nucleus group numbers and nucleus numbers are the same as above.
Hardware required
z Service PC.
z One free COM port on the Service PC.
z Special cable to connect DVD recorder to Service PC.
The service PC must have a terminal emulation program (e.g. OS2 Warp Terminal, ProComm,
or HyperTerminal) installed and must have a free COM port (e.g. COM1).
Activate the terminal emulation program and check that the port settings for the free COM port
are:
z 19200 bps,
z 8 data bits,
z No parity,
z 1 stop bit,
z No flow control.
Connect the free COM port via a special cable to the RS232 port of the DVD recorder. This
special cable will also connect the test pin, which is available on the connector, to ground (i.e.
activate test pin). Code number of PC interface cable: 3122 785 90017.
Activation
Connect the recorder to the mains. The following text will appear on the screen of the terminal
(program):
The first line indicates that the Diagnostic software has been activated and contains the
version number. The next lines are the successful result of the SDRAM interconnection test
and the basic SDRAM test. The last line allows the user to choose between the three possible
interface forms.
If pressing 'C' has made a choice for Command Interface, the prompt ("DD>") will appear. The
diagnostic software is now ready to receive commands. The commands that can be given are
the numbers of the nuclei.
Command Overview
We provide an overview of the nuclei and their numbers. This overview is preliminary and
subject to modifications.
Ref.
Function name Description
#
It switches the RS232
port and the S2B port in
pass-through mode. This
600 DS_BE_S2B_Pass means that the player
hangs. The only way to
exit this nucleus is via a
power off of the player
It checks the S2B
interface with the Basic
601 DS_BE_S2B_Engine
Engine by sending an
'echo' command
It returns the version
602 DS_BE_Version number of the Basic
Engine
It resets the Basic
603 DS_BE_Reset
Engine
It puts the laser of the
604 DS_BE_FocusOn basic engine into focus
(focus loop)
It switches the focus loop
605 DS_BE_FocusOff
off
It switches the disk motor
606 DS_BE_DiscMotorOn
(= spindle motor) on
Activation
Connect the recorder to the mains. The following text will appear on the screen of the terminal
(program):
The first line indicates that the Diagnostic software has been activated and contains the
version number. The next lines are the successful result of the SDRAM interconnection test
and the basic SDRAM test. The last line allows the user to choose between the three possible
interface forms.
If pressing 'M' has made a choice for Menu Interface, the Main Menu will appear.
Menu Structure
1. Digital Board
2. Analogue Board
3. Front Panel
4. Basic Engine
1. Reset
2. S2B Pass-through
3. S2B Echo
4. Focus On
5. Focus Off
6. Version
7. Self Test
8. Get Self Test Result
9. Basic Engine Test
10. Laser Test
11. Focus Test
12. Tilt Test
13. Optimise Jitter
14. Statistics Info
15. Log
1. Read Error Log
2. Reset Error LogSpindle Motor
16. Spindle Motor
1. Spindle Motor On
2. Spindle Motor Off
3. Spindle Motor Test
17. Radial
1. Radial On
2. Radial Off
3. Radial Initialisation
4. Radial ATLS Calibration
18. Sledge
1. Sledge test
2. Sledge test slow
19. Tray
1. Tray In
2. Tray Out
5. DVIO
6. Progressive Scan Board
7. Loop Tests
8. Log
9. Scripts
62700 The data byte was successfully read from the EEPROM
62701 The Basic Engine returned an error number
62702 Parity error from Basic Engine to Serial
62703 Communication time-out error
62704 Unexpected response from Basic Engine
62705 The user entered an invalid input
The fatal error log and the cumulative error log were
63400
successfully erased
63401 The Basic Engine returned an error number
63402 Parity error from Basic Engine to Serial
63403 Communication time-out error
63404 Unexpected response from Basic Engine
Basic Engine
Figure: Basic Engine functional testing
Loader
Figure: Loader testing
DVD-M
Figure: DVD-M testing
PWB
Figure: Mono board testin
Introduction
This training is intended for use by the Service Technician. The first portion of this document
contains a basic description of disc based data playback and recording technologies.
Technical Descriptions of the circuitry is followed by a Troubleshooting Section. Self
Diagnostics are included at the end to aid in troubleshooting.
The DVDR985 is the forth in a line of DVD recorders. The DVDR1500 was the first.
Recordings can be made from broadcast transmissions, and from other analog or digital
sources. The DVDRW format allows the user to record and erase a disc many times. The
recorded discs will play on most existing and future DVD players. The DVDR985 has a
connection for DV or Digital camcorders via an I-Link or Firewire connection. This connection
technically is called an IEEE 1394 connection. This machine records on 4.7Gbyte DVD+R and
DVD+RW discs. This machine uses a real-time MPEG2 Variable Bit Rate, VBR, Video
encoder. The DVDR985 plays back DVD Video, Video CD, Audio CD, CD-R, and CD-RW
discs.
Its many features include: Favorite Scene Selection for easy editing, Index Picture Screen for
instant overview of contents, Digital Time Base Corrector, Digital Audio output (DTS, AC-3,
MPEG, PCM), TruSurround for 3D sound, Zoom + Perfect Still. It is Widescreen, 16:9
compatible, and has a Universal Remote Control, 20 disc resume, Disc Lock, and One Touch
Recording.
Virgin Mode
The DVDR985, when first hooked up, needs to get information from the user about what
language and what local broadcast system the unit is going to operate with. Use the remote to
make those selections. The unit will not operate until this process is completed. If you want the
recorder to start up in Virgin mode, unplug the recorder. Plug the recorder in again while
holding the STANDBY-ON button.
DVD Basics
Philips with nine other manufacturers chose a format specification for DVDR and RW on March
16, 2001. This new format uses Real Time recording. Its recording is compatible with DVD-
Video, and DVD ROM. The data blocks use lossless linking. The physical layout matches very
closely that of DVD ROM. See figure below. It also uses Direct Overwrite when a RW disc is
used.
Laser Technology
CDs use a red laser created by a diode and lens system often called a Light Pen. See Figure
below. The narrow beam of light is focused onto the reflective layer of a disc. At the instant that
focus is achieved, the disc is spun. The laser starts on the innermost tracks of the CD and
reads outward. At the beginning of the disc is the Table of Contents. At the bottom of the Light
Pen are Monitoring Diodes. The Monitoring Diodes provide information about focus and
tracking. Data is retrieved from the disc in the form of pulses of light reflecting from the disc.
The pulses are created by Pits in the Reflective Layer of the disc. The Pits reflect less light
than the intact surface of the Reflective Layer, called Lands.
Disc Mechanical Layout
The DVD and CD share much of their technology. We will start with CDs and work our way to
the DVD. The CD is a plastic disc 120mm in diameter, with a thickness of 1.2mm. Refer to the
figure below. It has a silver colored Reflective Layer. The maximum playing time for a music
recording on a Compact Disc, CD, is 74 Min.
The CD is less vulnerable to damage than an analog record. That does not mean it does not
have to be treated with care. Dirt and heavy scratches can interfere with playability.
As shown in the figure below, the CD is subdivided into three parts: the Lead In Track, the
Program Area, and the Lead Out Area. These three sections together are considered the
Information Area. There is a hole in the center for holding the disc. The disc is held between
two equally sized concentric rings. The rings have an inner diameter of 29mm and an outer
diameter of 31mm.
The Data on the disc is recorded on a spiral shaped track with pits and lands. The reflective
side of the disc contains the tracks.
The production of a disc is a high tech process explained in Figure 5. The process starts with
glass that is photo etched. The glass is silver plated and is used as a form for a metal cast.
The metal cast is used to stamp a nickel Mother Stencil. The Mother Stencil is used to stamp
the Son Stencil. Son Stencils are used to stamp the foil of the discs. A protective layer and
label are added.
Read Process
The Servo circuit is responsible for focusing the laser and moving the Light Pen to follow the
spiraling tracks on the rotating disc. The digital High Frequency information, HF, is
demodulated and stored in RAM. When the RAM is half full, the data is fed out to the Digital to
Analog Converters. The speed of the rotating disc is servo controlled to keep the RAM half full.
The analog signals are amplified and sent to the output connectors.
From an external point of view, a DVD is the same as the CD. Recordable media creates the
need for three physical layouts. There are three possible states of a disc: a blank disc, a
partially recorded disc, and a full or finalized disc. The difference is in the way the Information
Area is divided. The Information Area of a blank disc extends from 22.35 mm centered on the
disc to 59 mm centered on the disc. Refer to the Figure.
A partially recorded disc’s Information Area has four sections: a PCA/RMA area, a Lead In
Area, a Recorded Program Area, and a Recordable Program Area. The PCA Area is the
Power Calibration Area, PCA. The RMA Area is the Recording Management Area.
A fully recorded or finalized disc’s Information Area has three sections: A lead in Area, the
Program Area, and the Lead Out Area.
The disc’s recordable layer contains major differences from that of a stamped disc. The blank
disc has a Pre-groove stamped into the recordable layer of the disc. This is polycarbonant for
DVD+Rs and organic dye material for DVD+RWs. This spiral Pre-groove is for the Servo circuit
to provide a mechanical reference during recording. The dye based RW recordable layer
provides a reflectivity of 40% light return and 70% light return. 40 percent reflectivity represents
Pits and the 70% represent the Lands.
Record Process
The record process shares most of its mechanical operation with that of the Play process. The
main difference is how the Servo is locked to the disc. The Servo follows the Pre-groove for
Radial Tracking and disc speed. The speed of the disc is locked to a wobble signal that is part
of the spiral grove stamped into the disc.
The intensity of the laser beam is modulated from Playback intensity to write intensity. As the
disc reads the Pre-groove, the laser arrives at a position where a Pit is to be formed. The laser
power increases from 4mW to 11mW. This raises the temperature of the disc to 250 degrees
Celsius. The recordable layer melts, reducing its volume. The polycarbonate flows into the
space vacated by the dye. The modulation from read laser power to write laser power forms a
pit and land pattern effectively the same as a prerecorded disc.
Re-recordable Technology
Disc Mechanical Layout
Disc usage mechanically is identical to the recordable media. The only difference is the
chemical make up of the recordable layer. The recordable layer is made up of an alloy of
silver, indium, antimony and tellurium.
Re-Recording Process
The Re-Record process shares much of its operation with that of a CDR. The blank disc’s
Information Area is in a polycrystalline state. During recording, the laser power is modulated
from 8mW to 14mW. 8mW is the Playback laser power and 14mW is the Record laser power.
The polycrystalline state of the recordable surface changes, or melts at 500-700 degrees C
into an amorphous state. The melted, amorphous areas reflect light less than the crystalline
areas, creating a pattern similar to the stamped CD. A major difference of CDRWs from CDRs
is the ability to erase.
To Erase a CDRW disc, the recordable layer must be returned to its polycrystalline state. This
is done by heating up the temperature of the recorded surface to 200 degrees C. This is less
than the melting point. This is done at X2 recording speed. The slower speed allows time for
the alloy to return to its proper state. This takes approximately 37 min. Some software erases
the just the TOC on the disc and allows the disc to be rewritten. This method is not as reliable.
Overwriting combines the processes of erasing and writing. When the disc and Light Pen are
in position to start writing the new data, the laser power starts modulating in the same manner
as it does for normal recording with one difference. During the time there is to be a land, the
laser power goes to the erase level rather than the Playback level.
DVDs
All of the previously discussed technologies apply to the DVD. Like CDs, DVDs are also
stamped into Play only discs. In this discussion, we will point out the differences between
DVDs and CDs. If you are new to disc based technology, you will want to start with the
information preceding this discussion. DVD Disc Mechanical Differences
Most DVDs are single sided, however, the DVD specification allows for two readable layers,
and the disc can be double sided. We will start our discussion with single sided, single layered
discs. A Digital Versatile Disc, DVD, looks very similar to a CD. The Clamping Area is larger,
starting at 11 mm centered to 16.5 mm centered. The Lead In Area is smaller, measuring 22.7
mm centered to 24 mm centered. The Information Area is limited to 58mm centered.
Two of the big differences between DVDs and CDs are the Pit and Land sizes, and the track
widths.
The Manufacturing process of a DVD is comparable to that of a CD. The main difference is the
thickness. The DVD can be a double sided product. Each side is .6mm. The two sides are
glued back to back, producing 1.2mm total thickness.
Wobble
A Pre-groove is stamped on writable discs. All recordable DVD media types feature a
microscopic wobble groove embedded in the plastic substrate. This wobble provides the
recorder with the timing information needed to place the data accurately on the disc. During
recording, the drive's laser follows this groove, to ensure consistent spacing of data in a spiral
track. The walls of the groove are modulated in a consistent sinusoidal pattern, so that a drive
can read and compare it to an oscillator for precise rotation of the disc. This modulated pattern
is called a wobble groove, because the walls of the groove appear to wobble from side to side.
This signal is only used during recording, and therefore has no effect on the Playback process.
Among the DVD family of formats, only recordable media use wobble grooves.
Two information layers are separated by a thin transparent layer. The first layer is partially
transparent. This allows the second layer to be read through the first layer. Both layers are
read by controlling the focus. There are two methods for reading the data of a Dual Layer disc,
PTP and OTP.
PTP is Parallel Track Path. That means the Lead In and Out Areas of the two layers
correspond to each other. Each Lead In Area is on the inner portion of the disc, and the Lead
Out Area is on the outer portion of the disc. This is useful to link data between the layers.
This allows instant access to the additional data or scene. OTP is Opposite Track Path. This
method links the end of one layer to the beginning of the other. The Lead In Area is still on the
inner portion of the disc. There is a Middle Track Area on both of the layers located on the
outer portion of the layers. The Middle Track Area links the data on the two layers together.
The Lead Out Area is on the second layer on the inner portion of the disc.
Capacity
Because a stamped DVD can be Dual Layered and Double Sided, there are four different
capacities. Refer to the chart. These capacities strictly pertain to raw data. The time available
for Video and Audio has many extra factors that determine the length of time on each side or
layer. The picture complexity and the amount of movement in the picture affect compression
and time on a disc. The number of languages affect the time on a disc. The type and quality of
the Audio has an affect on the time also. It can be mono, stereo, or AC-3. Therefore, the media
itself determines the capacity in time on the disc.
Overall Block
Key Components
The unit is made up of: the Power Supply, the Front Panel, the Basic Engine, the Digital Board,
the Analog Board, and the Digital Input/Output Board. Refer to the block diagram.
The Power Supply is a SMPS using Hot Ground on the primary side of the transformer. There
is no MAINS power switch. It is operating when AC is applied. It supplies power to: the Analog
Board, the Digital Board, and the Basic Engine.
This module contains a microcomputer that doubles as a fluorescent display driver. It receives
the IR inputs and the keyboard inputs. It communicates the user input from the Keyboard and
IR Receiver via the I2C Bus to the Microcomputer on the Analog Board.
The Servo controls the Mechanism. It handles the HF signal to and from the OPU. It uses a
Microcomputer to control all aspects of the Servo operation. This includes: tray operation,
spindle speed, focus, HF preprocessing, and radial positioning of the Light Pen.
Digital PCB
This module performs many functions. It interfaces between the Basic Engine and the rest of
the unit.
During Record, it encodes analog video into a recordable digital data stream. The Analog to
Digital Converter is in a Video Input Processor, VIP, that supplies the MPEG2 Encoder. The
Empress is the MPEG2 encoder. It supplies the data to the VSM, Versatile Stream Manager.
The VSM is the gateway to the BE.
During Playback, the MPEG2 Decoder receives its input directly from the BE. It decodes the
data stream into analog Video. The analog Video is sent to the Analog Board and Digital Video
is provided to the Line Doubler. The Line Doubler receives 11 bit digital YUV. The Line Doubler
produces progressive scan digital Y, Cr, Cb that goes to the Digital to Analog Encoder. D_R,
D_G, and D_B are sent to the Analog Board. The MPEG2 Decoder sends Digital Audio to the
Analog Board to be processed.
Analog PCB
This module contains all the A/V inputs and outputs including a Tuner. There is no RF
modulator. The RF output to the TV is merely a Loop-thru for the Antenna or Cable signals.
Source selection and output type are controlled by a microcomputer. The microcomputer
controls many functions throughout the unit including: user input, input/output selection, the
Tuner, the DAC, and ADC functions of the Audio. It also controls the Fans.
DVIO PCB
The Digital Input Module provides IEEE 1394 translation to the DVD recorder. It separates the
Digital Video and Audio. The Digital Audio is decoded and sent as Analog Audio to the Analog
Board. Digital Video (DV) is supplied to the Video Input Processor on the Digital Board.
Power Supply
This unit uses a stand alone Switch Mode Power Supply, SMPS. Refer to the circuit drawing. A
MOSFET transistor turns On and Off in an oscillator fashion, driving a transformer. The
primary half of the supply uses a Hot Ground. The primary side of the circuit provides drive and
coarse control of the power supply. The secondary side of the circuit rectifies and filters the
output of the transformer to produce many output voltages. It uses a cold ground, signal
ground system. Two of the output voltages are monitored for precise regulation. The 12Vdc is
supplied to the anode of the Optic Coupler’s diode, and the 5Vdc Standby is fed to the Shunt
Regulator. The regulation path includes an Optic Coupler to accommodate the different
grounding systems.
Circuit Description
AC Input Circuit
The input circuit consists of a lightning protection circuit and an EMI filter. The lightning
protection circuit consists of R3120, spark gaps 1124 and 1125. L5110, L5115, C2120 and
L5121 form the EMI filter. It prevents noise coming in or out through the mains. The AC input is
rectified by diodes 6151, 6152, 6153, 6154, and filtered by C2126. The voltage on C2126 is
approximately 155V. It can vary from 150V to 160V, depending on the AC input voltage.
Start Circuit
This circuit consists of R3125, 3126, R3139, R3141, C2140, and R3132. When the power plug
is connected to AC, the MOSFET 7125 will start conducting as soon as the gate voltage
reaches the threshold value. A current starts to flow in the primary winding of 5125, Pins 2 and
4. The MOSFET will be fed forward via the winding connected to Pins 7 and 8 by R3150 and
C2146. While the MOSFET is conducting, energy is building up in the transformer. The current
flow through the MOSFET is sensed by R3133, 3134, and 3135. When the current level rises
high enough to provide a voltage drop on these components and large enough to turn On
7140, 7125 is turned Off by 7140. Diodes 6130, 6131 and 6132 protect the control circuit in
case of failure of the MOSFET by providing an upperlimit to the voltage that can remain on the
source of the MOSFET.
Coarse Regulation
The positive portion of the signal on Pins 7 and 8 will be rectified via R3150 and D6140,
charging C2140 via R3140. In time, the voltage on C2140 will reach 15 to 20Vdc. This value
depends on the value of the Mains voltage and the load. The negative portion of the signal on
Pins 7 and 8 will be rectified via R3150 and D6142. This will charge C2151 to approximately -
15Vdc. This is used as a regulation supply.
The control circuit consists of T7140, D6141, C2144, C2145, C2147, R3147, and 3148. This
circuit controls the conduction time and the switching frequency of the MOSFET. It switches
Off the MOSFET as soon as the voltage on the source of T7125 reaches a certain value. This
value depends on the error voltage at the emitter of T7140, which can be a negative (+/- 0.6V).
The voltage fed back by the regulation circuit defines this error voltage.
Precise Regulation
The regulation circuit consists of an Optic-Coupler, 7200, 7251, and a voltage divider network.
The Optic-Coupler isolates the Hot Ground referenced voltage on the emitter of 7140 from the
Cold Ground referenced voltage on 7251. 7251, a Shunt Regulator, has two component
characteristics. It is a very stable and accurate reference diode and a high gain amplifier.
7251 will conduct from cathode to anode when the reference is higher than the internal
reference voltage of about 2.5Vdc. If the reference voltage is lower, the cathode current is
almost zero. The cathode current flows through the LED of the Optic-Coupler, controlling the
current through the transistor portion of the Optic- Coupler. The collector current of 7200 will
adjust the feedback level of the error voltage at the emitter of T7140.
This circuit consists of R3145, C2143, a thyristor circuit formed by T7141 and T7143, R3143
and R3142. When the output is shortened, the current through the FET will produce a large
voltage drop across the source resistors of the FET. That voltage turns On 7140 and 7143.
The thyristor circuit will start to conduct and switch Off the supply voltage to C2140. This
switches Off the drain current of the MOSFET, 7125. The start circuit will try to start up the
power supply again. If the short still exists, the complete start and stop sequence will repeat.
The power supply is in a hiccup mode and is ticking.
This circuit consists of R3149, D6144, 6143, R3144, C2142 and T7142. If the regulation circuit
does not function due to an error in the control loop, the regulated output voltage will increase.
This overvoltage is sensed on the hot ground side of the transformer at Pins 7 and 8. When an
overvoltage is detected, the circuit will activate the thyristor circuit T7141 and 7142. The power
supply will be shutdown as long as the error in the control loop is present.
There are six Rectifier/Smoothing circuits on the secondary side. Each supply voltage depends
on the number of windings in the transformer. From these circuits, several voltages are derived
and fed to three connectors. The following voltages are present at the output: 33Vdc, 12Vdc,
3.9Vdc, and 5Vdc Stby, -5Vdc Stby, and -33Vdc Vgnstby. The +12V is switched Off by the
STBY_Ctrl signal, ION. The -33Vdc is dedicated to the Front Panel Fluorescent Tube as a grid
supply. The FLYB signal is used as a Power Fail and measurement signal.
Front Panel
The main elements of the Front Panel are the microcomputer, 7156, the Display Tube, and the
keyboard. Refer to the circuit drawing. 7156 is an 8 bit microcomputer fitted with 96kB ROM
and 3kB RAM and is responsible for the following functions:
The Fluorescent Tube operates using a grid and segment scanning matrix. AC is supplied by a
switching regulator consisting of 7151, 7152, 7153, and 5153. With AC supplied, the
microcomputer scans the elements in the tube to determine what segments light up. The
system clock is generated with the 12MHz crystal, 1153.
Keyboard Matrix
There are 11 different keys on the display board. A resistor network is used to generate a
specific voltage value, depending on the key pressed, via the resistors 3186-90, 3145, 3197,
3177-3178, 3197, and 3180. This RTL data (voltage Level) is sent to 7156 on Pins 17, 18, 19,
and 20. Pressing keys simultaneously may lead to undesired functions!
IR Receiver
The IR receiver, 7140, contains a bandpass amplifier as well as a photo-diode. The photo-
diode receives approximately 940nm infrared pulses. The pulses are amplified and
demodulated. On the output of the IR receiver, 7140, is a pulse sequence at TTL levels. The
IR signal appears on Pin 5 of 1917 on the Front Panel. The IR signal goes to Pins 12 and 13 of
7160. 7160 establishes a minimum threshold for the IR signal to trigger its gate. This filters out
erroneous IR from reaching the Microcomputer.
The RC connection on the rear of the unit comes through the Analog PCB to 1916 Pin 10. This
signal also goes to 7160, Pin 5. This pulse sequence is an input to the controller for further
signal evaluation via IRR input on 7156, pin 2.
Bi-Color LED (Standby and ON)
The STBY-LED is a red/green bi-color-LED controlled by the STBYLED signal on Pin 10 of
7156. The LED drive circuit receives the 5Vdc Standby supply. The control voltage coming
from the Microcomputer is inverted by 7164. When the LED control voltage on the
microcomputer is High, a Low goes to the LED drive circuit, turning the LED green.
The Basic Engine consists of a DVD-Mechanism with dual laser Optical Pickup Unit (OPU), a
tray loader, a fan unit, and a PCB containing all electronics to control the module. Refer to the
block diagram.The DVDM contains the Focus and Radial Motor, the Sled, and the Tilt Motors.
The electronics of the module are responsible for all the servo tasks. It reads and writes data
to and from the disc.
The PCB is multilayer, using surface mounted circuitry with a very high component density.
Detailed diagnostics and fault finding are available via ComPair.
Some specifications:
z Record DVD+R and R/W
z Lossless linking
z Recording speed: 1.2 x
z Playback DVD, DVD+R(W), DVD (SL/DL), DVD-R, DVD-RW (V1.1)
z Playback speed: 1.2 x
z Playback CD, CD-DA, CD-R, CD-RW, CD-ROM, VCD/SVCD
z Playback speed: 3 x
z It controls all other functions like tray control, start/stop, disc rotation, tracking, jumping,
and communication to the Digital Board.
The Servo circuit provides the interface between the Mechanism and The Digital Signal
Processing Board. It is mostly on one board attached to the bottom of the mechanism. It is
made up of four main circuits:
Initialization process
During power-up, a reset of the BE is preformed. This is parallel to the reset process of the
Digital Board. After the MACE3 resets, a System reset occurs to reset the other
microcomputers in the BE. A self-test will automatically start. Each of the microcomputers must
respond to the I2C bus. The SDRAM and Flash are also tested. If the self test passes the
Servo Unit Ready (SUR) signal line will appear. The SUR line is a data transfer clock between
the VSM and the BE. Part of the self test is the CPR switching voltage coming from the
Versatile Stream Manager. If it is ready to function, it will be Low. After the self test passes, the
BE will wait for the first Serial to Basic Engine, S2B, user command. E.g. "Tray_out".
DVDR Mechanism
The DVDR-M is made up of three components: Optical Pickup Unit, OPU, the Sled, and the
Turntable Motor. The OPU contains two lasers: one for CDs with a wavelength of 780 nm, and
one for DVDs with a wavelength of 650 nm.
The OPU contains: the Optics, the Focus Motor, the Laser Drive IC (LADIC), the Tilt sensor,
the DVD Rewritable OPU Pre-Processor IC (DROPPI), and the EEPROM with the OPU
adjustment data.
DROPPI
The DROPPI (DVD Rewritable OPU Pre-Processor IC) is a multi-purpose analog pre-
processor. It supports many photo detector configurations and output signal modes. It
produces RF and servo feedback signals, Q1-Q6. Its output signals are on the same flex
ribbon cable with the wideband RF (differential signals). The Wobble, focus, and Sled Servo
signals are relatively low bandwidth.
LADIC
The Laser Drive IC, LADIC, controls the data to the lasers, and the supply to them. It performs
three main functions:
z It drives the laser for both Playback and Record functions. Its greatest stress is realized
during Record, producing data signals and write pulses. The recording process is flexible
with respect to the input modulation method (EFM, EFM+, 17 pp, etc.). This is necessary
to support CDR/RW and DVDR/RW. To accomplish this, the LADIC uses two Random
Access Memories (RAM) which can be loaded (non real-time) via the I2C Bus from the
microcontroller.
z It drives the laser with a sequence of programmable write pulses with high timing
accuracy and high peak current levels.
z It controls the exact light power levels coming from the laser and controls the exact
power absorbed by the disc during recording.
The LADIC needs three independent power supplies. These are the analog and digital power
supplies, and V Bias for the laser driver function. The supplies are separate to obtain
maximum output performance where there are large and highly dynamic current flows.
The LADIC is controlled by an I2C bus. The laser is operated at three current levels: Playback,
Record and Erase. During the initialization of a disc to be recorded on, and test recording is
preformed in a special place on the the inner most section of the disc. A series of random data
is recorded with a wide range of current levels. The data is played back. Two feedback signals
are generated and sent to the MACE3 circuit, A1 and A2. A second fine tuning of the Optimal
Laser Current is preformed. The disc is written to again except the current range is chosen by
the MACE3 using the feedback received. This fine tuning of the laser current produces the Calf
feedback signal that is sent to the MACE3 and it is stored in the MACE3’s operating RAM.
z The SPIDRE
z The MACE3
z The Encoder/Decoder
z The AWSOME
The Servo receives: 12Vdc, 5Vdc, 3.3Vdc and -5Vdc from the Power Supply. There are three
2.5V supplies on the Servo Board connected to the 3.3Vdc supply. Refer to the circuit drawing.
The MACE3 is reset by the Digital Board, via the Reset_BE signal. A Reset signal comes from
the MACE 3 for the rest of the servo. The Mace3 is the Host for the local I2C Bus.
SPIDRE
The SPIDRE (Signal Processing IC for DVD REwritable) is a multi-purpose analog pre-
processor IC specifically intended for writing applications.
The SPIDRE receives two Power Supplies: -5Vdc and 5Vdc. Its has three main tasks. Refer to
the circuit drawing. One is to interface the servo signals that go to the MACE3 Servo
Processor. The second is preprocessor for the RF signal coming from the disc during
Playback. The third is to process the RF signal coming from the Encoder during Record.
The SPIDRE is controlled by the AWSOME via a serial bus on Pins 35, 37, and 38. The
AWSOME communicates: gain information, data type, and operation mode, Play or Record.
The Servo signals to be processed include: Playback HF/RF, the focus servo feedback
signals, the radial feedback, the track loss signal, and tilt sensor signal. The HF/RF (EMF)
signal varies greatly between disc formats. The Focus Error and Radial Error signals come
from the mechanism on the Q1-6 signal paths. The Tilt Error has a Photo Tilt Sensor. The
dynamic range of these signals is very large. They are converted to Lower frequency RF data
paths that the MACE3 can accommodate. This is required for playability of the many different
kinds of discs.The error signals are all balanced to reduce noise interference. Thus, they are
named XX positive, and XX negative. The Output signals include: the Focus Error, the Radial
Error, the Tilt error, laser PoWer, and tracking loss signals.
The Record RF EFM data and EFM Clock comes from IC 7402, Encoder circuit, and is
supplied to the SPIDRE on Pins 48-51 of 7101. The SPIDRE processes the RF signals for gain
control of the Error control signals going to the MACE3 during Record. All of these signals are
balanced. Thus there is a negative and a positive signal for all of them.
The LASP, Laser Power feedback signal is processed by the SPIDRE. During Playback, the
EFM coming from the disc is used by the ALFA circuit to generate the AMEAS, ALFA
Measurement, signal that goes back to the LADIC for precise control of the LASER power.
During Record the EFM signal coming from the Encoder is used by the ALFA circuit to create
the AMEAS signal.
The pregrove tracking error signal comes from a Preprocessor in the OPU. The PPN signal is
amplified and sent to the Wobble Processor in the Decoder circuit.
The MACE3 IC is the Mini All Cd Engine third generation. Its vendor number is SAA7830. It is
a combined servo processor and microcomputer. Refer to the circuit drawing.
The servo processor handles the signals for focusing and tracking for disc access. It also
generates the control signals for tray control. In a CD/DVD system, there are several active
control loops. Some of them are needed to adjust the servo error signals. It monitors and
adjusts the offsets, signal amplitudes, and loop gains (AGCs). The control loops determine the
laser spot position on the disc in the radial (Sled), axial (focus), and tangential directions (Tilt).
This access system consists of two parts, namely the Focus Actuator and the Sled, which are,
within a certain range, mechanically and electrically independent.
The analog signals from the SPIDRE are converted into a digital representation using A/D
converters. The digital codes are then applied to logic circuitry to obtain the various control
signals.
OPC (Optimum Power Calibration)
This device has an integrated Optimum Power Calculation circuit for use in DVD/RW, and
DVD+R applications. It reads three analog signals: A1, A2, and CALF. These represent Max,
Min, and Average values of the EFM coming from the disc, respectively. It also takes the
Power (PW) signal from the laser controller and then feeds an analog signal, ALPHA0, out to
control the laser power. The conversion frequency is 88kHz per channel. Basically, the OPC
procedure tries to find out the optimum laser power to be used on a specific disc. It consists of
three phases:
1. WRITE - Random EFM data is written to the test area of the disc at increasing levels of
laser power, controlled by ALPHA0.
2. READ - The data on A1, A2, and CALF is read back from the test area and stored in
memory.
3. CALCULATION - the embedded microcomputer then calculates the setting of ALPHA0
where the least jitter is encountered. Some pre-processing is carried out by the OPC
logic to reduce the processor's load. This sequence is performed twice - first a coarse
calibration, followed by a fine-tuning.
The micro controller has many responsibilities. It processes the Serial to Basic Engine, S2B,
commands from the Digital Board. It controls the various processes in the mechanism via I2C.
The MACE3 uses a Parallel communication bus for access to its Flash ROM. The Flash
Memory contains the firmware for the BE. The MACE3, the Encoder and AWSOME share a
parallel bus with 32K of SRAM
When power is applied to the unit, the Digital Board sends a reset signal to the MACE3. The
MACE 3 checks its SRAM, the reads its Flash ROM and sends a System Reset signal to the
ICs on the Servo Board. When its memory tests are complete and they pass, it initializes its I
Square C Bus and communicates to the DROPPI and LADIC on the Mechanism. The Tilt
Motor is exercised and centered. The PSEN signal then appears. A Servo Unit Ready (SUR)
data control clock appears, indicating to the Digital Board that it is ready to receive commands.
The Microcomputer produces several outputs. Many of them are error signals. It produces: the
Radial Error, the Focus Error, the Tilt Motor control, and the Position Control Sled (PCS)
signals. Each of the motors has a driver circuit.
The Microcomputer controls the Tray motor drive circuit. The Tray switch goes directly to the
MACE3.
The Microcomputer controls the PCS. The Position Control Sled must operate very accurately.
It cannot track the Disc’s tracks of 1.6 microns alone, but its precision is a must. There are two
Hall sensors positioned 90 degrees apart in a circular fashion. A round magnet is attached to
the armature of the drive motor. The positioning of the sensors gives them their name, Sine
and Cosine. The motor is a basic universal type. The exact rotation of the armature is detected
by the Hall Sensors. The phase of the Hall sensor signals are compared to a reference signal
generated internally by the MACE3. The focus actuator moves the lens side to side for tracking
the individual tracks. When the drive current to the actuator increases to a certain point, the
microcomputer knows the Sled must be moved. The Sled is driven to minimize the actuator’s
drive current, meaning it is right under the proper track. The microcomputer produces the
Reference DC offset for the Op amp inputs.
Motor Drivers
The motor drivers each receive an error or control voltage. Refer to the circuit drawing. There
are 6 motor drivers in this unit: the Focus Motor Driver, the Radial Motor drivers, the Spindle
Motor Driver, the Tilt Motor Driver, the Sled Motor Driver and the Tray Motor Driver.
The Focus Motor is located on the OPU. It controls the up and down motion of the laser’s lens.
An error signal controls the driver circuit. It is produced by the MACE3 Microcomputer. The FO
signal comes into Pin 3 of 7302. The Driver circuit amplifies the signal and converts it to a
balanced output at Pins 1 and 2 of IC7302. The Output goes to the OPU.
The Radial Motor is located on the OPU. It controls the side to side motion of the laser’s lens.
This is used in conjunction with the Sled Motor for tracking. An error signal communicates the
drive signal to the driver circuit. It is produced by the MACE3 Microcomputer. The RA signal
comes into Pin 25 of 7302. The driver circuit amplifies the signal and converts it to a balanced
output at Pins 26 and 27 of IC7302. The Output goes to the OPU.
The Spindle Motor is a standard three phase motor similar to what is found in VCR capstan
motor circuits. The driver IC,7301, receives two control voltages. The Motor Error signal comes
into Pin 22. There is a Motor Enable switching voltage coming into Pin 23. A three phase drive
signal is provided to the motor. Three hall elements feed speed and phase data back to the
motor driver IC. These signals are amplified. Three FG signals are output to the
Encoder/Decoder from Pins 16, 17, and 18.
The MACE3 produces the SL control voltage for the driver circuit. The Sled motor drive signal
is provided to the Sled Motor by 7302. The SL signal comes into IC7302 on Pin 20. A control
voltage is developed and amplifiers produce the drive voltages on Pins 17 and 18. These are
connected to 1302 on Pins 7 and 8.
Trayin, and Trayout logic control lines are received from the MACE3 and a motor drive signal
is provided to the Tray Motor. The logic control signal comes into IC7302 on Pins 15 and 16. A
control voltage is developed and amplifiers produce the drive voltages on Pins 12 and 13.
These are connected to 1301 on Pins 3 and 4.
Encoder/Decoder/HDR65
The Encoder/Decoder has the following functions:
z Encoder for DVD+RW. This part creates the EFM+ (16 bit) signals from the I2S data
stream.
z Decoder for DVD and CD. This part processes the HF-signal from the SPIDRE. It
converts the EFM(+) signals to data, and performs error detection and error correction.
z Output to SPIDRE pre-processor for RF-AGC.
This IC decodes EFM or EFM+HF signals directly from the SPIDRE. Refer to the circuit
drawing. These include: HF, PLL data recovery, demodulation, and error correction.
The Encoder/Decoder has two independent microcontroller interfaces. The first is a serial I 2C
bus and the second is a standard 8 bit multiplexed parallel interface. Both of these interfaces
provide access to 32k of SRAM 8-bit registers for control and status.
The analog front-end input on Pins 9 and 10 converts the HF input to the digital domain via an
8-bit A/D converter. The A/D is supplied by an AGC circuit to obtain the optimum performance
from the converter. An external oscillator is supplied for this subsystem to recover the data
from the channel stream. It corrects asymmetry, performs noise filtering and equalization, and
finally recovers the bit clock and data from the channel using a digital PLL.
The demodulator portion detects the frame synchronization signals and decodes the EFM (14
bit) and EFM+ (16 bit) data and sub-code words into 8-bit symbols. Via the serial output
interface, the I2S data (audio and video) go to the DVD+RW interface.
The spindle-motor interface provides both motor control signals from the demodulator and, in
addition, contains a tachometer loop that accepts tachometer pulses from the motor unit. The
motor is a standard three phase motor. Motor speed is controlled by the Wobble Processor
during Record. During Playback the Wobble processor is monitoring the Data stacked up in the
SRAM of 7204. The Motor control signal is on Pin 98 which supplies the drive IC 7301.
AWESOME
AWESOME stands for: Adip decoding, Wobble processing, Error correction, Synchronous
start/stop and Occasionally Mend Errors. The AWESOME gate array chip, IC 7401, is a fully
digital DVD+RW add-on for the HDR65. A combination of both ICs can do CD and DVD
decoding and CD, DVD-R(W), and DVD+RW encoding. It contains logic for:
z Wobble processing
z Address detection
z Write clock generation
z Start and stop
z ADdress In Pregroove decoding, Adip
z Spindle motor control to do CLV on wobble
z Link bits insertion (according to DVD+RW standard).
z Output to SPIDRE pre-processor for wobble-AGC
It also receives the serial interface signal from the Encoder/Decoder IC on Pins 6, 7, and 8 and
merges the internal serial bus to be sent to the analog pre-processor (SPIDRE), on pins 72,
78, and 79.
The DVIO Board is a second source of Digital Video to the MPEG2 Encoder circuit. The
Encoder circuit is contained in the EMPRESS, IC7403. The Video Input Processor, VIP,
receives the selected Analog Video from the Analog Board or the DVIO Board, and converts
the selected signal to digital YUV for recording.
All data going to the BE passes through the VSM. The Empress supplies MPEG2 Video to the
Versatile Stream Manager, VSM. The VSM is a hub for data streams. The VSM also sends the
Digital Video to be recorded back through the playback signal path. This output from the VSM
is called the Parallel Digital Video path. Most of the data going to the Digital Processor from
the BE goes through the VSM. The exception is the Digital Video Playback Stream. It goes
directly to the MPEG2 Decoder, IC7200.
The Progressive Scan, Pscan, circuit contains a Line Doubler. The Pscan circuit sends Y/UV
Digital, 480P, Video to the Analog Board to be provided to the Output Jacks.
I2C Bus
The MPEG2 Decoder IC7200 contains a microcomputer. It communicates to the Analog
Board’s Microcomputer via the VSM. The Decoder and the VSM share a data bus, the EMI
Bus. The Decoder controls the operation of the other microcomputers on the Digital Board. via
an I2C Bus. The I2C bus controls the following IC’s: IC7201, IC7403, IC7500, IC7700, and
IC7801. The MPEG2 Decoder operates during Play and Record. It receives Digital Video from
the VSM during Record. It receives Digital Video from the BE during Play. The digital Video
and audio is decoded and supplied to the Analog Board, and the Progressive Scan circuit.
EMI Bus
The VSM and the MPEG2 Decoder share a Data Bus called the External Memory Interface,
EMI. The EMI contains 4 Megabytes of Flash EEPROM. The EEPROM contains the Firmware
for the Digital Board.
System Clocks
The System Clocks (27MHz) of the VSM, EMPRESS, and Progressive Scan circuits are
generated by an oscillator, 7906. Refer to the circuit drawing. The clock signal is buffered and
inverted by 7904, a quad inverter. These signals go to their respective circuits as
SYSCLK_XXXX. During Record mode, the audio clock, ACC_ACLK_OSC is generated by
IC7102. The audio clock must be synchronized with the incoming Video Field Identifier,
VIP_FID. During Playback mode, the audio clock, ACC_ACLK_PLL, is generated by the clock
synthesizer, IC7900. Both, ACC_ACLK_OSC (also goes to the EMPRESS as ACLK_EMP) and
ACC_ACLK_PLL are fed to the VSM. The VSM selects the appropriate clock. The EMPRESS
IC derives from the incoming ACLK_EMP clock the I 2S audio encoder Bit clock and Word
clock, AE_BCLK and AE_WCLK. They are sent to the VSM.
On/Off
The signal IOn, coming from the Analog Board’s microcomputer, enables the switched power
supplies. IOn goes Low to turn power On. The IOn signal passes through the Digital Board to
the Power Supply. The switched supplies are: the 5Vdc and 12Vdc on this module.
Reset
Control signal IRESET_DIG, controlled by the microcomputer on the Analog Board is sent to
the Reset Logic circuit. The IRESET_DIG transitions to High when the whole system is reset. A
Low is output on Pin 1 of 7902. This signal is labeled RESETn. The n on the end of many of
the names of the signal lines means enable.
EMPRESS
The EMPRESS IC encodes the Digital Video stream into an MPEG2 Video stream that is fed
to the VSM. Refer to the circuit drawing. The VIP supplies digital video in the form of CCIR656
parallel Y/UV. I2S Audio is sent from the Analog Board to IC7403/EMPRESS via connector
1602. The EMPRESS compresses the video and audio. It uses 4 meg of SDRAM and is
controlled via the I2C Bus of the Decoder IC. The audio is converted into an I 2S AC3 Audio
stream. The MPEG2 Video and the AC3 Audio stream are sent to the VSM to be recorded.
The VSM must receive data from several sources. Video comes into the VSM on two Data
buses. One Data bus comes from the VIP, and the other from the EMPRESS. The
SYSCLK_VSM on Pin 47 is essential for all input data processing. The VIP_FID_FF signal is
necessary for field information. UART1 carries operational communication between the Digital
Board and the Analog Board's microcomputer. Communication on UART2 is important if the
video source to be recorded is coming from the DVIO Board. The audio data stream coming in
on Pins 177 and 178 uses two special clocks for audio. One is the AE_BCLK, and the other is
ACC_ACLK_PLL.
S2B Interface
The S2B interface between the VSM (IC7100) and the Servo processor MACE3 controls the
Basic Engine during Record and Playback mode. This serial communication goes to the BE on
Pins 24, 132, 154, and 155.
Proper operation of the power up sequence involves the VSM. The VSM communicates to the
Analog Microcomputer, during the Power Up Self Test operation, using UART1.
The VSM uses two types of external memories. It has dedicated SDRAM, 7101, and It shares
the EMI Bus for its Firmware.
Loop-Through
The multiplexed Audio and Video stream in the VSM is fed back via the Parallel Front End
Interface to IC7200. This IC decodes the MPEG2 stream into Analog Video and I2S Audio.
The Video and Audio signals are routed to the Analog Board via connectors 1601 and 1602.
During recording, the signals are present at the outputs of the Analog Board.
MPEG2 Decoder
Playback
During Playback, the serial data from the Basic Engine goes directly to the MPEG2/AC3
Decoder, IC7200 via the serial Front End I2S Interface. Refer to the circuit drawing. IC7200 is
a MPEG2 Audio/Video Decoder and has the following outputs to the Analog Board: RGB, YC,
CVBS, I2S Audio, (PCM format) and SPDIF Audio (Digital Audio output). IC7200 is the source
of the I2C bus on the Digital Board.
MPEG2 decoding is preformed in IC7200. IC7200 uses SDRAM for its many functions. The
Basic Engine provides to the MPEG2 Decoder serial data from the disc on Pins 17-22. The
A/V Demultiplexer separates the Audio and Video data. IC7200 also contains the analog Video
Encoder. It provides RGB, Y/C and PCM audio to the Analog Board.
There is another video output path from IC7200. The Digital Video for the progressive scan
circuit, PSCAN_YUV(0-7).
Record
It produces the Parallel video output path. The Parallel Video path sends the recordable video
and audio back to the outputs during the record process. It receives the selected Multiplexed
Data stream from the VSM via the D_PAR_D(0,7) lines. There are support signals for the
Parallel Data Stream on Pins 196, 201, 205, and 206. Because of the amount of processing,
the output video is delayed about 4 seconds.
ComPair
The Compair service aid connects to 7200 via a serial communication port. Using ComPair
software and a computer’s COM Port, service troubleshooting and settings can be checked.
Compair has a dedicated connection on the Digital Board, 1901. The input Pins for 7200 are 2,
3, 197, 200, and, 204. Compair cannot function if 7200 does not initialize properly.
Power On
IC7200 participates in the initialization of the unit. Power up occurs in two stages. 7200
participates in the second stage. After the Analog Board and the Front Panel Microcomputer
check the unit and pass their tests, the Analog Microcomputer turns On the Standby supplies.
This includes the 3.3Vdc supply for 7200. 7200 then receives the DIG_Resetn signal from the
Analog Board.
7200 creates three reset outputs for the Digital Boards. Resetn_VE goes to the EMPRESS.
RSTN_DVIO goes to the DVIO Board. RSTN_BE goes to the BE. EMPRESS_BOOT signal
goes to the EMPRESS for its start up flag.
If 7200 passes its self test and the other ICs communicate properly, the unit’s power will stay
On. If not, the unit will go into Sleep mode, never looking for keyboard input again. This
process has 10 Seconds to occur. If it does not, the Analog Microcomputer will place the unit in
Sleep mode, turning Off the Standby supplies which is the VCC for most of the ICs on the
Digital Board.
Progressive Scan
The progressive scan section is integrated into the Digital Board and built around the SAGE
Fli2200 Deinterlacer/Line Doubler (7700). Refer to the circuit drawing. This I2C controlled
device uses 64Mbit SDRAM (32bit x 2M) to perform high quality de-interlacing (meshing). The
Deinterlacer gets his Digital Y/UV input data, Pins 20-27, from 7200. The format of the Digital
Y/UV input is CCIR656 with separated H sync, V Sync. Because the 7200 doesn't’t have a V
sync output the odd/even output of this IC has to be translated to a V sync signal. Vertical sync
is generated with a flip-flop IC7701 and an XOR, 7702.
D/A Converter
The output of 7701 (4:4:4 progressive Video) is fed to the Analog Device, 7801. The RGB
output is a current signal fed via a low pass filter to the output Op Amps, 7802 and 7803. The
Analog Video, 480P, is fed via a 7 poled flex to the Analog Board.
There is also a power fail circuit, which is necessary to mute audio when IPFAIL is low. If the
FLYB line is interrupted, 7330 turns Off. R3338 turns On 7331, sending a Low to the D/A
Converter to mute the audio.
Microcomputer
The Microcomputer, IC7803, is a 16 bit processor with internal ROM and 8kB RAM. Refer to
the circuit drawings. Page 1 Page 2 The System Clock operates at 20MHz. It uses I2C
interface to communicate with the other microcomputers in the unit. The clock rate is
approximately 95kHz. The Reset Pin is high during normal operation. It also requires a
composite sync input. The microcomputer uses non-volatile EEPROM, 7815. The EEPROM
stores data specific to the device, such as the AFC-reference value, clock-correction-factor,
etc.
Power up
7803 controls power up of the unit. There are three layers to the power up sequence. The first
layer involves the Analog Board and the Front Panel. The second layer involves the Digital
Board and the BE. The third involves the Front Panel and the Analog Board.
The first layer controls the first set of switched supplies. After the System Control
Microcomputer receives its reset, the ISTBY control voltage goes Low to turn On the first set of
switched supplies, The SW5Vdc and the SW8Vdc. It communicates on the I2C bus initializing
the Tuner, the Audio Decoder, and the Video/Audio Routing ICs. If they respond properly, It
then communicates on the I2C to the Front Panel Microcomputer. If the Front Panel
Microcomputer responds properly, the ION control voltage goes Low.
The second layer occurs when the ION switching voltage comes out of the Analog Board. The
ION control voltage passes through the Digital Board to the Power Supply and turns On a
second set of switched voltages. These include the 3.3Vdc supply. The 3.3Vdc supply is the
main B+ to many of the microcomputers throughout the unit. The System Control
Microcomputer then sends out the IReset signal to 7902 on the Digital Board. This IC produces
a delayed Resetn signal line for 7200. 7200 activates its I2C and provides several reset and
initialization signals for the Digital Boards and the BE. They all go through a self test. If the self
test succeeds, the VSM communicates through UART1 that the system is operating, and the
unit can enable the Front Panel to accept a response. The Front Panel Microcomputer then
places four dashes on the Front Panel Display. ION goes High placing the unit in Standby,
waiting for keyboard input. This normally takes 6-8 seconds. The System Control
Microcomputer allows 10 seconds for the UART1 response. If it does not come, the unit goes
into Sleep mode, and will not accept keyboard input.
When the Front Panel Microcomputer receives a keyboard response, it communicates that
action to the System Control Microcomputer to switch back On the second layer of switched
voltages.
Tuner
The Tuner is capable of receiving 125 channels, and is cable ready. Refer to the circuit
drawing. The RF connections on the back of the unit provide an RF loop through. There is no
RF Modulator, as seen in VCRs. The Tuner/Demodulator receives two supply voltages, 33Vdc
and SW5Vdc. The channel selection information is communicated via the I2C lines.
The IF signal, from the Tuner, is processed by the demodulator, IC7703. This unit is unique in
that it has two SAW Filters. 1701 is used for the Video IF, and 1702 is used for the Sound IF.
The AFC coil 5703 is adjusted so that when a frequency of 45.75 MHz is supplied to the IF
output of the Tuner, the AFC voltage on pin 17 of 7703 is 2.5V. The AGC is set using 3707 so
that, with a sufficiently large antenna input signal (74 dBV), the voltage at the IF output of the
Tuner, 1705 Pin 11 is 500 mVp-p. This adjustment must be performed with the audio carrier
switched off. The demodulated Video signal appears on Pin 16 of 7703. The Demodulator
AGC voltage at Pin 4 is used to determine the antenna signal strength. The FM-PLL
demodulator function of 7703 is not used and is deactivated by 3726. SIF1 is generated for
demodulation in the Sound processor, 7600.
The final stages in the demodulation process filter and amplify the Video. The signal is
buffered by 7705, AGC_MUTE. In the opposite direction, this line may be used to mute the
demodulator to avoid crosstalk when the Tuner signal is not needed. In this case, a High is
sent via AGC_MUTE. The Video trap 1703 reduces adjacent channel video and any sound
carrier left in the Video. The demodulated Video signal VFV is available after the buffer and
limiter stage. The Limiter,7706, filters noise peaks.
Audio Demodulator
The Sound Processor, 7600, demodulates the Audio and performs A/D and D/A conversion.
Refer to the circuit drawing. The I2C bus controls its operation. It uses two power supplies, the
5Vdc and the 8V Switched. IC 7600 has its own oscillator on Pins 5 and 6. It is a NTSC sound
processor. Amplitude and bandwidth of the demodulated audio signals can be determined in
7600 using the I2C bus. The Audio signal output from the Tuner is available at the Pins 30,
AFER, and 31, AFEL.
The Audio I/O switching is also controlled by 7507 via the I 2C Bus. Analog Audio coming from
Rear External Inputs 1,2, and External 3 are capacitively coupled to IC7507, Pins 35, 37, 53,
and 56. Digital Board input and Tuner Audio is routed via 7600 to 7507, Pins 39 and 41. 7507
selects the audio source. There are also two SVideo input connection possibilities: Front and
Rear SVideo In, which are connected to the input selector IC 7400 and 7401. Refer to Figure
49. One is used for Y, the other is used for Chroma switching. The outputs of 7400 and 7401
are connected to 7507, where the signals are routed as the Y/C selected input.
The Audio I/O switching is also controlled by 7507 via the I 2C Bus. Refer to the circuit drawing.
Analog Audio coming from Rear External Inputs 1, 2, and External 3 are capacitively coupled
to IC7507, Pins 35, 37, 53, and 56. Digital Board input and Tuner Audio is routed via 7600 to
7507, Pins 39 and 41. 7507 selects the audio source.
Output Jacks
CVBS Out is provided by the 75 Ohm driver 7430. Refer to the circuit drawing. Both CVBS
output sockets are connected to 7430 in parallel. Independent of which input signal is being
used: CVBS, S-Video, or Y/UV, 7507 supplies SVideo and Y/UV signals to the corresponding
sockets.
RC In
A Remote Control input socket is provided for those users that have a component stack with
multi remote capabilities.
The Y/UV In signal is routed directly to the Digital Board; there is no Y/UV IN to Y/UV Out loop
through in Standby. Refer to the circuit drawing. The Digital Board supplies only RGB signals,
a RGB Y/UV matrix is used. Refer to the circuit drawing. This matrix consists of the operational
amplifier 7200 which generates the U and V signals according the formulas: 2U = B -.338R -
.661G and 2V = R - .838G - .161B. Then the signals are routed to the UV Output sockets via
the 75-Ohm driver 7516. The corresponding Y signal is coming from the Digital Board via the
7507. The 75 Ohm Y jack is driven by 7516 connected to the Y/UV Output.
Audio Conversion
Audio is converted from analog to digital for recording purposes, and digital audio is converted
to Analog during Playback.
A/D
This is accomplished by 7004, Refer to the circuit drawing. IC7004 uses a PCM CLK signal, a
Bit CLK, and a Word CLK. An input amplitude of up to 2Vrms is expected on Pins 1 and 3.
7004 sends the data in I2S format to the Digital Board via Pin 13.
D/A
After a delay, the processed audio data comes back from the Digital Board to a D/A converter,
7001 on Pins 10, 11, and 12. 7001 converts the I 2S data back into a balanced analog signal on
Pins 28, 29, 31 and 32. IC 7001 uses a D_PCM CLK signal, a D_Bit CLK, and a D_Word CLK.
7002 converts the signals from a balanced output into standard cold ground referenced
signals. The signals go to 7507 on Pins 47 and 49, and the Audio Out Jacks.
Fan Control
The Fan Control circuit is necessary to control the speed of the cabinet fan, 1984, and the BE
Fan according to the changes of temperature and motor noise. Refer to the circuit drawing.
The temperature is measured via a Negative Temperature Coefficient, NTC, thermistor on the
IR Receiver Board, 3135. The sensor’s output voltage is labeled Temp_Sense.
The Fan Control circuit uses Op Amps to gain control of the sensor’s signal. When the
temperature is lower than 25°C the cabinet fan’s voltage is approximately. 5V and will reach
approximately 10V at a temperature of 40°C. The Microcomputer controls the On/Off function
of the two fans via control line ION_FAN and SW_BE_FAN. The TEMP signal goes to the
Microcomputer and the inputs of the Op Amps. The Microcomputer supplies the Motor On
switching voltages. The speed of both fans are controlled by the Temp_Sense line going into
the Op Amps.
Block Diagram
The DVIO module consists of the following blocks, refer to the block diagram. An independent
tunable audio and video clock is used for FIFO and PLL. A Microcomputer using an 8051 CPU
with 64 kilobyte of flash memory controls the whole operation. It also has 1 kilobyte of internal
data memory. There is a Watchdog timer and PCA outputs. The System Clock runs at
11.0592MHz. On board In Circuit Programming, ISP, can be used to update the EEPROM,
"Downloading".
Clock Circuit
There are two clocks to consider in the system, the video clock and the audio clock. Refer to
the circuit drawing. These two clocks are independent and will be discussed separately. The
video clock is approximately 27 MHz. When data is flowing from an external source, it does not
have exactly the same frequency and phase. Refer to the circuit drawing. This could cause
buffers to under-run or over-run. Since the clock cannot be modified in the source the clock is
adjusted to the required frequency and phase to process at the rate of the incoming data. The
same requirements apply to the audio clock. The audio clock operates at three frequencies.
The source can have a frequency of 8.192 MHz, 11.2896 MHz, or 12.228 MHz. This depends
on the sample-rate frequency 32kHz, 44.1kHz, or 48kHz, of the Audio signal.
DV Decoder
The AV data goes from the FIFO to the Decoder. Refer to the circuit drawing. It decodes the
stream into video data in 656 format. The Microcomputer has the ability to read the status
registers of the NW700 through the FPGA. By reading these registers extra data from the DV
stream, that is not decoded into audio or video, can be sent to the Digital Board, using TXD of
the serial interface. This includes Time Stamp and other similar data.
List of Abbreviations
+12V +12V Power Supply
+35V_DV_EDO +3V3 Power supply EDO Bus IC7404
+2V5_FLI +2V5 Power Supply for FLI
+2V5_PLL +2V5 Power Supply for PLL
+3V3 +3V3 Power Supply
+3V3_ANA +3V3 Power Supply Analogue
+3V3_DD +3V3 Power Supply Digital
+3V3_DLY +3V3 Power supply for IC7500
+3V3_DV +3V3 Power supply for IC7404
+3V3_FLI +3V3 Power Supply for FLI
+3V3_FPGA +3V3 Internal Power supply for IC7303
+3V3_FPGA_CONF +3V3 Power supply for IC 7300
+3V3 Analogue Power supply for PHY IC
+3V3_IEEE_A
7101
+3V3 Digital Power supply for PHY IC
+3V3_IEEE_D
7101
+3V3_IEEE_PLL +3V3 PLL Power supply for PHY IC 7101
+3V3_LINK +3V3 Power supply IC7103
+3V3_PLL +3V3 Power supply IC7307 & IC7308
+3V3 Power supply IC7301, IC7302,
+3V3_SRAM
IC7305 & IC7306
+5V +5V Power Supply
+5V_BUFFER +5V Power Supply for Video Filters
+5V Power supply IC7200, IC7201,
+5V_PROC
IC7203 & IC7208
+3V3 Power supply for DV_RAM (IC7400-
+VCC_DV_RAM
-> IC7404)
Horizontal Synchronization from Host
5508_HS
Decoder to Progressive Scan
Odd - Even control from Host Decoder to
5508_ODD_EVEN
Progressive Scan
Reset of LINK IC (7103) and PHY IC
1394_RSTN
(7101)
-5V -5V Power Supply
-5V_BUFFER -5V Power Supply for Video Filters
A(0:8) Address lines
A_EMPRESS(13:0) EMPRESS address output to SDRAM
Power Calibration Maximum and Minimum
A1,A2
signals
Audio Clock PLL output sync with
ACC_ACLK_OSC
incoming video for record
ACC_ACLK_PLL Audio Clock PLL output for play back
ACLK_EMP EMPRESS audio clock output
AD_ACLK Audio Decoder Clock
AD_BCLK Audio Decoder I2S bit clock
AD_DATAO Audio Decoder Output data (PCM)
AD_SPDIF33 Audio digital output to the analog board
AD_WCLK Audio Decoder I2S word clock
ADC Analogue to Digital Converter
ADIP ADdress In Pre-groove
AE_ACLK Audio Encoder Clock
AE_ACLK_OEN Audio Encoder Clock Output Enable
AE_BCLK Audio Encoder I2S bit clock
AE_BCLK_DV Audio Encoder I2S bit clock to DVIO
AE_BCLK_VSM Audio Encoder I2S bit clock to VSM
AE_DATAI Audio Encoder Input data (PCM)
Audio Encoder Input data (PCM) from
AE_DATAI_DV
DVIO
AE_DATAO Audio Encoder Output data (PCM)
AE_WCLK Audio Encoder I2S word clock
AE_WCLK_DV Audio Encoder I2S word clock to DVIO
AE_WCLK_VSM Audio Encoder I2S word clock to VSM
AGC Automatic Gain Control
ANA_WE Analogue write enable
ANA_WE_LV Analogue write enable Low Voltage
AUD_BCLK Audio Bit Clock
AUD_MUTE Audio Mute
AUD_SDI Audio Serial Data Input
AUD_SDO_CON Audio Serial Data Output to buffer IC 7505
AUD_SDO_DAC Audio Serial Data Output to DAC IC 7506
AUD_WS_701 Audio Word Select to DV CODEC IC 7404
AUD_WS_OUT Audio Word Select to buffer IC 7505
Adip decoding Wobble processing Error
AWSOME Correction Synchronous start/stop and
Occasionally Mend Errors
B_IN_VIP Video blue input to Video Input Processor
B_OUT Video blue output from Host Decoder
B_OUT_B Filtered blue video output
BA Bank Address
BCLK_CTL_SERVICE Bitclock control Service Interface
BE_BCLK Basic Engine I2S bit clock
BE_BCLK_VSM Basic Engine I2S bit clock to VSM
Basic Engine Control Processor ready to
BE_CPR
accept data
BE_DATA_RD Basic Engine Data read
BE_DATA_WR Basic Engine Data write
BE_FAN Basic Engine FAN
BE_FLAG Basic Engine error flag
BE_IRQN Basic Engine interrupt request
BE_LOADN Basic Engine LOAD(LOW active)
BE_RXD Basic Engine S2B received data
Basic Engine servo unit ready to accept
BE_SUR
data (S2B)
BE_SYNC Basic Engine sector/abs time sync
BE_TXD Basic Engine S2B transmitted data
BE_V4 Basic Engine versatile input pin
BE_WCLK Basic Engine I2S word clock
BUFENN_AUD Buffer Enable Audio
BUFENN_VID Buffer Enable Video
C_IN Video Chrominance input
Chrominance input to Video Input
C_IN_VIP
Processor
C_OUT Chrominance output from Host Decoder
C_OUT_B Filtered Chrominance output
CALF Laser Calibration Final voltage
CAS Column Address strobe
CAV Constant Angular Velocity
CB_OUT(9:0) Chrominance Blue out
CCLK Configuration Clock
CLK27M 27MHz Clock
CLK27M_CON 27MHz Clock to Digital Board
CLK27M_DV 27MHz Clock Digital Video Codec
CLK27M_OSC 27MHz Clock IC7304
CLK4 SDRAM clock
CLOCKGENAUD Clock generator Audio
CLOCKGENVID Clock generator Video
CLV Constant Linear Velocity
Cosphi Cosine Position Hall Information
CPUINT0 Control processor unit interrupt
CPUINT1 Control processor unit interrupt
CR_OUT(9:0) Chrominance Red out
CS Chip Select
CTS1P Clear to send (Service Interface)
CTSN Clear to Send
CVBR Cd Variable Bit Rate recording
Composite video output out of the Host
CVBS_OUT
Decoder
CVBS_OUT_B Filtered Composite video output
Composite video output to Video Input
CVBS_OUT_B_VIP
Processor(digital board video loop)
CVBS_Y_IN Composite video/Luminance input
Composite video/Luminance input to
CVBS_Y_IN_A
Video Input Processor
Composite video/Luminance input to
CVBS_Y_IN_B
Video Input Processor
Composite video/Luminance input to
CVBS_Y_IN_C
Video Input Processor
D_ADDR(10:0) Address bus
D_DATA(29:0) Data bus
D_EMPRESS(15:0) SDRAM data input/output of EMPRESS
D_PAR_D(7:0) Front-end parallel interface data (record)
D_PAR_DVALID Front-end parallel interface data valid
D_PAR_REQ Front-end parallel interface request
D_PAR_STR Front-end parallel interface strobe
D_PAR_SYNC Front-end parallel interface sync
DAC Digital to Analogue Converter
DAIO Digital Audio Input Output
DENC Digital Encoder
Direction For Use: description for the end
DFU
user
DNR Dynamic Noise Reduction
DOUT Serial configuration data output
DRAM Dynamic RAM
DROPPI Dvd Rewritable Opu Pre-Processor IC
DSD Direct Stream Digital
DSP Digital Signal Processing
DV_ASN DVCODEC Address Strobe
DV_DRQN DVCODEC Data Request Interrupt
DV_DSLN DVCODEC Data Strobe Lower 8 bits
DV_DSUN DVCODEC Data Strobe Upper 8 Bits
DV_DTACKN DVCODEC Data Transfer Acknowledge
DV_ERRN DVCODEC Error Interrupt
DV_HS_IN DVCODEC Horizontal synchronization In
DV_HS_OUT DVCODEC Horizontal Sync Out
DV_IN_CLK Digital Video in clock from DVIO board
DV_IN_DATA(7:0) Digital Video in data bus from DVIO board
Digital Video in horizontal sync from DVIO
DV_IN_HS
board
Digital Video in vertical synchronization
DV_IN_VS
from DVIO board
DV_LCN DVCODEC Last Code Interrupt
DV_PDN DVCODEC Power Down
DV_RSTN DVCODEC System Reset for NW701
DV_RWN DVCODEC Read/Write control signal
DV_VS DVCODEC Vertical Sync
Digital Video Encoder and Decoder
DVCODEC
compression scheme
EEPROM Electrical Erasable Programmable ROM
EFM Eight to Fourteen bit Modulation
External Memory Interface Address Bus
EMI_A(21:1)
(Host Decoder)
External Memory Interface Lower byte
EMI_BE0N
enable(Host Decoder)
External Memory Interface Upper byte
EMI_BE1N
enable(Host Decoder)
External Memory Interface SDRAM
EMI_CAS0N
column address strobe(Host Decoder)
External Memory Interface VSM Lower
EMI_CE1N
bank enable
External Memory Interface VSM Higher
EMI_CE2N
bank enable
External Memory Interface flash IC"s
EMI_CE3N
enable
External Memory Interface Data Bus(Host
EMI_D(15:0)
Decoder)
VDD_PLL
Power supply PLL audio decoder of
Sti5508
VDD_RGB Power supply video encoder of Sti5508
VDD_STI Power supply of Sti5508
VDD_YCC Power supply video encoder of Sti5508
VDD5_MK2703 Power supply MK2703
VDD5_OSC Power supply Oscillator
VDDA1A_7118 Power supply for analog input of VIP
VDDA2A_7118 Power supply for analog input of VIP
VDDA3A_7118 Power supply for analog input of VIP
VDDA4A_7118 Power supply for analog input of VIP
Power supply digital for peripheral cells of
VDDE_7118
VIP
VDDI_7118 Power supply digital for core of VIP
VDDX_7118 Power supply for crystal oscillator of VIP
VE_DATA(7:0) Video Encoder data Bus
VE_DSN Video Encoder Data Strobe
Video Encoder Data Transfer
VE_DTACKN
acknowledge
VIP_ERROR Video Input Processor error
VIP_FB Video Input Processor Fast Blanking
Video Input Processor field identifier to
VIP_FID_FF
Flip Flop
VIP_HS Video Input Processor Horizontal Sync
VIP_CLK Video Input Processor input Clock
Video Input Processor output data
VIP_IDQ
qualifier
Video Input Processor input general
VIP_IGP1
purpose 1
VIP_INT Video Input Processor interrupt
VIP_RTS1 Video Input Processor ready to send
VIP_VS Video Input Processor Vertical Sync
Video Input Processor digital video(CCIR
VIP_YUV(7:0)
656)
VS_IN Vertical Sync IN
Versatile Stream Manager SDRAM
VSM_M_A(13:0)
address bus
Versatile Stream Manager SDRAM
VSM_M_CASN
column address strobe
Versatile Stream Manager SDRAM clock
VSM_M_CLKEN
enable
Versatile Stream Manager SDRAM clock
VSM_M_CLKOUT
out
Versatile Stream Manager SDRAM data
VSM_M_D(15:0)
bus
Versatile Stream Manager SDRAM lower
VSM_M_LDQM
data mask enable
Versatile Stream Manager SDRAM row
VSM_M_RASN
address strobe
Versatile Stream Manager SDRAM upper
VSM_M_UDQM
data mask enable
Versatile Stream Manager SDRAM write
VSM_M_WEN
enable
Versatile Stream Manager UART1 clear to
VSM_UART1_CTSN
send to analog board
Versatile Stream Manager UART2 clear to
VSM_UART1_RTSN
send to DVIO board
Versatile Stream Manager UART1 ready
VSM_UART1_RX
to send to analog board
Versatile Stream Manager UART2 ready
VSM_UART1_TX
to send to DVIO board
Versatile Stream Manager UART1
VSM_UART2_CTSN
received data to analog board
Versatile Stream Manager UART2
VSM_UART2_RTSN
received data to DVIO board
Versatile Stream Manager UART1
VSM_UART2_RX
transmitted data to analog board
Versatile Stream Manager UART2
VSM_UART2_TX
transmitted data to DVIO board
VSOUT Vertical Sync OUT
WE Write Enable
WEN Write Enable control signal to SRAM
The spiral track stamped into recordable
WOBBLE
discs
Y_IN Luminance input from analog board
Y_OUT Luminance output from Host Decoder
Y_OUT_B Filtered luminance output
Luminance (Y) and Chrominance (C)
Y/C
signal
Y/UV Component video
YUV(0:7) Digital Video
YY_OUT(9:0) Luminance output from FLI
All Models (2022) - Set Wiring Diagram
All Models (2022) - Set Block Diagram
All Models (2022) - Basic Engine Block Diagram
All Models (2022) - Power Supply (Page 1) Schematic
All Models (2022) - Power Supply (Page 2) Schematic
All Models (2022) - Display Panel Schematic
All Models (2022) - Front AV Panel Schematic
All Models (2022) - IR and Standby Panel Schematic
All Models (2022) - Analog Board: All in One 1 Schematic
All Models (2022) - Analog Board: All in One 2 Schematic
All Models (2022) - Analog Board: Tuner / Demodulator Schematic
All Models (2022) - Analog Board: In / Out 1 Schematic
All Models (2022) - Analog Board: In / Out 2 Schematic
All Models (2022) - Analog Board: In / Out 3 Schematic
All Models (2022) - Analog Board: Sound Processing Schematic
All Models (2022) - Analog Board: Power Supply Schematic
All Models (2022) - Analog Board: Converter Schematic
All Models (2022) - Analog Board: RGB-YUV Converter Schematic
All Models (2022) - Analog Board: Digital In / Out Schematic
All Models (2022) - Analog Board: Fan Control Schematic
All Models (2022) - DVIO Front Board Schematic
All Models (2022) - DVIO Board: 1394 Interface Schematic
All Models (2022) - DVIO Board: Microprocessor Schematic
All Models (2022) - DVIO Board: Fifo & Control Schematic
All Models (2022) - DVIO Board: DVCODEC Schematic
All Models (2022) - DVIO Board: Audio & Video Output Schematic
All Models (2022) - Digital Board: VSM, Buffer Mem & Bit Engine Interface Schematic
All Models (2022) - Digital Board: AV Decoder STI5508 Schematic
All Models (2022) - Digital Board: AV Decoder Memory
All Models (2022) - Digital Board: Video Encoder, Empress
All Models (2022) - Digital Board: VIP CVBS Y/C Video Input
All Models (2022) - Digital Board: Analog Board Cons. Video In / Output
All Models (2022) - Digital Board: Progressive Scan - 1
All Models (2022) - Digital Board: Progressive Scan - 2
All Models (2022) - Digital Board: Power, Clock, and Reset Audio Clock
All Models (2022) - Servo Board 43015: Pre- Processor Schematic
All Models (2022) - Servo Board 43015: MACE3 Schematic
All Models (2022) - Servo Board 43015: Driver Schematic
All Models (2022) - Servo Board 43015: Decoder / Encoder Schematic
All Models (2022) - Servo Board 43015: Power Schematic
All Models (2022) - Servo Board 43353: Pre- Processor Schematic
All Models (2022) - Servo Board 43353: MACE3 Schematic
All Models (2022) - Servo Board 43353: Driver Schematic
All Models (2022) - Servo Board 43353: Decoder / Encoder Schematic
All Models (2022) - Servo Board 43353: Power Schematic
All Models (2022) - Power Supply CBA (Top View)
All Models (2022) - Power Supply CBA (Bottom View)
All Models (2022) - Display Panel CBA (Top View)
All Models (2022) - Display Panel CBA (Bottom View)
All Models (2022) - Front AV Panel CBA (Top)
All Models (2022) - Front AV Panel CBA (Bottom)
All Models (2022) - Analog Board CBA (Top View)
All Models (2022) - Analog Board CBA (Bottom View)
All Models (2022) - DVIO Front Board CBA (Top View)
All Models (2022) - DVIO Board CBA (Top View)
All Models (2022) - DVIO Board CBA (Bottom View)
All Models (2022) - Digital Board CBA (Top View)
All Models (2022) - Digital Board CBA (Bottom View)
All Models (2022) - Layout Servo Board 43015: (Top Side)
All Models (2022) - Layout Servo Board 43015: (Bottom Side)
All Models (2022) - Layout Servo Board 43353: (Top Side)
All Models (2022) - Layout Servo Board 43353: (Bottom Side)
All Models (2022) - Layout Analog Board (Testlands Top View)
All Models (2022) - Layout Analog Board (Testlands Bottom View)
All Models (2022) - Layout DVIO Board (Testlands Bottom View)
All Models (2022) - Layout Digital Board (Testlands Bottom View)
All Models (2022) - Test Point Overview Servo Board 43015
All Models (2022) - Test Point Overview Servo Board 43353
DVDR98517 - Manual no. 2022
Mechanical Parts 3143 Res, 10k, 5%, 1/16W. . . . . . . . . . 4822 051 30103
Mechanical Parts 3144 Res, 390 ohm, 5%, 1/16W. . . . . . . . 4822 051 30391
60 CONNECTOR FRONT ASSY (US). . . . . . . 3104 127 13560 3145 Res, 10k, 5%, 1/16W. . . . . . . . . . 4822 051 30103
65 TRAY FRONT ASSY COMPLETE . . . . . . . 3104 127 13450 3146 Res, 10k, 5%, 1/16W. . . . . . . . . . 4822 051 30103
65 TRAY FRONT ASSY COMPLETE . . . . . . . 3104 127 13520 3147 Res, 10k, 5%, 1/16W. . . . . . . . . . 4822 051 30103
81 VAE8015/002. . . . . . . . . . . . . . 9305 025 81502 3148 Res, 2k2, 5%, 1/16W. . . . . . . . . . 4822 051 30222
151 COVER ASSY . . . . . . . . . . . . . . 3104 127 13320 3149 Res, 4k7, 5%, 1/16W. . . . . . . . . . 4822 051 30472
191 FILTER AIR INLED BOTTOM. . . . . . . . 3104 124 07455 3150 Res, 5k6 5%, 1/16W . . . . . . . . . . 4822 051 30562
197 DUST FILTER. . . . . . . . . . . . . . 3104 123 30002 3151 Res, 1k, 5%, 1/16W . . . . . . . . . . 4822 051 30102
198 FILTER AIR INLET COVER . . . . . . . . 3104 124 07733 3152 Res, 22k, 5%, 1/2W . . . . . . . . . . 4822 116 52257
199 DC BRUSHLESS FAN . . . . . . . . . . . 3104 128 93031 3153 Res, 5R6, 1%, 1/16W, Metalized Glass . 2322 704 65608
151 FOOT SILVER ASSY . . . . . . . . . . . 3104 127 10740 3154 Res, 10k, 1%, 1/16W . . . . . . . . . 4822 050 21003
152 FOOT SILVER ASSY . . . . . . . . . . . 3104 127 10740 3155 Res, 2k2, 5%, 1/16W. . . . . . . . . . 4822 051 30222
153 FOOT SILVER ASSY . . . . . . . . . . . 3104 127 10740 3156 Res, 10k, 1%, 1/16W . . . . . . . . . 4822 050 21003
154 FOOT SILVER ASSY . . . . . . . . . . . 3104 127 10740 3157 Res, 47k, 5%, 1/2W . . . . . . . . . . 4822 116 83884
S 109 USER MANUAL DVDR985/171. . . . . . . . 3104 125 24290 3158 Res, 22k, 5%, 1/16W. . . . . . . . . . 4822 051 30223
170 DVDRW/006 PHILIPS DISC EUROPE. . . . . 9307 002 60006 3159 Res, 5k6 5%, 1/16W . . . . . . . . . . 4822 051 30562
171 DVD +R TEST DISC . . . . . . . . . . . 9307 002 60008 3160 Res, 5R6, 1%, 1/16W, Metalized Glass . 2322 704 65608
S 1001 DVDR DIG. BOARD 1.5 EMPRESS/US . . . . 3104 128 07800 3161 Res, 68k, 5%, 1/16W. . . . . . . . . . 4822 051 30683
S 1002 PSU DVDR1000-2 USA 50PS203 . . . . . . 3122 427 22721 3162 Res, 68k, 5%, 1/16W. . . . . . . . . . 4822 051 30683
S 1003 DVDR ANALOG BOARD NAFTA GEN1.5 . . . . 3103 608 50300 3163 Res, 10k, 5%, 1/16W. . . . . . . . . . 4822 051 30103
S 1005 PB DVDR1000 DVIO GEN.1.5 ASSY. . . . . 3104 128 07900 3164 Res, 10k, 1%, 1/16W . . . . . . . . . 4822 050 21003
8001 CWAS FLEX DVD 22 70 32S. . . . . . . . 3104 157 11641 3165 Res, 2k2, 5%, 1/16W. . . . . . . . . . 4822 051 30222
8002 CWAS FLEX DVD 22 70 32S. . . . . . . . 3104 157 11641 3166 Res, 270 ohm, 5%, 1/2W . . . . . . . . 4822 116 83876
8003 CWAS SPLIT FLEX 30 100 32S . . . . . . 3104 157 11790 3167 Res, 270 ohm, 5%, 1/2W . . . . . . . . 4822 116 83876
8004 CWAS FLEX DVD 10 110 32S . . . . . . . 3104 157 11531 3168 Res, 100 ohm, 5%, 1/2W . . . . . . . . 4822 116 52175
8013 CABLE IEEE-1394 4P AMP . . . . . . . . 3104 128 92921 3169 Res, 10k, 5%, 1/16W. . . . . . . . . . 4822 051 30103
8015 CWAS FLEX DVDR 7 360 32S . . . . . . . 3104 157 12191 3171 Res, 2k2, 5%, 1/16W. . . . . . . . . . 4822 051 30222
3172 Res, 4k7, 5%, 1/16W. . . . . . . . . . 4822 051 30472
Front Assy 3173 Res, 10k, 5%, 1/16W. . . . . . . . . . 4822 051 30103
Front Assy 3174 Res, 4M7, 5%, 1/16W, Metalized Glass . 4822 051 30475
1 FRONT ASSY . . . . . . . . . . . . . . 3104 127 13540 3177 Res, 1k, 5%, 1/16W . . . . . . . . . . 4822 051 30102
2 SIDE PLATE LEFT ASSY . . . . . . . . . 3104 127 13220 3178 Res, 2k2, 5%, 1/16W. . . . . . . . . . 4822 051 30222
3 SIDE PLATE RIGHT ASSY. . . . . . . . . 3104 127 13230 3180 Res, 10k, 5%, 1/16W. . . . . . . . . . 4822 051 30103
4 WINDOW . . . . . . . . . . . . . . . . 3104 124 08470 3182 Res, 1k5, 5%, 1/16W. . . . . . . . . 4822 051 30152
5 LIGHT GUIDE DVD STEP 2K. . . . . . . . 3139 244 00761 3183 Res, 2k2, 5%, 1/16W. . . . . . . . . . 4822 051 30222
11 BUTTON STANDBY ASSY. . . . . . . . . . 3104 127 13240 3186 Res, 1k, 5%, 1/16W . . . . . . . . . . 4822 051 30102
12 BUTTON PLAY/STOP/RECORD ASSY . . . . . 3104 127 13250 3187 Res, 2k2, 5%, 1/16W. . . . . . . . . . 4822 051 30222
13 BUTTON OPENCLOSE/RECVOLUM ASSY . . . . 3104 127 13260 3188 Res, 4k7, 5%, 1/16W. . . . . . . . . . 4822 051 30472
14 BUTTON DISPLAY ASSY. . . . . . . . . . 3104 127 13270 3189 Res, 10k, 5%, 1/16W. . . . . . . . . . 4822 051 30103
15 IR LENS ASSY . . . . . . . . . . . . . 3104 127 13530 3190 Res, 47k, 1%, 1/16W. . . . . . . . . . 4822 117 12925
S 1001 DISPLAYPANEL 4330 ASSY DVDR980 . . . . 3104 128 08270 3192 Res, 1k, 5%, 1/16W . . . . . . . . . . 4822 051 30102
S 1006 PCB ASSY 4319 DVIO-FRONT . . . . . . . 3104 128 07610 3193 Res, 10k, 5%, 1/16W. . . . . . . . . . 4822 051 30103
3194 Res, 2k2, 5%, 1/16W. . . . . . . . . . 4822 051 30222
Display PWB 3197 Res, 4k7, 5%, 1/16W. . . . . . . . . . 4822 051 30472
Display PWB 3999 TER. . . . . . . . . . . . . . . . . . 4822 117 12842
1140 SWITCH TACT PUSH . . . . . . . . . . . 4822 276 13732 5150 Coil, 10u. . . . . . . . . . . . . . . 4822 157 51462
1150 PROT DEV 65V 250MA PSC A . . . . . . . 2422 086 10947 5151 Coil, 10u. . . . . . . . . . . . . . . 4822 157 51462
1153 CST12,00MTW-TF01 . . . . . . . . . . . 5322 242 73686 5153 TRANSFORMER HEATER . . . . . . . . . . 2422 531 02423
1156 BUZZER PIEZO CB13PA-X5 . . . . . . . . 2422 527 00513 6140 LED VS LTL-14CHJ . . . . . . . . . . . 9322 140 17676
1159 SWITCH TACT PUSH . . . . . . . . . . . 4822 276 13732 6150 Zener Diode, 6.8 volt. . . . . . . . . 9322 129 38685
1160 SWITCH TACT PUSH . . . . . . . . . . . 4822 276 13732 6151 MCL4148. . . . . . . . . . . . . . . . 4822 130 83757
1162 SWITCH TACT PUSH . . . . . . . . . . . 4822 276 13732 6152 DIO SIG BAW56W . . . . . . . . . . . . 9340 260 20115
1163 SWITCH TACT PUSH . . . . . . . . . . . 4822 276 13732 6154 Zener Diode, 2.7 volt. . . . . . . . . 9322 102 64685
1167 SWITCH TACT PUSH . . . . . . . . . . . 4822 276 13732 6155 DIO SIG BAW56W . . . . . . . . . . . . 9340 260 20115
1168 SWITCH TACT PUSH . . . . . . . . . . . 4822 276 13732 6156 MCL4148. . . . . . . . . . . . . . . . 4822 130 83757
1169 SWITCH TACT PUSH . . . . . . . . . . . 4822 276 13732 6157 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
1170 SWITCH TACT PUSH . . . . . . . . . . . 4822 276 13732 6158 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
1171 SWITCH TACT PUSH . . . . . . . . . . . 4822 276 13732 6159 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
1174 SWITCH TACT PUSH . . . . . . . . . . . 4822 276 13732 6160 DIO SIG BAW56W . . . . . . . . . . . . 9340 260 20115
2140 Cap, 22u, 20%, 16v, Electrolytic . . . 4822 124 11946 6161 DIO SIG BAW56W . . . . . . . . . . . . 9340 260 20115
2150 Cap, 47u, 20%, 16V . . . . . . . . . . 4822 124 80231 6164 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2151 Cap, 100n, +80/-20%, 25v, Ceramic. . . 4822 126 14305 6165 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2152 Cap, 47n, 5%, 250V . . . . . . . . . . 4822 121 43526 6166 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2154 Cap, 330u, 20%, 16V. . . . . . . . . . 4822 124 40849 6167 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2155 Cap, 100n, +80/-20%, 25v, Ceramic. . . 4822 126 14305 6168 DIO SIG BAW56W . . . . . . . . . . . . 9340 260 20115
2156 Cap, 100n, +80/-20%, 50v, Ceramic. . . 2238 586 59812 6169 DIO SIG BAW56W . . . . . . . . . . . . 9340 260 20115
2157 Cap, 10n, 10%, 50V . . . . . . . . . . 5322 126 11583 6170 DIO SIG BAW56W . . . . . . . . . . . . 9340 260 20115
2158 Cap, 100n, +80/-20%, 25v, Ceramic. . . 4822 126 14305 6171 DIO SIG BAW56W . . . . . . . . . . . . 9340 260 20115
2159 Cap, 100n, +80/-20%, 50v, Ceramic. . . 2238 586 59812 6172 DIO SIG BAW56W . . . . . . . . . . . . 9340 260 20115
2160 Cap, 100n, +80/-20%, 25v, Ceramic. . . 4822 126 14305 6173 DIO SIG BAW56W . . . . . . . . . . . . 9340 260 20115
2161 Cap, 100n, +80/-20%, 25v, Ceramic. . . 4822 126 14305 6174 DIO SIG BAW56W . . . . . . . . . . . . 9340 260 20115
2165 Cap, 10n, 10%, 50V . . . . . . . . . . 5322 126 11583 6175 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2167 Cap, 470p, 5%, 50v, Ceramic. . . . . . 4822 126 13881 6176 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2168 Cap, 100p, 2%, 63V . . . . . . . . . . 4822 122 31765 6177 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2169 Cap, 10n, 10%, 50V . . . . . . . . . . 5322 126 11583 6178 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2170 Cap, 10n, 10%, 50V . . . . . . . . . . 5322 126 11583 6179 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2171 Cap, 220n, +80/-20%, 16v, Ceramic. . . 4822 126 13879 6180 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2173 Cap, 10n, 10%, 50V . . . . . . . . . . 5322 126 11583 6181 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2174 Cap, 100n, +80/-20%, 25v, Ceramic. . . 4822 126 14305 6182 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2175 Cap, 1u, +80/-20%, 10v, Ceramic. . . . 3198 017 41050 6183 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2177 Cap, 10n, 10%, 50V . . . . . . . . . . 5322 126 11583 6184 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2179 Cap, 10n, 10%, 50V . . . . . . . . . . 5322 126 11583 6185 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
2180 Cap, 100n, +80/-20%, 25v, Ceramic. . . 4822 126 14305 6186 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
3135 NTC DC 5W 10k 5% . . . . . . . . . . . 4822 117 12063 6187 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
3136 Res, 4k7, 5%, 1/16W. . . . . . . . . . 4822 051 30472 6188 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
3137 Res, 4k7, 5%, 1/16W. . . . . . . . . . 4822 051 30472 6189 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
3138 Res, 10k, 5%, 1/16W. . . . . . . . . . 4822 051 30103 6190 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
3139 Res, 390 ohm, 5%, 1/16W. . . . . . . . 4822 051 30391 6191 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
3140 Res, 220 ohm, 5%, 1/16W. . . . . . . . 4822 051 30221 6192 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
3141 Res, 4k7, 5%, 1/16W. . . . . . . . . . 4822 051 30472 6193 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621
3142 Res, 47k, 1%, 1/16W. . . . . . . . . . 4822 117 12925 6194 1N4148 . . . . . . . . . . . . . . . . 4822 130 30621