Philips 42pfl7762 LCD CH Lc7.5e La (001-070)
Philips 42pfl7762 LCD CH Lc7.5e La (001-070)
Philips 42pfl7762 LCD CH Lc7.5e La (001-070)
LC7.5E
LA
SUPER NOVA
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041007
©
Copyright 2007 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.
Published by WS 0770 BU CD Customer Service Printed in the Netherlands Subject to modification EN 3122 785 17372
EN 2 1. LC7.5E LA Technical Specifications, Connections, and Chassis Overview
1.1.2 Sound
Y Pb Pr
COMMON INTERFACE TV ANTENNA HDMI 2 HDMI 1
L R EXT. 4
S-VIDEO AUDIO IN
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Note: The following connector colour abbreviations are used 1.2.2 Rear Connections
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy=
Grey, Rd= Red, Wh= White, and Ye= Yellow. Service Connector (ComPair)
1 - SDA-S I2C Data (0 - 5 V) jk
1.2.1 Side Connections 2 - SCL-S I2C Clock (0 - 5 V) j
3 - Ground Gnd H
EXT3: Cinch: Video CVBS - In, Audio - In
Ye - Video CVBS 1 VPP / 75 ohm jq Service Connector (UART)
Wh - Audio L 0.5 VRMS / 10 kohm jq 1 - UART_TX Transmit k
Rd - Audio R 0.5 VRMS / 10 kohm jq 2 - Ground Gnd H
3 - UART_RX Receive j
EXT3: Head phone - Out
Bk - Head phone 32 - 600 ohm / 10 mW rt EXT1: Video RGB - In, CVBS - In/Out, Audio - In/Out
20 2
EXT3: HDMI: Digital Video, Digital Audio - In
19 1
18 2
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Figure 1-2 HDMI (type A) connector
Figure 1-3 SCART connector
1 - D2+ Data channel j
2 - Shield Gnd H 1 - Audio R 0.5 VRMS / 1 kohm k
3 - D2- Data channel j 2 - Audio R 0.5 VRMS / 10 kohm j
4 - D1+ Data channel j 3 - Audio L 0.5 VRMS / 1 kohm k
5 - Shield Gnd H 4 - Ground Audio Gnd H
6 - D1- Data channel j 5 - Ground Blue Gnd H
7 - D0+ Data channel j 6 - Audio L 0.5 VRMS / 10 kohm j
8 - Shield Gnd H 7 - Video Blue 0.7 VPP / 75 ohm j
9 - D0- Data channel j 8 - Function Select 0 - 2 V: INT
10 - CLK+ Data channel j 4.5 - 7 V: EXT 16:9
11 - Shield Gnd H 9.5 - 12 V: EXT 4:3 j
12 - CLK- Data channel j 9 - Ground Green Gnd H
13 - n.c. 10 - Easylink P50 0 - 5 V / 4.7 kohm jk
14 - n.c. 11 - Video Green 0.7 VPP / 75 ohm j
15 - DDC_SCL DDC clock j 12 - n.c.
16 - DDC_SDA DDC data jk 13 - Ground Red Gnd H
17 - Ground Gnd H 14 - Ground P50 Gnd H
18 - +5V j 15 - Video Red 0.7 VPP / 75 ohm j
19 - HPD Hot Plug Detect j 16 - Status/FBL 0 - 0.4 V: INT
20 - Ground Gnd H 1 - 3 V: EXT / 75 ohm j
17 - Ground Video Gnd H
18 - Ground FBL Gnd H
19 - Video CVBS 1 VPP / 75 ohm k
20 - Video CVBS 1 VPP / 75 ohm j
21 - Shield Gnd H
EN 4 1. LC7.5E LA Technical Specifications, Connections, and Chassis Overview
Common Interface
68p - See diagram B03B jk
Aerial - In
- - IEC-type (EU) Coax, 75 ohm D
CONTROL BOARD E
SMALL SIGNAL
B BOARD
LED PANEL J
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CONTROL BOARD E
SMALL SIGNAL
B BOARD
LED PANEL J
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2.3.5 Alternative BOM identification 130606
The third digit in the serial number (example: Figure 2-1 Serial number (example)
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the 2.3.6 Board Level Repair (BLR) or Component Level Repair
specific TV set. In general, it is possible that the same TV (CLR)
model on the market is produced with e.g. two different types
of displays, coming from two different suppliers. This will then
If a board is defective, consult your repair procedure to decide
result in sets which have the same CTN (Commercial Type
if the board has to be exchanged or if it should be repaired on
Number; e.g. 28PW9515/12) but which have a different B.O.M.
component level.
number.
If your repair procedure says the board should be exchanged
By looking at the third digit of the serial number, one can
completely, do not solder on the defective board. Otherwise, it
identify which B.O.M. is used for the TV set he is working with.
cannot be returned to the O.E.M. supplier for back charging!
If the third digit of the serial number contains the number “1”
(example: AG1B033500001), then the TV set has been
manufactured according to B.O.M. number 1. If the third digit is 2.3.7 NVM content
a “2” (example: AG2B0335000001), then the set has been
produced according to B.O.M. no. 2. This is important for If the processor NVM IC is replaced or initialised, the Model
ordering the correct spare parts! Number, Serial Number, and SSB Code number must be re-
For the third digit, the numbers 1...9 and the characters A...Z written to the NVM. ComPair will foresee in a possibility to do
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be this.
indicated by the third digit of the serial number.
2.3.8 Practical Service Precautions
Identification: The bottom line of a type plate gives a 14-digit
serial number. Digits 1 and 2 refer to the production centre (e.g. • It makes sense to avoid exposure to electrical shock.
AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers While some sources are expected to have a possible
to the Service version change code, digits 5 and 6 refer to the dangerous impact, others of quite high potential are of
production year, and digits 7 and 8 refer to production week (in limited current and are sometimes held in less regard.
example below it is 2006 week 17). The 6 last digits contain the • Always respect voltages. While some may not be
serial number. dangerous in themselves, they can cause unexpected
reactions that are best avoided. Before reaching into a
powered TV set, it is best to test the high voltage insulation.
It is easy to do, and is a good service precaution.
4. Mechanical Instructions
Index of this chapter: Notes:
4.1 Cable Dressing • Figures below can deviate slightly from the actual situation,
4.2 Service Positions due to the different set executions.
4.3 Assy/Panel Removal • Follow the disassemble instructions in described order.
4.4 Set Re-assembly
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For easy servicing of this set, there are a few possibilities 4.3.1 Rear Cover
created:
• The buffers from the packaging. Warning: Disconnect the mains power cord before you remove
• Foam bars (created for Service). the rear cover.
• Aluminium service stands (created for Service).
1. Refer to next figures.
Note: the aluminium service stands can only be used when the 2. Place the TV set upside down on a table top, using the
set is equipped with so-called “mushrooms”. Otherwise use the foam bars (see part “Service Positions”).
original stand that comes with the set. 3. Remove rear cover screws [1] and the stand (if mounted).
4. Remove Subwoofer mounting screws [2] (if present).
4.2.1 Foam Bars 5. Lift Subwoofer module, and unplug Subwoofer cable [3].
6. Unplug AmbiLight cables [4] (if present).
7. Remove rear cover.
1
2
1
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The foam bars (order code 3122 785 90580 for two pieces) can Figure 4-5 Rear cover removal (1/3)
be used for all types and sizes of Flat TVs. See figure “Foam
bars” for details.
Sets with a display of 42" and larger, require four foam bars [1].
Ensure that the foam bars are always supporting the cabinet
and never only the display.
Caution: Failure to follow these guidelines can seriously
damage the display!
By laying the TV face down on the (ESD protective) foam bars,
a stable situation is created to perform measurements and
alignments. By placing a mirror under the TV, you can monitor
the screen.
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The MkII aluminium stands with order code 3122 785 90690,
can also be used to do measurements, alignments, and 4
duration tests. The stands can be (dis)mounted quick and easy
by means of sliding them in/out the "mushrooms". The stands
are backwards compatible with the earlier models.
Important: For (older) FTV sets without these "mushrooms", it H_17370_038.eps
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2
2 2
3
1a
2
3
1b
1 2 2
3
2 2
2
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1
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2
Figure 4-9 Keyboard control panel
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4.3.6 Speakers
1. Unplug cables.
2. Remove the fixation screws.
3. Take the board out (it hinges at the left side).
When defective, replace the whole unit.
2 2 2
2 2 2
3 3 3 3
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3 3
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4.3.9 LCD Panel 5. Remove the T20 panel fixation screws [3]. Note that the
number of these screws can vary, depending on the
1. Refer to next figures. screensize.
2. Unplug the connectors [1] on the Main Supply Panel, the 6. Lift he complete central sub-frame from the set [4] (incl. the
display (LVDS connector), Loudspeakers, and the LED/IR PSU, SSB, and Side I/O boards and wiring).
board. 7. After removing the sub-frame, the LCD panel can be lifted
3. Do NOT forget to unplug the LVDS connector from the from the front cabinet.
SSB. Important: Be careful, as this is a fragile connector!
4. Remove T10 parker screws [2] on the top and bottom of the
central sub-frame.
3
3
3 2 3
1 1
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1
3
1
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Notes:
• While re-assembling, make sure that all cables are placed
and connected in their original position. See figure "Cable
dressing".
• Pay special attention not to damage the EMC foams.
Ensure that EMC foams are mounted correctly (one is
located above the LVDS connector on the display, between
the LCD display and the metal sub-frame).
Service Modes, Error Codes, and Fault Finding LC7.5E LA 5. EN 15
In the chassis schematics and layout overviews, the test points Software Identification, Version, and Cluster
(Fxxx) are mentioned. In the schematics, test points are The software ID, version, and cluster will be shown in the main
indicated with a rectangular box around “Fxxx” or “Ixxx”, in the menu display of SDM, SAM, and CSM.
layout overviews with a “half-moon” sign. The screen will show: “AAAABCD X.YY”, where:
As most signals are digital, it will be difficult to measure • AAAA is the chassis name: LC71 for analogue range (non-
waveforms with a standard oscilloscope. Several key ICs are DVB), LC72 for digital range (DVB).
capable of generating test patterns, which can be controlled via • B is the region indication: E= Europe, A= AP/China, U=
ComPair. In this way it is possible to determine which part is NAFTA, L= LATAM.
defective. • C is the display indication: L= LCD, P= Plasma.
• D is the language/feature indication: 1= standard, H=
Perform measurements under the following conditions: 1080p full HD.
• Service Default Mode. • X is the main version number: this is updated with a major
• Video: Colour bar signal. change of specification (incompatible with the previous
• Audio: 3 kHz left, 1 kHz right. software version). Numbering will go from 1 - 9 and A - Z.
– If the main version number changes, the new version
number is written in the NVM.
5.2 Service Modes – If the main version number changes, the default
settings are loaded.
The Service Mode feature is split into four parts: • YY is the sub version number: this is updated with a minor
• Service Default Mode (SDM). change (backwards compatible with the previous versions)
• Service Alignment Mode (SAM). Numbering will go from 00 - 99.
• Customer Service Mode (CSM) and Digital Customer – If the sub version number changes, the new version
Service Mode (DCSM). number is written in the NVM.
• Computer Aided Repair Mode (ComPair). – If the NVM is fresh, the software identification, version,
and cluster will be written to NVM.
SDM and SAM offer features, which can be used by the Service
engineer to repair/align a TV set. Some features are: Display Option Code Selection
• A pre-defined situation to ensure measurements can be When after an SSB or display exchange, the display option
made under uniform conditions (SDM). code is not set properly, it will result in a TV with “no display”.
• Activates the blinking LED procedure for error identification Therefore, it is required to set this display option code after
when no picture is available (SDM). such a repair.
• The possibility to overrule software protections when SDM To do so, press the following key sequence on a standard RC
was entered via the Service pins. transmitter: “062598” directly followed by MENU and “xxx”,
• Make alignments (e.g. white tone), (de)select options, where “xxx” is a 3 digit decimal value of the panel type: see
enter options codes, reset the error buffer (SAM). column “Panel Code” in table “Option Codes OP1...OP7” (ch.
• Display information (“SDM” or “SAM” indication in upper 8), or see sticker on the side/bottom of the cabinet. When the
right corner of screen, error buffer, software version, value is accepted and stored in NVM, the set will switch to
operating hours, options and option codes, sub menus). Stand-by, to indicate that the process has been completed.
PHILIPS
• Decrease the number of nuisance calls. 040
27mm
MODEL:
32PF9968/10
• Solved customers' problem without home visit. PROD.SERIAL NO:
AG 1A0620 000001
(CTN Sticker)
Specifications
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Region Freq. (MHz) Default syst. 260107
Note:
• If the TV is switched “off” by a power interrupt while in SDM,
the TV will show up in the last status of SDM menu as soon
SDM as the power is supplied again. The error buffer will not be
cleared.
• In case the set is in Factory mode by accident (with “F”
displayed on screen), by pressing and hold “VOL-“ and
“CH-” together should leave Factory mode.
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5.2.3 Service Alignment Mode (SAM) uploading via ComPair. Read paragraph “Service Tools” -
> “ComPair”. Caution: When this mode is selected without
Purpose ComPair connected, the TV will be blocked. Remove the
• To change option settings. AC power to reset the TV.
• To display / clear the error code buffer. 12. SW Events. Only to be used by development to monitor
• To perform alignments. SW behaviour during stress test.
C S M
1 0 T U N E R : WE A K / G O O D / S T R O NG
1 1 S Y S T E M: P A L / NT S C / S E C A M
1 2 S O U N D : MO N O / S T E R E O / NI C A M
1 3
1 4 H D A U : YES/N O
1 5 F O R M A T : X X X X X X X X
1 6 L. T. : xxxxxx
1 7 F P G A F W : xx.xx.xx
1 8 :
PAGE UP :B
y
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Purpose
The Digital Customer Service Mode shows error codes and
information on the IBO Zapper module (DVB reception part)
operation settings. The call centre can instruct the customer to
activate DCSM by telephone and read off the information
displayed. This helps the call centre to diagnose problems and
failures in the IBO Zapper module before making a service
call.The DCSM is a read-only mode; therefore, modifications
are not possible in this mode.
How to Activate
To activate the DCSM, put the television in its digital mode (via
the “A/D” button on the remote control).
1. Press the “Digital Menu” button on the remote control to
activate the digital user menu (called “Setup”). E_14970_042.eps
2. Activate the “Information” sub menu (via the “down” and 090904
“right” cursor buttons).
3. In the “Information” sub menu, press the following key Figure 5-9 DCSM menu - 3
sequence on the remote control to activate the DCSM:
“GREEN RED YELLOW 9 7 5 9” (do not allow the display 1. Hardware version: This indicates the version of the IBO
to time out between entries while keying this sequence). Zapper module hardware.
Then, the “Service menu” will appear (see figures below). 2. Application SW: The application software version.
3. NOR Version: The NOR Flash image software version
Alternative method to activate DCSM: press key sequence 4. Digital Frequency: The digital frequency that the set is
“123654” on the remote control transmitter while in digital mode tuned to.
(do not allow the display to time out between entries while 5. Bit Error Rate: The error rate measured before the error
keying the sequence). Then, the “Service menu” will appear correction algorithm circuitry. (this value gives an
(see figures below). impression of the received signal)
6. Tuner AGC: Tuner AGC value.
Menu explanation 7. COFDM Lock: Indication if COFDM decoder is locked.
8. AFD Status: Status of the Active Picture Format
Descriptor.
9. Terrestrial Delivery System Parameters:
– Bandwidth: Bandwidth of the received signal.
– Constellation Pattern: Displays the signal
constellation.
– Alpha Value: Displays the Alpha Value.
– FEC Scheme: Displays the Forward Error Correcting
Scheme
– Guard Interval: Displays the value for the Guard
Interval.
– Transmission Mode: Displays the Transmission
Mode.
10. Audio Comp Type: Type of detected audio stream.
11. MHEG Present: Indicates if MHEG is present or not.
12. CIM Card Present: Indicates if CIM card is present or not.
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How to exit
Press the BLUE button on the Remote Control to exit DCSM.
Figure 5-7 DCSM menu - 1
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5.3 Service Tools • ComPair UART interface cable: 3138 188 75051 (to be
used with chassis LC7.5).
5.3.1 ComPair
Note: If you encounter any problems, contact your local
support desk.
Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips
Consumer Electronics products. and offers the following: 5.3.2 LVDS Tool
1. ComPair helps you to quickly get an understanding on how
to repair the chassis in a short and effective way. Support of the LVDS Tool has been discontinued.
2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. You do not
have to know anything about I2C or UART commands
yourself, because ComPair takes care of this.
3. ComPair speeds up the repair time since it can
automatically communicate with the chassis (when the uP
is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.
Specifications
ComPair consists of a Windows based fault finding program
and an interface box between PC and the (defective) product.
The (new) ComPair II interface box is connected to the PC via
an USB cable. For the TV chassis, the ComPair interface box
and the TV communicate via a bi-directional cable via the
service connector(s).
How to Connect
This is described in the ComPair chassis fault finding database.
TO TV
TO TO TO
UART SERVICE I2C SERVICE UART SERVICE
CONNECTOR CONNECTOR CONNECTOR
ComPair II
Multi
RC in function
RC out
PC
Optional power
HDMI 5V DC
I2C only
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How to Order
ComPair II order codes:
• ComPair II interface: 3122 785 91020.
• ComPair32 CD (update): 3122 785 60160.
• ComPair I2C interface cable: 3122 785 90004 (to be used
with chassis L01, A02, A10, EMX, ...).
• ComPair I2C interface extension cable: 3139 131 03791 (to
be used with chassis L01, A02, A10, L04, LC4, LC7.1,
LC7.2).
• ComPair UART interface cable: 3122 785 90630 (to be
used with chassis LC4, EJ3, BJ2, BL2, BP2, ...).
• ComPair RS232 cable: 3104 311 12742 (to be used with
chassis Q52x).
• ComPair I2C adapter cable: 3122 785 90004 (to be used
with chassis TPM1.xA).
• ComPair I2C interface cable: 9965 100 07325 (to be used
with chassis LC7.5).
Service Modes, Error Codes, and Fault Finding LC7.5E LA 5. EN 21
results in other error codes (cause and effect), only the error 11 I2C error while communicating 7N01
with the HDMI IC.
code of the MAIN failure is displayed.
12 I2C error while communicating 7H03 if applicable
with the MOJO PNX8314.
Example: In case of a failure of the I2C bus (CAUSE), the error 13 DVB HW communication 7F01, if applicable
code for a “General I2C failure” and “Protection errors” is error. 7K00,
displayed. The error codes for the single devices (EFFECT) is 7H03
not displayed. All error codes are stored in the same error 14 SDRAM defective. 7D02
buffer (TV’s NVM) except when the NVM itself is defective. 15 I2C error while communicating 7F01
with the IBO COFDM channel
decoder.
5.4.2 How to Read the Error Buffer 16 I2C error while communicating 7H03
with the IBO NVM.
You can read the error buffer in 3 ways: 17 I2C error while communicating 7700 or
• On screen via the SAM/SDM/CSM (if you have a picture). with FPGA external
– ERROR: 6 0 0 0 0 : Error code 6 is the last and only 20 I2C error while communicating 7K00
with the IBO PCMCIA
detected error controller.
– ERROR: 9 6 0 0 0 : Error code 6 was detected first and 21 I2C error while communicating 7M07
error code 9 is the last detected (newest) error with the HDMI mux IC
• Via the blinking LED procedure (when you have no 22 I2C error while communicating
picture). See “The Blinking LED Procedure”. with the HDMI buffer in Side A/
• Via ComPair. V Panel
23 Reserved.
Note: If you exit SAM by disconnecting the mains from the 5.6 Software Upgrading
television set, the error buffer is not reset.
In this chassis, three SW “stacks” are used:
5.5 The Blinking LED Procedure • TV mains SW (processor and processor NVM).
• Digital TV SW (IBO Zapper).
5.5.1 Introduction
5.6.1 TV Main SW Upgrade
The software is capable of identifying different kinds of errors.
Because it is possible that more than one error can occur over For instructions on how to upgrade the TV Main software, refer
time, an error buffer is available, which is capable of storing the to ComPair.
last five errors that occurred. This is useful if the OSD is not
working properly. 5.6.2 “Digital TV” Software Upgrade
Errors can also be displayed by the blinking LED procedure. How to Upgrade Philips “Digital TV” Software (IBO Zapper):
The method is to repeatedly let the front LED pulse with as
many pulses as the error code number, followed by a period of Preparation of the Memory Device for Software Upgrade
1.5 seconds in which the LED is “off”. Then this sequence is For the procedure you will require:
repeated. 1. A personal computer with web browsing capability.
2. An archive utility that supports the ZIP-format (e.g. Winzip
Example (1): error code 4 will result in four times the sequence for Windows).
LED “on” for 0.25 seconds / LED “off” for 0.25 seconds. After 3. A CompactFlash PC Card Adapter (Type II).
this sequence, the LED will be “off” for 1.5 seconds. Any RC5 4. A CompactFlash (Type I) portable memory card for
command terminates the sequence. Error code LED blinking is insertion into the PC Card Adapter. Philips recommends
in red colour. using Compact Flash (CF) portable memory cards with
their respective PC Card Adapters (Sandisk or Kingston)
Example (2): the content of the error buffer is “12 9 6 0 0” with memory sizes of up to 256MB. Philips does not
After entering SDM, the following occurs: guarantee that other types of portable memory cards and
• 1 long blink of 5 seconds to start the sequence, their respective PC Card Adapters, including multi-card PC
• 12 short blinks followed by a pause of 1.5 seconds, Card Adapters work on Philips Digital TV.
• 9 short blinks followed by a pause of 1.5 seconds, Note: Only FAT16-formatted portable memory is
• 6 short blinks followed by a pause of 1.5 seconds, supported. NTFS & FAT32 are not supported.
• 1 long blink of 1.5 seconds to finish the sequence,
• The sequence starts again with 12 short blinks.
Copying of Software Image Files to the Flash Device
Copy the appropriate “FCL.img” and “IBOZ.img” to the root
5.5.2 Displaying the Entire Error Buffer directory of the flash device.
Additionally, the entire error buffer is displayed when Service Verifying the Current Version of the TV Software
Mode “SDM” is entered. In case the TV set is in protection or Before you start the software upgrade procedure, it is advised
Stand-by: The blinking LED procedure sequence (as in SDM- to check what the current TV software is. The current TV
mode in normal operation) must be triggered by the following software version can be seen in the “System software” menu.
RC sequence: “MUTE” “062500” “OK”. 1. First press the “A/D” key and then the “DIGITAL MENU”
In order to avoid confusion with RC5 signal reception blinking, key on the remote controller to access the “Setup” menu.
this blinking procedure is terminated when a RC5 command is 2. Access the “Information” menu.
received. 3. Access the “Current software version” menu.
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The TV will reset and the screen will go blank, after a few
seconds a dialogue box will occur to inform you that the current
module inserted in the CI slot is not recognized. This is normal
as the slot only recognizes a Conditional Access Module during
normal operation.
It is possible to download default values automatically into the On the next pages you will find start-up and shut-down
NVM in case a blank NVM is placed or when the NVM first 20 flowcharts, which might be helpful during fault finding.
address contents are "FF". After the default values are Please note that some events are only related to PDP sets,
downloaded, it is possible to start-up and to start aligning the and therefore not applicable to this LCD chassis.
TV set. To initiate a forced default download the following
action has to be performed:
1. Switch “off” the TV set with the mains cord disconnected
from the wall outlet (it does not matter if this is from "Stand-
by" or "Off" situation).
2. Short-circuit the SDM jumpers on the SSB (keep short
circuited).
3. Press “P+” or “CH+” on the local keyboard (and keep it
pressed).
4. Reconnect the mains supply to the wall outlet.
5. Release the “P+” or “CH+” when the set is “on” or blue LED
is blinking.
When the downloading has completed successfully, the set
should be into Stand-by, i.e. red LED on.
Service Modes, Error Codes, and Fault Finding LC7.5E LA 5. EN 25
V1.5 AC ON
LC07S
Start Up 13 June 2007
InitCold Component:
Error 6 - NVM 1. Check SDM port.
[Protection] - If SDM pin = LOW and NVM first 20Byte = 0xFF,
reload Software default NVM value.
2. Check Panel port.
- If Panel Pin = LOW and check slave address
0x65 = 0xA5, Enter Panel Mode.
HDMI_MUX_RST
Reset (LOW =150ms) then go to HIGH
For LCD:
Enable Audio Mute ( 50ms) BL_ON_OFF = HIGH
50ms STANDBYn = HIGH * BL_ADJ keep 100% for 1000ms
(Same function as CTRL-DISP3) For PDP:
then reduce gradually to 70% from
3000ms delay
1001ms to 3000ms .After 3000ms
* 100ms for 12V rising 100ms Wait for 100ms do the dimming according to
picture content.
Error 19 – 1080P
STANDBYn = LOW Enable RC Key
Standby
Normal Mode DVB recording mode H_17370_056.eps
090807
Start
SEMISTANDBY/ STANDBY
BL_ADJ
(PWM duty cycle 70%)
BL_ON_OFF = LOW
LCD_PWR_ON = LOW
Software Shutdown:
Standby using
LED = RED No
“power key”
WP for NVM
(ANTI_PLOP =HIGH)
(Mute_n = LOW)
Enable Audio Mute
Port Assignment in STANDBY Sets go to standby here
Total = 360ms
H_17370_057.eps
End 090807
Start
Power Down INT:
AC OFF or Transient INT
Avoid false trigger
Poll the Power Down
No
INT for 5 times
Yes
End
Mute Audio & VIdeo
Notes:
1. Power Down INT will based on fall edge triggering
2. +3V3STBY will stay for 15ms, software must perform WP for NVM within 15ms. WP for NVM
STANDBYn = LOW
Wait 5000 ms
Re-start: Start up
End
DC_PROT INT
Start
Yes
End
Mute Audio & VIdeo
WP for NVM
STANDBYn = LOW
End H_17370_058.eps
090807
Personal Notes:
E_06532_012.eps
131004
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 29
CN6
(5226)
9P
8B12
14. GND1
CN2
14P
8R01
CN3
CN7
8P
8B13
DISPLAY SUPPLY
1. +24VI
CN3
12P
2. +24VI
8319
8305
3. +24VI 8304
4. +24VI
CN2
14P
CN3
7. GND3
12P
ONLY USED
8316
FOR LPL PANEL
8. GND3
9. GND3 SSB
B (1150)
10. GND3
11. N.C.
INVERTER INVERTER
12. N.C.
CONTROL
CN6
CONTROL:
1. -12V(audio)
2. +12V(audio)
1N01
21P
E KEYBOARD
3. GND2(audio)
TUNER
4. 5.2VS
5. 5.2VS
6. 5.2VS D SIDE I/O
(1116)
CN1
2P3
(1114)
7. GND1
8. GND1
1R04
11P
8R04
9. GND1
1Q02
8308
10P
1M01
CN7
3P
CONTROL:
INLET
1. BL-ADJUST
1Q03
21P
8N01
8M01
2. PG
3. BL_ON_OFF
4. GND1
5. BOOST
8192(UK)
8M20 7P 3P
8191
H_17371_001.eps
171007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 30
4P 4P 30P
4P7
CN6
(5226)
9P
8B12
14. GND1
1M59
CN2
14P
5P
8R01
AMBI-LIGHT UNIT
CN3
CN7
8P
8B13
1M82
DISPLAY SUPPLY
7P
1. +24VI
CN3
2. +24VI 12P
8319
8305
3. +24VI 8304
4. +24VI
CN2
14P
MAIN SUPPLY
(IN BACK COVER)
CN3
7. GND3
12P
ONLY USED
8316
FOR LPL PANEL
8. GND3
9. GND3 SSB
B (1150)
10. GND3 INVERTER
INVERTER
11. N.C.
12. N.C.
1M82
AMBI-LIGHT UNIT
4P7
CONTROL
CN6
1M59
CONTROL:
5P
1. -12V(audio)
2. +12V(audio)
1N01
21P
E KEYBOARD
3. GND2(audio)
TUNER
1M09
4. 5.2VS
4P
5. 5.2VS
6. 5.2VS D SIDE I/O
(1116)
CN1
2P3
(1114)
7. GND1
8. GND1
1R04
11P
8R04
9. GND1
1Q02
8308
10P
1M01
CN7
3P
CONTROL:
1. BL-ADJUST INLET
1Q03
21P
8N01
8M01
2. PG
3. BL_ON_OFF
4. GND1
5. BOOST 8192(UK)
8M20 7P 3P
8191
H_17371_002.eps
171007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 31
LCD DISPLAY
(1004)
LVDS
51P
8316
8319 8R03
8B12
8B13
8P 14P 12P
9P X406 X404 X403
4P
X412
X405
4P
X411 TO SUBWOOFER
IN BACK COVER
(5226)
MAIN SUPPLY
(1005)
CN2
14P
8305
8304
CN3
12P
6P 8P 10P 5P 41P 3P 7P 11P 3P 4P
1B12 1B13 1305 1201 1R01 1A02 1L20 1304 1A03 1A01
INVERTER INVERTER
B SSB
(1150)
CONTROL
1N01
21P
E KEYBOARD
X101
2P3
D SIDE I/O
(1116)
(1114)
8308
1R04
11P
8R04
INLET
1Q02
10P
1M01
3P
1Q03
21P
8N01
8M01
8192(UK)
8191
8M20 7P 3P
LEFT SPEAKER 1M20 1M01
RIGHT SPEAKER
(5215) (5213) (5213) (5215) IR/LED/LIGHT
J SENSOR
(1112)
H_17371_003.eps
021007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 32
8M82
8M59
8M09 8M09
LCD DISPLAY
LVDS
51P
8316
8319 8R03
8B12
8321
8B13
8P 14P 12P
1M09
9P
4P
X412
X405
4P
X411 TO SUBWOOFER
1M59
5P
IN BACK COVER
(1175)
(5226)
1M82
4P7
MAIN SUPPLY
(1005)
CN2
1M82
14P
4P7
8305
8304
AMBI-LIGHT UNIT (IN BACK COVER)
CN3
1M59
12P
5P
6P 8P 10P 5P 41P 3P 7P 11P 3P 4P
INVERTER 1B12 1B13 1305 1201 1R01 1A02 1L20 1304 1A03 1A01
1M09
4P
B SSB
(1150) INVERTER
CONTROL
1N01
21P
E KEYBOARD
(1175)
X101
2P3
D SIDE I/O
(1116)
(1114)
8308
1R04
11P
8R04
INLET
1Q02
10P
1M01
3P
1Q03
21P
8N01
8M01
8192(UK)
8191
8M20 7P 3P
LEFT SPEAKER 1M20 1M01
RIGHT SPEAKER
(5215) (5213) (5213) (5215)
IR/LED/LIGHT
J SENSOR
(1112)
H_17371_004.eps
181007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 33
9P 8P
14P 12P CN6 CN7
CN2 CN3
TO SUBWOOFER
ON BACK COVER
(5226)
MAIN SUPPLY
(1005)
CN2
14P
8305
8304
CN3
12P
6P 8P 10P 5P 41P 3P 7P 11P 3P 4P
1B12 1B13 1305 1201 1R01 1A02 1L20 1304 1A03 1A01
INVERTER INVERTER
SSB
B (1150)
CONTROL
1N01
21P
E KEYBOARD
CN1
2P3
D SIDE I/O
(1116)
(1114)
8308
1R04
11P
8R04
INLET
1Q02
10P
1M01
3P
1Q03
21P
8N01
8M01
8192(UK)
8191
8M20 7P 3P
LEFT SPEAKER 1M20 1M01
RIGHT SPEAKER
(5215) (5213) (5213) (5215)
IR/LED/LIGHT
J SENSOR
(1112)
H_17371_005.eps
021007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 34
SDA
SCL
11
DVB_SW 7114
B04
EF
B03A DVB-DEMODULATOR B03B DVB-COMMON INTERFACE B03C DVB-MOJO B03E DVB-MOJO B05A TRIDENT - WX68 B05E FPGA I/O BANKS B07E LVDS CONNECTOR
ANALOG BACK END
7F01 7K00 7G00
TDA10046AHT PNX8314HS/C102 7C01
STV0700L
SVP WX68-7568-LF
COFDM 62
CHANNEL 61
PCMCIA MOJO CVBS_RF Y4
CVBS1
DECODER 2
CONTROLLER ADC
ADC 5J52
(PARALLEL)
C
TDA_DAT(0-7) TS_DATA(0-7) 163 B|Pb 5J54 IBO_B_IN W10
PC_B
(TS) B
(AV)
165 G|Y 5J53 IBO_G_IN Y7 PC_G
PROCESSOR 1R01
35 TDA_SYNC 49 62 TS_SYNC G 41
30 167 R|Pr 5J55 IBO_R_IN U8 PC_R
R +VDISP
21 1 40
TS
39
INTERFACE
7F04 38
COMP_OUT
B07B IO - SCART 1 & 2 ANALOG 4713 TxLVDSe_0n 1R02 LVDSe_0n 32
A14 TxFPGAe_0n
RF_AGC_IBO MUX
B02 1504 7503 B14 TxFPGAe_0p 4714 TxLVDSe_0p LVDSe_0p 31
3535 EF 3537 SC1_RF_OUT_CVBS
19 W2 TA1 4715 TxLVDSe_1n 1R03 LVDSe_1n 30
CVBS_OUT1 A15 TxFPGAe_1n
B15 TxFPGAe_1p 4716 TxLVDSe_1p LVDSe_1p 29
15 3528 SC1_R_IN W8
1K00 PR_R2 4717
3523 TB1 A16 TxFPGAe_2n TxLVDSe_2n 1R04 LVDSe_2n 28
11 SC1_G_IN W6 Y_G2
3516 B16 TxFPGAe_2p 4718 TxLVDSe_2p LVDSe_2p 27
7 SC1_B_IN Y9 PB_B2
A_MDO(0-7) 1 3545 TxFPGAe_CLKn 4725 TxLVDSe_CLKn 1R05 LVDSe_CLKn 25
20 SC1_CVBS_IN Y10 LVDSTC1 A18
PB_B3 OUT 4716
3528 Y5 B18 TxFPGAe_CLKp TxLVDSe_CLKp LVDSe_CLKp 24
16 SC1_FBL_IN
FB1
3518 A19 TxFPGAe_3n 4719 TxLVDSe_3n 1R06 TxLVDSe_3n 22
8 SC1_STATUS
PCMCIA 68P B04 TCLK1 4720
B19 TxFPGAe_3p TxLVDSe_3p TxLVDSe_3p 21
EXT1 B17 TxFPGAe_4n 4721 TxLVDSe_4n 1R07 TxLVDSe_4n 20
LVDS
A_MDI(0-7) 1506 7500 4722 RES TxLVDSe_4p 19
CONDITIONAL TD1 A17 TxFPGAe_4p TxLVDSe_4p CONNECTOR
19 3522 EF 3521 SC2_CVBS_MON_OUT
ACCESS V2 CVBS_OUT2 TO FULL HD
DISPLAY
H19 TxFPGAo_0n 4703 TxLVDSo_0n 1R08 TxLVDSo_0n 17
21
3529 SC2_Y_CVBS_IN TxFPGAo_0p 4704 16
2x SCART 20 V8 G20 TxLVDSo_0P TxLVDSo_0P
PR_R3
3552 G19 TxFPGAo_1n 4705 TxLVDSo_1n 1R09 TxLVDSo_1n 15
15 SC2_C_IN W4
FS2 4706 14
F20 TxFPGAo_1p TxLVDSo_1p TxLVDSo_1p
8 3550 SC2_STATUS
B04 E19 TxFPGAo_2n 4707 TxLVDSo_2n 1R10 TxLVDSo_2n 13
D20 TxFPGAo_2p 4708 TxLVDSo_2p TxLVDSo_2p 12
EXT2
B20 TxFPGAo_CLKn 4723 TxLVDSo_CLKn 1R11 TxLVDSo_CLKn 10
BO7D HDMI SWITCH B07A YPBPR & SVHS 4724
1615 A20 TxFPGAo_CLKp TxLVDSo_CLKP TxLVDSo_CLKP 9
3617 HD_Pr_IN Y8 4709 1R12
D19 TxFPGAo_3n TxLVDSo_3n TxLVDSo_3n 7
Pr PR_R1
C20 TxFPGAo_3p 4710 TxLVDSo_3p TxLVDSo_3p 6
3618 HD_Y_IN V6
Y Y_G1 F19 TxFPGAo_4n 4711 TxLVDSo_4n 1R13 TxLVDSo_4n 5
E20 TxFPGAo_4P 4712 TxLVDSo_4p RES TxLVDSo_4p 4
1601
3619 HD_Pb_IN W9
7M07 Pb PB_B3
SII9185ACTU
7601
1M01
1601 NC
1 FRONT_CVBS_SVHS_Y_IN Y6
RX2+A 28 + 1 COM Y_G3
3 Y_IN
3 RX2-A 27 - R0X2 NO FRONT_CVBS_SVHS_SEL
S VIDEO 5 B04
4 RX1+A 25 + 4 C_IN V9
2 C
24 - R0X1
1
6
2
RX1-A
7 RX0+A 22 + D2 SIDE I/O B04 MICROPROCESSOR
9 RX0-A 21 - R0X0 1302
10 RXC+A 19 + 1R04 1304
18
19
6 ODCK 3 7D01
2
9 RX0-B 6 20 57 - R1XC
2
(MAIN) 19 Y20
19
6
2
HDMI-MUX_TX1+
19
12 RXC-C 58 - R2XC + 4 48 +
TX1
- 5
HDMI-MUX_TX1- 47 - R0X1
19 HPD_RESET_C 56
+ 1 HDMI-MUX_TX2+ 70 +
HDMI TX2
- 2 HDMI-MUX_TX2- 69 - R0X2
CONNECTOR H_17371_006.eps
021007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 35
6103
INTERCARRIER MIXER AND
10
9
11
12 RF_AGC_IBO AM-DEMODULATOR
B03A 4 SIF2 24 SIF2
14
SIF AGC MAD 1A02
IF_AGC_IBO 13 RF_AGC 14 TAGC
I2C-BUS TRANSCEIVER
1
VIM_IBO
VIP_IBO
SDA
SCL
DVB_SW 11 SAW_SW WOOFER
B04 B04 3
B03A DVB-DEMODULATOR B03B DVB-COMMON INTERFACE B03C DVB-MOJO B06A AUDIO PROCESSOR
7F01 7K00 7G00 7411
TDA10046AHT STV0700L PNX8314HS/C102 MSP4450K-VK-E8-001 Y
62 MOJO 7A01
PCMCIA SIF 63
ANA-IN1+ TDA8932T 1A01
61 CONTROLLER
27 AUDIO-LS_L 3A03 2 27 5A03 1
COFDM 2 DACM-L
ADC MOJO_I2S_OUT_SD LEFT
CHANNEL 202 20
DA3 26 AUDIO-LS_R 3A11 14
2 SPEAKER
DECODER DACM-R
MOJO_I2S_OUT_SCK 17
CLASS D
TDA_DAT(0-7) TS_DATA(0-7) (TS) (AV) 203 CL3 POWER 3
MOJO_I2S_OUT_WS
SOUND
204 18
WS3 STANDBYn 3A19 AMPLIFIER RIGHT
TS PROCESSOR B04
6
22 5A04 4 SPEAKER
INTERFACE 67 3A26
XTALIN ENGAGE 5
12
B07B I0 - SCART 1 & 2 13 +5V_D
1K00 SUPPLY 7A05÷7A07
1411 68 61
XTALOUT +5V_AUD
18M432 62 DC_PROT
1504 SC1_AUDIO _MUTE_R B04 DC-DETECTION
B06C
1 SC1_AUDIO _OUT_R 80
A_MDO(0-7) 36
SC1-OUT-R 38
2x SCART 2 SC1_AUDIO_IN_R 55 +8V
SC1-IN-R 39
1 3 SC1_AUDIO _OUT_L 37 40
SC1-OUT-L
PCMCIA 68P 6 SC1_AUDIO_IN_L 54
SC1-IN-L
SC1_AUDIO _MUTE_L
B06C
EXT1
A_MDO(0-7) B06C HEADPHONE AMP & MUTING B04 MICRO D2 SIDE I/O
CONDITIONAL
1506 SC2_AUDIO _MUTE_R
ACCESS B06C PROCESSOR
1 SC2_AUDIO _OUT_R 33
SC2-OUT-R
2 SC2_AUDIO_IN_R 53
SC2-IN-R
3 SC2_AUDIO _OUT_L 34
21 SC2-OUT-L 7901
6 SC2_AUDIO_IN_L 52 1304 1R04 1R03
SC2-IN-L HP_AUDIO_OUT_L HP_LOUT 10 10 HEAD_PH_L
SC2_AUDIO _MUTE_L 24 2
B06C DACA-L
EXT2
23 HP_AUDIO_OUT_R HP_ROUT 11 11 HEAD_PH_R 3
DACA-R
B07A YPBPR & SVHS 5 HEADPHONE
1615
SC1_AUDIO _MUTE_R EXT3
COMP_AUDIO_IN_L COMP_AUDIO_IN_L 50 ANTI_PLOP
SC3-IN-L B04
AUDIO SC1_AUDIO _MUTE_L
EXT4 MUTING
L/R IN COMP_AUDIO_IN_R COMP_AUDIO_IN_R 51 SC2_AUDIO _MUTE_R B07B
SC3-IN-R
SC2_AUDIO _MUTE_L
POWER_DOWN
B04
CONTROL
D1 SIDE HDMI 7Q03 D2 SIDE I/O B04A MICROPROCESSOR MUTEn
B04
SII9181CNU
1R20 1R04 1304
HDMI L_FRONT_IN 6 6 SIDE_AUDIO_IN_L 48
1
SC4-IN-L
2
BUFFER AUDIO
RX EXT3
L/R IN R_FRONT_IN 8 8 SIDE_AUDIO_IN_R 49
SC4-IN-R
HDMI-SIDE
18
19
SII9125CTU UDA1334ATS
RX-A R0X
1M02 HDMI AUDIO
HDMI
18
(MAIN) DAC
19
(OPTIONAL) SWITCH
1
R1X
2
VOUTR SC5-IN-R
19
SD DATAI
1
R0X
2
TX HDMI-MUX
RX-C R2X 75 8
MUTE MUTE
18
19
7700
EP2C5F256C7N 1204
1101 7D01 7C01
7F01 TD1316AF/IHP-2 SVP WX68-7568 H2 CLK_OSC1
K4D261638K 7C02 TXFPGAe_CLKn J16
TDA10046AHT/C1 7201
7C04 TXFPGAe_CLKp J15 EPCS4I8 27M
MAIN FPGA
G17 BL_ADJUST F4 nCSO
SDRAM CONTROL B01A TXFPGAo_CLKn
1 TUNER H15 H4 DCLK
2Mx16x4 SCD
7F04 (HYBRID) TXFPGAo_CLKp H16 C3 ASDO
7111 DQ(0-31)
7G00 F1 DATA0
21 COMP_OUT
RF_AGC_IBO 12 PNX8314HS/C102
COFDM 2 6 B07E LVDS CONNECTOR
14 44 1R01
CHANNEL
13 7D02 B17 TXFPGAe_CLKn TxLVDSe_CLKn 25
DECODER 11 DVB_SW B04
K4D261638K
7F03 A17 TXFPGAe_CLKp TxLVDSe_CLKp 24
TO DISPLAY
54 4MHZ_CLK
1
7F02
MOJO WX_MA(0-11) VIDEO F19 TXFPGAo_CLKn TxLVDSo_CLKn 10 (LVDS)
1
2
35 TS_DATA(0-7) + 11
A_MDO(0-7) RXxxA R0X PROCESSOR
- 11 28
HDMI +3V3_STBY
18
19
HDMI_Y(0-7) 1312
63 TS_CLK 29 SWITCH
MUX 7312 9 ITV_SPI_CLK 6
62 TS_SYNC 30
1
2
A_MDI(0-7) + BD45275G
61 TS_VALID 28 RXxxB R1X 8 ITV_SPI_DATA_IN 5
- HDMI_Cr(0-7) 5 4
VOUT
18
19
A_MICLK 110 (3V3)
20
2,3 ITV_CONNECTOR A
1
15 MIU_RDY
2
A_MOCLK 118 109 +
57 61 CS 45
7K04 RXxxC R2X
- WR 74 ANTI_PLOP
MIU_ADDR(15-24) 62 44
18
B06C
19
35 63 RD 42
HDMI 75 BL_ON_OFF
27M 84 ALE_EMU 38 B01A
CONNECTOR
86 RST_H 4 72 POWER_DOWN
B06C
7K03 56 INT 18
78 MUTEn
PCMCIA 68P 76 HDMI_HOTPLUG_RESET 89 B06C
BUFFERING
PCMCIA_D(0-7) MIU_DATA(0-7) (MIU) 100 HDMI_RST_RX_BUF 5
88 RST_AUD
CONDITIONAL B06A
ACCESS 35 HDMI_INT_MUX 73
7K01 13 HDMI_RST_MUX 36
BUFFERING
PCMCIA_A(0-7) MIU_ADDR(0-7) MIU_ADDR(0-24) 4 RESET_n 3L11 IBO_RESET 2
73 FRONT_CVBS_SVHS_SEL
B07A
B03D FOR DVB ONLY
4 RSR_H
180 IB0_IRQ 16 B05A
7K01
3L79
K4S281632I-UC60
3L56 4301 SDM
25
6011 3013
SDRAM_CLK 136 7012
38 +5V_STANDBY
LED2 LED2 4 4 LED2 87
SYNC RED
SDRAM
SDRAM_DATA(0-15) (SDRAM) 7010
4x2Mx16 3010
RC 3 3 REMOTE 18
+5V_STANDBY
SDRAM_ADDR(0-14) IR
SENSOR
1 1 LIGHT_SENSOR 2
N.C.
H_17371_008.eps
021007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 37
Part 1
H_17370_025a.eps
070804
H_17370_025a.eps
070804
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 39
Part 2
H_17370_025b.eps
070804
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 40
Part 3
H_17370_025c.eps
070804
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 41
Part 4
H_17370_025d.eps
070804
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 42
I2C Overview
I²C
B04 MICROPROCESSOR B03C DVB-MOJO B06A AUDIO PROCESSOR B02 TUNER IF & DEMODULATOR B05A TRIDENT - WX68 B05B DDR & CPU INTERFACE
+3V3_STBY +3V3SW
7302
3L75
3360
3L76
3359
PCA9515ADP
28 3382 IIC_SDA_up 3 6 IIC_SDA
SDA2
27 3L62 IIC_SCL_up IIC_SCL
SCL2 2 7
3152
3151
3C08
3C09
3411
3410
3L54
3355
+3V3SW
ERR
7311 04 5 6 3 2 10 11 H17 H18
7303 7D01
M30300SAGP
3361
K4D261638K
3362
PCA9515ADP
MICRO 7L23 7411 7113 7C01
3 6 IIC_SDA_SIDE SDRAM
PROCESSOR M24C64 MSP4450P TDA9886T/V4 SVP WX68
8Mx16
7310 IIC_SCL_SIDE
MX29LV800CTTI EEPROM 2 7 SOUND DEMODULATOR TRIDENT ERR
10
(NVM) PROCESSOR
3G47
3G46
DATA EPROM 1314 7D02
1Mx8/ 3343 1305
2 9 8 K4D261638K
512kx16 ERR COMPAIR 3 TO 1Q02 ERR ERR ERR
06 SERVICE 09 08 05
ADDR 3345 D1 7G00 SDRAM
3 CONNECTOR 2 SIDE I/O
PNX8314HS 8Mx16
ERR
MOJO 14
3H12
3H13
74HCT4053D
3G44 I2C_LOCAL_SDA
P2 H1 7
+3V3_FPGA
3G43 1
6 I2C_LOCAL_SCL
7700
3
3K01
3K00
3H09
3H10
3F40
3F44
15
3204
EP2C5F256C7N
3203
1201 +5V_SW
3 3206 AMBI_SDA N2 ERR +5V_SW
FPGA 13 5 6 30 31 8 6 4
1 3205 AMBI_SCL P3
5120
5121
3F42
3F41
3H11
7H03 7K00 7F01
2 user_EEPROM_WP M24C64 STV0700L TDA10046AHT 4 3F46 I2C_TDA_SDA 2
ERR
185 7 5 4
17 3F48 I2C_TDA_SCL
EEPROM PCMCIA COFDM 3 5
8Kx8 CONTROLLER CHANNEL 1101
TO AMBI-LIGHT 7H00 TD1316AF/IHP
MODULE DECODER
M29W320ET70
(ONLY FOR AMBI-LIGHT SET) (ONLY FOR AMBI-LIGHT SET)
11 TUNER
B07D HDMI SWITCH B07C HDMI MAIN DATA NOR ERR ERR ERR DVB_SW
+5VHDMI_C 16 20
3M21
3M20
FLASH 15 B04A
+5VHDMI_B 2/4/8MB
+5VHDMI_A ERR
14 15 ADDR
3M39
3M40
07
3M37
3M38
3M35
3M36
7M07
1M01
3N40
3N39
SII9185CTU 7H02
16 DOC_SDAA 30 K4S281632I
1
2
+3V3_ANA-MUX
HDMI 26 27
15 DOC_SCLB 31 DATA SYNC
SWITCH
18
DRAM
3N35
19
3N36
7N01
1M02 SII9125CTU 4x2Mx16
16 DOC_SDAB 50 ERR ADDR
1
2
21 77 HDMI-MUX_SDA 33
HDMI
15 DOC_SCLB 51 HDMI-MUX_SCL MAIN
78 34
18
19
ERR
2
11
15 DOC_SCLC 71
18
19
1J14
HDMI TXD0 4J14
15 2
CONNECTOR
UART
4J15 SERVICE
SIDE HDMI 14 RXD0 3
D1 CONNECTOR
1Q02
IIC_SDA 2 FROM 1305
B04
IIC_SCL 3 SSB
3Q11
3Q10
+3V3_ANA-MUX
+5VHDMI_S
12 13
3N37
3N38
3Q14
3Q15
16 17 28
2
BUFFER
19
ERR
22
1R01
3354 BOLT_ON_SDA 3R26 1
33
TXD0
LVDS
3L53 BOLT_ON_SCL 3R25 2 CONNECTOR
RXD0 34
H_17371_009.eps
021007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 43
B01a +AUDIO_POWER_+12V_DISP
5B06 6B03 +VTUN B05c
RES
SUPPLY 7B13 (34V) B02 1 5A08 -AUDIO_POWER
16 +3V3_ANA-MUX +3V3_ANA-MUX
7J04 +3V3 B07d
B03a,b,c
+5VHDMI-MUX-_TPWR +5VHDMI-MUX-_TPWR
B07d
7 IJ01
CONTROL 1Q03 1N01
19 +5VHDMI-SIDE-_TPWR
+1V8S_SW +1V8S_SW D1
SIDE I/O
B01b
H_17371_010.eps
021007
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 44
6
VCC VREF 2B25 B3
Φ IB50 5B05 5B08 FB11
OUT
1
+3V3_SW
2B26 B4
SS24
3 2B27 B7
INH IB51 22u 10u
5
100u 16V
FB 2B63 F8
3B10
2B10
RES
2
10n
SYNC
4
IB12 2B27 2B65 D1
COMP
6B30
2B66 B5
2B12
22u
470u 16V
2B66
GND GND_HS
IB20
2B67 B5
9
2B25
2B26
220p
2B68 F9
22n
7
3B10 A5
2B67
RES
3B12 B5
B IB19
3B12
B 3B15 D4
3B17 F2
1K5 3B18 F2
3B65
4K7
1K0 1%
3B19 B5
3B66
3B19
6K8
3B65 B4
3B66 B4
3B67 C4
3B68 F9
GNDDC 4B04 E8
4B05 E8
+VTUN 4B06 E8
FB14 34V
BZX384-C33
220R
3B67
4B07 E8
220u
5B06
C C
22u 35V
2B19
6B02
4B08 E8
6B03
IB15 4B09 E8
IB14 4B10 E8
BAV99
7B13 4B11 E8
2B20
4B12 F8
100p
1 2N7002
5B01 A2
2
3B15
1K0
7B02 5B05 A5
LD1117DT33C
+5V_STANDBY 5B06 C4
FB13 5B08 A6
3 2
IN OUT +3V3_STBY
6B02 C6
GNDTUN
COM ONLY FOR ANALOG TUNER 6B03 C5
10u 16V
2B65
100n
2B18
D D 6B30 B5
TO / FROM PSU
1
7B01 A3
7B02 D2
7B12 F2
7B13 C5
1B12
FB07 E9
5V2 FB27 FB28
+5V_STANDBY 1 FB10 A2
4B04
4B05 ** FB29
FB30
2
3
FB11 A6
4B06
4B07 ** FB07
4
5
FB13 D2
FB14 C6
FB31 FB15 E2
6
1n0
RES
+5V_SW
RES
4B08
4B09 ** 440054-6
FB27 D9
E RES 4B10
** E FB28 D9
2B06
RES 4B11 FB29 E9
3B68
TO / FROM PSU
2V9
3B17
2B22
1 FB36 F8
POWER_DOWN RES 4B12 IB52 2V8 FB37 F8
2
BL_ON_OFF FB37
FB32
3 FB38 F8
4 FB39 F8
BACKLIGHT_BOOST FB33 1V6
0V(5V) 5
STANDBY FB38 FB40 F3
F 3B18 IB49 7B12 6
F
1
2
3
RES
2B63
2B68
220p
1n0
47u 16V
2B24
2B21
100n
IB20 B5
IB49 F2
IB50 A5
H_17370_001.eps
3139 123 6273.1 (---V) MEASURED IN STANDBY 010804
IB51 A4
IB52 F8
1 2 3 4 5 6 7 8 9
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 45
2P29
2P30
2P28
22u
22u
22u
2P46 D8 FP35 E4
7P06-1 FP05 2P48 E6 FP40 C1
+2V5_SW 2P49 E1 IP01 B2
3P20 7 8
10R
IP38 2P52 D5 IP02 A5
2 SI4936ADY FP08
GNDDC2V5 GNDDC1V2 5P01 7P09 FP06
+1V8_SW
2P53 D5 IP03 B3
1
IP01
2 3 2P54 D6 IP04 B3
3P37 6K8
BZX384-C6V8
2P59 100u 4V
PHD38N02LT
10u
3P25
10R
B B 2P55 B8 IP08 C1
100u 4V
100u 4V
100u 4V
2P34
2P33
2P72
6P05
2P55
2P56
3n3
22u
2P32 2P56 B9 IP09 D1
2P31
4P01
1u0
1
2P58 C8 IP16 D3
IP03 3n3
2P59 B6 IP17 D3
3P59 470R 1%
IP57 IP23
3P23
2P35
7P06-2 GNDDC2V5 2P61 D7 IP23 B7
10R
1n0
1u0
5 6 GNDDC2V5 GNDDC2V5 NC 2P68 D8 IP24 C8
1
2P36
2P73
100n
3P78 1K0
22n
GNDDC2 IP04
4 SI4936ADY 2P72 B7 IP25 C3
2P58
2P73 B8 IP26 C3
RES
3
NC
7P07-1
+2V5_SW 4 2P78 A3 IP27 C3
REF
2P38 1n0
7 8 3P13 C4 IP28 D1
GNDDC2V5 IP42 IP24
NC
1%
2 SI4936ADY +12V_DISP
A
6P12 IP58 3P20 B2 IP29 D1
3P38
3P77
7P08
2R2
1K0
7P11
3P23 B3 IP31 D3
14
TS431AILT
1K0
NCP5422ADR2G
C C
2
BZX384-C6V8 3P25 B4 IP32 E2
10R
3P61
VCC
680R 1%
10R
Φ NC
3P64
FP40
3P26 C3 IP33 A5
4 1 3P32 D3 IP36 C5
3P26
BST H1
GATE IP25 2P37 IP36 5P09 FP03 3P34 D4 IP37 A2
2 4P02
L1 IP26 3P13 +1V2_SW 3P37 B6 IP38 B3
7
2P46 100u 4V
100u 4V
1 IP27 3n3 10u 3P38 C6 IP39 D3
16
3n3
IP08 7P07-2
180R 1%
VFB H2
3P40 D2 IP40 D4
2P52
3P45
3P51
2P61
10 5 6
6K8
1n0
22u
2 GATE
IP09 15 IP16 3P32 2R2 IP40 3P41 D3 IP41 D4
L2
2P43
8 4
1 2P53 3P45 D6 IP42 C4
IP28 5 3
2P68
9
COMP +1
6 SI4936ADY IP59 3P47 A3 IP43 D4
2 -1 IP17 3P34 IP41 3P68 1n0 3P48 A3 IP44 D6
IP29 IP31
IS
3P49 A2 IP45 E1
2P54
100n
13 12 GNDDC1V2
D IP55 ROSC +2
-2
11
3K3 6K8 GNDDC1V2 GNDDC1V2 GNDDC1V2
D 3P50 D6 IP55 D1
100n
100n
GND
2P39
3P74
100n
6K8
IP44
3P51 D7 IP56 A4
3P40
39K
3P52 E6 IP57 B6
3
+2V5_SW
2P40
2P41
3P50
1K0
6K8 3P70 IP43 3P69
IP39 3P56 E1
3K3 6K8 FP35 3P59 C8
2K2
100p
GNDDC2 GNDDC2 GNDDC2 GNDDC2 3P61 C5
2P42
3P71
100n
680R 1%
6K8
3P64 C1
3P53
3P68 D4
RES
3P72 6K8 +1V2_SW GNDDC1V2
2P48
3P69 D4
3P52
IP32
E E 3P70 D3
3P71 E3
470R 1%
2P49
100p
3P56
10K
3P74 D4
GNDDC2 GNDDC2V5
3P77 C8
3P78 C7
IP45 3P79 C7
4P01 B3
4P02 C4
GNDDC2 GNDDC2 GNDDC2
H_17370_002.eps
5P01 B6
3139 123 6273.1 010804 5P02 A5
5P09 C7
1 2 3 4 5 6 7 8 9
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 46
B02
1104 E4 F114 H10
2112 B11 F115 B7
3111 5K6 RF_AGC 2113 B10 F116 B7
5118 I146 3136 I147 3137 +5V_IF 2115 B6 F117 B7
+12V_DISP
A 33R 47R
7133
47R A 2116 B6
2117 C3
F118 B7
F119 B7
L78M05CDT 2118 C10 F120 B7
I145 3110 2119 C8 F121 B7
*
1101 TUNER 1 IN OUT
3 4V9 8K2
2120 C9 F126 C7
SAW FILTERS 6110 2121 E7 F128 F2
2147
330n
2148
100n
COM I111
F112
4112* F132
14
TUNER
TD1316AF/IHP-2 13
F134 DVB ONLY BAS316
2122 D7 F129 H11
XTAL_OUT
2123 F3 F130 G6
DC_PWR
2
IF_OUT1
IF_OUT2
IF_OUT3
MT MT
RF_AGC
1102 +5V_IF 2149 3115
IF_AGC
A115 15 12 2112 2124 F2 F131 H11
1 5 VIF1 22u 2u2 39K
I O1 2113 2125 F2 F132 A6
SDA
SCL
+5V
4 A116 VIF2
CS
IF_ATV F101 IGND O2 RES 2126 F3 F133 B9
7111 10n
16
3 +VTUN ONLY FOR ANALOG TV 74HCT4053D 2127 F4 F134 A8
B GND
B
10
11
5112 VDD 2128 F7 F140 G8
1
2
3
4
5
6
7
8
9
5117 MDX
OFWK3953M 33R 6 2129 H11 F142 B7
+5V_IF 38M9 G4
5111 RES 2130 H11 F143 B7
2146
2115
2116
3192
RES
RES
390n 4V3 14 13 RF_AGC_IBO
1u0
1u0
1u0
1K0 F133 1 2131 I11 F145 C7
12 WAGC_SW
F116
F115
F117
F118
F119
F120
F121
F142
F143
2 DVB_SW 2132 I11 I111 A12
11 4125
3113
* 4113
I137 4X1
4X2
* IIC_SDA 2133 G6 I114 C4
6K8 2120 2118 2134 H7 I118 C4
I114 2119 2142 15 1
2117 10u 50V 2135 H8 I120 C2
4114
4115
4116
4117
4118
4119
+5V_IF 100n 22u 10n 2 I2C_TDA_SDA
10 2136 G6 I121 D10
10n 2137 H5 I122 D7
1SS356
** * ***
3117
6103
IIC_SCL
2K2
2138 H2 I123 E10
1103 A124 4 3 2139 H5 I124 E3
C 3118 1 5 SIF2 5 I2C_TDA_SCL C
F126
2140 I3 I125 F4
F145
I O1
2K2 I118 4 SIF1 9
ISWI O2 2141 I3 I126 F3
A125 2142 C8 I127 F3
3 GND
VSS VEE
2143 F5 I128 G6
7
SAW_SW I141 3119 I120
7109 OFWK9656M 2144 I3 I129 G6
BC847B 38M9
22K VIP_IBO 2145 I3 I130 H6
3188 1V3 IF_AGC_IBO 2146 B6 I131 H5
18K 2147 A8 I133 I4
I122
* 4120 VIM_IBO
IF_ATV
2148 A9
2149 B11
I135 I4
I136 I4
1V3 4MHZ_CLK 3110 A12 I137 B8
D 5120 120R I121 4121
*+5V_IF D 3111 A11
3113 B3
I138 G7
I139 G7
2122 RES 3120 10R 3115 B12 I141 C1
4123
15p RES 3117 C3 I142 F5
RES 7131 +3V3_SW 3118 C2 I143 H3
3190 BSH111 3119 C1 I144 H3
* 4K7
3120 D8 I145 A9
3123 E3 I146 A8
5121 120R I123 4122
*+5V_IF 3124 E2
3125 G7
I147 A8
I148 I7
2121 RES 3146 10R
3126 H7 I149 H11
15p RES 3127 H6 I150 H11
RES 7132 +3V3_SW
E 3191
4K7
BSH111 E 3133 H10
3134 H10
3135 F7
DEMODULATOR I124 3123 1104
3136 A8
3137 A9
RF_AGC 3124 3140 I8
330R 4M0 +5VS
100R 2123 3146 E8
2125
470n
2126
220n
2127
2143
22p
1n0
3135
16 I126
3187 I8
19 I127
15R
I142
3188 D2
0V
9
14
15
21
REF
AFC
TOP
VAGC
TAGC
ANALOG 3192 B8
* DIGITAL
2128
10n
4110 Y Y 3193 I5
4111 Y Y 3194 I5
TUNER AGC VIF AGC RC VCO DIGITAL VCO CONTROL AFC DETECTOR 4112 Y Y 3195 I5
4113 Y
4114 Y
4112 B6
VIF2 2V 2 VIF2 4115 Y
4113 B8
SOUND TRAPS F130 4114 C7
CVBS 17 2V1 7114 4116 Y
2V 1 VIF1 VIF-PLL 4.5 to 6.5 Mhz BC847B
VIF1 4117 Y 4115 C7
4118 Y 4116 C7
1V5
SINGLE REFERENCE QSS MIXER AUD 8 I138 * 4124 4119
4120 Y
Y
4117 C7
G SIF2 2V 24 SIF2
INTERCARRIER MIXER AND
AUDIO PROCESSING I128 2133 4121 Y G 4118 C7
150R
3125
AND SWITCHES DEEM 5 4122 Y 4119 C7
SIF1 2V 23 SIF1 AM-DEMODULATOR 4123 Y Y 4120 D8
10n Y
F140 4124 Y 4121 D10
I139 5116
CVBS_RF 4122 E10
MAD
5u6 4123 D7
I129 2136
180R
3126
2134
2135
NARROW-BAND FM-PLL AFD 6 4124 G7
15p
15p
SIF OUTPUT
SUPPLY
AGC PORTS I2 C-BUS TRANSCEIVER DEMODULATOR 470n 4125 B11
RES F114 3133 I149 5114 F129 4126 I5
+5V_SW +5VS 5111 B1
12 SIOMAD
4 FMPLL
10u 5112 B9
7 DGND
1R0
18 AGND
10 SDA
3 OP1
22 OP2
11 SCL
I144
+5VS 2137 I130 3127 5117 B5
2V1
I143 5118 A8
2138 10n +5VS I131 10n
1n0
5K6
10n
1R0
6110 A11
3151 I148 3140 2131 2132
IIC_SCL_up 100R I133 4126 22u 22u 7109 C2
2140 RES 7111 B10
3194 150R
I135 7134 7113 F2
IIC_SDA_up 3152 100R BC847B 3187
+5VS 7114 G7
I 22K
I
3195
18K
SSB: DVB-Demodulator
1 2 3 4 5 6 7 8 9 10 11
2F10 B
2F11 B
5
FF10 3F10 2F10 2F11 2F26 C
IF10 2 4 4MHz_MOJO 100n 47u 16V
1
1V3 1V6 IF11 +1V8_SW 2F27 D
NC
470R
2F28 D
2F12
100n
1
3
5F11
B 3F11
680K 3F13 220K
3F12
330R
FF11 FF12
+1V8_SW B 2F29 D
60R 2F30 D
2F14 2F15 2F16 2F13 2F19 2F17 2F20 2F18 2F31 D
2F21
100n 100n 100n 100n 100n 100n 100n 100n 2F32 D
47u 16V
+3V3FE 2F33 E
+3V3
3F10 B
3F11 B
7F03 +3V3FE
3V2 3F12 B
2F22
100n
74AHC1GU04GW
5
FF13 3F14 IF12 FF14 3F13 B
4MHZ_CLK 2 1 4
1V3 NC 1V6 330R
3F14 C
2F23 2F25 2F24
3
3F15
3F15 C
3F16 2F26 100n 100n 100n
3F16 C
C RF_AGC_IBO
IF32
680K 3F17 220K 390R 100n
7F01 64 60 59 57 53 50 42 22 5 47 34 19
C 3F17 C
TDA10046AHT/C1 3F18 D
3F19 D
VDD33_ADC
VDD18_PLL_ADC
VDDI18_4
VDDI18_3
VDDI18_2
VDDI18_1
VDDE33_3
VDDE33_2
VDDE33_1
VDDA33_ADC
VDDA18_PLL
VDDA18_OSC
+5V_SW RES 3F20 D
+5V_SW +5V_SW 3F21 D
RESET_FE_n
+5V_SW +5V_SW
3F22 D
2F27
3F18 IF13 IF33
3F23 D
MPEG-TS (SERIAL)
7F04-1 3F19 3F20 3V2 9 20 0V 3F21 10046_TDO 3F24 D
680K
3F22
10K 33R
8 3V3 17 0V STV_TDO
3F24 IF14 IF15 3F25 IF16 TDI 3F26 D
3 4F11 4F12 2V8 1
JTAG
COMP_OUT 1
AGC_TUN 16 2V4 JTAG_TM S 3F27 D
IF18 100K IF17
D 2V2 2
100K RES IF_AGC_IBO
FF16 3F26 1V3 2
AGC_IF
TMS
18 0V
D 3F28 E
100K
3F29 E
3F27
100n
4
FF18 FF17 3F30 E
VIP_IBO
FF20
2F31 100n
FF19
1V5 62
VIP COFDM TRST
14 2V4 JTAG_TRST
3F31-1
3F31-2
VIM_IBO 2F32 100n 1V5 61 13
+5V_SW
VIM CHANNEL DECODER ENSERI 3F31-3
3F31-4
FF21
MPEG-TS (SERIAL)
0V7 54 32 3F32-1
7F04-2 3F28 3F29 XIN S_DO
8 2F33
LM393D 100K 100K FF22 55 31
3F32-2
5 10p 0V6
7
XOUT S_OCLK 3F32-3
6 30 3F32-4
+5V_SW FF23 S_DEN
COMP_OUT 2V3 21 3F33 E
E 4
23
GPIO0
S_PSYNC
28
E 3F34-1
GPIO1 27
3F34-2
FE_LOCK FF24 3F30 IF19 25 S_UNCOR
TDA_DAT(0:7) 3F34-3
GPIO2 38 2V2 3F31-4 4 5 33R IF20 3F40 F6
33R 3V2 DO0 TDA_DAT(0)
26 39 2V2 3F31-3 3 6 33R IF21 TDA_DAT(1) 3F41 F3
3F33 GPIO3 DO1 IF22
3F31-2 2 7 33R 3F42 F3
MPEG-TS (PARALLEL )
+3V3FE 41 2V2 TDA_DAT(2)
DO2 IF23
10K 43 2V2 3F31-1 1 8 33R TDA_DAT(3) 3F44 F6
11 DO3
44 2V2 3F32-4 4 5 33R IF24 TDA_DAT(4)
+5V_SW +5V_SW SADDR0 DO4
46 2V2 3F32-3 3 6 33R IF25 3F46 F6
DO5 TDA_DAT(5)
10 48 2V2 3F32-2 2 7 33R IF26 TDA_DAT(6) 3F48 F6
SADDR1 DO6
49 2V2 3F32-1 1 8 33R IF27 TDA_DAT(7) 4F11 D
I2C_LOCAL_SDA DO7
3F40 100R 4V6 8 4F12 D
I2C
3F41 3F42 SDA 37 1V7 3F34-1 1 8 33R IF28 TDA_CLK
5F10 B
F 2K7 2K7 I2C_LOCAL_SCL 3F44 100R
FF25
4V6 6
SCL
OCLK
36 1V3 3F34-2 2 7 33R IF29 TDA_VALID
F 5F11 B
FF26 FF27 4 DEN 7F01 C
I2C_TDA_SDA 3F46 100R 5V
SDA_TUN IF30
35 0V 3F34-3 3 6 33R TDA_SYNC 7F02 B
FF28 FF29 3 PSYNC
I2C_TDA_SCL 3F48 100R 5V 7F03 C
SCL_TUN 33 0V
FF30 UNCOR 7F04-1
VSS_PLL_ADC
12 51 IF31 7F04-2
VSSA_OSC
VSSA_ADC
TEST SACLK FF10 B
FF11 B
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
FF12 B
FF13 C
FF14 C
63 58 56 52 45 40 29 24 15 7
G G FF16 D
FF17 D
FF18 D
FF19 D
FF20 D
H_17370_004.eps FF21 E
3139 123 6273.1 010804 FF22 E
FF23 E
1 2 3 4 5 6 7 8 9 10 11
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 48
DVB-COMMON INTERFACE
2K00 H4 FK48 J7
B03B B03B
2K01 I4 FK49 J9
2K02 H15 FK50 J7
2K03 H15 FK51 J9
2K04 J3 FK52 J7
2K05 H15 FK53 J9
2K06 H15 FK54 J7
2K07 F14 FK55 J9
A A 2K08 H15 FK56 J7
PCMCIA_5V
2K09 H15 FK57 J9
+3V3_STV
2K10 H15 FK58 J7
2K11 I15 FK59 J9
A_MOVAL
A_MISTRT
A_MIVAL
A_MICLK
A_MOCLK
A_MOSTRT
2K12 I15 FK60 J7
A_MDO(0:7)
A_|CD1
A_|CD2
A_|RDY|IRQ
A_RESET
PCMCIA_|REG
PCMCIA_|IORD
A_|WAIT
A_|CE1
A_|CE2
VCCEN
PCMCIA_|WE
PCMCIA_|OE
DATDI R
|ADOE
ADLE
PCMCIA_|IOWR
A_MDI(0:7)
|DATOE
2K13 I15 FK61 J9
2K14 F9 FK62 J8
A_MDO(0)
A_MDO(1)
A_MDO(2)
A_MDO(3)
A_MDO(4)
A_MDO(5)
A_MDO(6)
A_MDO(7)
A_MDI(0)
A_MDI(1)
A_MDI(2)
A_MDI(3)
A_MDI(4)
A_MDI(5)
A_MDI(6)
A_MDI(7)
3K19 2K15 K4 FK63 J7
10K
2K16 F8 FK67 H9
3K21 10K 2K17 G8 FK68 H7
3K00 F2 FK69 H9
3K20 10K 3K01 F2 FK70 H7
B B
3 47R
4 47R
1 47R
2 47R
3K02-1 F4 FK71 H9
47R
47R
47R
47R
47R
47R
47R
47R
47R
47R
47R
47R
47R
47R
47R
47R
47R
3K18
47R
10K
4K7
3K02-2 F4 FK72 H7
3K15 10K 3K02-3 F4 FK73 H9
3K03-1 F5 FK74 H7
3K16 10K 3K03-2 F5 FK75 H9
3K34-1 8
7
6
3K34-4 5
3K17 3K03-3 F5 FK80 H7
3K27
3K28
3K29
3K30
3K31
3K32
3K33
3K40
3K41
3K42
3K43
3K44
3K45
3K46
3K47
3K48
10K
3K39
3K03-4 F5 FK81 H16
3K34-2
3K34-3
3K22 10K 3K04 H9 FK82 I16
3K05-1 F5 FK83 I16
IK68
IK69
IK73
IK76
3K05-2 F5 FK84 F15
3K05-3 F6 IK68 C10
0V
0V
0V
0V
0V
0V
0V
0V
0V
3V2
3V2
3V2
3V2
3V2
3V2
3V2
PCMCIA
0V
0V
0V
0V
3V2
3V2
0V
0V
0V
0V
0V
0V
0V
0V
5V
5V
RDY|IRQA_ 101 5V
RDY|IRQB_ 100 5V
0V
0V
0V
0V
0V
3K05-4 F6 IK69 C10
C C 3K06 K9 IK70 F15
CONTROLLER
MICLKA 110
MIVALB 104
MIVALA 105
MDIA3 103
MDIA4 107
MDIA5 112
MDIA6 114
MDIA7 116
MOCLKA 118
MOSTRTA 127
MOVAL A 125
MICLKB 108
MDIB3 102
MDIB4 106
MDIB5 111
MDIB6 113
MDIB7 115
MOCLKB 117
MOSTRTB 126
124
MDOB0 128
RSTA 120
RSTB 119
122
WAITB_ 121
3K07 K9 IK72 F16
MISTRTA 92
MDIA0 94
MDIA1 96
MDIA2 99
MDOA3 74
MDOA4 76
MDOA5 78
MDOA6 80
MDOA7 84
MISTRTB 91
MDIB0 93
MDIB1 95
MDIB2 98
MDOB3 73
MDOB4 75
MDOB5 77
MDOB6 79
MDOB7 83
CD1A_ 72
CD1B_ 71
WE_ 97
IORD_ 89
IOW_R 90
OE_ 88
CE1A_ 82
CE1B_ 81
CE2A_ 87
CE2B_ 85
VCCEN 70
69
DATDI R 68
ADOE_ 67
ADLE 66
MDOA0 1
MDOA1 3
MDOA2 5
MDOB1 2
MDOB2 4
CD2A_ 7
CD2B_ 6
3K08 K6 IK73 C10
MOVAL B
WAITA_
DATOE_
3K09 F9 IK75 F11
3K10 E14 IK76 C11
3K11 F16 IK84 G8
3K12 F10 IK85 C4
86 3K13 F15
GND-DVB2
9 3K15 B9
GND-PROC 3K16 B9
STV_TDO
10
52 3K17 B9
TDO GND-TSO
D D 3K18 B9
MANAGEMENT
TS INTERFACE
INTERFACE
INTERRUPTS
JTAG_TRS T 39
11 65 38 8
UCSG
STV_TDI 37
2
3V2 15 WAIT|ACK
3K24-3 K4
CURRENT
62 MOSTRT
E E
3V2 16 WR|STR
49 MISTRT
63 MOCLK
3V2 12 EXTINT
3V2 17 RD|DIR
61 MOVAL
0V 34 RESET
13 EXTCS
3K24-4 K4
50 MICLK
48 MIVAL
53 MDO0
54 MDO1
55 MDO2
56 MDO3
57 MDO4
58 MDO5
59 MDO6
60 MDO7
+3V3_STV
40 MDI0
41 MDI1
42 MDI2
43 MDI3
44 MDI4
45 MDI5
46 MDI6
47 MDI7
STV0700L
7K00
3K25 K4
30 SDA
31 SCL
FK0135 CLK
32 SA0
33 SA1
19 A15
20 A16
3V2 21 A17
3V2 22 A18
3V2 23 A19
3V2 24 A20
3V2 25 A21
26 A22
27 A23
28 A24
29 A25
3V2 14 INT
3V2 18 CS
SWITCH 3K26 K4
3K27 C2
3K10
3V2
2V5
10K
3K28 C3
+5V_SW 7K05 3K29 C3
0V
0V
2V2
2V2
1V3
2V2
2V2
0V
0V
2V2
2V2
2V2
2V2
2V2
2V2
2V2
0V
0V
FK84
1V6
2V2
2V2
2V2
2V2
2V2
1V5
1V3
4V6
ST890C 3K30 C3
FK02
4V6
0V
0V
+3V3_STV 3K31 C3
FK06 7 1 5V
5V
IK75
MIU_ADDR(15)
MIU_ADDR(16)
MIU_ADDR(17)
MIU_ADDR(18)
MIU_ADDR(19)
MIU_ADDR(20)
MIU_ADDR(21)
MIU_ADDR(22)
MIU_ADDR(23)
MIU_ADDR(24)
PCMCIA_5V +5V_SW 3K32 C3
7K04 OUT1 IN1
100R
100R
4
TDA_DAT(0 )
TDA_DAT(1 )
TDA_DAT(2 )
TDA_DAT(3 )
TDA_DAT(4 )
TDA_DAT(5 )
TDA_DAT(6 )
TDA_DAT(7 )
3K09
2560NK 6 2
10K
OUT2 IN2 3K34-1 C4
3K11
27M
10K
10K IK70 3K34-2 C4
F VDD 5
SET FAULT_
8
F
3K02-3 33R
3K02-2 33R
3K02-1 33R
3K03-1 33R
3K03-2 33R
3K03-3 33R
3K03-4 33R
3K05-1 33R
3K05-2 33R
3K05-3 33R
3K05-4 33R
3K34-3 C4
3K00
3K01
3 0V
GND
OUT 3
1 3K34-4 C4
ON_
2K0 1%
STNDBY IK72
2K14
2K07
3K13
1n0
0V 3K38 C4
10u
TDA_DAT(0:7 )
RESET_STV
GND MIU_ADDR(0:24) 3K39 C4
EMC
2K16
47n
MIU_WEN
4
MIU_RDY
MIU_OEN
3K40 C4
STV_A25
I2C_LOCAL_SDA
STV_INT
I2C_LOCAL_SCL
STV_CS
2 3K41 C5
FK05
3K42 C5
TDA_VALID
TDA_SYNC
TS_DATA(0)
TS_DATA(1)
TS_DATA(2)
TS_DATA(3)
TS_DATA(4)
TS_DATA(5)
TS_DATA(6)
TS_DATA(7)
IK84
TDA_CLK
3K43 C5
TS_VALID
TS_SYNC
EMC
TS_CLK
VCCEN 3K44 C5
2K17
47n
3K45 C5
3K46 C5
G TS_DATA(0:7)
G 3K47 C6
3K48 C6
3K49 H2
3K50 H2
3K51 K6
A_MDO(0:7) 5K01
68p PCMCIA PCMCIA_5V
60R
PCMCIA_AVCC 3K52 C4
5K01 G15
2K05
A_MDO(3)
A_MDO(4)
A_MDO(5)
A_MDO(6)
A_MDO(7)
LATCH +3V3_BUF
100n
A_MDO(0)
A_MDO(1)
A_MDO(2)
5K02 H15
7K01 2K00 CONNECTOR +3V3_STV
5K03 H15
74LVC573ADB 5K04 I15
100n PCMCIA_A(0:14) 1K00-A 1K00-B 5K02
3K04
|ADOE 3K49 33R 0V 1 OE_ 20 5K05 I15
10K
EN PCMCIA_D(0:7) ROW_A ROW_B PCMCIA_5V PCMCIA_VPP
ADLE 3K50 33R 3V2 11 C1VCC 60R 7K00 E1
H H
2K02
2K03
100n
100n
PCMCIA_D(3) GND1 GND3 7K01 H3
MIU_ADDR(7) 0V 2 D0 Q0 19 0V PCMCIA_A(7) PCMCIA_D(4) FK80 D3 1 35 CD1 FK67 A_|CD1
MIU_ADDR(0:24) MIU_ADDR(6) 3 D1 1D
Q1 18 FK68 2 36 FK69 7K02 I3
3V2 3V2 PCMCIA_A(6) PCMCIA_D(5) D4 3 37 D11
MIU_ADDR(5) 3V2 4 D2 Q2 17 3V2 PCMCIA_A(5) PCMCIA_D(6) FK70 D5 D12 FK71 FK81 7K03 K3
4 38 5K03
MIU_ADDR(4) 3V2 5 D3 Q3 16 3V2 PCMCIA_A(4) PCMCIA_D(7) FK72 D6 D13 FK73 7K04 F8
MIU_ADDR(3) 3V2 6 D4 Q4 15 3V2 PCMCIA_A(3) A_|CE1 FK74 D7 5 39 D14 FK75 +3V3 +3V3_STV
10u 16V
6 40 60R 7K05 E16
2K06
2K08
2K09
2K10
100n
100n
100n
MIU_ADDR(2) 0V 7 D5 Q5 14 0V PCMCIA_A(2) PCMCIA_|OE FK10 CE1 D15 FK11 FK01 E9
MIU_ADDR(1) 8 D6 Q6 13 FK12 7 41 FK13
3V2 3V2 PCMCIA_A(1) PCMCIA_A(10) A10 8 42 CE2 A_|CE2
MIU_ADDR(0) 3V2 9 D7 Q7 12 3V2 PCMCIA_A(0) FK14 OE VS1 FK15 A_|VS1 FK02 F10
GND10 PCMCIA_A(11) FK16 A11 9 43 IORD FK17 PCMCIA_|IORD FK05 G9
10 44 5K04 FK82
PCMCIA_A(9) FK18 A9 IOWR FK19 PCMCIA_|IOWR FK06 F15
PCMCIA_A(8) FK20 A8 11 45 A17 FK21 A_MISTRT +3V3 +3V3_CORE
10u 16V
12 46 60R FK10 H7
2K11
2K12
100n
PCMCIA_A(13) FK22 A13 13 A18 FK23 A_MDI(0) FK11 H9
47
I LATCH +3V3_BUF 2K01
PCMCIA_A(14)
PCMCIA_|WE
FK24
FK26
A14
WE|P 14 48 A19
A20
FK25
FK27
A_MDI(1)
A_MDI(2) A_MDI(0:7)
I FK12 H7
7K02 A_|RDY|IRQ FK28 RDY|BSY 15 49 A21 FK29 A_MDI(3) FK13 H9
74LVC573ADB 16 50 5K05 FK83
PCMCIA_AVCC FK30 VCC1 VCC2 PCMCIA_AVCC FK14 I7
0V 1OE_ 20 100n PCMCIA_VPP FK31 VPP1 17 51 VPP2 PCMCIA_VPP +3V3 +3V3_BUF
10u 16V
EN 18 52 60R FK15 I9
2K13
11 A_MIVAL FK32 A16 A22 FK33 A_MDI(4)
C1VCC 19 53 FK16 I7
A_MICLK FK34 A15 A23 FK35 A_MDI(5)
MIU_ADDR(8) 0V 2 D0 Q0 19 0V PCMCIA_A(8) PCMCIA_A(12) FK36 A12 20 54 A24 FK37 FK17 I9
1D 21 55 A_MDI(6)
MIU_ADDR(9) 3V2 3 D1 Q1 18 3V2 PCMCIA_A(9) PCMCIA_A(7) FK38 A7 A25 FK39 A_MDI(7) FK18 I7
MIU_ADDR(10) 4 D2 Q2 17 FK40 22 56 FK41
0V 0V PCMCIA_A(10) PCMCIA_A(6) A6 23 57 VS2 A_MOCLK FK19 I9
MIU_ADDR(11) 0V 5 D3 Q3 16 0V PCMCIA_A(11) PCMCIA_A(5) FK42 A5 RESET FK43 A_RESET FK20 I7
MIU_ADDR(12) 3V2 6 D4 Q4 15 3V2 PCMCIA_A(12) PCMCIA_A(4) FK44 A4 24 58 WAIT FK45 A_|WAIT
MIU_ADDR(13) 25 59 FK21 I9
0V 7 D5 Q5 14 0V PCMCIA_A(13) PCMCIA_A(3) FK46 A3 INPACK FK47 A_|INPACK
MIU_ADDR(14) 3V2 8 D6 Q6 13 3V2 PCMCIA_A(14) PCMCIA_A(2) FK48 A2 26 60 REG FK49 PCMCIA_|REG FK22 I7
9 D7 GND Q7 12 PCMCIA_A(1) FK50 A1 27 61 BVD2|SPKR FK51 A_MOVAL FK23 I9
28 62
J 10 PCMCIA_A(0)
PCMCIA_D(0)
FK52
FK54
A0
D0 29 63
BVD1|STSCHG
D8
FK53
FK55
A_MOSTRT J FK24 I7
FK25 I9
FK56 30 64 FK57
PCMCIA_D(1) D1 31 65 D9 FK26 I7
PCMCIA_D(2) FK58 D2 D10 FK59
BUS TRANSCEIVER +3V3_BUF A_|IOIS16 FK60 WP|IOIS16
GND2
32
33
66
67 CD2
GND4 FK62
FK61 A_|CD2 FK27 I9
FK28 I7
2K04 FK63 34 68
3V2 7069 7172 FK29 I9
20 FK30 I7
3K51
3K06
100n
3K07
0V
3K08
10K
4K7
FK31 I7
74LVC245A 3EN2 FK32 I7
19 0V 3K26 33R |DATOE
G3 FK33 I9
2K15 100p
MIU_DATA(7) 0V 18 2 0V 3K23-4 4 5 33R PCMCIA_D(7) FK34 I7
1
+3V3_STV
MIU_DATA(0:15) 2 FK35 I9
K MIU_DATA(6)
MIU_DATA(5)
0V
0V
17
16
3
4
0V
0V
3K23-3
3K23-2
3
2
6
7
33R
33R
PCMCIA_D(6)
PCMCIA_D(5)
K FK36 I7
+3V3_STV
+3V3_STV
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 49
3G19
RES 3G15
10K
10K
10K
MOJO_TRST
MOJO_TDI
10046_TDO
FG10
FG11
FG12
RES
ROW_1
1G01-1
1
3
RES
ROW_2
1G01-2
2
4
FG13
SDRAM_DATA(0:15)
SDRAM_DATA(0) 0V 113
0
7G00-4
PNX8314HS
(SDRAM) 0
153 0V
0V
SDRAM_ADDR(0:14)
SDRAM_ADDR(0)
B03C 2G05 G6
2G06 H6
2G07 H6
2G08 H6
2G09 H6
IG20 G2
IG21 E6
MOJO_TRST
0V
MOJO_TCK
2V3 126 142
MOJO_TMS
SDRAM_DATA(12) SDRAM_ADDR(12) 3G16 A4
33R
RESET_n 12 12
2V3 125 150 0V 3G17 A4
RES 100n SDRAM_DATA(13) 13 13 SDRAM_ADDR(13) 3G18 A4
4MHZ_MOJO 2G31
SDRAM_DATA(14) 0V 124 151 0V SDRAM_ADDR(14) 3G19 A4
14 14 3G20 A4
4G31 5G05 33R
3G48
SDRAM_DATA(15) 2V3 123 138 2V1 SDRAM_DQM0 3G28 E14
RES 5G03 1V2clean 15 DQM0 3G29 F14
+1V2_SW 3G30 E14
100MHz 133 3V1 SDRAM_DQM1
FG37 FG18 DQM1
3G31 E14
2G32 4G04 STV_TDI
140 3V SDRAM_CAS 3G33 G2
C RES 4G05
CAS C
1V2
100n 10046_TDO 3G34 G2
141 2V9 SDRAM_RAS 3G35 F2
2G33 RAS
3V3
3V3
3V2
3V3
3V2
0V
CONFIGURABLE 3G36 F14
0V
10u 16V 139 3V SDRAM_WE
WE 3G37 F14
3V3 3G38 A4
SDRAM_CKE
160
157
159
158
4
3
2
1
207
208
137 3G40 I8
CKE
4G05 FOR DEVELOPMENT ONLY 3G41 E14
4G01, 4G02, 4G03,4G04 FOR PRODUCTION 136 1V5 SDRAM_CLK
HSCKB 3G43 H2
DSU_TPC0
AVSS_PLL
AVDD_PLL
XTAL_I N
RESETN
TCK
TRST
TMS
TDO
TDI
XTAL_OUT
3G44 H2
3G46 H2
(JTAG-ETAG-SYS)
3G47 I2
3G48 C6
PNX8314HS
3G51 G13
D 7G00-7
D
7G00-8
PNX8314HS 3G54 G13
3G55 G13
RESET_FE_n 3V3 31 3G56-1 H10
SYS_RESETN
IR_IN 3G56-2 H10
(GPIO)
DSU_CLK
DSU_TPC1
RESET_STV 0V 32 3G56-3 H10
1 PCST1
1 PCST0
IR_OUT
3G56-4 H10
user_EEPROM_WP 4V6 185 17 0V 3G57-1 G10
PWM DTR0
3G57-2 H10
0
VS VCXO_CLOCK
3G57-3 G10
3G57-4 H10
186
187
195
196
197
188
189
194
33 18 0V RX_ZAP FG22 FG21 3G41 10K 3G58-1 G10
5
VPP RX1
3G58-2 H10
7G00-2
IG21 FE_LOCK 3V3 34 19 3V3 TX_ZAP FG23 FG20 3G58-3 G10
+3V3_VDDP C4 TX1
PNX8314HS
E E 3G58-4 H10
3G11
NOR_RYBY 0V 35
10K
C8 BOOT <0:3> FG24 3G30 3G59-1 H10
(TS) 10K 3G59-2 H10
TS_DATA(0) 2V2 20 NOR_WP 0V 45 176 0V PIO19|ITU_OUT0|BOOT0
3G59-3 H10
FG26 3G12
0 SC1_DA 0
30 0V
10K
TS_DATA(1) 2V2 21 TS_SYNC FG25 3G28 10K +3V3
2V2 22 1 TS_SYNC +3V3_VDDP STV_INT 0V 46 177 3V3 PIO20|ITU_OUT1|BOOT1 3G59-4 H10
TS_DATA(2) 2 SC1_CMDVCC 1 3G60 I11
TS_DATA(3) 2V2 23 3 TS_DAT A TS_STROBE
29 1V6 TS_CLK 3G31 10K +3V3
TS_DATA(4) 2V2 24 STV_A25 0V 47 178 3V3 PIO21|ITU_OUT2|BOOT2 3G61 I11
TS_DATA(5) 2V2 25 4
5 TS_VAL
28 1V3 TS_VALID SC1_RST 2
FG28 FG27 3G36 10K RES 3G62 I11
TS_DATA(6) 2V2 26 DSW_n 3V3 48 179 3G63 F10
6 SC1_OFF 3 4G01 B9
TS_DATA(7) 2V2 27 7 ITU_OUT
PIO22|ITU_OUT3|BOOT3 3G29 10K +3V3
+1V2_SW 49 180 4G02 B9
SC1_CCK 4 RES
IG17 3G37 10K 4G03 B9
3G63 10K 0V 12 181 3V2 4G04 C8
CTS0 5
4G05 C8
F 7G00-3
5G06
13 RTS0 6
182 FG29 IBO_IRQ F 4G09 A2
PNX8314HS FG30 4G10 A2
33R 0V 14 183
RXD0 RX0 7 4G31 C3
168 5G07 FG39 1V2_CORE 7G00-1 0V 5G01 G5
CVBS 1V2 PNX8314HS 0V 15 184
Y TXD0 TX0 ITU_CLOCK 5G02 G5
IG14 IG18 5G03 C5
10u 16V
10u 16V
10u 16V
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 50
10u 16V
2H07
2H04
100n
2H13 C2
2H14 D6
A 7H00 A 2H15 D6
M29W320ET70N 37 3H00 C5
MIU_DATA(0:15) 3H05 C7
3H09 E7
MIU_ADDR(1) 3V2 25 29 0V MIU_DATA(0) 3H10 E7
0 EPROM 0 3H11 E7
MIU_ADDR(2) 0V 24 31 0V MIU_DATA(1)
1 4Mx8/2Mx16 1
MIU_ADDR(3) 3V2 23
2 2
33 0V MIU_DATA(2) 3H12 E8
MIU_ADDR(4) 3V2 22 35 0V MIU_DATA(3) 3H13 E8
5H01 3 3
+3V3 MIU_ADDR(5) 3V2 21 38 0V MIU_DATA(4)
4 4
0V
3H14 D5
100MHz MIU_ADDR(6) 3V2 20 40 MIU_DATA(5)
5 5 4H00 C5
MIU_ADDR(7) 0V 19 42 0V MIU_DATA(6)
10u 16V
6 6 4H01 C5
2H06
MIU_ADDR(8) 0V 18 44 0V MIU_DATA(7)
7 7
B MIU_ADDR(9)
MIU_ADDR(10)
3V2
0V
8
7
8
9
D
8
9
30
32
0V
0V
MIU_DATA(8)
MIU_DATA(9) B 4H02 C5
4H03 C5
MIU_ADDR(11) 0V 6 0 34 0V MIU_DATA(10)
3V2 10 A 10 4H04 C5
MIU_ADDR(12) 5 32M-1 36 0V MIU_DATA(11)
11 11 4H05 C7
MIU_ADDR(13) 0V 4 39 0V MIU_DATA(12)
FH07 12 12 4H12 E7
MIU_ADDR(14) 3V2 3
13 2/4/8MB 13
41 0V MIU_DATA(13)
MIU_ADDR(15) 0V 2
14 14
43 0V MIU_DATA(14) 4H15 C7
MIU_ADDR(16) 0V 1
15
NOR 15
45 0V MIU_DATA(15) 5H01 B1
MIU_ADDR(17) 3V2 48
5H02 A6
100n
100n
100n
100n
100n
100n
FLASH
100n
16 A-1
MIU_ADDR(18) 0V 17
3V2 16
17 5H03 D5
MIU_ADDR(19)
4H02 18 7H00 A6
MIU_ADDR(20) 3V2 9 IH07
19
2H10
2H08
2H09
2H13
2H03
2H12
2H11
3K3
3K3
SDRAM_ADDR(11) 0V SDRAM_DATA(8) 100MHz
11 8 44 1V3 1R0 220n 220n
SDRAM_DATA(9) 7H03
9 45 1V
3H11
SDRAM_DATA(10)
10K
10 M24C64-WMN6 5V
47 1V4 SDRAM_DATA(11)
8
11
SDRAM_ADDR(13) 0V 20 48 1V4 SDRAM_DATA(12) I2C ADDRESS:A0
Φ
3H12
3H13
21 0 12 50 1V3
SDRAM_ADDR(14) 0V BA SDRAM_DATA(13)
1 13 51 0V7 (8Kx8) 7 user_EEPROM_WP
SDRAM_DATA(14) 4V6 4H12
38 14 53 1V2 WC
SDRAM_CLK 1V5 SDRAM_DATA(15) FH00
CLK 15 EEPROM 3H10
6
E SDRAM_CKE 3V3 37
19 CKE
CS
1
2 0
1 ADR
SCL
5
4V6
FH04 100R
I2C_LOCAL_SCL
E
SDRAM_RAS 3V 18 3 4V6 I2C_LOCAL_SDA
RAS +5V_SW 2 SDA
SDRAM_CAS 3V 17 15 3V3 SDRAM_DQM0
CAS L 5V FH02 3H09
SDRAM_WE 3V 16 DQM 39 2V2 SDRAM_DQM1 4
WE U 100R
VSS VSSQ
28 41 54 6 12 46 52
H_17370_007.eps
3139 123 6273.1 010804
1 2 3 4 5 6 7 8
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 51
10u 16V
100n
2J01
2J02
PESD5V0S1BA
3u3 +3V3_SW
2J69 D2
2J70 D3
180R
3J59
180p
2J63
2J62
3J60
6J60
RES
47R
68p
2J71 E2
2J72 E2
2J73 E2
22u 16V
3J01
2J04
22K
3J01 B8
B IJ01 3J02
7J04 B 3J02 B8
3J03 B6
12K IJ02 1V2 SI2301BDS
3J03 1V8 3J14 D8
+1V8_SW 7J05 FJ01
C_CVBS IJ63 PDTC114ET +3V3 3J15 D8
100R
3J59 B2
BAS316
6J03
3J60 B3
3J61 C2
RES 3J62 C3
100u 16V
2J64
100n
EMC
2J05
2J06
3J63 D2
22p 3J64 D3
3J65 E2
5J53 FJ23 3J66 E3
G|Y IBO_G_IN
C IJ64
C 4J14 C8
PESD5V0S1BA
3u3
B|Pb IJ65 4J15 D8
3J62
6J61
RES
47R
5J01 A6
180R
3J61
180p
R|Pr
2J66
2J67
IJ66
68p
5J52 A3
5J53 C3
UART CONNECTOR (SERVICE) 4J14 5J54 D2
1J14 IJ67 5J55 E2
MSJ-035-29D PPO (PHT) FJ24 RES 3J14 100R TXD0
RES 6J03 B7
2 IJ68
2J68 6J14 D7
FJ25 RES 3J15 100R RXD0
3 6J15 D8
22p 1
5J54
4J15 6J60 B3
FJ26
1001
1002
IBO_B_IN 6J61 C3
D D
PESD5V0S1BA
2
3J63
180p
2J69
2J70
3J64
6J62
RES
PESD3V3L1BA
PESD3V3L1BA
47R
68p
7J04 B9
7J05 B7
6J14
6J15
FJ01 B9
ESD Protection
FJ02 D6
1
RES FJ22 A4
2J71 FJ23 C4
FJ24 D8
22p
5J55 FJ27 FJ25 D8
IBO_R_IN FJ26 D4
PESD5V0S1BA
E 3u3 E FJ27 E4
FJ28 A8
180R
3J65
180p
2J72
2J73
3J66
6J63
RES
47R
68p
IJ01 B7
IJ02 B8
IJ63 B1
IJ64 C1
IJ65 C1
IJ66 C1
H_17370_008.eps
3139 123 6273.1 010804 IJ67 D8
IJ68 D8
1 2 3 4 5 6 7 8 9
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 52
MICROPROCESSOR FRONT_Y_CVBS_IN
4L20 1305 A9 3L21 A11 F360 I9
B04
FRONT_Y_CVBS_IN_T
* *
RES 3L20 100R
+3V3_STBY
1306 H8 3L22 B11 F361 D3
TO / FROM SIDE IO RES 4L21
RES 3L21 100R FRONT_C_IN_T
1307 I8 3L23 B11 F362 B5
1308 I8 3L24 A11 F363 G10
1309 I9 3L25 A11 F364 G10
2L22 10p
10p
10p
10p
1305 1304
+3V3_STBY
+3V3_STBY
1310 I9 3L26 D5 F365 G10
1-440054-0
+3V3_STBY +3V3_SW 1 1311 H7 3L27 B12 F366 E10
HDMI_INT_SIDE FL20
RES
RES
RES
RES
*2L21
*2L23
* * 2L20
CPU_RST 1 2 1312 I5 3L28 D2 F367 E10
IIC_SCL_SIDE
A 2 3
A 1313 I4 3L53 G7 F368 B10
10K
IIC_SDA_SIDE FL21 FRONT_C_IN
*
IL21
1K0
3 4 1314 H3 3L54 G11 F369 E10
5301
+3V3_STBY
+3V3_STBY
60R
HDMI_RST_RX_BUF 4 5 4L24 IL20
L_FRONT_IN 220n SIDE_AUDIO_IN_L 1L20 H8 3L55 F5 F370 G6
BAS316
+3V3_SW FL22 RES 3L24 33R 2L24
10K
2315 5 6 2310 A4 3L56 F5 F379 D2
100n
RES
+1V8_SW 6 7 4L25 IL22
+5V_SW FL23 R_FRONT_IN RES 3L25 33R 2L25 220n SIDE_AUDIO_IN_R 2311 C10 3L57 D3 F380 B2
7 8 3L58 F5 F381 B3
2312
100n
2313
100n
2310
100n
7312 DDC_RESET FL24 IL23 2312 A4
8 9
3330
1n0
1n0
1n0
1n0
3310
BD45275G FL25 2313 A4 3L59 C5 F382 H10
5
6301 9 10
3319
VDD FL26 2314 B3 3L60 G5 F383 I10
NC 10 11 2315 A1 3L61 G5 F384 I10
Φ
*2L31
*2L30
*2L33
*2L32
RES
RES
RES
RES
F330 1 4 7311 1-440054-1 2316 B3 3L62 F7 F385 D3
ER VOUT
14
60
97
100K
M30300SAGP F386 C5
3L96
3V3 2317 2317 B1 3L63 D2
100n 2314 15p 1V5 HEAD_PH_L 3L22 33R HP_LOUT 2318 C3 3L67 E5 F387 H10
10K
2 3 VCC
Φ AVCC
13
3325
10K
1301
10M
XTA L
HEAD_PH_R 3L23 33R HP_ROUT 2320 F10 3L72 F2 F389 G3
11 HP_DETECT
100p
100p
2316 OUT 2323 F1 3L73 H2 FL20 A9
2L29 22n
2L28 22n
15p 1V5 3L75 E7 FL21 A9
2324 F7
B 3314 10K I312 6 95 I311 3313 330R F323 LED1 B 2327 H9 3L76 E7 FL22 A9
3316
BYTE 0 3315 100R
93 FL36 KEYB
RES
* 2L27
2L26
2329 I10 3L79 F5 FL23 A9
RES
RES
RES
CNVSS 3318 100R I387 7 1 3317 330R
92 IL37 HP_DETECT_T
*
CNVSS 2 3320 100R FOR EMC 2330 I10 3L86 D1 FL24 A9
F380 RES 3321 1K0 91 SC1_STATUS 4L26
3 3322 100R HP_DETECT_T 2331 I10 3L93 F7 FL25 A9
*
10 90 SC2_STATUS RES 3L27
*
RESET
AN
4 100R 2332 I12 3L94 H2 FL26 A9
3323 100R 89 3303 100R IL38 HDMI_HOTPLUG_RESET
F381 5 5302 F368 2333 I11 3L95 H2 FL36 B6
2L34 1n0
1n0
96 88 F362 3L05 100R F302 RST_AUD
+3V3_STBY VREF 6 3324 10K +3V3_STBY 2335 I11 3L96 B6 I311 B5
7
87 LED2 60R 2336 I11 4301 F6 I312 B3
2318
100n
AD(0) 86 3357 100R HDMI_RST_RX_BUF 2311
*2L35
RES
RES
0 2337 I12 4302 H11 I318 G9
AD(1) 85 1 P10<0:7> RES 3356 10K
+3V3_SW 10u
AD(2) 84 3329 100R IL30 RST_H 2338 E2 4303 H12 I326 C5
*
2 2339 I12 4304 H12 I330 D1
AD(3) 83 3 KI<0:3>
AD(4) 82 DATA 3396 1K0 +5V_STANDBY 2340 I11 4305 H12 I331 D3
4
AD(0:7) AD(5) 81 7322 STANDBY 7310 2341 E12 4306 G13 I332 D1
C
37
AD(6)
AD(7)
80
79
5
6
TBIN<0:4>
5 F386
PDTC114ET STANDBYn M29W800DT-70N6 AD(0:7) C 2L20 A11
2L21 A11
4307 G13
4309 I12
I333 D3
I334 D1
7 CLK3
4 I326 A(1:7) EPROM
SIN3 2L22 A12 4310 I11 I335 D3
3 I357 3L59 100R F304 A(1) F310 25 1Mx8/512Kx16 2L23 A12 4313 H6 I338 D3
P0<0:7> SOUT3 3L11 100R 0
2 IBO_RESET I390 RESET_n A(2) F311 24 29 F312 AD(0) 2L24 A12 4314 H11 I341 D5
DA0 1 0
3300 1K2 1 I389 A(3) F313 23 31 F314 AD(1) 2L25 A12 4315 H11 I342 D5
AN0<0:7> DA1 FOR DVB ONLY 2 1
CLK4
100 E_PAGE A(4) F315 22 3 2
33 F316 AD(2) 2L26 B11 4316 G9 I344 D5
MUTEn I353 3L57 100R I352 78 A(5) F317 21 35 F318 AD(3) 2L27 B11 4323 F1 I351 F5
8 ANEX0 4 3
CTRL_DISP1_up I330 3338 100R I331 77 99 I364 3380 100R I362 LCD_PWR_ON F319 20 38 F320
CTRL_DISP4_up I332 3339 100R I333 76 9 SOUT4 A(8:19) A(6) F321 19 5 4
40 F322
AD(4) 2L28 B12 4326 D1 I352 C3
10 ANEX1 A(7) 6 5 AD(5) 2L29 B12 4327 D1 I353 C1
BL_ON_OFF I334 3340 100R I335 75 98 RES 3387 100R IL39 CEC_D A(8) F324 18 42 F325 AD(6)
I338 74 11 SIN4 7 6 2L30 B11 4328 D1 I354 F5
ANTI_PLOP 3341 100R DAT A A(9) F326 8 44 F327 AD(7)
4326 4K7 3L28 F385 73 12 ADTRG
7 8 7
30 2L31 B11 4L03 H5 I357 C5
HDMI_INT_MUX A(10) F328 0 D
4327 RES +3V3_STBY 100R 72 13
RES 3L26 100R I388 WAGC_SW F329 6 9 A 8
32 2L32 B12 4L20 A11 I359 G5
HDMI_INT_MAIN A(11) 8M-1
D HDMI_INT_SIDE
POWER_DOWN
4328 RES 100R 3L63 HDMI_INT 3L17 F361 71 14
15
P9<0:7>
20 I341
A(12)
A(13)
F331
F332
5
4
10
11
9
10
34
36
D 2L33 B12
2L34 C11
4L21 A11
4L24 A11
I362 D6
I364 D5
TA4OUT I342 IL31 12 11 2L35 C12 4L25 A11 I365 G3
F379 3346 100R DDC_RESET A(14) F333 3 39
BZX384-C3V3
RES 6317
A(0) 0 INT 1
3349 10K +3V3_STBY A(18) F338 17 A-1
A(1) 69 16 IBO_IRQ A(19) F339 16 3307 F7 5306 E12 I374 I11
+12V_DISP 1 2 3350 10K 18
A(2) 68 2 ZP +3V3_STBY RES 3309 I6 6301 A1 I376 I12
I380 A(3) 67 15 I396 3397 47K 3326 100R F340 15 3310 A6 6306 I2 I380 E1
3 NMI +3V3_STBY CPU_RST RB
I393 6318 A(4) 66 ADDR 9 I397 3L67 100R ITV_SPI_CLK F341 12 9 3311 I6 6307 I3 I384 H3
7317 0V8 3L04 65 4 XCOUT
8 I398 100R ITV_SPI_DATA_I N 100R F366 11 RP
10
A(5) 5 XCIN 3388 3336 WE 3313 B5 6308 H8 I387 B3
BC847BW A(6) 64 I367 3382 100R F367 28 NC 13 3314 B3 6309 I8 I388 D6
1K5 PDZ8.2-B 6 F356 OE
2338
220n
3395
A(7) I389 C5
RES 2319 100n +3V3_SW 3315 B5 6310 I8
E BC847BW
+3V3_STBY
7
D<0:7>
P8<0:7>
+3V3_STBY
3L76 2K2
WR
47 CE
BYTE E 3316 B2 6311 I9 I390 C6
3317 B5 6312 I9 I391 H6
28 5306 30R
27
46
RD +3V3_SW
4K7
4K7
D<0:7> TA0OUT 3318 B3 6317 D1 I392 H6
TXD2 CE 3319 A2 6318 E2 I393 E2
3399
A<0:7>
10K
8
AN2<0:7> 27 I366
TB5IN +3V3_STBY 100n PCA9515A 3321 B3 7303 G12 I396 E5
100K A(8:19) P2<0:7> TA0IN IIC_SCL_up 3322 B5 7308 E1 I397 E5
0V6 3L62 100R VCC
3360
3359
RES RXD2 RES
4323 A(8) 61 4301 3323 B3 7310 C10 I398 E5
59
8 SCL2
26 NC F305 SDM F350 IIC_SDA_up IIC_SDA 3324 B5 7311 B3 IL20 A12
7L10 A(9) 9 TA1OUT
3 SDA0 SDA1 6
7323-2 +3V3_STBY BC847BW A(10) 58 3L79 10K +3V3_STBY 3325 B1 7312 A1 IL21 A13
10 V 3326 E10 7314 F6 IL22 A12
NL27WZ08USG A(11) 57
11 CLK2
25I351 3L56 100R
3L72
A(12)
8
12 ADDR V
TA1IN IIC_SCL_up IIC_SCL
IL25 5 A(13) 55 2 SCL0 SCL1 7 3330 A6 7322 C6 IL25 F1
3L15
F CE 3
6
A(14)
A(15)
54
53
13
14
V
CTS2
RES 3301 100R
SAW_SW
FPGA_BL_BOOST
+3V3_STBY +3V3_STBY +3V3_STBY
5 EN 1
F 3336 E9
3338 D3
7323-1 G1
7323-2 F1
IL26 G2
IL30 C6
330R 15 RTS2 NC NC+3V3_SW
24 IL32 3L16 1K0 +3V3_SW NC GND 3339 D3 7L10 F3 IL31 D6
TA2OUT
2320
100n
3 RES 3L93 4K7 IL32 F7
4
10K
P3<0:7> W
23 3L58 100R 1 +5V_SW
3341 D3 F302 B6 IL33 F6
3K3
3K3
4
TA2IN
3306
3353
52 2324 1u0
1K0
10K
A(16) 16 W 7314 3343 I2 F303 G6 IL34 I11
2323
100n
RES 4306
RES 4307
1 A(18) 50 ADDR I359 BACKLIGHT_BOOST 7303 3346 D5 F305 F5 IL37 B6
8
18 100R PCA9515ADP
7 IL26 A(19) 49 21 3L60 F370 DVB_SW 7L23 F309 G5
3347 D5 IL38 B6
RES 3L14
19 TA3IN
2 48 F303 HDMI_RST_MUX 8 M24C64-WMN6 VCC
3362
3361
0 3348 D5 F310 C10 IL39 D6
7323-1 47 RES FOR BDS 3L12 3K3 +3V3_STBY
NL27WZ08USG 46 1 P7<0:7>
3352 3K3 Φ IIC_SDA_SIDE 3349 D5 F311 C10
4
4316
33 3354 100R 5 EN 1 3355 G11
WR TXD0
4 3L54 NC NC NC 3356 C7 F318 D12
43 3L02 100R F309 3L01 4K7 100R GND
WRH SDA0 +3V3_STBY F345 3357 C5 F319 D10
22R I368 BHE CTS0 RES
RD 3384 42 32 3359 F13 F320 D12
4
RD CTS1
3L94 4K7 41 BOOT LOADER 4313 3360 F13 F321 D10
+3V3_STBY 40 BCLK RTS1
3L03 10K
3L73 I384 39 HLDA CLKS1
31 +3V3_STBY PANEL BOLT_ON_SDA F387 RES 4314 IIC_SDA RES 4304
3361 G13 F322 D12
47K HOLD CLK1 3362 G13 F323 B6
ALE_EMU +3V3_STBY 38 +3V3_STBY BOLT_ON_SCL F388 RES 4315 IIC_SCL
For Development only
3386 100R ALE SCL1 RES 4L03 RES 4305 3380 D5 F324 D10
3L95 4K7 37 30 3382 E7 F325 D12
+3V3_STBY RDY RXD1 1311
3L06
3L07
29
10K
10K
3L10
4302
4303
RES
RES
1R0
12
62
94
PESD3V3L1BA
1 3 1 F339 E10
2
2329 1n0
2330 1n0
2331 1n0
1n0
2
2335 1n0
2336 1n0
1n0
F348
2332 1n0
ITV_SPI_DATA_I N 440054-7 3L02 G5 F340 E10
BZX384-C6V8
BZX384-C6V8
BZX384-C6V8
BZX384-C6V8
1308
1309
1310
1307
5
6312
3
6306
1302
6307
1303
6310
6311
RES 6309
EMC
440054-3
EMC
EMC
EMC
1n0 2333
2337
7
I 8
F352
F354
IBO_IRQ
STANDBY
I 3L05 B5
3L06 H6
F343 I3
F344 I3
1
9
RES
RES
RES
1n0
RESET_n 3L08 H6 F346 I5
11
4310
4309
12 3L09 H6 F347 I5
3309 75R IBO_CVBS_IN 3L10 H11 F348 I5
2340
2339
RES
13
RES
3L11 C7 F349 I5
1415 3311 75R TO / FROM IR/ LED & KEYBOARD 3L12 G7 F350 F8
H_17370_009.eps 3L13 G7 F351 I5
3139 123 6273.1 010804 3L14 G9 F352 I5
1 2 3 4 5 6 7 8 9 10 11 12 13
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 53
220R ANTSTO
2C23
2C22
100n M4 2C13 B8
AVCC1
3C01
1C24
24M0
TxFPGAe_0p
1M0
N4 A14 7C01-1 2C14 B8
AVCC2 TA1P TxFPGAe_0n
N5 B14 SVP WX68 2C15 B8
WX_AVCC AVCC3 TA1M TxFPGAe_1p 3C02
P4 A15
2C26
2C25
2C24
AD(0:7)
100n
100n
100n
M3 A18 TxFPGAe_3p WX_PAVDD2 2C82 2n7 R4 Y6 2C06 100n FRONT_CVBS_SVHS_Y_IN 2C20 D8
TMDS_GND2 TD1P PLF2 Y_G3
N3 B18 TxFPGAe_3n AD(0) 3C04-1 1 8100R L17 W2 SC1_RF_OUT_CVBS
TMDS_GND3 TD1M AD0 CVBS_OUT1 2C21 D8
P3 A19 TxFPGAe_4p AD(1) 3C04-2 2 7100R L18 V2 SC2_CVBS_MON_OUT
TMDS_GND4 TE1P
TxFPGAe_4n AD(2)
AD1 CVBS_OUT2 2C22 A1
R1 B19 3C04-3 3 6100R L19 V9 2C07 100n SVHS_C_IN
TMDS_GND5 TE1M TxFPGAe_CLKn AD2 C 2C23 A1
M2 B17 AD(3) 3C04-4 4 5100R L20 W9 2C08 100n HD_PB_IN
RX0- TCLK1M AD3 PB_B1
B M1
N2
RX0+ TCLK1P
A17
F19
TxFPGAe_CLKp
TxFPGAo_CLKn
AD(4)
AD(5)
3C05-1 1
3C05-2 2
8100R
7100R
K17
K18
AD4 PB_B2
Y9 2C09
Y10 2C10
100n
100n
SC1_B_IN
SC1_CVBS_IN
B 2C24 B2
2C25 B2
NC
RX1- TCLK2M TxFPGAo_CLKp AD5 PB_B3
N1 E20 AD(6) 3C05-4 4 5100R K19 Y8 2C11 100n HD_PR_IN 2C26 B1
RX1+ TCLK2P TxFPGAo_4n AD6 PR_R1
P2 H19 A(0:7) AD(7) 3C05-3 3 6100R K20 W8 2C12 100n SC1_R_IN
RX2- TE2M TxFPGAo_4p A(0)
AD7 PR_R2 2C27 B1
+3V3_SW 5C08 FC03 WX_REGVCC
P1
RX2+ TE2P
G20 3C06-4 4 5100R N17
ADDR0 PR_R3
V8 2C13 100n SC2_Y_CVBS_IN
WX_REGVCC R5 G19 TxFPGAo_3n A(1) 3C06-3 3 6100R N18 V4 2C14 100n IBO_CVBS_IN 2C28 C1
REGVCC TD2M ADDR1 FS1
TxFPGAo_3p 2C29 C1
10u 6.3V
2C28
100n
3C40
3C41
RES
4K7
4K7
100n
100n
3C03-4 C6
RES
3C42
3C43
3C44
RES
4K7
4K7
4K7
2C21
2C20
FPGA_BL_DIMMING 4K7 220R 3C04-2 B6
IC02
3C04-3 B6
7C04 3C24 BL_ADJUST
3C04-4 B6
100n
BC847BW
RES 100R 3C05-1 B6
3C07
3C05-2 B6
D 100R
D
2C30
RES 3C05-3 B6
2C74
IC01 22u 3C05-4 B6
3C25 10K 7C02 3C06-1 C6
BC847BW
3C06-2 B6
RES
2C73 3C06-3 B6
10u 3C06-4 B6
3C07 D9
RES 3C08 C6
4C08 3C09 C6
3C10 C6
3C19 C8
E RES E 3C20 C9
3C22 D10
+5V_SW
7C03-1
+3V3_SW
FOR ITV ONLY 3C23 D11
3C24 D11
14
74LCX14T
3C25 D9
3C29
4K7
22R 3C32 F2
7C03-2
3C33 F2
14
74LCX14T
PC_VGA_V
3C34 F3
+5V_SW 3 4 3C34
3C36 F3
F 22R F 3C37 G3
3C39 C1
7
2C33 3C40 C2
3C32
4K7
7C03-3
14
74LCX14T 3C41 C2
100n
3C33 3C36 3C42 D2
VGA_V 5 6
3C43 D2
22R 22R 3C44 D2
4C07 C8
7
14
14
7C02 D10
7C03-1 E2
7C03-2 F2
7C03-3 F2
7C03-4 G2
7C03-5 G4
7C03-6 G5
H_17370_010.eps
3139 123 6273.1 010804 7C04 D10
FC01 A2
1 2 3 4 5 6 7 8 9 10 11
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 54
2D33
3D15
100n
1K0
220R 2D37 C8
22u 6.3V
2D71
2D72
2D38 C9
10n
DDR_VREF 2D39 C9
2D43 C8
B B
RES 2D31
2D32
2D34
3D16
100n
100n
100n
1K0
2D46 C7
2D57 C8
2D58 C8
2D59 C9
2D60 C9
2D71 B2
2D72 B2
+2V5_VDDMQ +2V5_VDDMQ 3D01-1 E4
3D01-2 E4
3D01-3 E4
470p
100n
470p
100n
470p
470p
100n
100n
100n
100n
3D01-4 E4
10n
10n
10n
10n
10n
10n
3D02-1 E4
C C
2D18
2D46
10u
10u
3D02-2 E4
2D02
2D04
2D03
2D43
2D11
2D12
2D57
2D58
2D59
2D60
2D08
2D09
2D37
2D38
2D39
2D10
3D02-3 D4
3D02-4 D4
3D05-1 D4
3D05-2 D4
3D05-3 D4
1
18
33
15
55
61
18
33
15
55
61
7D01 7D02 3D05-4 D4
K4D261638K K4D261638K
3D06-1 D4
VDD VDDQ VDD VDDQ 3D06-2 D4
WX_MA0 29 2 1_DQ0 3D06-1 1 8 22R WX_MD4 WX_MA0 29 2 2_DQ16 3D43-1 1 8 22R WX_MD20
A0 DQ0 A0 DQ0 2_DQ17 3D06-3 D4
WX_MA1 30 4 1_DQ1 3D06-2 2 7 22R WX_MD5 WX_MA1 30 4 3D43-2 2 7 22R WX_MD21
A1 DQ1 A1 DQ1
WX_MA2 31
A2 DQ2
5 1_DQ2 3D06-3 3 6 22R WX_MD6 WX_MA2 31
A2 DQ2
5 2_DQ18 3D43-3 3 6 22R WX_MD22 3D06-4 D4
D WX_MA3
WX_MA4
32
35
A3
A4
DQ3
DQ4
7
8
1_DQ3
1_DQ4
3D06-4
3D05-4
4
4
5
5
22R
22R
WX_MD7
WX_MD3
WX_MA3
WX_MA4
32
35
A3
A4
DQ3
DQ4
7
8
2_DQ19
2_DQ20
3D43-4
3D44-4
4
4
5
5
22R
22R
WX_MD23
WX_MD18 D 3D09 F1
3D10 G1
WX_MA5 36 10 1_DQ5 3D05-3 3 6 22R WX_MD2 WX_MA5 36 10 2_DQ21 3D44-3 3 6 22R WX_MD16
WX_MA6 37
A5 DQ5
11 1_DQ6 3D05-2 2 7 22R WX_MD1 WX_MA6 37
A5 DQ5
11 2_DQ22 3D44-2 2 7 22R WX_MD17 3D11 F1
A6 DQ6 A6 DQ6 3D14 G1
WX_MA7 38 13 1_DQ7 3D05-1 1 8 22R WX_MD0 WX_MA7 38 13 2_DQ23 3D44-1 1 8 22R WX_MD19
A7 DQ7 A7 DQ7
WX_MA8 39
A8 DQ8
54 1_DQ8 3D02-4 4 5 22R WX_MD15 WX_MA8 39
A8 DQ8
54 2_DQ24 3D47-4 4 5 22R WX_MD31 3D15 B4
WX_MA9 40 56 1_DQ9 3D02-3 3 6 22R WX_MD14 WX_MA9 40 56 2_DQ25 3D47-3 3 6 22R WX_MD30 3D16 B4
A9 DQ9 A9 DQ9
WX_MA10 28 57 1_DQ10 3D02-2 2 7 22R WX_MD12 WX_MA10 28 57 2_DQ26 3D47-2 2 7 22R WX_MD28
A10|AP DQ10 1_DQ11 A10|AP DQ10 2_DQ27
3D38 F7
WX_MA11 41 59 3D02-1 1 8 22R WX_MD13 WX_MA11 41 59 3D47-1 1 8 22R WX_MD29
A11 DQ11 A11 DQ11 3D40 F7
60 1_DQ12 3D01-1 1 8 22R WX_MD9 60 2_DQ28 3D48-1 1 8 22R WX_MD24
DQ12 DQ12 3D43-1 D10
62 1_DQ13 3D01-2 2 7 22R WX_MD8 62 2_DQ29 3D48-2 2 7 22R WX_MD25
DQ13 DQ13
DQ14
63 1_DQ14 3D01-3 3 6 22R WX_MD10
DQ14
63 2_DQ30 3D48-3 3 6 22R WX_MD26 3D43-2 D10
49 65 1_DQ15 3D01-4 4 5 22R WX_MD11 49 65 2_DQ31 3D48-4 4 5 22R WX_MD27 3D43-3 D10
DDR_VREF VREF DQ15 DDR_VREF VREF DQ15
3D43-4 D10
E WX_CS0#
WX_MCK0
24
45
CS_
CK NC1
14
WX_CS0#
WX_MCK0
24
45
CS_
CK NC1
14
E 3D44-1 D10
WX_MCK0# 46 17 WX_MCK0# 46 17 3D44-2 D10
CK_ NC2 CK_ NC2
WX_CLKE 44
CKE NC3
25 WX_CLKE 44
CKE NC3
25 3D44-3 D10
43 NC 43 NC 3D44-4 D10
NC4 NC4
WX_BA0 26 53 WX_BA0 26 53
BA0 NC5 BA0 NC5 3D47-1 E10
WX_BA1 27 42 WX_BA1 27 42
BA1 NC6 BA1 NC6 3D47-2 E10
WX_DQM0 20 WX_DQM2 20 3D47-3 D10
LDM LDM
WX_DQM1 47
UDM
WX_DQM3 47
UDM
3D47-4 D10
WX_DQS0 3D11 15R 1_DDQS0 16 WX_DQS2 3D38 15R 2_DDQS2 16 3D48-1 E10
LDQS LDQS
WX_DQS1 3D09 15R 1_DDQS1 51 WX_DQS3 3D40 15R 2_DDQS3 51
UDQS UDQS 3D48-2 E10
19 19
WX_WE# 21
DNU1
50 WX_WE# 21
DNU1
50 3D48-3 E10
WE_ DNU2 WE_ DNU2 3D48-4 E10
F WX_CAS#
WX_RAS#
22
23
CAS_
RAS_
WX_CAS#
WX_RAS#
22
23
CAS_
RAS_
F 5D03 B1
VSS VSSQ VSS VSSQ 7D01 D2
7D02 D8
FD01 B2
51R
51R
34
48
66
12
52
58
64
34
48
66
12
52
58
64
6
6
ID01 G2
ID01 ID05
ID05 G8
3D10
3D14
2D14
10n
G G
H_17370_011.eps
3139 123 6273.1 010804
1 2 3 4 5 6 7 8 9 10 11
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 55
22u 6.3V
100n
100n
100n
100n
150R 2E68 2E13 G2 IE11 D6
100n
10u 6.3V
2E67
2E14 G2 IE12 F6
2E48
2E15 G2 IE15 C9
2E47
2E44
2E45
2E46
2E16 G2
5E13 FE07 2E17 G2
+1V2_PLL 2E18 G2
22u 6.3V
150R 2E19 C6
2E70
2E69
100n
33R 7C01-4
SVP WX68 2E25 D6
2E71
100n
2E72
10u 6.3V
D13 C9 K3
VDDC3 VSS3 220R MVREF 2E29 E6
2E19
2E20
100n
+1V2_CORE D14 C12 WX_DQS3 E3
VDDC4 VSS4 DQS3
D15 D2 WX_DQS2 B2 2E30 E6
VDDC5 VSS5 DQS2
E13 H8 WX_AVSS_OUTBUF WX_DQS1 B6 2E31 F6
VDDC6 VSS6 DQS1
E14 H9 WX_DQS0 B9 +3V3_SW
100n
100n
100n
100n
100n
100n
100n
100n
100n
VDDC7 VSS7 DQS0 2E32 F6
10u 6.3V
2E57
2E55
2E54
2E53
2E51
2E58
2E52
2E50
2E49
2E35 D2
10u 6.3V
H16 H13 WX_DQM1 A6
VDDC11 VSS11 220R DQM1
RES
2E21
2E22
3E05
100n
J5 J8 WX_DQM0 A9 2E36 D2
4K7
VDDC12 VSS12 DQM0 VS NC
J16 J9 WX_MCK0# A12 P17 DP_HS 2E37 D2
VDDC13 VSS13 MCK0_ HS
K5 J10 WX_AVSS_BG_ASS WX_MCK0 IE05 E1 P19 DP_HS
K16
VDDC14 VSS14
J11 +3V3_SW D1
MCK0 DPB_HS
V19
NC 2E38 D2
VDDC15 VSS15 CS1_ DPB_VS NC 2E39 D2
R16 J12 WX_CS0# IE06 J3 V20 HDMI_H
VDDC16 VSS16 3E02 CS0_ DPA_HS
2E40 D2
3E06
+2V5_VDDMQ T14 J13 WX_PAVDD1 WX_WE# IE07 J4 Y19 HDMI_V
4K7
VDDC17 VSS17 WE_ DPA_VS
10u 6.3V
T15 K8 WX_CAS# IE08 K1 Y20 HDMI_DE 2E41 D3
VDDC18 VSS18 22R CAS_ DPB_DE
2E23
2E24
IE09
100n
B4 K9 WX_RAS# J1 W20 HDMI_VCLK 2E42 D3
VDDM1 VSS19 RAS_ DPA_CLK
C4 K10 WX_MD31 J2 Y15
100n
100n
100n
100n
100n
100n
100n
100n
470p
470p
10u 6.3V
2E37
2E39
2E75
2E76
2E36
2E42
D D
2E38
2E25
2E26
100n
E6 L8 WX_MD26 A1 W13 HDMI_Cr(5) 2E47 A4
VDDM7 VSS25 MD26 DPA19
E9 L9 WX_MD25 A2 Y13 HDMI_Cr(4)
E10
VDDM8 VSS26
L10 WX_PAVSS2 WX_MD24 A3
MD25 DPA18
Y14 HDMI_Cr(3)
2E48 A3
VDDM9 VSS27 MD24 DPA17 2E49 C3
E11 L11 WX_MD23 C5 W14 HDMI_Cr(2)
VDDM10 VSS28 MD23 DPA16
+3V3_SW E12 L12 +1V2_ADC WX_MD22 A4
DPA15
V14 HDMI_Cb(9) 2E50 C3
+2V5_VDDMQ +3V3_SW VDDM11 VSS29 MD22
F5 L13 IE11 WX_MD21 B5 U14 HDMI_Cb(8) 2E51 C3
5E16 FE01 VDDM12 VSS30 5E08 MD21 DPA14
WX_AVDD3_ADC1 G5 M8 WX_AVDD_ADC1 WX_MD20 A5 U15 HDMI_Cb(7) 2E52 C3
VDDM13 VSS31 MD20 DPA13
10u 6.3V
10u 6.3V
L16 M9 WX_MD19 D6 V15 HDMI_Cb(6)
220R VDDH1 VSS32 150R MD19 DPA12 2E53 C2
2E01
2E02
3E07
2E27
2E28
100n
100n
M16 M10 WX_MD18 A7 W15 HDMI_Cb(5)
VDDH2 VSS33 MD18 DPA11
0R
10u 6.3V
NC P20 N11 WX_MD11 A8 W17 HDMI_Y(6)
220R NC VSS40 150R MD11 DPA4
2E67 A2
2E03
2E04
2E29
2E30
100n
100n
WX_AVDD3_ADC1 Y3 N12 WX_MD10 D9 Y17 HDMI_Y(5)
AVDD3_ADC1 VSS41 MD10 DPA3
WX_AVDD3_ADC2 U9 N13 WX_MD9 D10 Y18 HDMI_Y(4) 2E68 A1
AVDD3_ADC2 VSS42 MD9 DPA2
+3V3_SW WX_AVSS_ADC2 WX_AVDD3_OUTBUF U3 P18 WX_AVSS_ADC2 WX_MD8 C10 W18 HDMI_Y(3)
AVDD3_OUTBUF VSS43 MD8 DPA1 2E69 B2
E2 T16 WX_MD7 B10 V18 HDMI_Y(2)
5E03 E8
VDDR1 VSS44
H20 +1V2_ADC WX_MD6 A10
MD7 DPA0
W19
2E70 B1
220R FE03 VDDR2 VSS45 WX_AVSS_OUTBUF MD6 DPB15 NC 2E71 B1
WX_LVDS_VDD WX_AVDD3_BG_ASS V3 Y2 IE12 WX_MD5 A11 U18
AVDD3_BG_ASS AVSS_OUTBUF 5E10 MD5 DPB14 NC
WX_PAVDD1 T3 E4 WX_AVDD_ADC3 WX_MD4 B11 U19 HDMI_Cb(1) 2E72 B2
10u 6.3V
2E06
2E07
2E08
100n
100n
100n
10u 6.3V
WX_PAVDD2 T4 E7 WX_MD3 C11 U20 HDMI_Cb(0) 2E75 D3
PAVDD2 VSSR2 150R MD3 DPB12
2E31
2E32
100n
WX_AVDD_ADC1 U5 W3 WX_AVSS_BG_ASS WX_MD2 D12 T20 HDMI_Cr(1) 2E76 D3
AVDD_ADC1 AVSS_BG_ASS MD2 DPB11
WX_LVDS_VSS WX_AVDD_ADC2 U7 T2 WX_PAVSS1 WX_MD1 A13 T18 HDMI_Cr(0)
WX_AVDD_ADC3 T8
AVDD_ADC2 PAVSS1
R3 WX_PAVSS2 WX_AVSS_ADC3 WX_MD0 B13
MD1 DPB10
T17 HDMI_Y(1)
2E77 E3
AVDD_ADC3 PAVSS2 MD0 DPB9 3E02 C7
+1V2_PLL WX_AVDD_ADC4 U6 T5 WX_AVSS_ADC1 WX_MA11 C13 R19 HDMI_Y(0)
F 5E04 FE04 +1V2_PLL
D18
AVDD_ADC4
LVDS_VDDP
AVSS_ADC1
AVSS_ADC2
T7 WX_AVSS_ADC2 +1V2_ADC WX_MA10 F1
F2
MA11
MA10
DPB8
R20 F 3E04 D7
WX_AVDDAPLL E17 T9 WX_AVSS_ADC3 5E11 WX_MA9 3E05 C11
LVDS_VDDA AVSS_ADC3 MA9
10u 6.3V
2E09
100n
10u 6.3V
WX_AVDDAPLL C17 E18 WX_MA7 F4
LVDS_VDDO1 LVDS_VSSP 150R MA7 3E07 E3
2E33
2E34
100n
W7 WX_MA0 H3
150R VREFP_2 MA0 5E08 D7
2E12
2E11
100n
H4
5E09 E7
5E10 F7
G 100p
WX_AVSSLLPLL
G 5E11 F7
2E13
2E14 100p 2E15 100p
5E12 A1
5E13 B1
5E14 B1
2E17 100p 2E16 100p 5E16 D1
2E18 100p 5E17 E1
7C01-2 B10
7C01-4 B4
H_17370_012.eps
3139 123 6273.1 010804
FE01 D2
FE02 E2
FE03 F2
1 2 3 4 5 6 7 8 9 10 11
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 56
2
I205 2214 27M0 2213 B6
10u
2214 B7
7202 RES RES
2211 EPCS16SI16N 2212 2213
3201 E5
1
10n 7201 RES 3 10n 10n 3202 E5
B EPCS4SI8 VCC
B 3203 E2
3
4
8
Φ NC 5 3204 E2
VCC F222
1 nCSO nCSO 7 SCD 6
Φ CS_ CS +3V3_FPGA
3205 E2
+3V3_FPGA
2 F223 3206 E2
SCD 6 DCLK DCLK 16 8
DATA DCLK DCLK DATA 3207 G5
F224
5 ASDO ASDO 15 11 RES 3222 F5
ASDI ASDI
3224 F5
(FOR DEVELOPMENT)
SOFTWARE DEBUGGER
GND NC 13 3225 G5
4
14
GND 1203
3231 C7
TMS_FPGA 3232 C7
10
F204 3246 100R JTAG_TMS
1
F227 TDI_FPGA F208 3240 100R F236 JTAG_TDI 3234 C7
TDO_FPGA 2
DATA0 DATA0 F202 3235 100R JTAG_TDO 3235 C7
C TCK_FPGA F225 3234 100R F201 JTAG_TCK
3
4 C 3236 A8
F207
5 3238 C7
RES +3V3_FPGA 6 3240 C7
3238 1K0
440054-6 3246 C7
3247 F5
3248 G5
4201 F2
4202 F2
4203 G2
4204 G3
4205 G2
D D 5201 A2
5202 A7
7201 B3
7202 B4
F201 C9
F202 C7
IIC_SCL_up 3201 100R MAIN_SCL F204 C7
IIC_SDA_up 3202 100R MAIN_SDA F207 C9
F208 C7
+3V3_FPGA RES RES F209 E3
TO DRIVE IC AL DRIVERS 2201 2202
F211 E1
100p 100p
F214 E3
E 3204 3203
E F222 B4
F223 B4
1K5 1K5
F224 B4
AMBI_SCL I209
100R 3205 S_SCL F209
F225 C7
F227 C4
F211
AMBI_SDA 100R 3206 S_SDA F214 F236 C9
F237 B8
I201 A6
2204 2203 I205 B2
1n0 1n0
I206 G2
2 CONNECTORS
I207 G2
I209 E1
F +3V3_FPGA +3V3_FPGA
OVERLAPPING 5PIN & 7PIN
F I210 F4
1202
RES I211 F4
1201
440054-5 440054-7 FOR PWM AL DRIVER I212 F4
I213 G4
4202
4201
1 1 I210 ambi_pwm(0)
RES
3247 100R
2 2 I211 3222 100R ambi_pwm(1) I232 A7
3 3 I212 3224 100R ambi_pwm(2)
I2S_SEL1 4 4 3225 100R ambi_pwm(3)
I207 I2S_SEL2 5 5 3207 100R ambi_pwm(4)
I206 6 I213 3248 100R ambi_pwm(5)
7
4205
4203
4204
RES
G G
1n0
1n0
1n0
1n0
2209 1n0
2210 1n0
2206
2208
2205
2207
H_17370_013.eps
3139 123 6273.1 010804
1 2 3 4 5 6 7 8 9 10
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 57
180R
3714
NC J1 J5 B16 H9
3 CONFIG F734 4707 C12
H16 L13 G14 J14
3751 4 CLK CONF_DONE GND
4708 C12
TxFPGAo_CLKn 22R H15 K14 VCCIO3 J3
5
TxFPGAe_CLKp 3752 22R J15 J13 R16 J8 4709 C12
6 0
J16 MSEL K12 F733 +2V5in-FPGA J9 4710 C12
7 1
180R
3713
7700-2 M10 K9 4711 C12
EP2C5F256C7N TCK
F2 TCK_FPGA M7 M8
TxFPGAe_CLKn 3753 22R F1 G1 TMS_FPGA P10 M9 4712 C12
Φ H4
DATA0 TMS
G2 TDO_FPGA 4701 P7 VCCIO4 P8 4713 D12
DCLK TDO 3702
ASDO C3 BANK1 DATA0 H5 TDI_FPGA RES T15 P9 4714 D12
10K
G nCSO F4
P1
IO_C3|ASDO
IO_F4|CSO_ IO_E3|LVDS7p
E3
E4 NC DCLK
TDI
+1V2-FPGA
T2 GND R15
R2
G 4715 D12
MAIN_SDA FPGA_BL_BOOST IO_P1|LVDS0p IO_E4|LVDS7n 4716 D12
P2 D5 I712 ambi_pwm(4) G9 T1
IO_P2|LVDS0n IO_D5|LVDS8p 4717 D12
N1 IO_N1|LVDS1p IO_E5|LVDS8n E5 RES H10 T16
AMBI_SDA N2 C1 I705 ambi_pwm(0) 2734 H7 VCCINT 4718 D12
L1 IO_N2|LVDS1n IO_C1|LVDS9p C2 ambi_pwm(1) 1n0 J7 L5
IO_L1|LVDS2p IO_C2|LVDS9n 4719 D12
L2 IO_L2|LVDS2nIO_L4|PLL1_OUTp L4 +1V2-PLL GND_PLL1 N5 4720 D12
FPGA_BL_DIMMING K4 M4 M5 4721 D12
IO_K4|LVDS3p
IO_M4|PLL1_OUTn 1
K5 IO_K5|LVDS3nIO_F3|VREFB1N0 F3 E12 2
VCCA_PLL D12
K1 J4 NC GND_PLL2 F12 4722 D12
K2 IO_K1|LVDS4nIO_J4|VREFB1N1 L3 L6 4723 C12
IO_K2|LVDS4p IO_L3 1
ambi_pwm(5) E1 IO_E1|LVDS5p IO_M1 M1 F11 2
VCCD_PLL
1
M6 4724 D12
E2 M2 GNDA_PLL E11 4725 D12
ambi_pwm(2) D3 IO_E2|LVDS5n IO_M2 M3 2
I728
H ambi_pwm(3) I713 D4
IO_D3|LVDS6p
IO_D4|LVDS6n
IO_M3
IO_P3
P3 AMBI_SCL H 4726 E12
5700 B1
5701 B1
RES 5702 C1
2700 5703 D1
1n0 7700-4 5704 E1
EP2C5F256C7N
5705 E2
Φ 7700-7
EP2C5F256C7N 7700-1 F8
BANK3 7700-2 G3
D13 M16 Φ
IO_M16|LVDS38p M15
IO_D13|LVDS29p 7700-3 B14
C14 NC
IO_M15|LVDS38n
IO_C14|LVDS29n 7700-4 H13
D16 IO_N16|LVDS39p N16
IO_D16|LVDS30p B8 H6
D15 N15 C15 J10 7700-5 B8
I G13 IO_N15|LVDS39n P16
IO_D15|LVDS30n
IO_G13|LVDS31pIO_P16|LVDS40p
C16 J6 I 7700-6 E14
G12 IO_G12|LVDS31nIO_P15|LVDS40n P15 D1 K13 7700-7 I15
H11 N14 D2 K6 F701 B2
IO_H11|LVDS32p
IO_N14|LVDS41p
J11 IO_N13|LVDS41n N13
IO_J11|LVDS32n D7 K7 F702 B2
NC F16 M12 NC NC D9 K8
IO_M12|LVDS42p N12
IO_F16|LVDS33p NC NC NC
F15 E13 N3 F703 C2
IO_N12|LVDS42n
IO_F15|LVDS33n F704 E2
G15 IO_M14|VREFB3N1 M14
IO_G15|LVDS34p E15 N4
G16 H13 F13 N6 F705 E2
IO_G16|LVDS34n
IO_H13|VREFB3N0
J12 IO_E14|PLL2_OUTp E14
IO_J12|LVDS35p F14 N7 F706 F9
H12 D14 F5 P6 F733 G9
K15 IO_H12|LVDS35n
IO_D14|PLL2_OUTn E16 G4 R6
IO_K15|LVDS36p IO_E16 F734 F9
K16 IO_K16|LVDS36n IO_L14 L14
L16 P14 I705 G4
IO_L16|LVDS37p IO_P14
L15 I712 G4
J IO_L15|LVDS37n
J I713 H2
I728 H2
H_17370_014.eps
3139 123 6273.1 010804
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 58
470p
1n5
+AUDIO_POWER_+12V_DISP 2414 B2 I431 D4
220u
4401 COM
25V
+12V_DISP
2415 B3 I432 D2
2439
470n
4402
A A 2416 B3
2408
2409
2417 B7
2410
+5V_D
+5V_D 2418 B7
5401 I426 F402 F403
2411
2419 C3
3402 120R +5V_AUD
+5V_SW 10u 2420 C6
2440
470n
2412
220p
2441
2442
470p
2413
220p
2443
2444
470p
2421 C7
1n5
1n5
1R0
2422 C7
5402 2423 C6
+5V_AUD
2424 D7
120R
2414 7411 2425 D7
61
62
39
12
13
10u MSP4450P-VK-E8 000 2426 D7
2415
A AH DVSUP 2427 D7
B 3p3 4 1
1411
SUP
Φ AUD_CL_OUT
70 B 2428 D6
2429 D7
18M432
XTALIN 2V4 67 MULTISTANDARD 26 0V6 AUDIO_LS_R 2430 D7
IN R 0V6
SOUND PROCESSOR 27 AUDIO_LS_L 2431 D7
3
2416 XTAL L
2
XTALOUT 2V4 68
OUT 2432 D2
28
RST_AUD
3p3
19
C
2418 2417 2433 D3
RESETQ DACM 330p 330p 2434 D3
80 29
+5V_AUD STNDBYQ SUB
100n 2419 66 2435 E3
TESTEN
69 30 2436 E3
TP SR
31 2437 F4
IIC_SCL_up I412 SL
3410 100R 2
IIC_SDA_up 3411 100R I413 3
CL
23 0V2 HP_AUDIO_OUT_R
2438 F4
RES 2446 100p DA I2C R 0V2 2439 A3
79 DACA 24 HP_AUDIO_OUT_L
C RES 2447 100p
I427 4
ADR_SEL L
6V7
+8V C 2440 A3
MOJO_I2S_OUT_SCK 1V4 RES 4408 40 2420 10u 16V 2441 A4
I428 5 CL M
MOJO_I2S_OUT_WS 1V6 RES 4407 2421 2422
WS CAPL 6V3
I414
330p 330p
2442 A4
38 2423 10u 16V
RES HDMI_SCK I429 17
A 2443 A6
CL3 I415
HDMI_WS I430 18 2444 A6
WS3
2445 E3
4409 8 78 2446 C3
IN 0
4410 9 DCTR_IO 77
OUT 1 2447 C3
10 DEL I2S
11
CL
76
3402 A1
WS SPDIF_OUT 3410 C3
MOJO_I2S_OUT_SD RES 4411 I431 7 36 3V8 I416 2424 10u 3417 100R SC1_AUDIO_OUT_R 3411 C3
1 R 3V8 I417
D HDMI_SD I432
4412 16
20
2
3
DA
SC1_OUT
L
37
3V8
2425 10u 3418 100R SC1_AUDIO_OUT_L
D 3416 D2
3417 D8
21 33 I418 2426 10u 3419 100R SC2_AUDIO_OUT_R
4
SC2_OUT
R
34 3V8 I419 2427 10u 3420 100R SC2_AUDIO_OUT_L
3418 D8
L 3419 D8
6
DA_OUT
41 3420 D8
I420 I421 1V5 63 R
SIF 2432 56p 2433 330p SC3_OUT 42 2428 2429 2430 2431 4401 A1
I422 IN1+ L 100p 100p 100p 100p
RES 3416 470R 2434 330p 64
5403 22u IN- ANA 4402 A1
2435 330p I423 65
IN2+ 4407 C3
UAB-09
2436 10u I424 2V6 56 1 4408 C3
VREFTOP
2445 100n 22 4409 D3
SC1_AUDIO_IN_R 55 32 4410 D3
R
SC1_AUDIO_IN_L 54 SC1_IN 46
L 4411 D3
47
E SC2_AUDIO_IN_R 53
R
NC 71 E 4412 D3
5401 A1
SC2_AUDIO_IN_L 52 SC2_IN 72
L
73 5402 B1
COMP_AUDIO_IN_R 51 74 5403 E2
R
COMP_AUDIO_IN_L 50 SC3_IN 75
L 7410 A3
SIDE_AUDIO_IN_R 49
7411 B4
R F401 A4
SIDE_AUDIO_IN_L 48 SC4_IN
L
F402 A4
HDMI_AUDIO_IN_R 58 F403 A5
R
HDMI_AUDIO_IN_L 57 SC5_IN
L I412 C3
VSS VREF I413 C3
I414 C6
F AGNDC A AH D 1 2
F I415 C6
45
59
60
43
44
14
15
35
25
I425
I416 D6
I417 D6
UAB-09
I418 D6
2438
100n
2437
10u I419 D6
I420 D3
I421 D4
H_17370_015.eps
3139 123 6273.1 010804 I422 D4
I423 E4
1 2 3 4 5 6 7 8 9
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 59
SSB: Audio
1 2 3 4 5 6 7 8 9 10 11
1A01 D11 FA11 E11
1A02 C11 FA12 E2
2A46
RES 4A02 2A15 D3 IA05 D2
47n
10n
1n0
10n
1n0
2A16 E3 IA06 D3
2A17 D8 IA07 D6
RES
2A52
RES
2A50
2A53
2A51
2A19 E4 IA10 E2
2A47
2A20 E3 IA11 E2
47n
TO / FROM PSU
100n
100n
3A04 12K 22K
5A03 2 2A47 B6 IA36 E7
3A06 10K 6K8 IA34
IA23 22u 2A13 2A37 IA04 3A05 3
3A07 10K 6K8 2A50 B1 IA37 E8
3A08 12K 22K 22R 440054-3 2A51 B1 IA38 F7
220n 220n
2A09
2A10
3A11 10K 6K8 3A09 2A52 B2 IA39 F7
10R GNDSND
D 7A01 GNDSND GNDSND
2A14
470n
2A17
TO SPEAKERS D 2A53 B2
2A54 B2
IA40 A6
IA41 A6
FA05 * IA01 IA02 TDA8932T IA35
1n0
29
20
AUDIO_LS_L 3A03 2A11 1u0 1A01 3A01 B6
8
VDDA 440054-4
*
3A04 2A12
2
220p IN1P
Φ
CLASS D
VDDP
OUT1
27 IA03 2A21
1n0
FA07
1 LEFT +
3A02 B8
3A03 D2
-2V8 FA08
3A06
IA05 IA06 POWER 2 GND 3A04 D3
FA06 ** 3A07
2A15
2A16
1u0
1u0 IA09
3
-2V8
IN1N AMPLIFIER OUT2
22 IA07
EMC 2A18 IA36 GNDSND
FA10
FA11
3
4
GND
RIGHT -
3A05 D9
15 4 2V6 FA04 1n0 3A06 D2
IA10 *
3A08 2A19 -2V8
220p
IN2P DIAG
3A07 E2
14 30 2A35
AUDIO_LS_R
FA09
3A11 * IA11
2A20 1u0
IA12
-2V8
IN2N HVP1 NC GNDSND
1M0
1n0 2A45
1n0 2A28 2A23
3A08 E3
3A09 D7
2A22 100n IA13 12 19 3A12
INREF HVP2 NC 470n 1n0 3A11 E2
2A24 100n -7V6
E VSSA 3A13 39K IA15 10
OSCREF BOOT1
28 8V9 2A25
IA14
15n
GNDSND 5A04
VDD E 3A12 E6
FA12 IA20 22u 2A26 IA37 2A38 IA17 3A14
3A13 E3
ENGAGE 31 21 3V9 2A27 15n 3A14 E9
NC OSCIO BOOT2 IA16
IA18 220n 220n 22R 3A15 E6
3A29
GNDSND 11 25 3A15 1M0 3A17
47K
HVPREF STAB1 10R GNDSND 3A17 E7
-8V2
IA19 7A05 3A19 F3
2A29 100n 18 24 -1V3
VSSA DREF STAB2 BC857BW
IA33 4V7 IA38 IA30 3A26 F3
3A26 4K7 5
ENGAGE 3A27 F9
3V2 DC_PROT
3A19 IA21 3A28 F9
3A30
STANDBYn 6 2A30 2A31
47K
POWERUP 100n 1n0 FA32 3A29 E10
10K -2V6
IA22 13 3A30 F10
3A31
10K
TEST 7A06 IA31
BC847BW 3A31 F11
F EMC VSSP VSSD|HW VSS IA39
F
2A40
2A32
470n
26
23
1
16
17
32
2A36 4A02 A6
VSSA 1n0 220K GNDSND 5A03 D7
3A28 7A07 5A04 E7
GNDSND GNDSND VSS BC847BW
GNDSND 5A05 C6
100n
100n
220K
GNDSND 5A06 C8
5A07 A6
2A41
VSSA
1u0
2A33
2A34
5A08 B2
5A09 B2
GNDSND GNDSND 7A01 D4
7A05 E11
G GNDSND
GNDSND
DC-DETECTION G 7A06 F10
7A07 F10
FA01 C6
FA02 C8
FA04 E6
FA05 D2
FA06 E2
FA07 D1 1
H_17370_016.eps FA08 D1 1
3139 123 6273.1 010804 FA09 E2
FA10 D1 1
1 2 3 4 5 6 7 8 9 10 11
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 60
4
HP_AUDIO_OUT_L HPIC_LIN 2V6 TS482IDT 2915 3904 3904 A6
2 HPIC_LOUT
470n 47K 3905 B3
F901 2V6 2V6 1 6.3V 47u 33R 3906 B3
3 +5V_SW
ITV Connector E
8
3907 C3
1901 5V3 3908 B4
2908 3909 B6
1 220n 3910 C6
2 2905
3911 D2
B SC2_CVBS_MON_OUT_ITV 3
4 33p
B 3912 D4
6 5 3908 120K 3913 D4
RES 3906 2913 RES
3914 E4
3915 E4
100K 220n 3909 HP_ROUT 3916 F4
I914 7901-2 33R 3917 C4
HP_AUDIO_OUT_R 2904 3905 F904
4
HPIC_RIN 2V6 TS482IDT
2916 3910 3918 D4
6 HPIC_ROUT
470n 47K 3934 D3
2V6 2V6 7 6.3V 47u 33R 3935 E2
5
8
3937 E1
2907
470n
3907
100K 5V3
3938 E2
3940 F3
3942 F5
C C 3943 F6
4901 D3
4902 D2
6914 E2
MUTING CIRCUIT 3 6916 E3
+3V3_STBY 6919 F4
3917 7901-1 A4
1 7911
BC847BW 7901-2 B4
1K0
2 7902 D3
7911 C5
I911 3911 7912 D5
ANTI_PLOP 3 7913 D5
10K 3V3 I912 7914 E5
3918
0V 1 7912
D 7902
BC857BW 1K0
BC847BW D 7915 E5
7916 F5
4902
RES
2
7917 E3
3912
+3V3_STBY
10K
7919 E2
I919 7922 F6
3 SC1_AUDIO_MUTE_R
F901 B3
4901
RES
2
10K
BC847BW
I922
3 SC2_AUDIO_MUTE_L
+3V3_STBY I933
3916
1 7916
BC847BW
1K0
2 ENGAGE
BAS316
3940
6919
RES
10K
F 3942
7922 F
MUTEn 0V 10K BC847BW
3943
22K
H_17370_017.eps
3139 123 6273.1 010804
1 2 3 4 5 6 7
E_06532_012.eps
131004
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 61
PESD5V0S1BA
MSD-244V-131 NIDIP RES 33R 100R 2602 A2
2602
8
2603 D7
1606
RED_RED_RIGHT RES 3601 RES
75R 2600 3604 2606 B2
6610
75R
2607 C3
1601-A 2608 C3
MSP-801V1-07-01-B NI FE 2609 C7
1
2610 D3
F602 2612 D3
3
2613 D6
B 1615-1 5 F614 4
B 2614 D7
2615 E7
6 HD_PB_IN_ITV 2 2616 E7
L RES
3600 A7
1609
6604
3619 HD_PB_IN PESD5V0S1BA 3601 A2
4
PB F615 3602 C7
PESD5V0S1BA
5
F607 RES 33R
MSD-244V-131 NIDIP 2606 3603 D6
3605
1610
75R
100R
RES RES 3609 C6
1608
6606 2609 3611 D2
C I610
PESD5V0S1BA
C 3612 D3
3617 A3
3609
3607 2607
COMP_AUDIO_IN_L
F608 3618 C7
PESD5V0S1BA
PESD5V0S1BA
5602 E7
2610 I611 RES
3611 COMP_AUDIO_IN_R 6604 B7
RES 6611
3603 2603
1607
F609 75R 6606 C7
PESD5V0S1BA
RES
D 6614 3n3 33K
D 6611 D7
6612 C2
6613 C2
FRONT_Y_CVBS_IN_T 2613 100n 5601 33R 6614 D2
+5V_SW
7601 D7
2614 100n 7602 F7
5
7601 7603 F6
RES
4601
74LVC1G3157GW F601 A7
VCC F602 B6
6 1 F604 C6
IN NO
F605 A1
FRONT_CVBS_SVHS_Y_IN 4
COM F607 B1
Y_IN
F608 C1
3 2615 100n
NC F609 D1
E GND
E F612 F1
F613 F1
RES 3620
RES
F614 B1
2
+5V_SW
ITV-Connector D 4K7
5602 33R
+5V_SW
F615 B6
I610 C4
RES
RES 2616 100n I611 D4
I615 A8
5
1619 FRONT_CVBS_SVHS_SEL 7602
HD_PR_IN_ITV 74LVC1G3157G W I623 C2
1
HD_Y_IN_ITV VCC I627 D2
2
3
HD_PB_IN_ITV 7603 6
IN NO
1 FRONT_C_IN_T I631 C8
F612 PDTC114ET
4
VGA_H SVHS_C_IN 4
5 COM
VGA_V
6
7 8 3
F613 NC
F F
4602
GND
BM06B-SRSS-TBT
2
C_IN
1 2 3 4 5 6 7 8
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 62
PESD5V0S1BA PESD5V0S1BA
150R 3500 I510 1525 A2 F528 F2
330p
SC2_AUDIO_OUT_R
1502
2508
1526 A1 F529 F9
RES 6518
PESD5V0S1BA PESD5V0S1BA
150R
2502
330p
1500
2502 C10 F530 H5
RES 6522
2506 C10 F531 E2
SCART 1 2508 B4 F532 E9
3507 F535 SC1_AUDIO_OUT_L 2509 D12 F534 B4
1504
2512 D10 F535 C4
F511 150R 3502 I512
2514
330p
SC1_AUDIO_MUTE_L SC2_AUDIO_OUT_L 2514 C4 F536 C4
1505
C Audio-R_out 1
C
RES 6519
150R 2515 C5 F537 D4
2506
330p
1501
2 F513 SC2_AUDIO_MUTE_L 2517 D4 F538 E5
Audio-R_in
RES 6523
2518 D12 F539 E5
Audio-L_out 3 F515
F536
SCART 2 2520 E10 F540 F5
4 3510 2515 I540 SC1_AUDIO_IN_R 2521 D5 F541 F5
F517
1506 2523 D4 F542 G4
PESD5V0S1BA
PESD5V0S1BA
150R 220n 2525 G10 F544 D11
RES 6504
2512
3508
1503
6 F519 1n0 33K
33K
1n0
Audio-L_in 2 F512 2526 G10 I510 B11
Audio-R_in
RES 6501
7 F520 2527 F4 I512 C11
RGB-B_in 3 F514
Audio-L_out 2528 E4 I517 D12
F521
D Function_Sw 8
3514 F537 2521 SC1_AUDIO_IN_L 4F516 D 2529 F4
2530 H10
I520 D12
I528 G12
9
PESD5V0S1BA PESD5V0S1BA PESD5V0S1BA
PESD5V0S1BA
150R 220n
1508
11 F522 2535 H3 I541 D5
RGB-G_in
2520
3513
7
33K
1n0
1512 2536 G10 I543 G11
RES 6505
12 F532
3516 F538 SC1_B_IN 8 2538 H3 I544 G12
Function_Sw
13 RES 3500 B10 I545 E11
100R
1516
3517
75R
PESD5V0S1BA
F524 27K
1514
3551
16 3508 D11 I552 G11
6K8
RGB-BL_in F539 1513
RES 6524
SC1_STATUS 12 3510 C4 I553 I11
17 3518 3511 D4 I554 I12
F525
3520
1517
13
6K8
18
14 SC2_C_IN_ITV 3513 E11 I557 F12
19 F526 3514 D4 I558 I12
Terr_CVBS_out F523 3552 I557 SC2_C_IN
15 3515 D4
20 F528 RGB-R_out/YC-C_in
PESD5V0S1BA
Video_in 3523 F540 100R 3516 E4
1515
SC1_G_IN 16 RES
3517 E4
RES 6509
21 RES 2524 3553
PESD5V0S1BA PESD5V0S1BA PESD5V0S1BA PESD5V0S1BA PESD5V0S1BA
100R 3518 E4
1519
3526
2527
75R
17 75R
RES 6515
3519 G11
F PPTV/55
18 F 3520 E4
F527 3521 G12
CVBS_out 19
+5V_SW 3522 G10
3528 F541 SC1_R_IN 20 F529 3523 F4
Video/YC-Y_in 3524 I11
RES 100R
1520
3530
2529
75R
21 3525 G10
RES 6516
3522
3533
6512
75R
2531
68R I5303V 1K0 3533 G4
RES 6521
7502 3535 G3
PESD5V0S1BA
RES 7500 BC857BW
1518
2526 3525 BC847B 3536 H4
RES 6525
1K0 3537 I12
1N4148
6513
3536
2535
1K0
RES 6517
3546 H4
3555 I556 SC2_CVBS_MON_OUT_ITV
3550 E10
68R SC2_Y_CVBS_IN_ITV 3551 E10
3552 F11
H 3545 F530 SC1_CVBS_IN 3529 100R I533 SC2_Y_CVBS_IN H 3553 F11
RES 3554 I12
PESD5V0S1BA
100R RES
1524
RES 6510
1521
75R 3531 4502 G11
75R +5V_SW
4504 I12
6501 D10
6504 D3
3524
3540
15R
6505 E10
4K7 6507 D3
2534 I553 2533 6509 F10
I548 6510 H9
220n 220n 6511 H3
I549 RES I558 3537
4504 SC1_RF_OUT_CVBS
I 7503
BC847B 1K0
I 6512 G5
6513 G5
7504 6514 E3
BC857BW
6515 F3
6516 G3
3554 I554 6517 H3
SC1_CVBS_RF_OUT 6518 C3
68R H_17370_019.eps 6519 C3
3139 123 6273.1 010804 6520 E3
6521 G3
1 2 3 4 5 6 7 8 9 10 11 12 13 6522 C10
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 63
B07C HDMI_INT_MAIN
+1V8SWA IN07 5N01
120R
+1V8_SW
2N03 E2
2N04 E2
2N05 F1
3N18-3 E4
3N18-4 E4
3N19 F4
100n
100n
100n
1n0
1n0
2N06 F2 3N20 F4
HDMI_RST_RX_BUF
+3V3_ANA-MUX
2N07 G1 3N21 F4
2N15
2N18
2N16
2N17
2N20
2N08 G1 3N22 G5
2N09 F2 3N23 E3
2N10 F2 3N24 G4
A A
3N35
3N36
7N01-1
4K7
4K7
SII9125CTU
2N11 E3 3N25 G1
IN06 5N02 +3V3_SW 2N12 E3 3N26 G1
+3V3SWA
FN01 MAIN 2N13 F4 3N27 E2
HDMI-MUX_TSCL 4N03 102 55 120R
100n
100n
INT
1n0
2N14 G4 3N33 B7
1n0
1n0
1n0
1n0
1n0
1n0
1n0
76
FN02
HDMI-MUX_TSDA 4N04 100 77 2N15 A9 3N34 B5
RESET
+3V3_ANA-MUX 82 NC 2N16 A9 3N35 A3
2N25
2N28
2N31
2N61
2N26
2N29
2N32
2N62
2N27
2N30
RSVDNC
34 83
33
DSCL0
84
2N17 A10 3N36 A3
DSDA0 2N18 A9 3N37 B3
98 5N03
3N37
3N38
29 2N20 A10 3N38 B3
4K7
7N01-2
4K7
DSCL1 120R +3V3_SW
3N33 SII9125CTU +3V3SWB IN09
28 99 2N25 A9 3N39 B5
DSDA1 RSVDL
2N26 A10 3N40 B5
100n
FN03 4K7
1n0
HDMI-SIDE_TSCL 4N05 3N39 100R 27 16 37
AVCC18
3N40 100R 26
CSCL 0
15
NC
54
2N27 A10 4N01 D4
FN04 CSDA 1 NC 2N28 A9 4N02 D4
HDMI-SIDE_TSDA 4N06 14 3N01 33R HDMI_Cb(0) 72
2N66
2N33
3N34 2
105 13 HDMI_Cb(1) 36 2N29 A10 4N03 A4
B IIC_SCL_SIDE
IIC_SDA_SIDE
4K7
CI2CA 3
4
10
3N03
3N02-1 1
33R
8 33R HDMI_Cb(2) 41 38 B 2N30 A11 4N04 A4
101 9 3N02-2 2 7 33R HDMI_Cb(3) 45 42 5N04 +1V8_SW 2N31 A9 4N05 B4
NC SCDT 5 +1V8SWB IN10
8 3N02-3 3 6 33R HDMI_Cb(4) 49 46
6 2N32 A10 4N06 B4
AGND
AVCC33
Pend New 12NC +5VHDMI-MUX_TPWR 4N07 35 7 3N02-4 4 5 33R HDMI_Cb(5) 53 50 120R
100n
R0PWR5V 7 2N33 B10 4N07 B4
1n0
+5VHDMI-SIDE_TPWR 4N08 30 3 3N08-1 1 8 33R HDMI_Cb(6) 59 56
R1PWR5V 8
TO / FROM SIDE I/O 2 3N08-2 2 7 33R HDMI_Cb(7) 63 60 2N34 C9 4N08 B4
9
HDMI-MUX_TXC+ 40 1 3N08-3 3 6 33R HDMI_Cb(8) 67 64 2N35 C10 5N01 A11
2N34
2N36
+ 10
1N01 HDMI-MUX_TXC- 39 R0XC 144 3N08-4 4 5 33R HDMI_Cb(9) 71 68 2N36 C10 5N02 A11
FI-RE21S-HF-R1500 - 11
141
HDMI-MUX_TX0+ 44 Q
12
140 NC
93 96
2N37 C11 5N03 A11
1 NC + 13 DGND XTALVCC IN11 5N05 +1V8_SW
HDMI-SIDE_TXC- HDMI-MUX_TX0- 43 R0X0 139 NC
3N05 33R HDMI_Y(0) +1V8SWC 2N38 C9 5N04 B11
2 - 14
138 3N07 33R HDMI_Y(1) 11 92 120R 2N39 C9 5N05 C11
100n
100n
100n
3 15 HDMI_Y(2) DVCC18
1n0
1n0
4
HDMI-SIDE_TXC+ HDMI-MUX_TX1+ 48
+ 16
135 3N04-1 1 8 33R 23 2N40 C11 5N06 C11
HDMI-SIDE_TX0- HDMI-MUX_TX1- 47 R0X1 134 3N04-2 2 7 33R HDMI_Y(3) 79 12
C 5 - 17
133 3 6 33R HDMI_Y(4) 90 24 C 2N41 D10 5N07 D11
CGND
3N04-3
POWER
2N42 D9 5N08 D11
2N38
2N39
2N35
2N40
2N37
6 18 HDMI_Y(5)
HDMI-SIDE_TX0+ HDMI-MUX_TX2+ 52 132 3N04-4 4 5 33R 106 25
7 + 19 HDMI_Y(6) 2N43 D10 5N09 E11
HDMI-SIDE_TX1- HDMI-MUX_TX2- 51 R0X2 129 3N06-1 1 8 33R 118 80
CVCC18
8 - 20
128 3N06-2 2 7 33R HDMI_Y(7) 130 91 5N06 +1V8_SW 2N44 D10 7N01-1 A6
9 21 3N06-3 HDMI_Y(8) +1V8SWD IN12
HDMI-SIDE_TX1+ HDMI-SIDE_TXC+ 58 127 3 6 33R 142 107 2N45 D9 7N01-2 B8
10 + 22 HDMI_Y(9)
HDMI-SIDE_TX2- HDMI-SIDE_TXC- 57 R1XC 126 3N06-4 4 5 33R 119 120R 2N46 D10 7N01-3 F7
100n
100n
11 - 23
1n0
1n0
1n0
1n0
1n0
1n0
1n0
123 4 131
12
HDMI-SIDE_TX2+ HDMI-SIDE_TX0+ 62
24
122
NC
17 143
2N47 D11 7N07 F3
13 + 25 NC 2N48 D9 FN01 A4
HDMI-SIDE_CEC_A HDMI-SIDE_TX0- 61 R1X0 121 3N09 33R HDMI_Cr(0) 31
2N42
2N45
2N48
2N41
2N43
2N46
2N49
2N44
2N47
14 - 26
120 3N10 33R HDMI_Cr(1) 73 6 2N49 D10 FN02 A4
IOGND
15 NC 27
HDMI-SIDE_TSCL HDMI-SIDE_TX1+ 66 117 3N11-1 1 8 33R HDMI_Cr(2) 87 18 2N50 D10 FN03 B4
16 + 28
HDMI-SIDE_TSDA HDMI-SIDE_TX1- 65 R1X1 116 3N11-2 2 7 33R HDMI_Cr(3) 103 32 2N51 E9 FN04 B4
17 - 29
115 3N11-3 3 6 33R HDMI_Cr(4) 112 74
IOVCC33
18 +5VHDMI-SIDE_TPWR 30 IN13 5N07 +3V3_SW 2N52 E10 IN06 A11
HDMI-SIDE_TX2+ 70 114 3N11-4 4 5 33R HDMI_Cr(5) 124 88 +3V3SWC
D 19
HDMI-SIDE_TX2- 69
+
R1X2
31
111 3N12-1 1 8 33R HDMI_Cr(6) 136 104 120R
D 2N53 E10 IN07 A11
100n
20 - 32
HDMI_HOTPLUG_RESET 110 3N12-2 2 7 33R HDMI_Cr(7) 113 2N54 E9 IN09 B11
21 NC 33
23 22 95 109 3N12-3 3 6 33R HDMI_Cr(8) 145 125 2N55 E10 IN10 B11
IN 34 GND_HS
25 24 108 3N12-4 4 5 33R HDMI_Cr(9) 137 2N56 E11 IN11 C11
2N50
RES
XTAL 35
27 26 2N67 +3V3_SW 4N01 4N02 94
100n OUT
19 3N13 HDMI_DE 97
2N58 E10 IN12 C11
29 28 DE 33R REGVCC 5N08 +3V3_SW
IN14 2N59 E10 IN13 D11
3N18-1 1 8 33R 89 +3V3SWD
NC MCLK
+3V3_SW +3V3_SW 20 3N14 33R HDMI_H 120R 2N60 F9 IN14 D11
100n
100n
HSYNC
1n0
1n0
1n0
1n0
1n0
1n0
1n0
3N18-4 4 5 33R 86 2N61 A9 IN15 E11
SCK
21 3N15 33R HDMI_V 2N62 A10 IN16 F2
VSYNC
3N18-3 3 6 33R 85
2N51
2N54
2N63
2N59
2N52
2N55
2N58
2N53
2N56
WS 2N63 E9 IN17 F2
3N27
3N23
22
1R0
1R0
75 +3V3SWE
47u 6.3V
MUTEOUT 3N02-1 B7
2N03
2N04
2N11
2N12
100n
100n
120R
100n
1n0
3N02-2 B7
33R
33R
33R
3N02-3 B7
3N19
3N20
3N21
3N02-4 B7
2N60
2N64
166
167
168
169
170
7N01-3 3N03 B7
SII9125CTU
RES 3N04-1 C7
7N07 VIA 3N04-2 C7
13
47u 6.3V
3N04-3 C7
2N05
2N06
100n
VDDD
147 160
VDDA
Φ VIA
HDMI_SCK
HDMI_WS
DAC BCK
149 162
F IN16
12
VREF_DAC SYSCLK
6 150
VIA VIA
163 F 3N05 C7
3N06-1 C7
151 164
PLL1 3N06-2 C7
IN17 152 165
2N09 10u
14 3 3N06-3 C7
IN18 VOUTL DATAI VIA
2N13 3N06-4 C7
2N10 10u 16 10 153 3N07 C7
154
155
156
157
158
VOUTR PLL0
28M322
1N02
11
1M0
220R
220R
0 3N08-2 B7
9 SFOR 7 3N22
DEEM 1 2N14
3N08-3 B7
CLKOUT
2 3N08-4 C7
3N25
3N26
WS 18p 33R
3N09 D7
8
VSSD
3N10 D7
VSSA
HDMI_AUDIO_IN_R MUTE
IN20 3N11-1 D7
G G 3N11-2 D7
5
15
HDMI_AUDIO_IN_L IN21
3N11-3 D7
3N11-4 D7
10n
10n
3N12-1 D7
3N12-2 D7
2N07
2N08
3N12-3 D7
3N12-4 D7
3N13 D7
H_17370_020.eps 3N14 E7
3139 123 6273.1 010804 3N15 E7
3N16 E7
1 2 3 4 5 6 7 8 9 10 11
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 64
B07D B07D
RES 1M03 F1 IM15 E7
7M01
LF18CD 2M01 B10
RES 4M01 2M02 B10
FM16
1 3
+3V3_STBY IN OUT +1V8_STBY 2M03 B10
A COM A 2M04 B10
100u 16V
2M05 B10
2M12
2M11
100n
RES
RES
1M01 2M06 B10
2
10029449-002 A 2M07 D10
RX2+A +3V3_ANA-MUX
1 2M08 D10
2 FM05 2M09 D10
RX2-A
3 2M10 D10
RX1+A +1V8_ANA-MUX
4 5M02
3M33
4M02 2M11 A10
RES
4K7
5 +1V8_SW
RX1-A 2M12 A9
100n
100n
100n
100n
100n
100n
100n
6 220R FM17
10u
10u
RX0+A 4M03
7 2M15 C10
HDMI_INT_MUX
8 2M16 C10
RX0-A 3M20 100R IIC_SCL_up
2M01
2M02
2M03
2M04
2M05
2M06
2M19
2M20
2M21
9 2M17 C10
RXC+A 3M21 100R IIC_SDA_up
B 10
11
RXC-A
HDMI_RST_MUX B 2M19 B11
2M20 B11
12
3M35 47K +5V_SW
13 +5VHDMI_A 2M21 B11
3M36 47K
14 NC 3M03 C2
FM01 DDC_SCLA 5M03 +1V8_DIG-MUX
15 RES 4M04 3M04 C3
FM02 DDC_SDAA +1V8_STBY
16
3M18
RES
3M07 F2
4K7
100n
100n
17 220R FM18
10u
FM03 +5VHDMI_A RES 4M05 3M08 F3
18 IM07 +5VHDMI-MUX_TPWR
HPD_RESET_A IM12
19 3M09 D4
21 20
2M15
2M16
2M17
3M10 F4
23 22
3M11 G4
3M34
+3V3_ANA-MUX +1V8_ANA-MUX +1V8_DIG-MUX
4K7
3M13 H2
DDC_RESET
3M03
100R
7M07 3M14 E7
C IM01 3M04
SII9185CTU
C 3M15 E7
23
43
55
63
17
29
37
49
57
69
33
73
RES
6
5M01 +3V3_ANA-MUX
7M02 2K2
4M12 4M10 3M18 B7
HDMI 1 IM02 AVCC33 AVCC18 DVCC18 +3V3_SW
BC847BW 3M20 B5
100n
100n
220R FM19
10u
10u
13 RES RES 3M21 B5
RESET Φ 3M32 IM13 6M08 +3V3_ANA-MUX +3V3_STBY RES 4M11
HDMI-SIDE_CEC_A 3M31 H3
HDMI A 54
14 82K BAT54 COL 3M32 C7
2M07
2M08
2M09
2M10
LSDA CEC
1M02 B EPSEL0
SWITCH
D
53 CEC_D
10029449-002 DDC_SCLA 3M33 B5
EPSEL1 3M34 C7
RX2+B 15 DDC_SCLB
1 LSCL
2 FM06
DDC_SCLC 3M35 B2
RX2-B DDC_SDAA 3M36 B2
3
RX1+B 79 31 DDC_SDAB
4 I2CADDR 0 3M37 E2
51 DDC_SDAC
D 5
6
RX1-B
RX0+B
35
TPWR
I2CSEL
DSCL 1
2
71 RES 6M02
4M09
BAT54 COL +5V_SW
+5VHDMI_A
D 3M38 E2
3M39 G2
7 3M09 INT
75 30 RES 6M03 BAT54 COL 3M40 G2
8 RSVDL 0
RX0-B 50 +5V_SW 4M01 A3
9 4K7 DSDA 1
RXC+B RXC+A 19 70 RES 6M06 BAT54 COL
10 C+ 2 4M02 B9
RXC-A 18 4M08 +5VHDMI_B
11 C- 4M03 B9
RXC-B RX0+A 22 32 RES 6M07 BAT54 COL
12 0+ 0 4M04 B9
3M37 47K RX0-A 21 52 +5V_SW
13 +5VHDMI_B 0- RPWR 1
3M38 47K RX1+A 25 R0X 72 RES 6M01 BAT54 COL 4M05 C9
14 NC 1+ 2
FM07 DDC_SCLB RX1-A 24 4M07 +5VHDMI_C 4M07 E7
15 1- 6M04 BAT54 COL
FM08 DDC_SDAB RX2+A 28 16
16
27
2+ 0
RES HPD_RESET_A
4M08 D7
RX2-A 36
17 2- HPD 1 4M09 D7
FM10 +5VHDMI_B 56 HPD_RESET_B
18 IM08 2 4M10 C9
HPD_RESET_B RXC+B 39 76 HPD_RESET_C
E 19
21 20
23 22
RXC-B
RX0+B
38
42
C+
C-
HPDIN
78
IM14 3M14
100R
HDMI_HOTPLUG_RESET
HDMI-MUX_TSCL
E 4M11 C9
4M12 C7
0+ TSCL
RX0-B 41 77 HDMI-MUX_TSDA
45
0- TSDA 5M01 C9
RX1+B R1X IM15
1+ 3M15 5M02 B9
RX1-B 44 100R
1-
RX2+B 48 5M03 B9
2+
IM03 RX2-B 47
2-
6M01 E7
DDC_RESET 10 HDMI-MUX_TXC+
C+ 6M02 D7
3M07
100R
RXC+C 59 11 HDMI-MUX_TXC-
3M08 C+ C- 6M03 D7
RXC-C 58 7 HDMI-MUX_TX0+
2K2 C- 0+ 6M04 E7
7M04 RX0+C 62 8 HDMI-MUX_TX0-
HDMI 2 IM04 BC847BW RX0-C 61
0+
TX
0-
4 HDMI-MUX_TX1+ 6M06 D7
0- 1+
RX1+C 65
1+
R2X
1-
5 HDMI-MUX_TX1- 6M07 D7
RX1-C 64 1 HDMI-MUX_TX2+ 6M08 C7
F 1M03
10029449-002
C RX2+C
RX2-C
68
67
1-
2+
2+
2-
2 HDMI-MUX_TX2- F 7M01 A9
2- 7M02 C2
RX2+C
1 3M10 7M04 F2
FM15 +1V8_ANA-MUX 12
2 EXT_SWING
3
RX2-C
470R 7M07 C5
RX1+C AGND DGND
4 7M09 H2
3
9
20
26
40
46
60
66
80
34
74
5 RES FM01 B2
RX1-C
6 3M11 FM02 B2
RX0+C
7
FM03 C2
8 1K0
9
RX0-C FM05 A1
RXC+C FM06 D1
10
11 FM07 E2
RXC-C
G 12
13
3M39
3M40
47K
47K
+5VHDMI_C G FM08 E2
FM10 E2
14 NC
15
FM11 DDC_SCLC FM11 G2
FM12 DDC_SDAC FM12 G2
16
17
FM13
FM13 G2
18 +5VHDMI_C
IM09 HPD_RESET_C FM15 F1
19 FM16 A10
21 20
23 22 FM17 B11
FM18 B11
FM19 C11
IM01 C3
IM10
IM02 C2
H DDC_RESET
H IM03 E3
3M13
100R
3M31 IM04 F2
2K2 IM07 C2
HDMI 3 7M09 IM08 E2
IM11 BC847BW
H_17370_021.eps IM09 G2
3139 123 6273.1 010804 IM10 H3
IM11 H2
IM12 C7
1 2 3 4 5 6 7 8 9 10 11
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 65
*
LVDS LVD S LVD S LVDS
1R02 -- -- Y Y DISPEN CPU-GO 1R11 F2
FROM FPGA 1R03 -- -- Y Y CTRL-DISP2(LCD_PWR_on) On time : H On time : H 1R12 F2
1R04 -- -- Y Y
Off time : Don’t care Off time : Don’t care
1R13 G2
1R05 -- -- Y Y
PDWIN 2R01 F5
TxLVDSe_0n LVDSe_0n 1R06 -- -- Y Y
CTRL-DISP3(Rev_Standby) On time : H 2R02 F5
1R07 -- -- -- Y
DLW21S
Off time : Don’t care 2R10 D8
1R02
1R08 Y Y Y Y
1R09 Y Y Y Y PDP-GO 2R11 C10
TxLVDSe_0 p LVDSe_0p 1R10 Y Y Y Y On time : H 2R12 C10
1R11 Y Y Y Y
CTRL-DISP4 Semi standby : L MAIN_RESET
B TxLVDSe_1 n LVDSe_1n 1R12 Y Y Y Y Off time : Don’t care B 2R20 G9
2R21 G9
1R13 -- Y -- Y
DLW21S
1R03 2R23 G9
2R24 G9
TxLVDSe_1 p LVDSe_1p 3R10 C8
+5V_STANDB Y +12V_DISP
3R12 D8
TxLVDSe_2 n LVDSe_2n +VDISP
DLW21S 5R01 RES 3R13 D9
IR08
7R05 3R25 F4
1R04
1R01 220R
FX15S-41S-0.5SH SI4835BDY 3R26 F4
5R02 FR01
4R01
4R02
4R03
4R04
TxLVDSe_2 p LVDSe_2p 48 49 3R35 F9
+VDISP
46 47 220R
TxLVDSe_CLKn 44 45 12V1 3R48 F9
LVDSe_CLKn 5R03
RES
42 43 3R49 F9
C C
DLW21S
3R50 F9
1R05
41 IR01 220R
40
3R51 F9
TxLVDSe_CLKp LVDSe_CLKp FR02 3R52 F9
47u 16V
39
2R11
2R12
100n
38 3R10 3R53 F9
TxLVDSe_3 n LVDSe_3n CTRL_DISP1
CTRL_DISP2
37 3R54 F9
DLW21S
36 47K 4R01 C8
1R06
CTRL_DISP3
35 6R02
CTRL_DISP4 4R02 C8
34
TxLVDSe_3 p LVDSe_3 p 4R03 C8
33 BZX384-C5V6
TxLVDSe_4 n LVDSe_4 n FR03 4R04 C8
32
FR04
FR05
31 3R12 IR02 2R10 4R05 G9
DLW21S
30 4R06 G9
1R07
RES
FR06 IR06
29 47R 1u0
FR07 4R07 G9
D TxLVDSe_4 p LVDSe_4 p FR08
28 3R13
47K D 4R08 G9
TxLVDSo_0 n LVDSo_0 n FR09
27
26 VDISP-SWITCH 5R01 C9
FR10
25 IR04 5R02 C9
7R07
DLW21S
24 0V 5R03 C9
1R08
23 PDTC114ET
FR11
22
6R02 D8
TxLVDSo_0 p LVDSo_0p FR12 7R05 C9
21 3V2
TxLVDSo_1 n LVDSo_1n FR13
20
19
LCD 7R07 D8
FR01 C10
FR14
DLW21S
18 FR02 C5
1R09
FR15
17
FR16
16
FR03 D4
TxLVDSo_1 p LVDSo_1p FR17 FR04 D4
<,,,annot_deleted,> 15 +3V3_SW
FR18
E E
RES
FR05 D4
RES
RES
RES
14
TxLVDSo_2 n LVDSo_2n FR19
FR20
13 FR06 D4
DLW21S
12 FR07 D4
1R10
4K7
4K7
4K7
4K7
11
FR21
10
FR08 D4
TxLVDSo_2 p LVDSo_2p FR22 SINGLE FR09 D4
9
8
LVD S FR10 D4
TxLVDSo_CLKn LVDSo_CLKn FR31
FR11 D4
3R48
3R49
3R50
3R51
7
FR30
DLW21S
6 FR24
*
3R35 FR12 D4
1R11
*
3 3R52 FR25
BOLT_ON_SCL 3R25 100R LCD_PWR_ON CTRL_DISP2
2 FR15 E4
TxLVDSo_3 n LVDSo_3n BOLT_ON_SDA 3R26 100R
1 100R FR16 E4
F F
DLW21S
FR26
*
IR05 3R53 FR17 E4
1R12
STANDBYn CTRL_DISP3
FR18 E4
100p
100p
100R
TxLVDSo_3 p LVDSo_3p FR19 E4
FR27
*
CTRL_DISP4_up 3R54 CTRL_DISP4
FR20 E4
TxLVDSo_4 n LVDSo_4 n
100R FR21 E4
2R02
2R01
RES
RES
DLW21S
FR22 E4
*
1R13
RES
LCD PDP
3R35 -- 100R FR23 F5
100p
100p
100p
100p
TxLVDSo_4 p LVDSo_4 p 3R52 -- 100R FR24 F10
4R05
4R06
4R07
4R08
3R53 -- 100R FR25 F10
3R54 -- 100R
FR26 F10
2R20
2R21
2R23
2R24
4R05
*
*
*
*
Y --
4R06 Y -- FR27 F10
G 4R07
4R08
Y
Y
--
--
PDP G FR28 F4
FR29 F4
FR30 F4
FR31 E4
IR01 C8
H_17370_022.eps IR02 D8
3139 123 6273.1 010804 IR04 D9
IR05 F8
1 2 3 4 5 6 7 8 9 10
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 66
H_17370_034.eps
3104 313 6073.5 080807
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 67
Part 1
H_17370_023a.eps
070804
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 69
Part 2
H_17370_023b.eps
070804
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 70
Part 3
H_17370_023c.eps
070804