Philips 42pfl7762 LCD CH Lc7.5e La (001-070)

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Colour Television Chassis

LC7.5E
LA

SUPER NOVA

H_17370_000.eps
041007

Contents Page Contents Page


1. Technical Specifications, Connections, and Chassis SSB: Audio Processor (B06A) 58 67-76
Overview 2 SSB: Audio (B06B) 59 67-76
2. Safety Instructions, Warnings, and Notes 6 SSB: Headphone Ampl. & Muting (B06C) 60 67-76
3. Directions for Use 7 SSB: YPBPR & SVHS (B07A) 61 67-76
4. Mechanical Instructions 8 SSB: I/O SCART 1&2 (B07B) 62 67-76
5. Service Modes, Error Codes, and Fault Finding 15 SSB: HDMI Main (B07C) 63 67-76
6. Block Diagrams, Test Point Overviews, and SSB: HDMI Switch (B07D) 64 67-76
Waveforms SSB: LVDS Connector (B07E) 65 67-76
Wiring Diagram 32” LCD (ME7) 29 SSB: SRP List 66 67-76
Wiring Diagram 32” LCD with AmbiLight (ME7) 30 Side I/O Panel (32”): HDMI (D) 77 79
Wiring Diagram 42” LCD (ME7) 31 Side I/O Panel (32”) (D) 78 79
Wiring Diagram 42” LCD with AmbiLight (ME7) 32 Side I/O Panel (42” & 52”): HDMI (D) 80 82
Wiring Diagram 52” LCD (ME7) 33 Side I/O Panel (42” & 52”) (D) 81 82
Block Diagram Video 34 Side I/O Panel (42” & 52”) (D) 81 82
Block Diagram Audio 35 Keyboard Control Panel (E) 83 84
Block Diagram Control & Clock Signals 36 Front IR / LED Panel (J) 85 86
Testpoint Overview SSB (Bottom Side) 37-41 8. Alignments 87
I2C Overview 42 9. Circuit Descriptions, Abbreviation List, and IC Data
Supply Lines Overview 43 Sheets 92
7. Circuit Diagrams and PWB Layouts Diagram PWB Abbreviation List 97
SSB: DC / DC 3V3, VTUN, & 5V_SW (B01A) 44 67-76 IC Data Sheets 99
SSB: DC / DC 1V2, 2V5, & 1V8 (B01B) 45 67-76 10. Spare Parts List 107
SSB: Tuner IF & Demodulator (B02) 46 67-76 11. Revision List 133
SSB: DVB-Demodulator (B03A) 47 67-76
SSB: DVB-T: DVB Common Interface (B03B) 48 67-76
SSB: DVB MOJO (B03C) 49 67-76
SSB: DVB MOJO Memory (B03D) 50 67-76
SSB: DVB MOJO Analog Back End (B03E) 51 67-76
SSB: Micro Processor (B04) 52 67-76
SSB: Trident WX68 (B05A) 53 67-76
SSB: DDR & CPU Interface (B05B) 54 67-76
SSB: WX Power / Ground (B05C) 55 67-76
SSB: FPGA Interface (AL Sets only) (B05D) 56 67-76
SSB: FPGA I/O Banks (B05E) 57 67-76

©
Copyright 2007 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.

Published by WS 0770 BU CD Customer Service Printed in the Netherlands Subject to modification EN 3122 785 17372
EN 2 1. LC7.5E LA Technical Specifications, Connections, and Chassis Overview

1. Technical Specifications, Connections, and Chassis Overview


Index of this chapter: 1.1.3 Miscellaneous
1.1 Technical Specifications
1.2 Connection Overview Power supply:
1.3 Chassis Overview - Mains voltage (VAC) : 220 - 240
- Mains frequency (Hz) : 50 / 60
Notes:
• Figures can deviate due to the different set executions. Ambient conditions:
• Specifications are indicative (subject to change). - Temperature range (°C) : +5 to +40
- Maximum humidity : 90% R.H.
1.1 Technical Specifications
Power consumption (values are indicative)
- Normal operation (W) : ≈ 110 (32")
1.1.1 Vision
: ≈ 170 (42")
- Stand-by (W) : <1
Display type : LCD
Screen size : 32" (82 cm), 16:9
Dimensions (WxHxD cm) : 80.4x53.3x17.8 (32")
: 42" (107 cm), 16:9
: 102.9x66.2x13.6 (42")
Resolution (HxV pixels) : 1366x768 (32")
: 1920x1080 (42")
Dyn. contrast ratio : 7500:1 Weight (kg) : 15 (32")
Min. light output (cd/m2) : 500 : 25.5 (42")
Typ. response time (ms) : 8 (32")
: 5 (42")
Viewing angle (HxV degrees) : 176x176 (32")
: 178x178 (42")
Tuning system : PLL
Presets/channels : 100 presets
Tuner bands : VHF, UHF, S, H
TV Colour systems : PAL B/G, D/K, I
: SECAM B/G, D/K, L/L’
: DVB-T COFDM
Video playback : NTSC
: PAL
: SECAM
Supported computer formats : 640x480
: 800x600
: 1024x768
: 1280x768
: 1280x1024
: 1360x768
Supported video formats : 640x480i - 1fH
: 640x480p - 2fH
: 720x576i - 1fH
: 720x576p - 2fH
: 1280x720p - 3fH
: 1920x1080i - 2fH
: 1920x1080p - 3fH

1.1.2 Sound

Sound systems : stereo, BBE®


Maximum power (WRMS) : 2 × 20
Technical Specifications, Connections, and Chassis Overview LC7.5E LA 1. EN 3

1.2 Connection Overview

Y Pb Pr
COMMON INTERFACE TV ANTENNA HDMI 2 HDMI 1
L R EXT. 4

S-VIDEO AUDIO IN

H_17370_051.eps
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Figure 1-1 Side and rear I/O connections

Note: The following connector colour abbreviations are used 1.2.2 Rear Connections
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy=
Grey, Rd= Red, Wh= White, and Ye= Yellow. Service Connector (ComPair)
1 - SDA-S I2C Data (0 - 5 V) jk
1.2.1 Side Connections 2 - SCL-S I2C Clock (0 - 5 V) j
3 - Ground Gnd H
EXT3: Cinch: Video CVBS - In, Audio - In
Ye - Video CVBS 1 VPP / 75 ohm jq Service Connector (UART)
Wh - Audio L 0.5 VRMS / 10 kohm jq 1 - UART_TX Transmit k
Rd - Audio R 0.5 VRMS / 10 kohm jq 2 - Ground Gnd H
3 - UART_RX Receive j
EXT3: Head phone - Out
Bk - Head phone 32 - 600 ohm / 10 mW rt EXT1: Video RGB - In, CVBS - In/Out, Audio - In/Out

20 2
EXT3: HDMI: Digital Video, Digital Audio - In

19 1
18 2
E_06532_017.eps
250505 21 1
E_06532_001.eps
050404
Figure 1-2 HDMI (type A) connector
Figure 1-3 SCART connector
1 - D2+ Data channel j
2 - Shield Gnd H 1 - Audio R 0.5 VRMS / 1 kohm k
3 - D2- Data channel j 2 - Audio R 0.5 VRMS / 10 kohm j
4 - D1+ Data channel j 3 - Audio L 0.5 VRMS / 1 kohm k
5 - Shield Gnd H 4 - Ground Audio Gnd H
6 - D1- Data channel j 5 - Ground Blue Gnd H
7 - D0+ Data channel j 6 - Audio L 0.5 VRMS / 10 kohm j
8 - Shield Gnd H 7 - Video Blue 0.7 VPP / 75 ohm j
9 - D0- Data channel j 8 - Function Select 0 - 2 V: INT
10 - CLK+ Data channel j 4.5 - 7 V: EXT 16:9
11 - Shield Gnd H 9.5 - 12 V: EXT 4:3 j
12 - CLK- Data channel j 9 - Ground Green Gnd H
13 - n.c. 10 - Easylink P50 0 - 5 V / 4.7 kohm jk
14 - n.c. 11 - Video Green 0.7 VPP / 75 ohm j
15 - DDC_SCL DDC clock j 12 - n.c.
16 - DDC_SDA DDC data jk 13 - Ground Red Gnd H
17 - Ground Gnd H 14 - Ground P50 Gnd H
18 - +5V j 15 - Video Red 0.7 VPP / 75 ohm j
19 - HPD Hot Plug Detect j 16 - Status/FBL 0 - 0.4 V: INT
20 - Ground Gnd H 1 - 3 V: EXT / 75 ohm j
17 - Ground Video Gnd H
18 - Ground FBL Gnd H
19 - Video CVBS 1 VPP / 75 ohm k
20 - Video CVBS 1 VPP / 75 ohm j
21 - Shield Gnd H
EN 4 1. LC7.5E LA Technical Specifications, Connections, and Chassis Overview

EXT2: Video YC - In, CVBS - In/Out, Audio - In/Out

1 - Audio R 0.5 VRMS / 1 kohm k


2 - Audio R 0.5 VRMS / 10 kohm j
3 - Audio L 0.5 VRMS / 1 kohm k
4 - Ground Audio Gnd H
5 - n.c.
6 - Audio L 0.5 VRMS / 10 kohm j
7 - C-out 0.7 VPP / 75 ohm k
8 - Function Select 0 - 2 V: INT
4.5 - 7 V: EXT 16:9
9.5 - 12 V: EXT 4:3 j
9 - n.c.
10 - Easylink P50 0 - 5 V / 4.7 kohm jk
11 - n.c.
12 - n.c.
13 - n.c.
14 - Ground P50 Gnd H
15 -C 0.7 VPP / 75 ohm j
16 - Status/FBL 0 - 0.4 V: INT
1 - 3 V: EXT / 75 ohm j
17 - Ground Video Gnd H
18 - Ground FBL Gnd H
19 - Video CVBS 1 VPP / 75 ohm k
20 - Video CVBS/Y 1 VPP / 75 ohm j
21 - Shield Gnd H

Common Interface
68p - See diagram B03B jk

Aerial - In
- - IEC-type (EU) Coax, 75 ohm D

HDMI1 & 2: Digital Video, Digital Audio - In


1 - D2+ Data channel j
2 - Shield Gnd H
3 - D2- Data channel j
4 - D1+ Data channel j
5 - Shield Gnd H
6 - D1- Data channel j
7 - D0+ Data channel j
8 - Shield Gnd H
9 - D0- Data channel j
10 - CLK+ Data channel j
11 - Shield Gnd H
12 - CLK- Data channel j
13 - n.c.
14 - n.c.
15 - DDC_SCL DDC clock j
16 - DDC_SDA DDC data jk
17 - Ground Gnd H
18 - +5V j
19 - HPD Hot Plug Detect j
20 - Ground Gnd H

EXT4: Cinch: Video YPbPr - In, Audio - In


Gn - Video Y 1 VPP / 75 ohm jq
Bu - Video Pb 0.7 VPP / 75 ohm jq
Rd - Video Pr 0.7 VPP / 75 ohm jq
Wh - Audio L 0.5 VRMS / 10 kohm jq
Rd - Audio R 0.5 VRMS / 10 kohm jq

EXT4: S-Video (Hosiden): Video Y/C - In


1 - Ground Y Gnd H
2 - Ground C Gnd H
3 - Video Y 1 VPP / 75 ohm j
4 - Video C 0.3 VPPP / 75 ohm j
Technical Specifications, Connections, and Chassis Overview LC7.5E LA 1. EN 5

1.3 Chassis Overview

SIDE I/O PANEL D

MAIN SUPPLY UNIT

CONTROL BOARD E
SMALL SIGNAL
B BOARD
LED PANEL J
H_17370_052.eps
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Figure 1-4 PWB/CBA locations (32" sets)

SIDE I/O PANEL D

MAIN SUPPLY UNIT

CONTROL BOARD E
SMALL SIGNAL
B BOARD
LED PANEL J
H_17370_054.eps
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Figure 1-5 PWB/CBA locations (42" models)


EN 6 2. LC7.5E LA Safety Instructions, Warnings, and Notes

2. Safety Instructions, Warnings, and Notes


Index of this chapter: Service Default Mode (see chapter 5) with a colour bar
2.1 Safety Instructions signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated
2.2 Warnings otherwise) and picture carrier at 475.25 MHz for PAL, or
2.3 Notes 61.25 MHz for NTSC (channel 3).
• Where necessary, measure the waveforms and voltages
with (D) and without (E) aerial signal. Measure the
2.1 Safety Instructions voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
Safety regulations require the following during a repair: indicated by means of the appropriate symbols.
• Connect the set to the Mains/AC Power via an isolation • Manufactured under license from Dolby Laboratories.
transformer (> 800 VA). “Dolby”, “Pro Logic” and the “double-D symbol”, are
• Replace safety components, indicated by the symbol h, trademarks of Dolby Laboratories.
only by components identical to the original ones. Any
other component substitution (other than original type) may 2.3.2 Schematic Notes
increase risk of fire or electrical shock hazard.
• All resistor values are in ohms, and the value multiplier is
Safety regulations require that after a repair, the set must be
often used to indicate the decimal point location (e.g. 2K2
returned in its original condition. Pay in particular attention to
indicates 2.2 kohm).
the following points:
• Resistor values with no multiplier may be indicated with
• Route the wire trees correctly and fix them with the
either an "E" or an "R" (e.g. 220E or 220R indicates 220
mounted cable clamps.
ohm).
• Check the insulation of the Mains/AC Power lead for
• All capacitor values are given in micro-farads (μ= x10-6),
external damage.
nano-farads (n= x10-9), or pico-farads (p= x10-12).
• Check the strain relief of the Mains/AC Power cord for
• Capacitor values may also use the value multiplier as the
proper function.
decimal point indication (e.g. 2p2 indicates 2.2 pF).
• Check the electrical DC resistance between the Mains/AC
• An "asterisk" (*) indicates component usage varies. Refer
Power plug and the secondary side (only for sets that have
to the diversity tables for the correct values.
a Mains/AC Power isolated power supply):
• The correct component values are listed in the Spare Parts
1. Unplug the Mains/AC Power cord and connect a wire
List. Therefore, always check this list when there is any
between the two pins of the Mains/AC Power plug.
doubt.
2. Set the Mains/AC Power switch to the "on" position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the 2.3.3 BGA (Ball Grid Array) ICs
Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading Introduction
should be between 4.5 Mohm and 12 Mohm. For more information on how to handle BGA devices, visit this
4. Switch "off" the set, and remove the wire between the URL: www.atyourservice.ce.philips.com (needs subscription,
two pins of the Mains/AC Power plug. not available for all regions). After login, select “Magazine”,
• Check the cabinet for defects, to prevent touching of any then go to “Repair downloads”. Here you will find Information
inner parts by the customer. on how to deal with BGA-ICs.

BGA Temperature Profiles


2.2 Warnings For BGA-ICs, you must use the correct temperature-profile,
which is coupled to the 12NC. For an overview of these profiles,
• All ICs and many other semiconductors are susceptible to visit the website www.atyourservice.ce.philips.com (needs
electrostatic discharges (ESD w). Careless handling subscription, but is not available for all regions)
during repair can reduce life drastically. Make sure that, You will find this and more technical information within the
during repair, you are connected with the same potential as "Magazine", chapter "Repair downloads".
the mass of the set by a wristband with resistance. Keep For additional questions please contact your local repair help
components and tools also at this same potential. Available desk.
ESD protection equipment:
– Complete kit ESD3 (small tablemat, wristband,
2.3.4 Lead-free Soldering
connection box, extension cable and earth cable)
4822 310 10671.
Due to lead-free technology some rules have to be respected
– Wristband tester 4822 344 13999.
by the workshop during a repair:
• Be careful during measurements in the high voltage
section. • Use only lead-free soldering tin Philips SAC305 with order
code 0622 149 00106. If lead-free solder paste is required,
• Never replace modules or other components while the unit
please contact the manufacturer of your soldering
is switched "on".
• When you align the set, use plastic rather than metal tools. equipment. In general, use of solder paste within
workshops should be avoided because paste is not easy to
This will prevent any short circuits and the danger of a
store and to handle.
circuit becoming unstable.
• Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able:
2.3 Notes – To reach a solder-tip temperature of at least 400°C.
– To stabilize the adjusted temperature at the solder-tip.
2.3.1 General – To exchange solder-tips for different applications.
• Adjust your solder tool so that a temperature of around
360°C - 380°C is reached and stabilized at the solder joint.
• Measure the voltages and waveforms with regard to the
Heating time of the solder-joint should not exceed ~ 4 sec.
chassis (= tuner) ground (H), or hot ground (I), depending
Avoid temperatures above 400°C, otherwise wear-out of
on the tested area of circuitry. The voltages and waveforms
tips will increase drastically and flux-fluid will be destroyed.
shown in the diagrams are indicative. Measure them in the
Directions for Use LC7.5E LA 3. EN 7

To avoid wear-out of tips, switch “off” unused equipment or


reduce heat. MADE IN BELGIUM
MODEL : 32PF9968/10
• Mix of lead-free soldering tin/parts with leaded soldering 220-240V ~ 50/60Hz
tin/parts is possible but PHILIPS recommends strongly to 128W
avoid mixed regimes. If this cannot be avoided, carefully PROD.NO: AG 1A0617 000001 VHF+S+H+UHF
clear the solder-joint from old tin and re-solder with new tin. S BJ3.0E LA

E_06532_024.eps
2.3.5 Alternative BOM identification 130606

The third digit in the serial number (example: Figure 2-1 Serial number (example)
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the 2.3.6 Board Level Repair (BLR) or Component Level Repair
specific TV set. In general, it is possible that the same TV (CLR)
model on the market is produced with e.g. two different types
of displays, coming from two different suppliers. This will then
If a board is defective, consult your repair procedure to decide
result in sets which have the same CTN (Commercial Type
if the board has to be exchanged or if it should be repaired on
Number; e.g. 28PW9515/12) but which have a different B.O.M.
component level.
number.
If your repair procedure says the board should be exchanged
By looking at the third digit of the serial number, one can
completely, do not solder on the defective board. Otherwise, it
identify which B.O.M. is used for the TV set he is working with.
cannot be returned to the O.E.M. supplier for back charging!
If the third digit of the serial number contains the number “1”
(example: AG1B033500001), then the TV set has been
manufactured according to B.O.M. number 1. If the third digit is 2.3.7 NVM content
a “2” (example: AG2B0335000001), then the set has been
produced according to B.O.M. no. 2. This is important for If the processor NVM IC is replaced or initialised, the Model
ordering the correct spare parts! Number, Serial Number, and SSB Code number must be re-
For the third digit, the numbers 1...9 and the characters A...Z written to the NVM. ComPair will foresee in a possibility to do
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be this.
indicated by the third digit of the serial number.
2.3.8 Practical Service Precautions
Identification: The bottom line of a type plate gives a 14-digit
serial number. Digits 1 and 2 refer to the production centre (e.g. • It makes sense to avoid exposure to electrical shock.
AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers While some sources are expected to have a possible
to the Service version change code, digits 5 and 6 refer to the dangerous impact, others of quite high potential are of
production year, and digits 7 and 8 refer to production week (in limited current and are sometimes held in less regard.
example below it is 2006 week 17). The 6 last digits contain the • Always respect voltages. While some may not be
serial number. dangerous in themselves, they can cause unexpected
reactions that are best avoided. Before reaching into a
powered TV set, it is best to test the high voltage insulation.
It is easy to do, and is a good service precaution.

3. Directions for Use


You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com
EN 8 4. LC7.5E LA Mechanical Instructions

4. Mechanical Instructions
Index of this chapter: Notes:
4.1 Cable Dressing • Figures below can deviate slightly from the actual situation,
4.2 Service Positions due to the different set executions.
4.3 Assy/Panel Removal • Follow the disassemble instructions in described order.
4.4 Set Re-assembly

4.1 Cable Dressing

H_17370_070.eps
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Figure 4-1 Cable dressing (32" sets)


Mechanical Instructions LC7.5E LA 4. EN 9

H_17370_072.eps
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Figure 4-2 Cable dressing (42" sets)


EN 10 4. LC7.5E LA Mechanical Instructions

4.2 Service Positions 4.3 Assy/Panel Removal

For easy servicing of this set, there are a few possibilities 4.3.1 Rear Cover
created:
• The buffers from the packaging. Warning: Disconnect the mains power cord before you remove
• Foam bars (created for Service). the rear cover.
• Aluminium service stands (created for Service).
1. Refer to next figures.
Note: the aluminium service stands can only be used when the 2. Place the TV set upside down on a table top, using the
set is equipped with so-called “mushrooms”. Otherwise use the foam bars (see part “Service Positions”).
original stand that comes with the set. 3. Remove rear cover screws [1] and the stand (if mounted).
4. Remove Subwoofer mounting screws [2] (if present).
4.2.1 Foam Bars 5. Lift Subwoofer module, and unplug Subwoofer cable [3].
6. Unplug AmbiLight cables [4] (if present).
7. Remove rear cover.
1

Required for sets


1 42"

2
1

E_06532_018.eps
171106

Figure 4-3 Foam bars H_17370_036.eps


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The foam bars (order code 3122 785 90580 for two pieces) can Figure 4-5 Rear cover removal (1/3)
be used for all types and sizes of Flat TVs. See figure “Foam
bars” for details.
Sets with a display of 42" and larger, require four foam bars [1].
Ensure that the foam bars are always supporting the cabinet
and never only the display.
Caution: Failure to follow these guidelines can seriously
damage the display!
By laying the TV face down on the (ESD protective) foam bars,
a stable situation is created to perform measurements and
alignments. By placing a mirror under the TV, you can monitor
the screen.

4.2.2 Aluminium Stands


3

H_17370_037.eps
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Figure 4-6 Rear cover removal (2/3)

E_06532_039.eps
290507

Figure 4-4 Aluminium stands

The MkII aluminium stands with order code 3122 785 90690,
can also be used to do measurements, alignments, and 4
duration tests. The stands can be (dis)mounted quick and easy
by means of sliding them in/out the "mushrooms". The stands
are backwards compatible with the earlier models.
Important: For (older) FTV sets without these "mushrooms", it H_17370_038.eps
is obligatory to use the provided screws, otherwise it is possible 090807

to damage the monitor inside!


Figure 4-7 Rear cover removal (3/3)
Mechanical Instructions LC7.5E LA 4. EN 11

4.3.2 AmbiLight Lamps (if present) 4.3.4 Side I/O Panel

1. Refer to next figure. 1. Refer to next figures.


2. Unplug connectors [1]. 2. Unplug connectors [1]. To release the flatcable connector
3. Remove the T10 parker screws [2]. [1b], push the two side levers and unplug the connector.
4. Remove the unit by shifting it sidewards [3]. 3. Remove screws [2] and remove the complete module [3].
When defective, replace the whole unit. When defective, replace the whole unit.

2
2 2

3
1a
2
3
1b
1 2 2
3

2 2
2
H_17370_049.eps
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H_17370_039.eps
080807 Figure 4-10 Side I/O module (1/2)

Figure 4-8 AmbiLight lamps

4.3.3 Keyboard Control Panel

1. Refer to next figure.


2. Unplug connector [2].
3. Remove the T10 parker screws [1].
4. Remove the unit. 1b
5. Release clips [3] and remove the board.
When defective, replace the whole unit.

H_17370_045.eps
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Figure 4-11 Side I/O module (2/2)

3 4.3.5 IR/LED Panel

1. Refer to next figure.


2. Unplug connectors [1].
3. Release clip [2] and remove the board.
When defective, replace the whole unit.

1
G_16850_007.eps
310707
2
Figure 4-9 Keyboard control panel

G_16850_009.eps
110107

Figure 4-12 IR/LED panel


EN 12 4. LC7.5E LA Mechanical Instructions

4.3.6 Speakers

Unplug the speaker cables and remove the speaker.

4.3.7 Main Supply Panel

1. Unplug cables.
2. Remove the fixation screws.
3. Take the board out (it hinges at the left side).
When defective, replace the whole unit.

4.3.8 Small Signal Board (SSB)

Note: Follow sequence below closely, otherwise you will have


difficulties with removing the top shielding.

1. Refer to next figures.


2. Disconnect all cables [1] on the SSB.
3. Remove the T10 tapping screws [2] that hold the SSB.
4. Remove the screws [3] that hold the connectors and the
connector plate.
5. Lift the complete SSB from the set (including the shielding
and connector plate).
6. Now, remove the connector plate first, by pulling it away
from the connectors.
7. Then, lift the top shielding from the SSB.

2 2 2

2 2 2

3 3 3 3

H_17370_044.eps
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Figure 4-13 SSB removal (1/2)

3 3 3 3
3 3

H_17370_043.eps
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Figure 4-14 SSB removal (2/2)


Mechanical Instructions LC7.5E LA 4. EN 13

4.3.9 LCD Panel 5. Remove the T20 panel fixation screws [3]. Note that the
number of these screws can vary, depending on the
1. Refer to next figures. screensize.
2. Unplug the connectors [1] on the Main Supply Panel, the 6. Lift he complete central sub-frame from the set [4] (incl. the
display (LVDS connector), Loudspeakers, and the LED/IR PSU, SSB, and Side I/O boards and wiring).
board. 7. After removing the sub-frame, the LCD panel can be lifted
3. Do NOT forget to unplug the LVDS connector from the from the front cabinet.
SSB. Important: Be careful, as this is a fragile connector!
4. Remove T10 parker screws [2] on the top and bottom of the
central sub-frame.

3
3

3 2 3

1 1

H_17370_042.eps
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Figure 4-15 LCD panel (1/3)

4
1

3
1

H_17370_046.eps
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Figure 4-16 LCD panel (2/3)

H_17370_047.eps
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Figure 4-17 LCD panel (3/3)


EN 14 4. LC7.5E LA Mechanical Instructions

4.4 Set Re-assembly

To re-assemble the whole set, execute all processes in reverse


order.

Notes:
• While re-assembling, make sure that all cables are placed
and connected in their original position. See figure "Cable
dressing".
• Pay special attention not to damage the EMC foams.
Ensure that EMC foams are mounted correctly (one is
located above the LVDS connector on the display, between
the LCD display and the metal sub-frame).
Service Modes, Error Codes, and Fault Finding LC7.5E LA 5. EN 15

5. Service Modes, Error Codes, and Fault Finding


Index of this chapter: 5.2.1 General
5.1 Test Points
5.2 Service Modes Some items are applicable to all Service Modes or are general.
5.3 Service Tools These are listed below.
5.4 Error Codes
5.5 The Blinking LED Procedure
Life Timer
5.6 Software Upgrading
During the life time cycle of the TV set, a timer is kept. It counts
5.7 Fault Finding and Repair Tips
the normal operation hours (not the Stand-by hours). The
actual value of the timer is displayed in SDM and CSM in a
5.1 Test Points decimal value. Every two soft-resets increase the hour by +1.

In the chassis schematics and layout overviews, the test points Software Identification, Version, and Cluster
(Fxxx) are mentioned. In the schematics, test points are The software ID, version, and cluster will be shown in the main
indicated with a rectangular box around “Fxxx” or “Ixxx”, in the menu display of SDM, SAM, and CSM.
layout overviews with a “half-moon” sign. The screen will show: “AAAABCD X.YY”, where:
As most signals are digital, it will be difficult to measure • AAAA is the chassis name: LC71 for analogue range (non-
waveforms with a standard oscilloscope. Several key ICs are DVB), LC72 for digital range (DVB).
capable of generating test patterns, which can be controlled via • B is the region indication: E= Europe, A= AP/China, U=
ComPair. In this way it is possible to determine which part is NAFTA, L= LATAM.
defective. • C is the display indication: L= LCD, P= Plasma.
• D is the language/feature indication: 1= standard, H=
Perform measurements under the following conditions: 1080p full HD.
• Service Default Mode. • X is the main version number: this is updated with a major
• Video: Colour bar signal. change of specification (incompatible with the previous
• Audio: 3 kHz left, 1 kHz right. software version). Numbering will go from 1 - 9 and A - Z.
– If the main version number changes, the new version
number is written in the NVM.
5.2 Service Modes – If the main version number changes, the default
settings are loaded.
The Service Mode feature is split into four parts: • YY is the sub version number: this is updated with a minor
• Service Default Mode (SDM). change (backwards compatible with the previous versions)
• Service Alignment Mode (SAM). Numbering will go from 00 - 99.
• Customer Service Mode (CSM) and Digital Customer – If the sub version number changes, the new version
Service Mode (DCSM). number is written in the NVM.
• Computer Aided Repair Mode (ComPair). – If the NVM is fresh, the software identification, version,
and cluster will be written to NVM.
SDM and SAM offer features, which can be used by the Service
engineer to repair/align a TV set. Some features are: Display Option Code Selection
• A pre-defined situation to ensure measurements can be When after an SSB or display exchange, the display option
made under uniform conditions (SDM). code is not set properly, it will result in a TV with “no display”.
• Activates the blinking LED procedure for error identification Therefore, it is required to set this display option code after
when no picture is available (SDM). such a repair.
• The possibility to overrule software protections when SDM To do so, press the following key sequence on a standard RC
was entered via the Service pins. transmitter: “062598” directly followed by MENU and “xxx”,
• Make alignments (e.g. white tone), (de)select options, where “xxx” is a 3 digit decimal value of the panel type: see
enter options codes, reset the error buffer (SAM). column “Panel Code” in table “Option Codes OP1...OP7” (ch.
• Display information (“SDM” or “SAM” indication in upper 8), or see sticker on the side/bottom of the cabinet. When the
right corner of screen, error buffer, software version, value is accepted and stored in NVM, the set will switch to
operating hours, options and option codes, sub menus). Stand-by, to indicate that the process has been completed.

The (D)CSM is a Service Mode that can be enabled by the


consumer. The CSM displays diagnosis information, which the
customer can forward to the dealer or call centre. In CSM Display Option
mode, “CSM”, is displayed in the top right corner of the screen. Code

The information provided in CSM and the purpose of CSM is to:


• Increase the home repair hit rate. 39mm

PHILIPS
• Decrease the number of nuisance calls. 040
27mm

MODEL:
32PF9968/10
• Solved customers' problem without home visit. PROD.SERIAL NO:
AG 1A0620 000001

(CTN Sticker)

ComPair Mode is used for communication between a computer E_06532_038.eps


and a TV on I2C /UART level and can be used by a Service 290107

engineer to quickly diagnose the TV set by reading out error


codes, read and write in NVMs, communicate with ICs and the Figure 5-1 Location of Display Option Code sticker
uP (PWM, registers, etc.), and by making use of a fault finding
database. It will also be possible to up and download the During this algorithm, the NVM-content must be filtered,
software of the TV set via I2C with help of ComPair. To do this, because several items in the NVM are TV-related and not SSB-
ComPair has to be connected to the TV set via the ComPair related (e.g. Model and Prod. S/N). Therefore, “Model” and
connector, which will be accessible through the rear of the set “Prod. S/N” data is changed into “See Type Plate”.
(without removing the rear cover). In case a call centre or consumer reads “See Type Plate” in
CSM mode, he needs to look to the side/bottom sticker to
identify the set, for further actions.
EN 16 5. LC7.5E LA Service Modes, Error Codes, and Fault Finding

5.2.2 Service Default Mode (SDM) On Screen Menu


After activating SDM, the following screen is visible, with SDM
Purpose in the upper right corner of the screen to indicate that the
Set the TV in SDM mode in order to be able to: television is in Service Default Mode.
• Create a pre-defined setting for measurements to be
made. S D M
HHHHH A A A A B C D - X . Y Y
• Override software protections. E R R X X X X X X X X X X
• Start the blinking LED procedure. O P X X X X X X X X X X X X X X X X X X
• Read the error buffer.
• Check the life timer.

Specifications

Table 5-1 SDM default settings

G_16860_030.eps
Region Freq. (MHz) Default syst. 260107

Europe (except France), 475.25 PAL B/G


Figure 5-3 SDM menu
AP-PAL/-Multi
France SECAM L
Menu explanation:
NAFTA, AP-NTSC 61.25 (channel 3) NTSC M • HHHHH: Are the operating hours (in decimal).
LATAM PAL M • AAAABCD-X.YY: See paragraph “Service Modes” ->
“General” -> “Software Identification, Version, and Cluster”
• Set linear video and audio settings to 50%, but volume to for the SW name definition.
25%. Stored user settings are not affected. • SDM: The character “SDM” to indicate that the TV set is in
• All service-unfriendly modes (if present) are disabled, since Service mode.
they interfere with diagnosing/repairing a set. These • ERR: Shows all errors detected since the last time the
service unfriendly modes are: buffer was erased. Five errors possible.
– (Sleep) timer. • OP: Used to read-out the option bytes. See “Options” in the
– Blue mute/Wall paper. Alignments section for a detailed description. Seven codes
– Auto switch “off” (when there is no “ident” signal). are possible.
– Hotel or hospital mode.
– Child lock or parental lock (manual or via V-chip). How to Navigate
– Skipping, blanking of “Not favourite”, “Skipped” or As this mode is read only, there is not much to navigate. To
“Locked” presets/channels. switch to other modes, use one of the following methods:
– Automatic storing of Personal Preset or Last Status • Command MENU from the user remote will enter the
settings. normal user menu (brightness, contrast, colour, etc...) with
– Automatic user menu time-out (menu switches back/ “SDM” OSD remaining, and pressing MENU key again will
OFF automatically. return to the last status of SDM again.
– Auto Volume levelling (AVL). • To prevent the OSD from interfering with measurements in
SDM, command “OSD” (“STATUS” for NAFTA and
How to Activate LATAM) from the user remote will toggle the OSD “on/off”
To activate SDM, use one of the following methods: with “SDM” OSD remaining always “on”.
• Press the following key sequence on the remote control • Press the following key sequence on the remote control
transmitter: “062596” directly followed by the MENU button transmitter: “062596” directly followed by the OSD/i+
(do not allow the display to time out between entries while button to switch to SAM (do not allow the display to time out
keying the sequence). between entries while keying the sequence).
• Short one of the “Service” jumpers on the TV board during
cold start (see Figures “Service jumper”). Then press the How to Exit
mains button (remove the short after start-up). Switch the set to STANDBY by pressing the mains button on
Caution: Activating SDM by shorting “Service” jumpers will the remote control transmitter or on the television set.
override the DC speaker protection (error 1), the General If you switch the television set “off” by removing the mains (i.e.,
I2C error (error 4), and the Trident video processor error unplugging the television), the television set will remain in SDM
(error 5). When doing this, the service-technician must when mains is re-applied, and the error buffer is not cleared.
know exactly what he is doing, as it could damage the The error buffer will only be cleared when the “clear” command
television set. is used in the SAM menu.

Note:
• If the TV is switched “off” by a power interrupt while in SDM,
the TV will show up in the last status of SDM menu as soon
SDM as the power is supplied again. The error buffer will not be
cleared.
• In case the set is in Factory mode by accident (with “F”
displayed on screen), by pressing and hold “VOL-“ and
“CH-” together should leave Factory mode.

H_17370_048.eps
080807

Figure 5-2 Service jumper (SSB component side)


Service Modes, Error Codes, and Fault Finding LC7.5E LA 5. EN 17

5.2.3 Service Alignment Mode (SAM) uploading via ComPair. Read paragraph “Service Tools” -
> “ComPair”. Caution: When this mode is selected without
Purpose ComPair connected, the TV will be blocked. Remove the
• To change option settings. AC power to reset the TV.
• To display / clear the error code buffer. 12. SW Events. Only to be used by development to monitor
• To perform alignments. SW behaviour during stress test.

Specifications How to Navigate


• Operation hours counter (maximum five digits displayed). • In the SAM menu, select menu items with the MENU UP/
• Software version, error codes, and option settings display. DOWN keys on the remote control transmitter. The
• Error buffer clearing. selected item will be indicated. When not all menu items fit
• Option settings. on the screen, use the MENU UP/DOWN keys to display
• Software alignments (Tuner, White Tone, and Audio). the next / previous menu items.
• NVM Editor. • With the MENU LEFT/RIGHT keys, it is possible to:
• ComPair Mode switching. – Activate the selected menu item.
• Set the screen mode to full screen (all contents on screen – Change the value of the selected menu item.
are viewable). – Activate the selected sub menu.
• When you press the MENU button twice while in top level
How to Activate SAM, the set will switch to the normal user menu (with the
SAM mode still active in the background). To return to the
To activate SAM, use one of the following methods:
SAM menu press the MENU button.
• Press the following key sequence on the remote control
transmitter: “062596" directly followed by the OSD/ • Command “OSD/i+” key from the user remote will toggle
the OSD “on/off” with “SAM” OSD remaining always “on”.
STATUS/INFO/i+ button (it depends on region which
• Press the following key sequence on the remote control
button is present on the RC). Do not allow the display to
time out between entries while keying the sequence. transmitter: “062596” directly followed by the MENU button
to switch to SDM (do not allow the display to time out
• Or via ComPair.
between entries while keying the sequence).
After entering SAM, the following screen is visible, with SAM in
the upper right corner of the screen to indicate that the How to Store SAM Settings
television is in Service Alignment Mode. To store the settings changed in SAM mode (except the
OPTIONS settings), leave the top level SAM menu by using the
S A M POWER button on the remote control transmitter or the
television set.
L L L L L A A A A B C D - X . Y Y
E R R X X X X X X X X X X
O P X X X X X X X X X X X X X X X X X X
How to Exit
C l e a r > Y e s Switch the set to STANDBY by pressing the mains button on
O p t i o n s > the remote control transmitter or the television set.
T u n e r >
R G B A l i g n >
N V M E d i t o r >
C o m p a i r >
Note:
S W E V E N T S > • When the TV is switched “off” by a power interrupt while in
SAM, the TV will show up in "normal operation mode" as
G_16860_031.eps
260107
soon as the power is supplied again. The error buffer will
not be cleared.
• In case the set is in Factory mode by accident (with “F”
Figure 5-4 SAM menu
displayed on screen), by pressing and hold “VOL-“ and
“CH-” together should leave Factory mode.
Menu explanation:
1. LLLLL. This represents the run timer. The run timer counts
normal operation hours, but does not count Stand-by
hours.
2. AAAABCD-X.YY. See paragraph “Service Modes” ->
“General” -> “Software Identification, Version, and Cluster”
for the SW name definition.
3. SAM. Indication of the Service Alignment Mode.
4. ERR (ERRor buffer). Shows all errors detected since the
last time the buffer was erased. Five errors possible.
5. OP (Option Bytes). Used to read-out the option bytes. See
“Options” in the Alignments section for a detailed
description. Seven codes are possible.
6. Clear. Erases the contents of the error buffer. Select the
CLEAR menu item and press the MENU RIGHT key. The
content of the error buffer is cleared.
7. Options. Used to set the option bits. See “Options” in the
“Alignments” chapter for a detailed description.
8. Tuner. Used to align the tuner. See “Tuner” in the
“Alignments” chapter for a detailed description.
9. RGB Align. Used to align the White Tone. See “White
Tone” in the “Alignments” chapter for a detailed
description.
10. NVM Editor. Can be used to change the NVM data in the
television set. See also paragraph “Fault Finding and
Repair Tips” further on.
11. ComPaIr. Can be used to switch the television to “In
Application Programming” mode (IAP), for software
EN 18 5. LC7.5E LA Service Modes, Error Codes, and Fault Finding

5.2.4 Customer Service Mode (CSM) Menu Explanation


1. MODEL. Type number, e.g. 32PFL7762D/05. (*)
Purpose 2. PROD S/N. Product serial no., e.g. AG1A0712123456. (*)
The Customer Service Mode shows error codes and 3. SW ID. Software cluster and version is displayed.
information on the TV’s operation settings. A call centre can 4. OP. Option code information.
instruct the customer (by telephone) to enter CSM in order to 5. CODES. Error buffer contents.
identify the status of the set. This helps them to diagnose 6. SSB. Indication of the SSB factory ID (= 12nc). (*)
problems and failures in the TV before making a service call. 7. NVM. The NVM software version no.
The CSM is a read-only mode; therefore, modifications are not 8. Flash Data. PQ (picture quality) and AQ (audio quality)
possible in this mode. data version. This is a sub set of the main SW.
9. DISPLAY. Indication of the display ID (=12 nc).
Specifications 10. TUNER. Indicates the tuner signal condition: “Weak” when
• Ignore “Service unfriendly modes”. signal falls below threshold value, “Medium” when signal is
• Line number for every line (to make CSM language at mid-range, and “Strong” when signal falls above
independent). threshold value.
• Set the screen mode to full screen (all contents on screen 11. SYSTEM. Gives information about the video system of the
are viewable). selected transmitter (PAL/SECAM/NTSC).
• After leaving the Customer Service Mode, the original 12. SOUND. Gives information about the audio system of the
settings are restored. selected transmitter (MONO/STEREO/NICAM).
• Possibility to use “CH+” or “CH-” for channel surfing, or 13. n.a.
enter the specific channel number on the RC. 14. HDAU. HDMI audio stream detection. “YES” means audio
stream detected. “NO” means no audio stream present.
Only displayed when HDMI source is selected.
How to Activate
15. FORMAT. Gives information about the video format of the
To activate CSM, press the following key sequence on the
selected transmitter (480i/480p/720p/1080i).
remote control transmitter: “123654” (do not allow the display
16. L.T. (LIFE TIMER). Operating hours indication.
to time out between entries while keying the sequence).
17. FPGA FW. Only applicable to sets with an FPGA.
18. Reserved.
Upon entering the Customer Service Mode, the following
screen will appear:
(*) If an NVM IC is replaced or initialised, the Model Number,
C S M Serial Number, and SSB Code Number must be re-written to
1 M O D E L : 3 2 P F L 7 7 6 2 D / 0 5 the NVM. ComPair will foresee in a possibility to do this.
2 P R O D S / N : A G 1 A 0 7 1 2 1 2 3 4 5 6
3 S W I D : L C 7 5 E L 1 - 1 . x x
4 O P : X X X X X X X X X X X X X X X X X X X X X
5 C O D E S : X X X X X X X X X X How to Exit
6 S S B : 3 1 3 9 1 2 7 1 2 3 4 1
7 N V M : X X X X X X X X To exit CSM, use one of the following methods:
8 F l a s h D a t a : X X . X X . X X . X X • Press the MENU button twice, or POWER button on the
9 D I S P L A Y : xxxx xxx xxxxx
PAGE DOWN B
y remote control transmitter.
H_17370_035a.eps
080807 • Press the POWER button on the television set.

Figure 5-5 CSM menu -1- (example)

C S M
1 0 T U N E R : WE A K / G O O D / S T R O NG
1 1 S Y S T E M: P A L / NT S C / S E C A M
1 2 S O U N D : MO N O / S T E R E O / NI C A M
1 3
1 4 H D A U : YES/N O
1 5 F O R M A T : X X X X X X X X
1 6 L. T. : xxxxxx
1 7 F P G A F W : xx.xx.xx
1 8 :
PAGE UP :B
y

H_17370_035b.eps
080807

Figure 5-6 CSM menu -2- (example)


Service Modes, Error Codes, and Fault Finding LC7.5E LA 5. EN 19

5.2.5 Digital Customer Service Mode (DCSM)

Purpose
The Digital Customer Service Mode shows error codes and
information on the IBO Zapper module (DVB reception part)
operation settings. The call centre can instruct the customer to
activate DCSM by telephone and read off the information
displayed. This helps the call centre to diagnose problems and
failures in the IBO Zapper module before making a service
call.The DCSM is a read-only mode; therefore, modifications
are not possible in this mode.

How to Activate
To activate the DCSM, put the television in its digital mode (via
the “A/D” button on the remote control).
1. Press the “Digital Menu” button on the remote control to
activate the digital user menu (called “Setup”). E_14970_042.eps
2. Activate the “Information” sub menu (via the “down” and 090904
“right” cursor buttons).
3. In the “Information” sub menu, press the following key Figure 5-9 DCSM menu - 3
sequence on the remote control to activate the DCSM:
“GREEN RED YELLOW 9 7 5 9” (do not allow the display 1. Hardware version: This indicates the version of the IBO
to time out between entries while keying this sequence). Zapper module hardware.
Then, the “Service menu” will appear (see figures below). 2. Application SW: The application software version.
3. NOR Version: The NOR Flash image software version
Alternative method to activate DCSM: press key sequence 4. Digital Frequency: The digital frequency that the set is
“123654” on the remote control transmitter while in digital mode tuned to.
(do not allow the display to time out between entries while 5. Bit Error Rate: The error rate measured before the error
keying the sequence). Then, the “Service menu” will appear correction algorithm circuitry. (this value gives an
(see figures below). impression of the received signal)
6. Tuner AGC: Tuner AGC value.
Menu explanation 7. COFDM Lock: Indication if COFDM decoder is locked.
8. AFD Status: Status of the Active Picture Format
Descriptor.
9. Terrestrial Delivery System Parameters:
– Bandwidth: Bandwidth of the received signal.
– Constellation Pattern: Displays the signal
constellation.
– Alpha Value: Displays the Alpha Value.
– FEC Scheme: Displays the Forward Error Correcting
Scheme
– Guard Interval: Displays the value for the Guard
Interval.
– Transmission Mode: Displays the Transmission
Mode.
10. Audio Comp Type: Type of detected audio stream.
11. MHEG Present: Indicates if MHEG is present or not.
12. CIM Card Present: Indicates if CIM card is present or not.
E_14970_040.eps
090904
How to exit
Press the BLUE button on the Remote Control to exit DCSM.
Figure 5-7 DCSM menu - 1

E_14970_041.eps
100904

Figure 5-8 DCSM menu - 2


EN 20 5. LC7.5E LA Service Modes, Error Codes, and Fault Finding

5.3 Service Tools • ComPair UART interface cable: 3138 188 75051 (to be
used with chassis LC7.5).
5.3.1 ComPair
Note: If you encounter any problems, contact your local
support desk.
Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips
Consumer Electronics products. and offers the following: 5.3.2 LVDS Tool
1. ComPair helps you to quickly get an understanding on how
to repair the chassis in a short and effective way. Support of the LVDS Tool has been discontinued.
2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. You do not
have to know anything about I2C or UART commands
yourself, because ComPair takes care of this.
3. ComPair speeds up the repair time since it can
automatically communicate with the chassis (when the uP
is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.

Specifications
ComPair consists of a Windows based fault finding program
and an interface box between PC and the (defective) product.
The (new) ComPair II interface box is connected to the PC via
an USB cable. For the TV chassis, the ComPair interface box
and the TV communicate via a bi-directional cable via the
service connector(s).

How to Connect
This is described in the ComPair chassis fault finding database.

TO TV

TO TO TO
UART SERVICE I2C SERVICE UART SERVICE
CONNECTOR CONNECTOR CONNECTOR

ComPair II
Multi
RC in function
RC out

Optional Power Link/ Mode


Switch Activity I2C RS232 /UART

PC

ComPair II Developed by Philips Brugge

Optional power
HDMI 5V DC
I2C only

G_06532_036.eps
240807

Figure 5-10 ComPair II interface connection

Caution: It is compulsory to connect the TV to the PC as


shown in the picture above (with the ComPair interface in
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs will be
blown!

How to Order
ComPair II order codes:
• ComPair II interface: 3122 785 91020.
• ComPair32 CD (update): 3122 785 60160.
• ComPair I2C interface cable: 3122 785 90004 (to be used
with chassis L01, A02, A10, EMX, ...).
• ComPair I2C interface extension cable: 3139 131 03791 (to
be used with chassis L01, A02, A10, L04, LC4, LC7.1,
LC7.2).
• ComPair UART interface cable: 3122 785 90630 (to be
used with chassis LC4, EJ3, BJ2, BL2, BP2, ...).
• ComPair RS232 cable: 3104 311 12742 (to be used with
chassis Q52x).
• ComPair I2C adapter cable: 3122 785 90004 (to be used
with chassis TPM1.xA).
• ComPair I2C interface cable: 9965 100 07325 (to be used
with chassis LC7.5).
Service Modes, Error Codes, and Fault Finding LC7.5E LA 5. EN 21

5.4 Error Codes Table 5-2 Error code overview

5.4.1 Introduction Error


code1) Description Item nr. Remarks
0 No error.
Error codes are required to indicate failures in the TV set. In 1 DC Protection of speakers.
principle a unique error code is available for every: 2 +12V protection error. 12V missing or "low".
• Activated protection. 3 Reserved.
• Failing I2C device. 4 General I2C error. note 2
• General I2C error. 5 Trident Video Processor 7C01 When Trident IC is
• SDRAM failure. communication error. defective, error 10 and 14
might also be reported.
The last five errors, stored in the NVM, are shown in the Trident communicates via
parallel bus, not via the I2C
Service menu’s. This is called the error buffer. bus. The I2C bus of Trident
The error code buffer contains all errors detected since the last is only used in ComPair
time the buffer was erased. The buffer is written from left to mode.
right. When an error occurs that is not yet in the error code 6 I2C error while communicating 7L23 The TV will not start-up due
buffer, it is displayed at the left side and all other errors shift one with the NVM. to critical data not available
from the NVM, but the LED
position to the right. will blink the error code.
An error will be added to the buffer if this error differs from any 7 I2C error while communicating 1101
error in the buffer. The last found error is displayed on the left. with the Tuner.
An error with a designated error code may never lead to a 8 I2C error while communicating 7113
deadlock situation. This means that it must always be with the IF Demodulator.
diagnosable (e.g. error buffer via OSD or blinking LED 9 I2C error communicating with 7411
procedure, ComPair to read from the NVM). the Sound Processor.

In case a failure identified by an error code automatically 10 SDRAM defective. 7D01

results in other error codes (cause and effect), only the error 11 I2C error while communicating 7N01
with the HDMI IC.
code of the MAIN failure is displayed.
12 I2C error while communicating 7H03 if applicable
with the MOJO PNX8314.
Example: In case of a failure of the I2C bus (CAUSE), the error 13 DVB HW communication 7F01, if applicable
code for a “General I2C failure” and “Protection errors” is error. 7K00,
displayed. The error codes for the single devices (EFFECT) is 7H03
not displayed. All error codes are stored in the same error 14 SDRAM defective. 7D02
buffer (TV’s NVM) except when the NVM itself is defective. 15 I2C error while communicating 7F01
with the IBO COFDM channel
decoder.
5.4.2 How to Read the Error Buffer 16 I2C error while communicating 7H03
with the IBO NVM.
You can read the error buffer in 3 ways: 17 I2C error while communicating 7700 or
• On screen via the SAM/SDM/CSM (if you have a picture). with FPGA external

Example: 18 Reserved. (iTV)

– ERROR: 0 0 0 0 0 : No errors detected 19 Reserved. (1080p bolt-on module)

– ERROR: 6 0 0 0 0 : Error code 6 is the last and only 20 I2C error while communicating 7K00
with the IBO PCMCIA
detected error controller.
– ERROR: 9 6 0 0 0 : Error code 6 was detected first and 21 I2C error while communicating 7M07
error code 9 is the last detected (newest) error with the HDMI mux IC
• Via the blinking LED procedure (when you have no 22 I2C error while communicating
picture). See “The Blinking LED Procedure”. with the HDMI buffer in Side A/
• Via ComPair. V Panel
23 Reserved.

5.4.3 Error Codes


Notes
In case of non-intermittent faults, write down the errors present 1. Some of the error codes reported are depending on the
in the error buffer and clear the error buffer before you begin option code configurations.
the repair. This ensures that old error codes are no longer 2. This error means: no I2C device is responding to the
present. particular I2C bus. Possible causes: SCL/SDA shorted to
If possible, check the entire contents of the error buffer. In GND, SCL shorted to SDA, or SCL/SDA open (at uP pin).
some situations, an error code is only the result of another error The internal bus of the Trident platform should not cause
and not the actual cause of the problem (for example, a fault in the entire system to halt as such an error can be reported.
the protection detection circuitry can also lead to a protection).
5.4.4 How to Clear the Error Buffer

The error code buffer is cleared in the following cases:


• By using the CLEAR command in the SAM menu:
– To enter SAM, press the following key sequence on the
remote control transmitter: “062596” directly followed
by the OSD/i+ button (do not allow the display to time
out between entries while keying the sequence).
– Make sure the menu item CLEAR is selected. Use the
MENU UP/DOWN buttons, if necessary.
– Press the MENU RIGHT button to clear the error
buffer. The text on the right side of the “CLEAR” line will
change from “CLEAR?” to “CLEARED”
• If the contents of the error buffer have not changed for 50
hours, the error buffer resets automatically.
EN 22 5. LC7.5E LA Service Modes, Error Codes, and Fault Finding

Note: If you exit SAM by disconnecting the mains from the 5.6 Software Upgrading
television set, the error buffer is not reset.
In this chassis, three SW “stacks” are used:
5.5 The Blinking LED Procedure • TV mains SW (processor and processor NVM).
• Digital TV SW (IBO Zapper).
5.5.1 Introduction
5.6.1 TV Main SW Upgrade
The software is capable of identifying different kinds of errors.
Because it is possible that more than one error can occur over For instructions on how to upgrade the TV Main software, refer
time, an error buffer is available, which is capable of storing the to ComPair.
last five errors that occurred. This is useful if the OSD is not
working properly. 5.6.2 “Digital TV” Software Upgrade

Errors can also be displayed by the blinking LED procedure. How to Upgrade Philips “Digital TV” Software (IBO Zapper):
The method is to repeatedly let the front LED pulse with as
many pulses as the error code number, followed by a period of Preparation of the Memory Device for Software Upgrade
1.5 seconds in which the LED is “off”. Then this sequence is For the procedure you will require:
repeated. 1. A personal computer with web browsing capability.
2. An archive utility that supports the ZIP-format (e.g. Winzip
Example (1): error code 4 will result in four times the sequence for Windows).
LED “on” for 0.25 seconds / LED “off” for 0.25 seconds. After 3. A CompactFlash PC Card Adapter (Type II).
this sequence, the LED will be “off” for 1.5 seconds. Any RC5 4. A CompactFlash (Type I) portable memory card for
command terminates the sequence. Error code LED blinking is insertion into the PC Card Adapter. Philips recommends
in red colour. using Compact Flash (CF) portable memory cards with
their respective PC Card Adapters (Sandisk or Kingston)
Example (2): the content of the error buffer is “12 9 6 0 0” with memory sizes of up to 256MB. Philips does not
After entering SDM, the following occurs: guarantee that other types of portable memory cards and
• 1 long blink of 5 seconds to start the sequence, their respective PC Card Adapters, including multi-card PC
• 12 short blinks followed by a pause of 1.5 seconds, Card Adapters work on Philips Digital TV.
• 9 short blinks followed by a pause of 1.5 seconds, Note: Only FAT16-formatted portable memory is
• 6 short blinks followed by a pause of 1.5 seconds, supported. NTFS & FAT32 are not supported.
• 1 long blink of 1.5 seconds to finish the sequence,
• The sequence starts again with 12 short blinks.
Copying of Software Image Files to the Flash Device
Copy the appropriate “FCL.img” and “IBOZ.img” to the root
5.5.2 Displaying the Entire Error Buffer directory of the flash device.

Additionally, the entire error buffer is displayed when Service Verifying the Current Version of the TV Software
Mode “SDM” is entered. In case the TV set is in protection or Before you start the software upgrade procedure, it is advised
Stand-by: The blinking LED procedure sequence (as in SDM- to check what the current TV software is. The current TV
mode in normal operation) must be triggered by the following software version can be seen in the “System software” menu.
RC sequence: “MUTE” “062500” “OK”. 1. First press the “A/D” key and then the “DIGITAL MENU”
In order to avoid confusion with RC5 signal reception blinking, key on the remote controller to access the “Setup” menu.
this blinking procedure is terminated when a RC5 command is 2. Access the “Information” menu.
received. 3. Access the “Current software version” menu.

To erase the error buffer, the RC command “MUTE” “062599 Example:


“OK” can be used. The menu shows “IdtvZapper_HW260.256_SW2.0.24”. This
means that the hardware version is “260.256” and the software
version is “2.0.24”.

G_16221_001.eps
241006

Figure 5-11 Current software version


Service Modes, Error Codes, and Fault Finding LC7.5E LA 5. EN 23

Software Upgrade Procedure


1. Power ON your TV with the power switch at the side of the
TV. Put your TV ON by using the remote controller if the TV
is in Stand-by.
2. Make sure that it is in “Digital” mode (via “A/D” button).
3. Make sure that your TV is not in Stand-by. Power OFF your
TV with the power switch of the TV.
4. Remove the Conditional Access Module (if any) from the
CI-slot.
5. Insert the PC Card Adapter with the portable memory card
containing the software upgrade files.
6. Switch ON your TV with the power switch at the side of the G_16221_005.eps
241006
TV.
7. At start-up, the TV will scan the CI slot until it finds the
update content. The TV will automatically go to the Figure 5-15 Upgrade ready
upgrade mode. After a few seconds it will display the status
of the upgrade procedure. When the software upgrade has been successful, switch OFF
the TV, remove the PC Card Adapter, and restart the TV with
Warnings: the Power switch at the side of the TV.
Do NOT remove the memory card or the PC card adapter The TV will now start up with the new software.
during the software upgrade procedure.
In case of a power drop during the upgrade procedure, don’t Verifying that the Software Has Been Upgraded
remove the portable memory from the TV. The TV will continue Successfully
the upgrade as soon as the power comes back. Verify that the software is upgraded to the new version by
following the procedure outlined in the section “Verifying the
Example: At start-up of the TV, the current software is erased. current version of the TV software”.

G_16221_002.eps
241006

Figure 5-12 Erasure of the software

If the erasure is successful, the programming will start.

G_16221_003.eps
241006

Figure 5-13 Programming of the software

Example: The programming is completed when the progress


bar reaches the 100% mark.

G_16221_004.eps
241006

Figure 5-14 Programming complete

The TV will reset and the screen will go blank, after a few
seconds a dialogue box will occur to inform you that the current
module inserted in the CI slot is not recognized. This is normal
as the slot only recognizes a Conditional Access Module during
normal operation.

Example: The following dialogue box will appear after the TV is


upgraded successfully:
EN 24 5. LC7.5E LA Service Modes, Error Codes, and Fault Finding

5.7 Fault Finding and Repair Tips Alternative method (1):


1. Go to SAM.
Notes: 2. Select NVM Editor.
• It is assumed that the components are mounted correctly 3. Select ADR (address) to 1 (dec).
with correct values and no bad solder joints. 4. Change the VAL (value) to 170 (dec).
• Before any fault finding actions, check if the correct options 5. Store the value.
are set. 6. Do a hard reset to make sure new default values took
place.

5.7.1 NVM Editor


Alternative method (2):
It is also possible to upload the default values to the NVM with
In some cases, it can be convenient if one directly can change
ComPair in case the SW is changed, the NVM is replaced with
the NVM contents. This can be done with the “NVM Editor” in
a new (empty) one, or when the NVM content is corrupted.
SAM mode. With this option, single bytes can be changed.
After replacing an EEPROM (or with a defective/no EEPROM),
default settings should be used to enable the set to start-up and
Caution:
allow the Service Default Mode and Service Alignment Mode to
• Do not change the NVM settings without
be accessed.
understanding the function of each setting, because
incorrect NVM settings may seriously hamper the
correct functioning of the TV set! 5.7.3 Start-up/Shut-down Flowcharts
• Always write down the existing NVM settings, before
changing the settings. This will enable you to return to the Important note for DVB sets:
original settings, if the new settings turn out to be incorrect. • When you put a DVB set into Stand-by mode with an RC,
the set will go to “Semi Stand-by” mode for 5 minutes. This,
Table 5-3 NVM editor overview to facilitate “Off the Air download” (OAD). If there is no
activity within these 5 minutes, the set will switch to Stand-
by mode. In “Semi Stand-by” mode, the LCD backlight and
Hex Dec Description
Audio Amplifier are turned “off” but other circuits still work
.ADR 0x000A 10 Existing value
as normal. The customer might think the set is in Stand-by.
.VAL 0x0000 0 New value
However, in real Stand-by mode, only the uP and the NVM
.Store Store?
are alive and all other circuits are switched “off”.
• If you press the mains switch at the local key board in a
5.7.2 Load Default NVM Values DVB set, the set will switch to Stand-by mode.

It is possible to download default values automatically into the On the next pages you will find start-up and shut-down
NVM in case a blank NVM is placed or when the NVM first 20 flowcharts, which might be helpful during fault finding.
address contents are "FF". After the default values are Please note that some events are only related to PDP sets,
downloaded, it is possible to start-up and to start aligning the and therefore not applicable to this LCD chassis.
TV set. To initiate a forced default download the following
action has to be performed:
1. Switch “off” the TV set with the mains cord disconnected
from the wall outlet (it does not matter if this is from "Stand-
by" or "Off" situation).
2. Short-circuit the SDM jumpers on the SSB (keep short
circuited).
3. Press “P+” or “CH+” on the local keyboard (and keep it
pressed).
4. Reconnect the mains supply to the wall outlet.
5. Release the “P+” or “CH+” when the set is “on” or blue LED
is blinking.
When the downloading has completed successfully, the set
should be into Stand-by, i.e. red LED on.
Service Modes, Error Codes, and Fault Finding LC7.5E LA 5. EN 25

V1.5 AC ON
LC07S
Start Up 13 June 2007

+5VSTBY & +3V3STBY Available

M16C POR by +3VSTBY


150ms
STANDBYn = LOW

InitCold Component:
Error 6 - NVM 1. Check SDM port.
[Protection] - If SDM pin = LOW and NVM first 20Byte = 0xFF,
reload Software default NVM value.
2. Check Panel port.
- If Panel Pin = LOW and check slave address
0x65 = 0xA5, Enter Panel Mode.
HDMI_MUX_RST
Reset (LOW =150ms) then go to HIGH

No Last status is ON?


User wake up the sets
in DVB recording mode
Yes
Standby Normal
No Mode
Yes Read NVM completed. LCD_PWR_ON = HIGH
STOP I²C activities. (Same function as CTRL-DISP2)
SDI PDP => CTRL_DISP1 = LOW
Disable Audio Mute
Standby Soft Mode Standby Normal Mode LED = BLUE for Normal mode
(NO LED) (RED LED) LED = RED for Recording mode
20ms Wait for 20 ms

Disable Audio Mute


Port Assignment in STANDBY BLOCK RC Key
Port Assignment in STANDBY

Switch ON LVDS Signal


Wait for RC key or Yes M16C RST_H = LOW
Wait for Power Local Key
Wake up event HDMI_RST_RX_BUF=LOW
RST_AUD = LOW
RESET_n = LOW 2000ms to Init. Warm Component
LCD_PWR_ON = LOW 2500ms (For software)
SDI PDP => CTRL_DISP1 = LOW

For LCD:
Enable Audio Mute ( 50ms) BL_ON_OFF = HIGH
50ms STANDBYn = HIGH * BL_ADJ keep 100% for 1000ms
(Same function as CTRL-DISP3) For PDP:
then reduce gradually to 70% from
3000ms delay
1001ms to 3000ms .After 3000ms
* 100ms for 12V rising 100ms Wait for 100ms do the dimming according to
picture content.

Error 2 Wait for 100ms Is Power Down =


No
[Protection] Time out = 2000ms HIGH? Blank Picture
Picture Mode Setup & Detection
Yes
* 50ms for 1V2 DC-DC wait
* 50ms for Trident requirement 100ms Wait for 100ms
unBlank Picture &
Notes: UnMute Audio
M16C RST_H = HIGH
---------
1. LC07S TV software only start communication with IBOZ once 300ms Wait for 300ms
receive the INT message from IBOZ. End
2.Initialise HDMI MUX & Buffer IIC address ( EDID,CEC)
(SVP_Trident) M16C RST_H to LOW
3.RESET_n is to reset IBOZ HDMI_RST_RX_BUF= HIGH
4. Enable Mute mean ANTI_PLOP= LOW, MUTEn=HIGH RST_AUD = HIGH
5. Disable Mute mean ANTI_PLOP = HIGH, MUTEn=LOW (IBO) RESET_n = HIGH

Enable Power Down INT


Enable DC_PROT INT No
Wait for IBO Config
MAX 500 ms
Initialise Trident WX
KMNPLL Latch data need 50us setup time
500ms BL_ADJ = HIGH (100% Duty Cycle) first!!
DPTVInit( )
Wait for IBO System Ready
MAX 5000 ms
Error 7 Initialise Tuner

Initialise IF Demodulator, Afric


Error 8
TDA9886T

Error 9 Initialise Micronas


For DVB Sets only (Semistandby) Mute Audio
Recording mode
SDI PDP => CTRL_DISP1 = HIGH
FHP PDP => CTRL_DISP4 = LOW Error 11 Initialise HDMI Receiver, Sil 9125

Recording Mode finished Error 5 - Trident


Error 21 Initialise HDMI Mux, Sil 9185 [Protection]

Error 10 – SDRAM 7204


[Protection]
Software Shutdown: Error 22 Initialise HDMI Buffer, Sil 9181
Error 14 – SDRAM 7205
AmbiLight Set [Protection]
Initialise AmbiLight
WP for NVM
Error 3 Error 17 – AmbiLight
Yes Initialise FHP Panel (Provision)
[Protection]
* For FHP PDP Sets only

Port Assignment in STANDBY Initialise Bolt-ON Error 18 – iTV iFace


(100Hz, iTV, USB) TBC

Error 19 – 1080P
STANDBYn = LOW Enable RC Key

Standby
Normal Mode DVB recording mode H_17370_056.eps
090807

Figure 5-16 Start-up flowchart


EN 26 5. LC7.5E LA Service Modes, Error Codes, and Fault Finding

Start
SEMISTANDBY/ STANDBY

Mute Audio (ANTI_PLOP=LOW)


(MUTEn =HIGH)

BL_ADJ
(PWM duty cycle 70%)

BL_ON_OFF = LOW

300ms Wait 300ms

Switch OFF LVDS

20ms Wait 20ms

LCD_PWR_ON = LOW

Software Shutdown:

Standby using
LED = RED No
“power key”

For DVB Sets only (Semistandby)


Wait for 3000ms Yes
Except power tact switch
LED = NO LED
for Standby soft mode

SDI PDP => CTRL_DISP1 = HIGH


FHP PDP => CTRL_DISP4 = LOW
Disable Power Down INT &
DC_PROT_INT

Off Air Downloading/ Recording Mode


BL_ADJ = LOW
(PWM duty cycle 0%)

IBOZ send shut down command

WP for NVM

(ANTI_PLOP =HIGH)
(Mute_n = LOW)
Enable Audio Mute
Port Assignment in STANDBY Sets go to standby here

Blocking for the next start up to ensure


40ms STANDBYn = LOW power supply discard properly.

Total = 360ms

Wait for 3000ms

Disable Audio Mute (ANTI_PLOP =HIGH)


(Mute_n = LOW)

H_17370_057.eps
End 090807

Figure 5-17 Semi Stand-by/Stand-by flowchart


Service Modes, Error Codes, and Fault Finding LC7.5E LA 5. EN 27

Start
Power Down INT:
AC OFF or Transient INT
Avoid false trigger
Poll the Power Down
No
INT for 5 times

Yes
End
Mute Audio & VIdeo

Notes:
1. Power Down INT will based on fall edge triggering
2. +3V3STBY will stay for 15ms, software must perform WP for NVM within 15ms. WP for NVM

STANDBYn = LOW

Wait 5000 ms

Re-start: Start up

End

DC_PROT INT

Start

Avoid false trigger


is DC_PROT = LOW
No
for 3 sec?

Yes

End
Mute Audio & VIdeo

Error 1 Log Error Code


[Protection]

WP for NVM

STANDBYn = LOW

End H_17370_058.eps
090807

Figure 5-18 Power Down & DC_PROT flowchart


EN 28 5. LC7.5E LA Service Modes, Error Codes, and Fault Finding

Personal Notes:

E_06532_012.eps
131004
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 29

6. Block Diagrams, Test Point Overviews, and Waveforms


Wiring Diagram 32” LCD (ME7)
WIRING 32” LCD (STYLING ME7)
CN2
DISPLAY SUPPLY
1. +24VI
2. +24VI
3. +24VI
LCD DISPLAY
(1004)
4. +24VI
5. +24VI
6. GND3
7. GND3
8. GND3
9. GND3
LVDS
10. GND3 30P
4P 4P
11. VBRI CN4 CN5 TO SUBWOOFER
12. ON/OFF IN BACK COVER
13. PWM

CN6
(5226)

9P
8B12
14. GND1

CN2
14P
8R01
CN3

CN7
8P
8B13
DISPLAY SUPPLY
1. +24VI
CN3
12P

2. +24VI
8319

8305
3. +24VI 8304
4. +24VI
CN2
14P

5. +24VI MAIN SUPPLY 6P 8P 10P 5P 41P 3P 7P 11P 3P 4P


6. GND3 (1005) 1B12 1B13 1305 1201 1R01 1A02 1L20 1304 1A03 1A01

CN3
7. GND3

12P
ONLY USED
8316
FOR LPL PANEL
8. GND3
9. GND3 SSB
B (1150)
10. GND3
11. N.C.
INVERTER INVERTER
12. N.C.

CONTROL
CN6
CONTROL:
1. -12V(audio)
2. +12V(audio)

1N01
21P

E KEYBOARD
3. GND2(audio)
TUNER
4. 5.2VS
5. 5.2VS
6. 5.2VS D SIDE I/O
(1116)
CN1
2P3

(1114)
7. GND1
8. GND1

1R04
11P
8R04
9. GND1

1Q02
8308

10P

1M01
CN7

3P
CONTROL:
INLET
1. BL-ADJUST

1Q03
21P
8N01

8M01
2. PG
3. BL_ON_OFF
4. GND1
5. BOOST
8192(UK)

8M20 7P 3P
8191

6. PSON 1M20 1M01


7. N.C. RIGHT SPEAKER LEFT SPEAKER
8. +12V (5213) (5215) IR/LED/LIGHT
(5215) (5213) J SENSOR
(1112)

H_17371_001.eps
171007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 30

Wiring Diagram 32” LCD with AmbiLight (ME7)


WIRING 32” LCD + AMBI LIGHT (STYLING ME7)
CN2
DISPLAY SUPPLY
1. +24VI
2. +24VI
3. +24VI
LCD DISPLAY
(1004)
4. +24VI 8M82
5. +24VI 8M09 8M09
8M59
6. GND3
7. GND3
8. GND3

(IN BACK COVER)


8116
9. GND3
LVDS
10. GND3
1M09

4P 4P 30P
4P7

11. VBRI CN4 CN5 TO SUBWOOFER


12. ON/OFF IN BACK COVER
13. PWM

CN6
(5226)

9P
8B12
14. GND1
1M59

CN2
14P
5P

8R01

AMBI-LIGHT UNIT
CN3

CN7
8P
8B13
1M82

DISPLAY SUPPLY
7P

1. +24VI
CN3
2. +24VI 12P
8319

8305
3. +24VI 8304
4. +24VI
CN2
14P

MAIN SUPPLY
(IN BACK COVER)

5. +24VI 6P 8P 10P 5P 41P 3P 7P 11P 3P 4P


6. GND3 (1005) 1B12 1B13 1305 1201 1R01 1A02 1L20 1304 1A03 1A01

CN3
7. GND3

12P
ONLY USED
8316
FOR LPL PANEL
8. GND3
9. GND3 SSB
B (1150)
10. GND3 INVERTER
INVERTER
11. N.C.
12. N.C.

1M82
AMBI-LIGHT UNIT

4P7

CONTROL
CN6

1M59
CONTROL:

5P
1. -12V(audio)
2. +12V(audio)

1N01
21P

E KEYBOARD
3. GND2(audio)
TUNER

1M09
4. 5.2VS

4P
5. 5.2VS
6. 5.2VS D SIDE I/O
(1116)
CN1
2P3

(1114)
7. GND1
8. GND1

1R04
11P
8R04
9. GND1

1Q02
8308

10P

1M01
CN7

3P
CONTROL:
1. BL-ADJUST INLET

1Q03
21P
8N01

8M01
2. PG
3. BL_ON_OFF
4. GND1
5. BOOST 8192(UK)
8M20 7P 3P
8191

6. PSON 1M20 1M01


7. N.C. RIGHT SPEAKER LEFT SPEAKER
8. +12V (5213) (5215) IR/LED/LIGHT
(5215) (5213) J SENSOR
(1112)

H_17371_002.eps
171007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 31

Wiring Diagram 42” LCD (ME7)


WIRING 42” LCD (STYLING ME7)

LCD DISPLAY
(1004)

LVDS
51P

8316
8319 8R03
8B12
8B13

8P 14P 12P
9P X406 X404 X403
4P
X412
X405
4P
X411 TO SUBWOOFER
IN BACK COVER
(5226)

MAIN SUPPLY
(1005)
CN2
14P

8305
8304

CN3
12P
6P 8P 10P 5P 41P 3P 7P 11P 3P 4P
1B12 1B13 1305 1201 1R01 1A02 1L20 1304 1A03 1A01
INVERTER INVERTER
B SSB
(1150)

CONTROL
1N01
21P

E KEYBOARD
X101
2P3

D SIDE I/O
(1116)

(1114)
8308

1R04
11P
8R04

INLET

1Q02
10P

1M01
3P
1Q03
21P
8N01

8M01
8192(UK)
8191

8M20 7P 3P
LEFT SPEAKER 1M20 1M01
RIGHT SPEAKER
(5215) (5213) (5213) (5215) IR/LED/LIGHT
J SENSOR
(1112)

H_17371_003.eps
021007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 32

Wiring Diagram 42” LCD with AmbiLight (ME7)


WIRING 42” LCD + AMBI LIGHT (STYLING ME7)

8M82
8M59
8M09 8M09

LCD DISPLAY

AMBI-LIGHT UNIT (IN BACK COVER)


(1004)

LVDS
51P

8316
8319 8R03
8B12

8321
8B13

8P 14P 12P
1M09

X406 X404 X403


4P

9P
4P
X412
X405
4P
X411 TO SUBWOOFER
1M59
5P

IN BACK COVER

(1175)
(5226)
1M82
4P7

MAIN SUPPLY
(1005)
CN2

1M82
14P

4P7
8305
8304
AMBI-LIGHT UNIT (IN BACK COVER)

CN3

1M59
12P

5P
6P 8P 10P 5P 41P 3P 7P 11P 3P 4P
INVERTER 1B12 1B13 1305 1201 1R01 1A02 1L20 1304 1A03 1A01

1M09
4P
B SSB
(1150) INVERTER

CONTROL
1N01
21P

E KEYBOARD
(1175)

X101
2P3

D SIDE I/O
(1116)

(1114)
8308

1R04
11P
8R04

INLET

1Q02
10P

1M01
3P
1Q03
21P
8N01

8M01
8192(UK)
8191

8M20 7P 3P
LEFT SPEAKER 1M20 1M01
RIGHT SPEAKER
(5215) (5213) (5213) (5215)
IR/LED/LIGHT
J SENSOR
(1112)

H_17371_004.eps
181007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 33

Wiring Diagram 52” LCD (ME7)


WIRING 52” LCD (STYLING ME7)
CN2 CN3 CN6 CN7
DISPLAY SUPPLY DISPLAY SUPPLY CONTROL: CONTROL:
1. +24Vinv 1. +24Vinv 1. -12V(Audio) 1. BL-ADJUST
2. +24Vinv 2. +24Vinv 2. +12V(Audio) 2. Power OK
3. +24Vinv 3. +24Vinv 3. GND2(Audio) 3. BL_ON_OFF
4. +24Vinv 4. +24Vinv 4. 5V2stby 4. GND1
5. +24Vinv 5. +24Vinv 5. 5V2stby 5. Boost LCD DISPLAY
6. GND3 6. GND3 6. 5V2stby 6. STANDBY (1004)
7. GND3 7. GND3 7. GND1 7. N.C.
8. GND3 8. GND3 8. GND1 8. 12Vssb
9. GND3 9. GND3 9. GND1
10. GND3 10. GND3
11. Vbri 11. N.C. LVDS
12. ON/OFF 12. N.C. 51P
13. PWM 8316
14. GND1 8219 8R01
8B12
8B13

9P 8P
14P 12P CN6 CN7
CN2 CN3

TO SUBWOOFER
ON BACK COVER
(5226)

MAIN SUPPLY
(1005)
CN2
14P

8305
8304

CN3
12P
6P 8P 10P 5P 41P 3P 7P 11P 3P 4P
1B12 1B13 1305 1201 1R01 1A02 1L20 1304 1A03 1A01
INVERTER INVERTER
SSB
B (1150)

CONTROL
1N01
21P

E KEYBOARD
CN1
2P3

D SIDE I/O
(1116)

(1114)
8308

1R04
11P
8R04

INLET

1Q02
10P

1M01
3P
1Q03
21P
8N01

8M01
8192(UK)
8191

8M20 7P 3P
LEFT SPEAKER 1M20 1M01
RIGHT SPEAKER
(5215) (5213) (5213) (5215)
IR/LED/LIGHT
J SENSOR
(1112)

H_17371_005.eps
021007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 34

Block Diagram Video


VIDEO
B02 TUNER IF & DEMODULATOR +5VS
7113
1101 TDA9886T/V4
TD1316AF/IHP-2
1102
DEMODULATOR
5 VIF1 1 VIF1 SUPPLY
MAIN 8 IF_ATV 1 SOUND TRAPS CVBS 17
IF_OUT1 VIF-PLL
TUNER 4 VIF2 2 VIF2 4.5 to 6.5 Mhz
(HYBRID)
2
RF_AGC 1103
7111 5 SIF1 23 SIF1 SINGLE REFERENCE QSS MIXER
1 INTERCARRIER MIXER AND
10
11
9
12 RF_AGC_IBO AM-DEMODULATOR
B03A 4 SIF2 24 SIF2
14 MAD
SIF AGC
IF_AGC_IBO
13 RF_AGC 14 TAGC
I2C-BUS TRANSCEIVER
VIP_IBO
VIM_IBO

TUNER AGC VIF AGC

SDA
SCL
11
DVB_SW 7114
B04
EF

B03A DVB-DEMODULATOR B03B DVB-COMMON INTERFACE B03C DVB-MOJO B03E DVB-MOJO B05A TRIDENT - WX68 B05E FPGA I/O BANKS B07E LVDS CONNECTOR
ANALOG BACK END
7F01 7K00 7G00
TDA10046AHT PNX8314HS/C102 7C01
STV0700L
SVP WX68-7568-LF
COFDM 62
CHANNEL 61
PCMCIA MOJO CVBS_RF Y4
CVBS1
DECODER 2
CONTROLLER ADC
ADC 5J52
(PARALLEL)

172 C_CVBS IBO_CVBS_IN V4 FS1


VIDEO
MPEG-TS

C
TDA_DAT(0-7) TS_DATA(0-7) 163 B|Pb 5J54 IBO_B_IN W10
PC_B
(TS) B
(AV)
165 G|Y 5J53 IBO_G_IN Y7 PC_G
PROCESSOR 1R01
35 TDA_SYNC 49 62 TS_SYNC G 41
30 167 R|Pr 5J55 IBO_R_IN U8 PC_R
R +VDISP
21 1 40
TS
39
INTERFACE
7F04 38
COMP_OUT
B07B IO - SCART 1 & 2 ANALOG 4713 TxLVDSe_0n 1R02 LVDSe_0n 32
A14 TxFPGAe_0n
RF_AGC_IBO MUX
B02 1504 7503 B14 TxFPGAe_0p 4714 TxLVDSe_0p LVDSe_0p 31
3535 EF 3537 SC1_RF_OUT_CVBS
19 W2 TA1 4715 TxLVDSe_1n 1R03 LVDSe_1n 30
CVBS_OUT1 A15 TxFPGAe_1n
B15 TxFPGAe_1p 4716 TxLVDSe_1p LVDSe_1p 29
15 3528 SC1_R_IN W8
1K00 PR_R2 4717
3523 TB1 A16 TxFPGAe_2n TxLVDSe_2n 1R04 LVDSe_2n 28
11 SC1_G_IN W6 Y_G2
3516 B16 TxFPGAe_2p 4718 TxLVDSe_2p LVDSe_2p 27
7 SC1_B_IN Y9 PB_B2
A_MDO(0-7) 1 3545 TxFPGAe_CLKn 4725 TxLVDSe_CLKn 1R05 LVDSe_CLKn 25
20 SC1_CVBS_IN Y10 LVDSTC1 A18
PB_B3 OUT 4716
3528 Y5 B18 TxFPGAe_CLKp TxLVDSe_CLKp LVDSe_CLKp 24
16 SC1_FBL_IN
FB1
3518 A19 TxFPGAe_3n 4719 TxLVDSe_3n 1R06 TxLVDSe_3n 22
8 SC1_STATUS
PCMCIA 68P B04 TCLK1 4720
B19 TxFPGAe_3p TxLVDSe_3p TxLVDSe_3p 21
EXT1 B17 TxFPGAe_4n 4721 TxLVDSe_4n 1R07 TxLVDSe_4n 20
LVDS
A_MDI(0-7) 1506 7500 4722 RES TxLVDSe_4p 19
CONDITIONAL TD1 A17 TxFPGAe_4p TxLVDSe_4p CONNECTOR
19 3522 EF 3521 SC2_CVBS_MON_OUT
ACCESS V2 CVBS_OUT2 TO FULL HD
DISPLAY
H19 TxFPGAo_0n 4703 TxLVDSo_0n 1R08 TxLVDSo_0n 17
21
3529 SC2_Y_CVBS_IN TxFPGAo_0p 4704 16
2x SCART 20 V8 G20 TxLVDSo_0P TxLVDSo_0P
PR_R3
3552 G19 TxFPGAo_1n 4705 TxLVDSo_1n 1R09 TxLVDSo_1n 15
15 SC2_C_IN W4
FS2 4706 14
F20 TxFPGAo_1p TxLVDSo_1p TxLVDSo_1p
8 3550 SC2_STATUS
B04 E19 TxFPGAo_2n 4707 TxLVDSo_2n 1R10 TxLVDSo_2n 13
D20 TxFPGAo_2p 4708 TxLVDSo_2p TxLVDSo_2p 12
EXT2
B20 TxFPGAo_CLKn 4723 TxLVDSo_CLKn 1R11 TxLVDSo_CLKn 10
BO7D HDMI SWITCH B07A YPBPR & SVHS 4724
1615 A20 TxFPGAo_CLKp TxLVDSo_CLKP TxLVDSo_CLKP 9
3617 HD_Pr_IN Y8 4709 1R12
D19 TxFPGAo_3n TxLVDSo_3n TxLVDSo_3n 7
Pr PR_R1
C20 TxFPGAo_3p 4710 TxLVDSo_3p TxLVDSo_3p 6
3618 HD_Y_IN V6
Y Y_G1 F19 TxFPGAo_4n 4711 TxLVDSo_4n 1R13 TxLVDSo_4n 5
E20 TxFPGAo_4P 4712 TxLVDSo_4p RES TxLVDSo_4p 4
1601
3619 HD_Pb_IN W9
7M07 Pb PB_B3
SII9185ACTU
7601
1M01
1601 NC
1 FRONT_CVBS_SVHS_Y_IN Y6
RX2+A 28 + 1 COM Y_G3
3 Y_IN
3 RX2-A 27 - R0X2 NO FRONT_CVBS_SVHS_SEL
S VIDEO 5 B04
4 RX1+A 25 + 4 C_IN V9
2 C
24 - R0X1
1

6
2

RX1-A
7 RX0+A 22 + D2 SIDE I/O B04 MICROPROCESSOR
9 RX0-A 21 - R0X0 1302
10 RXC+A 19 + 1R04 1304
18
19

12 RXC-A 18 - R0XC FRONT_CVBS_IN 2 2 FRONT_Y_CVBS_IN_T


19 HPD_RESET_A VIDEO
16 4 4
N.C.
HDMI
OPTIONAL SWITCH
1M02
D1 SIDE HDMI 7Q03
B07C HDMI MAIN B05C B05B DDR & CPU
1 RX2+B 48 +
SII9181CNU
3 RX2-B 47 - R1X2 1Q01
4 RX1+B 45 + ADC 1 RX2+S 35 HDMI
BUFFER 7N01
44 - R1X1
1

6 ODCK 3 7D01
2

RX1-B RX2-S 34 1Q03 1N01 SII9125CTU


7 RX0+B 42 + 4 RX1+S 33 18 18 HDMI-SIDE_TXC+ ADC K4D261638K
DE 8 58 +
5 HDMI_VCLK W20 DP-CLK
42 - R1X0
1

9 RX0-B 6 20 57 - R1XC
2

RX1-S 32 9 20 HDMI-SIDE_TXC- ODCK


10 HSYNC 7 15 15
HDMI (0-11)
RXC+B 39 + RX0+S 30 6 HDMI-SIDE_TX0+ 62 + HDMI_DE
18

(MAIN) 19 Y20
19

VSYNC DE DP_DE_FLD SDRAM


12 RXC-B 38 - R1XC 9 RX0-S 29 7 17 17 HDMI-SIDE_TX0- 61 - R1X0 HDMI_H 2Mx16x4
20 V20 DP_HS
19 HPD_RESET_B 36 10 RXC+S 28 3 12 12 HDMI-SIDE_TX1+ 66 + HSYNC DIGITAL IN WX_MD(0-31) (0-15)
18

21 HDMI_V Y10 DP_VS


19

12 RXC-S 27 4 14 14 HDMI-SIDE_TX1- 65 - R1X1 VSYNC


9 9 MEMORY
1M03 19 25 1 HDMI-SIDE_TX2+ 70 + 7D02
2 11 11 HDMI-SIDE_TX2- 69 - R1X2 K4D261638K
1 RX2+C 68 + HDMI_Cb(0-9)
HDMI
3 RX2-C 67 - R2X2
CONNECTOR WX_MA (0-11)
4 RX1+C 65 +
HDMI-MUX_TXC+ SDRAM
64 - R2X1 + 10 40 +
1

6
2

RX1-C HDMI_Y(0-9) 2Mx16x4


7
TXC
- 11
HDMI-MUX_TXC- 39 - R0XC
RX0+C 62 + (16-31)
7 HDMI-MUX_TX0+ 44 +
9 RX0-C 61 - R2X0 +
10
TX0
-
8 HDMI-MUX_TX0- 43 - R0X0 HDMI_Cr(0-9)
RXC+C 59 +
18

HDMI-MUX_TX1+
19

12 RXC-C 58 - R2XC + 4 48 +
TX1
- 5
HDMI-MUX_TX1- 47 - R0X1
19 HPD_RESET_C 56
+ 1 HDMI-MUX_TX2+ 70 +
HDMI TX2
- 2 HDMI-MUX_TX2- 69 - R0X2
CONNECTOR H_17371_006.eps
021007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 35

Block Diagram Audio


AUDIO
B02 TUNER IF & DEMODULATOR +5VS B06B AUDIO
7113
1101 TDA9886T/V4
TD1316AF/IHP
1102
DEMODULATOR
5 VIF1 1 VIF1 SUPPLY
MAIN 8 IF-ATV 1 SOUND TRAPS CVBS
IF_OUT1 VIF-PLL
TUNER 4 VIF2 2 VIF2 4.5 to 6.5 Mhz
(HYBRID)
2
RF_AGC 1103
7111 1 5 SIF1 23 SIF1 SINGLE REFERENCE QSS MIXER
SIOMAD 12

6103
INTERCARRIER MIXER AND
10

9
11
12 RF_AGC_IBO AM-DEMODULATOR
B03A 4 SIF2 24 SIF2
14
SIF AGC MAD 1A02
IF_AGC_IBO 13 RF_AGC 14 TAGC
I2C-BUS TRANSCEIVER
1
VIM_IBO
VIP_IBO

7109 TUNER AGC VIF AGC 2 SUB


12

SDA
SCL
DVB_SW 11 SAW_SW WOOFER
B04 B04 3

B03A DVB-DEMODULATOR B03B DVB-COMMON INTERFACE B03C DVB-MOJO B06A AUDIO PROCESSOR
7F01 7K00 7G00 7411
TDA10046AHT STV0700L PNX8314HS/C102 MSP4450K-VK-E8-001 Y

62 MOJO 7A01
PCMCIA SIF 63
ANA-IN1+ TDA8932T 1A01
61 CONTROLLER
27 AUDIO-LS_L 3A03 2 27 5A03 1
COFDM 2 DACM-L
ADC MOJO_I2S_OUT_SD LEFT
CHANNEL 202 20
DA3 26 AUDIO-LS_R 3A11 14
2 SPEAKER
DECODER DACM-R
MOJO_I2S_OUT_SCK 17
CLASS D
TDA_DAT(0-7) TS_DATA(0-7) (TS) (AV) 203 CL3 POWER 3
MOJO_I2S_OUT_WS
SOUND
204 18
WS3 STANDBYn 3A19 AMPLIFIER RIGHT
TS PROCESSOR B04
6
22 5A04 4 SPEAKER
INTERFACE 67 3A26
XTALIN ENGAGE 5
12
B07B I0 - SCART 1 & 2 13 +5V_D
1K00 SUPPLY 7A05÷7A07
1411 68 61
XTALOUT +5V_AUD
18M432 62 DC_PROT
1504 SC1_AUDIO _MUTE_R B04 DC-DETECTION
B06C
1 SC1_AUDIO _OUT_R 80
A_MDO(0-7) 36
SC1-OUT-R 38
2x SCART 2 SC1_AUDIO_IN_R 55 +8V
SC1-IN-R 39
1 3 SC1_AUDIO _OUT_L 37 40
SC1-OUT-L
PCMCIA 68P 6 SC1_AUDIO_IN_L 54
SC1-IN-L
SC1_AUDIO _MUTE_L
B06C
EXT1
A_MDO(0-7) B06C HEADPHONE AMP & MUTING B04 MICRO D2 SIDE I/O
CONDITIONAL
1506 SC2_AUDIO _MUTE_R
ACCESS B06C PROCESSOR
1 SC2_AUDIO _OUT_R 33
SC2-OUT-R
2 SC2_AUDIO_IN_R 53
SC2-IN-R
3 SC2_AUDIO _OUT_L 34
21 SC2-OUT-L 7901
6 SC2_AUDIO_IN_L 52 1304 1R04 1R03
SC2-IN-L HP_AUDIO_OUT_L HP_LOUT 10 10 HEAD_PH_L
SC2_AUDIO _MUTE_L 24 2
B06C DACA-L
EXT2
23 HP_AUDIO_OUT_R HP_ROUT 11 11 HEAD_PH_R 3
DACA-R
B07A YPBPR & SVHS 5 HEADPHONE
1615
SC1_AUDIO _MUTE_R EXT3
COMP_AUDIO_IN_L COMP_AUDIO_IN_L 50 ANTI_PLOP
SC3-IN-L B04
AUDIO SC1_AUDIO _MUTE_L
EXT4 MUTING
L/R IN COMP_AUDIO_IN_R COMP_AUDIO_IN_R 51 SC2_AUDIO _MUTE_R B07B
SC3-IN-R
SC2_AUDIO _MUTE_L

POWER_DOWN
B04
CONTROL
D1 SIDE HDMI 7Q03 D2 SIDE I/O B04A MICROPROCESSOR MUTEn
B04
SII9181CNU
1R20 1R04 1304
HDMI L_FRONT_IN 6 6 SIDE_AUDIO_IN_L 48
1

SC4-IN-L
2

BUFFER AUDIO
RX EXT3
L/R IN R_FRONT_IN 8 8 SIDE_AUDIO_IN_R 49
SC4-IN-R
HDMI-SIDE
18
19

B07D HDMI SWITCH B07C HDMI MAIN


7M07
SII9185ACTU
1M01
7N01 7N07
1
2

SII9125CTU UDA1334ATS
RX-A R0X
1M02 HDMI AUDIO
HDMI
18

(MAIN) DAC
19

(OPTIONAL) SWITCH
1

R1X
2

HDMI-SIDE 86 HDMI_I2S_SCK 1 14 HDMI_AUDIO_IN_L 57


SCK BCK VOUTL SC5-IN-L
RX-B R1X 85 HDNI_I2S_WS 2
1M03 WS WS
81 HDMI_I2S_SD 3 16 HDMI_AUDIO_IN_R 58
18

VOUTR SC5-IN-R
19

SD DATAI
1

R0X
2

TX HDMI-MUX
RX-C R2X 75 8
MUTE MUTE
18
19

HDMI FOR MORE DETAILS SEE H_17371_007.eps


CONNECTOR BLOCK DIAGRAM VIDEO 021007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 36

Block Diagram Control & Clock Signals


CONTROL & CLOCK SIGNALS
B03A DVB-DEMODULATOR B03B DVB-COMMON INTERFACE B02 TUNER IF & DEMODULATOR B03C DVB-MOJO B05B DDR & CPU INTERFACE B05A TRIDENT - WX68 B05E FPGA I/O BANKS B05D FPGA INTERGACE
(ONLY FOR AMBI-LIGHT)

7700
EP2C5F256C7N 1204
1101 7D01 7C01
7F01 TD1316AF/IHP-2 SVP WX68-7568 H2 CLK_OSC1
K4D261638K 7C02 TXFPGAe_CLKn J16
TDA10046AHT/C1 7201
7C04 TXFPGAe_CLKp J15 EPCS4I8 27M
MAIN FPGA
G17 BL_ADJUST F4 nCSO
SDRAM CONTROL B01A TXFPGAo_CLKn
1 TUNER H15 H4 DCLK
2Mx16x4 SCD
7F04 (HYBRID) TXFPGAo_CLKp H16 C3 ASDO
7111 DQ(0-31)
7G00 F1 DATA0
21 COMP_OUT
RF_AGC_IBO 12 PNX8314HS/C102
COFDM 2 6 B07E LVDS CONNECTOR
14 44 1R01
CHANNEL
13 7D02 B17 TXFPGAe_CLKn TxLVDSe_CLKn 25
DECODER 11 DVB_SW B04
K4D261638K
7F03 A17 TXFPGAe_CLKp TxLVDSe_CLKp 24
TO DISPLAY
54 4MHZ_CLK
1
7F02
MOJO WX_MA(0-11) VIDEO F19 TXFPGAo_CLKn TxLVDSo_CLKn 10 (LVDS)

SDRAM PROCESSOR E20 TXFPGAo_CLKp TxLVDSo_CLKp 9


4MHZ_MOJO 158
1 2Mx16x4
25 FE_LOCK 34
B04 MICROPROCESSOR
9 RESET_FE_n 31
7311
44 WX_MCLK 111 AD(0-7)
M30300SAGP
7K00 7113
STV0700L TDA9886T/V4
A(0-7)
77 CTRL_DISP1_up
TDA_DAT(0-7) RF_AGC 14 DEMODULATOR B07D HDMI SWITCH B07C HDMI MAIN 7310 B07E
M29W800DT
7817 76 CTRL_DISP4_up
PCMCIA B07E
37 TDA_CLK 50 SII9025CTU
CONTROLLER 99 LCD_PWR_ON
TDA_VALID 5 HDMI_VCLK W20 B07E
36 48
EPROM AD(0-7) 3 STANDBYn
35 TDA_SYNC 49 B06B B07E
HDMI
7322 STANDBY
MAIN 1Mx8 B01A B06C
34 RESET_STV 32 (GPIO) 512Kx16 A(0-19)
7M07
13
SII9185ACTU 26 CE 48
1K00
12 CPU_RST 10 1301
1 HDMI_Cb(0-7) MICRO 10M
(TS)

1
2
35 TS_DATA(0-7) + 11
A_MDO(0-7) RXxxA R0X PROCESSOR
- 11 28
HDMI +3V3_STBY

18
19
HDMI_Y(0-7) 1312
63 TS_CLK 29 SWITCH
MUX 7312 9 ITV_SPI_CLK 6
62 TS_SYNC 30

1
2
A_MDI(0-7) + BD45275G
61 TS_VALID 28 RXxxB R1X 8 ITV_SPI_DATA_IN 5
- HDMI_Cr(0-7) 5 4
VOUT

18
19
A_MICLK 110 (3V3)
20
2,3 ITV_CONNECTOR A

1
15 MIU_RDY

2
A_MOCLK 118 109 +
57 61 CS 45
7K04 RXxxC R2X
- WR 74 ANTI_PLOP
MIU_ADDR(15-24) 62 44

18
B06C

19
35 63 RD 42
HDMI 75 BL_ON_OFF
27M 84 ALE_EMU 38 B01A
CONNECTOR
86 RST_H 4 72 POWER_DOWN
B06C
7K03 56 INT 18
78 MUTEn
PCMCIA 68P 76 HDMI_HOTPLUG_RESET 89 B06C
BUFFERING
PCMCIA_D(0-7) MIU_DATA(0-7) (MIU) 100 HDMI_RST_RX_BUF 5
88 RST_AUD
CONDITIONAL B06A
ACCESS 35 HDMI_INT_MUX 73

7K01 13 HDMI_RST_MUX 36

BUFFERING
PCMCIA_A(0-7) MIU_ADDR(0-7) MIU_ADDR(0-24) 4 RESET_n 3L11 IBO_RESET 2
73 FRONT_CVBS_SVHS_SEL
B07A
B03D FOR DVB ONLY
4 RSR_H
180 IB0_IRQ 16 B05A
7K01

E KEYBOARD CONTROL SC1_STATUS 91


B07B 7315
BUFFERING SC2_STATUS 90 M24C64-WMN6P
PCMCIA_D(8-14) MIU_ADDR(8-14) B07A
CHANNEL + 1011
CHANNEL - 1012 DC_PROT 71 100 E_PAGE 7 EEPROM
34 B06B
68 MENU 1013
VOLUME - 1014 8Kx8
VOLUME + 1015 1M01
B03D DVB-MOJO MEMORY 1016
7H00 ON / OFF KEYBOARD 2
M29W320ET70N6F

J IR/LED/LIGHT-SENSOR 1M01 DCC_RESET


EPROM 19
B07D
SDRAM MIU_ADDR(0-20) 2
23 SAW_SW
B02
4MX8/2Mx16 21 DVB_SW
1M20 1M20 B02
MIU_DATA(0-15)
7 7 KEYB 93
2/4/8MB 6010 3012
7011
NOR 38 RESET_n +5V_STANDBY
+3V3_STBY
B04A LED1 LED1 6 6 LED1 95
FLASH BLEU
7H02

3L79
K4S281632I-UC60
3L56 4301 SDM
25
6011 3013
SDRAM_CLK 136 7012
38 +5V_STANDBY
LED2 LED2 4 4 LED2 87
SYNC RED
SDRAM
SDRAM_DATA(0-15) (SDRAM) 7010
4x2Mx16 3010
RC 3 3 REMOTE 18
+5V_STANDBY
SDRAM_ADDR(0-14) IR
SENSOR
1 1 LIGHT_SENSOR 2
N.C.
H_17371_008.eps
021007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 37

Test Point Overview SSB (Overview Bottom Side)


A115 E5 F129 D5 F211 A5 F312 C4 F328 C3 F344 B2 F363 C3 F387 B3 F520 D2 F537 E2 F613 E2 FA05 A3 FB10 B9 FB39 A9 FF12 F8 FF29 E7 FG26 C10 FH01 D9 FJ28 B9 FK21 E9 FK37 E9 FK53 E8 FK72 E9 FL36 C5 FM19 F4 FR06 A5 FR22 A4 I123 E6 I142 E5 I212 A7 I344 D4 I380 B4 I415 A3 IB20 A9 IN10 E3
A116 E5 F130 D5 F214 A5 F313 C5 F329 C3 F345 C3 F364 C3 F388 C3 F521 D2 F538 D3 F614 F2 FA06 A3 FB11 A9 FB40 A8 FF13 F7 FF30 E7 FG27 C9 FH02 B10 FK01 F9 FK22 E9 FK38 D9 FK54 D8 FK73 E9 FM01 F4 FN01 E3 FR07 A5 FR23 A7 I124 D5 I143 E5 I213 A7 I351 C3 I384 C3 I416 A3 IB49 A10 IN11 E4
A124 E5 F131 E6 F222 B4 F314 C4 F330 C5 F346 B4 F365 C3 F389 C5 F522 D2 F539 D2 F615 F3 FA07 A1 FB13 A10 FC01 B7 FF14 F8 FG10 B10 FG28 C9 FH03 B9 FK02 F10 FK23 E9 FK39 E9 FK55 E8 FK74 D9 FM02 F4 FN02 E4 FR08 A5 FR24 A5 I125 E5 I144 E5 I232 A4 I352 C4 I387 D5 I417 A3 IB50 B9 IN12 E3
A125 E5 F132 D7 F223 B4 F315 C4 F331 C3 F347 C3 F366 C3 F401 A3 F523 D2 F540 D3 F701 A4 FA08 A1 FB14 B9 FC02 C7 FF16 E7 FG11 B10 FG29 C8 FH04 B10 FK05 D8 FK24 D9 FK40 E9 FK56 E8 FK75 E9 FM03 F4 FN03 E4 FR09 A5 FR25 A5 I126 D5 I145 E6 I311 C4 I353 B4 I388 F7 I418 A3 IB51 A10 IN13 D4
F101 E5 F133 E6 F224 B4 F316 C4 F332 C3 F348 C3 F367 D5 F402 B3 F524 D2 F541 D3 F702 B4 FA09 B3 FB15 A9 FC03 C7 FF17 E8 FG12 B10 FG30 B9 FH05 D10 FK06 F9 FK25 E9 FK41 E8 FK57 E8 FK80 D10 FM05 F4 FN04 E4 FR10 A5 FR26 A5 I127 D5 I146 E7 I312 D4 I354 C3 I389 D4 I419 A3 IB52 A9 IN14 D4
F112 E7 F134 F7 F225 A4 F317 C4 F333 C4 F349 C3 F368 C5 F403 A4 F525 C2 F542 D2 F703 B5 FA10 A1 FB27 A10 FD01 B6 FF18 E7 FG13 D10 FG31 B10 FH06 D9 FK10 E9 FK26 E9 FK42 D9 FK58 D8 FK81 F9 FM06 F5 FP03 B8 FR11 A5 FR27 A5 I128 E5 I147 E6 I318 C3 I357 C4 I390 C5 I420 B3 IC01 C5 IN15 D4
F114 E7 F140 D5 F227 B4 F318 C4 F334 C4 F350 D3 F369 D4 F510 E2 F526 C3 F543 E1 F704 B5 FA11 A1 FB28 A8 FE01 D7 FF19 E8 FG14 C10 FG32 C10 FH07 C8 FK11 E9 FK27 E9 FK43 E9 FK59 E8 FK82 F9 FM07 F4 FP05 A8 FR12 A5 FR28 A4 I129 E5 I148 E5 I326 C4 I359 D3 I391 F7 I421 B3 IC02 B5 IN16 E3
F115 F6 F142 E6 F236 A6 F319 C5 F335 C4 F351 A4 F370 F7 F511 E3 F527 C2 F544 D1 F705 B5 FA12 A3 FB29 A9 FE02 C6 FF20 E7 FG15 C10 FG33 B10 FH08 D10 FK12 D9 FK28 D9 FK44 E8 FK60 E8 FK83 D10 FM08 F4 FP06 B8 FR13 A5 FR29 A4 I130 E4 I149 D5 I330 C4 I362 A5 I392 F7 I422 B3 IC07 C6 IN17 E3
F116 F6 F143 D6 F237 B4 F320 C4 F336 C4 F352 D3 F379 A4 F512 E1 F528 C2 F601 F3 F706 B5 FA13 A2 FB30 A9 FE03 B6 FF21 F7 FG16 D10 FG34 C10 FJ01 D9 FK13 E9 FK29 E9 FK45 E8 FK61 E8 FK84 E9 FM10 F4 FP08 A8 FR14 A5 FR30 A4 I131 E5 I150 E7 I331 C4 I364 C4 I393 B3 I423 B3 ID01 A4 IN18 E3
F117 F6 F145 E7 F302 B4 F321 C5 F337 C4 F353 C3 F380 D5 F513 E2 F529 C1 F602 F2 F733 B5 FA14 A2 FB31 A9 FE04 C7 FF22 E8 FG17 C10 FG35 C10 FJ02 B1 FK14 E9 FK30 E9 FK46 D8 FK62 E10 FL20 A3 FM11 F3 FP35 B9 FR15 A4 FR31 A4 I133 D5 I201 A4 I332 A5 I365 C3 I394 B3 I424 B3 ID05 B4 IN19 E3
F118 E6 F201 A6 F303 E3 F322 C4 F338 C4 F354 C5 F381 C5 F514 E1 F530 C2 F604 F2 F734 A5 FA15 A2 FB32 A9 FE05 C7 FF23 E7 FG18 B10 FG36 C10 FJ22 C9 FK15 E9 FK31 E9 FK47 E8 FK63 E8 FL21 A2 FM12 F3 FP40 A8 FR16 A4 I111 E7 I135 D5 I205 B4 I333 C4 I366 C3 I396 D4 I425 B3 IE04 A6 IN20 E3
F119 E6 F202 A4 F304 A4 F323 A3 F339 C4 F356 D3 F382 A3 F515 E3 F531 D3 F605 F1 F901 B4 FA16 A1 FB33 A9 FE06 C7 FF24 C10 FG19 C10 FG37 B9 FJ23 C9 FK16 D9 FK32 E9 FK48 E8 FK67 E10 FL22 A2 FM13 F3 FR01 A6 FR17 A4 I114 E5 I136 D5 I206 A7 I334 C4 I367 C3 I397 D4 I426 A3 IE05 A6 IN21 E3
F120 E6 F204 A4 F305 D3 F324 C4 F340 C3 F357 A3 F383 A3 F516 D2 F532 D2 F607 F2 F904 B4 FA17 A1 FB34 A8 FE07 B6 FF25 F7 FG20 C10 FG39 C10 FJ24 B1 FK17 E9 FK33 E9 FK49 E8 FK68 E10 FL23 A2 FM15 F3 FR02 A6 FR18 A4 I118 E5 I137 E5 I207 A7 I335 C4 I368 C3 I398 D4 I427 B4 IE06 A6 IP01 B8
F121 E6 F207 A6 F309 C3 F325 C4 F341 C3 F360 A3 F384 A3 F517 D2 F534 E3 F608 F2 FA01 A2 FA18 A1 FB36 A9 FE08 C6 FF26 E7 FG21 C10 FG40 C9 FJ25 B1 FK18 E9 FK34 D9 FK50 D8 FK69 E10 FL24 A2 FM16 E4 FR03 A5 FR19 A4 I120 E5 I138 D5 I209 A5 I338 C4 I373 A3 I412 B4 I428 B4 IE07 A6 IP02 B8
F126 E7 F208 A4 F310 C4 F326 C3 F342 B2 F361 C4 F385 C4 F518 D1 F535 A3 F609 F1 FA02 A1 FA32 A2 FB37 A9 FF10 C8 FF27 E7 FG24 C9 FG41 C9 FJ26 C8 FK19 E9 FK35 E9 FK51 E8 FK70 D10 FL25 A2 FM17 F4 FR04 A5 FR20 A4 I121 E7 I139 D5 I210 A7 I341 D3 I374 A4 I413 B4 I429 A4 IE08 A6 IP03 A9
F128 D5 F209 A5 F311 C4 F327 C4 F343 B2 F362 C4 F386 C5 F519 E2 F536 E2 F612 E2 FA04 A2 FB07 A9 FB38 A10 FF11 E8 FF28 E7 FG25 C9 FH00 B9 FJ27 C9 FK20 D9 FK36 E9 FK52 E8 FK71 E10 FL26 A2 FM18 F4 FR05 A5 FR21 A4 I122 F6 I141 D4 I211 A7 I342 C3 I376 A4 I414 A3 I430 A4 IE09 A6 IP04 A8
I431 B4 IE10 C7 IP08 A8
I432 B4 IE11 C7 IP09 B8
I510 E2 IE12 C6 IP16 B8
I512 E2 IE15 A7 IP17 A8
I517 E1 IF10 F7 IP23 B8
I520 D1 IF11 C9 IP24 B8
I528 C2 IF12 F7 IP25 A8
I530 C2 IF13 F7 IP26 A8
I533 C1 IF14 E7 IP27 B9
I540 E2 IF15 E7 IP28 A8
I541 E2 IF16 E8 IP29 B8
I543 C2 IF17 E7 IP31 A8
I544 C1 IF18 E8 IP32 B8
I545 D2 IF19 F8 IP33 B7
I548 C3 IF20 F8 IP36 B9
I549 C3 IF21 F8 IP37 A8
I550 C3 IF22 F8 IP38 A8
I551 C2 IF23 F8 IP39 B8
I552 C2 IF24 F8 IP40 B8
I553 D3 IF25 F8 IP41 A8
I554 C3 IF26 F8 IP42 B9
I556 C2 IF27 F9 IP43 B8
I557 D2 IF28 F8 IP44 B8
I558 C3 IF29 F8 IP45 B8
I610 E2 IF30 F8 IP55 B8
I611 E1 IF31 E8 IP56 A8
I615 E2 IF32 E7 IP57 A8
I623 E2 IF33 F8 IP58 B8
Part 1 I627
I631
E1
E2
IG13
IG14
C9 IP59
C9 IR01
B8
A6
H_17370_025a.eps I705
I712
A7
A6
IG15
IG16
C10 IR02
C10 IR04
A5
A6
I713 A7 IG17 C10 IR05 A5
I728 A7 IG18 B10 IR06 A6
I911 B4 IG19 C10 IR08 A6
I912 E1 IG20 B10
I913 B2 IG21 B10
I914 B2 IH04 C10
I919 E2 IH06 D10
Part 2 I920
I921
E1
E1
IH07
IJ01
D9
D8
H_17370_025b.eps I922
I930
E1
E2
IJ02
IJ63
D8
C9
I931 E1 IJ64 C9
I932 E1 IJ65 C9
I933 E1 IJ66 C9
IA01 A2 IJ67 F1
IA02 A2 IJ68 F1
IA03 A2 IK68 E9
IA04 A1 IK69 F9
IA05 A3 IK70 F9
IA06 A3 IK72 F9
IA07 A2 IK73 E9

Part 3 Part 4 IA09 B2 IK75 C9


IA10 B3 IK76 F9

H_17370_025c.eps H_17370_025d.eps IA11 B3 IK84 F8


IA12 B2 IK85 F10
IA13 B2 IL20 A3
IA14 A2 IL21 B3
IA15 A2 IL22 A3
IA16 B2 IL23 B3
IA17 A1 IL25 C3
IA18 A2 IL26 C4
IA19 B2 IL30 C5
IA20 A2 IL31 A7
IA21 A2 IL32 C3
IA22 B2 IL33 D3
IA23 A2 IL34 A3
IA24 A2 IL35 A3
IA25 A2 IL37 C5
IA26 B2 IL38 E3
IA27 A1 IL39 F3
IA29 A2 IM01 F5
IA30 A2 IM02 F5
IA31 A2 IM03 F4
IA33 A3 IM04 F4
IA34 A1 IM07 F5
IA35 A2 IM08 F4
IA36 A2 IM09 F3
IA37 A1 IM10 F3
IA38 B2 IM11 F3
IA39 B2 IM12 E3
IA40 A2 IM13 F4
IA41 A3 IM14 E3
IB12 A9 IM15 E4
IB14 B9 IN06 E4
H_17370_025.eps IB15 B9 IN07 E3
3139 123 6273.1 070804 IB19 A9 IN09 E3
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 38

Test Point Overview SSB (Part 1 Bottom Side)

Part 1

H_17370_025a.eps
070804

H_17370_025a.eps
070804
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 39

Test Point Overview SSB (Part 2 Bottom Side)

Part 2

H_17370_025b.eps
070804
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 40

Test Point Overview SSB (Part 3 Bottom Side)

Part 3

H_17370_025c.eps
070804
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 41

Test Point Overview SSB (Part 4 Bottom Side)

Part 4

H_17370_025d.eps
070804
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 42

I2C Overview
I²C
B04 MICROPROCESSOR B03C DVB-MOJO B06A AUDIO PROCESSOR B02 TUNER IF & DEMODULATOR B05A TRIDENT - WX68 B05B DDR & CPU INTERFACE
+3V3_STBY +3V3SW

7302

3L75

3360
3L76

3359
PCA9515ADP
28 3382 IIC_SDA_up 3 6 IIC_SDA
SDA2
27 3L62 IIC_SCL_up IIC_SCL
SCL2 2 7

3152

3151

3C08

3C09
3411

3410
3L54

3355
+3V3SW
ERR
7311 04 5 6 3 2 10 11 H17 H18
7303 7D01
M30300SAGP

3361
K4D261638K

3362
PCA9515ADP
MICRO 7L23 7411 7113 7C01
3 6 IIC_SDA_SIDE SDRAM
PROCESSOR M24C64 MSP4450P TDA9886T/V4 SVP WX68
8Mx16
7310 IIC_SCL_SIDE
MX29LV800CTTI EEPROM 2 7 SOUND DEMODULATOR TRIDENT ERR
10
(NVM) PROCESSOR

3G47

3G46
DATA EPROM 1314 7D02
1Mx8/ 3343 1305
2 9 8 K4D261638K
512kx16 ERR COMPAIR 3 TO 1Q02 ERR ERR ERR
06 SERVICE 09 08 05
ADDR 3345 D1 7G00 SDRAM
3 CONNECTOR 2 SIDE I/O
PNX8314HS 8Mx16
ERR
MOJO 14

B05D FPGA INTERFACE B05E FPGA I/O BANKS


B03D DVB-MOJO MEMORY B03B DVB-COMMON INTERFACE B03A DVB-DEMODULATOR B02 TUNER IF & DEMODULATOR
IIC_SDA_up 3202 MAIN_SDA ERR
12
+5V_SW
IIC_SCL_up 3201 MAIN_SCL
7111

3H12
3H13
74HCT4053D
3G44 I2C_LOCAL_SDA
P2 H1 7
+3V3_FPGA
3G43 1
6 I2C_LOCAL_SCL
7700
3

3K01

3K00
3H09

3H10

3F40

3F44
15
3204

EP2C5F256C7N
3203

1201 +5V_SW
3 3206 AMBI_SDA N2 ERR +5V_SW
FPGA 13 5 6 30 31 8 6 4
1 3205 AMBI_SCL P3

5120

5121
3F42
3F41
3H11
7H03 7K00 7F01
2 user_EEPROM_WP M24C64 STV0700L TDA10046AHT 4 3F46 I2C_TDA_SDA 2
ERR
185 7 5 4
17 3F48 I2C_TDA_SCL
EEPROM PCMCIA COFDM 3 5
8Kx8 CONTROLLER CHANNEL 1101
TO AMBI-LIGHT 7H00 TD1316AF/IHP
MODULE DECODER
M29W320ET70
(ONLY FOR AMBI-LIGHT SET) (ONLY FOR AMBI-LIGHT SET)
11 TUNER
B07D HDMI SWITCH B07C HDMI MAIN DATA NOR ERR ERR ERR DVB_SW
+5VHDMI_C 16 20
3M21

3M20

FLASH 15 B04A
+5VHDMI_B 2/4/8MB
+5VHDMI_A ERR
14 15 ADDR
3M39
3M40

07
3M37
3M38
3M35
3M36

7M07
1M01

3N40

3N39
SII9185CTU 7H02
16 DOC_SDAA 30 K4S281632I
1
2

+3V3_ANA-MUX
HDMI 26 27
15 DOC_SCLB 31 DATA SYNC
SWITCH
18

DRAM
3N35
19

3N36

7N01
1M02 SII9125CTU 4x2Mx16
16 DOC_SDAB 50 ERR ADDR
1
2

21 77 HDMI-MUX_SDA 33
HDMI
15 DOC_SCLB 51 HDMI-MUX_SCL MAIN
78 34
18
19

1M03 B03E DVB-MOJO ANALOG


BACK END
16 DOC_SDAC 70
1

ERR
2

11
15 DOC_SCLC 71
18
19

1J14
HDMI TXD0 4J14
15 2
CONNECTOR
UART
4J15 SERVICE
SIDE HDMI 14 RXD0 3
D1 CONNECTOR
1Q02
IIC_SDA 2 FROM 1305
B04
IIC_SCL 3 SSB
3Q11

3Q10

+3V3_ANA-MUX
+5VHDMI_S
12 13
3N37
3N38
3Q14
3Q15

1Q01 7Q03 1Q03 1N01


DDC_SDAS 37 SII9181CNU 52 HDMI-SIDE_TSDA 2 HDMI-SIDE_TSDA
1

16 17 28
2

15 DDC_SCLS 38 HDMI 53 HDMI-SIDE_TSCL 3 16 HDMI-SIDE_TSCL 29


18

BUFFER
19

ERR
22

B07E LVDS CONNECTOR


+3V3_SW
3352
3351

1R01
3354 BOLT_ON_SDA 3R26 1
33
TXD0
LVDS
3L53 BOLT_ON_SCL 3R25 2 CONNECTOR
RXD0 34
H_17371_009.eps
021007
Block Diagrams, Test Point Overviews, and Waveforms LC7.5E LA 6. 43

Supply Lines Overview


SUPPLY LINES OVERVIEW
B01A DC-DC - 3V3 & VTUN & 5 V_SW B02 TUNER IF & DEMODULATOR B04 MICROPROCESSOR B06A AUDIO PROCESSOR B07D HDMI SWITCH

CN7 +12V_DISP +12V_DISP


+3V3_SW +3V3_SW B01a +12V_DISP +12V_DISP
X406 1B13 +1V8_SW +1V8_SW
B01a +3V3_STBY +3V3_STBY B01a B01b
7 7 +5V_STANDBY B01a
+5V_SW +5V_SW 4401 +AUDIO_POWER_+12V_DISP
B01a +3V3_SW 5M02 +1V8_ANA-MUX
8 8 +12V_DISP +3V3_SW
B03a,B04, 3133 B01a 7410
B06a,B07e 5114 +5VS +8V
+5V_STANDBY +5V_STANDBY IN OUT 5M03 +1V8_DIG-MUX
B01a COM
CN6 3134 5115 +5V_IF 1L20 1M20
X404 3L10 B01a +3V3_SW +3V3_SW
5304 5 J
1 IR/LED +5V_SW +5V_SW
+VTUN +VTUN 5M01 +3V3_ANA-MUX
1A03 B01a B01a
2 B07c
B06B ONLY FOR ANALOG TV 3402 +5V_SW
5401 +5V_D B01a +5V_SW
3 SSB
1B12 +12V_DISP +12V_DISP
+5V_STANDBY B01a B05A TRIDENT - WX68
5402 +5V_AUD 3M13 +5VHDMI-MUX-_TPWR
4 1
B04,B05a +3V3_SW B07c
7B02 B01a +3V3_SW
5 2
+3V3_STBY
6 3
IN OUT
COM
B04,B06c B03A DVB-DEMODULATOR
B01a
+5V_STANDBY +5V_STANDBY B06B AUDIO
1M01
7 4 +1V8_SW +1V8_SW 1A03 HDMI +5VHDMI_A
18
+5V_SW B01b 2 5A09 +AUDIO_POWER CONNECTOR-1
7B12
8 5
B02,B03a,b,d
B03e
+3V3 +3V3 B05A TRIDENT - WX68
CN6 3A01 VDDA 1M02
9 6 B06a,c,B07a,b,d HDMI +5VHDMI_B
A 18
STANDBY +2V5_SW +2V5_SW CONNECTOR-2
B04 5F10 +3V3FE B01b SUPPLY
5A05 VDD
5D03 +2V5_VDDMQ 1M03
HDMI +5VHDMI_C
+5V_SW +5V_SW B05c 18
3D15 DDR_VREF 5A07 4A01 CONNECTOR-3
5B01

B01a +AUDIO_POWER_+12V_DISP
5B06 6B03 +VTUN B05c
RES
SUPPLY 7B13 (34V) B02 1 5A08 -AUDIO_POWER

B07E LVDS CONNECTOR


B03B DVB-COMMON INTERFACE
B05C WX POWER / GROUND
3A02 VSSA
3B67 +3V3 +3V3
B03e
+1V2_SW +1V2_SW 5A06 VSS +12V_DISP +12V_DISP
B01b B01a
ONLY FOR ANALOG TUNER 5K03 +3V3_STV
5E12 +1V2_ADC 7R05 5R02 VDISP
7B01 5K04 +3V3_CORE
3 1 5B03 5B02 +3V3_SW
5E13
B06C HEADPHONE AMP & MUTING 5R03 1R01
STEP B03e,B04, +1V2_PLL 41
DOWN B05a,c,e, 5K05 +3V3_BUF TO
7R07
REG. B07c,d LCD_PWR_ON DISPLAY
5E14 +1V2_CORE +3V3_STBY +3V3_STBY
CONTROL B04
B01a
7 +5V_SW +5V_SW +3V3_SW +3V3_SW
B01a +5V_SW +5V_SW
B01a B01a
7K05 +2V5_VDDMQ +2V5_VDDMQ
PCMCIA_5V B05a
CN4 IN OUT
COM
DDR_VREF DDR_VREF
X405
B05a
1
5K01 PCMCIA_AVCC D1 SIDE HDMI
2
B07A YPBPR & SVHS
5K02 PCMCIA_VPP 1305 1Q02
3 +5V_SW +5V_SW 5 +3V3_SW
4
B05D FPGA INTERFACE
B01a
B04
D2
SSB 5Q01 +3V3_ANA-SIDE
SUPPLY +3V3_FPGA +3V3_FPGA
CN5 AMBI-LIGHT B05e 6 +1V8_SW
X411 MODULES B03C DVB-MOJO (ONLY FOR AMBI-LIGHT SETS)
B07B I/O - SCART 1 & 2 5Q02 +1V8_ANA-SIDE
1
+1V2_SW +1V2_SW
2 5Q03 +1V8_DIG-SIDE
B01b B05E FPGA I/O BANKS +5V_SW +5V_SW
3 B01a
+3V3 +3V3 7 +5V_SW
4 B03e +3V3_SW +3V3_SW
B01a D2
1Q03
5G04 +3V3_VDDP 3Q09 +5VHDMI_SIDE_TPWR 3 1N01
5700 +3V3_FPGA
B07C HDMI MAIN B07C
B05d SSB
+2V5_SW +2V5_SW +5V_SW +5V_SW
B01b
B01a 1Q01
+3V3_SW +3V3_SW 18 +5VHDMI_S
+3V3clean +3V3clean 5701 +2V5out-FPGA
B03e B01a

5702 5N02 +3V3_SWA


+2V5in-FPGA
B01B DC/DC - 1V2 & 2V5 & 1V8
B01b
+1V2_SW +1V2_SW 5N03 +3V3_SWB D2 SIDE I/O
B03D DVB-MOJO MEMORY
5A07 +12V 5703 +1V2_FPGA +3V3_SW +3V3_SW
+3V3 +3V3 5N07 +3V3_SWC D1
B03e +5V_SW +5V_SW
7P06-1
5704 5705 +2V5in-PLL 5N08 +3V3_SWD
7P11 5H02 +3V3_NOR48 D1
7R02
1 5N09 +3V3_SWE +5V_USB
STEP 5P01 +2V5_SW IN OUT
7P06-2 B05a,e
DOWN +5V_SW +5V_SW COM
+1V8_SW +1V8_SW
REG. B01a
+1V8_SW B01b
2 B03a,e
B07c,d 5N01 +1V8_SWA

+12V B03E DVB-MOJO ANALOG BACK END


5N04 +1V8_SWB J IR/LED/LIGHT-SENSOR
7P07-1
+3V3_SW +3V3_SW
5N05 1V8_SWC 1L20 1M20
15 B01a +5V_STANDBY +5V_STANDBY
5P09 B04 5
+1V2_SW
7P07-2 B03c,B05c,e 5J01 +3V3clean 5N06 +1V8_SWD
B03E SSB

16 +3V3_ANA-MUX +3V3_ANA-MUX
7J04 +3V3 B07d
B03a,b,c
+5VHDMI-MUX-_TPWR +5VHDMI-MUX-_TPWR
B07d
7 IJ01
CONTROL 1Q03 1N01
19 +5VHDMI-SIDE-_TPWR
+1V8S_SW +1V8S_SW D1
SIDE I/O
B01b

H_17371_010.eps
021007
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 44

7. Circuit Diagrams and PWB Layouts


SSB: DC / DC 3V3, VTUN, & 5V_SW
1 2 3 4 5 6 7 8 9 1B12 D9
1B13 F9

B01A DC / DC - 3V3 & VTUN & 5V_SW B01A


2B06 E8
2B10 A6
2B12 B2
2B18 D2
2B19 C6
5B01 FB10
2B20 C5
+5V_SW 2B21 F3
A 10u
7B01 A 2B22 F2
2B24 F3
L5973D 8

6
VCC VREF 2B25 B3
Φ IB50 5B05 5B08 FB11
OUT
1
+3V3_SW
2B26 B4

SS24
3 2B27 B7
INH IB51 22u 10u
5

100u 16V
FB 2B63 F8

3B10

2B10
RES
2

10n
SYNC
4
IB12 2B27 2B65 D1
COMP

6B30
2B66 B5
2B12

22u

470u 16V
2B66
GND GND_HS
IB20
2B67 B5
9

2B25

2B26
220p
2B68 F9

22n
7
3B10 A5

2B67
RES
3B12 B5
B IB19
3B12
B 3B15 D4
3B17 F2
1K5 3B18 F2

3B65

4K7

1K0 1%
3B19 B5

3B66

3B19
6K8
3B65 B4
3B66 B4
3B67 C4
3B68 F9
GNDDC 4B04 E8
4B05 E8
+VTUN 4B06 E8
FB14 34V

BZX384-C33
220R
3B67
4B07 E8

220u
5B06
C C

22u 35V
2B19

6B02
4B08 E8

6B03
IB15 4B09 E8
IB14 4B10 E8

BAV99
7B13 4B11 E8

2B20
4B12 F8

100p
1 2N7002
5B01 A2

2
3B15

1K0
7B02 5B05 A5
LD1117DT33C
+5V_STANDBY 5B06 C4
FB13 5B08 A6
3 2
IN OUT +3V3_STBY
6B02 C6
GNDTUN
COM ONLY FOR ANALOG TUNER 6B03 C5
10u 16V
2B65

100n

2B18

D D 6B30 B5

TO / FROM PSU
1

7B01 A3
7B02 D2
7B12 F2
7B13 C5
1B12
FB07 E9
5V2 FB27 FB28
+5V_STANDBY 1 FB10 A2
4B04
4B05 ** FB29
FB30
2
3
FB11 A6
4B06
4B07 ** FB07
4
5
FB13 D2
FB14 C6
FB31 FB15 E2
6

1n0
RES
+5V_SW
RES
4B08
4B09 ** 440054-6
FB27 D9
E RES 4B10
** E FB28 D9

2B06
RES 4B11 FB29 E9

ONLY FOR LCD +5V_STANDBY *


LCD 4B04 / 4B05 / 4B06 / 4B07
FB30 E9
FB31 E9
FB15
PDP 4B08 / 4B09 / 4B10 / 4B11
FB32 F8
FB33 F8
1B13 FB34 F8
4u7 35V

3B68

TO / FROM PSU
2V9
3B17

2B22

BL_ADJUST FB36 100R


6K8

1 FB36 F8
POWER_DOWN RES 4B12 IB52 2V8 FB37 F8
2
BL_ON_OFF FB37
FB32
3 FB38 F8
4 FB39 F8
BACKLIGHT_BOOST FB33 1V6
0V(5V) 5
STANDBY FB38 FB40 F3
F 3B18 IB49 7B12 6
F
1
2
3

STANDBY +5V_STANDBY 7 IB12 A4


0V(5V) 6K8
4 +12V_DISP FB39 FB34
IB14 C4
8
FB40 IB15 C5
440054-8
5
6
7
8

SI4423DY +5V_SW IB19 B4

RES
2B63

2B68

220p
1n0
47u 16V
2B24

2B21

100n

IB20 B5
IB49 F2
IB50 A5
H_17370_001.eps
3139 123 6273.1 (---V) MEASURED IN STANDBY 010804
IB51 A4
IB52 F8

1 2 3 4 5 6 7 8 9
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 45

SSB: DC / DC 1V2, 2V5, & 1V8


1 2 3 4 5 6 7 8 9 2P07 A3 6P05 B8
2P28 A4 6P12 C7

DC/DC - 1V2 & 2V5 & 1V8 2P29 A4 6P13 A4

B01B B01B 2P30 A4


2P31 B2
2P32 B3
6P14 A3
6P15 A2
7P05 A2
2P33 B6 7P06-1 B3
2P78 1u0 2P34 B6 7P06-2 B3
BC817-25W 3P47 68R
7P05 2P35 B4 7P07-1 C4
6P14 IP56 6P13 2P36 B6 7P07-2 C4
BAS316 3P48 68R 2P37 C4 7P08 C8
BAS316
2P38 C4 7P09 B7
A BZX384-C18
3P49 220R 2P07 100n +12V_DISP
A 2P39 D3 7P11 C2
2P40 D1 FP03 C9
IP37
6P15 5P02 2P41 D1 FP05 B9
GNDDC2 IP33 2P42 E3 FP06 B9
IP02 10u
2P43 D7 FP08 B6

2P29

2P30

2P28
22u

22u

22u
2P46 D8 FP35 E4
7P06-1 FP05 2P48 E6 FP40 C1
+2V5_SW 2P49 E1 IP01 B2
3P20 7 8

10R
IP38 2P52 D5 IP02 A5
2 SI4936ADY FP08
GNDDC2V5 GNDDC1V2 5P01 7P09 FP06
+1V8_SW
2P53 D5 IP03 B3
1
IP01
2 3 2P54 D6 IP04 B3

3P37 6K8

BZX384-C6V8
2P59 100u 4V

PHD38N02LT
10u

3P25

10R
B B 2P55 B8 IP08 C1

100u 4V

100u 4V

100u 4V
2P34
2P33

2P72

6P05

2P55

2P56
3n3

22u
2P32 2P56 B9 IP09 D1
2P31

4P01
1u0

1
2P58 C8 IP16 D3
IP03 3n3
2P59 B6 IP17 D3

3P59 470R 1%
IP57 IP23
3P23

2P35
7P06-2 GNDDC2V5 2P61 D7 IP23 B7
10R

1n0

1u0
5 6 GNDDC2V5 GNDDC2V5 NC 2P68 D8 IP24 C8

1
2P36

2P73
100n

3P78 1K0

RES 3P79 1K0

22n
GNDDC2 IP04
4 SI4936ADY 2P72 B7 IP25 C3

2P58
2P73 B8 IP26 C3

RES
3

NC
7P07-1
+2V5_SW 4 2P78 A3 IP27 C3

REF
2P38 1n0
7 8 3P13 C4 IP28 D1
GNDDC2V5 IP42 IP24

NC

1%
2 SI4936ADY +12V_DISP

A
6P12 IP58 3P20 B2 IP29 D1

3P38

3P77
7P08
2R2

1K0
7P11
3P23 B3 IP31 D3
14

TS431AILT

1K0
NCP5422ADR2G
C C

2
BZX384-C6V8 3P25 B4 IP32 E2

10R

3P61
VCC
680R 1%

10R
Φ NC
3P64

FP40
3P26 C3 IP33 A5
4 1 3P32 D3 IP36 C5
3P26

BST H1
GATE IP25 2P37 IP36 5P09 FP03 3P34 D4 IP37 A2
2 4P02
L1 IP26 3P13 +1V2_SW 3P37 B6 IP38 B3
7

2P46 100u 4V

100u 4V
1 IP27 3n3 10u 3P38 C6 IP39 D3
16

3n3
IP08 7P07-2

180R 1%
VFB H2
3P40 D2 IP40 D4

2P52

3P45

3P51

2P61
10 5 6

6K8
1n0

22u
2 GATE
IP09 15 IP16 3P32 2R2 IP40 3P41 D3 IP41 D4
L2

2P43
8 4
1 2P53 3P45 D6 IP42 C4
IP28 5 3

2P68
9
COMP +1
6 SI4936ADY IP59 3P47 A3 IP43 D4
2 -1 IP17 3P34 IP41 3P68 1n0 3P48 A3 IP44 D6
IP29 IP31
IS
3P49 A2 IP45 E1

2P54

100n
13 12 GNDDC1V2
D IP55 ROSC +2
-2
11
3K3 6K8 GNDDC1V2 GNDDC1V2 GNDDC1V2
D 3P50 D6 IP55 D1
100n

100n

GND

2P39

3P74
100n

6K8

IP44
3P51 D7 IP56 A4
3P40

39K

3P52 E6 IP57 B6
3

+2V5_SW
2P40

2P41

3P41 3P53 E7 IP58 C7


3P54 E1 IP59 D6

3P50

1K0
6K8 3P70 IP43 3P69
IP39 3P56 E1
3K3 6K8 FP35 3P59 C8

2K2
100p
GNDDC2 GNDDC2 GNDDC2 GNDDC2 3P61 C5
2P42

3P71
100n

680R 1%
6K8

3P64 C1

3P53
3P68 D4

RES
3P72 6K8 +1V2_SW GNDDC1V2

2P48
3P69 D4

3P52
IP32
E E 3P70 D3
3P71 E3
470R 1%

GNDDC2 GNDDC2 GNDDC2 3P72 E3


3P54

2P49

100p
3P56

10K

3P74 D4
GNDDC2 GNDDC2V5
3P77 C8
3P78 C7
IP45 3P79 C7
4P01 B3
4P02 C4
GNDDC2 GNDDC2 GNDDC2
H_17370_002.eps
5P01 B6
3139 123 6273.1 010804 5P02 A5
5P09 C7

1 2 3 4 5 6 7 8 9
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 46

SSB: Tuner IF & Demodulator


1 2 3 4 5 6 7 8 9 10 11 12 1101 A6 A125 C5
1102 B4 F101 B1

TUNER IF & DEMODULATOR


1103 C4 F112 A6

B02
1104 E4 F114 H10
2112 B11 F115 B7
3111 5K6 RF_AGC 2113 B10 F116 B7
5118 I146 3136 I147 3137 +5V_IF 2115 B6 F117 B7
+12V_DISP
A 33R 47R
7133
47R A 2116 B6
2117 C3
F118 B7
F119 B7
L78M05CDT 2118 C10 F120 B7
I145 3110 2119 C8 F121 B7
*
1101 TUNER 1 IN OUT
3 4V9 8K2
2120 C9 F126 C7
SAW FILTERS 6110 2121 E7 F128 F2

2147

330n

2148
100n
COM I111
F112
4112* F132
14
TUNER
TD1316AF/IHP-2 13
F134 DVB ONLY BAS316
2122 D7 F129 H11

XTAL_OUT
2123 F3 F130 G6

DC_PWR

2
IF_OUT1

IF_OUT2
IF_OUT3
MT MT

RF_AGC
1102 +5V_IF 2149 3115

IF_AGC
A115 15 12 2112 2124 F2 F131 H11
1 5 VIF1 22u 2u2 39K
I O1 2113 2125 F2 F132 A6

SDA
SCL

+5V
4 A116 VIF2

CS
IF_ATV F101 IGND O2 RES 2126 F3 F133 B9
7111 10n

16
3 +VTUN ONLY FOR ANALOG TV 74HCT4053D 2127 F4 F134 A8
B GND
B

10
11
5112 VDD 2128 F7 F140 G8

1
2
3
4
5
6
7
8
9
5117 MDX
OFWK3953M 33R 6 2129 H11 F142 B7
+5V_IF 38M9 G4
5111 RES 2130 H11 F143 B7

2146

2115

2116
3192

RES

RES
390n 4V3 14 13 RF_AGC_IBO

1u0

1u0

1u0
1K0 F133 1 2131 I11 F145 C7
12 WAGC_SW

F116
F115
F117
F118
F119

F120
F121
F142
F143
2 DVB_SW 2132 I11 I111 A12
11 4125
3113
* 4113
I137 4X1
4X2
* IIC_SDA 2133 G6 I114 C4
6K8 2120 2118 2134 H7 I118 C4
I114 2119 2142 15 1
2117 10u 50V 2135 H8 I120 C2

4114
4115

4116

4117
4118
4119
+5V_IF 100n 22u 10n 2 I2C_TDA_SDA
10 2136 G6 I121 D10
10n 2137 H5 I122 D7

1SS356
** * ***

3117

6103
IIC_SCL

2K2
2138 H2 I123 E10
1103 A124 4 3 2139 H5 I124 E3
C 3118 1 5 SIF2 5 I2C_TDA_SCL C

F126
2140 I3 I125 F4

F145
I O1
2K2 I118 4 SIF1 9
ISWI O2 2141 I3 I126 F3
A125 2142 C8 I127 F3
3 GND
VSS VEE
2143 F5 I128 G6

7
SAW_SW I141 3119 I120
7109 OFWK9656M 2144 I3 I129 G6
BC847B 38M9
22K VIP_IBO 2145 I3 I130 H6
3188 1V3 IF_AGC_IBO 2146 B6 I131 H5
18K 2147 A8 I133 I4
I122
* 4120 VIM_IBO
IF_ATV
2148 A9
2149 B11
I135 I4
I136 I4
1V3 4MHZ_CLK 3110 A12 I137 B8
D 5120 120R I121 4121
*+5V_IF D 3111 A11
3113 B3
I138 G7
I139 G7
2122 RES 3120 10R 3115 B12 I141 C1

4123
15p RES 3117 C3 I142 F5
RES 7131 +3V3_SW 3118 C2 I143 H3
3190 BSH111 3119 C1 I144 H3
* 4K7
3120 D8 I145 A9
3123 E3 I146 A8
5121 120R I123 4122
*+5V_IF 3124 E2
3125 G7
I147 A8
I148 I7
2121 RES 3146 10R
3126 H7 I149 H11
15p RES 3127 H6 I150 H11
RES 7132 +3V3_SW
E 3191
4K7
BSH111 E 3133 H10
3134 H10
3135 F7
DEMODULATOR I124 3123 1104
3136 A8
3137 A9
RF_AGC 3124 3140 I8
330R 4M0 +5VS
100R 2123 3146 E8
2125

470n
2126
220n

2127

2143
22p

1n0

RES 2124 I125 3151 I3


F128 1n5 3152 I3
22n

3135
16 I126

3187 I8
19 I127

15R
I142
3188 D2
0V
9

14

15

21

7113 3190 D10


F TDA9886T/V4 F 3191 E10
VPLL

REF

AFC
TOP

VAGC
TAGC

ANALOG 3192 B8
* DIGITAL

2128

10n
4110 Y Y 3193 I5
4111 Y Y 3194 I5
TUNER AGC VIF AGC RC VCO DIGITAL VCO CONTROL AFC DETECTOR 4112 Y Y 3195 I5
4113 Y
4114 Y
4112 B6
VIF2 2V 2 VIF2 4115 Y
4113 B8
SOUND TRAPS F130 4114 C7
CVBS 17 2V1 7114 4116 Y
2V 1 VIF1 VIF-PLL 4.5 to 6.5 Mhz BC847B
VIF1 4117 Y 4115 C7
4118 Y 4116 C7
1V5
SINGLE REFERENCE QSS MIXER AUD 8 I138 * 4124 4119
4120 Y
Y
4117 C7
G SIF2 2V 24 SIF2
INTERCARRIER MIXER AND
AUDIO PROCESSING I128 2133 4121 Y G 4118 C7

150R
3125
AND SWITCHES DEEM 5 4122 Y 4119 C7
SIF1 2V 23 SIF1 AM-DEMODULATOR 4123 Y Y 4120 D8
10n Y
F140 4124 Y 4121 D10
I139 5116
CVBS_RF 4122 E10
MAD
5u6 4123 D7
I129 2136
180R
3126

2134

2135
NARROW-BAND FM-PLL AFD 6 4124 G7

15p

15p
SIF OUTPUT
SUPPLY
AGC PORTS I2 C-BUS TRANSCEIVER DEMODULATOR 470n 4125 B11
RES F114 3133 I149 5114 F129 4126 I5
+5V_SW +5VS 5111 B1
12 SIOMAD

4 FMPLL

10u 5112 B9
7 DGND

1R0
18 AGND

10 SDA
3 OP1

22 OP2

11 SCL

2129 2130 5114 H11


13 NC
20 Vp

H 22u 10n H 5115 H11


5116 G7
2V3

I144
+5VS 2137 I130 3127 5117 B5
2V1

I143 5118 A8
2138 10n +5VS I131 10n
1n0

5K6
10n

I150 5115 5120 D7


22K 2139 3134 F131
+5V_SW +5V_IF 5121 E7
6103 C3
2145

3193 390p 10u


2144
RES

1R0
6110 A11
3151 I148 3140 2131 2132
IIC_SCL_up 100R I133 4126 22u 22u 7109 C2
2140 RES 7111 B10
3194 150R
I135 7134 7113 F2
IIC_SDA_up 3152 100R BC847B 3187
+5VS 7114 G7
I 22K
I
3195

18K

4K7 7131 D11


2141 RES
7132 E11
SIF I136 7133 A8
7134 I6
H_17370_003.eps
3139 123 6273.1 010804
A115 B5
A116 B5
A124 C5
1 2 3 4 5 6 7 8 9 10 11 12
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 47

SSB: DVB-Demodulator
1 2 3 4 5 6 7 8 9 10 11
2F10 B
2F11 B

B03A DVB - DEMODULATOR B03A


2F12 B
2F13 B
2F14 B
2F15 B
2F16 B
A A 2F17 B
2F18 B
2F19 B
2F20 B
2F21 B
2F22 C
5F10
2F23 C
+3V3
+3V3FE +3V3 2F24 C
7F02 +3V3FE 2F25 C
3V2 60R
74AHC1GU04GW

5
FF10 3F10 2F10 2F11 2F26 C
IF10 2 4 4MHz_MOJO 100n 47u 16V
1
1V3 1V6 IF11 +1V8_SW 2F27 D
NC
470R
2F28 D

2F12

100n
1

3
5F11
B 3F11
680K 3F13 220K
3F12
330R
FF11 FF12
+1V8_SW B 2F29 D
60R 2F30 D
2F14 2F15 2F16 2F13 2F19 2F17 2F20 2F18 2F31 D
2F21
100n 100n 100n 100n 100n 100n 100n 100n 2F32 D
47u 16V
+3V3FE 2F33 E
+3V3
3F10 B
3F11 B
7F03 +3V3FE
3V2 3F12 B

2F22

100n
74AHC1GU04GW

5
FF13 3F14 IF12 FF14 3F13 B
4MHZ_CLK 2 1 4
1V3 NC 1V6 330R
3F14 C
2F23 2F25 2F24

3
3F15
3F15 C
3F16 2F26 100n 100n 100n
3F16 C
C RF_AGC_IBO
IF32
680K 3F17 220K 390R 100n
7F01 64 60 59 57 53 50 42 22 5 47 34 19
C 3F17 C
TDA10046AHT/C1 3F18 D
3F19 D

VDD33_ADC

VDD18_PLL_ADC

VDDI18_4

VDDI18_3

VDDI18_2

VDDI18_1

VDDE33_3

VDDE33_2

VDDE33_1
VDDA33_ADC

VDDA18_PLL

VDDA18_OSC
+5V_SW RES 3F20 D
+5V_SW +5V_SW 3F21 D
RESET_FE_n
+5V_SW +5V_SW
3F22 D
2F27
3F18 IF13 IF33
3F23 D

MPEG-TS (SERIAL)
7F04-1 3F19 3F20 3V2 9 20 0V 3F21 10046_TDO 3F24 D
680K
3F22

4K7 4K7 CLR_ TDO


3F23

LM393D 100n 3F25 D


4K7

10K 33R
8 3V3 17 0V STV_TDO
3F24 IF14 IF15 3F25 IF16 TDI 3F26 D
3 4F11 4F12 2V8 1

JTAG
COMP_OUT 1
AGC_TUN 16 2V4 JTAG_TM S 3F27 D
IF18 100K IF17
D 2V2 2
100K RES IF_AGC_IBO
FF16 3F26 1V3 2
AGC_IF
TMS
18 0V
D 3F28 E
100K

3F29 E
3F27

3V3 2F28 2F29 100n JTAG_TCK


100n 1K0 TCK
2F30

100n

4
FF18 FF17 3F30 E
VIP_IBO
FF20
2F31 100n
FF19
1V5 62
VIP COFDM TRST
14 2V4 JTAG_TRST
3F31-1
3F31-2
VIM_IBO 2F32 100n 1V5 61 13
+5V_SW
VIM CHANNEL DECODER ENSERI 3F31-3
3F31-4
FF21

MPEG-TS (SERIAL)
0V7 54 32 3F32-1
7F04-2 3F28 3F29 XIN S_DO
8 2F33
LM393D 100K 100K FF22 55 31
3F32-2
5 10p 0V6
7
XOUT S_OCLK 3F32-3
6 30 3F32-4
+5V_SW FF23 S_DEN
COMP_OUT 2V3 21 3F33 E
E 4
23
GPIO0
S_PSYNC
28
E 3F34-1
GPIO1 27
3F34-2
FE_LOCK FF24 3F30 IF19 25 S_UNCOR
TDA_DAT(0:7) 3F34-3
GPIO2 38 2V2 3F31-4 4 5 33R IF20 3F40 F6
33R 3V2 DO0 TDA_DAT(0)
26 39 2V2 3F31-3 3 6 33R IF21 TDA_DAT(1) 3F41 F3
3F33 GPIO3 DO1 IF22
3F31-2 2 7 33R 3F42 F3

MPEG-TS (PARALLEL )
+3V3FE 41 2V2 TDA_DAT(2)
DO2 IF23
10K 43 2V2 3F31-1 1 8 33R TDA_DAT(3) 3F44 F6
11 DO3
44 2V2 3F32-4 4 5 33R IF24 TDA_DAT(4)
+5V_SW +5V_SW SADDR0 DO4
46 2V2 3F32-3 3 6 33R IF25 3F46 F6
DO5 TDA_DAT(5)
10 48 2V2 3F32-2 2 7 33R IF26 TDA_DAT(6) 3F48 F6
SADDR1 DO6
49 2V2 3F32-1 1 8 33R IF27 TDA_DAT(7) 4F11 D
I2C_LOCAL_SDA DO7
3F40 100R 4V6 8 4F12 D

I2C
3F41 3F42 SDA 37 1V7 3F34-1 1 8 33R IF28 TDA_CLK
5F10 B
F 2K7 2K7 I2C_LOCAL_SCL 3F44 100R
FF25
4V6 6
SCL
OCLK
36 1V3 3F34-2 2 7 33R IF29 TDA_VALID
F 5F11 B
FF26 FF27 4 DEN 7F01 C
I2C_TDA_SDA 3F46 100R 5V
SDA_TUN IF30
35 0V 3F34-3 3 6 33R TDA_SYNC 7F02 B
FF28 FF29 3 PSYNC
I2C_TDA_SCL 3F48 100R 5V 7F03 C
SCL_TUN 33 0V
FF30 UNCOR 7F04-1

VSS_PLL_ADC
12 51 IF31 7F04-2

VSSA_OSC
VSSA_ADC
TEST SACLK FF10 B
FF11 B

VSS7

VSS6

VSS5

VSS4

VSS3

VSS2

VSS1
FF12 B
FF13 C
FF14 C
63 58 56 52 45 40 29 24 15 7
G G FF16 D
FF17 D
FF18 D
FF19 D
FF20 D
H_17370_004.eps FF21 E
3139 123 6273.1 010804 FF22 E
FF23 E

1 2 3 4 5 6 7 8 9 10 11
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 48

SSB: DVB-T: DVB Common Interface


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1K00-A H7 FK46 J7
1K00-B H8 FK47 J9

DVB-COMMON INTERFACE
2K00 H4 FK48 J7

B03B B03B
2K01 I4 FK49 J9
2K02 H15 FK50 J7
2K03 H15 FK51 J9
2K04 J3 FK52 J7
2K05 H15 FK53 J9
2K06 H15 FK54 J7
2K07 F14 FK55 J9
A A 2K08 H15 FK56 J7

PCMCIA_5V
2K09 H15 FK57 J9

+3V3_STV
2K10 H15 FK58 J7
2K11 I15 FK59 J9

A_MOVAL
A_MISTRT
A_MIVAL
A_MICLK

A_MOCLK
A_MOSTRT
2K12 I15 FK60 J7
A_MDO(0:7)

A_|CD1

A_|CD2

A_|RDY|IRQ

A_RESET

PCMCIA_|REG

PCMCIA_|IORD
A_|WAIT

A_|CE1

A_|CE2

VCCEN
PCMCIA_|WE

PCMCIA_|OE

DATDI R
|ADOE

ADLE
PCMCIA_|IOWR
A_MDI(0:7)

|DATOE
2K13 I15 FK61 J9
2K14 F9 FK62 J8

A_MDO(0)
A_MDO(1)
A_MDO(2)

A_MDO(3)
A_MDO(4)
A_MDO(5)

A_MDO(6)
A_MDO(7)
A_MDI(0)
A_MDI(1)

A_MDI(2)
A_MDI(3)
A_MDI(4)

A_MDI(5)
A_MDI(6)
A_MDI(7)
3K19 2K15 K4 FK63 J7
10K
2K16 F8 FK67 H9
3K21 10K 2K17 G8 FK68 H7
3K00 F2 FK69 H9
3K20 10K 3K01 F2 FK70 H7
B B

3 47R

4 47R
1 47R
2 47R
3K02-1 F4 FK71 H9

47R
47R
47R

47R

47R
47R
47R

47R

47R

47R
47R
47R

47R
47R
47R

47R
47R
3K18

47R
10K

4K7
3K02-2 F4 FK72 H7
3K15 10K 3K02-3 F4 FK73 H9
3K03-1 F5 FK74 H7
3K16 10K 3K03-2 F5 FK75 H9

3K34-1 8
7
6

3K34-4 5
3K17 3K03-3 F5 FK80 H7
3K27
3K28
3K29

3K30

3K31
3K32
3K33

2V8 IK85 3K38


3K52

3K40

3K41
3K42
3K43

3K44
3K45
3K46

3K47
3K48
10K

3K39
3K03-4 F5 FK81 H16

3K34-2
3K34-3
3K22 10K 3K04 H9 FK82 I16
3K05-1 F5 FK83 I16

IK68

IK69

IK73

IK76
3K05-2 F5 FK84 F15
3K05-3 F6 IK68 C10

0V
0V

0V
0V
0V

0V

0V

0V
0V

3V2

REG_ 123 3V2


3V2
0V

3V2
3V2

3V2

3V2
3V2
3V2
PCMCIA
0V

0V

0V
0V

3V2

3V2
0V

0V
0V

0V

0V
0V
0V

0V

5V
5V
RDY|IRQA_ 101 5V
RDY|IRQB_ 100 5V

0V
0V

0V
0V

0V
3K05-4 F6 IK69 C10
C C 3K06 K9 IK70 F15
CONTROLLER
MICLKA 110

MIVALB 104
MIVALA 105

MDIA3 103
MDIA4 107

MDIA5 112
MDIA6 114
MDIA7 116

MOCLKA 118
MOSTRTA 127

MOVAL A 125

MICLKB 108

MDIB3 102
MDIB4 106

MDIB5 111
MDIB6 113
MDIB7 115

MOCLKB 117

MOSTRTB 126
124

MDOB0 128

RSTA 120
RSTB 119
122

WAITB_ 121
3K07 K9 IK72 F16
MISTRTA 92

MDIA0 94
MDIA1 96

MDIA2 99

MDOA3 74
MDOA4 76
MDOA5 78
MDOA6 80

MDOA7 84

MISTRTB 91

MDIB0 93

MDIB1 95
MDIB2 98

MDOB3 73
MDOB4 75
MDOB5 77

MDOB6 79
MDOB7 83

CD1A_ 72

CD1B_ 71

WE_ 97
IORD_ 89

IOW_R 90
OE_ 88
CE1A_ 82
CE1B_ 81

CE2A_ 87
CE2B_ 85
VCCEN 70
69

DATDI R 68
ADOE_ 67

ADLE 66
MDOA0 1
MDOA1 3
MDOA2 5

MDOB1 2
MDOB2 4

CD2A_ 7

CD2B_ 6
3K08 K6 IK73 C10

MOVAL B

WAITA_

DATOE_
3K09 F9 IK75 F11
3K10 E14 IK76 C11
3K11 F16 IK84 G8
3K12 F10 IK85 C4
86 3K13 F15
GND-DVB2
9 3K15 B9
GND-PROC 3K16 B9
STV_TDO
10

52 3K17 B9
TDO GND-TSO
D D 3K18 B9

MANAGEMENT
TS INTERFACE
INTERFACE

INTERRUPTS
JTAG_TRS T 39
11 65 38 8

TRST_ GND-TSI 3K19 B9


3K20 B9
IC

UCSG
STV_TDI 37
2

TDI GND-CORE 3K21 B9


JTAG_TMS 3K22 C9
TMS 109 3K23-1 K4
JTAG_TCK VCC-PROC +3V3_STV
TCK 3K23-2 K4
64 3K23-3 K4
VCC-TSO
51 3K23-4 K4
VCC-TSI 3K24-1 K4
36 3K24-2 K4
VCC-CORE +3V3_CORE

3V2 15 WAIT|ACK
3K24-3 K4
CURRENT
62 MOSTRT

E E

3V2 16 WR|STR
49 MISTRT

63 MOCLK

3V2 12 EXTINT

3V2 17 RD|DIR
61 MOVAL

0V 34 RESET

13 EXTCS
3K24-4 K4
50 MICLK

48 MIVAL

53 MDO0
54 MDO1
55 MDO2

56 MDO3
57 MDO4
58 MDO5

59 MDO6

60 MDO7
+3V3_STV
40 MDI0

41 MDI1
42 MDI2
43 MDI3
44 MDI4

45 MDI5
46 MDI6

47 MDI7
STV0700L
7K00

3K25 K4
30 SDA
31 SCL

FK0135 CLK
32 SA0
33 SA1

19 A15
20 A16

3V2 21 A17

3V2 22 A18
3V2 23 A19
3V2 24 A20
3V2 25 A21
26 A22
27 A23
28 A24

29 A25
3V2 14 INT

3V2 18 CS
SWITCH 3K26 K4
3K27 C2

3K10
3V2

2V5

10K
3K28 C3
+5V_SW 7K05 3K29 C3

0V
0V
2V2

2V2
1V3
2V2

2V2

0V

0V
2V2
2V2
2V2
2V2

2V2

2V2

2V2

0V

0V
FK84
1V6

2V2

2V2
2V2
2V2
2V2
1V5

1V3
4V6

ST890C 3K30 C3

FK02
4V6

0V
0V

+3V3_STV 3K31 C3
FK06 7 1 5V
5V

IK75

MIU_ADDR(15)
MIU_ADDR(16)
MIU_ADDR(17)

MIU_ADDR(18)
MIU_ADDR(19)
MIU_ADDR(20)

MIU_ADDR(21)
MIU_ADDR(22)
MIU_ADDR(23)
MIU_ADDR(24)
PCMCIA_5V +5V_SW 3K32 C3
7K04 OUT1 IN1
100R
100R

4
TDA_DAT(0 )
TDA_DAT(1 )

TDA_DAT(2 )
TDA_DAT(3 )
TDA_DAT(4 )

TDA_DAT(5 )
TDA_DAT(6 )
TDA_DAT(7 )

+3V3_STV 3K12 3K33 C3

3K09
2560NK 6 2

10K
OUT2 IN2 3K34-1 C4

3K11
27M

10K
10K IK70 3K34-2 C4
F VDD 5
SET FAULT_
8
F
3K02-3 33R
3K02-2 33R
3K02-1 33R

3K03-1 33R

3K03-2 33R
3K03-3 33R
3K03-4 33R
3K05-1 33R

3K05-2 33R
3K05-3 33R
3K05-4 33R

3K34-3 C4
3K00
3K01

3 0V

GND
OUT 3
1 3K34-4 C4
ON_

2K0 1%
STNDBY IK72

2K14

2K07

3K13
1n0
0V 3K38 C4

10u
TDA_DAT(0:7 )

RESET_STV
GND MIU_ADDR(0:24) 3K39 C4

EMC
2K16
47n

MIU_WEN
4

MIU_RDY
MIU_OEN
3K40 C4

STV_A25
I2C_LOCAL_SDA

STV_INT
I2C_LOCAL_SCL

STV_CS
2 3K41 C5
FK05
3K42 C5
TDA_VALID
TDA_SYNC

TS_DATA(0)
TS_DATA(1)
TS_DATA(2)

TS_DATA(3)
TS_DATA(4)
TS_DATA(5)
TS_DATA(6)

TS_DATA(7)

IK84
TDA_CLK

3K43 C5
TS_VALID
TS_SYNC

EMC
TS_CLK

VCCEN 3K44 C5

2K17
47n
3K45 C5
3K46 C5
G TS_DATA(0:7)
G 3K47 C6
3K48 C6
3K49 H2
3K50 H2
3K51 K6
A_MDO(0:7) 5K01
68p PCMCIA PCMCIA_5V
60R
PCMCIA_AVCC 3K52 C4
5K01 G15

2K05
A_MDO(3)
A_MDO(4)
A_MDO(5)
A_MDO(6)
A_MDO(7)
LATCH +3V3_BUF

100n
A_MDO(0)
A_MDO(1)
A_MDO(2)
5K02 H15
7K01 2K00 CONNECTOR +3V3_STV
5K03 H15
74LVC573ADB 5K04 I15
100n PCMCIA_A(0:14) 1K00-A 1K00-B 5K02

3K04
|ADOE 3K49 33R 0V 1 OE_ 20 5K05 I15

10K
EN PCMCIA_D(0:7) ROW_A ROW_B PCMCIA_5V PCMCIA_VPP
ADLE 3K50 33R 3V2 11 C1VCC 60R 7K00 E1
H H

2K02

2K03
100n

100n
PCMCIA_D(3) GND1 GND3 7K01 H3
MIU_ADDR(7) 0V 2 D0 Q0 19 0V PCMCIA_A(7) PCMCIA_D(4) FK80 D3 1 35 CD1 FK67 A_|CD1
MIU_ADDR(0:24) MIU_ADDR(6) 3 D1 1D
Q1 18 FK68 2 36 FK69 7K02 I3
3V2 3V2 PCMCIA_A(6) PCMCIA_D(5) D4 3 37 D11
MIU_ADDR(5) 3V2 4 D2 Q2 17 3V2 PCMCIA_A(5) PCMCIA_D(6) FK70 D5 D12 FK71 FK81 7K03 K3
4 38 5K03
MIU_ADDR(4) 3V2 5 D3 Q3 16 3V2 PCMCIA_A(4) PCMCIA_D(7) FK72 D6 D13 FK73 7K04 F8
MIU_ADDR(3) 3V2 6 D4 Q4 15 3V2 PCMCIA_A(3) A_|CE1 FK74 D7 5 39 D14 FK75 +3V3 +3V3_STV

10u 16V
6 40 60R 7K05 E16

2K06

2K08

2K09

2K10
100n

100n

100n
MIU_ADDR(2) 0V 7 D5 Q5 14 0V PCMCIA_A(2) PCMCIA_|OE FK10 CE1 D15 FK11 FK01 E9
MIU_ADDR(1) 8 D6 Q6 13 FK12 7 41 FK13
3V2 3V2 PCMCIA_A(1) PCMCIA_A(10) A10 8 42 CE2 A_|CE2
MIU_ADDR(0) 3V2 9 D7 Q7 12 3V2 PCMCIA_A(0) FK14 OE VS1 FK15 A_|VS1 FK02 F10
GND10 PCMCIA_A(11) FK16 A11 9 43 IORD FK17 PCMCIA_|IORD FK05 G9
10 44 5K04 FK82
PCMCIA_A(9) FK18 A9 IOWR FK19 PCMCIA_|IOWR FK06 F15
PCMCIA_A(8) FK20 A8 11 45 A17 FK21 A_MISTRT +3V3 +3V3_CORE

10u 16V
12 46 60R FK10 H7

2K11

2K12
100n
PCMCIA_A(13) FK22 A13 13 A18 FK23 A_MDI(0) FK11 H9
47
I LATCH +3V3_BUF 2K01
PCMCIA_A(14)
PCMCIA_|WE
FK24
FK26
A14
WE|P 14 48 A19
A20
FK25
FK27
A_MDI(1)
A_MDI(2) A_MDI(0:7)
I FK12 H7
7K02 A_|RDY|IRQ FK28 RDY|BSY 15 49 A21 FK29 A_MDI(3) FK13 H9
74LVC573ADB 16 50 5K05 FK83
PCMCIA_AVCC FK30 VCC1 VCC2 PCMCIA_AVCC FK14 I7
0V 1OE_ 20 100n PCMCIA_VPP FK31 VPP1 17 51 VPP2 PCMCIA_VPP +3V3 +3V3_BUF

10u 16V
EN 18 52 60R FK15 I9

2K13
11 A_MIVAL FK32 A16 A22 FK33 A_MDI(4)
C1VCC 19 53 FK16 I7
A_MICLK FK34 A15 A23 FK35 A_MDI(5)
MIU_ADDR(8) 0V 2 D0 Q0 19 0V PCMCIA_A(8) PCMCIA_A(12) FK36 A12 20 54 A24 FK37 FK17 I9
1D 21 55 A_MDI(6)
MIU_ADDR(9) 3V2 3 D1 Q1 18 3V2 PCMCIA_A(9) PCMCIA_A(7) FK38 A7 A25 FK39 A_MDI(7) FK18 I7
MIU_ADDR(10) 4 D2 Q2 17 FK40 22 56 FK41
0V 0V PCMCIA_A(10) PCMCIA_A(6) A6 23 57 VS2 A_MOCLK FK19 I9
MIU_ADDR(11) 0V 5 D3 Q3 16 0V PCMCIA_A(11) PCMCIA_A(5) FK42 A5 RESET FK43 A_RESET FK20 I7
MIU_ADDR(12) 3V2 6 D4 Q4 15 3V2 PCMCIA_A(12) PCMCIA_A(4) FK44 A4 24 58 WAIT FK45 A_|WAIT
MIU_ADDR(13) 25 59 FK21 I9
0V 7 D5 Q5 14 0V PCMCIA_A(13) PCMCIA_A(3) FK46 A3 INPACK FK47 A_|INPACK
MIU_ADDR(14) 3V2 8 D6 Q6 13 3V2 PCMCIA_A(14) PCMCIA_A(2) FK48 A2 26 60 REG FK49 PCMCIA_|REG FK22 I7
9 D7 GND Q7 12 PCMCIA_A(1) FK50 A1 27 61 BVD2|SPKR FK51 A_MOVAL FK23 I9
28 62
J 10 PCMCIA_A(0)
PCMCIA_D(0)
FK52
FK54
A0
D0 29 63
BVD1|STSCHG
D8
FK53
FK55
A_MOSTRT J FK24 I7
FK25 I9
FK56 30 64 FK57
PCMCIA_D(1) D1 31 65 D9 FK26 I7
PCMCIA_D(2) FK58 D2 D10 FK59
BUS TRANSCEIVER +3V3_BUF A_|IOIS16 FK60 WP|IOIS16
GND2
32
33
66
67 CD2
GND4 FK62
FK61 A_|CD2 FK27 I9
FK28 I7
2K04 FK63 34 68
3V2 7069 7172 FK29 I9
20 FK30 I7
3K51

3K06

100n
3K07

0V
3K08

10K
4K7

1 3K25 33R DATDI R


10K

7K03 VCC 3EN1


10K

FK31 I7
74LVC245A 3EN2 FK32 I7
19 0V 3K26 33R |DATOE
G3 FK33 I9
2K15 100p
MIU_DATA(7) 0V 18 2 0V 3K23-4 4 5 33R PCMCIA_D(7) FK34 I7
1
+3V3_STV

MIU_DATA(0:15) 2 FK35 I9
K MIU_DATA(6)
MIU_DATA(5)
0V
0V
17
16
3
4
0V
0V
3K23-3
3K23-2
3
2
6
7
33R
33R
PCMCIA_D(6)
PCMCIA_D(5)
K FK36 I7
+3V3_STV
+3V3_STV

MIU_DATA(4) 0V 15 5 0V 3K23-1 1 8 33R PCMCIA_D(4) FK37 I9


MIU_DATA(3) 0V 14 6 0V 3K24-4 4 5 33R PCMCIA_D(3) FK38 I7
MIU_DATA(2) 0V 13 7 0V 3K24-3 3 6 33R PCMCIA_D(2) FK39 I9
MIU_DATA(1) 0V 12 8 0V 3K24-2 2 7 33R PCMCIA_D(1) FK40 J7
MIU_DATA(0) 0V 11 9 0V 3K24-1 1 8 33R PCMCIA_D(0)
GND FK41 J9
FK42 J7
10 H_17370_005.eps FK43 J9
3139 123 6273.1 010804 FK44 J7
FK45 J9

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 49

SSB: DVB MOJO


1G01-1 A8 IG15 G1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1G01-2 A9 IG16 G1
2G02 G5 IG17 F11
2G03 G6 IG18 F2

DVB-MOJO 3G38 10K 2G04 G6 IG19 G2

B03C RES 3G18

3G19
RES 3G15
10K
10K
10K
MOJO_TRST
MOJO_TDI
10046_TDO
FG10
FG11
FG12
RES
ROW_1
1G01-1
1
3
RES
ROW_2
1G01-2
2
4
FG13
SDRAM_DATA(0:15)

SDRAM_DATA(0) 0V 113
0
7G00-4
PNX8314HS

(SDRAM) 0
153 0V

0V
SDRAM_ADDR(0:14)

SDRAM_ADDR(0)
B03C 2G05 G6
2G06 H6
2G07 H6
2G08 H6
2G09 H6
IG20 G2
IG21 E6

5 6 SDRAM_DATA(1) 2V6 114


1 1
154 SDRAM_ADDR(1) 2G10 H6
3G16 10K FG14 7 8 2G11 H6
MOJO_TMS 2V6 0V
A +3V3
3G17 10K FG15
9
11
10
12
SDRAM_DATA(2) 115
2 2
155 SDRAM_ADDR(2)
A 2G12 F6
2G13 G6
MOJO_TCK SDRAM_DATA(3) 2V6 116 156 0V SDRAM_ADDR(3)
13 14 3 3 2G14 G6
3G20 10K RESET_n FG16 15 16 2V6 117 149 0V 2G15 G6
17 18 SDRAM_DATA(4) 4 4 SDRAM_ADDR(4)
2G16 G6
FG40 19 20 2G17 G6
MIU_WEN 4G09 SDRAM_DATA(5) 2V6 118 5 5
148 0V SDRAM_ADDR(5)
FTSH FTSH 2G18 G6
FG41 0V 2G19 H9
NOR_RYBY RES 4G10 SDRAM_DATA(6) 0V 121 6 6
147 SDRAM_ADDR(6)
SDRAM_ADDR 2G20 I9
SDRAM_DATA(7) 2V3 122 146 0V SDRAM_ADDR(7) 2G21 I9
7 7
FOR DEV. ONLY SDRAM_DATA(8) 2V9 132 145 0V SDRAM_ADDR(8)
2G22 H6
2G23 I6
8 SDRAM_DATA 8
2G24 I6
SDRAM_DATA(9) 2V5 129 144 0V SDRAM_ADDR(9) 2G31 B3
9 9
4G01 JTAG_TCK 2G32 C5
SDRAM_DATA(10) 0V 128 152 0V SDRAM_ADDR(10)
B 4G02 JTAG_TRST
10 10
0V
B 2G33 C5
3G11 E6
SDRAM_DATA(11) 2V5 127 143 SDRAM_ADDR(11)
11 11 3G12 E9
4G03 JTAG_TMS 3G15 A4

MOJO_TRST
0V

MOJO_TCK
2V3 126 142

MOJO_TMS
SDRAM_DATA(12) SDRAM_ADDR(12) 3G16 A4

33R
RESET_n 12 12
2V3 125 150 0V 3G17 A4
RES 100n SDRAM_DATA(13) 13 13 SDRAM_ADDR(13) 3G18 A4
4MHZ_MOJO 2G31
SDRAM_DATA(14) 0V 124 151 0V SDRAM_ADDR(14) 3G19 A4
14 14 3G20 A4
4G31 5G05 33R

3G48
SDRAM_DATA(15) 2V3 123 138 2V1 SDRAM_DQM0 3G28 E14
RES 5G03 1V2clean 15 DQM0 3G29 F14
+1V2_SW 3G30 E14
100MHz 133 3V1 SDRAM_DQM1
FG37 FG18 DQM1
3G31 E14
2G32 4G04 STV_TDI
140 3V SDRAM_CAS 3G33 G2
C RES 4G05
CAS C

1V2
100n 10046_TDO 3G34 G2
141 2V9 SDRAM_RAS 3G35 F2
2G33 RAS

3V3

3V3

3V2
3V3

3V2
0V
CONFIGURABLE 3G36 F14

0V
10u 16V 139 3V SDRAM_WE
WE 3G37 F14
3V3 3G38 A4
SDRAM_CKE

160
157
159
158
4
3

2
1

207
208
137 3G40 I8
CKE
4G05 FOR DEVELOPMENT ONLY 3G41 E14
4G01, 4G02, 4G03,4G04 FOR PRODUCTION 136 1V5 SDRAM_CLK
HSCKB 3G43 H2

DSU_TPC0
AVSS_PLL

AVDD_PLL

XTAL_I N

RESETN

TCK

TRST

TMS

TDO

TDI
XTAL_OUT
3G44 H2
3G46 H2

(JTAG-ETAG-SYS)
3G47 I2
3G48 C6

PNX8314HS
3G51 G13
D 7G00-7
D

7G00-8
PNX8314HS 3G54 G13
3G55 G13
RESET_FE_n 3V3 31 3G56-1 H10

SYS_RESETN
IR_IN 3G56-2 H10
(GPIO)

DSU_CLK

DSU_TPC1
RESET_STV 0V 32 3G56-3 H10

1 PCST1

1 PCST0
IR_OUT
3G56-4 H10
user_EEPROM_WP 4V6 185 17 0V 3G57-1 G10
PWM DTR0
3G57-2 H10

0
VS VCXO_CLOCK
3G57-3 G10
3G57-4 H10

186
187

195
196
197

188
189
194
33 18 0V RX_ZAP FG22 FG21 3G41 10K 3G58-1 G10

5
VPP RX1
3G58-2 H10
7G00-2
IG21 FE_LOCK 3V3 34 19 3V3 TX_ZAP FG23 FG20 3G58-3 G10
+3V3_VDDP C4 TX1
PNX8314HS
E E 3G58-4 H10

3G11
NOR_RYBY 0V 35

10K
C8 BOOT <0:3> FG24 3G30 3G59-1 H10
(TS) 10K 3G59-2 H10
TS_DATA(0) 2V2 20 NOR_WP 0V 45 176 0V PIO19|ITU_OUT0|BOOT0
3G59-3 H10

FG26 3G12
0 SC1_DA 0
30 0V

10K
TS_DATA(1) 2V2 21 TS_SYNC FG25 3G28 10K +3V3
2V2 22 1 TS_SYNC +3V3_VDDP STV_INT 0V 46 177 3V3 PIO20|ITU_OUT1|BOOT1 3G59-4 H10
TS_DATA(2) 2 SC1_CMDVCC 1 3G60 I11
TS_DATA(3) 2V2 23 3 TS_DAT A TS_STROBE
29 1V6 TS_CLK 3G31 10K +3V3
TS_DATA(4) 2V2 24 STV_A25 0V 47 178 3V3 PIO21|ITU_OUT2|BOOT2 3G61 I11
TS_DATA(5) 2V2 25 4
5 TS_VAL
28 1V3 TS_VALID SC1_RST 2
FG28 FG27 3G36 10K RES 3G62 I11
TS_DATA(6) 2V2 26 DSW_n 3V3 48 179 3G63 F10
6 SC1_OFF 3 4G01 B9
TS_DATA(7) 2V2 27 7 ITU_OUT
PIO22|ITU_OUT3|BOOT3 3G29 10K +3V3
+1V2_SW 49 180 4G02 B9
SC1_CCK 4 RES
IG17 3G37 10K 4G03 B9
3G63 10K 0V 12 181 3V2 4G04 C8
CTS0 5
4G05 C8
F 7G00-3
5G06
13 RTS0 6
182 FG29 IBO_IRQ F 4G09 A2
PNX8314HS FG30 4G10 A2
33R 0V 14 183
RXD0 RX0 7 4G31 C3
168 5G07 FG39 1V2_CORE 7G00-1 0V 5G01 G5
CVBS 1V2 PNX8314HS 0V 15 184
Y TXD0 TX0 ITU_CLOCK 5G02 G5
IG14 IG18 5G03 C5
10u 16V
10u 16V
10u 16V

MOJO_I2S_OUT_SD 3G35 22R 202 172 0V 33R 100n 41 42 16


SD_OUT C C_CVBS 2G12 DCD0 PIO <16:27> RES 5G04 I6
IG15 IG19 1V (AV) CVBS RES +3V3 5G05 C4
MOJO_I2S_OUT_SCK 3G34 22R 203 2G13 100n 78 (PWR) 79 3G51
SCK_OUT 5G01 PLL_OUTX0 5G06 F5
IG16 IG20 0V Y
170 10K 5G07 F5
MOJO_I2S_OUT_WS 3G33 22R 204 100MHz 2G14 100n 119 120
2G02
2G17
2G18

VDDC VSSC 7G00-1 F7


1V6
WS_OUT CVBS PIO <0:15> DSW_I2C_enable 3G55
206 163 0V RES 100n 134 135 +3V3 7G00-2 E3
B|Pb 2G15
SPDIF B 5G02 3G54 10K RES 10K 7G00-3 F3
G 205 FSCLK G
165 0V G|Y 100MHz 2G16 100n 191 192
MIU_DATA(0:15) 7G00-5 G 7G00-4 A12
7G00-5 G12
PNX8314HS MIU_ADDR(0:24)
100n 3V3 10
Y 7G00-6 H4
2G03 11
167 0V R|Pr MIU_DATA(0) 3G57-1 8 1 33R 69 0V 75 0V MIU_ADDR(0) 7G00-7 D12
R 3G57-3 6 3 0 0
2G04 100n 43 44 MIU_DATA(1) 33R 67 0V (MIU) 80 3V3 MIU_ADDR(1) 7G00-8 D7
C 8 1 1 1
MIU_DATA(2) 3G58-1 33R 65 0V 81 0V MIU_ADDR(2) FG10 A7
100n 3G58-3 6 3 33R 2 2
2G05 60 61 MIU_DATA(3) 63 0V 82 3V3 MIU_ADDR(3) FG11 A7
8 1 3 3
MIU_DATA(4) 3G56-1 33R 59 0V 83 3V3 MIU_ADDR(4) FG12 A7
100n 6 3 4 4
2G06 76 77 MIU_DATA(5) 3G56-3 33R 57 0V 84 3V3 MIU_ADDR(5) FG13 A9
8 1 5 5
MIU_DATA(6) 3G59-1 33R 55 0V 85 3V3 MIU_ADDR(6) FG14 A7
100n 6 3 6 6
2G07 94 VDDP VSSP 95 MIU_DATA(7) 3G59-3 33R 53 0V 86 0V MIU_ADDR(7) FG15 A7
7 2 7 7
MIU_DATA(8) 3G57-2 33R 68 0V MIU_DAT A 87 0V MIU_ADDR(8) FG16 A7
100n 5 4 8 8
7G00-6 2G08 111 112 MIU_DATA(9) 3G57-4 33R 66 0V 88 3V3 MIU_ADDR(9) FG17 H2
7 2 9 9
PNX8314HS MIU_DATA(10) 3G58-2 33R 64 0V 89 0V
H FG31 2G09 100n 130 131 MIU_DATA(11) 3G58-4 5 4 33R 62 0V 10
11
10
11
90 0V
MIU_ADDR(10)
MIU_ADDR(11) H FG18 C6
FG19 H2
I2C_LOCAL_SCL 3G43 100R FG32 6 SCL0 (I2C-USB-SCO)
MIU_DATA(12) 3G56-2 7 2 33R 58 0V 12 MIU_ADDR 12
91 3V3 MIU_ADDR(12) FG20 E13
4V6 37 2G10 100n 161 162 MIU_DATA(13) 3G56-4 5 4 33R 56 0V 92 0V MIU_ADDR(13)
FG33 3G44 FG21 E13
I2C_LOCAL_SDA 100R FG34 7 SC0_CMDVCC
MIU_DATA(14) 3G59-2 7 2 33R 54 0V 13 13
93 3V3 MIU_ADDR(14)
SDA0
199 2G11 100n 190 193 MIU_DATA(15) 3G59-4 5 4 33R 52 0V 14 14
96 0V FG22 E13
FG17 3G46 4V6 +3V3clean MIU_ADDR(15) FG23 E13
IIC_SCL_SIDE 100R FG35 8 USB_PWR
2G22
15 15
97 0V MIU_ADDR(16)
SCL1
200 175 MIU_RDY 3V3 109
16
98 3V3 FG24 E14
FG19 3G47 3V3 2G19 100n MIU_ADDR(17)
IIC_SDA_SIDE 100R FG36 9 USB_DP 0 MIU_RDY 17
99 3V3 MIU_ADDR(18) FG25 E14
SDA1
201 10u 16V 169 NOR_CS 3V3 74
18
100 3V3 FG26 E9
3V3 USB_DM 2G23 AVDD 1 2G20 100n MIU_CS_N0 19 MIU_ADDR(19)
36 101 3V3 MIU_ADDR(20) FG27 F14
SC0_DA STV_CS 3G60 20 FG28 F13
40 164 2G21 100n 3V3 73 102 3V3 MIU_ADDR(21)
198 SC0_CCK 10u 16V 2 MIU_CS_N1 21
103 0V FG29 F13
USB_OVRCUR 2G24 33R 22 MIU_ADDR(22)
38 171 72 104 0V MIU_ADDR(23) FG30 F13
SC0_RST 1 MIU_CS_N2 23
39 105 0V FG31 H2
I SC0_OFF 10u 16V IDUMP
2
166 71 MIU_CS_N3
24 MIU_ADDR(24)
I FG32 H3
5G04 107 FG33 H2
174 IG13 MIU_OEN 3G61 3V3 70 MIU_MASK1
+3V3 MIU_OE_N FG34 H3
110
1K2 1%

60R +3V3_VDDP 1V2 MIU_WEN 33R MIU_LBA FG35 H3


3G40

173 3V3 108 MIU_WEN FG36 I3


3G62 MIU_BAA
50 FG37 C5
33R 106 FG39 F6
MIU_MASK0
MIU_CLK
51 FG40 A7
FG41 A7
H_17370_006.eps IG13 I8
3139 123 6273.1 010804 IG14 F1

1 2 3 4 5 6 7 8 9 10 11 12 13 14
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 50

SSB: DVB MOJO Memory


1 2 3 4 5 6 7 8
2H03 C2
2H04 A7

B03D DVB-MOJO MEMORY B03D 2H06 B1


2H07 A7
MIU_ADDR(0:24) 2H08 C2
2H09 C2
2H10 C2
FH08 +3V3_NOR48
+3V3 5H02 2H11 C3
100MHz 2H12 C2

10u 16V
2H07

2H04

100n
2H13 C2
2H14 D6
A 7H00 A 2H15 D6
M29W320ET70N 37 3H00 C5
MIU_DATA(0:15) 3H05 C7
3H09 E7
MIU_ADDR(1) 3V2 25 29 0V MIU_DATA(0) 3H10 E7
0 EPROM 0 3H11 E7
MIU_ADDR(2) 0V 24 31 0V MIU_DATA(1)
1 4Mx8/2Mx16 1
MIU_ADDR(3) 3V2 23
2 2
33 0V MIU_DATA(2) 3H12 E8
MIU_ADDR(4) 3V2 22 35 0V MIU_DATA(3) 3H13 E8
5H01 3 3
+3V3 MIU_ADDR(5) 3V2 21 38 0V MIU_DATA(4)
4 4
0V
3H14 D5
100MHz MIU_ADDR(6) 3V2 20 40 MIU_DATA(5)
5 5 4H00 C5
MIU_ADDR(7) 0V 19 42 0V MIU_DATA(6)
10u 16V

6 6 4H01 C5
2H06

MIU_ADDR(8) 0V 18 44 0V MIU_DATA(7)
7 7
B MIU_ADDR(9)
MIU_ADDR(10)
3V2
0V
8
7
8
9
D
8
9
30
32
0V
0V
MIU_DATA(8)
MIU_DATA(9) B 4H02 C5
4H03 C5
MIU_ADDR(11) 0V 6 0 34 0V MIU_DATA(10)
3V2 10 A 10 4H04 C5
MIU_ADDR(12) 5 32M-1 36 0V MIU_DATA(11)
11 11 4H05 C7
MIU_ADDR(13) 0V 4 39 0V MIU_DATA(12)
FH07 12 12 4H12 E7
MIU_ADDR(14) 3V2 3
13 2/4/8MB 13
41 0V MIU_DATA(13)
MIU_ADDR(15) 0V 2
14 14
43 0V MIU_DATA(14) 4H15 C7
MIU_ADDR(16) 0V 1
15
NOR 15
45 0V MIU_DATA(15) 5H01 B1
MIU_ADDR(17) 3V2 48
5H02 A6
100n

100n

100n

100n

100n

100n
FLASH
100n

16 A-1
MIU_ADDR(18) 0V 17
3V2 16
17 5H03 D5
MIU_ADDR(19)
4H02 18 7H00 A6
MIU_ADDR(20) 3V2 9 IH07
19
2H10

2H08
2H09

2H13

2H03

2H12

2H11

3V2 10 13 0V 4H05 MIU_ADDR(22) 7H02 C1


20 NC
MIU_ADDR(22) 4H03 7H03 E5
C MIU_ADDR(21)
+3V3_NOR48 3H00
RES
3K3
4H04
4H00
3V2
3V2
15
12
RB
RP VPP/WP_
14
IH06 3H05 +3V3_NOR48 C FH00 E7
SDRAM_ADDR(0:14)
IH04 3V2 11 FH01 D5
WE 3V2 10K
MIU_ADDR(20) 4H01 3V2 28 FH02 E7
OE
SDRAM_ADDR(12) RES 3V2 26
CE
FH03 D6
4H15 NOR_WP
NOR_RYBY 3V2 47 FH04 E7
7H02 BYTE
K4S281632I-UC60T
RES FH05 D5
1 14 27 3 9 43 49 RESET_n 27 46
FH06 D5
VDD VDDQ
SDRAM_ADDR(0) 0V 23 36 0V FH07 B2
24 0 MIU_WEN FH01
SDRAM_ADDR(1) 0V NC 40 SDRAM_DATA(0:15) FH08 A7
25 1 MIU_OEN
SDRAM_ADDR(2) 0V FH05 IH04 C5
26 2 2 1V3
SDRAM_ADDR(3) 0V SDRAM_DATA(0)
29 3 0 4 1V3 NOR_CS FH06 IH06 C7
SDRAM_ADDR(4) 0V SDRAM_DATA(1)
4 Φ 1 IH07 C7
D SDRAM_ADDR(5)
SDRAM_ADDR(6)
0V
0V
30
31 5 A
6
SYNC
2
3
5 1V
7 1V3
SDRAM_DATA(2)
SDRAM_DATA(3) D
SDRAM_ADDR(7) 0V 32 DRAM 8 1V3 SDRAM_DATA(4) +3V3_NOR48
33 7 4 10 1V2 +5V_SW
SDRAM_ADDR(8) 0V SDRAM_DATA(5)
34 8 4x2Mx16 5 11 0V
SDRAM_ADDR(9) 0V SDRAM_DATA(6)
9 6 3H14 5H03 FH03 2H14 2H15
SDRAM_ADDR(10) 0V 22 13 1V4 SDRAM_DATA(7)
10 D 7 +5V_SW
35 42 1V3

3K3
3K3
SDRAM_ADDR(11) 0V SDRAM_DATA(8) 100MHz
11 8 44 1V3 1R0 220n 220n
SDRAM_DATA(9) 7H03
9 45 1V

3H11
SDRAM_DATA(10)

10K
10 M24C64-WMN6 5V
47 1V4 SDRAM_DATA(11)

8
11
SDRAM_ADDR(13) 0V 20 48 1V4 SDRAM_DATA(12) I2C ADDRESS:A0
Φ

3H12
3H13
21 0 12 50 1V3
SDRAM_ADDR(14) 0V BA SDRAM_DATA(13)
1 13 51 0V7 (8Kx8) 7 user_EEPROM_WP
SDRAM_DATA(14) 4V6 4H12
38 14 53 1V2 WC
SDRAM_CLK 1V5 SDRAM_DATA(15) FH00
CLK 15 EEPROM 3H10
6
E SDRAM_CKE 3V3 37
19 CKE
CS
1
2 0
1 ADR
SCL
5
4V6
FH04 100R
I2C_LOCAL_SCL
E
SDRAM_RAS 3V 18 3 4V6 I2C_LOCAL_SDA
RAS +5V_SW 2 SDA
SDRAM_CAS 3V 17 15 3V3 SDRAM_DQM0
CAS L 5V FH02 3H09
SDRAM_WE 3V 16 DQM 39 2V2 SDRAM_DQM1 4
WE U 100R
VSS VSSQ

28 41 54 6 12 46 52

H_17370_007.eps
3139 123 6273.1 010804

1 2 3 4 5 6 7 8
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 51

SSB: DVB MOJO Analog Back End


1 2 3 4 5 6 7 8 9
1001 D7
1002 D7

B03E DVB-MOJO ANALOG BACK END B03E 1J14 D6


2J01 B7
2J02 B7
2J04 B8
2J05 C8
2J06 C9
2J60 A3
A RES
A 2J62 B3
2J63 B2
2J60 2J64 C3
5J01 FJ28 2J66 C2
22p +3V3_SW +3V3clean
60R
2J67 C3
5J52 FJ22
IBO_CVBS_IN 2J68 D2

10u 16V

100n
2J01

2J02
PESD5V0S1BA
3u3 +3V3_SW
2J69 D2
2J70 D3

180R
3J59

180p
2J63

2J62

3J60

6J60
RES
47R
68p
2J71 E2
2J72 E2
2J73 E2

22u 16V
3J01

2J04
22K
3J01 B8
B IJ01 3J02
7J04 B 3J02 B8
3J03 B6
12K IJ02 1V2 SI2301BDS
3J03 1V8 3J14 D8
+1V8_SW 7J05 FJ01
C_CVBS IJ63 PDTC114ET +3V3 3J15 D8
100R
3J59 B2

BAS316
6J03
3J60 B3
3J61 C2
RES 3J62 C3

100u 16V
2J64

100n
EMC
2J05

2J06
3J63 D2
22p 3J64 D3
3J65 E2
5J53 FJ23 3J66 E3
G|Y IBO_G_IN
C IJ64
C 4J14 C8

PESD5V0S1BA
3u3
B|Pb IJ65 4J15 D8
3J62

6J61
RES
47R

5J01 A6
180R
3J61

180p

R|Pr
2J66

2J67

IJ66
68p

5J52 A3
5J53 C3
UART CONNECTOR (SERVICE) 4J14 5J54 D2
1J14 IJ67 5J55 E2
MSJ-035-29D PPO (PHT) FJ24 RES 3J14 100R TXD0
RES 6J03 B7
2 IJ68
2J68 6J14 D7
FJ25 RES 3J15 100R RXD0
3 6J15 D8
22p 1
5J54
4J15 6J60 B3
FJ26

1001

1002
IBO_B_IN 6J61 C3
D D
PESD5V0S1BA

3u3 FJ02 6J62 D3


6J63 E3
180R

2
3J63

180p
2J69

2J70

3J64

6J62
RES

PESD3V3L1BA

PESD3V3L1BA
47R
68p

7J04 B9
7J05 B7

6J14

6J15
FJ01 B9

ESD Protection
FJ02 D6

1
RES FJ22 A4
2J71 FJ23 C4
FJ24 D8
22p
5J55 FJ27 FJ25 D8
IBO_R_IN FJ26 D4
PESD5V0S1BA

E 3u3 E FJ27 E4
FJ28 A8
180R
3J65

180p
2J72

2J73

3J66

6J63
RES
47R
68p

IJ01 B7
IJ02 B8
IJ63 B1
IJ64 C1
IJ65 C1
IJ66 C1
H_17370_008.eps
3139 123 6273.1 010804 IJ67 D8
IJ68 D8

1 2 3 4 5 6 7 8 9
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 52

SSB: Micro Processor


1301 B3 3L15 F1 F353 I5
1 2 3 4 5 6 7 8 9 10 11 12 13 1302 I3 3L16 F7 F354 I5
1303 I3 3L17 D3 F356 E8
1304 A9 3L20 A11 F357 H8

MICROPROCESSOR FRONT_Y_CVBS_IN
4L20 1305 A9 3L21 A11 F360 I9

B04
FRONT_Y_CVBS_IN_T

* *
RES 3L20 100R

+3V3_STBY
1306 H8 3L22 B11 F361 D3
TO / FROM SIDE IO RES 4L21
RES 3L21 100R FRONT_C_IN_T
1307 I8 3L23 B11 F362 B5
1308 I8 3L24 A11 F363 G10
1309 I9 3L25 A11 F364 G10

2L22 10p
10p
10p
10p
1305 1304

+3V3_STBY
+3V3_STBY
1310 I9 3L26 D5 F365 G10
1-440054-0
+3V3_STBY +3V3_SW 1 1311 H7 3L27 B12 F366 E10
HDMI_INT_SIDE FL20

RES
RES

RES

RES
*2L21

*2L23
* * 2L20
CPU_RST 1 2 1312 I5 3L28 D2 F367 E10
IIC_SCL_SIDE
A 2 3
A 1313 I4 3L53 G7 F368 B10

10K
IIC_SDA_SIDE FL21 FRONT_C_IN

*
IL21

1K0
3 4 1314 H3 3L54 G11 F369 E10

5301
+3V3_STBY

+3V3_STBY

60R
HDMI_RST_RX_BUF 4 5 4L24 IL20
L_FRONT_IN 220n SIDE_AUDIO_IN_L 1L20 H8 3L55 F5 F370 G6

BAS316
+3V3_SW FL22 RES 3L24 33R 2L24

10K
2315 5 6 2310 A4 3L56 F5 F379 D2
100n

RES
+1V8_SW 6 7 4L25 IL22
+5V_SW FL23 R_FRONT_IN RES 3L25 33R 2L25 220n SIDE_AUDIO_IN_R 2311 C10 3L57 D3 F380 B2
7 8 3L58 F5 F381 B3

2312

100n

2313

100n
2310

100n
7312 DDC_RESET FL24 IL23 2312 A4
8 9

3330

1n0

1n0

1n0

1n0
3310
BD45275G FL25 2313 A4 3L59 C5 F382 H10
5

6301 9 10

3319
VDD FL26 2314 B3 3L60 G5 F383 I10
NC 10 11 2315 A1 3L61 G5 F384 I10
Φ

*2L31
*2L30

*2L33
*2L32
RES
RES

RES

RES
F330 1 4 7311 1-440054-1 2316 B3 3L62 F7 F385 D3
ER VOUT

14
60

97

100K
M30300SAGP F386 C5

3L96
3V3 2317 2317 B1 3L63 D2
100n 2314 15p 1V5 HEAD_PH_L 3L22 33R HP_LOUT 2318 C3 3L67 E5 F387 H10

10K
2 3 VCC
Φ AVCC
13
3325
10K

SUB GND 2319 E9 3L71 G2 F388 H10


IN

1301
10M
XTA L
HEAD_PH_R 3L23 33R HP_ROUT 2320 F10 3L72 F2 F389 G3
11 HP_DETECT

100p

100p
2316 OUT 2323 F1 3L73 H2 FL20 A9

2L29 22n

2L28 22n
15p 1V5 3L75 E7 FL21 A9
2324 F7
B 3314 10K I312 6 95 I311 3313 330R F323 LED1 B 2327 H9 3L76 E7 FL22 A9

3316
BYTE 0 3315 100R
93 FL36 KEYB

RES
* 2L27
2L26
2329 I10 3L79 F5 FL23 A9

RES

RES
RES
CNVSS 3318 100R I387 7 1 3317 330R
92 IL37 HP_DETECT_T

*
CNVSS 2 3320 100R FOR EMC 2330 I10 3L86 D1 FL24 A9
F380 RES 3321 1K0 91 SC1_STATUS 4L26
3 3322 100R HP_DETECT_T 2331 I10 3L93 F7 FL25 A9

*
10 90 SC2_STATUS RES 3L27

*
RESET
AN
4 100R 2332 I12 3L94 H2 FL26 A9
3323 100R 89 3303 100R IL38 HDMI_HOTPLUG_RESET
F381 5 5302 F368 2333 I11 3L95 H2 FL36 B6

2L34 1n0

1n0
96 88 F362 3L05 100R F302 RST_AUD
+3V3_STBY VREF 6 3324 10K +3V3_STBY 2335 I11 3L96 B6 I311 B5
7
87 LED2 60R 2336 I11 4301 F6 I312 B3

2318

100n
AD(0) 86 3357 100R HDMI_RST_RX_BUF 2311

*2L35
RES

RES
0 2337 I12 4302 H11 I318 G9
AD(1) 85 1 P10<0:7> RES 3356 10K
+3V3_SW 10u
AD(2) 84 3329 100R IL30 RST_H 2338 E2 4303 H12 I326 C5

*
2 2339 I12 4304 H12 I330 D1
AD(3) 83 3 KI<0:3>
AD(4) 82 DATA 3396 1K0 +5V_STANDBY 2340 I11 4305 H12 I331 D3
4
AD(0:7) AD(5) 81 7322 STANDBY 7310 2341 E12 4306 G13 I332 D1
C

37
AD(6)
AD(7)
80
79
5
6
TBIN<0:4>
5 F386
PDTC114ET STANDBYn M29W800DT-70N6 AD(0:7) C 2L20 A11
2L21 A11
4307 G13
4309 I12
I333 D3
I334 D1
7 CLK3
4 I326 A(1:7) EPROM
SIN3 2L22 A12 4310 I11 I335 D3
3 I357 3L59 100R F304 A(1) F310 25 1Mx8/512Kx16 2L23 A12 4313 H6 I338 D3
P0<0:7> SOUT3 3L11 100R 0
2 IBO_RESET I390 RESET_n A(2) F311 24 29 F312 AD(0) 2L24 A12 4314 H11 I341 D5
DA0 1 0
3300 1K2 1 I389 A(3) F313 23 31 F314 AD(1) 2L25 A12 4315 H11 I342 D5
AN0<0:7> DA1 FOR DVB ONLY 2 1
CLK4
100 E_PAGE A(4) F315 22 3 2
33 F316 AD(2) 2L26 B11 4316 G9 I344 D5
MUTEn I353 3L57 100R I352 78 A(5) F317 21 35 F318 AD(3) 2L27 B11 4323 F1 I351 F5
8 ANEX0 4 3
CTRL_DISP1_up I330 3338 100R I331 77 99 I364 3380 100R I362 LCD_PWR_ON F319 20 38 F320
CTRL_DISP4_up I332 3339 100R I333 76 9 SOUT4 A(8:19) A(6) F321 19 5 4
40 F322
AD(4) 2L28 B12 4326 D1 I352 C3
10 ANEX1 A(7) 6 5 AD(5) 2L29 B12 4327 D1 I353 C1
BL_ON_OFF I334 3340 100R I335 75 98 RES 3387 100R IL39 CEC_D A(8) F324 18 42 F325 AD(6)
I338 74 11 SIN4 7 6 2L30 B11 4328 D1 I354 F5
ANTI_PLOP 3341 100R DAT A A(9) F326 8 44 F327 AD(7)
4326 4K7 3L28 F385 73 12 ADTRG
7 8 7
30 2L31 B11 4L03 H5 I357 C5
HDMI_INT_MUX A(10) F328 0 D
4327 RES +3V3_STBY 100R 72 13
RES 3L26 100R I388 WAGC_SW F329 6 9 A 8
32 2L32 B12 4L20 A11 I359 G5
HDMI_INT_MAIN A(11) 8M-1
D HDMI_INT_SIDE
POWER_DOWN
4328 RES 100R 3L63 HDMI_INT 3L17 F361 71 14
15
P9<0:7>
20 I341
A(12)
A(13)
F331
F332
5
4
10
11
9
10
34
36
D 2L33 B12
2L34 C11
4L21 A11
4L24 A11
I362 D6
I364 D5
TA4OUT I342 IL31 12 11 2L35 C12 4L25 A11 I365 G3
F379 3346 100R DDC_RESET A(14) F333 3 39
BZX384-C3V3
RES 6317

+3V3_STBY P1<0:7> U 13 12 3300 C2 4L26 B12 I366 E6


19 REMOTE A(15) F334 2 41
3L86 TA4IN
1
14 13
43 3301 F6 5301 A4 I367 E6
A(0:7) INT<3:5> U 3347 10K +3V3_STBY A(16) F335 15 14
18 3348 47R INT A(17) F336 48 45 F337 A(0) 3303 B5 5302 B10 I368 G3
22K 0 16 15
3393

70 17 I344 17 3306 F7 5304 I11 I373 I10


15K

A(0) 0 INT 1
3349 10K +3V3_STBY A(18) F338 17 A-1
A(1) 69 16 IBO_IRQ A(19) F339 16 3307 F7 5306 E12 I374 I11
+12V_DISP 1 2 3350 10K 18
A(2) 68 2 ZP +3V3_STBY RES 3309 I6 6301 A1 I376 I12
I380 A(3) 67 15 I396 3397 47K 3326 100R F340 15 3310 A6 6306 I2 I380 E1
3 NMI +3V3_STBY CPU_RST RB
I393 6318 A(4) 66 ADDR 9 I397 3L67 100R ITV_SPI_CLK F341 12 9 3311 I6 6307 I3 I384 H3
7317 0V8 3L04 65 4 XCOUT
8 I398 100R ITV_SPI_DATA_I N 100R F366 11 RP
10
A(5) 5 XCIN 3388 3336 WE 3313 B5 6308 H8 I387 B3
BC847BW A(6) 64 I367 3382 100R F367 28 NC 13 3314 B3 6309 I8 I388 D6
1K5 PDZ8.2-B 6 F356 OE
2338

220n
3395

7308 63 IIC_SDA_up F369 26 14


1K5

A(7) I389 C5
RES 2319 100n +3V3_SW 3315 B5 6310 I8
E BC847BW
+3V3_STBY
7
D<0:7>
P8<0:7>
+3V3_STBY
3L76 2K2
WR
47 CE
BYTE E 3316 B2 6311 I9 I390 C6
3317 B5 6312 I9 I391 H6
28 5306 30R

27

46
RD +3V3_SW

4K7

4K7
D<0:7> TA0OUT 3318 B3 6317 D1 I392 H6
TXD2 CE 3319 A2 6318 E2 I393 E2
3399

A<0:7>
10K

DC_PROT 3398 I394 SDA2 7302 3320 B5 7302 E12 I394 E2


3L75 2K2 2341

8
AN2<0:7> 27 I366
TB5IN +3V3_STBY 100n PCA9515A 3321 B3 7303 G12 I396 E5
100K A(8:19) P2<0:7> TA0IN IIC_SCL_up 3322 B5 7308 E1 I397 E5
0V6 3L62 100R VCC

3360

3359
RES RXD2 RES
4323 A(8) 61 4301 3323 B3 7310 C10 I398 E5
59
8 SCL2
26 NC F305 SDM F350 IIC_SDA_up IIC_SDA 3324 B5 7311 B3 IL20 A12
7L10 A(9) 9 TA1OUT
3 SDA0 SDA1 6
7323-2 +3V3_STBY BC847BW A(10) 58 3L79 10K +3V3_STBY 3325 B1 7312 A1 IL21 A13
10 V 3326 E10 7314 F6 IL22 A12
NL27WZ08USG A(11) 57
11 CLK2
25I351 3L56 100R
3L72

56 FRONT_CVBS_SVHS_SEL 3329 C5 7317 E1 IL23 A13


47K

A(12)
8

12 ADDR V
TA1IN IIC_SCL_up IIC_SCL
IL25 5 A(13) 55 2 SCL0 SCL1 7 3330 A6 7322 C6 IL25 F1
3L15
F CE 3
6
A(14)
A(15)
54
53
13
14
V
CTS2
RES 3301 100R
SAW_SW
FPGA_BL_BOOST
+3V3_STBY +3V3_STBY +3V3_STBY
5 EN 1
F 3336 E9
3338 D3
7323-1 G1
7323-2 F1
IL26 G2
IL30 C6
330R 15 RTS2 NC NC+3V3_SW
24 IL32 3L16 1K0 +3V3_SW NC GND 3339 D3 7L10 F3 IL31 D6
TA2OUT

2320

100n
3 RES 3L93 4K7 IL32 F7
4

I354 3340 D3 7L23 G10

10K
P3<0:7> W
23 3L58 100R 1 +5V_SW
3341 D3 F302 B6 IL33 F6

3K3

3K3
4
TA2IN

3306

3353
52 2324 1u0

1K0

10K
A(16) 16 W 7314 3343 I2 F303 G6 IL34 I11
2323

100n

A(17) 51 22 3L55 10K IL33 BC847BW 2 RES 3307


8

17 TA3OUT 3345 I2 F304 C6 IL35 I12

RES 4306
RES 4307
1 A(18) 50 ADDR I359 BACKLIGHT_BOOST 7303 3346 D5 F305 F5 IL37 B6

8
18 100R PCA9515ADP
7 IL26 A(19) 49 21 3L60 F370 DVB_SW 7L23 F309 G5
3347 D5 IL38 B6

RES 3L14
19 TA3IN
2 48 F303 HDMI_RST_MUX 8 M24C64-WMN6 VCC

3362

3361
0 3348 D5 F310 C10 IL39 D6
7323-1 47 RES FOR BDS 3L12 3K3 +3V3_STBY
NL27WZ08USG 46 1 P7<0:7>
3352 3K3 Φ IIC_SDA_SIDE 3349 D5 F311 C10
4

CS +3V3_SW F363 3 SDA0 SDA1 6


2
36 3L61 100R 3L53 100R BOLT_ON_SCL (8Kx8) E_PAGE 3350 E5 F312 C12
F389 45 7
3 CTS0 I318 WC 3351 G7 F313 C10
EEPROM 3V3 F364 3355
G CS P4<0:7>
RTS0
CLK0
35
NC RES FOR BDS 3L13 3K3 +3V3_STBY
1
2 0 SCL
6
2 SCL0 SCL1 7 IIC_SCL_SIDE
G 3352 G7
3353 F11
F314 C12
F315 C10
I365 SCL1 1 ADR F365 100R 3354 G7 F316 C12
WR 3L71 22R 3V3 44 34 3351 3K3 3 5
WRL RXD0 +3V3_SW BOLT_ON_SDA 2 SDA F317 D10

4316
33 3354 100R 5 EN 1 3355 G11
WR TXD0
4 3L54 NC NC NC 3356 C7 F318 D12
43 3L02 100R F309 3L01 4K7 100R GND
WRH SDA0 +3V3_STBY F345 3357 C5 F319 D10
22R I368 BHE CTS0 RES
RD 3384 42 32 3359 F13 F320 D12

4
RD CTS1
3L94 4K7 41 BOOT LOADER 4313 3360 F13 F321 D10
+3V3_STBY 40 BCLK RTS1
3L03 10K
3L73 I384 39 HLDA CLKS1
31 +3V3_STBY PANEL BOLT_ON_SDA F387 RES 4314 IIC_SDA RES 4304
3361 G13 F322 D12
47K HOLD CLK1 3362 G13 F323 B6
ALE_EMU +3V3_STBY 38 +3V3_STBY BOLT_ON_SCL F388 RES 4315 IIC_SCL
For Development only

3386 100R ALE SCL1 RES 4L03 RES 4305 3380 D5 F324 D10
3L95 4K7 37 30 3382 E7 F325 D12
+3V3_STBY RDY RXD1 1311
3L06

3L07

29
10K

10K

CLKOUT TXD1 3384 G2 F326 D10


UART CON

SDA1 3V2 KEYB 3386 H2 F327 D12


H 5 4 H
BZX384-C6V8
P5<0:7> P6<0:7> 3 F357 RES 3387 D5 F328 D10
6308 EMC +5V_STANDBY +3V3_STBY
1306

3L08 100R I391 2327 3388 E5 F329 D10


VSS AVSS 3L09 100R I392 2
1 10n 3389 H11 F330 A1

3L10

4302

4303
RES

RES
1R0
12
62

94

1L20 3390 I11 F331 D10


COMPAI R RESERVED 3391 I11 F332 D10
1314 7 F382 3389 47R LED1 3393 D1 F333 D10
IIC_SDA_up F342 MSJ-035-29D PPO (PHT)
3343 100R 6 I373 5304 220R I374 3395 E2 F334 D10
2 RESERVED 1312 ITV_Connector A: 5 F383 3390 47R I376 LED2 3396 C7 F335 D10
3345 100R F343 1
F346 4 F384 3391 47R REMOTE 3397 E5 F336 D10
3 1 F347 BOLT_ON_SCL 3 3398 E2 F337 D12
IIC_SCL_up 1313
2 F360
F349 BOLT_ON_SDA 2 3399 E3 F338 D10
+5V_STANDBY
PESD3V3L1BA

PESD3V3L1BA

1 3 1 F339 E10
2

F344 +5V_STANDBY 3L01 G6


4

2329 1n0

2330 1n0

2331 1n0

1n0
2

2335 1n0

2336 1n0

1n0
F348

2332 1n0
ITV_SPI_DATA_I N 440054-7 3L02 G5 F340 E10
BZX384-C6V8

BZX384-C6V8

BZX384-C6V8

BZX384-C6V8
1308

1309

1310
1307

5
6312
3
6306

1302

6307

1303

6310

6311
RES 6309

6 F353 ITV_SPI_CLK 3L03 H5 F341 E10


F351 REMOTE 3L04 E2 F342 H3

EMC
440054-3

EMC

EMC
EMC

1n0 2333

2337
7
I 8
F352
F354
IBO_IRQ
STANDBY
I 3L05 B5
3L06 H6
F343 I3
F344 I3
1

9
RES

RES

RES

SC1_CVBS_RF_OUT IL34 3L07 H7 F345 G10


10 IL35

1n0
RESET_n 3L08 H6 F346 I5
11

4310

4309
12 3L09 H6 F347 I5
3309 75R IBO_CVBS_IN 3L10 H11 F348 I5

2340

2339
RES
13

RES
3L11 C7 F349 I5
1415 3311 75R TO / FROM IR/ LED & KEYBOARD 3L12 G7 F350 F8
H_17370_009.eps 3L13 G7 F351 I5
3139 123 6273.1 010804 3L14 G9 F352 I5

1 2 3 4 5 6 7 8 9 10 11 12 13
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 53

SSB: Trident WX68


1 2 3 4 5 6 7 8 9 10 11 1C24 A6 FC02 A2
2C01 A6 FC03 B2

Trident - WX68 2C02 A6 IC01 D10

B05A Pin Name


WS
Pin No
U12
1(HIGH)
Use ALE to latch Address
0(LOW)
Use Falling Edges of WR#&RD# to latch Address(*)
B05A 2C03 A8 IC02 D11
2C04 B8 IC07 A3
2C05 B8
SD0 V12 Use Rising Edge of WR# to latch data(*) Use Falling Edge of WR# to latch dat a 2C06 B8
SCK Y11 I2C Slave Address=0x7E/7F(*) I2C Slave Address=0x7C/7D 2C07 B8
2C08 B8
7C01-3 2C09 B8
SVP WX68
2C10 B8
+3V3_SW 5C06 FC01 2C11 B8
A WX_PVCC WX_PVCC
L4
IC07 M5 PVCC
2C01 18p
A 2C12 B8
10u 6.3V

220R ANTSTO
2C23

2C22
100n M4 2C13 B8
AVCC1

3C01

1C24

24M0
TxFPGAe_0p

1M0
N4 A14 7C01-1 2C14 B8
AVCC2 TA1P TxFPGAe_0n
N5 B14 SVP WX68 2C15 B8
WX_AVCC AVCC3 TA1M TxFPGAe_1p 3C02
P4 A15

TO FPGA / TO LVDS CONNECTO R


L2
AVCC4 TB1P
B15 TxFPGAe_1n 2C02 18p 33R W1 Y4 2C03 100n CVBS_RF 2C17 C8
+3V3_SW 5C07 FC02 NC RXC- TB1M XTALI CVBS1
WX_AVCC L1 A16 TxFPGAe_2p Y1 V6 2C04 100n HD_Y_IN 2C18 C8
NC RXC+ TC1P XTALO Y_G1
TxFPGAe_2n 2C19 C8
10u 6.3V

L3 B16 WX_PAVDD1 2C81 2n7 U2 W6 2C05 100n SC1_G_IN


220R TMDS_GND1 TC1M MLF1 Y_G2
2C27

2C26

2C25

2C24

AD(0:7)
100n

100n

100n
M3 A18 TxFPGAe_3p WX_PAVDD2 2C82 2n7 R4 Y6 2C06 100n FRONT_CVBS_SVHS_Y_IN 2C20 D8
TMDS_GND2 TD1P PLF2 Y_G3
N3 B18 TxFPGAe_3n AD(0) 3C04-1 1 8100R L17 W2 SC1_RF_OUT_CVBS
TMDS_GND3 TD1M AD0 CVBS_OUT1 2C21 D8
P3 A19 TxFPGAe_4p AD(1) 3C04-2 2 7100R L18 V2 SC2_CVBS_MON_OUT
TMDS_GND4 TE1P
TxFPGAe_4n AD(2)
AD1 CVBS_OUT2 2C22 A1
R1 B19 3C04-3 3 6100R L19 V9 2C07 100n SVHS_C_IN
TMDS_GND5 TE1M TxFPGAe_CLKn AD2 C 2C23 A1
M2 B17 AD(3) 3C04-4 4 5100R L20 W9 2C08 100n HD_PB_IN
RX0- TCLK1M AD3 PB_B1
B M1
N2
RX0+ TCLK1P
A17
F19
TxFPGAe_CLKp
TxFPGAo_CLKn
AD(4)
AD(5)
3C05-1 1
3C05-2 2
8100R
7100R
K17
K18
AD4 PB_B2
Y9 2C09
Y10 2C10
100n
100n
SC1_B_IN
SC1_CVBS_IN
B 2C24 B2
2C25 B2
NC
RX1- TCLK2M TxFPGAo_CLKp AD5 PB_B3
N1 E20 AD(6) 3C05-4 4 5100R K19 Y8 2C11 100n HD_PR_IN 2C26 B1
RX1+ TCLK2P TxFPGAo_4n AD6 PR_R1
P2 H19 A(0:7) AD(7) 3C05-3 3 6100R K20 W8 2C12 100n SC1_R_IN
RX2- TE2M TxFPGAo_4p A(0)
AD7 PR_R2 2C27 B1
+3V3_SW 5C08 FC03 WX_REGVCC
P1
RX2+ TE2P
G20 3C06-4 4 5100R N17
ADDR0 PR_R3
V8 2C13 100n SC2_Y_CVBS_IN
WX_REGVCC R5 G19 TxFPGAo_3n A(1) 3C06-3 3 6100R N18 V4 2C14 100n IBO_CVBS_IN 2C28 C1
REGVCC TD2M ADDR1 FS1
TxFPGAo_3p 2C29 C1
10u 6.3V

P5 F20 A(2) 3C06-2 2 7100R N19 W4 2C15 100n SC2_C_IN


220R DGND TD2P ADDR2 FS2
2C29

2C28
100n

T10 E19 TxFPGAo_2n A(3) 3C06-1 1 8100R N20 Y5 SC1_FBL_IN 2C30 D9


NC PWR5V TC2M ADDR3 FB1
T11 D20 TxFPGAo_2p A(4) 3C03-1 1 8100R M20 U4
NC DSCL TC2P ADDR4 FB2 NC 2C33 F3
U11 B20 TxFPGAo_0n A(5) 3C03-2 2 7100R M19 V10 PC_VGA_H
NC DSDA TA2M
A20 TxFPGAo_0p A(6)
ADDR5 AIN_H 2C73 D9
U12
WS TA2P 3C03-3 3 6100R M18
ADDR6 AIN_V
U10 PC_VGA_V
V11 D19 TxFPGAo_1n A(7) 3C03-4 4 5100R M17 U8 2C17 100n IBO_R_IN 2C74 D11
NC SCDT TB2M ADDR7 PC_R
V12 C20 TxFPGAo_1p ALE_EMU J18 Y7 2C18 100n IBO_G_IN 2C81 B6
+3V3_SW SD0 TB2P ALE PC_G 100n IBO_B_IN
+3V3_SW +3V3_SW W11 WR J19 W10 2C19 2C82 B6
AUDIOCLK WR_ PC_B
C NC
NC
W12
Y11
SPDIF RD
IIC_SDA 3C08 100R
J20
H17
RD_ TESTMODE
F17 3C19
F16
470R
3C20 1K0 +5V_STANDBY
C 3C01 A6
SCK SDA V5SF 3C02 A7
3C39

3C40

3C41
RES

IIC_SCL H18 G17


4K7

4K7

4K7

3C09 100R SCL PWM0


CS 3C10 0R J17 G18 INT +3V3_SW 3C03-1 C6
CPU_CS INTN
F18 4C07 RST_H 3C03-2 C6
RESET
3C03-3 C6

100n
100n
3C03-4 C6
RES
3C42

3C43

3C44
RES
4K7

4K7

4K7

3C22 3C23 3C04-1 B6

2C21

2C20
FPGA_BL_DIMMING 4K7 220R 3C04-2 B6
IC02
3C04-3 B6
7C04 3C24 BL_ADJUST
3C04-4 B6

100n
BC847BW
RES 100R 3C05-1 B6
3C07
3C05-2 B6
D 100R
D

2C30
RES 3C05-3 B6
2C74
IC01 22u 3C05-4 B6
3C25 10K 7C02 3C06-1 C6
BC847BW
3C06-2 B6
RES
2C73 3C06-3 B6
10u 3C06-4 B6
3C07 D9
RES 3C08 C6
4C08 3C09 C6
3C10 C6
3C19 C8
E RES E 3C20 C9
3C22 D10
+5V_SW
7C03-1
+3V3_SW
FOR ITV ONLY 3C23 D11
3C24 D11
14

74LCX14T
3C25 D9
3C29

4K7

1 2 3C30 PC_VGA_H 3C29 E2


3C31 22R 3C30 E3
VGA_H 3C31 F2
7

22R 3C32 F2
7C03-2
3C33 F2
14

74LCX14T
PC_VGA_V
3C34 F3
+5V_SW 3 4 3C34
3C36 F3
F 22R F 3C37 G3
3C39 C1
7

2C33 3C40 C2
3C32

4K7

7C03-3
14

74LCX14T 3C41 C2
100n
3C33 3C36 3C42 D2
VGA_V 5 6
3C43 D2
22R 22R 3C44 D2
4C07 C8
7

7C03-4 7C03-5 7C03-6 4C08 E10


14

14

14

74LCX14T 74LCX14T 74LCX14T 5C06 A1


3C37 5C07 A1
9 8 11 10 13 12
5C08 B1
G 22R G 7C01-1 A7
7C01-3 A3
7

7C02 D10
7C03-1 E2
7C03-2 F2
7C03-3 F2
7C03-4 G2
7C03-5 G4
7C03-6 G5
H_17370_010.eps
3139 123 6273.1 010804 7C04 D10
FC01 A2

1 2 3 4 5 6 7 8 9 10 11
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 54

SSB: DDR & CPU Interface


1 2 3 4 5 6 7 8 9 10 11
2D02 C2

B05B DDR&CPU INTERFACE B05B


2D03 C3
2D04 C3
2D08 C3
2D09 C3
2D10 C3
A A 2D11 C2
2D12 C3
2D14 G1
2D18 C2
2D31 B3
+2V5_VDDMQ +2V5_VDDMQ 2D32 B4
5D03 FD01 2D33 B4
+2V5_SW +2V5_VDDMQ 2D34 B4

2D33

3D15
100n

1K0
220R 2D37 C8
22u 6.3V
2D71

2D72
2D38 C9

10n
DDR_VREF 2D39 C9
2D43 C8
B B

RES 2D31

2D32

2D34

3D16
100n

100n

100n

1K0
2D46 C7
2D57 C8
2D58 C8
2D59 C9
2D60 C9
2D71 B2
2D72 B2
+2V5_VDDMQ +2V5_VDDMQ 3D01-1 E4
3D01-2 E4
3D01-3 E4

470p
100n

470p
100n
470p

470p

100n

100n

100n

100n
3D01-4 E4
10n

10n

10n

10n

10n

10n
3D02-1 E4
C C
2D18

2D46
10u

10u
3D02-2 E4
2D02

2D04

2D03

2D43
2D11

2D12

2D57

2D58

2D59

2D60
2D08

2D09

2D37

2D38

2D39
2D10
3D02-3 D4
3D02-4 D4
3D05-1 D4
3D05-2 D4
3D05-3 D4
1

18

33

15

55

61

18

33

15

55

61
7D01 7D02 3D05-4 D4
K4D261638K K4D261638K
3D06-1 D4
VDD VDDQ VDD VDDQ 3D06-2 D4
WX_MA0 29 2 1_DQ0 3D06-1 1 8 22R WX_MD4 WX_MA0 29 2 2_DQ16 3D43-1 1 8 22R WX_MD20
A0 DQ0 A0 DQ0 2_DQ17 3D06-3 D4
WX_MA1 30 4 1_DQ1 3D06-2 2 7 22R WX_MD5 WX_MA1 30 4 3D43-2 2 7 22R WX_MD21
A1 DQ1 A1 DQ1
WX_MA2 31
A2 DQ2
5 1_DQ2 3D06-3 3 6 22R WX_MD6 WX_MA2 31
A2 DQ2
5 2_DQ18 3D43-3 3 6 22R WX_MD22 3D06-4 D4
D WX_MA3
WX_MA4
32
35
A3
A4
DQ3
DQ4
7
8
1_DQ3
1_DQ4
3D06-4
3D05-4
4
4
5
5
22R
22R
WX_MD7
WX_MD3
WX_MA3
WX_MA4
32
35
A3
A4
DQ3
DQ4
7
8
2_DQ19
2_DQ20
3D43-4
3D44-4
4
4
5
5
22R
22R
WX_MD23
WX_MD18 D 3D09 F1
3D10 G1
WX_MA5 36 10 1_DQ5 3D05-3 3 6 22R WX_MD2 WX_MA5 36 10 2_DQ21 3D44-3 3 6 22R WX_MD16
WX_MA6 37
A5 DQ5
11 1_DQ6 3D05-2 2 7 22R WX_MD1 WX_MA6 37
A5 DQ5
11 2_DQ22 3D44-2 2 7 22R WX_MD17 3D11 F1
A6 DQ6 A6 DQ6 3D14 G1
WX_MA7 38 13 1_DQ7 3D05-1 1 8 22R WX_MD0 WX_MA7 38 13 2_DQ23 3D44-1 1 8 22R WX_MD19
A7 DQ7 A7 DQ7
WX_MA8 39
A8 DQ8
54 1_DQ8 3D02-4 4 5 22R WX_MD15 WX_MA8 39
A8 DQ8
54 2_DQ24 3D47-4 4 5 22R WX_MD31 3D15 B4
WX_MA9 40 56 1_DQ9 3D02-3 3 6 22R WX_MD14 WX_MA9 40 56 2_DQ25 3D47-3 3 6 22R WX_MD30 3D16 B4
A9 DQ9 A9 DQ9
WX_MA10 28 57 1_DQ10 3D02-2 2 7 22R WX_MD12 WX_MA10 28 57 2_DQ26 3D47-2 2 7 22R WX_MD28
A10|AP DQ10 1_DQ11 A10|AP DQ10 2_DQ27
3D38 F7
WX_MA11 41 59 3D02-1 1 8 22R WX_MD13 WX_MA11 41 59 3D47-1 1 8 22R WX_MD29
A11 DQ11 A11 DQ11 3D40 F7
60 1_DQ12 3D01-1 1 8 22R WX_MD9 60 2_DQ28 3D48-1 1 8 22R WX_MD24
DQ12 DQ12 3D43-1 D10
62 1_DQ13 3D01-2 2 7 22R WX_MD8 62 2_DQ29 3D48-2 2 7 22R WX_MD25
DQ13 DQ13
DQ14
63 1_DQ14 3D01-3 3 6 22R WX_MD10
DQ14
63 2_DQ30 3D48-3 3 6 22R WX_MD26 3D43-2 D10
49 65 1_DQ15 3D01-4 4 5 22R WX_MD11 49 65 2_DQ31 3D48-4 4 5 22R WX_MD27 3D43-3 D10
DDR_VREF VREF DQ15 DDR_VREF VREF DQ15
3D43-4 D10
E WX_CS0#
WX_MCK0
24
45
CS_
CK NC1
14
WX_CS0#
WX_MCK0
24
45
CS_
CK NC1
14
E 3D44-1 D10
WX_MCK0# 46 17 WX_MCK0# 46 17 3D44-2 D10
CK_ NC2 CK_ NC2
WX_CLKE 44
CKE NC3
25 WX_CLKE 44
CKE NC3
25 3D44-3 D10
43 NC 43 NC 3D44-4 D10
NC4 NC4
WX_BA0 26 53 WX_BA0 26 53
BA0 NC5 BA0 NC5 3D47-1 E10
WX_BA1 27 42 WX_BA1 27 42
BA1 NC6 BA1 NC6 3D47-2 E10
WX_DQM0 20 WX_DQM2 20 3D47-3 D10
LDM LDM
WX_DQM1 47
UDM
WX_DQM3 47
UDM
3D47-4 D10
WX_DQS0 3D11 15R 1_DDQS0 16 WX_DQS2 3D38 15R 2_DDQS2 16 3D48-1 E10
LDQS LDQS
WX_DQS1 3D09 15R 1_DDQS1 51 WX_DQS3 3D40 15R 2_DDQS3 51
UDQS UDQS 3D48-2 E10
19 19
WX_WE# 21
DNU1
50 WX_WE# 21
DNU1
50 3D48-3 E10
WE_ DNU2 WE_ DNU2 3D48-4 E10
F WX_CAS#
WX_RAS#
22
23
CAS_
RAS_
WX_CAS#
WX_RAS#
22
23
CAS_
RAS_
F 5D03 B1
VSS VSSQ VSS VSSQ 7D01 D2
7D02 D8
FD01 B2
51R
51R

34

48

66

12

52

58

64

34

48

66

12

52

58

64
6

6
ID01 G2
ID01 ID05
ID05 G8
3D10

3D14
2D14

10n

G G

H_17370_011.eps
3139 123 6273.1 010804

1 2 3 4 5 6 7 8 9 10 11
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 55

SSB: WX Power / Ground


1 2 3 4 5 6 7 8 9 10 11 2E01 E2 FE04 F2
2E02 E2 FE05 G2

B05C WX POWER / GROUND B05C


2E03 E2 FE06 A1
2E04 E2 FE07 B1
2E05 F1 FE08 B1
2E06 F1 IE04 C9
2E07 F2 IE05 C9
2E08 F2 IE06 C9
2E09 F2 IE07 C9
+1V2_SW +3V3_SW 2E10 F2 IE08 D9
2E11 G2 IE09 D9
A 5E12 FE06
+1V2_ADC A 2E12 G2 IE10 C6

22u 6.3V

100n
100n

100n

100n
150R 2E68 2E13 G2 IE11 D6

100n

10u 6.3V
2E67
2E14 G2 IE12 F6

2E48
2E15 G2 IE15 C9

2E47
2E44

2E45

2E46
2E16 G2
5E13 FE07 2E17 G2
+1V2_PLL 2E18 G2
22u 6.3V

150R 2E19 C6
2E70

2E69

100n

Pin Name Pin No 1(HIGH) 0(LOW) 2E20 C6


DP_HS P19 MPU in A/D Multiplix Mode MPU in A/D Separate Mode(*) 2E21 C6
2E22 C6
B 5E14 FE08
+1V2_CORE
7C01-2
B 2E23 D6
2E24 D6
22u 6.3V

33R 7C01-4
SVP WX68 2E25 D6
2E71

100n
2E72

SVP WX68 DDR_VREF


+3V3_SW 2E26 D6
C14 B3 WX_BA1 2E27 E6
VDDC1 VSS1 5E06 BA1
C15 C6 WX_AVDD3_OUTBUF WX_BA0 K4
VDDC2 VSS2 BA0 2E28 E6

10u 6.3V
D13 C9 K3
VDDC3 VSS3 220R MVREF 2E29 E6

2E19

2E20
100n
+1V2_CORE D14 C12 WX_DQS3 E3
VDDC4 VSS4 DQS3
D15 D2 WX_DQS2 B2 2E30 E6
VDDC5 VSS5 DQS2
E13 H8 WX_AVSS_OUTBUF WX_DQS1 B6 2E31 F6
VDDC6 VSS6 DQS1
E14 H9 WX_DQS0 B9 +3V3_SW
100n

100n

100n

100n

100n

100n

100n

100n

100n
VDDC7 VSS7 DQS0 2E32 F6
10u 6.3V

E15 H10 +3V3_SW WX_CLKE B12


10u 6.3V

VDDC8 VSS8 CLKE 2E33 F6


2E66

2E57

G16 H11 IE10 WX_DQM3 IE15 K2


VDDC9 VSS9 5E07 DQM3 2E34 F6
H5 H12 WX_AVDD3_BG_ASS WX_DQM2 IE04 B1
C VDDC10 VSS10 DQM2
C
2E56

2E55

2E54

2E53

2E51
2E58

2E52

2E50

2E49

2E35 D2

10u 6.3V
H16 H13 WX_DQM1 A6
VDDC11 VSS11 220R DQM1

RES
2E21

2E22

3E05
100n
J5 J8 WX_DQM0 A9 2E36 D2

4K7
VDDC12 VSS12 DQM0 VS NC
J16 J9 WX_MCK0# A12 P17 DP_HS 2E37 D2
VDDC13 VSS13 MCK0_ HS
K5 J10 WX_AVSS_BG_ASS WX_MCK0 IE05 E1 P19 DP_HS
K16
VDDC14 VSS14
J11 +3V3_SW D1
MCK0 DPB_HS
V19
NC 2E38 D2
VDDC15 VSS15 CS1_ DPB_VS NC 2E39 D2
R16 J12 WX_CS0# IE06 J3 V20 HDMI_H
VDDC16 VSS16 3E02 CS0_ DPA_HS
2E40 D2

3E06
+2V5_VDDMQ T14 J13 WX_PAVDD1 WX_WE# IE07 J4 Y19 HDMI_V

4K7
VDDC17 VSS17 WE_ DPA_VS

10u 6.3V
T15 K8 WX_CAS# IE08 K1 Y20 HDMI_DE 2E41 D3
VDDC18 VSS18 22R CAS_ DPB_DE

2E23

2E24
IE09

100n
B4 K9 WX_RAS# J1 W20 HDMI_VCLK 2E42 D3
VDDM1 VSS19 RAS_ DPA_CLK
C4 K10 WX_MD31 J2 Y15
100n

100n

100n

100n

100n

100n

100n
100n

470p

470p

VDDM2 VSS20 MD31 DPB_CLK NC 2E43 D1


D4 K11 WX_PAVSS1 WX_MD30 D3 T19 HDMI_Cr(9)
10u 6.3V

VDDM3 VSS21 MD30 DPA23 2E44 A3


2E43

D5 K12 WX_MD29 C3 Y12 HDMI_Cr(8)


VDDM4 VSS22 3E04 MD29 DPA22
D11 K13 WX_PAVDD2 WX_MD28 C2 U13 HDMI_Cr(7) 2E45 A3
VDDM5 VSS23 MD28 DPA21
2E41
2E40

10u 6.3V
2E37

2E39

2E75

2E76

E5 L5 WX_MD27 C1 V13 HDMI_Cr(6) 2E46 A3


2E35

2E36

2E42

D D
2E38

VDDM6 VSS24 22R MD27 DPA20

2E25

2E26
100n
E6 L8 WX_MD26 A1 W13 HDMI_Cr(5) 2E47 A4
VDDM7 VSS25 MD26 DPA19
E9 L9 WX_MD25 A2 Y13 HDMI_Cr(4)
E10
VDDM8 VSS26
L10 WX_PAVSS2 WX_MD24 A3
MD25 DPA18
Y14 HDMI_Cr(3)
2E48 A3
VDDM9 VSS27 MD24 DPA17 2E49 C3
E11 L11 WX_MD23 C5 W14 HDMI_Cr(2)
VDDM10 VSS28 MD23 DPA16
+3V3_SW E12 L12 +1V2_ADC WX_MD22 A4
DPA15
V14 HDMI_Cb(9) 2E50 C3
+2V5_VDDMQ +3V3_SW VDDM11 VSS29 MD22
F5 L13 IE11 WX_MD21 B5 U14 HDMI_Cb(8) 2E51 C3
5E16 FE01 VDDM12 VSS30 5E08 MD21 DPA14
WX_AVDD3_ADC1 G5 M8 WX_AVDD_ADC1 WX_MD20 A5 U15 HDMI_Cb(7) 2E52 C3
VDDM13 VSS31 MD20 DPA13
10u 6.3V

10u 6.3V
L16 M9 WX_MD19 D6 V15 HDMI_Cb(6)
220R VDDH1 VSS32 150R MD19 DPA12 2E53 C2
2E01

2E02

3E07

2E27

2E28
100n

100n
M16 M10 WX_MD18 A7 W15 HDMI_Cb(5)
VDDH2 VSS33 MD18 DPA11
0R

N16 M11 WX_MD17 B7 Y16 HDMI_Cb(4) 2E54 C2


VDDH3 VSS34 MD17 DPA10
WX_AVSS_ADC1 P16 M12 WX_AVSS_ADC1 WX_MD16 C7 W16 HDMI_Cb(3) 2E55 C2
2E77 VDDH4 VSS35 MD16 DPA9
T12 M13 WX_MD15 D7 V16 HDMI_Cb(2) 2E56 C2
VDDH5 VSS36 MD15 DPA8
+3V3_SW T13 N8 +1V2_ADC WX_MD14 D8 U16 HDMI_Y(9) 2E57 C1
RES 10u VDDH6 VSS37 MD14 DPA7
R17 N9 WX_MD13 C8 U17 HDMI_Y(8)
E 5E17 FE02
WX_AVDD3_ADC2 R18
VDDH7
VDDH8
VSS38
VSS39
N10 WX_AVDD_ADC2
5E09
WX_MD12 B8
MD13
MD12
DPA6
DPA5
V17 HDMI_Y(7) E 2E58 C2
2E66 C1
10u 6.3V

10u 6.3V
NC P20 N11 WX_MD11 A8 W17 HDMI_Y(6)
220R NC VSS40 150R MD11 DPA4
2E67 A2
2E03

2E04

2E29

2E30
100n

100n
WX_AVDD3_ADC1 Y3 N12 WX_MD10 D9 Y17 HDMI_Y(5)
AVDD3_ADC1 VSS41 MD10 DPA3
WX_AVDD3_ADC2 U9 N13 WX_MD9 D10 Y18 HDMI_Y(4) 2E68 A1
AVDD3_ADC2 VSS42 MD9 DPA2
+3V3_SW WX_AVSS_ADC2 WX_AVDD3_OUTBUF U3 P18 WX_AVSS_ADC2 WX_MD8 C10 W18 HDMI_Y(3)
AVDD3_OUTBUF VSS43 MD8 DPA1 2E69 B2
E2 T16 WX_MD7 B10 V18 HDMI_Y(2)
5E03 E8
VDDR1 VSS44
H20 +1V2_ADC WX_MD6 A10
MD7 DPA0
W19
2E70 B1
220R FE03 VDDR2 VSS45 WX_AVSS_OUTBUF MD6 DPB15 NC 2E71 B1
WX_LVDS_VDD WX_AVDD3_BG_ASS V3 Y2 IE12 WX_MD5 A11 U18
AVDD3_BG_ASS AVSS_OUTBUF 5E10 MD5 DPB14 NC
WX_PAVDD1 T3 E4 WX_AVDD_ADC3 WX_MD4 B11 U19 HDMI_Cb(1) 2E72 B2
10u 6.3V

PAVDD1 VSSR1 MD4 DPB13


2E05

2E06

2E07

2E08
100n

100n

100n

10u 6.3V
WX_PAVDD2 T4 E7 WX_MD3 C11 U20 HDMI_Cb(0) 2E75 D3
PAVDD2 VSSR2 150R MD3 DPB12

2E31

2E32
100n
WX_AVDD_ADC1 U5 W3 WX_AVSS_BG_ASS WX_MD2 D12 T20 HDMI_Cr(1) 2E76 D3
AVDD_ADC1 AVSS_BG_ASS MD2 DPB11
WX_LVDS_VSS WX_AVDD_ADC2 U7 T2 WX_PAVSS1 WX_MD1 A13 T18 HDMI_Cr(0)
WX_AVDD_ADC3 T8
AVDD_ADC2 PAVSS1
R3 WX_PAVSS2 WX_AVSS_ADC3 WX_MD0 B13
MD1 DPB10
T17 HDMI_Y(1)
2E77 E3
AVDD_ADC3 PAVSS2 MD0 DPB9 3E02 C7
+1V2_PLL WX_AVDD_ADC4 U6 T5 WX_AVSS_ADC1 WX_MA11 C13 R19 HDMI_Y(0)
F 5E04 FE04 +1V2_PLL
D18
AVDD_ADC4
LVDS_VDDP
AVSS_ADC1
AVSS_ADC2
T7 WX_AVSS_ADC2 +1V2_ADC WX_MA10 F1
F2
MA11
MA10
DPB8
R20 F 3E04 D7
WX_AVDDAPLL E17 T9 WX_AVSS_ADC3 5E11 WX_MA9 3E05 C11
LVDS_VDDA AVSS_ADC3 MA9
10u 6.3V

WX_LVDS_VDD D16 T6 WX_AVSS_ADC4 WX_AVDD_ADC4 WX_MA8 F3 3E06 C11


150R LVDS_VDDD AVSS_ADC4 MA8
2E10

2E09

100n

10u 6.3V
WX_AVDDAPLL C17 E18 WX_MA7 F4
LVDS_VDDO1 LVDS_VSSP 150R MA7 3E07 E3
2E33

2E34
100n

WX_AVDDLLPLL D17 E16 WX_MA6 G4


LVDS_VDDO2 LVDS_VSSA MA6 5E03 E1
WX_AVSSAPLL U1 C16 WX_LVDS_VSS WX_MA5 G3
AVDDAPLL LVDS_VSSD MA5
R2 C18 WX_AVSS_ADC4 WX_MA4 G2
MA4
5E04 F1
AVDDLLPLL LVDS_VSSO1
+1V2_PLL V5 C19 WX_MA3 G1 5E05 G1
VREFN_1 LVDS_VSSO2 MA3
W5 V1 WX_AVSSAPLL WX_MA2 H1 5E06 B7
5E05 FE05 VREFP_1 AVSSAPLL MA2
WX_AVDDLLPLL V7 T1 WX_AVSSLLPLL WX_MA1 H2
VREFN_2 AVSSLLPLL MA1 5E07 C7
10u 6.3V

W7 WX_MA0 H3
150R VREFP_2 MA0 5E08 D7
2E12

2E11

100n

H4
5E09 E7
5E10 F7
G 100p
WX_AVSSLLPLL
G 5E11 F7
2E13
2E14 100p 2E15 100p
5E12 A1
5E13 B1
5E14 B1
2E17 100p 2E16 100p 5E16 D1
2E18 100p 5E17 E1
7C01-2 B10
7C01-4 B4
H_17370_012.eps
3139 123 6273.1 010804
FE01 D2
FE02 E2
FE03 F2
1 2 3 4 5 6 7 8 9 10 11
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 56

SSB: FPGA Interface (AL Sets only)


1 2 3 4 5 6 7 8 9 10
1201 F3
1202 F4

B05D FPGA INTERFACE +3V3_FPGA


B05D 1203 C9
1204 A7
(ONLY FOR AMBI-LIGHT SET) 2201 E6
2202 E6
5202 2203 F2
30R
2204 F2
I201
A +3V3_FPGA
1204
A 2205 G4
2206 G4
DSO751SV 2207 G4
1 4 2208 G4
2209 G5
5201 I232
30R 3 3236 CLK_OSC1 2210 G5
2211 B2
47R F237
2212 B5

2
I205 2214 27M0 2213 B6
10u
2214 B7
7202 RES RES
2211 EPCS16SI16N 2212 2213
3201 E5

1
10n 7201 RES 3 10n 10n 3202 E5
B EPCS4SI8 VCC
B 3203 E2

3
4

8
Φ NC 5 3204 E2
VCC F222
1 nCSO nCSO 7 SCD 6
Φ CS_ CS +3V3_FPGA
3205 E2
+3V3_FPGA
2 F223 3206 E2
SCD 6 DCLK DCLK 16 8
DATA DCLK DCLK DATA 3207 G5
F224
5 ASDO ASDO 15 11 RES 3222 F5
ASDI ASDI
3224 F5

FOR PROGRAMMING FPGA


12 3231 3232
1K0

(FOR DEVELOPMENT)
SOFTWARE DEBUGGER
GND NC 13 3225 G5
4
14
GND 1203
3231 C7
TMS_FPGA 3232 C7

10
F204 3246 100R JTAG_TMS
1
F227 TDI_FPGA F208 3240 100R F236 JTAG_TDI 3234 C7
TDO_FPGA 2
DATA0 DATA0 F202 3235 100R JTAG_TDO 3235 C7
C TCK_FPGA F225 3234 100R F201 JTAG_TCK
3
4 C 3236 A8
F207
5 3238 C7
RES +3V3_FPGA 6 3240 C7
3238 1K0
440054-6 3246 C7
3247 F5
3248 G5
4201 F2
4202 F2
4203 G2
4204 G3
4205 G2
D D 5201 A2
5202 A7
7201 B3
7202 B4
F201 C9
F202 C7
IIC_SCL_up 3201 100R MAIN_SCL F204 C7
IIC_SDA_up 3202 100R MAIN_SDA F207 C9
F208 C7
+3V3_FPGA RES RES F209 E3
TO DRIVE IC AL DRIVERS 2201 2202
F211 E1
100p 100p
F214 E3
E 3204 3203
E F222 B4
F223 B4
1K5 1K5
F224 B4
AMBI_SCL I209
100R 3205 S_SCL F209
F225 C7
F227 C4
F211
AMBI_SDA 100R 3206 S_SDA F214 F236 C9
F237 B8
I201 A6
2204 2203 I205 B2
1n0 1n0
I206 G2
2 CONNECTORS
I207 G2
I209 E1
F +3V3_FPGA +3V3_FPGA
OVERLAPPING 5PIN & 7PIN
F I210 F4
1202
RES I211 F4
1201
440054-5 440054-7 FOR PWM AL DRIVER I212 F4
I213 G4
4202

4201

1 1 I210 ambi_pwm(0)
RES

3247 100R
2 2 I211 3222 100R ambi_pwm(1) I232 A7
3 3 I212 3224 100R ambi_pwm(2)
I2S_SEL1 4 4 3225 100R ambi_pwm(3)
I207 I2S_SEL2 5 5 3207 100R ambi_pwm(4)
I206 6 I213 3248 100R ambi_pwm(5)
7
4205

4203

4204
RES

G G
1n0

1n0

1n0
1n0

2209 1n0

2210 1n0
2206

2208
2205

2207

H_17370_013.eps
3139 123 6273.1 010804

1 2 3 4 5 6 7 8 9 10
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 57

SSB: FPGA I/O Banks


2700 H1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2701 B2
2702 B3
2703 B4

B05E FPGA I/O BANKS B05E


2704 B4
2705 B4
2706 C2
2707 C2
2708 C2
2709 C3
2710 C3
A A 2711 C3
2712 C4
2713 C4
TO LVDS
FROM TRIDENT FROM TRIDENT TO LVDS 2714 C4
2715 C4
3747 2717 C2
+3V3_SW 5700 F701 +3V3_FPGA TxFPGAo_3p 2718 C2
22R 2719 C2
30R 3748 3720
180R TxFPGAe_3p 2720 C3
2701 2702 2703 2704 2705 3749 2721 C3
TxFPGAo_3n 22R
1u0 10n 10n 10n 10n 3721 2724 D2
22R
180R
B TxFPGAo_1p
3738 3722
TxFPGAe_3n B 2725 D3
2726 D3
22R 22R 2729 E2
3739
180R 2730 E3
TxFPGAo_1n
3740 INPUT BANK 3723
TxFPGAe_2p OUTPUT BANK 2734 G8
+2V5_SW 5701 F702 +2V5out-FPGA 22R 7700-5 22R 7700-3 3700 F10
EP2C5F256C7N 3724 EP2C5F256C7N
30R TxFPGAo_0p
3735
Φ
180R
3725
FPGA BYPASS Φ
3701 F10
3702 G11
22R TxFPGAe_2n
2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 3736 BANK4 TxFPGAo_0n 4703 TxLVDSo_0n BANK2 3703 F9
22R
4u7 10n 10n 10n 10n 10n 10n 180R M11 IO_M11|LVDS43p IO_T7|LVDS54p T7 4704 C4
10n 10n 10n 3737 TxFPGAo_0p TxLVDSo_0p TxLVDSe_3p IO_C4|LVDS10p IO_B9|LVDS21p B9 TxLVDSo_3p 3713 G7
TxFPGAo_0n L11 R7 TxFPGAo_1n 4705 TxLVDSo_1n TxLVDSe_3n C5 A9 TxLVDSo_3n 3714 F7
22R T14 IO_L11|LVDS43n IO_R7|LVDS54n T5 3726
TxFPGAe_1p TxFPGAo_1p 4706 TxLVDSo_1p TxLVDSe_0p G7 IO_C5|LVDS10n IO_A9|LVDS21n D10
IO_T14|LVDS44p IO_T5|LVDS55p IO_G7|LVDS11p IO_D10|LVDS22p 3720 B10
R14 R5 TxFPGAo_2n 4707 TxLVDSo_2n TxLVDSe_0n G6 D11
C 3741
T13 IO_R14|LVDS44n IO_R5|LVDS55n
IO_T13|LVDS45p IO_T4|LVDS56p
R13 IO_R13|LVDS45n IO_R4|LVDS56n
T4
R4
3727
180R
22R
TxFPGAo_2p 4708
4709
TxLVDSo_2p F9
F10
IO_G6|LVDS11n IO_D11|LVDS22n A10
IO_F9|LVDS12p IO_A10|LVDS23p TxLVDSo_4p C 3721 B10
5702 F703 +2V5in-FPGA TxFPGAo_2p 3728 TxFPGAo_3n TxLVDSo_3n IO_F10|LVDS12nIO_B10|LVDS23n B10 TxLVDSo_4n 3722 B10
22R T12 P5 TxFPGAe_1n TxFPGAo_3p 4710 TxLVDSo_3p TxLVDSe_2p E6 G11 3723 B10
30R 3742 R12 IO_T12|LVDS46p IO_P5|LVDS57p P4 22R TxFPGAo_4n 4711 TxLVDSo_4n TxLVDSe_2n F6 IO_E6|LVDS13p IO_G11|LVDS24p G10
NC 3724 B10
180R IO_R12|LVDS46n IO_P4|LVDS57n IO_F6|LVDS13n IO_G10|LVDS24n
P12 T3 TxFPGAo_4p 4712 TxLVDSo_4p TxLVDSo_0p A3 A12
2717 2718 2719 2720 2721 TxFPGAo_2n
3743 P13 IO_P12|LVDS47p IO_T3|LVDS58p R3 TxLVDSo_0n B3 IO_A3|LVDS14p IO_A12|LVDS25p B12 3725 C10
4u7 10n 10n 10n 10n IO_P13|LVDS47n IO_R3|LVDS58n 3729 IO_B3|LVDS14n IO_B12|LVDS25n 3726 C10
22R K11 IO_K11|LVDS48p IO_N9|LVDS59p N9 TxFPGAe_0p TxFPGAo_CLKn 4723 TxLVDSo_CLKn TxLVDSo_1p A4 IO_A4|LVDS15p IO_A13|LVDS26p A13
K10 N10 22R TxFPGAo_CLKp 4724 TxLVDSo_CLKp TxLVDSo_1n B4 B13 3727 C10
TxFPGAo_4p
3744 R10 IO_K10|LVDS48nIO_N10|LVDS59n L7 3730 TxLVDSo_2p A5 IO_B4|LVDS15n IO_B13|LVDS26n C12
3728 C10
IO_R10|LVDS49p IO_L7|LVDS60p 180R IO_A5|LVDS16p IO_C12|LVDS27p
22R T10 L8 TxFPGAe_0n 4713 TxLVDSe_0n TxLVDSo_2n B5 C13 3729 C10
3745 L9 IO_T10|LVDS49n IO_L8|LVDS60n N11 3731
TxFPGAe_0n TxFPGAe_0p 4714 TxLVDSe_0p TxLVDSe_CLKp C6 IO_B5|LVDS16n IO_C13|LVDS27n A14
180R IO_L9|LVDS50pIO_N11|VREFB4N0 IO_C6|LVDS17p IO_A14|LVDS28p 3730 D10
L10 IO_L10|LVDS50nIO_N8|VREFB4N1 N8 22R TxFPGAe_1n 4715 TxLVDSe_1n TxLVDSe_CLKn D6 IO_D6|LVDS17n IO_B14|LVDS28n B14
3746 T11 L12 4716 A6 D8 3731 D10
TxFPGAo_4n TxFPGAe_1p TxLVDSe_1p TxLVDSe_4p
+1V2-FPGA R11 IO_T11|LVDS51p IO_L12 P11 TxFPGAe_2n 4717 TxLVDSe_2n TxLVDSe_4n B6 IO_A6|LVDS18p IO_D8|VREFB2N1 C11
3732 E10
D +1V2_SW 5703 22R
R9
IO_R11|LVDS51n
T9 IO_T9|LVDS52p
IO_P11
IO_T6 T6 TxFPGAe_2p 4718
4719
TxLVDSe_2p TxLVDSe_1p F8
F7
IO_B6|LVDS18n
IO_C11|VREFB2N0
IO_F8|LVDS19p IO_A8 A8
A11
D 3733 E10
30R IO_R9|LVDS52n TxFPGAe_3n TxLVDSe_3n TxLVDSe_1n IO_F7|LVDS19n IO_A11 3734 E10
T8 IO_T8|LVDS53p TxFPGAe_3p 4720 TxLVDSe_3p TxLVDSo_CLKp B7 IO_B7|LVDS20p IO_B11 B11
2724 2725 2726 R8 4721 A7 3735 C6
IO_R8|LVDS53n TxFPGAe_4n TxLVDSe_4n TxLVDSo_CLKn IO_A7|LVDS20n
47u 10n 10n TxFPGAe_4p 4722 TxLVDSe_4p 3736 C7
4V 3737 C6
3732 TxFPGAe_CLKn 4725 TxLVDSe_CLKn 3738 B6
TxFPGAe_4p TxFPGAe_CLKp 4726 TxLVDSe_CLKp 3739 B7
22R 3740 B6
3733
180R 3741 C6
3734 3742 C7
TxFPGAe_4n
5704 5705 F704 +1V2-PLL 22R 3743 C6
E 30R F705 30R E 3744 D6
3745 D7
7700-6
2729 2730 EP2C5F256C7N 3746 D6
1u0 10n 3747 B6
+3V3_FPGA Φ
3748 B7
POWER
+3V3_FPGA +3V3_FPGA 3749 B6
B1 A1
G3 A16 3750 F6
K3 VCCIO1 B15 3751 F6
R1 B2 3752 G6
7700-1 +2V5out-FPGA C8 3753 G6
EP2C5F256C7N 3703 3700 3701 4700 A15 GND C9
10K 10K 10K 4700 F10
A2 E8
CLK_OSC1 Φ C10 E9 4701 G10
F MAIN_SCL H2
CONTROL
G5
C7
E10
VCCIO2 G8
H14
F 4703 C12
4704 C12
0 CE
TxFPGAo_CLKp 3750 22R H1 M13 F706 E7 H3 4705 C12
1 STATUS
J2 H8 4706 C12
2

180R
3714
NC J1 J5 B16 H9
3 CONFIG F734 4707 C12
H16 L13 G14 J14
3751 4 CLK CONF_DONE GND
4708 C12
TxFPGAo_CLKn 22R H15 K14 VCCIO3 J3
5
TxFPGAe_CLKp 3752 22R J15 J13 R16 J8 4709 C12
6 0
J16 MSEL K12 F733 +2V5in-FPGA J9 4710 C12
7 1
180R
3713
7700-2 M10 K9 4711 C12
EP2C5F256C7N TCK
F2 TCK_FPGA M7 M8
TxFPGAe_CLKn 3753 22R F1 G1 TMS_FPGA P10 M9 4712 C12
Φ H4
DATA0 TMS
G2 TDO_FPGA 4701 P7 VCCIO4 P8 4713 D12
DCLK TDO 3702
ASDO C3 BANK1 DATA0 H5 TDI_FPGA RES T15 P9 4714 D12
10K
G nCSO F4
P1
IO_C3|ASDO
IO_F4|CSO_ IO_E3|LVDS7p
E3
E4 NC DCLK
TDI
+1V2-FPGA
T2 GND R15
R2
G 4715 D12
MAIN_SDA FPGA_BL_BOOST IO_P1|LVDS0p IO_E4|LVDS7n 4716 D12
P2 D5 I712 ambi_pwm(4) G9 T1
IO_P2|LVDS0n IO_D5|LVDS8p 4717 D12
N1 IO_N1|LVDS1p IO_E5|LVDS8n E5 RES H10 T16
AMBI_SDA N2 C1 I705 ambi_pwm(0) 2734 H7 VCCINT 4718 D12
L1 IO_N2|LVDS1n IO_C1|LVDS9p C2 ambi_pwm(1) 1n0 J7 L5
IO_L1|LVDS2p IO_C2|LVDS9n 4719 D12
L2 IO_L2|LVDS2nIO_L4|PLL1_OUTp L4 +1V2-PLL GND_PLL1 N5 4720 D12
FPGA_BL_DIMMING K4 M4 M5 4721 D12
IO_K4|LVDS3p
IO_M4|PLL1_OUTn 1
K5 IO_K5|LVDS3nIO_F3|VREFB1N0 F3 E12 2
VCCA_PLL D12
K1 J4 NC GND_PLL2 F12 4722 D12
K2 IO_K1|LVDS4nIO_J4|VREFB1N1 L3 L6 4723 C12
IO_K2|LVDS4p IO_L3 1
ambi_pwm(5) E1 IO_E1|LVDS5p IO_M1 M1 F11 2
VCCD_PLL
1
M6 4724 D12
E2 M2 GNDA_PLL E11 4725 D12
ambi_pwm(2) D3 IO_E2|LVDS5n IO_M2 M3 2
I728
H ambi_pwm(3) I713 D4
IO_D3|LVDS6p
IO_D4|LVDS6n
IO_M3
IO_P3
P3 AMBI_SCL H 4726 E12
5700 B1
5701 B1
RES 5702 C1
2700 5703 D1
1n0 7700-4 5704 E1
EP2C5F256C7N
5705 E2
Φ 7700-7
EP2C5F256C7N 7700-1 F8
BANK3 7700-2 G3
D13 M16 Φ
IO_M16|LVDS38p M15
IO_D13|LVDS29p 7700-3 B14
C14 NC
IO_M15|LVDS38n
IO_C14|LVDS29n 7700-4 H13
D16 IO_N16|LVDS39p N16
IO_D16|LVDS30p B8 H6
D15 N15 C15 J10 7700-5 B8
I G13 IO_N15|LVDS39n P16
IO_D15|LVDS30n
IO_G13|LVDS31pIO_P16|LVDS40p
C16 J6 I 7700-6 E14
G12 IO_G12|LVDS31nIO_P15|LVDS40n P15 D1 K13 7700-7 I15
H11 N14 D2 K6 F701 B2
IO_H11|LVDS32p
IO_N14|LVDS41p
J11 IO_N13|LVDS41n N13
IO_J11|LVDS32n D7 K7 F702 B2
NC F16 M12 NC NC D9 K8
IO_M12|LVDS42p N12
IO_F16|LVDS33p NC NC NC
F15 E13 N3 F703 C2
IO_N12|LVDS42n
IO_F15|LVDS33n F704 E2
G15 IO_M14|VREFB3N1 M14
IO_G15|LVDS34p E15 N4
G16 H13 F13 N6 F705 E2
IO_G16|LVDS34n
IO_H13|VREFB3N0
J12 IO_E14|PLL2_OUTp E14
IO_J12|LVDS35p F14 N7 F706 F9
H12 D14 F5 P6 F733 G9
K15 IO_H12|LVDS35n
IO_D14|PLL2_OUTn E16 G4 R6
IO_K15|LVDS36p IO_E16 F734 F9
K16 IO_K16|LVDS36n IO_L14 L14
L16 P14 I705 G4
IO_L16|LVDS37p IO_P14
L15 I712 G4
J IO_L15|LVDS37n
J I713 H2
I728 H2

H_17370_014.eps
3139 123 6273.1 010804

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 58

SSB: Audio Processor


1 2 3 4 5 6 7 8 9 1411 B3 I424 E4
2408 A4 I425 F4

AUDIO PROCESSOR 2409 A4 I426 A3

B06A 7410 F401 +8V


B06A 2410 A4
2411 A2
2412 A4
I427 C4
I428 C4
I429 C2
L78L08ACU 1
IN OUT 2413 A5 I430 C2
3

470p
1n5
+AUDIO_POWER_+12V_DISP 2414 B2 I431 D4

220u
4401 COM

25V
+12V_DISP
2415 B3 I432 D2

2439

470n
4402
A A 2416 B3

2408
2409
2417 B7

2410
+5V_D
+5V_D 2418 B7
5401 I426 F402 F403
2411
2419 C3
3402 120R +5V_AUD
+5V_SW 10u 2420 C6

2440

470n

2412

220p
2441

2442

470p

2413

220p
2443

2444

470p
2421 C7

1n5

1n5
1R0
2422 C7
5402 2423 C6
+5V_AUD
2424 D7
120R
2414 7411 2425 D7

61
62

39

12
13
10u MSP4450P-VK-E8 000 2426 D7
2415
A AH DVSUP 2427 D7
B 3p3 4 1
1411
SUP
Φ AUD_CL_OUT
70 B 2428 D6
2429 D7
18M432
XTALIN 2V4 67 MULTISTANDARD 26 0V6 AUDIO_LS_R 2430 D7
IN R 0V6
SOUND PROCESSOR 27 AUDIO_LS_L 2431 D7

3
2416 XTAL L

2
XTALOUT 2V4 68
OUT 2432 D2
28
RST_AUD
3p3
19
C
2418 2417 2433 D3
RESETQ DACM 330p 330p 2434 D3
80 29
+5V_AUD STNDBYQ SUB
100n 2419 66 2435 E3
TESTEN
69 30 2436 E3
TP SR
31 2437 F4
IIC_SCL_up I412 SL
3410 100R 2
IIC_SDA_up 3411 100R I413 3
CL
23 0V2 HP_AUDIO_OUT_R
2438 F4
RES 2446 100p DA I2C R 0V2 2439 A3
79 DACA 24 HP_AUDIO_OUT_L
C RES 2447 100p
I427 4
ADR_SEL L
6V7
+8V C 2440 A3
MOJO_I2S_OUT_SCK 1V4 RES 4408 40 2420 10u 16V 2441 A4
I428 5 CL M
MOJO_I2S_OUT_WS 1V6 RES 4407 2421 2422
WS CAPL 6V3
I414
330p 330p
2442 A4
38 2423 10u 16V
RES HDMI_SCK I429 17
A 2443 A6
CL3 I415
HDMI_WS I430 18 2444 A6
WS3
2445 E3
4409 8 78 2446 C3
IN 0
4410 9 DCTR_IO 77
OUT 1 2447 C3
10 DEL I2S
11
CL
76
3402 A1
WS SPDIF_OUT 3410 C3
MOJO_I2S_OUT_SD RES 4411 I431 7 36 3V8 I416 2424 10u 3417 100R SC1_AUDIO_OUT_R 3411 C3
1 R 3V8 I417
D HDMI_SD I432
4412 16
20
2
3
DA
SC1_OUT
L
37

3V8
2425 10u 3418 100R SC1_AUDIO_OUT_L
D 3416 D2
3417 D8
21 33 I418 2426 10u 3419 100R SC2_AUDIO_OUT_R
4
SC2_OUT
R
34 3V8 I419 2427 10u 3420 100R SC2_AUDIO_OUT_L
3418 D8
L 3419 D8
6
DA_OUT
41 3420 D8
I420 I421 1V5 63 R
SIF 2432 56p 2433 330p SC3_OUT 42 2428 2429 2430 2431 4401 A1
I422 IN1+ L 100p 100p 100p 100p
RES 3416 470R 2434 330p 64
5403 22u IN- ANA 4402 A1
2435 330p I423 65
IN2+ 4407 C3
UAB-09
2436 10u I424 2V6 56 1 4408 C3
VREFTOP
2445 100n 22 4409 D3
SC1_AUDIO_IN_R 55 32 4410 D3
R
SC1_AUDIO_IN_L 54 SC1_IN 46
L 4411 D3
47
E SC2_AUDIO_IN_R 53
R
NC 71 E 4412 D3
5401 A1
SC2_AUDIO_IN_L 52 SC2_IN 72
L
73 5402 B1
COMP_AUDIO_IN_R 51 74 5403 E2
R
COMP_AUDIO_IN_L 50 SC3_IN 75
L 7410 A3
SIDE_AUDIO_IN_R 49
7411 B4
R F401 A4
SIDE_AUDIO_IN_L 48 SC4_IN
L
F402 A4
HDMI_AUDIO_IN_R 58 F403 A5
R
HDMI_AUDIO_IN_L 57 SC5_IN
L I412 C3
VSS VREF I413 C3
I414 C6
F AGNDC A AH D 1 2
F I415 C6
45

59
60

43
44

14
15

35
25

I425
I416 D6
I417 D6
UAB-09
I418 D6
2438

100n

2437
10u I419 D6
I420 D3
I421 D4
H_17370_015.eps
3139 123 6273.1 010804 I422 D4
I423 E4

1 2 3 4 5 6 7 8 9
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 59

SSB: Audio
1 2 3 4 5 6 7 8 9 10 11
1A01 D11 FA11 E11
1A02 C11 FA12 E2

B06B AUDIO B06B


1A03 B1
2A01 B7
2A02 B9
FA13 B1
FA14 B1
FA15 B1
2A04 C6 FA16 B1
2A08 C9 FA17 B1
2A09 D5 FA18 B1
2A10 D5 FA32 F11
2A11 D3 IA01 D2
A 5A07
RES 4A01 IA40
A 2A12 D4
2A13 D8
IA02 D3
IA03 D6
+AUDIO_POWER +AUDIO_POWER_+12V_DISP
2A14 D7 IA04 D9
33R

2A46
RES 4A02 2A15 D3 IA05 D2

47n
10n

1n0

10n

1n0
2A16 E3 IA06 D3
2A17 D8 IA07 D6

RES
2A52
RES
2A50

IA41 2A18 E6 IA09 E3

2A53
2A51

2A19 E4 IA10 E2

2A47
2A20 E3 IA11 E2

47n
TO / FROM PSU

GNDSND 2A21 D7 IA12 E3


GNDSND
1A03 10R
IA25
-12V2
2A22 E3 IA13 E4
3A02 VSSA
FA13 FA14 -12V2 5A08 10u 2A23 E8 IA14 E6
B 1
2
FA15
FA17
FA16
FA18
+12V2 5A09 10u
-AUDIO_POWER
+AUDIO_POWER
GNDSND
3A01 10R
IA24
11V9
2A02
100n
B 2A24 E3 IA15 E4
3 GNDSND VDDA 2A25 E6 IA16 E6
2A26 E8 IA17 E9
440054-3 RES 2A01
2A54 100n 2A27 E6 IA18 E5
100n GNDSND 2A28 E7 IA19 E4
FA02
2A29 E3 IA20 E6
IA27 +12V2
-AUDIO_POWER 5A06 30R VSS 2A30 F6 IA21 F4
GNDSND
IA26 2A08 2A31 F7 IA22 F4
+AUDIO_POWER 5A05 30R 12V2 VDD 220u 25V 2A32 F4 IA23 D6
FA01 2A04 2A33 G5 IA24 B6
220u 25V
2A34 G5 IA25 B9
2A35 E7 IA26 C6
C GNDSND
C 2A36 F7 IA27 B9
GNDSND 2A37 D8 IA29 F10
2A38 E8 IA30 F10

VDDA VDD TO SUBWOOFER OUT 2A40 F3


2A41 G9
IA31 F10
IA33 F4
LCD PDP 1A02
*
3A03 10K 6K8
1
2A45 E7
2A46 A6
IA34 D8
IA35 D7

100n

100n
3A04 12K 22K
5A03 2 2A47 B6 IA36 E7
3A06 10K 6K8 IA34
IA23 22u 2A13 2A37 IA04 3A05 3
3A07 10K 6K8 2A50 B1 IA37 E8
3A08 12K 22K 22R 440054-3 2A51 B1 IA38 F7
220n 220n

2A09

2A10
3A11 10K 6K8 3A09 2A52 B2 IA39 F7
10R GNDSND
D 7A01 GNDSND GNDSND
2A14
470n
2A17
TO SPEAKERS D 2A53 B2
2A54 B2
IA40 A6
IA41 A6
FA05 * IA01 IA02 TDA8932T IA35
1n0

29
20
AUDIO_LS_L 3A03 2A11 1u0 1A01 3A01 B6
8
VDDA 440054-4
*
3A04 2A12
2
220p IN1P
Φ
CLASS D
VDDP
OUT1
27 IA03 2A21
1n0
FA07
1 LEFT +
3A02 B8
3A03 D2
-2V8 FA08
3A06
IA05 IA06 POWER 2 GND 3A04 D3
FA06 ** 3A07
2A15
2A16
1u0
1u0 IA09
3
-2V8
IN1N AMPLIFIER OUT2
22 IA07
EMC 2A18 IA36 GNDSND
FA10
FA11
3
4
GND
RIGHT -
3A05 D9
15 4 2V6 FA04 1n0 3A06 D2
IA10 *
3A08 2A19 -2V8
220p
IN2P DIAG
3A07 E2
14 30 2A35
AUDIO_LS_R
FA09
3A11 * IA11
2A20 1u0
IA12
-2V8
IN2N HVP1 NC GNDSND
1M0
1n0 2A45
1n0 2A28 2A23
3A08 E3
3A09 D7
2A22 100n IA13 12 19 3A12
INREF HVP2 NC 470n 1n0 3A11 E2
2A24 100n -7V6
E VSSA 3A13 39K IA15 10
OSCREF BOOT1
28 8V9 2A25
IA14
15n
GNDSND 5A04
VDD E 3A12 E6
FA12 IA20 22u 2A26 IA37 2A38 IA17 3A14
3A13 E3
ENGAGE 31 21 3V9 2A27 15n 3A14 E9
NC OSCIO BOOT2 IA16
IA18 220n 220n 22R 3A15 E6

3A29
GNDSND 11 25 3A15 1M0 3A17

47K
HVPREF STAB1 10R GNDSND 3A17 E7
-8V2
IA19 7A05 3A19 F3
2A29 100n 18 24 -1V3
VSSA DREF STAB2 BC857BW
IA33 4V7 IA38 IA30 3A26 F3
3A26 4K7 5
ENGAGE 3A27 F9
3V2 DC_PROT
3A19 IA21 3A28 F9

3A30
STANDBYn 6 2A30 2A31

47K
POWERUP 100n 1n0 FA32 3A29 E10
10K -2V6
IA22 13 3A30 F10

3A31

10K
TEST 7A06 IA31
BC847BW 3A31 F11
F EMC VSSP VSSD|HW VSS IA39
F
2A40

2A32
470n

CGND VSSA IA29 4A01 A6


1n0 3A27
7

26
23

1
16
17
32

2A36 4A02 A6
VSSA 1n0 220K GNDSND 5A03 D7
3A28 7A07 5A04 E7
GNDSND GNDSND VSS BC847BW
GNDSND 5A05 C6
100n
100n

220K
GNDSND 5A06 C8
5A07 A6

2A41
VSSA

1u0
2A33
2A34

5A08 B2
5A09 B2
GNDSND GNDSND 7A01 D4
7A05 E11
G GNDSND
GNDSND
DC-DETECTION G 7A06 F10
7A07 F10
FA01 C6
FA02 C8
FA04 E6
FA05 D2
FA06 E2
FA07 D1 1
H_17370_016.eps FA08 D1 1
3139 123 6273.1 010804 FA09 E2
FA10 D1 1

1 2 3 4 5 6 7 8 9 10 11
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 60

SSB: Headphone Ampl. & Muting


1 2 3 4 5 6 7
1901 B2
2901 A4
Personal Notes:
B06C HEADPHONE AMP & MUTING B06C
2902 A2
2904 B2
2905 B4
2907 C3
2901 2908 B5
2913 B5
A 3902
33p
120K A 2914 E2
2915 A5
RES 2916 C5
3903 HP_LOUT 3901 A3
3902 A4
I913 2902 3901 7901-1 33R 3903 A6

4
HP_AUDIO_OUT_L HPIC_LIN 2V6 TS482IDT 2915 3904 3904 A6
2 HPIC_LOUT
470n 47K 3905 B3
F901 2V6 2V6 1 6.3V 47u 33R 3906 B3
3 +5V_SW
ITV Connector E

8
3907 C3
1901 5V3 3908 B4
2908 3909 B6
1 220n 3910 C6
2 2905
3911 D2
B SC2_CVBS_MON_OUT_ITV 3
4 33p
B 3912 D4
6 5 3908 120K 3913 D4
RES 3906 2913 RES
3914 E4
3915 E4
100K 220n 3909 HP_ROUT 3916 F4
I914 7901-2 33R 3917 C4
HP_AUDIO_OUT_R 2904 3905 F904

4
HPIC_RIN 2V6 TS482IDT
2916 3910 3918 D4
6 HPIC_ROUT
470n 47K 3934 D3
2V6 2V6 7 6.3V 47u 33R 3935 E2
5

8
3937 E1

2907

470n
3907
100K 5V3
3938 E2
3940 F3
3942 F5
C C 3943 F6
4901 D3
4902 D2
6914 E2
MUTING CIRCUIT 3 6916 E3
+3V3_STBY 6919 F4
3917 7901-1 A4
1 7911
BC847BW 7901-2 B4
1K0
2 7902 D3
7911 C5
I911 3911 7912 D5
ANTI_PLOP 3 7913 D5
10K 3V3 I912 7914 E5
3918
0V 1 7912
D 7902
BC857BW 1K0
BC847BW D 7915 E5
7916 F5
4902
RES

2
7917 E3
3912

+3V3_STBY
10K

7919 E2
I919 7922 F6
3 SC1_AUDIO_MUTE_R
F901 B3
4901
RES

RES 3913 I930 F904 B3


3934 1 7913
4K7 BC847BW I911 D2
1K0 I912 D3
2
I920
I913 A1
RES 3 SC1_AUDIO_MUTE_L I914 B1
7917
BC857BW I931 I919 D6
RES RES 3914 1 I920 E6
7914
POWER_DOWN 6914 3935
3V3 RES BC847BW I921 E6
E BAT54 COL 4K7
6916
BAS316
1K0
2 E I922 F6
RES RES I921 I930 D5
2914 0V 3 SC2_AUDIO_MUTE_R I931 E5
STANDBY 3937 0V 47u 6.3V
3915 I932 I932 E5
1 7915 I933 F5
10K
RES BC847BW
7919 1K0
3938
RES

2
10K

BC847BW
I922
3 SC2_AUDIO_MUTE_L
+3V3_STBY I933
3916
1 7916
BC847BW
1K0
2 ENGAGE
BAS316
3940

6919
RES

10K

F 3942
7922 F
MUTEn 0V 10K BC847BW

3943
22K

H_17370_017.eps
3139 123 6273.1 010804

1 2 3 4 5 6 7

E_06532_012.eps
131004
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 61

SSB: YPBPR & SVHS


1 2 3 4 5 6 7 8
1601-A B6
1601-B C5
YPBPR & SVHS
B07A B07A 1601-C A5
1606 B1
1607 D6
1608 C6
1609 B6
1610 C1
PEND NEW 12NC PEND NEW 12NC 1611 C1
A 1615-2 2
SVHS A 1613 D1
1615-1 B1
3 HD_PR_IN_ITV 1601-C 1615-2 A1
PR MSP-801V1-07-01-B NI FE 1619 F1
F605 3617 HD_PR_IN F601 3600 I615
1 C_IN 2600 A7
R GND

PESD5V0S1BA
MSD-244V-131 NIDIP RES 33R 100R 2602 A2
2602

8
2603 D7
1606
RED_RED_RIGHT RES 3601 RES
75R 2600 3604 2606 B2
6610
75R
2607 C3
1601-A 2608 C3
MSP-801V1-07-01-B NI FE 2609 C7
1
2610 D3
F602 2612 D3
3
2613 D6
B 1615-1 5 F614 4
B 2614 D7
2615 E7
6 HD_PB_IN_ITV 2 2616 E7
L RES
3600 A7

1609
6604
3619 HD_PB_IN PESD5V0S1BA 3601 A2
4
PB F615 3602 C7
PESD5V0S1BA

5
F607 RES 33R
MSD-244V-131 NIDIP 2606 3603 D6
3605
1610

BLUE_WHITE_LEFT RES 3604 A7


6612 75R
I631 3605 C2
3602 Y_IN 3607 C2
3608 C3

75R
100R
RES RES 3609 C6

1608
6606 2609 3611 D2
C I610
PESD5V0S1BA
C 3612 D3
3617 A3

3609
3607 2607
COMP_AUDIO_IN_L
F608 3618 C7
PESD5V0S1BA

150R I623 220n 3619 B3


2608 3608
1611

RES 33K 3620 E6


6613 3n3 1601-B 6
4601 E5
Y 7
F604 3618 HD_Y_IN 4602 F5
4603 F7
MSP-801V1-07-01-B NI FE
33R 5601 D7
HD_Y_IN_ITV

PESD5V0S1BA
5602 E7
2610 I611 RES
3611 COMP_AUDIO_IN_R 6604 B7

RES 6611
3603 2603

1607
F609 75R 6606 C7
PESD5V0S1BA

150R I627 220n


2612 3612 6610 B2
1613

RES
D 6614 3n3 33K
D 6611 D7
6612 C2
6613 C2
FRONT_Y_CVBS_IN_T 2613 100n 5601 33R 6614 D2
+5V_SW
7601 D7
2614 100n 7602 F7

5
7601 7603 F6

RES
4601
74LVC1G3157GW F601 A7
VCC F602 B6
6 1 F604 C6
IN NO
F605 A1
FRONT_CVBS_SVHS_Y_IN 4
COM F607 B1
Y_IN
F608 C1
3 2615 100n
NC F609 D1
E GND
E F612 F1
F613 F1
RES 3620
RES
F614 B1

2
+5V_SW
ITV-Connector D 4K7
5602 33R
+5V_SW
F615 B6
I610 C4
RES
RES 2616 100n I611 D4
I615 A8

5
1619 FRONT_CVBS_SVHS_SEL 7602
HD_PR_IN_ITV 74LVC1G3157G W I623 C2
1
HD_Y_IN_ITV VCC I627 D2
2
3
HD_PB_IN_ITV 7603 6
IN NO
1 FRONT_C_IN_T I631 C8
F612 PDTC114ET
4
VGA_H SVHS_C_IN 4
5 COM
VGA_V
6
7 8 3
F613 NC
F F
4602

GND
BM06B-SRSS-TBT

2
C_IN

RES 4603 H_17370_018.eps


3139 123 6273.1 010804

1 2 3 4 5 6 7 8
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 62

SSB: I/O SCART 1&2


1 2 3 4 5 6 7 8 9 10 11 12 13
1500 C9 6523 C10
1501 C9 6524 E10

B07B IO - SCART 1 & 2 B07B


1502 C3
1503 D9
1504 C2
6525 G9
7500 G10
7502 G11
1505 C3 7503 I11
1506 D8 7504 I11
1507 D3 F510 D9
RES RES 1508 E9 F511 C2
A ITV-Connector B ITV-Connector C A 1509 D2
1510 E9
F512 D9
F513 C2
1526
SC1_B_IN 1511 D3 F514 D9
1 SC1_G_IN 1525 1512 E2 F515 C2
2 SC1_R_IN SC2_AUDIO_IN_R
3 1 1513 E9 F516 D9
SC1_FBL_IN SC2_AUDIO_IN_L 1514 E9 F517 C2
4 2
5 SC1_AUDIO_OUT_L 3 SC2_Y_CVBS_IN_ITV 1515 F9 F518 D9
6 SC1_AUDIO_OUT_R 4 SC2_C_IN_ITV 1516 E3 F519 D2
7 5 1517 E3 F520 D2
6 7
8
1518 G9 F521 D2
9 10 1519 F3 F522 D2
1520 G3 F523 F9
B B 1521 H9 F524 E2
SC1_AUDIO_MUTE_R 1522 G3 F525 E2
3503 F534 1523 H3 F526 F2
SC1_AUDIO_OUT_R SC2_AUDIO_MUTE_R 1524 H3 F527 F9

PESD5V0S1BA PESD5V0S1BA
150R 3500 I510 1525 A2 F528 F2

330p
SC2_AUDIO_OUT_R

1502

2508
1526 A1 F529 F9

RES 6518

PESD5V0S1BA PESD5V0S1BA
150R

2502

330p
1500
2502 C10 F530 H5

RES 6522
2506 C10 F531 E2
SCART 1 2508 B4 F532 E9
3507 F535 SC1_AUDIO_OUT_L 2509 D12 F534 B4
1504
2512 D10 F535 C4
F511 150R 3502 I512

2514

330p
SC1_AUDIO_MUTE_L SC2_AUDIO_OUT_L 2514 C4 F536 C4
1505
C Audio-R_out 1
C
RES 6519
150R 2515 C5 F537 D4

2506

330p
1501
2 F513 SC2_AUDIO_MUTE_L 2517 D4 F538 E5
Audio-R_in

RES 6523
2518 D12 F539 E5
Audio-L_out 3 F515
F536
SCART 2 2520 E10 F540 F5
4 3510 2515 I540 SC1_AUDIO_IN_R 2521 D5 F541 F5
F517
1506 2523 D4 F542 G4
PESD5V0S1BA

150R 220n 3506 F543 2509 I517


1507

5 SC2_AUDIO_IN_R 2524 F10 F543 C11


3511 1 F510
2517 Audio-R_out

PESD5V0S1BA
150R 220n 2525 G10 F544 D11
RES 6504

2512

3508
1503
6 F519 1n0 33K

33K
1n0
Audio-L_in 2 F512 2526 G10 I510 B11
Audio-R_in

RES 6501
7 F520 2527 F4 I512 C11
RGB-B_in 3 F514
Audio-L_out 2528 E4 I517 D12
F521
D Function_Sw 8
3514 F537 2521 SC1_AUDIO_IN_L 4F516 D 2529 F4
2530 H10
I520 D12
I528 G12
9
PESD5V0S1BA PESD5V0S1BA PESD5V0S1BA

150R 220n I541 2531 G4 I530 G10


1511

1509 5 2518 I520


3515 3512 F544
RES 6507

10 2523 SC2_AUDIO_IN_L 2533 I11 I533 H12


1n0 33K 6 F518
Audio-L_in 2534 I10 I540 C5

PESD5V0S1BA
150R 220n

1508
11 F522 2535 H3 I541 D5
RGB-G_in

2520

3513
7

33K
1n0
1512 2536 G10 I543 G11

RES 6505
12 F532
3516 F538 SC1_B_IN 8 2538 H3 I544 G12
Function_Sw
13 RES 3500 B10 I545 E11
100R
1516

3517
75R

2528 9 3502 C10 I548 I11


RES 6514

14 1510 3503 B4 I549 I12


F531 10 3550 I545
SC2_STATUS 3506 D10 I550 G4
E RGB-R_in 15
11 E 3507 C4 I551 G10

PESD5V0S1BA
F524 27K

1514

3551
16 3508 D11 I552 G11

6K8
RGB-BL_in F539 1513

RES 6524
SC1_STATUS 12 3510 C4 I553 I11
17 3518 3511 D4 I554 I12
F525
3520
1517

13
6K8

27K 3512 D10 I556 H12


RES 6520

18
14 SC2_C_IN_ITV 3513 E11 I557 F12
19 F526 3514 D4 I558 I12
Terr_CVBS_out F523 3552 I557 SC2_C_IN
15 3515 D4
20 F528 RGB-R_out/YC-C_in

PESD5V0S1BA
Video_in 3523 F540 100R 3516 E4

1515
SC1_G_IN 16 RES
3517 E4

RES 6509
21 RES 2524 3553
PESD5V0S1BA PESD5V0S1BA PESD5V0S1BA PESD5V0S1BA PESD5V0S1BA

100R 3518 E4
1519

3526

2527
75R

17 75R
RES 6515

3519 G11
F PPTV/55
18 F 3520 E4
F527 3521 G12
CVBS_out 19
+5V_SW 3522 G10
3528 F541 SC1_R_IN 20 F529 3523 F4
Video/YC-Y_in 3524 I11
RES 100R
1520

3530

2529
75R

21 3525 G10
RES 6516

3519 3538 3526 F4


15R 4K7
3528 F4
PPTV/55 2536 I551 2525 3529 H10
I543 I552 3530 G4
3532 F542 SC1_FBL_IN 220n 220n 5V2
RES I544 3521 I528 SC2_CVBS_MON_OUT 3531 H10
3V7 4502
G G
1N4148

RES 1K0 3532 G4


1522

3522
3533

6512
75R

2531
68R I5303V 1K0 3533 G4
RES 6521

7502 3535 G3

PESD5V0S1BA
RES 7500 BC857BW

1518
2526 3525 BC847B 3536 H4

RES 6525
1K0 3537 I12
1N4148
6513

I550 3538 G11


3535 68R
3540 I12
RES
3545 H4
1523

3536

2535
1K0
RES 6517

3546 H4
3555 I556 SC2_CVBS_MON_OUT_ITV
3550 E10
68R SC2_Y_CVBS_IN_ITV 3551 E10
3552 F11
H 3545 F530 SC1_CVBS_IN 3529 100R I533 SC2_Y_CVBS_IN H 3553 F11
RES 3554 I12

PESD5V0S1BA
100R RES
1524

2538 3546 2530 3555 H12


RES 6511

RES 6510
1521
75R 3531 4502 G11
75R +5V_SW
4504 I12
6501 D10
6504 D3

3524
3540

15R
6505 E10
4K7 6507 D3
2534 I553 2533 6509 F10
I548 6510 H9
220n 220n 6511 H3
I549 RES I558 3537
4504 SC1_RF_OUT_CVBS
I 7503
BC847B 1K0
I 6512 G5
6513 G5
7504 6514 E3
BC857BW
6515 F3
6516 G3
3554 I554 6517 H3
SC1_CVBS_RF_OUT 6518 C3
68R H_17370_019.eps 6519 C3
3139 123 6273.1 010804 6520 E3
6521 G3
1 2 3 4 5 6 7 8 9 10 11 12 13 6522 C10
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 63

SSB: HDMI Main


1 2 3 4 5 6 7 8 9 10 11
1N01 C1 3N18-1 D4

HDMI MAIN 1N02 G5 3N18-2 E4

B07C HDMI_INT_MAIN
+1V8SWA IN07 5N01

120R
+1V8_SW
2N03 E2
2N04 E2
2N05 F1
3N18-3 E4
3N18-4 E4
3N19 F4

100n

100n
100n
1n0

1n0
2N06 F2 3N20 F4
HDMI_RST_RX_BUF
+3V3_ANA-MUX
2N07 G1 3N21 F4

2N15

2N18

2N16

2N17

2N20
2N08 G1 3N22 G5
2N09 F2 3N23 E3
2N10 F2 3N24 G4
A A

3N35

3N36
7N01-1

4K7
4K7
SII9125CTU
2N11 E3 3N25 G1
IN06 5N02 +3V3_SW 2N12 E3 3N26 G1
+3V3SWA
FN01 MAIN 2N13 F4 3N27 E2
HDMI-MUX_TSCL 4N03 102 55 120R

100n

100n
INT

1n0
2N14 G4 3N33 B7

1n0

1n0

1n0

1n0

1n0

1n0

1n0
76
FN02
HDMI-MUX_TSDA 4N04 100 77 2N15 A9 3N34 B5
RESET
+3V3_ANA-MUX 82 NC 2N16 A9 3N35 A3

2N25

2N28

2N31

2N61

2N26

2N29

2N32

2N62

2N27

2N30
RSVDNC
34 83
33
DSCL0
84
2N17 A10 3N36 A3
DSDA0 2N18 A9 3N37 B3
98 5N03

3N37

3N38
29 2N20 A10 3N38 B3

4K7
7N01-2

4K7
DSCL1 120R +3V3_SW
3N33 SII9125CTU +3V3SWB IN09
28 99 2N25 A9 3N39 B5
DSDA1 RSVDL
2N26 A10 3N40 B5

100n
FN03 4K7

1n0
HDMI-SIDE_TSCL 4N05 3N39 100R 27 16 37

AVCC18
3N40 100R 26
CSCL 0
15
NC
54
2N27 A10 4N01 D4
FN04 CSDA 1 NC 2N28 A9 4N02 D4
HDMI-SIDE_TSDA 4N06 14 3N01 33R HDMI_Cb(0) 72

2N66

2N33
3N34 2
105 13 HDMI_Cb(1) 36 2N29 A10 4N03 A4
B IIC_SCL_SIDE
IIC_SDA_SIDE
4K7
CI2CA 3
4
10
3N03
3N02-1 1
33R
8 33R HDMI_Cb(2) 41 38 B 2N30 A11 4N04 A4
101 9 3N02-2 2 7 33R HDMI_Cb(3) 45 42 5N04 +1V8_SW 2N31 A9 4N05 B4
NC SCDT 5 +1V8SWB IN10
8 3N02-3 3 6 33R HDMI_Cb(4) 49 46
6 2N32 A10 4N06 B4

AGND

AVCC33
Pend New 12NC +5VHDMI-MUX_TPWR 4N07 35 7 3N02-4 4 5 33R HDMI_Cb(5) 53 50 120R

100n
R0PWR5V 7 2N33 B10 4N07 B4

1n0
+5VHDMI-SIDE_TPWR 4N08 30 3 3N08-1 1 8 33R HDMI_Cb(6) 59 56
R1PWR5V 8
TO / FROM SIDE I/O 2 3N08-2 2 7 33R HDMI_Cb(7) 63 60 2N34 C9 4N08 B4
9
HDMI-MUX_TXC+ 40 1 3N08-3 3 6 33R HDMI_Cb(8) 67 64 2N35 C10 5N01 A11

2N34

2N36
+ 10
1N01 HDMI-MUX_TXC- 39 R0XC 144 3N08-4 4 5 33R HDMI_Cb(9) 71 68 2N36 C10 5N02 A11
FI-RE21S-HF-R1500 - 11
141
HDMI-MUX_TX0+ 44 Q
12
140 NC
93 96
2N37 C11 5N03 A11
1 NC + 13 DGND XTALVCC IN11 5N05 +1V8_SW
HDMI-SIDE_TXC- HDMI-MUX_TX0- 43 R0X0 139 NC
3N05 33R HDMI_Y(0) +1V8SWC 2N38 C9 5N04 B11
2 - 14
138 3N07 33R HDMI_Y(1) 11 92 120R 2N39 C9 5N05 C11

100n

100n

100n
3 15 HDMI_Y(2) DVCC18

1n0

1n0
4
HDMI-SIDE_TXC+ HDMI-MUX_TX1+ 48
+ 16
135 3N04-1 1 8 33R 23 2N40 C11 5N06 C11
HDMI-SIDE_TX0- HDMI-MUX_TX1- 47 R0X1 134 3N04-2 2 7 33R HDMI_Y(3) 79 12
C 5 - 17
133 3 6 33R HDMI_Y(4) 90 24 C 2N41 D10 5N07 D11

CGND
3N04-3

POWER
2N42 D9 5N08 D11

2N38

2N39

2N35

2N40

2N37
6 18 HDMI_Y(5)
HDMI-SIDE_TX0+ HDMI-MUX_TX2+ 52 132 3N04-4 4 5 33R 106 25
7 + 19 HDMI_Y(6) 2N43 D10 5N09 E11
HDMI-SIDE_TX1- HDMI-MUX_TX2- 51 R0X2 129 3N06-1 1 8 33R 118 80

CVCC18
8 - 20
128 3N06-2 2 7 33R HDMI_Y(7) 130 91 5N06 +1V8_SW 2N44 D10 7N01-1 A6
9 21 3N06-3 HDMI_Y(8) +1V8SWD IN12
HDMI-SIDE_TX1+ HDMI-SIDE_TXC+ 58 127 3 6 33R 142 107 2N45 D9 7N01-2 B8
10 + 22 HDMI_Y(9)
HDMI-SIDE_TX2- HDMI-SIDE_TXC- 57 R1XC 126 3N06-4 4 5 33R 119 120R 2N46 D10 7N01-3 F7

100n

100n
11 - 23

1n0

1n0

1n0

1n0

1n0

1n0

1n0
123 4 131
12
HDMI-SIDE_TX2+ HDMI-SIDE_TX0+ 62
24
122
NC
17 143
2N47 D11 7N07 F3
13 + 25 NC 2N48 D9 FN01 A4
HDMI-SIDE_CEC_A HDMI-SIDE_TX0- 61 R1X0 121 3N09 33R HDMI_Cr(0) 31

2N42

2N45

2N48

2N41

2N43

2N46

2N49

2N44

2N47
14 - 26
120 3N10 33R HDMI_Cr(1) 73 6 2N49 D10 FN02 A4

IOGND
15 NC 27
HDMI-SIDE_TSCL HDMI-SIDE_TX1+ 66 117 3N11-1 1 8 33R HDMI_Cr(2) 87 18 2N50 D10 FN03 B4
16 + 28
HDMI-SIDE_TSDA HDMI-SIDE_TX1- 65 R1X1 116 3N11-2 2 7 33R HDMI_Cr(3) 103 32 2N51 E9 FN04 B4
17 - 29
115 3N11-3 3 6 33R HDMI_Cr(4) 112 74

IOVCC33
18 +5VHDMI-SIDE_TPWR 30 IN13 5N07 +3V3_SW 2N52 E10 IN06 A11
HDMI-SIDE_TX2+ 70 114 3N11-4 4 5 33R HDMI_Cr(5) 124 88 +3V3SWC
D 19
HDMI-SIDE_TX2- 69
+
R1X2
31
111 3N12-1 1 8 33R HDMI_Cr(6) 136 104 120R
D 2N53 E10 IN07 A11

100n
20 - 32
HDMI_HOTPLUG_RESET 110 3N12-2 2 7 33R HDMI_Cr(7) 113 2N54 E9 IN09 B11
21 NC 33
23 22 95 109 3N12-3 3 6 33R HDMI_Cr(8) 145 125 2N55 E10 IN10 B11
IN 34 GND_HS
25 24 108 3N12-4 4 5 33R HDMI_Cr(9) 137 2N56 E11 IN11 C11

2N50
RES
XTAL 35
27 26 2N67 +3V3_SW 4N01 4N02 94
100n OUT
19 3N13 HDMI_DE 97
2N58 E10 IN12 C11
29 28 DE 33R REGVCC 5N08 +3V3_SW
IN14 2N59 E10 IN13 D11
3N18-1 1 8 33R 89 +3V3SWD
NC MCLK
+3V3_SW +3V3_SW 20 3N14 33R HDMI_H 120R 2N60 F9 IN14 D11

100n

100n
HSYNC

1n0

1n0

1n0

1n0

1n0

1n0

1n0
3N18-4 4 5 33R 86 2N61 A9 IN15 E11
SCK
21 3N15 33R HDMI_V 2N62 A10 IN16 F2
VSYNC
3N18-3 3 6 33R 85

2N51

2N54

2N63

2N59

2N52

2N55

2N58

2N53

2N56
WS 2N63 E9 IN17 F2
3N27

3N23

22
1R0

1R0

EVNODD NC 2N64 F10 IN18 F1


3N18-2 2 7 33R 81
SD
5 3N16 HDMI_VCLK 2N66 B9 IN19 F2
E NC
78
SPDIF
ODCK 33R
E 2N67 D1 IN20 G2
5N09 +3V3_SW 3N01 B7 IN21 G1
IN15
47u 6.3V

75 +3V3SWE
47u 6.3V

MUTEOUT 3N02-1 B7
2N03

2N04

2N11

2N12
100n

100n

120R

100n
1n0
3N02-2 B7
33R

33R

33R

3N02-3 B7
3N19

3N20

3N21

3N02-4 B7

2N60

2N64
166
167
168
169
170
7N01-3 3N03 B7
SII9125CTU
RES 3N04-1 C7
7N07 VIA 3N04-2 C7
13
47u 6.3V

UDA1334ATS 146 159


4

3N04-3 C7
2N05

2N06
100n

VDDD

147 160
VDDA

Φ VIA
HDMI_SCK

HDMI_WS

1 148 161 3N04-4 C7


HDMI_SD

DAC BCK
149 162
F IN16
12
VREF_DAC SYSCLK
6 150
VIA VIA
163 F 3N05 C7
3N06-1 C7
151 164
PLL1 3N06-2 C7
IN17 152 165
2N09 10u
14 3 3N06-3 C7
IN18 VOUTL DATAI VIA
2N13 3N06-4 C7
2N10 10u 16 10 153 3N07 C7
154
155
156
157
158
VOUTR PLL0
28M322

IN19 18p 3N08-1 B7


3N24

1N02

11
1M0
220R

220R

0 3N08-2 B7
9 SFOR 7 3N22
DEEM 1 2N14
3N08-3 B7
CLKOUT
2 3N08-4 C7
3N25

3N26

WS 18p 33R
3N09 D7
8
VSSD

3N10 D7
VSSA

HDMI_AUDIO_IN_R MUTE
IN20 3N11-1 D7
G G 3N11-2 D7
5

15

HDMI_AUDIO_IN_L IN21
3N11-3 D7
3N11-4 D7
10n

10n

3N12-1 D7
3N12-2 D7
2N07

2N08

3N12-3 D7
3N12-4 D7
3N13 D7
H_17370_020.eps 3N14 E7
3139 123 6273.1 010804 3N15 E7
3N16 E7

1 2 3 4 5 6 7 8 9 10 11
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 64

SSB: HDMI Switch


1 2 3 4 5 6 7 8 9 10 11
1M01 A1 IM13 C7

HDMI SWITCH 1M02 D1 IM14 E7

B07D B07D
RES 1M03 F1 IM15 E7
7M01
LF18CD 2M01 B10
RES 4M01 2M02 B10
FM16
1 3
+3V3_STBY IN OUT +1V8_STBY 2M03 B10
A COM A 2M04 B10

100u 16V
2M05 B10

2M12

2M11
100n
RES

RES
1M01 2M06 B10

2
10029449-002 A 2M07 D10
RX2+A +3V3_ANA-MUX
1 2M08 D10
2 FM05 2M09 D10
RX2-A
3 2M10 D10
RX1+A +1V8_ANA-MUX
4 5M02

3M33
4M02 2M11 A10

RES

4K7
5 +1V8_SW
RX1-A 2M12 A9

100n

100n

100n

100n

100n

100n

100n
6 220R FM17

10u

10u
RX0+A 4M03
7 2M15 C10
HDMI_INT_MUX
8 2M16 C10
RX0-A 3M20 100R IIC_SCL_up

2M01

2M02

2M03

2M04

2M05

2M06

2M19

2M20

2M21
9 2M17 C10
RXC+A 3M21 100R IIC_SDA_up
B 10
11
RXC-A
HDMI_RST_MUX B 2M19 B11
2M20 B11
12
3M35 47K +5V_SW
13 +5VHDMI_A 2M21 B11
3M36 47K
14 NC 3M03 C2
FM01 DDC_SCLA 5M03 +1V8_DIG-MUX
15 RES 4M04 3M04 C3
FM02 DDC_SDAA +1V8_STBY
16

3M18
RES
3M07 F2

4K7

100n

100n
17 220R FM18

10u
FM03 +5VHDMI_A RES 4M05 3M08 F3
18 IM07 +5VHDMI-MUX_TPWR
HPD_RESET_A IM12
19 3M09 D4
21 20

2M15

2M16

2M17
3M10 F4
23 22
3M11 G4

3M34
+3V3_ANA-MUX +1V8_ANA-MUX +1V8_DIG-MUX

4K7
3M13 H2
DDC_RESET
3M03
100R

7M07 3M14 E7
C IM01 3M04
SII9185CTU
C 3M15 E7

23
43
55
63

17
29
37
49
57
69

33
73
RES

6
5M01 +3V3_ANA-MUX
7M02 2K2
4M12 4M10 3M18 B7
HDMI 1 IM02 AVCC33 AVCC18 DVCC18 +3V3_SW
BC847BW 3M20 B5

100n

100n
220R FM19

10u

10u
13 RES RES 3M21 B5
RESET Φ 3M32 IM13 6M08 +3V3_ANA-MUX +3V3_STBY RES 4M11
HDMI-SIDE_CEC_A 3M31 H3
HDMI A 54
14 82K BAT54 COL 3M32 C7

2M07

2M08

2M09

2M10
LSDA CEC
1M02 B EPSEL0
SWITCH
D
53 CEC_D
10029449-002 DDC_SCLA 3M33 B5
EPSEL1 3M34 C7
RX2+B 15 DDC_SCLB
1 LSCL
2 FM06
DDC_SCLC 3M35 B2
RX2-B DDC_SDAA 3M36 B2
3
RX1+B 79 31 DDC_SDAB
4 I2CADDR 0 3M37 E2
51 DDC_SDAC
D 5
6
RX1-B
RX0+B
35
TPWR
I2CSEL
DSCL 1
2
71 RES 6M02
4M09
BAT54 COL +5V_SW
+5VHDMI_A
D 3M38 E2
3M39 G2
7 3M09 INT
75 30 RES 6M03 BAT54 COL 3M40 G2
8 RSVDL 0
RX0-B 50 +5V_SW 4M01 A3
9 4K7 DSDA 1
RXC+B RXC+A 19 70 RES 6M06 BAT54 COL
10 C+ 2 4M02 B9
RXC-A 18 4M08 +5VHDMI_B
11 C- 4M03 B9
RXC-B RX0+A 22 32 RES 6M07 BAT54 COL
12 0+ 0 4M04 B9
3M37 47K RX0-A 21 52 +5V_SW
13 +5VHDMI_B 0- RPWR 1
3M38 47K RX1+A 25 R0X 72 RES 6M01 BAT54 COL 4M05 C9
14 NC 1+ 2
FM07 DDC_SCLB RX1-A 24 4M07 +5VHDMI_C 4M07 E7
15 1- 6M04 BAT54 COL
FM08 DDC_SDAB RX2+A 28 16
16
27
2+ 0
RES HPD_RESET_A
4M08 D7
RX2-A 36
17 2- HPD 1 4M09 D7
FM10 +5VHDMI_B 56 HPD_RESET_B
18 IM08 2 4M10 C9
HPD_RESET_B RXC+B 39 76 HPD_RESET_C
E 19
21 20
23 22
RXC-B
RX0+B
38
42
C+
C-
HPDIN
78
IM14 3M14
100R
HDMI_HOTPLUG_RESET
HDMI-MUX_TSCL
E 4M11 C9
4M12 C7
0+ TSCL
RX0-B 41 77 HDMI-MUX_TSDA
45
0- TSDA 5M01 C9
RX1+B R1X IM15
1+ 3M15 5M02 B9
RX1-B 44 100R
1-
RX2+B 48 5M03 B9
2+
IM03 RX2-B 47
2-
6M01 E7
DDC_RESET 10 HDMI-MUX_TXC+
C+ 6M02 D7
3M07
100R

RXC+C 59 11 HDMI-MUX_TXC-
3M08 C+ C- 6M03 D7
RXC-C 58 7 HDMI-MUX_TX0+
2K2 C- 0+ 6M04 E7
7M04 RX0+C 62 8 HDMI-MUX_TX0-
HDMI 2 IM04 BC847BW RX0-C 61
0+
TX
0-
4 HDMI-MUX_TX1+ 6M06 D7
0- 1+
RX1+C 65
1+
R2X
1-
5 HDMI-MUX_TX1- 6M07 D7
RX1-C 64 1 HDMI-MUX_TX2+ 6M08 C7
F 1M03
10029449-002
C RX2+C
RX2-C
68
67
1-
2+
2+
2-
2 HDMI-MUX_TX2- F 7M01 A9
2- 7M02 C2
RX2+C
1 3M10 7M04 F2
FM15 +1V8_ANA-MUX 12
2 EXT_SWING
3
RX2-C
470R 7M07 C5
RX1+C AGND DGND
4 7M09 H2
3
9
20
26
40
46
60
66
80

34
74

5 RES FM01 B2
RX1-C
6 3M11 FM02 B2
RX0+C
7
FM03 C2
8 1K0
9
RX0-C FM05 A1
RXC+C FM06 D1
10
11 FM07 E2
RXC-C
G 12
13
3M39
3M40
47K
47K
+5VHDMI_C G FM08 E2
FM10 E2
14 NC
15
FM11 DDC_SCLC FM11 G2
FM12 DDC_SDAC FM12 G2
16
17
FM13
FM13 G2
18 +5VHDMI_C
IM09 HPD_RESET_C FM15 F1
19 FM16 A10
21 20
23 22 FM17 B11
FM18 B11
FM19 C11
IM01 C3
IM10
IM02 C2
H DDC_RESET
H IM03 E3
3M13
100R

3M31 IM04 F2
2K2 IM07 C2
HDMI 3 7M09 IM08 E2
IM11 BC847BW
H_17370_021.eps IM09 G2
3139 123 6273.1 010804 IM10 H3
IM11 H2
IM12 C7
1 2 3 4 5 6 7 8 9 10 11
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 65

SSB: LVDS Connector


1 2 3 4 5 6 7 8 9 10
1R01 C5 IR06 D9
1R02 B2 IR08 C9

B07E LVDS CONNECTOR 1R03 B2


1R04 C2
LGE FHP 1080p 1R05 C2
SDI
1R06 D2
1R07 D2
A CTRL-DISP1
RESET
Semi standby : H
A 1R08 D2
Normal and off : L 1R09 E2
8 Bit Single 10 Bit Single 8 Bit Dual 10 Bit Dual
1R10 E2

*
LVDS LVD S LVD S LVDS
1R02 -- -- Y Y DISPEN CPU-GO 1R11 F2
FROM FPGA 1R03 -- -- Y Y CTRL-DISP2(LCD_PWR_on) On time : H On time : H 1R12 F2
1R04 -- -- Y Y
Off time : Don’t care Off time : Don’t care
1R13 G2
1R05 -- -- Y Y
PDWIN 2R01 F5
TxLVDSe_0n LVDSe_0n 1R06 -- -- Y Y
CTRL-DISP3(Rev_Standby) On time : H 2R02 F5
1R07 -- -- -- Y

DLW21S
Off time : Don’t care 2R10 D8

1R02
1R08 Y Y Y Y
1R09 Y Y Y Y PDP-GO 2R11 C10
TxLVDSe_0 p LVDSe_0p 1R10 Y Y Y Y On time : H 2R12 C10
1R11 Y Y Y Y
CTRL-DISP4 Semi standby : L MAIN_RESET
B TxLVDSe_1 n LVDSe_1n 1R12 Y Y Y Y Off time : Don’t care B 2R20 G9
2R21 G9
1R13 -- Y -- Y

DLW21S
1R03 2R23 G9
2R24 G9
TxLVDSe_1 p LVDSe_1p 3R10 C8
+5V_STANDB Y +12V_DISP
3R12 D8
TxLVDSe_2 n LVDSe_2n +VDISP
DLW21S 5R01 RES 3R13 D9
IR08
7R05 3R25 F4
1R04

1R01 220R
FX15S-41S-0.5SH SI4835BDY 3R26 F4
5R02 FR01

4R01

4R02
4R03
4R04
TxLVDSe_2 p LVDSe_2p 48 49 3R35 F9
+VDISP
46 47 220R
TxLVDSe_CLKn 44 45 12V1 3R48 F9
LVDSe_CLKn 5R03

RES
42 43 3R49 F9
C C
DLW21S

3R50 F9
1R05

41 IR01 220R
40
3R51 F9
TxLVDSe_CLKp LVDSe_CLKp FR02 3R52 F9

47u 16V
39

2R11

2R12

100n
38 3R10 3R53 F9
TxLVDSe_3 n LVDSe_3n CTRL_DISP1
CTRL_DISP2
37 3R54 F9
DLW21S

36 47K 4R01 C8
1R06

CTRL_DISP3
35 6R02
CTRL_DISP4 4R02 C8
34
TxLVDSe_3 p LVDSe_3 p 4R03 C8
33 BZX384-C5V6
TxLVDSe_4 n LVDSe_4 n FR03 4R04 C8
32
FR04
FR05
31 3R12 IR02 2R10 4R05 G9
DLW21S

30 4R06 G9
1R07
RES

FR06 IR06
29 47R 1u0
FR07 4R07 G9
D TxLVDSe_4 p LVDSe_4 p FR08
28 3R13
47K D 4R08 G9
TxLVDSo_0 n LVDSo_0 n FR09
27
26 VDISP-SWITCH 5R01 C9
FR10
25 IR04 5R02 C9
7R07
DLW21S

24 0V 5R03 C9
1R08

23 PDTC114ET
FR11
22
6R02 D8
TxLVDSo_0 p LVDSo_0p FR12 7R05 C9
21 3V2
TxLVDSo_1 n LVDSo_1n FR13
20
19
LCD 7R07 D8
FR01 C10
FR14
DLW21S

18 FR02 C5
1R09

FR15
17
FR16
16
FR03 D4
TxLVDSo_1 p LVDSo_1p FR17 FR04 D4
<,,,annot_deleted,> 15 +3V3_SW
FR18
E E

RES
FR05 D4

RES
RES

RES
14
TxLVDSo_2 n LVDSo_2n FR19
FR20
13 FR06 D4
DLW21S

12 FR07 D4
1R10

4K7

4K7

4K7

4K7
11
FR21
10
FR08 D4
TxLVDSo_2 p LVDSo_2p FR22 SINGLE FR09 D4
9
8
LVD S FR10 D4
TxLVDSo_CLKn LVDSo_CLKn FR31
FR11 D4

3R48

3R49

3R50

3R51
7
FR30
DLW21S

6 FR24

*
3R35 FR12 D4
1R11

FR29 CTRL_DISP1_up CTRL_DISP1


5
FR28
100R
FR13 E4
4
TxLVDSo_CLKp
<,,,annot_deleted,> LVDSo_CLKp FR23 FR14 E4

*
3 3R52 FR25
BOLT_ON_SCL 3R25 100R LCD_PWR_ON CTRL_DISP2
2 FR15 E4
TxLVDSo_3 n LVDSo_3n BOLT_ON_SDA 3R26 100R
1 100R FR16 E4
F F
DLW21S

FR26

*
IR05 3R53 FR17 E4
1R12

STANDBYn CTRL_DISP3
FR18 E4
100p

100p

100R
TxLVDSo_3 p LVDSo_3p FR19 E4
FR27

*
CTRL_DISP4_up 3R54 CTRL_DISP4
FR20 E4
TxLVDSo_4 n LVDSo_4 n
100R FR21 E4
2R02

2R01
RES

RES
DLW21S

FR22 E4

*
1R13
RES

LCD PDP
3R35 -- 100R FR23 F5

100p

100p

100p

100p
TxLVDSo_4 p LVDSo_4 p 3R52 -- 100R FR24 F10

4R05

4R06

4R07

4R08
3R53 -- 100R FR25 F10
3R54 -- 100R
FR26 F10

2R20

2R21

2R23

2R24
4R05

*
*
*
*
Y --
4R06 Y -- FR27 F10

G 4R07
4R08
Y
Y
--
--
PDP G FR28 F4
FR29 F4
FR30 F4
FR31 E4
IR01 C8
H_17370_022.eps IR02 D8
3139 123 6273.1 010804 IR04 D9
IR05 F8
1 2 3 4 5 6 7 8 9 10
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 66

SSB: SRP List


Netname Schematic A(9) B04 (2x) HDMI_Cb(1) B07C (1x) IBO_CVBS_IN B04 (1x) MIU_DATA(11) B03D (1x) SC2_AUDIO_MUTE_R B06C (1x) TDA_DAT(7) B03B (1x) VIF2 B02 (2x)
A_MICLK B03B (2x) HDMI_Cb(2) B05C (1x) IBO_CVBS_IN B05A (1x) MIU_DATA(12) B03C (1x) SC2_AUDIO_MUTE_R B07B (1x) TDA_SYNC B03A (1x) VIM_IBO B02 (1x)
+12V_DISP B01A (1x) A_MISTRT B03B (2x) HDMI_Cb(2) B07C (1x) IBO_G_IN B03E (1x) MIU_DATA(12) B03D (1x) SC2_AUDIO_OUT_L B06A (1x) TDA_SYNC B03B (1x) VIM_IBO B03A (1x)
+12V_DISP B01B (2x) A_MIVAL B03B (2x) HDMI_Cb(3) B05C (1x) IBO_G_IN B05A (1x) MIU_DATA(13) B03C (1x) SC2_AUDIO_OUT_L B07B (1x) TDA_VALID B03A (1x) VIP_IBO B02 (1x)
+12V_DISP B02 (1x) A_MOCLK B03B (2x) HDMI_Cb(3) B07C (1x) IBO_IRQ B03C (1x) MIU_DATA(13) B03D (1x) SC2_AUDIO_OUT_R B06A (1x) TDA_VALID B03B (1x) VIP_IBO B03A (1x)
+12V_DISP B04 (1x) A_MOSTRT B03B (2x) HDMI_Cb(4) B05C (1x) IBO_IRQ B04 (2x) MIU_DATA(14) B03C (1x) SC2_AUDIO_OUT_R B07B (1x) TDI_FPGA B05D (1x) VSS B06B (3x)
+12V_DISP B06A (1x) A_MOVAL B03B (2x) HDMI_Cb(4) B07C (1x) IBO_R_IN B03E (1x) MIU_DATA(14) B03D (1x) SC2_C_IN B05A (1x) TDI_FPGA B05E (1x) VSSA B06B (5x)
+12V_DISP B07E (1x) AD(0) B04 (2x) HDMI_Cb(5) B05C (1x) IBO_R_IN B05A (1x) MIU_DATA(15) B03C (1x) SC2_C_IN B07B (1x) TDO_FPGA B05D (1x) WAGC_SW B02 (1x)
+1V2_ADC B05C (5x) AD(0) B05A (1x) HDMI_Cb(5) B07C (1x) IF_AGC_IBO B02 (1x) MIU_DATA(15) B03D (1x) SC2_C_IN_ITV B07B (2x) TDO_FPGA B05E (1x) WAGC_SW B04 (1x)
+1V2_CORE B05C (2x) AD(0:7) B04 (2x) HDMI_Cb(6) B05C (1x) IF_AGC_IBO B03A (1x) MIU_DATA(2) B03B (1x) SC2_CVBS_MON_OUT B05A (1x) TMS_FPGA B05D (1x) WR B04 (1x)
+1V2_PLL B05C (4x) AD(1) B04 (2x) HDMI_Cb(6) B07C (1x) IF_ATV B02 (2x) MIU_DATA(2) B03C (1x) SC2_CVBS_MON_OUT B07B (1x) TMS_FPGA B05E (1x) WR B05A (1x)
+1V2_SW B01B (3x) AD(1) B05A (1x) HDMI_Cb(7) B05C (1x) IIC_SCL B02 (1x) MIU_DATA(2) B03D (1x) SC2_CVBS_MON_OUT_ITV B06C (1x) TS_CLK B03B (1x) WX_AVCC B05A (2x)
+1V2_SW B03C (2x) AD(2) B04 (2x) HDMI_Cb(7) B07C (1x) IIC_SCL B04 (1x) MIU_DATA(3) B03B (1x) SC2_CVBS_MON_OUT_ITV B07B (1x) TS_CLK B03C (1x) WX_BA0 B05B (2x)
+1V2_SW B05C (1x) AD(2) B05A (1x) HDMI_Cb(8) B05C (1x) IIC_SCL B05A (1x) MIU_DATA(3) B03C (1x) SC2_STATUS B04 (1x) TS_DATA(0) B03B (1x) WX_BA0 B05C (1x)
+1V2_SW B05E (1x) AD(3) B04 (2x) HDMI_Cb(8) B07C (1x) IIC_SCL B07C (1x) MIU_DATA(3) B03D (1x) SC2_STATUS B07B (1x) TS_DATA(0) B03C (1x) WX_BA1 B05B (2x)
+1V2-FPGA B05E (2x) AD(3) B05A (1x) HDMI_Cb(9) B05C (1x) IIC_SCL_SIDE B04 (2x) MIU_DATA(4) B03B (1x) SC2_Y_CVBS_IN B05A (1x) TS_DATA(0:7) B03C (1x) WX_BA1 B05C (1x)
+1V2-PLL B05E (2x) AD(4) B04 (2x) HDMI_Cb(9) B07C (1x) IIC_SCL_up B02 (1x) MIU_DATA(4) B03C (1x) SC2_Y_CVBS_IN B07B (1x) TS_DATA(1) B03B (1x) WX_CAS# B05B (2x)
+1V8_ANA-MUX B07D (3x) AD(4) B05A (1x) HDMI_Cr(0) B05C (1x) IIC_SCL_up B03C (1x) MIU_DATA(4) B03D (1x) SC2_Y_CVBS_IN_ITV B07B (2x) TS_DATA(1) B03C (1x) WX_CAS# B05C (1x)
+1V8_DIG-MUX B07D (2x) AD(5) B04 (2x) HDMI_Cr(0) B07C (1x) IIC_SCL_up B04 (2x) MIU_DATA(5) B03B (1x) SDRAM_ADDR(0) B03C (1x) TS_DATA(2) B03B (1x) WX_CLKE B05B (2x)
+1V8_STBY B07D (2x) AD(5) B05A (1x) HDMI_Cr(1) B05C (1x) IIC_SCL_up B05D (1x) MIU_DATA(5) B03C (1x) SDRAM_ADDR(0) B03D (1x) TS_DATA(2) B03C (1x) WX_CLKE B05C (1x)
+1V8_SW B01B (1x) AD(6) B04 (2x) HDMI_Cr(1) B07C (1x) IIC_SCL_up B06A (1x) MIU_DATA(5) B03D (1x) SDRAM_ADDR(0:14) B03C (1x) TS_DATA(3) B03B (1x) WX_CS0# B05B (2x)
+1V8_SW B03A (2x) AD(6) B05A (1x) HDMI_Cr(2) B05C (1x) IIC_SCL_up B07D (1x) MIU_DATA(6) B03B (1x) SDRAM_ADDR(0:14) B03D (1x) TS_DATA(3) B03C (1x) WX_CS0# B05C (1x)
+1V8_SW B03E (1x) AD(7) B04 (2x) HDMI_Cr(2) B07C (1x) IIC_SDA B02 (1x) MIU_DATA(6) B03C (1x) SDRAM_ADDR(1) B03C (1x) TS_DATA(4) B03B (1x) WX_DQM0 B05B (1x)
+1V8_SW B04 (1x) AD(7) B05A (1x) HDMI_Cr(3) B05C (1x) IIC_SDA B04 (1x) MIU_DATA(6) B03D (1x) SDRAM_ADDR(1) B03D (1x) TS_DATA(4) B03C (1x) WX_DQM0 B05C (1x)
+1V8_SW B07C (4x) ALE_EMU B04 (1x) HDMI_Cr(3) B07C (1x) IIC_SDA B05A (1x) MIU_DATA(7) B03B (1x) SDRAM_ADDR(10) B03C (1x) TS_DATA(5) B03B (1x) WX_DQM1 B05B (1x)
+1V8_SW B07D (1x) ALE_EMU B05A (1x) HDMI_Cr(4) B05C (1x) IIC_SDA B07C (1x) MIU_DATA(7) B03C (1x) SDRAM_ADDR(10) B03D (1x) TS_DATA(5) B03C (1x) WX_DQM1 B05C (1x)
+1V8SWA B07C (1x) ambi_pwm(0) B05D (1x) HDMI_Cr(4) B07C (1x) IIC_SDA_SIDE B04 (2x) MIU_DATA(7) B03D (1x) SDRAM_ADDR(11) B03C (1x) TS_DATA(6) B03B (1x) WX_DQM2 B05B (1x)
+1V8SWB B07C (1x) ambi_pwm(0) B05E (1x) HDMI_Cr(5) B05C (1x) IIC_SDA_up B02 (1x) MIU_DATA(8) B03C (1x) SDRAM_ADDR(11) B03D (1x) TS_DATA(6) B03C (1x) WX_DQM2 B05C (1x)
+1V8SWC B07C (1x) ambi_pwm(1) B05D (1x) HDMI_Cr(5) B07C (1x) IIC_SDA_up B03C (1x) MIU_DATA(8) B03D (1x) SDRAM_ADDR(12) B03C (1x) TS_DATA(7) B03B (1x) WX_DQM3 B05B (1x)
+1V8SWD B07C (1x) ambi_pwm(1) B05E (1x) HDMI_Cr(6) B05C (1x) IIC_SDA_up B04 (2x) MIU_DATA(9) B03C (1x) SDRAM_ADDR(12) B03D (1x) TS_DATA(7) B03C (1x) WX_DQM3 B05C (1x)
+2V5_SW B01B (3x) ambi_pwm(2) B05D (1x) HDMI_Cr(6) B07C (1x) IIC_SDA_up B05D (1x) MIU_DATA(9) B03D (1x) SDRAM_ADDR(13) B03C (1x) TS_SYNC B03B (1x) WX_DQS0 B05B (1x)
+2V5_SW B05B (1x) ambi_pwm(2) B05E (1x) HDMI_Cr(7) B05C (1x) IIC_SDA_up B06A (1x) MIU_OEN B03B (1x) SDRAM_ADDR(13) B03D (1x) TS_SYNC B03C (1x) WX_DQS0 B05C (1x)
+2V5_SW B05E (1x) ambi_pwm(3) B05D (1x) HDMI_Cr(7) B07C (1x) IIC_SDA_up B07D (1x) MIU_OEN B03C (1x) SDRAM_ADDR(14) B03C (1x) TS_VALID B03B (1x) WX_DQS1 B05B (1x)
+2V5_VDDMQ B05B (5x) ambi_pwm(3) B05E (1x) HDMI_Cr(8) B05C (1x) INT B04 (1x) MIU_OEN B03D (1x) SDRAM_ADDR(14) B03D (1x) TS_VALID B03C (1x) WX_DQS1 B05C (1x)
+2V5_VDDMQ B05C (2x) ambi_pwm(4) B05D (1x) HDMI_Cr(8) B07C (1x) INT B05A (1x) MIU_RDY B03B (1x) SDRAM_ADDR(2) B03C (1x) TXD0 B03C (1x) WX_DQS2 B05B (1x)
+2V5in-FPGA B05E (2x) ambi_pwm(4) B05E (1x) HDMI_Cr(9) B05C (1x) ITV_SPI_CLK B04 (2x) MIU_RDY B03C (1x) SDRAM_ADDR(2) B03D (1x) TXD0 B03E (1x) WX_DQS2 B05C (1x)
+2V5out-FPGA B05E (2x) ambi_pwm(5) B05D (1x) HDMI_Cr(9) B07C (1x) ITV_SPI_DATA_IN B04 (2x) MIU_WEN B03B (1x) SDRAM_ADDR(3) B03C (1x) TxFPGAe_0n B05A (1x) WX_DQS3 B05B (1x)
+3V3 B03A (3x) ambi_pwm(5) B05E (1x) HDMI_DE B05C (1x) JTAG_TCK B03A (1x) MIU_WEN B03C (1x) SDRAM_ADDR(3) B03D (1x) TxFPGAe_0n B05E (1x) WX_DQS3 B05C (1x)
+3V3 B03B (3x) AMBI_SCL B05D (1x) HDMI_DE B07C (1x) JTAG_TCK B03B (1x) MIU_WEN B03D (1x) SDRAM_ADDR(4) B03C (1x) TxFPGAe_0p B05A (1x) WX_MA0 B05B (2x)
+3V3 B03C (7x) AMBI_SCL B05E (1x) HDMI_H B05C (1x) JTAG_TCK B03C (1x) MOJO_I2S_OUT_SCK B03C (1x) SDRAM_ADDR(4) B03D (1x) TxFPGAe_0p B05E (1x) WX_MA0 B05C (1x)
+3V3 B03D (2x) AMBI_SDA B05D (1x) HDMI_H B07C (1x) JTAG_TCK B05D (1x) MOJO_I2S_OUT_SCK B06A (1x) SDRAM_ADDR(5) B03C (1x) TxFPGAe_1n B05A (1x) WX_MA1 B05B (2x)
+3V3 B03E (1x) AMBI_SDA B05E (1x) HDMI_HOTPLUG_RESET B04 (1x) JTAG_TMS B03A (1x) MOJO_I2S_OUT_SD B03C (1x) SDRAM_ADDR(5) B03D (1x) TxFPGAe_1n B05E (1x) WX_MA1 B05C (1x)
+3V3_ANA-MUX B07C (2x) ANTI_PLOP B04 (1x) HDMI_HOTPLUG_RESET B07C (1x) JTAG_TMS B03B (1x) MOJO_I2S_OUT_SD B06A (1x) SDRAM_ADDR(6) B03C (1x) TxFPGAe_1p B05A (1x) WX_MA10 B05B (2x)
+3V3_ANA-MUX B07D (4x) ANTI_PLOP B06C (1x) HDMI_HOTPLUG_RESET B07D (1x) JTAG_TMS B03C (1x) MOJO_I2S_OUT_WS B03C (1x) SDRAM_ADDR(6) B03D (1x) TxFPGAe_1p B05E (1x) WX_MA10 B05C (1x)
+3V3_BUF B03B (4x) ASDO B05D (2x) HDMI_INT_MAIN B04 (1x) JTAG_TMS B05D (1x) MOJO_I2S_OUT_WS B06A (1x) SDRAM_ADDR(7) B03C (1x) TxFPGAe_2n B05A (1x) WX_MA11 B05B (2x)
+3V3_CORE B03B (2x) ASDO B05E (1x) HDMI_INT_MAIN B07C (1x) JTAG_TRST B03A (1x) MUTEn B04 (1x) SDRAM_ADDR(7) B03D (1x) TxFPGAe_2n B05E (1x) WX_MA11 B05C (1x)
+3V3_FPGA B05D (8x) AUDIO_LS_L B06A (1x) HDMI_INT_MUX B04 (1x) JTAG_TRST B03B (1x) MUTEn B06C (1x) SDRAM_ADDR(8) B03C (1x) TxFPGAe_2p B05A (1x) WX_MA2 B05B (2x)
+3V3_FPGA B05E (4x) AUDIO_LS_L B06B (1x) HDMI_INT_MUX B07D (1x) JTAG_TRST B03C (1x) nCSO B05D (2x) SDRAM_ADDR(8) B03D (1x) TxFPGAe_2p B05E (1x) WX_MA2 B05C (1x)
+3V3_NOR48 B03D (4x) AUDIO_LS_R B06A (1x) HDMI_INT_SIDE B04 (2x) KEYB B04 (2x) nCSO B05E (1x) SDRAM_ADDR(9) B03C (1x) TxFPGAe_3n B05A (1x) WX_MA3 B05B (2x)
+3V3_STBY B01A (1x) AUDIO_LS_R B06B (1x) HDMI_RST_MUX B04 (1x) LCD_PWR_ON B04 (1x) NOR_CS B03C (1x) SDRAM_ADDR(9) B03D (1x) TxFPGAe_3n B05E (1x) WX_MA3 B05C (1x)
+3V3_STBY B04 (31x) -AUDIO_POWER B06B (2x) HDMI_RST_MUX B07D (1x) LCD_PWR_ON B07E (1x) NOR_CS B03D (1x) SDRAM_CAS B03C (1x) TxFPGAe_3p B05A (1x) WX_MA4 B05B (2x)
+3V3_STBY B06C (3x) BACKLIGHT_BOOST B01A (1x) HDMI_RST_RX_BUF B04 (2x) LED1 B04 (2x) NOR_RYBY B03C (1x) SDRAM_CAS B03D (1x) TxFPGAe_3p B05E (1x) WX_MA4 B05C (1x)
+3V3_STBY B07D (2x) BACKLIGHT_BOOST B04 (1x) HDMI_RST_RX_BUF B07C (1x) LED2 B04 (2x) NOR_RYBY B03D (1x) SDRAM_CKE B03C (1x) TxFPGAe_4n B05A (1x) WX_MA5 B05B (2x)
+3V3_STV B03B (10x) BL_ADJUST B01A (1x) HDMI_SCK B06A (1x) MAIN_SCL B05D (1x) NOR_WP B03C (1x) SDRAM_CKE B03D (1x) TxFPGAe_4n B05E (1x) WX_MA5 B05C (1x)
+3V3_SW B01A (1x) BL_ADJUST B05A (1x) HDMI_SCK B07C (1x) MAIN_SCL B05E (1x) NOR_WP B03D (1x) SDRAM_CLK B03C (1x) TxFPGAe_4p B05A (1x) WX_MA6 B05B (2x)
+3V3_SW B02 (2x) BL_ON_OFF B01A (1x) HDMI_SD B06A (1x) MAIN_SDA B05D (1x) PC_VGA_H B05A (2x) SDRAM_CLK B03D (1x) TxFPGAe_4p B05E (1x) WX_MA6 B05C (1x)
+3V3_SW B03E (2x) BL_ON_OFF B04 (1x) HDMI_SD B07C (1x) MAIN_SDA B05E (1x) PC_VGA_V B05A (2x) SDRAM_DATA(0) B03C (1x) TxFPGAe_CLKn B05A (1x) WX_MA7 B05B (2x)
+3V3_SW B04 (9x) BOLT_ON_SCL B04 (2x) HDMI_V B05C (1x) MIU_ADDR(0) B03B (1x) PCMCIA_5V B03B (4x) SDRAM_DATA(0) B03D (1x) TxFPGAe_CLKn B05E (1x) WX_MA7 B05C (1x)
+3V3_SW B05A (8x) BOLT_ON_SCL B07E (1x) HDMI_V B07C (1x) MIU_ADDR(0) B03C (1x) PCMCIA_AVCC B03B (3x) SDRAM_DATA(0:15) B03C (1x) TxFPGAe_CLKp B05A (1x) WX_MA8 B05B (2x)
+3V3_SW B05C (9x) BOLT_ON_SDA B04 (2x) HDMI_VCLK B05C (1x) MIU_ADDR(0:24) B03B (1x) PCMCIA_VPP B03B (3x) SDRAM_DATA(1) B03C (1x) TxFPGAe_CLKp B05E (1x) WX_MA8 B05C (1x)
+3V3_SW B05E (1x) BOLT_ON_SDA B07E (1x) HDMI_VCLK B07C (1x) MIU_ADDR(0:24) B03C (1x) POWER_DOWN B01A (1x) SDRAM_DATA(1) B03D (1x) TxFPGAo_0n B05A (1x) WX_MA9 B05B (2x)
+3V3_SW B07C (8x) C_IN B07A (2x) HDMI_WS B06A (1x) MIU_ADDR(1) B03B (1x) POWER_DOWN B04 (1x) SDRAM_DATA(10) B03C (1x) TxFPGAo_0n B05E (1x) WX_MA9 B05C (1x)
+3V3_SW B07D (1x) CE B04 (1x) HDMI_WS B07C (1x) MIU_ADDR(1) B03C (1x) POWER_DOWN B06C (1x) SDRAM_DATA(10) B03D (1x) TxFPGAo_0p B05A (1x) WX_MCK0 B05B (2x)
+3V3_SW B07E (1x) CE B05E (1x) HDMI_Y(0) B05C (1x) MIU_ADDR(1) B03D (1x) RD B04 (1x) SDRAM_DATA(11) B03C (1x) TxFPGAo_0p B05E (1x) WX_MCK0 B05C (1x)
+3V3_VDDP B03C (3x) CEC_D B04 (1x) HDMI_Y(0) B07C (1x) MIU_ADDR(10) B03B (1x) RD B05A (1x) SDRAM_DATA(11) B03D (1x) TxFPGAo_1n B05A (1x) WX_MCK0# B05B (2x)
+3V3clean B03C (1x) CEC_D B07D (1x) HDMI_Y(1) B05C (1x) MIU_ADDR(10) B03C (1x) REMOTE B04 (3x) SDRAM_DATA(12) B03C (1x) TxFPGAo_1n B05E (1x) WX_MCK0# B05C (1x)
+3V3clean B03E (1x) CLK_OSC1 B05D (1x) HDMI_Y(1) B07C (1x) MIU_ADDR(10) B03D (1x) RESET_FE_n B03A (1x) SDRAM_DATA(12) B03D (1x) TxFPGAo_1p B05A (1x) WX_MD0 B05B (1x)
+3V3FE B03A (5x) CLK_OSC1 B05E (1x) HDMI_Y(2) B05C (1x) MIU_ADDR(11) B03B (1x) RESET_FE_n B03C (1x) SDRAM_DATA(13) B03C (1x) TxFPGAo_1p B05E (1x) WX_MD0 B05C (1x)
+3V3SWA B07C (1x) COMP_AUDIO_IN_L B06A (1x) HDMI_Y(2) B07C (1x) MIU_ADDR(11) B03C (1x) RESET_n B03C (1x) SDRAM_DATA(13) B03D (1x) TxFPGAo_2n B05A (1x) WX_MD1 B05B (1x)
+3V3SWB B07C (1x) COMP_AUDIO_IN_L B07A (1x) HDMI_Y(3) B05C (1x) MIU_ADDR(11) B03D (1x) RESET_n B03D (1x) SDRAM_DATA(14) B03C (1x) TxFPGAo_2n B05E (1x) WX_MD1 B05C (1x)
+3V3SWC B07C (1x) COMP_AUDIO_IN_R B06A (1x) HDMI_Y(3) B07C (1x) MIU_ADDR(12) B03B (1x) RESET_n B04 (2x) SDRAM_DATA(14) B03D (1x) TxFPGAo_2p B05A (1x) WX_MD10 B05B (1x)
+3V3SWD B07C (1x) COMP_AUDIO_IN_R B07A (1x) HDMI_Y(4) B05C (1x) MIU_ADDR(12) B03C (1x) RESET_STV B03B (1x) SDRAM_DATA(15) B03C (1x) TxFPGAo_2p B05E (1x) WX_MD10 B05C (1x)
+3V3SWE B07C (1x) CPU_RST B04 (1x) HDMI_Y(4) B07C (1x) MIU_ADDR(12) B03D (1x) RESET_STV B03C (1x) SDRAM_DATA(15) B03D (1x) TxFPGAo_3n B05A (1x) WX_MD11 B05B (1x)
+5V_AUD B06A (3x) CS B04 (1x) HDMI_Y(5) B05C (1x) MIU_ADDR(13) B03B (1x) RF_AGC B02 (2x) SDRAM_DATA(2) B03C (1x) TxFPGAo_3n B05E (1x) WX_MD11 B05C (1x)
+5V_D B06A (2x) CS B05A (1x) HDMI_Y(5) B07C (1x) MIU_ADDR(13) B03C (1x) RF_AGC_IBO B02 (1x) SDRAM_DATA(2) B03D (1x) TxFPGAo_3p B05A (1x) WX_MD12 B05B (1x)
+5V_IF B02 (7x) CTRL_DISP1 B07E (2x) HDMI_Y(6) B05C (1x) MIU_ADDR(13) B03D (1x) RF_AGC_IBO B03A (1x) SDRAM_DATA(3) B03C (1x) TxFPGAo_3p B05E (1x) WX_MD12 B05C (1x)
+5V_STANDBY B01A (4x) CTRL_DISP1_up B04 (1x) HDMI_Y(6) B07C (1x) MIU_ADDR(14) B03B (1x) RST_AUD B04 (1x) SDRAM_DATA(3) B03D (1x) TxFPGAo_4n B05A (1x) WX_MD13 B05B (1x)
+5V_STANDBY B04 (4x) CTRL_DISP1_up B07E (1x) HDMI_Y(7) B05C (1x) MIU_ADDR(14) B03C (1x) RST_AUD B06A (1x) SDRAM_DATA(4) B03C (1x) TxFPGAo_4n B05E (1x) WX_MD13 B05C (1x)
+5V_STANDBY B05A (1x) CTRL_DISP2 B07E (2x) HDMI_Y(7) B07C (1x) MIU_ADDR(14) B03D (1x) RST_H B04 (1x) SDRAM_DATA(4) B03D (1x) TxFPGAo_4p B05A (1x) WX_MD14 B05B (1x)
+5V_STANDBY B07E (1x) CTRL_DISP3 B07E (2x) HDMI_Y(8) B05C (1x) MIU_ADDR(15) B03B (1x) RST_H B05A (1x) SDRAM_DATA(5) B03C (1x) TxFPGAo_4p B05E (1x) WX_MD14 B05C (1x)
+5V_SW B01A (3x) CTRL_DISP4 B07E (2x) HDMI_Y(8) B07C (1x) MIU_ADDR(15) B03C (1x) RX0+A B07D (2x) SDRAM_DATA(5) B03D (1x) TxFPGAo_CLKn B05A (1x) WX_MD15 B05B (1x)
+5V_SW B02 (2x) CTRL_DISP4_up B04 (1x) HDMI_Y(9) B05C (1x) MIU_ADDR(15) B03D (1x) RX0+B B07D (2x) SDRAM_DATA(6) B03C (1x) TxFPGAo_CLKn B05E (1x) WX_MD15 B05C (1x)
+5V_SW B03A (9x) CTRL_DISP4_up B07E (1x) HDMI_Y(9) B07C (1x) MIU_ADDR(16) B03B (1x) RX0+C B07D (2x) SDRAM_DATA(6) B03D (1x) TxFPGAo_CLKp B05A (1x) WX_MD16 B05B (1x)
+5V_SW B03B (2x) CVBS_RF B02 (1x) HDMI-MUX_TSCL B07C (1x) MIU_ADDR(16) B03C (1x) RX0-A B07D (2x) SDRAM_DATA(7) B03C (1x) TxFPGAo_CLKp B05E (1x) WX_MD16 B05C (1x)
+5V_SW B03D (3x) CVBS_RF B05A (1x) HDMI-MUX_TSCL B07D (1x) MIU_ADDR(16) B03D (1x) RX0-B B07D (2x) SDRAM_DATA(7) B03D (1x) TxLVDSe_0n B05E (1x) WX_MD17 B05B (1x)
+5V_SW B04 (2x) DATA0 B05D (2x) HDMI-MUX_TSDA B07C (1x) MIU_ADDR(17) B03B (1x) RX0-C B07D (2x) SDRAM_DATA(8) B03C (1x) TxLVDSe_0n B07E (1x) WX_MD17 B05C (1x)
+5V_SW B05A (2x) DATA0 B05E (1x) HDMI-MUX_TSDA B07D (1x) MIU_ADDR(17) B03C (1x) RX1+A B07D (2x) SDRAM_DATA(8) B03D (1x) TxLVDSe_0p B05E (1x) WX_MD18 B05B (1x)
+5V_SW B06A (1x) DC_PROT B04 (1x) HDMI-MUX_TX0- B07C (1x) MIU_ADDR(17) B03D (1x) RX1+B B07D (2x) SDRAM_DATA(9) B03C (1x) TxLVDSe_0p B07E (1x) WX_MD18 B05C (1x)
+5V_SW B06C (1x) DC_PROT B06B (1x) HDMI-MUX_TX0- B07D (1x) MIU_ADDR(18) B03B (1x) RX1+C B07D (2x) SDRAM_DATA(9) B03D (1x) TxLVDSe_1n B05E (1x) WX_MD19 B05B (1x)
+5V_SW B07A (3x) DCLK B05D (2x) HDMI-MUX_TX0+ B07C (1x) MIU_ADDR(18) B03C (1x) RX1-A B07D (2x) SDRAM_DQM0 B03C (1x) TxLVDSe_1n B07E (1x) WX_MD19 B05C (1x)
+5V_SW B07B (2x) DCLK B05E (1x) HDMI-MUX_TX0+ B07D (1x) MIU_ADDR(18) B03D (1x) RX1-B B07D (2x) SDRAM_DQM0 B03D (1x) TxLVDSe_1p B05E (1x) WX_MD2 B05B (1x)
+5V_SW B07D (4x) DDC_RESET B04 (2x) HDMI-MUX_TX1- B07C (1x) MIU_ADDR(19) B03B (1x) RX1-C B07D (2x) SDRAM_DQM1 B03C (1x) TxLVDSe_1p B07E (1x) WX_MD2 B05C (1x)
+5VHDMI_A B07D (3x) DDC_RESET B07D (3x) HDMI-MUX_TX1- B07D (1x) MIU_ADDR(19) B03C (1x) RX2+A B07D (2x) SDRAM_DQM1 B03D (1x) TxLVDSe_2n B05E (1x) WX_MD20 B05B (1x)
+5VHDMI_B B07D (3x) DDC_SCLA B07D (2x) HDMI-MUX_TX1+ B07C (1x) MIU_ADDR(19) B03D (1x) RX2+B B07D (2x) SDRAM_RAS B03C (1x) TxLVDSe_2n B07E (1x) WX_MD20 B05C (1x)
+5VHDMI_C B07D (3x) DDC_SCLB B07D (2x) HDMI-MUX_TX1+ B07D (1x) MIU_ADDR(2) B03B (1x) RX2+C B07D (2x) SDRAM_RAS B03D (1x) TxLVDSe_2p B05E (1x) WX_MD21 B05B (1x)
+5VHDMI-MUX_TPWR B07C (1x) DDC_SCLC B07D (2x) HDMI-MUX_TX2- B07C (1x) MIU_ADDR(2) B03C (1x) RX2-A B07D (2x) SDRAM_WE B03C (1x) TxLVDSe_2p B07E (1x) WX_MD21 B05C (1x)
+5VHDMI-MUX_TPWR B07D (1x) DDC_SDAA B07D (2x) HDMI-MUX_TX2- B07D (1x) MIU_ADDR(2) B03D (1x) RX2-B B07D (2x) SDRAM_WE B03D (1x) TxLVDSe_3n B05E (1x) WX_MD22 B05B (1x)
+5VHDMI-SIDE_TPWR B07C (2x) DDC_SDAB B07D (2x) HDMI-MUX_TX2+ B07C (1x) MIU_ADDR(20) B03B (1x) RX2-C B07D (2x) SIDE_AUDIO_IN_L B04 (1x) TxLVDSe_3n B07E (1x) WX_MD22 B05C (1x)
+5VS B02 (4x) DDC_SDAC B07D (2x) HDMI-MUX_TX2+ B07D (1x) MIU_ADDR(20) B03C (1x) RXC+A B07D (2x) SIDE_AUDIO_IN_L B06A (1x) TxLVDSe_3p B05E (1x) WX_MD23 B05B (1x)
+8V B06A (2x) DDR_VREF B05B (3x) HDMI-MUX_TXC- B07C (1x) MIU_ADDR(20) B03D (1x) RXC+B B07D (2x) SIDE_AUDIO_IN_R B04 (1x) TxLVDSe_3p B07E (1x) WX_MD23 B05C (1x)
+AUDIO_POWER B06B (3x) DDR_VREF B05C (1x) HDMI-MUX_TXC- B07D (1x) MIU_ADDR(21) B03B (1x) RXC+C B07D (2x) SIDE_AUDIO_IN_R B06A (1x) TxLVDSe_4n B05E (1x) WX_MD24 B05B (1x)
+AUDIO_POWER_+12V_DISP B06A (1x) DP_HS B05C (2x) HDMI-MUX_TXC+ B07C (1x) MIU_ADDR(21) B03C (1x) RXC-A B07D (2x) SIF B02 (1x) TxLVDSe_4n B07E (1x) WX_MD24 B05C (1x)
+AUDIO_POWER_+12V_DISP B06B (1x) DVB_SW B02 (1x) HDMI-MUX_TXC+ B07D (1x) MIU_ADDR(21) B03D (1x) RXC-B B07D (2x) SIF B06A (1x) TxLVDSe_4p B05E (1x) WX_MD25 B05B (1x)
+VDISP B07E (2x) DVB_SW B04 (1x) HDMI-SIDE_CEC_A B07C (1x) MIU_ADDR(22) B03B (1x) RXC-C B07D (2x) SIF1 B02 (2x) TxLVDSe_4p B07E (1x) WX_MD25 B05C (1x)
+VTUN B01A (1x) E_PAGE B04 (2x) HDMI-SIDE_CEC_A B07D (1x) MIU_ADDR(22) B03C (1x) RXD0 B03C (1x) SIF2 B02 (2x) TxLVDSe_CLKn B05E (1x) WX_MD26 B05B (1x)
+VTUN B02 (1x) ENGAGE B06B (1x) HDMI-SIDE_TSCL B07C (2x) MIU_ADDR(22) B03D (1x) RXD0 B03E (1x) STANDBY B01A (2x) TxLVDSe_CLKn B07E (1x) WX_MD26 B05C (1x)
10046_TDO B03A (1x) ENGAGE B06C (1x) HDMI-SIDE_TSDA B07C (2x) MIU_ADDR(23) B03B (1x) SAW_SW B02 (1x) STANDBY B04 (2x) TxLVDSe_CLKp B05E (1x) WX_MD27 B05B (1x)
10046_TDO B03C (1x) FE_LOCK B03A (1x) HDMI-SIDE_TX0- B07C (2x) MIU_ADDR(23) B03C (1x) SAW_SW B04 (1x) STANDBY B06C (1x) TxLVDSe_CLKp B07E (1x) WX_MD27 B05C (1x)
4MHZ_CLK B02 (1x) FE_LOCK B03C (1x) HDMI-SIDE_TX0+ B07C (2x) MIU_ADDR(24) B03B (1x) SC1_AUDIO_IN_L B06A (1x) STANDBYn B04 (1x) TxLVDSo_0n B05E (1x) WX_MD28 B05B (1x)
4MHZ_CLK B03A (1x) FPGA_BL_BOOST B05E (1x) HDMI-SIDE_TX1- B07C (2x) MIU_ADDR(24) B03C (1x) SC1_AUDIO_IN_L B07B (1x) STANDBYn B06B (1x) TxLVDSo_0n B07E (1x) WX_MD28 B05C (1x)
4MHz_MOJO B03A (1x) FPGA_BL_DIMMING B05A (1x) HDMI-SIDE_TX1+ B07C (2x) MIU_ADDR(3) B03B (1x) SC1_AUDIO_IN_R B06A (1x) STANDBYn B07E (1x) TxLVDSo_0p B05E (1x) WX_MD29 B05B (1x)
4MHz_MOJO B03C (1x) FPGA_BL_DIMMING B05E (1x) HDMI-SIDE_TX2- B07C (2x) MIU_ADDR(3) B03C (1x) SC1_AUDIO_IN_R B07B (1x) STV_A25 B03B (1x) TxLVDSo_0p B07E (1x) WX_MD29 B05C (1x)
A(0) B04 (2x) FRONT_C_IN_T B04 (1x) HDMI-SIDE_TX2+ B07C (2x) MIU_ADDR(3) B03D (1x) SC1_AUDIO_MUTE_L B06C (1x) STV_A25 B03C (1x) TxLVDSo_1n B05E (1x) WX_MD3 B05B (1x)
A(0) B05A (1x) FRONT_C_IN_T B07A (1x) HDMI-SIDE_TXC- B07C (2x) MIU_ADDR(4) B03B (1x) SC1_AUDIO_MUTE_L B07B (1x) STV_CS B03B (1x) TxLVDSo_1n B07E (1x) WX_MD3 B05C (1x)
A(0:7) B04 (1x) FRONT_CVBS_SVHS_SEL B04 (1x) HDMI-SIDE_TXC+ B07C (2x) MIU_ADDR(4) B03C (1x) SC1_AUDIO_MUTE_R B06C (1x) STV_CS B03C (1x) TxLVDSo_1p B05E (1x) WX_MD30 B05B (1x)
A(1) B04 (2x) FRONT_CVBS_SVHS_SEL B07A (1x) HP_AUDIO_OUT_L B06A (1x) MIU_ADDR(4) B03D (1x) SC1_AUDIO_MUTE_R B07B (1x) STV_INT B03B (1x) TxLVDSo_1p B07E (1x) WX_MD30 B05C (1x)
A(1) B05A (1x) FRONT_CVBS_SVHS_Y_IN B05A (1x) HP_AUDIO_OUT_L B06C (1x) MIU_ADDR(5) B03B (1x) SC1_AUDIO_OUT_L B06A (1x) STV_INT B03C (1x) TxLVDSo_2n B05E (1x) WX_MD31 B05B (1x)
A(1:7) B04 (1x) FRONT_CVBS_SVHS_Y_IN B07A (1x) HP_AUDIO_OUT_R B06A (1x) MIU_ADDR(5) B03C (1x) SC1_AUDIO_OUT_L B07B (2x) STV_TDO B03A (1x) TxLVDSo_2n B07E (1x) WX_MD31 B05C (1x)
A(10) B04 (2x) FRONT_Y_CVBS_IN_T B04 (1x) HP_AUDIO_OUT_R B06C (1x) MIU_ADDR(5) B03D (1x) SC1_AUDIO_OUT_R B06A (1x) STV_TDO B03B (1x) TxLVDSo_2p B05E (1x) WX_MD4 B05B (1x)
A(11) B04 (2x) FRONT_Y_CVBS_IN_T B07A (1x) HP_DETECT_T B04 (2x) MIU_ADDR(6) B03B (1x) SC1_AUDIO_OUT_R B07B (2x) SVHS_C_IN B05A (1x) TxLVDSo_2p B07E (1x) WX_MD4 B05C (1x)
A(12) B04 (2x) GNDDC B01A (1x) HP_LOUT B04 (1x) MIU_ADDR(6) B03C (1x) SC1_B_IN B05A (1x) SVHS_C_IN B07A (1x) TxLVDSo_3n B05E (1x) WX_MD5 B05B (1x)
A(13) B04 (2x) GNDDC1V2 B01B (6x) HP_LOUT B06C (1x) MIU_ADDR(6) B03D (1x) SC1_B_IN B07B (2x) TCK_FPGA B05D (1x) TxLVDSo_3n B07E (1x) WX_MD5 B05C (1x)
A(14) B04 (2x) GNDDC2 B01B (13x) HP_ROUT B04 (1x) MIU_ADDR(7) B03B (1x) SC1_CVBS_IN B05A (1x) TCK_FPGA B05E (1x) TxLVDSo_3p B05E (1x) WX_MD6 B05B (1x)
A(15) B04 (2x) GNDDC2V5 B01B (6x) HP_ROUT B06C (1x) MIU_ADDR(7) B03C (1x) SC1_CVBS_IN B07B (1x) TDA_CLK B03A (1x) TxLVDSo_3p B07E (1x) WX_MD6 B05C (1x)
A(16) B04 (2x) GNDSND B06B (25x) HPD_RESET_A B07D (2x) MIU_ADDR(7) B03D (1x) SC1_CVBS_RF_OUT B04 (1x) TDA_CLK B03B (1x) TxLVDSo_4n B05E (1x) WX_MD7 B05B (1x)
A(17) B04 (2x) GNDTUN B01A (1x) HPD_RESET_B B07D (2x) MIU_ADDR(8) B03B (1x) SC1_CVBS_RF_OUT B07B (1x) TDA_DAT(0) B03A (1x) TxLVDSo_4n B07E (1x) WX_MD7 B05C (1x)
A(18) B04 (2x) HD_PB_IN B05A (1x) HPD_RESET_C B07D (2x) MIU_ADDR(8) B03C (1x) SC1_FBL_IN B05A (1x) TDA_DAT(0) B03B (1x) TxLVDSo_4p B05E (1x) WX_MD8 B05B (1x)
A(19) B04 (2x) HD_PB_IN B07A (1x) I2C_LOCAL_SCL B03A (1x) MIU_ADDR(8) B03D (1x) SC1_FBL_IN B07B (2x) TDA_DAT(0:7) B03A (1x) TxLVDSo_4p B07E (1x) WX_MD8 B05C (1x)
A(2) B04 (2x) HD_PB_IN_ITV B07A (2x) I2C_LOCAL_SCL B03B (1x) MIU_ADDR(9) B03B (1x) SC1_G_IN B05A (1x) TDA_DAT(0:7) B03B (1x) TxLVDSo_CLKn B05E (1x) WX_MD9 B05B (1x)
A(2) B05A (1x) HD_PR_IN B05A (1x) I2C_LOCAL_SCL B03C (1x) MIU_ADDR(9) B03C (1x) SC1_G_IN B07B (2x) TDA_DAT(1) B03A (1x) TxLVDSo_CLKn B07E (1x) WX_MD9 B05C (1x)
A(3) B04 (2x) HD_PR_IN B07A (1x) I2C_LOCAL_SCL B03D (1x) MIU_ADDR(9) B03D (1x) SC1_R_IN B05A (1x) TDA_DAT(1) B03B (1x) TxLVDSo_CLKp B05E (1x) WX_PAVDD1 B05A (1x)
A(3) B05A (1x) HD_PR_IN_ITV B07A (2x) I2C_LOCAL_SDA B03A (1x) MIU_DATA(0) B03B (1x) SC1_R_IN B07B (2x) TDA_DAT(2) B03A (1x) TxLVDSo_CLKp B07E (1x) WX_PAVDD1 B05C (1x)
A(4) B04 (2x) HD_Y_IN B05A (1x) I2C_LOCAL_SDA B03B (1x) MIU_DATA(0) B03C (1x) SC1_RF_OUT_CVBS B05A (1x) TDA_DAT(2) B03B (1x) user_EEPROM_WP B03C (1x) WX_PAVDD2 B05A (1x)
A(4) B05A (1x) HD_Y_IN B07A (1x) I2C_LOCAL_SDA B03C (1x) MIU_DATA(0) B03D (1x) SC1_RF_OUT_CVBS B07B (1x) TDA_DAT(3) B03A (1x) user_EEPROM_WP B03D (1x) WX_PAVDD2 B05C (1x)
A(5) B04 (2x) HD_Y_IN_ITV B07A (2x) I2C_LOCAL_SDA B03D (1x) MIU_DATA(0:15) B03C (1x) SC1_STATUS B04 (1x) TDA_DAT(3) B03B (1x) VCCEN B03B (2x) WX_PVCC B05A (2x)
A(5) B05A (1x) HDMI_AUDIO_IN_L B06A (1x) I2C_TDA_SCL B02 (1x) MIU_DATA(0:15) B03D (1x) SC1_STATUS B07B (1x) TDA_DAT(4) B03A (1x) VDD B06B (3x) WX_RAS# B05B (2x)
A(6) B04 (2x) HDMI_AUDIO_IN_L B07C (1x) I2C_TDA_SCL B03A (1x) MIU_DATA(1) B03B (1x) SC2_AUDIO_IN_L B06A (1x) TDA_DAT(4) B03B (1x) VDDA B06B (2x) WX_RAS# B05C (1x)
A(6) B05A (1x) HDMI_AUDIO_IN_R B06A (1x) I2C_TDA_SDA B02 (1x) MIU_DATA(1) B03C (1x) SC2_AUDIO_IN_L B07B (2x) TDA_DAT(5) B03A (1x) VGA_H B05A (1x) WX_REGVCC B05A (2x)
A(7) B04 (2x) HDMI_AUDIO_IN_R B07C (1x) I2C_TDA_SDA B03A (1x) MIU_DATA(1) B03D (1x) SC2_AUDIO_IN_R B06A (1x) TDA_DAT(5) B03B (1x) VGA_H B07A (1x) WX_WE# B05B (2x)
A(7) B05A (1x) HDMI_Cb(0) B05C (1x) IBO_B_IN B03E (1x) MIU_DATA(10) B03C (1x) SC2_AUDIO_IN_R B07B (2x) TDA_DAT(6) B03A (1x) VGA_V B05A (1x) WX_WE# B05C (1x)
A(8) B04 (2x) HDMI_Cb(0) B07C (1x) IBO_B_IN B05A (1x) MIU_DATA(10) B03D (1x) SC2_AUDIO_MUTE_L B06C (1x) TDA_DAT(6) B03B (1x) VGA_V B07A (1x) Y_IN B07A (2x)
A(8:19) B04 (2x) HDMI_Cb(1) B05C (1x) IBO_CVBS_IN B03E (1x) MIU_DATA(11) B03C (1x) SC2_AUDIO_MUTE_L B07B (1x) TDA_DAT(7) B03A (1x) VIF1 B02 (2x)

H_17370_034.eps
3104 313 6073.5 080807
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 67

Layout SSB (Overview Top Side)


1001 B10 1307 A8 1508 D10 1523 C9 1A01 A10 1R02 A6 2142 E6 2341 C8 2432 B8 2447 B8 2915 A7 2A22 B9 2B24 B1 2C09 D5 2C82 C4 2E17 D5 2G02 C3 2K07 E1 2L29 A8 2P29 B3 2R23 A6 3314 D7 3352 C8 3397 D7 3725 A6 3740 B6 3902 B7 3A03 A8 3B12 A1 3C32 C3 3D47 B4 3R25 A7 7410 A8
1002 B9 1308 A8 1509 D9 1524 C9 1A02 A7 1R03 A6 2201 A6 2408 B8 2433 B8 2700 A6 2916 A7 2A24 B9 2B25 A2 2C10 D5 2D31 A4 2E18 D5 2G17 B1 2K11 D3 2L30 A8 2P30 B3 2R24 A6 3315 C7 3354 C8 3398 B8 3726 A6 3741 B6 3903 A7 3A04 A9 3B17 A1 3C33 C3 3D48 B4 3R26 A7 7700 B6
1101 E3 1309 A8 1510 D10 1525 B10 1A03 A9 1R04 A6 2202 A6 2409 B8 2434 B8 2702 A6 2A01 A9 2A29 B9 2B26 A2 2C11 D5 2D32 C4 2E19 D4 2G18 C1 2K13 D3 2L31 A8 2P34 A3 3113 E6 3317 C7 3359 C8 3399 B7 3727 A6 3742 B6 3904 A7 3A06 A8 3B18 A1 3C34 C3 3E02 C4 3R35 A6 7901 B7
1102 E6 1310 A8 1511 D9 1526 E10 1B12 A2 1R05 A6 2211 B7 2410 A8 2435 B8 2718 A6 2A02 A9 2A30 A9 2B27 A2 2C12 D5 2D71 A4 2E20 D4 2G22 D3 2K14 F2 2L32 A8 2P46 B3 3117 F6 3320 C6 3360 C8 3402 B8 3728 A6 3743 B6 3905 B7 3A07 B8 3B19 A1 3C36 D3 3E04 C4 3R48 A6 7917 B7
1103 E6 1312 B8 1512 D9 1601 F9 1B13 A2 1R06 A6 2212 B7 2411 B8 2436 B8 2721 A6 2A04 B9 2A32 B9 2B65 A2 2C13 D5 2D72 A4 2E23 C4 2G23 D1 2K16 F3 2L33 A8 2P55 C3 3118 E6 3322 C7 3361 C8 3410 B7 3729 A6 3744 B6 3906 B7 3A08 B9 3B65 A2 3C37 D3 3G15 B1 3R49 A6 7919 B7
1104 D6 1313 A1 1513 D10 1606 F10 1C24 C4 1R07 A6 2213 B7 2412 B8 2437 B8 2724 B7 2A08 A9 2A33 A9 2B66 B2 2C14 D4 2E01 D4 2E24 C4 2G24 B1 2K17 F3 2L34 A8 2P56 C4 3119 E6 3324 C7 3362 C8 3411 B7 3730 A6 3745 B6 3907 B7 3A11 B8 3B66 A1 3D01 B5 3G19 B1 3R50 A6 7A01 A9
1201 A4 1314 B9 1514 D10 1607 F9 1J14 B10 1R08 A7 2310 D7 2413 B8 2438 B8 2734 A6 2A09 A9 2A34 A9 2B67 A2 2C15 D4 2E02 D4 2E25 C4 2G33 B2 2L20 A8 2L35 A8 2P59 B3 3188 E6 3329 D7 3380 C6 3416 B8 3731 A6 3746 B6 3908 A7 3A13 B9 3C01 C4 3D02 B5 3G48 B1 3R51 A6 7A05 A9
1202 A4 1500 E10 1515 D10 1608 F9 1K00 E5 1R09 A7 2312 C7 2414 B8 2439 A7 2901 A7 2A10 B9 2A40 A9 2C01 C4 2C18 D5 2E09 C4 2E26 C4 2H06 C3 2L21 A7 2M11 F6 2P61 B3 3192 D6 3330 C6 3382 C8 3702 B7 3732 B6 3747 B6 3909 A7 3A19 A9 3C02 D4 3D05 B5 3G56 D1 3R52 A6 7A06 A9
1203 A5 1501 E10 1516 D9 1609 F8 1L20 A8 1R10 A7 2313 B7 2417 B8 2440 A7 2902 B7 2A11 A9 2A41 A9 2C02 C4 2C19 D5 2E10 C4 2F10 D3 2H07 D1 2L22 A7 2N03 E8 2P68 B3 3201 A6 3343 B9 3384 C8 3713 B6 3733 B6 3748 B6 3910 A7 3A26 A8 3C03 C6 3D06 B5 3G57 D1 3R53 A6 7A07 A9
1301 D7 1502 E9 1517 D9 1610 F9 1M01 F6 1R11 A7 2314 D7 2418 B8 2441 B8 2904 B7 2A12 A9 2B10 A2 2C03 D4 2C22 B4 2E11 C4 2F11 D3 2H08 D3 2L23 A8 2N06 E8 2P72 A4 3202 A6 3345 B9 3386 C8 3714 B6 3734 B6 3749 B6 3934 B7 3A27 A9 3C04 C6 3D09 B5 3G58 D1 3R54 A6 7B01 B1
1302 B9 1503 E10 1518 C10 1611 F9 1M02 F7 1R12 A7 2316 D7 2419 B8 2442 B8 2905 A7 2A15 A8 2B12 B1 2C04 D5 2C23 C4 2E12 C4 2F12 F3 2J01 B1 2L24 A8 2N11 E8 2R01 A7 3303 C6 3347 D8 3387 C6 3720 B6 3735 B6 3750 B6 3935 B7 3A28 A9 3C05 C6 3D11 B5 3G59 D1 4113 D6 7B02 A1
1303 B9 1504 D9 1519 D9 1613 F10 1M03 F8 1R13 A7 2317 D7 2420 B8 2443 B8 2907 B7 2A16 B8 2B18 A1 2C05 D5 2C28 C4 2E13 D5 2F13 F3 2J04 D3 2L25 A8 2N13 D8 2R02 A7 3309 B8 3348 D8 3388 D7 3721 B6 3736 B6 3751 B6 3937 B7 3A29 A9 3C06 C6 3D38 B4 3J01 D3 4117 E5 7C01 C5
1304 A9 1505 E9 1520 D9 1615 F9 1N01 F10 2117 F6 2318 C7 2421 B8 2444 B8 2908 B7 2A18 A9 2B19 B2 2C06 D5 2C29 C4 2E14 D5 2F20 D3 2J05 D3 2L26 A8 2N14 E8 2R11 A5 3310 C6 3349 D8 3393 B7 3722 B6 3737 B6 3752 B6 3938 B7 3A30 A9 3C29 C4 3D40 B4 3J02 D3 4120 E5 7C03 C3
1305 A3 1506 D10 1521 C10 1619 E9 1N02 D8 2119 E6 2323 C8 2422 B7 2445 B8 2913 B7 2A19 B9 2B21 B1 2C07 D5 2C33 C4 2E15 D5 2F21 D3 2J06 D3 2L27 A8 2N67 E10 2R20 A6 3311 B8 3350 D7 3395 B8 3723 A6 3738 B6 3753 B6 3A01 A9 3A31 A9 3C30 C4 3D43 B4 3J03 D3 4301 A7 7D01 B5
1306 A8 1507 E9 1522 D9 1901 B9 1R01 A6 2127 D6 2338 B8 2423 A8 2446 B8 2914 B7 2A20 B8 2B22 A1 2C08 D5 2C81 C4 2E16 D5 2F22 E3 2K06 F1 2L28 A8 2P28 A3 2R21 A6 3313 C7 3351 C8 3396 C6 3724 A6 3739 B6 3901 B7 3A02 A9 3B10 A2 3C31 C4 3D44 B5 3J14 B9 4313 C8 7D02 B4
3J15 B9 4323 C8 7G00 C2
3K00 F2 4401 A7 7H00 D2
3K01 F2 4402 A7 7H02 C3
3K02 E3 4407 B7 7J04 D3
3K03 F3 4408 B7 7J05 D3
3K05 F3 4409 B7 7K00 F2
3K09 F2 4410 B7 7K04 F3
3K12 F2 4411 B7 7L10 B8
3K15 E1 4412 B7 7M07 F7
3K16 E2 4902 B7 7N01 E7
3K18 F1 4H01 D2 7P06 A3
3K21 F2 4H02 D2 7P07 B3
3K25 E2 4H03 D3
3K26 E2 4H04 D2
3K27 F1 4H05 D2
Part 1 3K28
3K29
E2
F1
4J14
4J15
B9
B9
H_17370_023a.eps 3K30
3K31
E2
E2
4L03
4L20
C8
A7
3K32 E2 4L21 A8
3K33 E1 4L24 A8
3K34 F1 4L25 A8
3K49 E2 4L26 A8
3K50 E2 4N03 E7
3K51 F1 4N04 E7
3K52 F1 4N05 E7
3L01 C8 4R05 A6
3L02 C8 4R06 A6
3L03 C8 4R07 A6
3L04 B7 4R08 A6
3L05 C7 5111 F6
3L06 C8 5117 E6
3L07 C8 5201 B7
3L08 C8 5301 B7
3L09 C8 5306 C8
Part 2 3L11 C6 5401 B8
3L12 C8 5402 B8
H_17370_023b.eps 3L13 C8 5403 B8
3L15 C8 5700 A6
3L17 B7 5A03 A10
3L20 A7 5A04 B10
3L21 A8 5A05 A9
3L22 A8 5A06 A9
3L23 A8 5B01 B1
3L24 A8 5B05 B2
3L25 A8 5B08 A2
3L27 A8 5C06 C4
3L28 D8 5C08 C4
3L53 C8 5D03 A4
3L55 D8 5E04 C4
3L56 D8 5E05 C4
3L58 D8 5E06 D4
3L59 C6 5E16 D4
3L61 C8 5F10 D3
3L62 C8 5F11 D3
3L63 D8 5G01 C3
3L67 D7 5G02 C3
3L71 C8 5G04 D3
3L72 B8 5G06 C3
3L73 C8 5G07 C3
3L75 C8 5H01 D3
3L76 C8 5H02 D1
3L79 D8 5K03 F1
3L86 B7 5K04 D2
3L94 C8 5K05 D3
3L95 C8 5P01 A3
3N01 E7 5P02 A2
3N02 D7 5P09 B3
3N03 E7 6103 E6
Part 3 3N04 D7 6306 B9
3N05 D7 6307 B9
H_17370_023c.eps Part 4 3N06 D7 6317 B7
3N07 D7 6318 B8
H_17370_023d.eps 3N08 D7 6914 B7
3N09 D7 6B30 B2
3N10 D7 6J03 D3
3N11 D8 6J14 B9
3N12 D8 6J15 B9
3N13 E7 7109 E6
3N14 E7 7113 D6
3N15 E7 7201 B7
3N16 D7 7302 C8
3N22 D8 7303 C8
3N24 D8 7308 B7
3N33 D8 7311 C7
3N34 D8 7317 B7
H_17370_023.eps 3N39 E7 7322 C6
3139 123 6273.1 070804 3N40 E7 7323 C8
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 68

Layout SSB ( Part 1 Top Side)

Part 1

H_17370_023a.eps
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Circuit Diagrams and PWB Layouts LC7.5E LA 7. 69

Layout SSB ( Part 2 Top Side)

Part 2

H_17370_023b.eps
070804
Circuit Diagrams and PWB Layouts LC7.5E LA 7. 70

Layout SSB ( Part 3 Top Side)

Part 3

H_17370_023c.eps
070804

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