2021-22 ADE Lab Manual (New Syllabus)

CMR TECHNICAL CAMPUS
Approved by AICTE, Permanently Affiliated to JNTUH, Accredited by NAAC & NBA

Kandlakoya (V), Medchal Road, Hyderabad-501401, www.cmrtc.ac.in
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
CERTIFICATE
ACADEMIC YEAR: 2020-21
This is to certify that the bonafide record work done by
Mr./Ms. bearing
H.T.No _________________of II –B.Tech I-Semester in the Analog and
Digital Electronics Laboratory is satisfactory.
Faculty In-Charge
LIST OF EXPERIMENTS
A minimum of 12 experiments have to be performed.
1. Volt-Ampere characteristics of UJT.

2. Diode-Clippers.
3. Diode-Clampers.
4. Input and output characteristics of FET in CS configuration.
5. Common Source JFET Amplifier.
6. Realization of Boolean expressions using Gates .
7. Design and realization logic gates using universal gates.
8. Generation of clock using NAND/NOR gates.
9. Design a 4-bit adder/subtractor.
10. Design and realization of 8x1 MUX using 2x1 MUX.
11. Design and realization a synchronous and Asynchronous counter using flip-flops
12. Realization of logic gates using DTL, TTL, ECL, etc.
INDEX
Page No. Performed Faculty Remarks
Name of the Experiment
S.No Date Signature
bb
Analog and Digital Electronics Lab
EXPERIMENT-1
VOLT-AMPERE CHARACTERISTICS OF UJT
AIM: To study and plot the emitter characteristics (VE vs IE) of a UJT.
APPARATUS:
1.Bread Board
2.UJT
3.Regulated Power Supply
4.Digital Ammeter
5.Digital Voltmeter
6.Connecting Wires
CIRCUIT DIAGRAMS:
RBB
2N2646
RE IE (0-20mA) B2 1K
E
(0-30) v 1K
B1
VEE VE VBBI
(0-20V) VBB
(0-20V) (0-30v)
Pin assignment of UJT:

Emitter Base -1
Base - 2
Department of ECE, CMRTC Page 1

bb
THEORY:
The Uni-junction transistor is a 3-terminal solid-state device (emitter and the Two bases).
Fig (a) shows the symbol of UJT. A simplified equivalent circuit is shown in fig (b).
B2
RB2
E VBB
E B2
VE
D1 RB1 VRB1
B1
B1
Fig (a): Symbol of UJT Fig (b): Equivalent Circuit
This device has only one pn junction and hence it is known as Uni-junction transistor. The
PN emitter to base junction is shown as diode D1. The inter base resistance RBB of the N-type
Si bar appears as two resistors RB1 & RB2 where RBB equals the sum of RB1 & RB2. Referring
to the equivalent circuit.
I. When no voltage is applied between B1 and B2 with emitter open, the inter base
resistance is given by RBB = RB1 + RB2.
II. When a voltage VBB is applied between B1 and B2 with emitter open, voltage will divide
up across RB1 & RB2.
R B1 VRB1 R B1
VRB1   VBB , 
R B1  R B2 VBB R B1  R B2
R B1
VRB1 = VBB where = the intrinsic stand-off ratio 
R B1  R B2
The VBB across RB1 reverse biased diode thereby dropping the emitter current to zero.
III. When supply is connected at the emitter, the diode is forward biased making the input
voltage to exceed by VD
VP = VBB + VD
The emitter conductivity characteristics are such that as I E increases the emitter to base (B1)
voltage.Since the diode is conducting, the resistance between emitter and base (B1) reduces and
hence the internal drop from emitter to B1 decreases. At a peak point Vp and the valley point Vv, the
slope of the emitter characteristics is 0. At points to the left of VB the E-B1 is forward biased and IE
exists. Between Vp & Vv increase in IE is accompanied by a reduction in emitter voltage VE. This is
the negative resistance region of UJT. Beyond the valley point V v an increase in IE is accompanied

bb

by an increase in VE. This region is known as the saturation region.
PROCEDURE:
1. Make the connections as per circuit diagram.
2. Keep output voltage VBBI = 5V by varying VBB.
3. Varying VEE gradually, note down both emitter current IE and emitter voltage (VE).
4. Step Size is not fixed because of non linear curve and vary the X-axis variable (i.e. if
output variation is more, decrease input step size and vice versa).
5. Repeat above procedure (step 3) for VBBI =10V.
Observations :
VBB1 = 5V VBB1 = 10V
IE (mA) VE (V) IE (mA) VE (V)
Expected Graph: Plot the tabulated readings on a graph sheet with IE on X-axis and VE on
Y-axis.
Peak point
VE (V) saturation region
Cutoff Region -ve resistance
Region
Valley point
0 Ip IV IE (mA)
Inference:
1. There is a negative resistant region from peak point to valley point.
2. Increase in VBBI increases the value of peak and valley voltages.

bb
Precautions:
1. While doing the experiment do not exceed the ratings of the UJT. This may lead to
damage the UJT.
2. Connect voltmeter and Ammeter in correct polarities as shown in the Circuit diagram.
3 Do not switch ON the power supply unless you have checked the
Circuit connections as per the circuit diagram.
4. Make sure while selecting the emitter, base -1 and base – 2 terminals
Of the UJT.
Result: The emitter characteristics of UJT have been determined.
Viva-voce Questions
1. Specifications of UJT?
2. What is the importance of UJT?
3. When will be UJT is switched?
4. Why UJT is called as a relaxation oscillator?
5. What is a Relaxation Oscillator?

bb

bb
EXPERIMENT-2
DIODE CLIPPERS
AIM:
a) To study the clipping circuits using diodes.
b) To observe the transfer characteristics of all the clipping circuits in CRO
APPARATUS:
S.NO. Name Range Quantity
1 Signal Generator.
(0-1)MHz 1
Bread board
2 - 1
CRO (0-1)MHz
3 1
DC power supply (dual)
4 (0-20)V 1
Resistors (1 K, 10K)
5 - 1
6 Diodes (1N4007) - 2
- 10-15 Nos
Connecting patch cards.
7
THEORY:
Clipping circuits basically limit the amplitude of the input signal either below or above
certain voltage level. They are referred to as Voltage limiters, Amplitude selectors or
Slicers. A clipping circuit is one, in which a small section of input waveform is missing
or cut or truncated at the output section.
Clipping circuits are classified based on the position of Diode.
1. Series Diode Clipper
2. Shunt Diode Clipper

bb
PROCEDURE:
1. Connect the circuit as shown in fig.1

2. In each case apply 10 VP-P, 1 KHz Sine wave I/P using a signal generator.
3. O/P is taken across the load RL.
4. Observe the O/P waveform on the CRO and compare with I/P waveform.
5. Sketch the I/P as well as O/P waveforms and mark the numerical values.
6. Note the changes in the O/P due to variations in the reference voltage V R = 2V,
3V.
7. Obtain the transfer characteristics of Fig.1, by keeping CRO in X-Y mode.
8. Repeat the above steps for all the circuit.
PRECAUTIONS:
1. Set the CRO O/P channel in DC mode always.

2. Observe the waveform simultaneously by keeping common ground.
3. See that there is no DC component in the I/P.
4. To find transfer characteristics apply input to the X-Channel, O/P to Y-Channel,
adjust the dot at the center of the screen when CRO is in X-Y mode. Both the
channels must be in ground, then remove ground and plot the transfer
characteristics.

bb
Circuit Diagram Input &Output Wave Forms

bb
Circuit diagram O/P Wave Forms

bb
Circuit Diagrams Transfer Characteristics

bb
RESULT: Different types of clipping circuits have been studied and observed the responses
for various combinations of VR and clipping diodes.
CONCLUSION:
Viva Voce Questions:
1.Define clipping circuit?
2.What are the different types of clippers?
3.Which kind of a clipper is called a slicer circuit?
4.What are the disadvantages of the shunt clipper?

bb

bb

bb

bb

bb
EXPERIMENT-3
DIODE-CLAMPERS
AIM: To study the clamping circuits using diodes and capacitors.
APPARATUS:
S.NO. Name Range Quantity
1 Signal Generator. (0-1)MHz 1
2 Bread board - 1
3 CRO (0-1)MHz 1
4 DC power supply (dual) (0-20)V

Resistors(100K),Capacitor(0.
5 - Each 1 No.
1f)
6 Diodes (1N4007) - 1
Connecting patch cards.
7 - 10-15 No’s
THEORY:
Clamping circuits add a DC level to an AC signal. A clamper is also refer to

as DC restorer or DC re-inserter. The Clampers which clamp the given
waveform either above or below the reference level, which are known as
positive or negative clamping respectively.
PROCEDURE:
1. Connect the circuit as per circuit diagram.
2. Apply a Sine wave of 10VP-P, 1 KHz at the input terminals with the help of
Signal Generator.
3. Observe the I/P & O/P waveforms of CRO and plot the waveforms and mark
the values with VR = 2 V, 3V
4. O/P is taken across the load RL.
5. Repeat the above steps for all clamping circuits as shown.
6. Waveforms are drawn assuming diode is ideal.

bb
CIRCUIT DIAGRAM I/P & O/P WAVE FORMS
Vi =5V
-5V
C1
V1 0.1uF R1
0.5V
10V D1
7.07V_rms 100kohm
1000Hz 1N4007GP
0Deg
-9.5V
C1
V0
V1 0.1uF
9.5V
10V R1
D1
7.07V_rms 100kohm 5V
1N4007GP
1000Hz
0Deg
-0.5V
C1
0.1uF D1
1N4007GP
V1
10V R1 -1.5V
7.07V_rms 100kohm
1000Hz
V2 -6.5V
0Deg
2V
-11.5V

bb
Circuit diagram O/P Wave forms
RESULT:
bb
Different types of clamping circuits are studied and observed the response for different combinations
Of VR and diodes.
CONCLUSION:
VIVA VOCE QUESTIONS:
1. What are the applications of clamping circuits?
2. What is the synchronized clamping?
3. Why is a clamper called a dc inserter?
4. What is clamping circuit theorem. How does the modified clamping Circuit theorem differs from
this?
5. Differentiate –ve clamping circuit from +ve clamping circuits in the above circuits?

bb

bb

bb
EXPERIMENT-4
INPUT AND OUTPUT CHARACTERISTICS OF FET IN CS
CONFIGURATION
AIM:
To conduct an experiment on a given JFET and obtain
1.Drain characteristics
2.Transfer Characteristics.
3.To find rd, gm, and μ from the characteristics.
APPARATUS:
1. FET Trainer Kit
2. Digital Voltmeter (0-20V)
3. Digital Ammeter (0-20mA)
4. Patch Chords
THEORY:
The common-source (CS) amplifier may be viewed as a transconductance amplifier or
as a voltage amplifier. (See classification of amplifiers). As a transconductance amplifier, the
input voltage is seen as modulating the current going to the load. As a voltage amplifier, input
voltage modulates the amount of current flowing through the FET, changing the voltage across
the output resistance according to Ohm's law. However, the FET device's output resistance
typically is not high enough for a reasonable transconductance amplifier (ideally infinite), nor
low enough for a decent voltage amplifier (ideally zero). Another major drawback is the
amplifier's limited high-frequency response.
CIRCUIT DIAGRAM: ID (0-200mA) 1k
68K D
G ID BFW10
S
VDD(0-30V)
VGG VDS (0–20V

(0-30V)
VGS(0–20V)

bb
PROCEDURE:
DRAIN CHARACTERISTICS:
1. Make the connections as per the circuit and start with VGG and VDD keeping at zero volts.
2. Keep VGG such that VGS = 0 volts, Now vary VDD such that VDS Varies in steps of 1 volt up
to 10 volts. And Note down the corresponding Drain current I D
3. Repeat the above experiment with VGS = -1V and -2V and tabulate the readings.
4. Draw a graph VDS Vs ID against VGS as parameter on graph.
5. From the above graph calculate rd and note down the corresponding diode current against
the voltage in the tabular form.
6.Draw the graph between voltages across the Diode Vs Current through the diode in the first
quadrant as shown in fig.
TRANSFER CHARACTERISTICS:
7.Set VGG and VDD at zero volts .keep VDS = 1Volt.

8. Vary VGG such that VGS varies in steps of 0.5 volts. Note down the corresponding Drain
current ID, until ID = 0mA and Tabulate the readings.
9. Repeat the above experiment for VDS = 3.0 Volts and 5.0 Volts and tabulate the readings.
10.Draw graph between VGS Vs ID with VDS as parameter.
11. From the graph find g m.
12. Now μ = gm x rd.

bb
TABULAR FORM:
DRAIN CHARACTERISTICS:
S.No VGS = 0 volts VGS = -1V VGS = -2V

VDS (V) ID (mA) ID (mA) ID (mA)
TRANSFER CHARACTERISTICS:
VDS = 1.0V VDS = 3.0V VDS = 5.0V

S.No
VGS (V) ID (mA) ID (mA) ID (mA)

bb
MODEL GRAPH:
CALCULATIONS:
CALCULATION OF rd :
Construct a Triangle on one of the output characteristic for a particular V GS in the active
region and find ΔVDS and ΔI D
Now rd = ΔVDS/ ΔID (VGS = constant)
CALCULATION OF gm :
Construct a Triangle on one of the Transfer characteristics for a particular V DS

find ΔVGS and ΔID.
Now gm = ΔID/Δ VGS (VDS = constant).
CALCULATION OF μ:
μ = gm*rd= ____________
PRECAUTIONS:
1. While doing the experiment do not exceed the ratings of the FET. This may lead to damage the FET.
2. Connect voltmeter and Ammeter in correct polarities as shown in the Circuit diagram.
3. Do not switch ON the power supply unless you have checked the Circuit connections as per the circuit
diagram.
4. Make sure while selecting the Source, Drain and Gate terminals Of the FET.

bb
RESULT:
1. Drain Resistance (rd) = ………….
2. Tran conductance (gm) = ………….
3. Amplification factor () = ……………
CONCLUSION:
VIVA QUESTIONS:
1. Why FET is called as a unipolar transistor?
2. What are the advantages of FET?
3. What is the difference between MOSFET and FET?
4. What is Trans conductance?
5. State weather FET is voltage controlled or current controlled and also state the reason?

bb
EXPERIMENT-5
COMMON SOURCE JFET AMPLIFIER
AIM: To Study the common source amplifier and to find
1. Cut off frequencies.
2. Bandwidth.
3. Gain.
APPARATUS:
1. CS(FET) Amplifier Kit
2. CRO
3. Function Generator
4. BNC Probes
5. Patch Chords
THEORY:
The common-source (CS) amplifier may be viewed as a
transconductance amplifier or as a voltage amplifier. (See classification of amplifiers). As
a transconductance amplifier, the input voltage is seen as modulating the current going to
the load. As a voltage amplifier, input voltage modulates the amount of current flowing
through the FET, changing the voltage across the output resistance according to Ohm's
law. However, the FET device's output resistance typically is not high enough for a
reasonable transconductance amplifier (ideally infinite), nor low enough for a decent
voltage amplifier (ideally zero). Another major drawback is the amplifier's limited high-
frequency response. Therefore, in practice the output often is routed through either a
voltage follower (common-drain or CD stage), or a current follower (common-gate or CG
stage), to obtain more favorable output and frequency characteristics.

bb
CIRCUIT DIAGRAM:
PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Set Source Voltage Vs = 50mV (say) at 1 KHz frequency, using function generator.
3. Keeping the input voltage constant vary the frequency from 50Hz to 1MHz in regular steps and
note down the corresponding output voltage.
4. Plot the Graph: gain (dB) Vs frequency.
5. Calculate the bandwidth, gain and cut off frequencies from Graph.

bb
TABULAR FORM:
Input Voltage (vi) =
O/P Voltage, Voltage Gain
S.No Frequency (Hz) Vo (V) Av =Vo/Vi Av in dB= 20 log (Av)
MODEL GRAPH:
PRECAUTIONS:
1. Check the wires for continuity before use.
2. Keep the power supply at zero volts before starting the experiment.
3. All the contacts must be intact.
4. For a good JFET ID will be ≥ 11.0 mA at VGS = 0.0 volts if not change the JFET.

bb
RESULT:
Cut off Frequencies FH=___________Hz, FL=______________Hz
Bandwidth B.W = FH-FL = _______________Hz
Maximum Gain = ______________
3db Gain = Maximum Gain -3db = ______________
CONCLUSION:
VIVA QUESTIONS:
1.What are the advantages of JFET over BJT?
2.Why input resistance in FET amplifier is more than the BJT amplifier?
3.What is a uni-polar device?
4.What is pinch off voltage?
5.What are various FETs?

bb

bb
EXPERIMENT-6
REALIZATION OF BOOLEAN EXPRESSIONS USING GATES
AIM: Realization of Boolean expressions by using logic gates.
APPARATUS REQUIRED: IC 7420, Trainer kit, connecting wires, patch cards.
THEORY:
The Boolean function can be represented easily in SOP (sum of products) form and POS
(product of sums) form. To represent these standardized equations logically, we use the logic
gates.Any Boolean function can be represented by using a number of logic gates by
interconnecting them. Logic gates implementation or logic representation of Boolean
functions is very simple and easy form.The implementation of Boolean functions by using
logic gates involves in connecting one logic gate’s output to another gate’s input and involves
in using AND, OR, NAND and NOR gates. Laws and theorems of Boolean logic are used to
manipulate the Boolean expressions and logic gates are used to implement these Boolean
expressions in digital electronics. AND gate, OR gate and NOT gate are the three basic logic
gates used in digital electronics
CIRCUIT DIAGRAM:
NOT/COMPLEMENT GATE:
F=x’
Truth table:

bb
AND Gate:
F=xy
Truth table:
OR Gate:
F=x+y
Truth table:
NAND Gate:
F= (xy)’
Truth table:

bb
NOR Gate:
F=(x+y)’
Truth table:
EX-OR Gate:
F=(xy’+x’y)
Truth table:
EX-NOR Gate:
F= (xy’+x’y)’
Truth table:

bb
PROCEDURE:
PART (A):
1. Supply connections are given at the corresponding pins of ICs.
2. Each IC is taken separately and the individual gates in each IC are tested by giving inputs and the
truth tables are verified.
3. Same procedure is repeated for all ICs.
PART (B):
1. Connect the circuit as per the given expression
F=(x+Y)’+y
F=(xy)’+x
F=(xy’+x’y)
F=(xy’+x’y)’
PRECAUTIONS:
1. The power supply pins must be checked whether power is available at
those pins using test probes.
2. No loose connections should be there and care must be taken to avoid
shorting of pins.
RESULT:
CONCLUSION:
VIVA QUESTIONS:
1. Which logic gate gives the ouput logic high when if any one of input is high.
2. Which logic gate gives the ouput logic 0 when if any one of input is high.
3.Which logic gate gives the ouput logic high when both the inputs given as same.

bb
EXPERIMENT-7
DESIGN AND REALIZATION OF LOGIC GATES USING
UNIVERSAL GATES
AIM: To verify NAND and NOR as universal gates
APPARATUS REQUIRED: IC 7420, Trainer kit, connecting wires, patch cards.
THEORY:
NAND gate is actually a combination of two logic gates: AND gate followed by NOT
gate. So its output is complement of the output of an AND gate. This gate can have minimum
two inputs, output is always one. By using only NAND gates, we can realize all logic
functions: AND,OR, NOT, X-OR, X-NOR, NOR. So this gate is also called universal gate.
NOR gate is actually a combination of two logic gates: OR gate followed by NOT gate.
So its output is complement of the output of an AND gate. This gate can have minimum two
inputs, output is always one. By using only NAND gates, we can realize all logic functions:
AND, OR, NOT, X-OR, X-NOR, NOR. So this gate is also called universal gate.
CIRCUIT DIAGRAMS:
REALIZATION OF BASIC GATE OPERATIONS USING NAND GATES:
1. AND OPERATION:
00
1 00
31
2 3
2
2. NOT OPERATION:
03
1
3
2

bb
3. OR OPERATION:
03
1
3
2
03
1
3
2
03
1
3
2
4. XOR & XNOR OPERATION:
REALIZATION OF BASIC GATE OPERATIONS USING NOR GATE:
1. AND OPERATION:
02
2
1
3
02
2
1
3
02
2
1
3
2.NOT OPERATION:
02
2
1
3
3. OR OPERATION:
02
2 02
1 2
3 1
3

bb
4. XNOR & XOR OPERATION:
PROCEDURE:
PART (A):
2. Each IC is taken separately and the individual gates in each IC are tested by giving inputs
and the truth tables are verified.
3. Same procedure is repeated for all ICs.
PART (B):
5. For realization of individual gates using NAND gates alone, the connections are made as
per the logic diagrams.
6. Inputs are given and the truth tables of individual gates are verified.
7. The same procedure is repeated for realization of individual gates using NOR gates.

bb
PRECAUTIONS:
1. The power supply pins must be checked whether power is available at those pins using test
probes.
2. No loose connections should be there and care must be taken to avoid shorting of pins.
RESULT:
The truth tables of individual gates are verified and their realizations using
NAND gates alone and NOR gates alone have been verified.
CONCLUSION:
VIVA QUESTIONS:
1. If one of the inputs of an EX-OR gate is high, its output will be--------
2.To DISABLE a NOR gate one of its inputs needs to be connected to logic level-------------
3.What is the difference between a positive logic system and negative logic system?
4.What are universal gates? Why that name?
5.Minimum number of NAND gates necessary to realize EX-OR gate using NAND gates only
is --------.
6.Minimum number of NOR gates necessary to realize EX-OR gate using NOR gates only is

bb
EXPERIMENT-8
GENERATION OF CLOCK USING NAND / NOR GATES
AIM: To Study and implement the generation of clock using NAND/NOR gates
APPARATUS:
1) Trainer kit
2) Patch chords
3) CRO
4) Power supply
THEORY:
A clock generator is a circuit that produces a timing signal (known as a clock signal and
behaves as such) for use in synchronizing a circuit's operation. The signal can range from a
simple symmetrical square wave to more complex arrangements. The basic parts that all clock
generators share are a resonant circuit and an amplifier. Since all logic operations in a
synchronous machine occur in synchronism with a clock, the system clock becomes the basic
timing unit. The system clock must provide a periodic wave forms that can be used as a
synchronous signal. The square waveform is a typical clock waveform used in a digital
system.
The clock defines a basic timing interval during which logic operation must be
performed. This basic timing interval is defined as a clock cycle time and is equal to one
period of the clock waveform. Thus all logic elements, flip-flops, gates, and so on must
complete their transition in less than one clock cycle time. In this experiment to generating the
clock we are using the NAND and NOR gates using these gates we generating the 450KHZ
clock signal.

bb
CIRCUIT DIAGRAM:
PROCEDURE:
1) Connect the power chord to the mains power supply
2) Turn on the trainer kit you can observe the led indication on the kit.
3) Now connect the CRO probe in channel ‘1’ to the NAND gate and connect the positive to
the output of the circuit and negative to the ground.
4) Observe the waveform on the CRO and note down the waveform time period and
amplitude of the signal.
5) Plot the graph for the above readings.

6) The above steps repeated for the NOR gate also.
EXPECTED WAVEFORMS:

bb
RESULT:
For NAND Gate, Time Period T = ___________Sec & Frequency = ____________Hz
For NOR Gate, Time Period T = _____________Sec & Frequency = ____________Hz
CONCLUSION:
VIVA QUESTIONS:
1. What is clock? What is the use of click in digital circuits?
2. How to generate clock signals?
3. What is the range of clock signals used in digital circuits?
4. How to calculate time and frequency from the graph?
5. Give some Clock generator Circuits

bb
EXPERIMENT-9
DESIGN A 4 – BIT ADDER / SUBTRACTOR
AIM: To construct the 4 Bit Adder and Subtractor
APPARATUS:
1.Physitech’s 4 Bit adder/subtractor trainer kit

2.Patch chords
3.Power supply
THEORY:
A Binary Subtractor is a decision making circuit that subtracts two binary numbers
from each other, for example, X – Y to find the resulting difference between the two numbers.
Unlike the Binary Adder which produces a SUM and a CARRY bit when two binary
numbers are added together, the binary subtractor produces a DIFFERENCE, D by using a
BORROW bit, B from the previous column. Then obviously, the operation of subtraction is
the opposite to that of addition. We learnt from our maths lessons at school that the minus
sign, “–” is used for a subtraction calculation, and when one number is subtracted from
another, a borrow is required if the subtrahend is greater than the minuend. Consider the
simple subtraction of the two denary (base 10) numbers below. We cannot directly subtract 8
from 3 in the first column as 8 is greater than 3, so we have to borrow a 10, the base number,
from the next column and add it to the minuend to produce 13 minus 8. This “borrowed” 10 is
then return back to the subtrahend of the next column once the difference is found. Simple
school math’s, borrow a 10 if needed, find the difference and return the borrow. The
subtraction of one binary number from another is exactly the same idea as that for subtracting
two decimal numbers but as the binary number system is a Base-2 numbering system which
uses “0” and “1” as its two independent digits, large binary numbers which are to be
subtracted from each other are therefore represented in terms of “0’s” and “1’s”. Binary
Subtraction can take many forms but the rules for subtraction are the same whichever process
you use. As binary notation only has two digits, subtracting a “0” from a “0” or a “1” leaves
the result unchanged as 0-0 = 0 and 1-0 = 1. Subtracting a “1” from a “1” results in a “0”, but
subtracting a “1” from a “0” requires a borrow. In other words 0 – 1requires a borrow. For the

bb
simple 1-bit subtraction problem above, if the borrow bit is ignored the result of their binary
subtraction resembles that of an Exclusive-OR Gate. To prevent any confusion in this tutorial
between a binary subtractor input labelled, B and the resulting borrow bit output from the
binary subtractor also being labelled, B, we will label the two input bits as X for the minuend
and Y for the subtrahend. Then the resulting truth table is the difference between the two
input bits of a single binary subtractor. As with the Binary Adder, the difference between the
two digits is only a “1” when these two inputs are not equal as given by the Ex-OR
expression. However, we need an additional output to produce the borrow bit when input X =
0 and Y = 1. Unfortunately there are no standard logic gates that will produce an output for
this particular combination of X and Y inputs. But we know that an AND Gate produces an
output “1” when both of its inputs X and Y are “1” (HIGH) so if we use an inverter or NOT
Gate to complement the input X before it is fed to the AND gate, we can produce the required
borrow output when X = 0 and Y = 1. If we wanted to use the 4-bit adder for addition once
again, all we would need to do is set the carry-in (CIN) input LOW at logic “0”. Because we
can use the 4-bit adder IC such as the 74LS83 or 74LS283 as a full-adder or a full-subtractor
they are available as a single adder/subtractor circuit with a single control input for selecting
between the two operations.
PIN CONFIGRATION:

bb
CIRCUIT DIAGRAM:
PROCEDURE:
1.Connect the circuit as per circuit diagram
2.Connect A0, A1, A2, A3 to the Input Switches provided on the trainer kit.
3.Connect the X-OR Gates outputs to IC 74LS83 B0, B1, B2, B3 terminals as shown in above
circuit diagram.
4.Connect the input terminal of X-OR Gates to Input switches provided on trainer kit and
consider as B0, B1, B2, B3.
5.Connect E0, E1, E2, E3 terminal of the IC 74LS83 to the output indicators (LED’S).
6.Connect the Cin terminal to another X-OR Gate I/P terminal, provided on the trainer and the
same Cin to 0/Gnd or 1/High for Adder and Subtractor (0/Gnd is for Adder and 1/High is for
Subtractor).
7.Connect the C0 and B0 terminals to output indicators(LED’S).
8.Verify the Truth Table given below.

bb
TRUTH TABLE:
4 BIT ADDERS:
INPUTS OUTPUTS
A3 A2 A1 A0 B3 B2 B1 B0 COut E3 E2 E1 E0
1 0 0 0 0 0 1 0 0 1 0 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0
1 0 1 0 1 0 1 1 1 0 1 0 1
0 1 1 0 0 0 1 1 0 1 0 0 1
1 1 1 0 1 1 1 1 1 1 1 0 1
1 0 1 0 1 1 0 1 1 0 1 1 1
4 BIT SUBTRACTOR:
INPUTS OUTPUTS
A3 A2 A1 A0 B3 B2 B1 B0 BOut E3 E2 E1 E0
1 0 0 0 0 0 1 0 0 0 1 1 0
1 0 0 0 1 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 1 1 0 1 0
0 0 0 1 0 1 1 1 1 1 0 1 0
1 0 1 0 1 0 1 1 1 1 1 1 1
0 1 1 0 0 0 1 1 0 0 0 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1
1 0 1 0 1 1 0 1 1 1 1 0 1
RESULT:
CONCLUSION:
VIVA QUESTIONS:
1. What is adder? What is subtractor?
2. Is Full adder is used to perform subtraction? & Explain
3. Draw full adder circuits with truth table?
4. Draw full subtractor circuits with truth table?

bb

bb
EXPERIMENT-10
DESIGN AND REALIZATION OF 8X1 MUX USING 2X1 MUX
AIM: To Design a 8:1 Multiplexer using 2:1 Multiplexers
APPARATUS:
1. Physitech’s 8:1 Multiplexer using 2:1 Multiplexers trainer kit.
2. Patch Cords.
THEORY:
Multiplexer is one of the basic building units of a computer system which in principle
allows sharing of a common line by more than one input lines. It connects multiple input lines
to a single output line. At a specific time one of the input lines is selected and the selected input
is passed on to the output line.
The multiplexer or MUX is a digital switch, also called as data selector. It is a
combinational circuit with more than one input line, one output line and more than one select
line. It allows the binary information from several input lines or sources and depending on the
set of select lines, particular input line is routed onto a single output line.
2-TO-1 MULTIPLEXER
A 2-to-1 multiplexer consists of two inputs D0 and D1, one select input S and one
output Y. Depends on the select signal, the output is connected to either of the inputs. Since
there are two input signals only two ways are possible to connect the inputs to the outputs, so
one select is needed to do these operations.
If the select line is low, then the output will be switched to D0 input, whereas if
select line is high, then the output will be switched to D1 input. The figure below shows the
block diagram of a 2-to-1 multiplexer which connects two 1-bit inputs to a common
destination.

bb
The truth table of the 2-to-1 multiplexer is shown below. Depending on the selector
switching the inputs are produced at outputs , i.e., D0 , D1 and are switched to the output for
S=0 and S=1 respectively . Thus, the Boolean expression for the output becomes D0 when S=0
and output is D1 when S=1.
From the truth table the Boolean expression of the output is given as
4- TO-1 MULTIPLEXER
A 4-to-1 multiplexer consists four data input lines as D0 to D3, two select lines as S0
and S1 and a single output line Y. The select lines S1 and S2 select one of the four input lines
to connect the output line. The particular input combination on select lines selects one of input
(D0 through D3) to the output. The figure below shows the block diagram of a 4-to-1
multiplexer in which the multiplexer decodes the input through select line

bb
The truth table of a 4-to-1 multiplexer is shown below in which four input combinations
00, 10, 01 and 11 on the select lines respectively switches the inputs D0, D2, D1 and D3 to the
output. That means when S1=0 and S0 =0, the output at Y is D0, similarly Y is D1 if the select
inputs S1=0 and S0= 1 and so on.

bb
PIN CONFIGRATION:
CIRCUIT DIAGRAM:

bb
PROCEDURE:
1. Connect the circuit as per circuit diagram.
2. Connect D0 to D7 to the input switches provided on the trainer kit.
3. Connect Selection line Inputs to the Input switches.
4. Connect the Output terminal “Y” to the Output indicator (LED).
5. Verify the truth table given below.
TRUTH TABLE:
Selection Inputs Output
S2 S1 S0 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

RESULT:
CONCLUSION:
VIVA:
1. What is a Multiplexer?
2. What is the difference between Mux and De-Mux?
3. What is function of enable input on a Multiplexer?
4. How many select lines are required for 8:1 Mux?

bb
EXPERIMENT-11
DESIGN AND REALIZATION A SYNCHRONOUS AND
ASYNCHRONOUS COUNTER USING FLIP-FLOPS
AIM:
To Design a synchronous and Asynchronous counter using flip-flops
APPARATUS:
1.Physitech’s Synchronous and Asynchronous counter using flip-flops

2.Patch Cords- 24No’s.
THEORY:
Synchronous Counter:
Synchronous Counters are so called because the clock input of all the individual flip-flops
within the counter are all clocked together at the same time by the same clock signal. It can be
seen above, that the external clock pulses (pulses to be counted) are fed directly to each of the J-
K flip-flops in the counter chain and that both the J and K inputs are all tied together in toggle
mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH, logic “1”
allowing the flip-flop to toggle on every clock pulse. Then the synchronous counter follows a
predetermined sequence of states in response to the common clock signal, advancing one state
for each pulse. The J and K inputs of flip-flop FFB are connected directly to the output QA of
flip-flop FFA, but the J and K inputs of flip-flops FFC and FFD are driven from separate AND
gates which are also supplied with signals from the input and output of the previous stage. These
additional AND gates generate the required logic for the JK inputs of the next stage. If we enable
each JK flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q) are
“HIGH” we can obtain the same counting sequence as with the asynchronous circuit but without
the ripple effect, since each flip-flop in this circuit will be clocked at exactly the same time.
Asynchronous Counter:
An Asynchronous counter can have 2n-1 possible counting states e.g. MOD-16 for a 4-bit
counter, (0-15) making it ideal for use in Frequency Division applications. But it is also possible
to use the basic asynchronous counter configuration to construct special counters with counting
states less than their maximum output number. For example, modulo or MOD counters. This is
achieved by forcing the counter to reset itself to zero at a pre-determined value producing a type
of asynchronous counter that has truncated sequences. Then an n-bit counter that counts up to its

bb
maximum modulus ( 2n ) is called a full sequence counter and a n-bit counter whose modulus is
less than the maximum possible is called a truncated counter. But why would we want to create
an asynchronous truncated counter that is not a MOD-4, MOD-8, or some other modulus that is
equal to the power of two. The answer is that we can by using combinational logic to take
advantage of the asynchronous inputs on the flip-flop. If we take the modulo-16 asynchronous
counter and modified it with additional logic gates it can be made to give a decade (divide-by-
10) counter output for use in standard decimal counting and arithmetic circuits. Such counters
are generally referred to as Decade Counters. A decade counter requires resetting to zero when
the output count reaches the decimal value of 10, ie. when DCBA = 1010 and to do this we need
to feed this condition back to the reset input. A counter with a count sequence from binary
“0000” (BCD = “0”) through to “1001” (BCD = “9”) is generally referred to as a BCD binary-
coded-decimal counter because its ten state sequence is that of a BCD code but binary decade
counters are more common.
CIRCUIT DIAGRAM:
SYNCHRONOUS UP COUNTER:

bb
SYNCHRONOUS DOWN COUNTER:
ASYNCHRONOUS UP COUNTER:
ASYNCHRONOUS DOWN COUNTER:
PROCEDURE:
1.Connect the circuit as per circuit diagram.
2.Verify the truth tables as given below.

bb
TRUTH TABLE:
SYNCHRONOUS/ASYNCHRONOUS UP COUNTER:
Clock Q4 Q3 Q2 Q1 Output Output in

Pulse in (LED’s) 7seg. Disp
1st L L L L 0 0
2nd L L L H 1 1
3rd L L H L 10 2
4th L L H H 11 3
5th L H L L 100 4
6th L H L H 101 5
7th L H H L 110 6
8th L H H H 111 7
9th H L L L 1000 8
10th H L L H 1001 9
11th H L H L 1010 10
12th H L H H 1011 11
13th 1 1 0 0 1100 12
14th 1 1 0 1 1101 13
15th H H H L 1110 14
16th H H H H 1111 15
SYNCHRONOUS/ASYNCHRONOUS DOWN COUNTER:
Clock Q4 Q3 Q2 Q1 Output Output in

Pulse in (LED’s) 7seg. Disp
16th H H H H 1111 15
15th H H H L 1110 14
14th 1 1 0 1 1101 13
13th 1 1 0 0 1100 12
12th H L H H 1011 11
11th H L H L 1010 10
10th H L L H 1001 9
9th H L L L 1000 8
8th L H H H 111 7
7th L H H L 110 6
6th L H L H 101 5
5th L H L L 100 4
4th L L H H 11 3
3rd L L H L 10 2
2nd L L L H 1 1
1st L L L L 0 0

bb
PRECAUTIONS:
1. No pins must be left open. If we are not using particular pins in that
application, disable those pins.
2. Care has to be taken in identifying the LSB and MSBs.
3. Avoid loose connections and shorting of pins
RESULT:
CONCLUSION:
VIVA QUESTIONS:
1.What is counter?
2.What is up counter?
3.What is down counter?
4.What is Synchronous counter?
5.What is Asynchronous counter?
6. Distinghish Synchronous counter & Asynchronous counter?

bb
EXPERIMENT-12
Realization of logic gates using DTL,TTL,ECL,etc.
AIM:
To understand basic gate operation of following logic families:

1.Diode Transistor Logic (DTL),
2.Transistor Transistor Logic (TTL),
3.Emitter Coupled Logic (ECL),
4.Complementary MOS (CMOS).
APPARATUS:
1.Physitech’s Realization of Logics Gates using DTL, TTL, ECL and CMOS Logics Trainer kit.
2.Patch Cords.
THEORY:
Simple digital logic gates can be made by combining transistors, diodes and resistors as
discrete components. Let us investigate some of such circuits using Diode-Transistor Logic
(DTL) and Transistor- Transistor Logic (TTL) as described below.
(i) Diode-Transistor Logic (DTL):

The simple 2-input Diode-Resistor gate can be converted into a NAND/NOR universal
gate by the addition of a single transistor inverting (NOT) stage employing DTL. Diode-
Transistor Logic, or DTL, refers to the technology for designing and fabricating digital circuits
wherein logic gates employ diodes in the input stage and bipolar junction transistors at the output
stage. The output BJT switches between its cut-off and saturation regions to create logic 1 and 0,
respectively. The logic level shift problem of DRL gates is not present in DTL and TTL gates so
that gates may be connected in series indefinitely. If a gate drives several similar gates in parallel
problems may occur: the maximum number of gates that can be driven in parallel is identified as
the "fanout" of a gate. DTL offers better noise margins and greater fan-outs than RTL (Resistor-
Transistor Logic),but suffers from low speed, especially in comparison to TTL. Diodes take up
far less room than resistors, and can be constructed easily. In addition, the internal resistance of a
diode is small when the diode is forward biased, thus allowing for faster switching action. As a
result, gates built with diodes in place of most resistors can operate at higher frequencies.

bb
Because of this diode-transistor logic (DTL) rapidly replaced RTL in most digital applications.
DTL Inverter Circuit:
The DTL inverter uses a transistor and a collector load resistor as shown in the circuit
diagram. The input is connected through a pair of diodes in series with the base of the transistor.
The diode connected directly to the transistor base serves to raise the input voltage required to
turn the transistor on to about 1.3 to 1.4 volts. Any input voltage below this threshold will hold
the transistor off. The base resistor is also connected which should be sufficient to turn the
transistor on and off quickly thus enabling higher switching speeds.
CIRCUIT DIAGRAM FOR DTL INVERTER CIRCUIT:
DTL NAND Circuit:

The DTL NAND gate combines the DTL inverter with a simple Diode-Resistor
Logic(DRL) AND gate as shown in its circuit diagram. Thus, any number of inputs can be added
simply by adding input diodes to the circuit. The problem of signal degradation caused by Diode
Logic is overcome by the transistor, which amplifies the signal while inverting it. This means
DTL gates can be cascaded to any required extent, without losing the digital signal.

bb
CIRCUIT DIAGRAM FOR DTL NAND CIRCUIT:
DTL NOR CIRCUIT:

Similar to DTL NAND circuit one can construct the NOR gate by using a DRL OR gate
followed by a transistor inverter, as shown in circuit diagram (i). One can also construct a DTL
NOR more elegantly by combining multiple DTL inverters with a common output as shown in
the schematic diagram (ii). Any number of inverters may be combined in this fashion to allow
the required number of inputs to the NOR gate. (You should try both the circuits!)
CIRCUIT DIAGRAM FOR DTL NOR CIRCUIT:

bb
PROCEDURE:
1.Connect the circuit as shown in the circuit diagrams.
2.Switch ON the trainer kit.
3.Verify the truth tables given below.
TRUTH TABLES:
A B Q=(A+B)’
0 0 1 A B Q=(A.B)’
A Q=A’ 0 1 0 0 0 1
0 1 0 1 1
1 0 0
1 0 1 0 1
1 1 0
1 1 0
Logic “NOT” Operation Logic “NOR” Operation Logic “NAND” Operation
(ii) TRANSISTOR- TRANSISTOR LOGIC (TTL):
Transistor-transistor logic uses bipolar transistors in the input and output stages. TTL is
commonly found in relatively low speed applications. Thus before using commercial ICs that
uses TTL, let’s first understand the circuit in discrete form.
TTL Inverter Circuit:

Looking at the DTL inverter circuit, one can note that the two diodes are opposed to each other
in direction. That is, their P-type anodes are connected together and to the pull-up resistor, while

bb
one cathode is the signal input and the other is connected to the transistor's base. Thus, one can
replace these two diodes with a single NPN transistor as shown in the circuit diagram. This
makes lot of sense owing to the fact that the amount of space required by a transistor in an IC is
essentially the same as the space required by a diode and by eliminating the space required by
one diode at the same time.
CIRCUIT DIAGRAM FOR TTL NOT CIRCUIT:
TTL NOR Circuit:

TTL integrated circuits provide multiple inputs to NAND gates by designing transistors with
multiple emitters on the chip. Unfortunately, we can't very well simulate that on a breadboard
socket. However, a NOR gate can be designed using an extra inverter transistors just as in the
case of DTL NOR gate.
CIRCUIT DIAGRAM FOR TTL NOR CIRCUIT:
PROCEDURE:

2. Switch ON the trainer kit.

bb
TRUTH TABLES:
A Q=A’ A B Q=(A+B)’
0 0 1
0 1
0 1 0
1 0
1 0 0
1 1 0
Logic “NOT” Operation Logic “NOR” Operation
ECL INVERTER CIRCUIT:

Emitter-coupled logic is a high-speed bipolar logic family. To get familiar with this logic, let’s examine
an ECL inverter/buffer as shown in Figure 1. In this figure, Vin is the input of the gate, Vout− is the
inverted version of Vin and Vout+ is the complement of Vout−. In this particular example, Vout+ can be
considered as the buffered version of the input. Moreover, VBB is an appropriate voltage (4V in Figure
1). Let’s define the logic high and logic low as 4.4 V and 3.6 V, respectively, and examine the operation
of the circuit.
Note:where R1,R2,R2=1KΩ
Assume that Vin is logic high (4.4 V), hence the emitter of Q1 will be about 4.4-0.6=3.8 V.
Therefore, the base-emitter voltage of Q2 will be 0.2 V. This base-emitter voltage is not
sufficient to turn Q2 on. Hence, the resistor R2 will pull the collector of Q2 up to Vcc=5 V. To
calculate the collector voltage Vc1, we should note that the current flowing through R3, which is
3.8V1.3kΩ=2.92mA, will go through Q1. Hence, we obtain Vc1=5V−300Ω×2.92mA=4.12V (to
simplify the calculations, we’ve assumed that the collector current is equal to the emitter
current). The emitter followers Q3 and Q4 will act as buffers to pass the (DC level shifted)

bb
collector voltages of Q1 and Q2 to the final outputs of the ECL gate, Vout− and Vout+.
Assuming a base-emitter voltage of 0.6V for Q3 and Q4, we obtain Vout+=4.4V and Vout−
=3.52V. As you can see, applying logic high to the input gives a logic high at Vout+ and a
voltage level very close to the defined logic low (3.6 V) at Vout−. Hence, the circuit of Figure 1
serves as an inverter/buffer. If we apply the logic-low voltage (3.6V) to the input of the gate, Q2
will turn on and Q1 will be off. This will lead to a logic high at Vout− and a voltage level very
close to the logic low (3.61 V) at Vout+
(iii) CMOS INVERTER CIRCUIT:

CMOS circuits are constructed in such a way that all P-type metal-oxide-semiconductor
(PMOS) transistors must have either an input from the voltage source or from another PMOS
transistor. Similarly, all NMOS transistors must have either an input from ground or from
another NMOS transistor. The composition of a PMOS transistor creates low resistance between
its source and drain contacts when a low gate voltage is applied and high resistance when a high
gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high
resistance between source and drain when a low gate voltage is applied and low resistance when
a high gate voltage is applied. CMOS accomplishes current reduction by complementing every
nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage
on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct, while a low
voltage on the gates causes the reverse. This arrangement greatly reduces power consumption
and heat generation. However, during the switching time, both MOSFETs conduct briefly as the
gate voltage goes from one state to another. This induces a brief spike in power consumption and
becomes a serious issue at high frequencies.
The adjacent image shows what happens when an input is connected to both a PMOS
transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of
input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current
that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and
much more current can flow from the supply to the output. Because the resistance between the
supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current
drawn from Q is small. The output, therefore, registers a high voltage.On the other hand, when
the voltage of input A is high, the PMOS transistor is in an OFF (high resistance) state so it
would limit the current flowing from the positive supply to the output, while the NMOS
transistor is in an ON (low resistance) state, allowing the output from drain to ground. Because
the resistance between Q and ground is low, the voltage drop due to a current drawn into Q

bb
placing Q above ground is small. This low drop results in the output registering a low voltage.
PROCEDURE:
2.Switch ON the trainer kit.
TRUTH TABLES:
Logic “NOT” Operation
A Q=A’
0 1
1 0
RESULT:

bb
CONCLUSION:
VIVA QUESTIONS:
1.What is DTL?
2.What is TTL?
3.What is ECL?
4.What is CMOS?
5.What is logic family?
6.Explain differences between different logic families?

2021-22 ADE Lab Manual (New Syllabus)

Uploaded by

Copyright:

Available Formats

2021-22 ADE Lab Manual (New Syllabus)

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

2021-22 ADE Lab Manual (New Syllabus)

Uploaded by

Copyright:

Available Formats

CMR TECHNICAL CAMPUS

Approved by AICTE, Permanently Affiliated to JNTUH, Accredited by NAAC & NBA

ACADEMIC YEAR: 2020-21

This is to certify that the bonafide record work done by

H.T.No _________________of II –B.Tech I-Semester in the Analog and

Digital Electronics Laboratory is satisfactory.

1. Volt-Ampere characteristics of UJT.

Analog and Digital Electronics Lab

Pin assignment of UJT:

Department of ECE, CMRTC Page 1

Analog and Digital Electronics Lab

Department of ECE, CMRTC Page 2

Analog and Digital Electronics Lab

Department of ECE, CMRTC Page 3

Analog and Digital Electronics Lab

Result: The emitter characteristics of UJT have been determined.

Department of ECE, CMRTC Page 4

Analog and Digital Electronics Lab

Department of ECE, CMRTC Page 5

Analog and Digital Electronics Lab

S.NO. Name Range Quantity

Department of ECE, CMRTC Page 6

Analog and Digital Electronics Lab

1. Connect the circuit as shown in fig.1

1. Set the CRO O/P channel in DC mode always.

Department of ECE, CMRTC Page 7

Analog and Digital Electronics Lab

Circuit Diagram Input &Output Wave Forms

Department of ECE, CMRTC Page 8

Analog and Digital Electronics Lab

Circuit diagram O/P Wave Forms

Department of ECE, CMRTC Page 9

Analog and Digital Electronics Lab

Circuit Diagrams Transfer Characteristics

Department of ECE, CMRTC Page 10

Analog and Digital Electronics Lab

Viva Voce Questions:

1.Define clipping circuit?

2.What are the different types of clippers?

3.Which kind of a clipper is called a slicer circuit?

4.What are the disadvantages of the shunt clipper?

Department of ECE, CMRTC Page 11

Analog and Digital Electronics Lab

Department of ECE, CMRTC Page 12

Analog and Digital Electronics Lab

Department of ECE, CMRTC Page 13

Analog and Digital Electronics Lab

Department of ECE, CMRTC Page 14

Analog and Digital Electronics Lab

Department of ECE, CMRTC Page 15

Analog and Digital Electronics Lab

S.NO. Name Range Quantity

1 Signal Generator. (0-1)MHz 1

4 DC power supply (dual) (0-20)V

Clamping circuits add a DC level to an AC signal. A clamper is also refer to

Department of ECE, CMRTC Page 16

Analog and Digital Electronics Lab

CIRCUIT DIAGRAM I/P & O/P WAVE FORMS

Department of ECE, CMRTC Page 17

For NOR Gate, Time Period T = _Sec & Frequency = Hz