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    Parity Generators / Checkers: Object: Theory

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    Parity Generators / Checkers: Object: Theory

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    5_2020_06_16!04_19_28_PM

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    Parity Generators / Checkers: Object: Theory

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    shitalanimkar

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    © All Rights Reserved
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    of 4

    Exp. No.

    6: PARITY GENERATORS/CHECKERS Logic Laboratory

    PARITY GENERATORS / CHECKERS

    Object: To study how to detect the error in the data.

    Theory:
    Errors can occur as digital codes are being transferred from one point to another
    within a digital system or while codes are being transmitted from one system to another. The
    errors take the form of undesired changes in the bits that make up the coded information; that
    is, a "1" can change to a "0", or a "0" to "1", due to component malfunction or electrical
    noise. Many systems, however, employ a parity bit as a means of detecting a bit error.
    Binary information is normally handled by a digital system in groups of bits called words. A
    word always contains either an even or an odd number of 1's. An even parity bit makes the
    total even.

    As an illustration of how parity bits are attached to a code word, table (6-1) lists the
    parity bits for each BCD code number for both even and odd parity. The parity bit for each
    BCD number is in the p column.

    Even Parity Odd Parity


    Pe 8421 Po 8421
    0 0000 1 0000
    1 0001 0 0001
    1 0010 0 0010
    0 0011 1 0011
    1 0100 0 0100
    0 0101 1 0101
    0 0110 1 0110
    1 0111 0 0111
    1 1000 0 1000
    0 1001 1 1001

    Table (6-1)

    The parity bit can be attached to the code group at either the beginning or the end depending
    on system design.
    Notice that the total number of 1's, including the parity bit, is always even for even parity
    and always odd for odd parity.

    02
    Exp. No. 6: PARITY GENERATORS/CHECKERS Logic Laboratory

    Parity Logic:

    In order to check for or generate the proper parity in a given code word, a very basic
    principle can be used. The sum of an even number of 1's is always zero, and the sum of an
    odd number of 1's is always one. Therefore, in order to determine if a given code word is
    even, or odd parity, all of the bits in that code word are summed. The sum of two bits can be
    generated by an EX-OR gates, as shown in Fig.(6-1-a); the sum of three bits can be formed
    by two EX-OR gates connected as shown in Fig.(6-1-b); and so on.

    A
    A B
    F
    B F
    C
    (a) Summing of two bits (b) Summing of three bits

    Fig.(6-1)

    A typical 5-bit generator / checker circuit is shown in Fig. (6-2).

    It can be used for either odd or even parity. When used as an odd parity checkers as
    shown, the operation as follows:

    A 5-bit code (four data bits and one parity bit) is applied to the inputs. The four data
    bits are on the EX-OR inputs, and the parity bit is applied to the ODD input line. When the
    number of 1's in the 5-bit code is odd, the ODD output is LOW, indicating proper parity.
    When there is an even number of 1's, the ODD output is HIGH, indicating incorrect parity
    which is illustrated in Fig.(6-2).
    Parity ODD
    0
    bit
    0
    0 ODD output
    Data 0
    bits
    1
    0

    (a) Code Correct


    Parity ODD
    1
    bit
    0
    0 ODD output
    Data 1
    bits
    1
    0

    (b) Code Error

    02
    Exp. No. 6: PARITY GENERATORS/CHECKERS Logic Laboratory

    Similarly, even parity checks are illustrated for both non error and error conditions in
    Fig.(6-3).
    Parity EVEN
    1
    bit
    0
    0 EVEN output 0
    Data
    bits
    1
    0

    (a) Code Correct

    Parity EVEN
    0
    bit
    0
    0 EVEN output 1
    Data
    bits
    1
    0

    (b) Code Error

    Fig.(6-3)

    Procedure:
    1. Design an even/odd parity generator for 4-bit data.
    2. Design a parity checker circuit for a 4-bit data.
    3. Design a logic circuit for a 3-bit message to be transmitted with an even parity bit.
    4. Four data bits are to be transmitted. Design a parity bit generator to give an o/p of '1' if the
    number of logic 1's in the message is: (i) odd; (ii) even.

    Discussion:
    1. Attach the proper even parity bit to the following codes:
    a) 11010 b) 1001 c) 0111101
    2. Repeat problem 1 for odd parity.
    3. Check each of the even parity codes for an error.
    4. The waveforms shown in Fig. (6-4) are applied to 4-bit parity logic. Determine the output
    waveform in proper relation to the inputs. How many times does even parity occur?
    00
    Exp. No. 6: PARITY GENERATORS/CHECKERS Logic Laboratory

    A A
    B B
    C E
    C D
    D

    Fig.(6-4)

    02

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