The condition Sn Rn is OFCLOCKED RS FF TRUTH TABLE

of clocked S-R FLIP-FLOPtorbidden and it

Is given in fig.
must not be allowed to occur. The logic symbol
D-FLIP FLOP
The RS-FF can be modified to
introducing an inverting forbidden prevent
gate
the indeteminate state
gate in one ofof the mentioned above Dy
SVmbol 1S shown in fig.-3b The data are stored in the inputs as shown in Fig-3a. Its logic
during thc clock pulse, hence the name data latch. the memory and are presented dt
output intormation in counters until the readout has This circuit is frequently used tor storing
facilitates counting circuits to begin their next cvcletaken place. The use of the data latcn
cycle is tak1ng place. The truth table of D-FF is while theto readout from the previous
Table and shown in Fig. restricted the middle two entries ol

CHANGE
IN CLK D
D
D Q 0 TO 1 0

1TO 0 0 1
CLKI +CLK
0 TO 1 1 0

1TO 0 1 1 0

FIG.3 (a) D-FLIP FLOP

FIG. 3(c) TRUTH TABLE
FIG. 3(b) SYMBOL
J-KFLIP-FLOP
It is not possible to achieve toggling (i.e. changing the state of the output whenever the
input makes a transition from high to low) with the help of the gated FF discussed above.
The basicJK-FF had is shovwn in Fig-4a. Has all the characteristics of a clocked RS-FF and
can be toggled.
Fig.-4b Shows the symbol used for the JK flip-flop. It has three inputs and two outputs.
The middle input is called the trigger of 'clock' input; the two other inputs are the J and K
inputs. The flip-flop response is determined by the values of J and Kat the instant when
the trigger or clock pulse arrives. There are four cases to describe.

Eredl Techuologies 3
 STUDY OF VARIOUS TYPES OF FLIP-FLOPS

Pr

JO Q
Pr

OCLK
CLKO
K
Cr

KO
dcr Fig-4a
Fig-4b

trigger or clock
When J=land K=1, the flip-flop goes to Race over condition, each time aclock pulse. On
When J=1 and K=0, the flip-flop will set on the next
pulse arrives.
is like setting an RS flip-flop.
succeeding triggers the flip-flop stays set. In other words, ittrigger, and then stay reset on
When J=0 and K-1, the flip-flop will reset on the next
J-0 and K-0, the flip-flop
succeeding clock pulses (like resetting an RS flip-flop). When flip-flop action, Since Q is the
the JK
remains in whatever state it is in. Table summarizes table tells us that the output is
trigger arrives, the first entry of the truth
value just before the
the same before and after the trigger.

CHANGE
IN CLK K
OPERATION CLK Cr Pr Q
0 A 0 0
0 TO 1 CLEAR
M 1
PRESET 0 1 0
Q Q E
1 TO 0 0
R
E
FIG. 4(d) FUNCTION
1 0
0 TO 1
E OF PRESET & CLEAR
0
1TO 0
0 S
0 TO 1 0 E
T
0 1
1TO 0 1 R
1 1
1 A V
0 TO 1 E
1 0
1 E R
1TO 0
TABLE
FIG. 4(c) TRUTH
CEDURE
EXPERIMENT
NO. 3
To
1.construct
02
onnect

aD
both (Data)
the
outputs flip-flops

of &
the study
D
flip its
characteristics.
flop
to
the
pective

Output

LEDs

O1
and
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soyou Compare
Tabulateyour and again
Observe 5. PROCEDURE
EXPERIMENT ToNO. 4 edge
and
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ck observations the the the the On J-K LED Conneet
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tlhe the J the flip-flop
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both your yourcorresponding that On
is JoutputTerminal J the
supply. Thecorresponding that the he
en, J with pulse.
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data results the switch the D(LK
to Q to lever Q both & output output
supply.
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the "1" on Terminal
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ut OFF and ON Outputs.remain to circuit the its terminal the asQ* is Q* is to STUDY of
table andClockLogic give SWl characteristics. SWland
as in Q*Logic JK shown
truth is to is 0` he
at shown Fig.
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is to"0" th e one and to (binary table OF
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and "1", "1" and same clock select Clock *1* one to
make
in ie and shown Fig. is is VARIOUS
ie one to 0 the
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earlier respective 1) in ie ie
uld will truth Terminal with Led Table-3
is thagain
e the
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be with and the corresponding corresponding
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her Logic"1" K right
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FLIP-FLOPS
to pulse.
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Q Q TOP the to to
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TOP
off side and is OFF
in sde
ON