IIST AV 312 CAO Bsmanoj August December 2024 Lecture 5

Welcome to
AV 312: Computer Architecture and

Organization
Lecture-5
Instructor: B. S. Manoj
[email protected]
IIST AV 312 Computer Architecture and

7th August 2024 1
Organization August-December 2024
Contents
• General Announcements
• History of Computing

7th August 2024 2
General Announcements
• Team formation with 4 team members must be finalized
– By this Thursday.
– A google form will be sent for the team information
– T3: Design and document the design
– T4: Design and Develop an 8bit processor
• CSE Club President: B Shanmugharajan
• Refreshing your Verilog knowledge will be helpful
• Golden Rules
– GR-1: Target 100% attendance
• Punctuality certificate from me guaranteed
– if you attend all classes where attendance is taken
– GR-2:
• Daily preparation of the portions taught
– GR-3:
• Being a good team player
7th August 2024 3
7th August 2024 4
7th August 2024 5
• History of Computers and computing

7th August 2024 7
x86 Evolution (1)
• 8080
– first general purpose microprocessor
– 8 bit data path
– Used in first personal computer – Altair
• 8086 – 5MHz – 29,000 transistors
– much more powerful
– 16 bit
– instruction cache, prefetch few instructions
– 8088 (8 bit external bus) used in first IBM PC
• 80286
– 16 Mbyte memory addressable
– up from 1Mb
• 80386
– 32 bit
– Support for multitasking
• 80486
– sophisticated powerful cache and instruction pipelining
– built in maths co-processor
7th August 2024
9
x86 Evolution (2)
• Pentium
– Superscalar
– Multiple instructions executed in parallel
• Pentium Pro
– Increased superscalar organization
– Aggressive register renaming
– branch prediction
– data flow analysis
– speculative execution
• Pentium II
– MMX technology
– graphics, video & audio processing
• Pentium III
– Additional floating point instructions for 3D graphics

7th August 2024 10
x86 Evolution (3)
• Pentium 4
– Note Arabic rather than Roman numerals
– Further floating point and multimedia enhancements
• Core
– First x86 with dual core
• Core 2
– 64 bit architecture
• Core 2 Quad – 3GHz – 820 million transistors
– Four processors on chip
• x86 architecture dominant outside embedded systems
• Organization and technology changed dramatically
• Instruction set architecture evolved with backwards compatibility
• ~1 instruction per month added
• 500 instructions available
• See Intel web pages for detailed information on processors
7th August 2024 11
Moore’s Law
• Increased density of components on chip
• Gordon Moore – co-founder of Intel observed the Number of
transistors on a chip will double every year
• Since 1970’s development has slowed a little
– Number of transistors doubles every 18 months
• Cost of a chip has remained almost unchanged
• Higher packing density means shorter electrical paths, giving
higher performance
• Smaller size gives increased flexibility
• Reduced power and cooling requirements
• Fewer interconnections increases reliability

7th August 2024 12
Technological and Economic Forces
January 3, 1929 – March 24, 2023
Moore’s law predicted a 60 percent annual increase in the number

of transistors that can be put on a chip (doubling every 18
months). The data points given above and below the line are
7th August 2024 13
memory sizes, in 2024
Organization August-December bits.
Introduction to the x86 Architecture
Moore’s law for (Intel) CPU chips.

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7th August 2024 15
Intel i9 9900 (9th generation)

7th August 2024 16
A simple hypothetical computer

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Program Concept
• Hardwired systems
are inflexible
• General purpose
hardware can do
different tasks, given
correct control
signals
• Instead of re-wiring,
supply a new set of
control signals
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What is a program?
• A sequence of steps
• For each step, an arithmetic or logical
operation is done
• For each operation, a different set of control
signals is needed

7th August 2024 19
Function of Control Unit
• For each operation a unique code is provided
– e.g. ADD, MOVE
• A hardware segment accepts the code and
issues the control signals
• With these, we have a simple computer!

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Components
• The Control Unit and the Arithmetic and Logic
Unit constitute the Central Processing Unit
• Data and instructions need to get into the
system and results out
– Input/output
• Temporary storage of code and results is
needed
– Main memory

7th August 2024 21
Computer Components: Top Level View

7th August 2024 22
Characteristics of Hypothetical
machine

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Instruction Cycle
• Two steps:
– Fetch
– Execute

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Fetch Cycle
• Program Counter (PC) holds address of next
instruction to fetch
• Processor fetches instruction from memory
location pointed to by PC
• Increment PC
– Unless told otherwise
• Instruction loaded into Instruction Register (IR)
• Processor interprets instruction and performs
required actions

7th August 2024 25
A single bit memory using D Latch

7th August 2024 26
Summary
• Evolution and History of Intel Processors
• Moore’s law (statement)
• Programmable Computer
• Instruction format
• Instruction cycle

7th August 2024 27

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Welcome to

AV 312: Computer Architecture and

IIST AV 312 Computer Architecture and

IIST AV 312 Computer Architecture and

• CSE Club President: B Shanmugharajan

• Refreshing your Verilog knowledge will be helpful

IIST AV 312 Computer Architecture and

IIST AV 312 Computer Architecture and

IIST AV 312 Computer Architecture and

January 3, 1929 – March 24, 2023

Moore’s law predicted a 60 percent annual increase in the number

Moore’s law for (Intel) CPU chips.

IIST AV 312 Computer Architecture and

IIST AV 312 Computer Architecture and

IIST AV 312 Computer Architecture and

• With these, we have a simple computer!

IIST AV 312 Computer Architecture and

IIST AV 312 Computer Architecture and

IIST AV 312 Computer Architecture and

IIST AV 312 Computer Architecture and

IIST AV 312 Computer Architecture and

IIST AV 312 Computer Architecture and

IIST AV 312 Computer Architecture and

IIST AV 312 Computer Architecture and

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