Cmos Lab 1

The CMOS Transistor
Objective: To investigate the layout and the basic features of the CMOS Transistor.
Observation:
1. Draw the "Process Simulation" and "View Window". Label all layers. Explain
the operation of the layout.
Fig 1: Process Simulation Fig 2: View Window
The Process Simulation represents how different layers of a semiconductor device or

any related system are fabricated. The process typically includes layers like the
substrate, oxide layers, metal interconnects, and doping regions.
Here's a breakdown of the different layers:
1. Substrate: This is the very basic layer on which the entire framework build upon.
Usually made from silicon or other semiconductor material.
2. Oxide Layer: An insulating layer — usually silicon dioxide (SiO2) is deposited

or grown on the substrate. The SiO2 layer can be thermally grown or deposited
with CVD.
3. Polysilicon Layer: The oxide may be a gate oxide layer and the layer of
polysilicon may be in gates in MOSFETs.
4. Doping Layer: The desired electrical properties are select by doping the substrate
with impurities, phosphorus would make n-type region while Boron will p-type.
5. Metal Layer: For interconnects, a metal layer (e.g., aluminum or copper) is

deposited. The layer here is for the electrical connections to one item from another
2. View Window Layout Diagram:
The View Window shows how the different layers align with each other during the
fabrication process.
Layers in View Window:
 Substrate (Silicon)
 Gate Oxide
 Source and Drain Regions
 Polysilicon Gate
2. Name the different regions of operation and their equations of the Transistor.
Sketch the Id vs. Vds graph and indicate the different regions.
1. Cutoff Region: For Vgs<VthV_{gs} < V_{th}Vgs<Vth, Id=0I_d = 0Id=0. There is

no current flow, and the transistor is off.
2. Linear Region: For Vgs>VthV_{gs} > V_{th}Vgs>Vth and Vds<Vgs−VthV_{ds}

< V_{gs} - V_{th}Vds<Vgs−Vth, the current increases linearly with VdsV_{ds}Vds.
The MOSFET operates like a variable resistor.
3. Saturation Region: For Vds>Vgs−VthV_{ds} > V_{gs} - V_{th}Vds>Vgs−Vth, the

current becomes independent of VdsV_{ds}Vds and remains constant, indicating
saturation.
Fig 3: ID vs VDS Graph
4. Vary the voltages of the transistor to get two settings in each of the region.
Tabulate the settings and results. Sketch Id vs. Vds for each case indicating the
region.
1. Vgs = 0V, Vds = 0V
 Region: Cutoff (OFF state)

 Reason: Since Vgs=0V_(gs) = 0Vgs=0, which is less than Vth=0.5 VV_(th) = 0.5,
Vth=0.5V, the transistor is OFF and no current flows through the drain-source
channel.
Fig 4: 1. Vgs = 0V, Vds = 0V
2. Vgs = 2V, Vds = 0.5V

 Region: Linear region
 Reason: Since Vgs=2 V>VthV_{gs} = 2, > V(th)Vgs=2V>Vth and Vds=0.5
V<Vgs−VthV_{ds} = 0.5, < V_{gs} - V_{th}Vds=0.5V<Vgs−Vth, the transistor
operates in the linear region. Current increases linearly with VdsV_{ds}Vds
Fig 5: Vgs = 2V, Vds = 0.5V

3. Vgs = 3V, Vds = 4V
 Region: Saturation region
 Reason: Vgs=3 V>VthV_{gs} = 3, {V} > V_{th}Vgs=3V>Vth and Vds=4
V>Vgs−VthV_{ds} = 4,{V} > V_{gs} - V_{th}Vds=4V>Vgs−Vth. Since
Vds>Vgs−VthV_{ds} > V_{gs} - V_{th}Vds>Vgs−Vth, the transistor is in
saturation.
Fig 6: Vgs = 3V, Vds = 4V
 Vgs = 5V, Vds = 5V

 Region: Saturation region
 Reason: Vgs=5 V>VthV_{gs} = 5 ,{V} > V_{th}Vgs=5V>Vth and Vds=5
V>Vgs−VthV_{ds} = 5, {V} > V_{gs} - V_{th}Vds=5V>Vgs−Vth, so the transistor
is in the saturation region. IdI_dId is independent of VdsV_{ds}Vds.
Fig 7: Vgs = 5V, Vds = 5V

5. Vgs = -1V, Vds = 4V
 Region: Cutoff region
 Reason: Since Vgs=−1 V<VthV_{gs} = -1 \, \text{V} < V_{th}Vgs=−1V<Vth, the
transistor is in cutoff, regardless of VdsV_{ds}Vds.
Fig 8: Vgs = -1V, Vds = 4V
VGS VDS Operation Region Reason

0 0 Cutoff Vgs<Vth, transistor
OFF
2 0.5 Linear Vds<Vgs−Vth
3 4 Saturation Vds>Vgs−Vth
5 5 Saturation Vds>Vgs−Vth
-1 4 Cutoff Vgs<Vth, transistor
OFF
4. Using the "Options Menu" change the width of the device. How does it influence
the transistor and why?
Fig 9: Original width
1. Linear Region
Changing the width (W) of the MOSFET device directly influences its performance, particularly in
terms of current handling capability.
The effective gate voltage (Vgeff) is smallest at the drain and largest at the source. The effect
of changing this voltage can be seen as changing a channel resistance. Therefore, Vds
increases as Id increases.
5. Set the width back to its original value. Then change the length of the transistor.
How does it influence the transistor and why?
Fig 10: Setting the original width and increasing the length
Increased Length → Decreased Drain Current (Id):
 The drain current (Id) is inversely proportional to the length (L) of the transistor.
 Increasing L reduces the drain current because the channel through which current
flows is longer, increasing the resistance of the channel and reducing current flow.
6. Vary the temperature and investigate its effects.
Fig 11: Setting the temperature to 8 degree
Fig 12: Setting the temperature to 110 degree

 Increasing the temperature in a MOSFET affects several key parameters. Carrier
mobility decreases due to increased lattice vibrations, reducing drain current (Id).
 Threshold voltage (Vth) typically decreases, which can lead to higher leakage
currents. As a result, the on-resistance (Rds(on)) increases, making the transistor less
efficient.
 Additionally, subthreshold leakage currents rise exponentially with temperature,
which is a concern for low-power applications. Overall, higher temperatures can
negatively impact the transistor’s performance, reliability, and may lead to thermal
runaway if not properly managed.
PMOS transistor
1. Draw the "Process Simulation" and "View Window". Label all layers. Explain
the operation of the layout.
Fig 13: Process Simulation and View Window
The view window is a cross-sectional diagram of the PMOS transistor, showing how the
different layers and regions interact.
Key Layers and Regions in the View Window:
1. N-type Substrate:
o The PMOS is fabricated in an n-type well. This creates a reverse-bias
condition for the p-type source and drain regions, allowing the PMOS to
function properly.
2. Gate Oxide:
o A thin SiO₂ layer sits between the gate and the underlying n-well, forming the
dielectric of the gate capacitor.
3. Polysilicon Gate:
o The gate electrode controls the flow of current between the source and drain. A
negative gate-to-source voltage (Vgs) inverts the n-type region below the gate
to form a conductive p-channel.
4. Source and Drain Regions:
o The source and drain regions are heavily p-doped (P+). When a sufficient
negative gate voltage is applied, a p-channel is formed between the source and
drain.
5. Metal Contacts:
o Metal connections are made to the source, drain, and gate for electrical access.
2. Name the different regions of operation and their equations of the Transistor.
Sketch the Id vs. Vds graph and indicate the different regions.
 Cutoff Region:
 For Vgs<VthV_{gs} < V_{th}Vgs<Vth, Id=0I_d = 0Id=0 and there is no current
flow. This appears as a flat line on the x-axis (zero current).
 Triode Region:
 As Vgs>VthV_{gs} > V_{th}Vgs>Vth and Vds<Vgs−VthV_{ds} < V_{gs} -
V_{th}Vds<Vgs−Vth, current increases linearly with VdsV_{ds}Vds. The MOSFET
behaves like a resistor, and the curve rises linearly.
 Saturation Region:
 For Vds>Vgs−VthV_{ds} > V_{gs} - V_{th}Vds>Vgs−Vth, the MOSFET reaches
saturation, and IdI_dId becomes constant. This is represented by a flat line in the
graph, where the current remains unchanged despite increases in VdsV_{ds}Vds.
Fig 14: ID vs VDS Graph
3. Vary the voltages of the transistor to get two settings in each of the region.
Tabulate the settings and results. Sketch Id vs. Vds for each case indicating the
region.

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The CMOS Transistor

Fig 1: Process Simulation Fig 2: View Window

The Process Simulation represents how different layers of a semiconductor device or

Here's a breakdown of the different layers:

2. Oxide Layer: An insulating layer — usually silicon dioxide (SiO2) is deposited

5. Metal Layer: For interconnects, a metal layer (e.g., aluminum or copper) is

Layers in View Window:

1. Cutoff Region: For Vgs<VthV_{gs} < V_{th}Vgs<Vth, Id=0I_d = 0Id=0. There is

2. Linear Region: For Vgs>VthV_{gs} > V_{th}Vgs>Vth and Vds<Vgs−VthV_{ds}

3. Saturation Region: For Vds>Vgs−VthV_{ds} > V_{gs} - V_{th}Vds>Vgs−Vth, the

Fig 3: ID vs VDS Graph

 Region: Cutoff (OFF state)

Fig 4: 1. Vgs = 0V, Vds = 0V

2. Vgs = 2V, Vds = 0.5V

Fig 5: Vgs = 2V, Vds = 0.5V

Fig 6: Vgs = 3V, Vds = 4V

 Vgs = 5V, Vds = 5V

Fig 7: Vgs = 5V, Vds = 5V

Fig 8: Vgs = -1V, Vds = 4V

VGS VDS Operation Region Reason

Fig 9: Original width

6. Vary the temperature and investigate its effects.

Fig 11: Setting the temperature to 8 degree

Fig 12: Setting the temperature to 110 degree

Fig 13: Process Simulation and View Window

Fig 14: ID vs VDS Graph

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