ALC887

ALC887
(PN: ALC887-GR)
7.1 CHANNEL HIGH DEFINITION AUDIO CODEC

WITH TWO INDEPENDENT SPDIF-OUT
DATASHEET
Rev. 1.0
24 July 2008
Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
ALC887
Datasheet
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means without the written permission of Realtek Semiconductor Corp.
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technical inaccuracies or typographical errors.
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Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT

This document is intended for the hardware and software engineer’s general information on the Realtek
ALC887 High Definition Audio Codec IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary
1.0 2008/07/24 First release
7.1 Channel High Definition Audio Codec w/Two ii Rev. 1.0

Independent SPDIF-OUT
ALC887
Datasheet
Table of Contents
1. GENERAL DESCRIPTION ..............................................................................................................................................1
2. FEATURES .........................................................................................................................................................................2
2.1. HARDWARE FEATURES .................................................................................................................................................2
2.2. SOFTWARE FEATURES ..................................................................................................................................................3
3. SYSTEM APPLICATIONS ...............................................................................................................................................4
4. BLOCK DIAGRAM ...........................................................................................................................................................5

4.1. ANALOG INPUT/OUTPUT UNIT .....................................................................................................................................6
5. PIN ASSIGNMENTS..........................................................................................................................................................7
5.1. ALC887 PIN ASSIGNMENT ..........................................................................................................................................7
5.2. GREEN PACKAGE AND VERSION IDENTIFICATION .........................................................................................................7
6. PIN DESCRIPTIONS.........................................................................................................................................................8
6.1. DIGITAL I/O PINS .........................................................................................................................................................8
6.2. ANALOG I/O PINS ........................................................................................................................................................8
6.3. FILTER/REFERENCE ......................................................................................................................................................9
6.4. POWER/GROUND ........................................................................................................................................................10
7. HIGH DEFINITION AUDIO LINK PROTOCOL........................................................................................................11
7.1. LINK SIGNALS ............................................................................................................................................................11
7.1.1. Signal Definitions .................................................................................................................................................12
7.1.2. Signaling Topology ...............................................................................................................................................13
7.2. FRAME COMPOSITION ................................................................................................................................................14
7.2.1. Outbound Frame – Single SDO............................................................................................................................14
7.2.2. Outbound Frame – Multiple SDOs.......................................................................................................................15
7.2.3. Inbound Frame – Single SDI ................................................................................................................................16
7.2.4. Inbound Frame – Multiple SDIs...........................................................................................................................17
7.2.5. Variable Sample Rates..........................................................................................................................................17
7.3. RESET AND INITIALIZATION ........................................................................................................................................20
7.3.1. Link Reset .............................................................................................................................................................20
7.3.2. Codec Reset ..........................................................................................................................................................21
7.3.3. Double Function Reset .........................................................................................................................................21
7.3.4. Codec Initialization Sequence ..............................................................................................................................22
7.4. VERB AND RESPONSE FORMAT ...................................................................................................................................22
7.4.1. Command Verb Format ........................................................................................................................................22
7.4.2. Response Format..................................................................................................................................................25
7.5. POWER MANAGEMENT ...............................................................................................................................................26
7.5.1. ALC887 Additional Power Features.....................................................................................................................27
8. SUPPORTED VERBS AND PARAMETERS ................................................................................................................28
8.1. VERB – GET PARAMETERS (VERB ID=F00H) .............................................................................................................28
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h).............................................................................28
8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) ..........................................................................28
8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)......................................................29
8.1.4. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) ...........................................................29
8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)................................................29
8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ...................................................30
7.1 Channel High Definition Audio Codec w/Two iii Rev. 1.0
ALC887
Datasheet
8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah).................................................31
8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)..................................................32
8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................32
8.1.10. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)...........................33
8.1.11. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) .........................33
8.1.12. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)........................................................34
8.1.13. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)..................................................34
8.1.14. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h) ..................................................34
8.1.15. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)...........................................................35
8.1.16. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)...............................................35
8.2. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ................................................................................36
8.3. VERB – SET CONNECTION SELECT (VERB ID=701H) .................................................................................................36
8.4. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) .........................................................................................37
8.5. VERB – GET PROCESSING STATE (VERB ID=F03H)....................................................................................................40
8.6. VERB – SET PROCESSING STATE (VERB ID=703H).....................................................................................................40
8.7. VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................41
8.8. VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................41
8.9. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................42
8.10. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................42
8.11. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................43
8.12. VERB – SET AMPLIFIER GAIN (VERB ID=3H).............................................................................................................44
8.13. VERB – GET CONVERTER FORMAT (VERB ID=AH) ....................................................................................................45
8.14. VERB – SET CONVERTER FORMAT (VERB ID=2H)......................................................................................................46
8.15. VERB – GET POWER STATE (VERB ID=F05H) ............................................................................................................46
8.16. VERB – SET POWER STATE (VERB ID=705H) .............................................................................................................47
8.17. VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...............................................................................47
8.18. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ................................................................................48
8.19. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) ..............................................................................................48
8.20. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...............................................................................................49
8.21. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...........................................................................49
8.22. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ............................................................................50
8.23. VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................50
8.24. VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................51
8.25. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH) ........................................................................................51
8.26. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) 52
8.27. VERB – GET BEEP GENERATOR (VERB ID=F0AH) ...................................................................................................52
8.28. VERB – SET BEEP GENERATOR (VERB ID=70AH) ....................................................................................................53
8.29. VERB – GET GPIO DATA (VERB ID=F15H) ...............................................................................................................53
8.30. VERB – SET GPIO DATA (VERB ID=715H) ................................................................................................................54
8.31. VERB – GET GPIO ENABLE MASK (VERB ID=F16H) ................................................................................................54
8.32. VERB – SET GPIO ENABLE MASK (VERB ID=716H) .................................................................................................55
8.33. VERB – GET GPIO DIRECTION (VERB ID=F17H) ......................................................................................................55
8.34. VERB – SET GPIO DIRECTION (VERB ID=717H) .......................................................................................................56
8.35. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) ........................................................56
8.36. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H) .......................................................57
8.37. VERB – FUNCTION RESET (VERB ID=7FFH) ..............................................................................................................57
8.38. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH) .........................................58
8.39. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH)............................................60
8.40. VERB – GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/D22H/F23H)..................................................................61
8.41. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H/722H /721H/720H FOR BYTES 3,2,1,0) .....................................61
8.42. GET/SET EAPD ENABLE (VID=70CH/F0CH)............................................................................................................62
9. ELECTRICAL CHARACTERISTICS...........................................................................................................................63
9.1. DC CHARACTERISTICS ...............................................................................................................................................63
9.1.1. Absolute Maximum Ratings ..................................................................................................................................63
7.1 Channel High Definition Audio Codec w/Two iv Rev. 1.0
ALC887
Datasheet
9.1.2. Threshold Voltage .................................................................................................................................................63
9.1.3. Digital Filter Characteristics ...............................................................................................................................64
9.1.4. SPDIF Input/Output Characteristics....................................................................................................................64
9.2. AC CHARACTERISTIC ................................................................................................................................................65
9.2.1. Link Reset and Initialization Timing.....................................................................................................................65
9.2.2. Link Timing Parameters at the Codec ..................................................................................................................66
9.2.3. SPDIF Output and Input Timing...........................................................................................................................67
9.3. ANALOG PERFORMANCE ............................................................................................................................................68
10. APPLICATION CIRCUITS .......................................................................................................................................69
10.1. FILTER CONNECTION ..................................................................................................................................................69
10.2. ONBOARD FRONT PANEL HEADER CONNECTION........................................................................................................70
10.3. JACK CONNECTION ON REAR PANEL ..........................................................................................................................71
10.4. SPDIF INPUT/OUTPUT CONNECTION .........................................................................................................................71
10.5. SECONDARY SPDIF-OUT CONNECTED TO HDMI TX CONNECTOR ...........................................................................72
10.6. DIFFERENTIAL ANALOG CD USED AS LINE LEVEL INPUT ..........................................................................................72
11. MECHANICAL DIMENSIONS......................................................................................................................................73
12. ORDERING INFORMATION .......................................................................................................................................74
7.1 Channel High Definition Audio Codec w/Two v Rev. 1.0

ALC887
Datasheet
List of Tables
TABLE 1. DIGITAL I/O PINS ........................................................................................................................................................8
TABLE 2. ANALOG I/O PINS .......................................................................................................................................................8
TABLE 3. FILTER/REFERENCE .....................................................................................................................................................9
TABLE 4. POWER/GROUND .......................................................................................................................................................10
TABLE 5. LINK SIGNAL DEFINITIONS........................................................................................................................................12
TABLE 6. HDA SIGNAL DEFINITIONS .......................................................................................................................................12
TABLE 7. DEFINED SAMPLE RATE AND TRANSMISSION RATE ...................................................................................................18
TABLE 8. 48KHZ VARIABLE RATE OF DELIVERY TIMING ..........................................................................................................18
TABLE 9. 44.1KHZ VARIABLE RATE OF DELIVERY TIMING .........................................................................................................19
TABLE 10. 40-BIT COMMANDS IN 4-BIT VERB FORMAT .............................................................................................................22
TABLE 11. 40-BIT COMMANDS IN 12-BIT VERB FORMAT ...........................................................................................................22
TABLE 12. SUPPORTED COMMANDS ...........................................................................................................................................23
TABLE 13. SUPPORTED PARAMETERS .........................................................................................................................................24
TABLE 14. SOLICITED RESPONSE FORMAT .................................................................................................................................25
TABLE 15. UNSOLICITED RESPONSE FORMAT .............................................................................................................................25
TABLE 16. SYSTEM POWER STATE DEFINITIONS.........................................................................................................................26
TABLE 17. POWER CONTROLS IN NID 01H.................................................................................................................................26
TABLE 18. POWERED DOWN CONDITIONS ..................................................................................................................................27
TABLE 19. VERB – GET PARAMETERS (VERB ID=F00H) ............................................................................................................28
TABLE 20. PARAMETER – VENDOR ID (VERB ID=F00H, PARAMETER ID=00H).........................................................................28
TABLE 21. PARAMETER – REVISION ID (VERB ID=F00H, PARAMETER ID=02H) .......................................................................28
TABLE 22. PARAMETER – SUBORDINATE NODE COUNT (VERB ID=F00H, PARAMETER ID=04H)...............................................29
TABLE 23. PARAMETER – FUNCTION GROUP TYPE (VERB ID=F00H, PARAMETER ID=05H)......................................................29
TABLE 24. PARAMETER – AUDIO FUNCTION CAPABILITIES (VERB ID=F00H, PARAMETER ID=08H) .........................................29
TABLE 25. PARAMETER – AUDIO WIDGET CAPABILITIES (VERB ID=F00H, PARAMETER ID=09H).............................................30
TABLE 26. PARAMETER – SUPPORTED PCM SIZE, RATES (VERB ID=F00H, PARAMETER ID=0AH)...........................................31
TABLE 27. PARAMETER – SUPPORTED STREAM FORMATS (VERB ID=F00H, PARAMETER ID=0BH) ..........................................32
TABLE 28. PARAMETER – PIN CAPABILITIES (VERB ID=F00H, PARAMETER ID=0CH)...............................................................32
TABLE 29. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, INPUT AMPLIFIER PARAMETER ID=0DH).......................33
TABLE 30. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, OUTPUT AMPLIFIER PARAMETER ID=12H) ....................33
TABLE 31. PARAMETER – CONNECT LIST LENGTH (VERB ID=F00H, PARAMETER ID=0EH)......................................................34
TABLE 32. PARAMETER – SUPPORTED POWER STATES (VERB ID=F00H, PARAMETER ID=0FH) ................................................34
TABLE 33. PARAMETER – PROCESSING CAPABILITIES (VERB ID=F00H, PARAMETER ID=10H) .................................................34
TABLE 34. PARAMETER – GPIO CAPABILITIES (VERB ID=F00H, PARAMETER ID=11H)............................................................35
TABLE 35. PARAMETER – VOLUME KNOB CAPABILITIES (VERB ID=F00H, PARAMETER ID=13H).............................................35
TABLE 36. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ...............................................................................36
TABLE 37. VERB – SET CONNECTION SELECT (VERB ID=701H) ................................................................................................36
TABLE 38. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) ........................................................................................37
TABLE 39. VERB – GET PROCESSING STATE (VERB ID=F03H)...................................................................................................40
TABLE 40. VERB – SET PROCESSING STATE (VERB ID=703H)....................................................................................................40
TABLE 41. VERB – GET COEFFICIENT INDEX (VERB ID=DH).....................................................................................................41
TABLE 42. VERB – SET COEFFICIENT INDEX (VERB ID=5H) ......................................................................................................41
TABLE 43. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ...........................................................................................42
TABLE 44. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H).............................................................................................42
TABLE 45. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ..........................................................................................................43
TABLE 46. VERB – SET AMPLIFIER GAIN (VERB ID=3H) ...........................................................................................................44
TABLE 47. VERB – GET CONVERTER FORMAT (VERB ID=AH) ...................................................................................................45
TABLE 48. VERB – SET CONVERTER FORMAT (VERB ID=2H) ....................................................................................................46
TABLE 49. VERB – GET POWER STATE (VERB ID=F05H)............................................................................................................46
TABLE 50. VERB – SET POWER STATE (VERB ID=705H)............................................................................................................47
TABLE 51. VERB –GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...............................................................................47
7.1 Channel High Definition Audio Codec w/Two vi Rev. 1.0

ALC887
Datasheet
TABLE 52. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H)...............................................................................48
TABLE 53. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) .............................................................................................48
TABLE 54. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ..............................................................................................49
TABLE 55. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ..........................................................................49
TABLE 56. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ...........................................................................50
TABLE 57. VERB – GET PIN SENSE (VERB ID=F09H).................................................................................................................50
TABLE 58. VERB – EXECUTE PIN SENSE (VERB ID=709H).........................................................................................................51
TABLE 59. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH).......................................................................................51
TABLE 60. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3)
............................................................................................................................................................................................52
TABLE 61. VERB – GET BEEP GENERATOR (VERB ID= F0AH) .................................................................................................52
TABLE 62. VERB – SET BEEP GENERATOR (VERB ID= 70AH) ..................................................................................................53
TABLE 63. VERB – GET GPIO DATA (VERB ID= F15H) .............................................................................................................53
TABLE 64. VERB – SET GPIO DATA (VERB ID= 715H) ..............................................................................................................54
TABLE 65. VERB – GET GPIO ENABLE MASK (VERB ID= F16H) ..............................................................................................54
TABLE 66. VERB – SET GPIO ENABLE MASK (VERB ID=716H) ................................................................................................55
TABLE 67. VERB – GET GPIO DIRECTION (VERB ID=F17H) .....................................................................................................55
TABLE 68. VERB – SET GPIO DIRECTION (VERB ID=717H) ......................................................................................................56
TABLE 69. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H)........................................................56
TABLE 70. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H) ........................................................57
TABLE 71. VERB – FUNCTION RESET (VERB ID=7FFH).............................................................................................................57
TABLE 72. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH).........................................58
TABLE 73. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH)...........................................60
TABLE 74. VERB – GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/F22H/F23H) .................................................................61
TABLE 75. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H/722H//721H/720H FOR BYTES 3,2,1,0) ....................................61
TABLE 76. VERB – GET/SET EAPD [31:0] .................................................................................................................................62
TABLE 77. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................63
TABLE 78. THRESHOLD VOLTAGE ..............................................................................................................................................63
TABLE 79. DIGITAL FILTER CHARACTERISTICS ..........................................................................................................................64
TABLE 80. SPDIF INPUT/OUTPUT CHARACTERISTICS ................................................................................................................64
TABLE 81. LINK RESET AND INITIALIZATION TIMING .................................................................................................................65
TABLE 82. LINK TIMING PARAMETERS AT THE CODEC ...............................................................................................................66
TABLE 83. SPDIF OUTPUT AND INPUT TIMING ..........................................................................................................................67
TABLE 84. ANALOG PERFORMANCE ...........................................................................................................................................68
TABLE 85. ORDERING INFORMATION ..........................................................................................................................................74
7.1 Channel High Definition Audio Codec w/Two vii Rev. 1.0
ALC887
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM ......................................................................................................................................................5
FIGURE 2. ANALOG INPUT/OUTPUT UNIT...................................................................................................................................6
FIGURE 3. ALC887 PIN ASSIGNMENTS ......................................................................................................................................7
FIGURE 4. HDA LINK PROTOCOL .............................................................................................................................................11
FIGURE 5. BIT TIMING ..............................................................................................................................................................12
FIGURE 6. SIGNALING TOPOLOGY ............................................................................................................................................13
FIGURE 7. SDO OUTBOUND FRAME.........................................................................................................................................14
FIGURE 8. SDO STREAM TAG IS INDICATED IN SYNC ...............................................................................................................14
FIGURE 9. STRIPED STREAM ON MULTIPLE SDOS ......................................................................................................................15
FIGURE 10. SDI INBOUND STREAM............................................................................................................................................16
FIGURE 11. SDI STREAM TAG AND DATA ...................................................................................................................................16
FIGURE 12. CODEC TRANSMITS DATA OVER MULTIPLE SDIS ....................................................................................................17
FIGURE 13. LINK RESET TIMING ................................................................................................................................................21
FIGURE 14. CODEC INITIALIZATION SEQUENCE ..........................................................................................................................22
FIGURE 15. LINK RESET AND INITIALIZATION TIMING................................................................................................................65
FIGURE 16. LINK SIGNALS TIMING .............................................................................................................................................66
FIGURE 17. OUTPUT AND INPUT TIMING ....................................................................................................................................67
FIGURE 18. FILTER CONNECTION ...............................................................................................................................................69
FIGURE 19. FRONT PANEL HEADER CONNECTION ......................................................................................................................70
FIGURE 20. JACK CONNECTION ON REAR PANEL........................................................................................................................71
FIGURE 21. SPDIF INPUT/OUTPUT CONNECTION .......................................................................................................................71
FIGURE 22. SECONDARY SPDIF-OUT CONNECTED TO HDMI TX CONNECTOR ........................................................................72
FIGURE 23. DIFFERENTIAL ANALOG CD USED AS LINE LEVEL INPUT........................................................................................72
7.1 Channel High Definition Audio Codec w/Two viii Rev. 1.0
ALC887
Datasheet
1. General Description
The ALC887 is a 7.1 Channel High Definition Audio Codec with two independent SPDIF outputs.
Featuring eight channels of DAC support 7.1 sound playback, and integrates two stereo ADC that can
support a stereo microphone, and feature Acoustic Echo Cancellation (AEC), Beam Forming (BF), and
Noise Suppression (NS) for voice applications.
ALC887 is designed not only to meet the premium audio performance requirements in current WLP3.10
(Windows Logo Program), but provides better characteristics for future WLP. That brings user real high
fidelity of sound quality.
The ALC887 supports 16/20/24-bit SPDIF input and output functions with sampling rate of up to 192kHz,
offering easy connection of PCs to high quality consumer electronic products such as digital speakers.. In
addition to the standard (primary) SPDIF output function, the ALC887 features another independent
(secondary) SPDIF-OUT output and converters that transport digital audio to a High Definition Media
Interface (HDMI) transmitter output to HDTV system or A/V receiver, this feature is becoming more
common in high-end PCs.
As ALC series HD audio codec, all analog IO are input and output capable, and headphone amplifiers are
also integrated at each analog output. That provides flexible design for various system configuration.
Addition to audio functions, ALC887 also conforms to Intel’s Audio Codec low power state white paper
and is ECR compliant. This low power design consumes various and less power in different operation
mode, and save more power when system is in suspend mode.
The ALC887 supports host audio controller from the Intel ICH series chipset, and also from any other
HDA compatible audio controller. With EAX/Direct Sound 3Dcompatibility, and software utilities like
environment sound emulation, multiple-band software equalizer and dynamic range control, optional
Dolby® PCEE program, DTS® CONNECT™ program, the ALC887 provides an excellent home
entertainment package and game experience for PC users.
7.1 Channel High Definition Audio Codec w/Two 1 Rev. 1.0

ALC887
Datasheet
2. Features
2.1. Hardware Features
Meets premium audio requirements for Microsoft WLP 3.10
Meets stricter performance requirements for future WLP
High-performance DACs with 97dB Signal-to-Noise Ratio (SNR), ADCs with 90dB SNR
Four stereo DACs (8 channels) support 16/20/24-bit PCM format for 7.1 sound playback.
Two stereo ADCs (4 channels) support 16/20/24-bit PCM format recording simultaneously
All DACs supports 16/20/24-bit, 44.1k/48k/96k/192kHz sample rate
All ADCs supports 16/20/24-btt, 44.1k/48k/96k/192kHz sample rate
Two independent SPDIF-OUT converters support 16/20/24-bit, 44.1k/48k/88.2k/96k/192kHz sample
rate. One converter for normal SPDIF output, the other outputs an independent digital stream to the
HDMI transmitter
One SPDIF-IN converter supports 44.1k/48k/96k/192k Hz sample rate
High-quality analog differential CD input
Supports external PCBEEP input, built-in digital BEEP generator, and pass-through function in D3
mode
Software selectable 2.5V/3.75V VREFOUT to be analog microphone bias
Two jack detection pins each designed to detect up to 4 jacks
Supports legacy analog mixer architecture
Wide range (–80dB ~ +42dB) volume control with 1.5dB resolution of analog to analog mixer gain
Software selectable boost gain (+10/+20/+30dB) for analog microphone input
All analog jacks are stereo input and output re-tasking for analog plug & play
Built-in headphone amplifiers for each re-tasking jack
Two GPIOs for customized applications
Supports Anti-pop mode when analog power AVDD is on and digital power is off
Supports stereo digital microphone interface to improve voice quality
48-pin LQFP ‘Green’ package, and pin compatible with ALC888 series
ALC887
Datasheet
Supports low voltage IO for HDA Link (1.5V~3.3V)
Intel low power ECR compliant, supports power status control for each analog converter and pin
widgets, supports jack detection and wake up event in D3 mode
2.2. Software Features

Meets Microsoft WLP 3.10 and future WLP audio requirements
WaveRT based audio function driver for Windows Vista
EAX™ 1.0 & 2.0 compatible, especially the EAX effect is supported in Windows Vista
Direct Sound 3D™ compatible
Emulation of 26 sound environments to enhance gaming experience
Multi bands of software equalizer and tool are provided
Voice Cancellation and Key Shifting effect
Dynamic range control (expander, compressor and limiter) with adjustable parameters
Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience
Provides 10-foot GUI for Windows Media Center
Realtek proprietary Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming
(BF) technology for voice application
HDMI audio driver for AMD platform
Dolby® PCEE program™ (optional software feature)
DTS® CONNECT™ (optional software feature)
SRS® TrueSurround HD (optional software feature)
Fortemedia® SAM™ technology for voice processing (Beam Forming and Acoustic Echo
Cancellation) (optional software feature)

ALC887
Datasheet
3. System Applications
Desktop multimedia PCs
Notebook PCs

4.
ALC887 High Definition Audio Codec
Front
Surr
SideSurr CLfe 17h
05h 0Fh M I/O
PCM-4 SRC M VOL Boost SIDESURR(Port-H)
DAC SideSurr DAC SideSurr
M
Front
Surr
04h 0Eh SideSurr CLfe 16h
PCM-3 SRC DAC M VOL CLfe M
CLfe DAC I/O CEN/LFE(Port-G)
M Boo st
03h 0Dh Front
PCM-2 SRC DAC Surr DAC M VOL Surr Surr
M SideSurr CLfe 15h
M I/OA
02h 0Ch Boost SURR(Port-A)
PCM-1 SRC DAC Front DAC M VOL Front
M Front
Surr
Block Diagram
SideSurr CLfe 14h

0Bh VOL M M I/OA
Boost FRONT(Port-D)
VOL M
VOL M
7.1 Channel High Definition Audio Codec w/Two

VOL M BEEP Gen BEEP-IN 1Dh
Digital VOL M
VOL M
Interface VOL M CD-IN 1Ch
Figure 1.
VOL M
Front
VOL M Surr
SideSurr CLfe 1Bh
5
VOL M M I/OA
1 Boost LINE2(Port-E)
M
M
M Front
09h M Surr
M
SRC ADC VOL M M 22h SideSurr CLfe 1Ah
M
Parameters M
M
M I/OA
M Boost LINE1(Port-C)
M
M
M Front
M Surr
M SideSurr CLfe 19h
08h M
M M
Block Diagram
SRC ADC VOL M M I/OA MIC2(Port-F)
M Boost
M 23h
M
M
M Front
Surr
SideSurr CLfe 18h
M I/OA
Boost MIC1(Port-B)
DMIC_LR 12h
SP-OUT DATA 10h

S/PDIF-OUT S/PDIF-OUT2 11h
SP-OUT DATA 06h
S/PDIF-OUT S/PDIF-OUT1 1Eh
SP-IN PCM 0Ah
S/PDIF-IN S/PDIF-IN 1Fh
Sense A
Jack Detect Sense B
Sense C
Rev. 1.0
Datasheet
ALC887
ALC887
Datasheet
4.1. Analog Input/Output Unit

Pin Complex widgets NID=14h~1Bh are re-tasking IO.
A Left
R
R
EN_OBUF EN_AMP Right
Output_Signal_Left
Output_Signal_Right EN_OBUF
Input_Signal_Left
Input_Signal_Right EN_IBUF
Figure 2. Analog Input/Output Unit

ALC887
Datasheet
5. Pin Assignments
5.1. ALC887 Pin Assignment
FRO N T- R (Port- D)
FRO N T- L (Port- D)
M I C1- V REFO- R
M I C1- V REFO- L
L I N E1- V REFO
L I N E2- V REFO
M I C2- V REFO
A V D D1
Sense C
Sense B
A VSS1
V REF
36 35 34 33 32 31 30 29 28 27 26 25
NC 37 24 LINE 1- R ( Port- C- R)
AVDD2 38 23 LINE 1- L ( Port- C- L)
SURR- L ( Port- A - L) 39 22 MIC 1- R ( Port- B- R)
JDREF 40 21 MIC 1- L ( Port- B- L)
SURR- R ( Port- A-R) 41 20 ALC887 CD-R
AVSS2 42 19 CD- GND
CENTER (Port-G-L) 43 18 CD- L
LFE ( Port- G- R) 44 17 MIC 2- R ( Port-F- R)
SIDE-L (Port-H-L) 45 LLLLLLL GXXXVV 16 MIC 2- L ( Port-F- L)
SIDE-R (Port-H-R) 46 15 LINE 2- R ( Port-E- R)
SPDIFI/EAPD 47 14 LINE 2- L ( Port-E- L)
SPDIFO 48 13 Sense A
1 2 3 4 5 6 7 8 9 10 11 12
PC B EEP
D V D D- I O
DVDD
SPDI FO2
SD A T A - O U T
GPOI 0/ D M I C- C L K
GPIO1/ D M I C- D A T A
D VSS
BITCLK
SY NC
SD A T A-I N
RESET#
Figure 3. ALC887 Pin Assignments
5.2. Green Package and Version Identification

Green package is indicated by a ‘G’ as shown in Figure 3Figure 3. The silicon and stepping version
number are shown in the location marked ‘VV’.

ALC887
Datasheet
6. Pin Descriptions
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Name Type Pin Description Characteristic Definition
RESET# I 11 H/W Reset Vt=0.5*DVDD
SYNC I 10 Sample Sync (48kHz) Vt=0.5*DVDD
BITCLK I 6 24MHz Bit Clock Input Vt=0.5*DVDD
SDATA-OUT I 5 Serial TDM Data Input Vt=0.5*DVDDIO
SDATA-IN O 8 Serial TDM Data Output Vt=0.5*DVDDIO, VOH=DVDDIO,
VOL=DVSS
SPDIFI / I/O 47 SPDIF Input / VIL=1.45V, VIH=1.85V /
EAPD Signal to Power Down External Amplifier VOH=DVDD, VOL=DVSS
SPDIFO O 48 First SPDIF Output Output has 12mA@75Ω driving capability
VOH=DVDD, VOL=DVSS
SPDIFO2 O 2 Secondary SPDIF Output for Digital Output has 12mA@75Ω driving capability
Audio Output to HDMI VOH=DVDD, VOL=DVSS
GPIO0 / IO 3 General Purpose Input/Output 0 Input: Vt=(2/3)*DVDD
DMIC-CLK Clock Output to Digital MIC Output: VOH=DVDD, VOL=DVSS
GPIO1 / IO 4 General Purpose Input/Output 1 Input: Vt=(2/3)*DVDD
DMIC-DATA Serial Data from Digital MIC Output: VOH=DVDD, VOL=DVSS
Total: 10 Pins
6.2. Analog I/O Pins

Table 2. Analog I/O Pins
LINE2-L IO 14 2nd Line Input Left Channel Analog input/output, default is input (JACK-E)
LINE2-R IO 15 2nd Line Input Right Channel Analog input/output, default is input (JACK –E)
MIC2-L IO 16 2nd Stereo Microphone Input Left Analog input/output, default is input (JACK –F)
Channel
MIC2-R IO 17 2nd Stereo Microphone Input Right Analog input/output, default is input (JACK –F)
Channel
CD-L I 18 CD Input Left Channel Analog input, 1.6Vrms of full-scale input
CD-GND I 19 CD Input Reference Ground Analog input, 1.6Vrms of full-scale input
CD-R I 20 CD Input Right Channel Analog input, 1.6Vrms of full-scale input
MIC1-L IO 21 1st Stereo Microphone Input Left Analog input/output, default is input (JACK –B)
Channel
MIC1-R IO 22 1st Stereo Microphone Input Right Analog input/output, default is input (JACK –B)
Channel
LINE1-L IO 23 1st Line Input Left Channel Analog input/output, default is input (JACK –C)
LINE1-R IO 24 1st Line Input Right Channel Analog input/output, default is input (JACK –C)
PCBEEP I 12 External PCBEEP Input Analog input, 1.6Vrms of full-scale input
ALC887
Datasheet
FRONT-L IO 35 Front Output Left Channel Analog output (JACK –D)
FRONT-R IO 36 Front Output Right Channel Analog output (JACK –D)
SURR–L IO 39 Surround Out Left Channel Analog output (JACK –A)
SURR–R IO 41 Surround Out Right Channel Analog output (JACK –A)
CENTER O 43 Center Output Analog output (JACK –G)
LFE O 44 Low Frequency Output Analog output (JACK –G)
SIDE–L O 45 Side Output Left Channel Analog output (JACK –H)
SIDE–R O 46 Side Output Right Channel Analog output (JACK –H)
Sense A I 13 Jack Detect Pin l Jack resistor network input 1 for port A/B/C/D
{39.2k, 20k, 10k, 5.1k} with 1% accuracy
Sense B I 34 Jack Detect Pin 2 Jack resistor network input 2 for port E/F/G/H
Sense C I 33 Jack Detect Pin 3 Jack resistor network input 3 for CD, 1st SPDIF
Out, 2nd SPDIF Out, SPDIF-IN
Total: 23 Pins
6.3. Filter/Reference
Table 3. Filter/Reference
VREF - 27 2.5V Reference Voltage 10µf capacitor to analog ground
MIC1-VREFO-L O 28 Bias Voltage for MIC1 Jack 2.5V/3.75V reference voltage
LINE1-VREFO O 29 Bias Voltage for LINE1 Jack 2.5V/3.75V reference voltage
MIC2-VREFO O 30 Bias Voltage for MIC2 Jack 2.5V/3.75V reference voltage
LINE2-VREFO O 31 Bias Voltage for LINE2 Jack 2.5V/3.75V reference voltage
MIC1-VREFO-R O 32 Bias Voltage for MIC1 Jack 2.5V/3.75V reference voltage
NC - 37 Not Connection
JDREF - 40 Reference Resistor for Jack Detection 20K, 1% external resistor to analog ground
Total: 8 Pins

ALC887
Datasheet
6.4. Power/Ground
Table 4. Power/Ground
AVDD1 I 25 Analog VDD Analog power for mixer and amplifier
AVSS1 I 26 Analog GND Analog ground for mixer and amplifier
AVDD2 I 38 Analog VDD Analog power for DACs and ADCs
AVSS2 I 42 Analog GND Analog ground for DACs and ADCs
DVDD I 1 Digital VDD Digital power for core
DVDD-IO I 9 Digital VDD Digital IO power for HDA bus
DVSS I 7 Digital GND Digital ground for HDA bus
Total: 7 Pins

ALC887
Datasheet
7. High Definition Audio Link Protocol

7.1. Link Signals
The High Definition Audio (HDA) link is the digital serial interface that connects the HDA codecs to the
HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent
by the HDA controller. The input and output streams, including command and PCM data, are isochronous
with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol.
Previous Frame Tframe_sync = 20.833 盜 (48KHz)

Next Frame
BCLK
Frame SYNC= 8 BCLK Stream 'A' Tag Stream 'B' Tag

(Here 'A' = 5) (Here 'B' = 6)
SYNC
SDO Command Stream Stream 'A' Data Stream 'B' Data
(40-bit data)
SDI Stream
Response Stream 'C' Tag Stream 'C' Data
(36-bit data) (n bytes + 10-bit data)
RST#
Figure 4. HDA Link Protocol

ALC887
Datasheet
7.1.1. Signal Definitions

Table 5. Link Signal Definitions
Item Description
BCLK 24.0MHz bit clock sourced from the HDA controller and connecting to all codecs.
SYNC 48kHz of signal is used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs.
SDO Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are carried
on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec samples data
present on SDO with respect to each edge of BCLK. The HDA controller must support at least one SDO. To
extend outbound bandwidth, multiple SDOs may be supported.
SDI Serial data input signal driven by the codec. This is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be supported.
SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of
BCLK. SDI can be driven by the controller to initialize the codec’s ID.
RST# Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the
HDA controller and connects to all codecs.
Table 6. HDA Signal Definitions

Signal Name Source Type for Controller Description
BCLK Controller Output Global 24.0MHz bit clock
SYNC Controller Output Global 48kHz Frame Sync and outbound tag signal
SDO Controller Output Serial data output from controller
SDI Codec/Controller Input/Output Serial data input from codec. Weakly pulled down by the
controller
RST# Controller Output Global active low reset signal
BCLK
SYNC 8-Bit Frame SYNC

Start of Frame
SDO 7 6 5 4 3 2 1 0 999 998 997 996 995 994 993 992 991 990
SDI 3 2 1 0 499 498 497 496 495 494
Codec samples SDO at both rising and falling edge of BCLK

Controller samples SDI at rising edge of BCLK
Figure 5. Bit Timing

ALC887
Datasheet
7.1.2. Signaling Topology

The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream.
RST#, BCLK, SYNC, SDO0 and SDO1 are driven by controller to codecs. Each codec drives its own
point-to-point SDI signal(s) to the controller.
Figure 6 shows the possible connections between the HDA controller and codecs:
• Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission
• Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate
• Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate
• Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and
codecs. Section 7.2 Frame Composition, page 14 describes the detailed outbound and inbound stream
compositions for single and multiple SDOs/SDIs.
The connections shown in Figure 7 can be implemented concurrently in an HDA system. The ALC887 is
designed to receive a single SDO stream.
SDI14
.
.
.
.
.
.
SDI13
SDI2
HDA SDI1
Controller SDI0
SDO1
SDO0
SYNC
BCLK
RST#
SYNC
SYNC
SYNC
SYNC
SDO0
SDO0
SDO1
SDO0
BCLK
SDO0
SDO1
RST#
BCLK
BCLK
BCLK
S DI0
SDI0
RST#
SDI0
SDI0
SDI1
SDI1
SDI2
RST#
RST#
...
Codec 0 Codec 1 Codec 2 Codec N
Single SDO Two SDOs Single SDO Two SDOs

Single SDI Single SDI Two SDIs Multiple SDIs
Figure 6. Signaling Topology

ALC887
Datasheet
7.2. Frame Composition

7.2.1. Outbound Frame – Single SDO
An outbound frame is composed of one 32-bit command stream and multiple data streams. There are one
or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA
controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the
sample rate is a multiple of 48kHz. This means there should be two blocks in the same stream to carry
96kHz samples (Figure 7).
For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started
at the end of the stream tag. The stream tag includes a 4-bit preamble and 4-bit stream ID (Figure 8).
To keep the cadence of converters bound to the same stream, samples for these converters must be placed
in the same block.
Previous Frame
A 48kHz Frame is composed of Command stream and multiple Data streams Next Frame
Frame SYNC Stream 'A' Tag Stream 'X' Tag

SYNC (Here 'A' = 5) (Here 'X' = 6)
SDO Command Stream Stream 'A' Data Stream 'X' Data 0s
Null Field Padded at the

Sample Block(s) One or multiple blocks in a stream end of Frame
.. For 48kHz rate, only Block1 is included

Block 1 Block 2 Block Y For 96kHz rate, Block1 includes (N)th time of samples, Block2
.
includes (N+1)th time of samples
..
Sample 1 Sample 2 Sample Z Z channels of PCM Sample
.
msb ... lsb msb first in a sample
Figure 7. SDO Outbound Frame
BCLK
Stream Tag
msb lsb
SYNC 1010
Preamble Stream=10 Data of Stream 10

(4-Bit) (4-Bit)
ms b
SDO 7 6 5 4 3 2 1 0
Previous Stream
Figure 8. SDO Stream Tag is Indicated in SYNC

ALC887
Datasheet
7.2.2. Outbound Frame – Multiple SDOs

The HDA controller allows two SDO signals to be used to stripe outbound data, completing transmission
in less time to get more bandwidth. If software determines that the target codec supports multiple SDO
capability, it enables the ‘Stripe Control’ bit in the controller’s Output Stream Control Register to initiate
a specific stream (Stream ‘A’ in Figure 9) to be transmitted on multiple SDOs. In this case, the MSB of
the stream data is always carried on SDO0, the second bit on SDO1 and so forth.
SDO1 is for transmitting a striped stream. The codec does not support multiple SDOs connected to
SDO0.
To ensure that all codecs can determine their corresponding stream, the command stream is not striped. It
is always transmitted on SDO0, and copied on SDO1.
S tre a m 'A ' T a g S tre a m 'X ' T a g S tre a m 'Y ' T a g
SYNC
F ra m e S Y N C
S tre a m 'A ' to C o d e c A
S D O0 ..
C o m m a n d S tre a m S tre a m 'X ' to C o d e c X S tre a m 'Y ' to C o d e c Y
.
Dn Dn -2
..
S D O1 C o m m a n d S tre a m . 0s 0s
..
D Dn -3 .
n -1
S tre a m A is "b it-s trip e d " o n S D O 0 a n d S D O 1
C o m m a n d s tre a m is u n c h a n g e d , n o t s trip e d
Figure 9. Striped Stream on Multiple SDOs

ALC887
Datasheet
7.2.3. Inbound Frame – Single SDI

An Inbound Frame – A single SDI is composed of one 36-bit response stream and multiple data streams.
Except for the initialization sequence (turnaround and address frame), the SDI is driven by the codec at
each rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 10).
The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream
includes one 4-bit stream tag, one 6-bit data length, and n-bit sample blocks. Zeros will be padded if the
total length of the contiguous sample blocks within a given stream is not of integral byte length (Figure
11).
Previous Frame A 48kHz Frame is Composed of a Response Stream and Multiple Data streams Next Frame
Frame SYNC
SYNC
SDI Response Stream Stream 'A' Stream 'X' 0s
Null Field Padded at the end of Frame

Stream Tag Sample Block(s)
For 48kHz rate, only Block1 is included

Block 1 Block 2 ... Block Y Null Pad For 96kHz rate, Block{1, 2} includes {(N)th (N+1)th} time of samples
Sample 1 Sample 2 ... Sample Z Z channels of PCM Sample
msb ... lsb msb first in a sample
Figure 10. SDI Inbound Stream
BCLK
Stream Tag Data Length in Bytes n-Bit Sample Block Null Pad Next Stream
SDI B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Dn-1 Dn-2 D0 0 0 0 0
(Data Length in Bytes *8)-Bit

A Complete Stream
Figure 11. SDI Stream Tag and Data

ALC887
Datasheet
7.2.4. Inbound Frame – Multiple SDIs

A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound
stream exceeds the data transfer limits of a single SDI, the codec can divide the data into separate SDI
signals, each of which operate independently, with different stream numbers at the same frame time. This
is similar to having multiple codecs connected to the controller. The controller samples the divided stream
into separate memory with multiple DMA descriptors, then software re-combines the divided data into a
meaningful stream.
SYNC
Frame SYNC
Stream 'A'
SDI 0 Response Stream Tag A Data A Stream 'X' Stream 'Y'
Stream 'B'
SDI 1 Response Stream Tag B Data B 0s 0s
Codec drives SDI0 and SDI1 Stream A, B, X, and Y are independent and have separate IDs
Figure 12. Codec Transmits Data Over Multiple SDIs
7.2.5. Variable Sample Rates

The HDA link is designed for sample rates of 48kHz. Variable rates of sample are delivered in multiple or
sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample
block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate
of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own
sample rate, independent of any other stream.
The HDA controller supports 48kHz and 44.1kHz base rates. Table7, page 18, shows the recommended
sample rates based on multiples or sub-multiples of one of the two base rates.
Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in
multiples (n) of 48kHz contain n sample blocks in a frame. Table 8, shows the delivery cadence of
variable rates based on 48kHz.
The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple
rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid
frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample
blocks are transmitted every 160 frames.
The cadence ‘12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)’ interleaves 13 frames containing no

sample blocks in every 160 frames. It provides a low long-term frequency drift for 44.1kHz of delivery
rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence and interleave n empty frames.

ALC887
Datasheet
Rates in multiples (n) of 44.1kHz applying this cadence contain n sample blocks in the non-empty frame
AND interleave an empty frame between non-empty frames (Table 9).
Table 7. Defined Sample Rate and Transmission Rate

(Sub) Multiple 48kHz Base 44.1kHz Base
1/6 8kHz (1 sample block every 6 frames) -
1/4 12kHz (1 sample block every 4 frames) 11.025kHz (1 sample block every 4 frames)
1/3 16kHz (1 sample block every 3 frames) -
1/2 - 22.05kHz (1 sample block every 2 frames)
2/3 32kHz (2 sample blocks every 3 frames) -
1 48kHz (1 sample block per frame) 44.1kHz (1 sample block per frame)
2 96kHz (2 sample blocks per frame) 88.2kHz (2 sample blocks per frame)
4 192kHz (4 sample blocks per frame) 176.4kHz (4 sample blocks per frame)
Table 8. 48kHz Variable Rate of Delivery Timing

Rate Delivery Cadence Description
8kHz YNNNNN (repeat) One sample block is transmitted in every 6 frames
12kHz YNNN (repeat) One sample block is transmitted in every 4 frames
16kHz YNN (repeat) One sample block is transmitted in every 3 frames
32kHz Y2NN (repeat) One sample block is transmitted in every 6 frames
48kHz Y (repeat) One sample block is transmitted in every 6 frames
96kHz Y2 (repeat) Two sample blocks are transmitted in each frame
192kHz Y4 (repeat) Four sample blocks are transmitted in each frame
N: No sample block in a frame.
Y: One sample block in a frame.
Yx: X sample blocks in a frame

ALC887
Datasheet
Table 9. 44.1kHz Variable Rate of Delivery Timing

Rate Delivery Cadence
11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
22.05kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
44.1kHz 12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)
88.2kHz 122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat)
174.4kHz 124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)
11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{ - } =NNNN
22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN
{11}=YNYNYNYNYNYNYNYNYNYNYN
{ - }=NN
44.1kHz 12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with no
sample block.
sample block.
sample block.

ALC887
Datasheet
7.3. Reset and Initialization

There are two types of reset within an HDA link:
• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
• Codec Reset. Generated by software directing a command to reset a specific codec back to its default
state
An initialization sequence is requested after any of the following three events:
1. Link Reset
2. Codec Reset
3. Codec changes its power state (for example, hot docking a codec to an HDA system)
7.3.1. Link Reset

A link reset may be caused by 3 events:
1. The HDA controller asserts RST# for any reason (power up, or PCI reset)
2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA
controller
3. Software initiates power management sequences. Figure 13, page 21, shows the ‘Link Reset’ timing
including the ‘Enter’ sequence ( ~ ) and ‘Exit’ sequence ( ~ )
Enter ‘Link Reset’:
Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a
link reset
When the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at
the end of the frame
The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low
The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state
All link signals driven by controller and codecs should be tri-state by internal pull low resistors

ALC887
Datasheet
Exit from ‘Link Reset’:
If BCLK is re-started for any reason (codec wake-up event, power management, etc.)
Software is responsible for de-asserting RST# after a minimum of 100µs BCLK running time (the
100µsec provides time for the codec PLL to stabilize)
Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the
last bit of frame SYNC, it means the codec requests an initialization sequence)
Previous Frame 4 BCLK 4 BCLK Link in Reset >=100 usec >= 4 BCLK Initialization Sequence
BCLK
Normal Frame Normal Frame

SYNC SYNC is absent Driven Low Pulled Low SYNC
2 8
SDOs Driven Low Pulled Low
Wake Event
SDIs Driven Low Pulled Low
9
RST# Pulled Low
1 3 4 5 6 7
Figure 13. Link Reset Timing
7.3.2. Codec Reset

A ‘Codec Reset’ is initiated via the codec RESET command verb. It results in the target codec being reset
to the default state. After the target codec completes its reset operation, an initialization sequence will not
be requested. In the extended power state, a function reset cannot initialize the register setting in power
state D3. The Host SW needs to send a ‘double function reset’ to reset all settings.
7.3.3. Double Function Reset

Double Function Reset is executed by sending two Function Group resets back to back. This Function
Group ‘Double’ reset shall do a full initialization and reset all settings to their power on defaults. This
Double Reset is defined as two Function Group Reset verbs received without any other intervening valid
verbs. The reset verbs are not required to be received in sequential frames, but there must not be any other
verbs received in frames between the consecutive Function Group Reset verbs. It is allowed that there are
several null commands received in frames between Function Group Reset verbs.

ALC887
Datasheet
7.3.4. Codec Initialization Sequence

The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the
controller
The codec will stop driving the SDI during this turnaround period
The controller drives SDI to assign a CAD to the codec
The controller releases the SDI after the CAD has been assigned
Normal operation state

Exit from Reset Connection Frame Turnaround Frame Address Frame
(Non- 48kHz Frame) (Non-48kHz Frame) Normal Operation
BCLK
Frame SYNC Frame SYNC Frame SYNC

SYNC
4 5 6 Response
SDIx
SD0 SD1 SD14
1 2 3 7 8
RST#
Codec Codec Controller Drives SDIx Controller Codec Drives SDIx
Drives SDIx Turnaround Turnaround
( 477 BCLK ( 477 BCLK
Max.) Max.)
Figure 14. Codec Initialization Sequence
7.4. Verb and Response Format

7.4.1. Command Verb Format
There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with
12-bit identifiers (12-bit verbs) and 8-bits of data. Table 10 shows the 4-bit verb structure of a command
stream sent from the controller to operate the codec. Table 11 is the 12-bit verb structure that gets and
controls parameters in the codec.
Table 10. 40-Bit Commands in 4-Bit Verb Format

Bit [39:32] Bit [31:28] Bit [27:20] Bit [19:16] Bit [15:0]
Reserved Codec Address Node ID Verb ID Payload
Table 11. 40-Bit Commands in 12-Bit Verb Format

Bit [39:32] Bit [31:28] Bit [27:20] Bit [19:8] Bit [7:0]
Reserved Codec Address Node ID Verb ID Payload

ALC887
Datasheet
Table 12. Supported Commands
Modem Function Group*1
HDMI Function Group*1
Vendor Define Group*1

Audio Function Group
Vendor Define Widget

Audio Out Converter
Audio In Converter
Beep Generator
Selector Widget
Power Widget*1
Volume Knob
Sum Widget
Pin Widget
Root Node
Get Verb
Set Verb
Supported Verb
Get parameter F00 - Y Y - - - Y Y Y Y Y Y Y Y Y

Connection Select F01 701 - - - - - - Y Y - Y - - - -
Get Connection List F02 - - - - - - - Y Y Y Y - - - -
Entry
Processing State F03 703 - - - - - - - - - - - - - -
Coefficient Index D-- 5-- - - - - - - - - - - - - - Y
Processing Coefficient C-- 4-- - - - - - - - - - - - - - Y
Amplifier Gain/Mute B-- 3-- - - - - - - Y Y Y - - - - -
Stream Format A-- 2-- - - - - - Y Y - - - - - - -
Digital Converter 1 F0D 70D - - - - - Y Y - - - - - - -
Digital Converter 2 F0D 70E - - - - - Y Y - - - - - - -
Power State F05 705 - Y - - - - - - - - - - - -
Channel / Stream ID F06 706 - - - - - Y Y - - - - - - -
SDI Select F04 704 - - - - - - - - - - - - - -
Pin Widget Control F07 707 - - - - - - - Y - - - - - -
Unsolicited Enable F08 708 - - - - - - - Y - - - Y - -
Pin Sense F09 709 - - - - - - - Y - - - - - -
EAPD / BTL Enable F0C 70C - - - - - - - - - - - - - -
All GPIO Control F10- 710- - - - - - - - - - - - - - -
F1A 71A
Beep Generator Control F0A 70A - - - - - - - - - - - - Y -
Volume Knob Control F0F 70F - - - - - - - - - - - - - -
Subsystem ID, Byte 0 F20 720 - Y - - - - - - - - - - - -
Config Default, Byte 0 F1C 71C - - - - - - - Y - - - - - -
Config Default, Byte 1 F1C 71D - - - - - - - Y - - - - - -
Config Default, Byte 2 F1C 71E - - - - - - - Y - - - - - -
Config Default, Byte 3 F1C 71F - - - - - - - Y - - - - - -
RESET - 7FF - Y - - - - - - - - - - - -
*1: The ALC887 does not support Modem/HDMI/Vendor groups and Power State widgets.

ALC887
Datasheet
Table 13. Supported Parameters
Modem Function Group*1
HDMI Function Group*1
Vendor Define Group*1

Audio Function Group
Vendor Define Widget

Audio Out Converter
Audio In Converter
Beep Generator
Selector Widget
Power Widget*1
Parameter ID
Volume Knob
Sum Widget
Pin Widget
Root Node
Supported Parameter
Vendor ID 00 Y - - - - - - - - - - - - -
Revision ID 02 Y - - - - - - - - - - - - -
Subordinate Node Count 04 Y Y - - - - - - - - - - - -
Function Group Type 05 - Y - - - - - - - - - - - -
Audio Function Group Capabilities 08 - Y - - - - - - - - - - - -
Audio Widget Capabilities 09 - - - - - Y Y Y Y Y Y Y Y Y
Sample Size, Rate 0A - Y - - - Y Y - - - - - - -
Stream Formats 0B - Y - - - Y Y - - - - - - -
Pin Capabilities 0C - - - - - - - Y - - - - - -
Input Amp Capabilities 0D - - - - - - Y - Y Y - - - -
Output Amp Capabilities 12 - - - - - - - Y Y - - - - -
Connection List Length 0E - - - - - - Y Y Y Y - - - -
Supported Power States 0F - Y - - - Y Y Y Y Y - - - Y
Processing Capabilities 10 - - - - - - - - - - - - - Y
GPI/O Count 11 - - - - - - - - - - - - - -
Volume Knob Capabilities 13 - - - - - - - - - - - - - -
*1: The ALC887 does not support Modem/HDMI/Vendor groups and Power State widgets.

ALC887
Datasheet
7.4.2. Response Format

There are two types of response from the codec to the controller. Solicited Responses are returned by the
codec in response to a current command verb. The codec will send Solicited Response data in the next
frame, without regard to the Set (Write) or Get (Read) command. The 32-bit Response is interpreted by
software, opaque to the controller.
Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI
status information can be actively delivered to the controller and interpreted by software. The ‘Tag’ in
Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.
Table 14. Solicited Response Format

Bit [35] Bit [34] Bit [33:32] Bit [31:0]
Valid Unsol=0 Reserved Response
Table 15. Unsolicited Response Format

Bit [35] Bit [34] Bit [33:32] Bit [31:28] Bit [27:0]
Valid Unsol=1 Reserved Tag Response
Note: The response stream in the link protocol is 36-bits wide. The response is placed in the lower 32-bit
field. Bit-35 is a ‘Valid’ bit to indicate the response is ‘Ready’. Bit-34 is set to indicate that an unsolicited
response was sent.

ALC887
Datasheet
7.5. Power Management

The ALC887 does not support Wake-Up events when in low power mode. All power management state
changes in widgets are driven by software. Table 16 shows the System Power State Definitions.
In the ALC887, all the widgets, including output/input converters, support power control. Software may
have various power states depending on system configuration. Table 17 indicates those nodes that support
power management. To simplify power control, software can configure whole codec power states through
the audio function (NID=01h). Output converters (DACs) and input converters (ADCs) have no
individual power control to supply fine-grained power control.
Table 16. System Power State Definitions

Power States Definitions
D0 All power on. Individual DACs and ADCs can be powered up or down as required.
D1 All amplifiers and converters (DACs and ADCs) are powered down. State maintained, analog reference
stays up.
D2 All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but analog
reference is off (D1 + analog reference off).
D3 (Hot) Power still supplied. The codec stops the internal clock. State is maintained.
D3 (Cold) All Power removed. State lost.
Table 17. Power Controls in NID 01h

Item Description D0 D1 D2 D3 Link Reset
Audio Function LINK Response Normal Normal Normal PD PD
(NID=01h) Front DAC Normal PD PD PD PD
Surr DAC Normal PD PD PD PD
Cen/Lfe DAC Normal PD PD PD PD
Side DAC Normal PD PD PD PD
LINE ADC Normal PD PD PD PD
MIX ADC Normal PD PD PD PD
All Headphone Drivers Normal Normal PD PD Normal
All Mixers Normal Normal PD PD Normal
All Reference Normal Normal PD PD Normal
Note: PD=Powered Down

ALC887
Datasheet
Table 18. Powered Down Conditions

Condition Description
LINK Response powered down Internal clock is stopped. SDATA-IN and SPDIF-OUT are floated with pulled low
47K resistors internally. SPDIF-IN is also floated. Detection of ‘Link Reset Entry’
and ‘Link Reset Exit’ sequences are supported. All states are maintained if DVDD
is supplied
Front DAC powered down Analog block and digital filter are powered down
Surr DAC powered down Analog block and digital filter are powered down
CEN/LFE DAC powered down Analog block and digital filter are powered down
SIDESURR DAC powered down Analog block and digital filter are powered down
LINE ADC powered down Analog block and digital filter are powered down. Data on SDATA-IN is quiet
MIX ADC powered down Analog block and digital filter are powered down. Data on SDATA-IN is quiet
Headphone Driver powered down All headphone drivers are powered down
Mixers powered down All internal mixer widgets are powered down. The DC reference and VREFOUTx
at individual pin complexes are still alive
Reference power down All internal references, DC reference, and VREFOUTx at individual pin
complexes are off
7.5.1. ALC887 Additional Power Features

The ALC887 is designed to meet Intel’s low-power-state white paper and is ECR HDA-015B compliant.
It meets the five attributes discussed in the white paper:
1. D3 state power < 30mW.
2. Exit latency (D3 to D0 transfer) < 10ms.
3. Audio pop/click suppression during D3 and D0 transition < -65dBV.
4. Supports Jack detection in D3 state.
5. D3 functions with or without the BITCLK
The ALC887 minimizes D3 state idle mode power consumption and increases overall battery life in
mobile systems.
In D3 mode, only a power on reset or a ‘double function reset’ resets all ALC887 settings, cutting
software configuration time spent entering/leaving D3 state, and reducing latency time for D3 to D0
transitions.
The ALC887 supports Wake-Up events in D3 mode, including jack detection and GPIO status changes. If
the HDA-Link was alive (with BCLK), the ALC887 Wake-Up response is as normal. If no BITCLK is
present, the ALC887 drives the SDI high in order to wake up the system

ALC887
Datasheet
8. Supported Verbs and Parameters

This section describes the Verbs and Parameters supported by various widgets in the ALC887. If a verb is
not supported by the addressed widget, it will respond with 32 bits of ‘0’.
8.1. Verb – Get Parameters (Verb ID=F00h)

The ‘Get Parameters’ verb is used to get system information and the function capabilities of the HDA
codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget.
Some parameters are supported only in a specific widget. Refer to section 7.4.1 Command Verb Format,
to get detailed information about supported parameters.
Table 19. Verb – Get Parameters (Verb ID=F00h)

Get Parameter Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=00h Verb ID=F00h Parameter ID[7:0] 32-bit Response
Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’.
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)

Table 20. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Codec Response Format
Bit Description
31:16 Vendor ID=10ECh (Realtek’s PCI vendor ID)
15:0 Device ID=0887h
Note: The Root Node (NID=00h) supports this parameter.
8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)

Table 21. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Bit Description
31:24 Reserved. Read as 0’s
23:20 MajRev. The major version number (in decimal) of the HDA Spec to which the ALC887 is fully compliant
19:16 MinRev. The minor version number (in decimal) of the HDA Spec to which the ALC887 is fully compliant
15:8 Revision ID. The vendor’s revision number.
02h is for ALC887.
7:0 Stepping ID. The vendor’s stepping number within the given Revision ID
Note: The Root Node (NID=00h in the ALC887) supports this parameter.

ALC887
Datasheet
8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h,

Parameter ID=04h)
For the root node, the Subordinate Node Count provides information about audio function group nodes
associated with the root node. For function group nodes, it provides the total number of widgets
associated with this function node.
Table 22. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
Bit Description
31:24 Reserved. Read as 0’s.
23:16 Starting Node Number.
The starting node number in the sequential widgets
7:0 Total Number of Nodes. For a root node, the total number of function groups in the root node.
For a function group, the total number of widget nodes in the function group
8.1.4. Parameter – Function Group Type (Verb ID=F00h,

Parameter ID=05h)
Table 23. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)
Bit Description
8 UnSol Capable.
0: Unsolicited response is not supported by this function group
1: Unsolicited response is supported by this function group
7:0 Function Group Type.
00h: Reserved 01h: Audio Function 02h: Modem Function
03h~7Fh: Reserved 80h~FFh: Vendor Defined Function
Note: The Audio Function Group (NID=01h) supports this parameter.
8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h,

Parameter ID=08h)
Table 24. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Bit Description
16 Beep Generator. A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group.
11:8 Input Delay.
3:0 Output Delay.
Note: The Audio Function Group (NID=01h) supports this parameter.

ALC887
Datasheet
8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h,

Parameter ID=09h)
Table 25. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Bit Description
23:20 Widget Type
0h: Audio Output 1h: Audio Input 2h: Mixer
3h: Selector 4h: Pin Complex 5h: Power Widget
6h: Volume Knob Widget 7h~Eh: Reserved Fh: Vendor defined audio widget
19:16 Delay. Samples delayed between the HDA link and widgets
10 Power Control
0: Power state control is not supported on this widget
1: Power state is supported on this widget
9 Digital
0: An analog input or output converter
1: A widget translating digital data between the HDA link and digital I/O (SPDIF, I2S, etc.)
8 ConnList. Connection List
0: Connected to HDA link. No Connection List Entry should be queried
1: Connection List Entry must be queried
7 UnsolCap. Unsolicited Capable
0: Unsolicited response is not supported
1: Unsolicited response is supported
6 ProcWidget. Processing Widget
0: No processing control
1: Processing control is supported
5 Reserved. Read as 0
4 Format Override
3 AmpParOvr, AMP Param Override
2 OutAmpPre. Out AMP Present
1 InAmpPre. In AMP Present
0 Stereo
0: Mono Widget
1: Stereo Widget

ALC887
Datasheet
8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h,

Parameter ID=0Ah)
Parameters here provide default information about formats. Individual converters have their own
parameters to provide supported formats if their ‘Format Override’ bit is set.
Table 26. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Bit Description
20 B32. 32-bit audio format support
0: Not supported 1: Supported
11 R12. 384kHz (=8*48kHz) rate support
9 R10. 176.4kHz (=4*44.1kHz) rate support
7 R8. 88.2kHz (=2*44.1kHz) rate support
6 R7. 48kHz rate support
5 R6. 44.1kHz rate support
4 R5. 32kHz (=2/3*48kHz) rate support
3 R4. 22.05kHz (=1/2*44.1kHz) rate support
1 R2. 11.025kHz (=1/4*44.1kHz) rate support

ALC887
Datasheet
8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h,

Parameter ID=0Bh)
Parameters in this node only provide default information for audio function groups. Individual converters
have their own parameters to provide supported formats if the ‘Format Override’ bit is set.
Table 27. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Bit Description
2 AC3
1 Float32
0 PCM
Note: Input converters and output converters support this parameter.
8.1.9. Parameter – Pin Capabilities (Verb ID=F00h,

Parameter ID=0Ch)
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.
Table 28. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)

Bit Description
15:8 VREF Control Capability. ‘1’ in corresponding bit field indicates signal levels of associated Vrefout are
specified as a percentage of AVDD.
7:6 5 4 3 2 1 0
Reserved 100% 80% Reserved Ground 50% Hi-Z
7 L-R Swap. Indicates the capability of swapping the left and rights
6 Balanced I/O Pin. ‘1’ indicates this pin complex has balanced pins.
5 Input Capable. ‘1’ indicates this pin complex supports input.
4 Output Capable. ‘1’ indicates this pin complex supports output.
3 Headphone Drive Capable. ‘1’ indicates this pin complex has an amplifier to drive a headphone.
2 Presence Detect Capable. ‘1’ indicates this pin complex can detect whether there is anything plugged in.
1 Trigger Required. ‘1’ indicates whether a software trigger is required for an impedance measurement.
0 Impedance Sense Capable.
‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type
Note: Only Pin Complex widgets support this parameter.

ALC887
Datasheet
8.1.10. Parameter – Amplifier Capabilities (Verb ID=F00h,

Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 29. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Bit Description
31 (Input) Mute Capable
30:23 Reserved. Read as 0
22:16 Step Size
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB
14:8 Number of Steps
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed
6:0 Offset
Indicates which step is 0dB
8.1.11. Parameter – Amplifier Capabilities (Verb ID=F00h,

Output Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 30. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Bit Description
31 (Output) Mute Capable
22:16 Step Size
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB
14:8 Number of Steps
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed
6:0 Offset. Indicates which step is 0dB

ALC887
Datasheet
8.1.12. Parameter – Connect List Length (Verb ID=F00h,

Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.
Table 31. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Bit Description
7 Short Form
0: Short Form 1: Long Form
6:0 Connect List Length
Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one input,
and there is no Connection Select Control (Not a MUX widget)
8.1.13. Parameter – Supported Power States (Verb ID=F00h,

Parameter ID=0Fh)
Table 32. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
Bit Description
3 D3Sup
1: Power state D3 is supported
2 D2Sup
1 D1Sup
0 D0Sup
8.1.14. Parameter – Processing Capabilities (Verb ID=F00h,

Parameter ID=10h)
Table 33. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)
Bit Description
15:8 NumCoeff. Number of Coefficient
0 Benign
0: Processing unit is not linear and time invariant
1: Processing unit is linear and time invariant

ALC887
Datasheet
8.1.15. Parameter – GPIO Capabilities (Verb ID=F00h,

Parameter ID=11h)
Table 34. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)
Bit Description
31 GPIWake=0
The ALC887 does not support GPIO wake up function
30 GPIUnsol=1
The ALC887 supports GPIO unsolicited response
23:16 NumGPIs=00h
No GPI pin is supported
15:8 NumGPOs=00h
No GPO pin is supported
7:0 NumGPIOs=02h
Three GPIO pins are supported
8.1.16. Parameter – Volume Knob Capabilities (Verb ID=F00h,

Parameter ID=13h)
Table 35. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)
Codec Response Format for NID=21h (Volume Control Knob)
Bit Description
7 Delta
0: Software cannot modify the Volume Control Knob volume
1: Software can write a base volume to the Volume Control Knob
6:0 NumSteps
The number of steps in the range of the Volume Control Knob

ALC887
Datasheet
8.2. Verb – Get Connection Select Control (Verb ID=F01h)

Table 36. Verb – Get Connection Select Control (Verb ID=F01h)
Get Command Format Codec Response Format
CAd=X Node ID=Xh Verb ID=F01h 0’s Bit[7:0] are Connection Index
Codec Response for Analog Port-A/B/C/D/E/F/G/H

Bit Description
31:8 0’s
7:0 Connection Index Currently Set (Default value is 00h)
00h: Sum Widget NID=0Ch 01h: Sum Widget NID=0Dh
02h: Sum Widget NID=0Eh 03h: Sum Widget NID=0Fh
Other: Reserved
Codec Response for first Digital Pin SPDIF-OUT 1Eh

Bit Description
31:8 0’s
00h: Digital Converter (SPDIF-OUT) NID=06h
Other: Reserved
Codec Response for second Digital Pin SPDIF-OUT 11h

Bit Description
31:8 0’s
00h: Digital Converter (SPDIF-OUT) NID=10h
Other: Reserved
Codec Response for other NID

Bit Description
31:0 Not Supported (returns 00000000h)
8.3. Verb – Set Connection Select (Verb ID=701h)

Table 37. Verb – Set Connection Select (Verb ID=701h)
Set Command Format Codec Response Format
CAd=X Node ID=Xh Verb ID=701h Select Index [7:0] 0’s for all nodes

ALC887
Datasheet
8.4. Verb – Get Connection List Entry (Verb ID=F02h)

Table 38. Verb – Get Connection List Entry (Verb ID=F02h)
CAd=X Node ID=Xh Verb ID=F02h Offset Index - N[7:0] 32-bit Response
Codec Response for NID=08h (LINE ADC)

Bit Description
31:8 Connection List Entry (N+3), (N+2) and (N+1)
Returns 000000h
7:0 Connection List Entry (N)
Returns 23h (Sum Widget) for N=0~3 Returns 00h for N>3
Codec Response for NID=09h (MIX ADC)

Bit Description
Returns 000000h
Returns 22h (Sum Widget) for N=0~3 Returns 00h for N>3
Codec Response for NID=0Ah (SPDIF-IN Converter)

Bit Description
Returns 000000h
Returns 1Fh (SPDIF-IN Pin Widget) for N=0~3 Returns 00h for N>3
Codec Response for NID=0Bh (Mixer)

Bit Description
31:24 Connection List Entry (N+3)
Returns 1Bh (Pin Complex – LINE2) for N=0~3
Returns 15h (Pin Complex-SURR) for N=4~7 Returns 00h for N>7
Returns 1Ah (Pin Complex – LINE1) for N=0~3
Returns 14h (Pin Complex – FRONT) for N=4~7 Returns 00h for N>7
Returns 19h (Pin Complex – MIC2) for N=0~3.
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7
Returns 17h (Pin Complex – SIDESURR) for N=8~11 Returns 00h for N>11
Returns 18h (Pin Complex – MIC1) for N=0~3
Returns 1Ch (Pin Complex – CD) for N=4~7
Returns 16h (Pin Complex – CEN/LFE) for N=8~11 Returns 00h for N>11

ALC887
Datasheet
Codec Response for NID=0Ch (Front Sum)
Bit Description
Returns 00h
Returns 00h
Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3
Returns 02h (Front DAC) for N=0~3 Returns 00h for N>3
Codec Response for NID=0Dh (Surround Sum)

Bit Description
Returns 00h
Returns 00h
Returns 03h (Surround DAC) for N=0~3 Returns 00h for N>3.
Codec Response for NID=0Eh (Cen/Lfe Sum)

Bit Description
Returns 00h
Returns 00h
Returns 04h (Cen/Lfe DAC) for N=0~3 Returns 00h for N>3
Codec Response for NID=0Fh (Side-Surr Sum)

Bit Description
Returns 00h
Returns 00h
Returns 05h (Front DAC) for N=0~3 Returns 00h for N>3

ALC887
Datasheet
Codec Response for NID=14h~1Bh (Port-A to port-H)

Bit Description
Returns 0Fh (Sum Widget NID=0Fh) for N=0~3
Returns 00h for n>3
Returns 0Eh (Sum Widget NID=0Eh) for N=0~3
Returns 00h for N>3
Returns 0Dh (Sum Widget NID=0Dh) for N=0~3
Returns 00h for N>3
Returns 0Ch (Sum Widget NID=0Ch) for N=0~3
Returns 26h (Sum Widget NID=26h) for N=4~7
Returns 00h for N>7
Codec Response for NID=1Eh (Pin Widget: SPDIF-OUT)

Bit Description
31:16 Connection List Entry (N+3) and (N+2)
Returns 0000h
Returns 00h
Returns 06h (SPDIF-OUT converter) for N=0~3
Returns 00h for N>3
Codec Response for NID= 22h/23h/ (Sum Widget before MIX/LINE ADCs)
Bit Description
Returns 1Bh (Pin Complex – LINE2) for N=0~3
Returns 15h (Pin Complex-SURR) for N=4~7
Returns 00h for N>7
Returns 1Ah (Pin Complex – LINE1) for N=0~3
Returns 14h (Pin Complex – FRONT) for N=4~7
Returns 0Bh (Sum Widget) for N=8~11
Returns 00h for N>11
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7
Returns 17h (Pin Complex – SIDESURR) for N=8~11

ALC887
Datasheet
Codec Response for NID= 22h/23h/ (Sum Widget before MIX/LINE ADCs)
Bit Description
Returns 1Ch (Pin Complex – CD) for N=4~7
Returns 16h (Pin Complex – CEN/LFE) for N=8~11
Codec Response for Other NID

Bit Description
8.5. Verb – Get Processing State (Verb ID=F03h)

Table 39. Verb – Get Processing State (Verb ID=F03h)
CAd=X Node ID=Xh Verb ID=F03h 0’s 32-bit response
Codec Response for All NID

Bit Description
8.6. Verb – Set Processing State (Verb ID=703h)

Table 40. Verb – Set Processing State (Verb ID=703h)
CAd=X Node ID=Xh Verb ID=703h Processing State [7:0] 0’s for all nodes

Bit Description
31:0 0’s

ALC887
Datasheet
8.7. Verb – Get Coefficient Index (Verb ID=Dh)

Table 41. Verb – Get Coefficient Index (Verb ID=Dh)
CAd=X Node ID=Xh Verb ID=Dh 0’s Bit [15:0] are Coefficient Index
Codec Response for NID=20h (Realtek Defined Registers)

Bit Description
15:0 Coefficient Index

Bit Description
8.8. Verb – Set Coefficient Index (Verb ID=5h)

Table 42. Verb – Set Coefficient Index (Verb ID=5h)
CAd=X Node ID=Xh Verb ID=5h Coefficient Index [15:0] 0’s for all nodes

Bit Description
31:0 0’s

ALC887
Datasheet
8.9. Verb – Get Processing Coefficient (Verb ID=Ch)

Table 43. Verb – Get Processing Coefficient (Verb ID=Ch)
CAd=X Node ID=Xh Verb ID=Ch 0’s Processing Coefficient [15:0]
Codec Response for NID=20h (Realtek Defined Registers)

Bit Description
15:0 Processing Coefficient

Bit Description
8.10. Verb – Set Processing Coefficient (Verb ID=4h)

Table 44. Verb – Set Processing Coefficient (Verb ID=4h)
CAd=X Node ID=Xh Verb ID=4h Coefficient [15:0] 0’s for all nodes

Bit Description
31:0 0’s

ALC887
Datasheet
8.11. Verb – Get Amplifier Gain (Verb ID=Bh)

This verb is used to get gain/attenuation settings from each widget.
Table 45. Verb – Get Amplifier Gain (Verb ID=Bh)

CAd=X Node ID=Xh Verb ID=Bh ‘Get’ payload [15:0] Bit[7:0] are responsible for ‘Get’
‘Get’ Payload in Command Bit[15:0]

Bit Description
15 Get Input/Output
0: Input amplifier gain is requested
1: Output amplifier gain is requested
14 Reserved. Read as 0.
13 Get Left/Right
0: Right amplifier gain is requested
1: Left amplifier gain is requested
3:0 Index[3:0] for Input Source
Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored
Codec Response for 08h (LINE ADC) and 09h (MIX ADC)
Bit Description
31:8 0’s
7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute 1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0. (No Output Amplifier Mute)
6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –16.5B~+30dB in 1.5dB steps.
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute)
Codec Response for NID=0Bh (MIXER Sum Widget)

Bit Description
31:8 0’s
0: Unmute 1: Mute (Default for all Index)
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0. (No Output Amplifier Mute)
6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –34.5dB~+12dB in 1.5dB steps.
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute)

ALC887
Datasheet
Codec Response for NID=0Ch~0Fh (Sum Widget: Front, Surr, CenLfe, SideSurr)
Bit Description
31:8 0’s
0: Unmute 1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute)
6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0. (No Input Amplifier Gain)
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –46.5dB~0dB in 1.5dB steps.
Codec Response for NID=14h~1Bh (Pin Complex: Front, Surr, CenLfe, SideSurr, MIC1, MIC2, LINE1, LINE2)
Bit Description
31:8 0’s
7 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute.
0:Unmute 1:Mute (NID=14h~1Bh,Default=1)
6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0’s
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain)
Codec Response to Other NID

Bit Description
8.12. Verb – Set Amplifier Gain (Verb ID=3h)

This verb is used to set amplifier gain/attenuation in each widget.
Table 46. Verb – Set Amplifier Gain (Verb ID=3h)

CAd=X Node ID=Xh Verb ID=3h ‘Set’ payload [7:0] 0’s for all nodes
‘Set’ Payload in Command Bit[15:0]

Bit Description
15 Set Output Amp. ‘1’ indicates output amplifier gain will be set
14 Set Input Amp. ‘1’ indicates input amplifier gain will be set
13 Set Left Amp. ‘1’ indicates left amplifier gain will be set
12 Set Right Amp. ‘1’ indicates right amplifier gain will be set
11:8 Index Offset (for input amplifiers on Sum widgets and Selector Widgets)
5 bits index offset in connection list is used to select which input gain will be set on a Sum or a Selector
widget. The index is ignored if the node is not a Sum or a Selector widget, or the ‘Set Input Amp’ bit is not set
7 Mute
0: Unmute 1: Mute (-∞gain)
6:0 Gain[6:0]. A 7-bit step value specifying the amplifier gain.

ALC887
Datasheet
8.13. Verb – Get Converter Format (Verb ID=Ah)

Table 47. Verb – Get Converter Format (Verb ID=Ah)
CAd=X Node ID=Xh Verb ID=Ah 0’s Bit[15:0] are converter format
Codec Response for NID=02h~06h, 10h (Output Converters: Front, Surr, Cen/Lfe, SideSurr, 1st SPDIF-OUT, 2nd
SPDIF-OUT).
Codec Response for NID=08h~0Ah (Input Converters: LINE, MIX DAC, and SPDIF-IN)
Bit Description
15 Stream Type (TYPE)
0: PCM 1: Non-PCM
14 Sample Base Rate (BASE)
0: 48kHz 1: 44.1kHz
13:11 Sample Base Rate Multiple (MULT)
000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved
10:8 Sample Base Rate Divisor (DIV)
000b: /1 001b: /2 010b: /3 011b: /4 100b: /5
101b: /6 110b: /7 111b: /8
The ALC887 does not support Divisor. Always read as 000b
7 Reserved. Read as 0.
6:4 Bits per Sample (BITS)
000b: 8 bits 001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits
101b~111b: reserved
3:0 Number of Channels
0: 1 channel 1: 2 channels 2: 3 channels ……… 15: 16 channels

Bit Description

ALC887
Datasheet
8.14. Verb – Set Converter Format (Verb ID=2h)

Table 48. Verb – Set Converter Format (Verb ID=2h)
CAd=X Node ID=Xh Verb ID=2h Set format [15:0] 0’s for all nodes
‘Set’ Payload in Command Bit[15:0]

Bit Description
15 Stream Type (TYPE)
0: PCM 1: Non-PCM
14 Sample Base Rate (BASE)
0: 48kHz 1: 44.1kHz
13:11 Sample Base Rate Multiple (MULT)
000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved
10:8 Sample Base Rate Divisor (DIV)
000b: /1 001b: /2 010b: /3 011b: /4
100b: /5 101b: /6 110b: /7 111b: /8
6:4 Bits per Sample (BITS)
000b: 8 bits 001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: Reserved
3:0 Number of Channels
0: 1 channel 1: 2 channels 2: 3 channels ……… 15: 16 channels
8.15. Verb – Get Power State (Verb ID=F05h)

Table 49. Verb – Get Power State (Verb ID=F05h)
CAd=X Node ID=01h Verb ID=Ah 0’s Power State [7:0]
Codec Response for NID=01h (Audio Function Group)

Bit Description
5:4 PS-Act. Actual Power State [1:0]
00: Power state is D0 01: Power state is D1
PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes
(NID=01h), PS-Act is always equal to PS-Set
1:0 PS-Set, Set Power State [1:0]
PS-Set controls the current power setting of the referenced node

Bit Description

ALC887
Datasheet
8.16. Verb – Set Power State (Verb ID=705h)

Table 50. Verb – Set Power State (Verb ID=705h)
CAd=X Node ID=01h Verb ID=705h Power State [7:0] 0’s for all nodes
‘Power State’ in Command Bit[7:0]

Bit Description
5:4 PS-Act. Actual Power State [1:0]
PS-Act indicates the actual power state of the referenced node.
1:0 PS-Set. Set Power State [1:0]
8.17. Verb – Get Converter Stream, Channel (Verb ID=F06h)

Table 51. Verb –Get Converter Stream, Channel (Verb ID=F06h)

CAd=X Node ID=Xh Verb ID=F06h 0’s Stream & Channel [7:0]
Codec Response for NID=02h~06h, 10h (Output Converters: Front, Surr, Cen/Lfe, SideSurr, 1st SPDIF-OUT, 2nd
SPDIF-OUT)
Codec Response for NID=08h~0Ah (Input Converters: LINE ADC, MIX DAC, and SPDIF-IN)
Bit Description
7:4 Stream[3:0]
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
3:0 Channel[3:0]
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its
left and right channel.

Bit Description

ALC887
Datasheet
8.18. Verb – Set Converter Stream, Channel (Verb ID=706h)

Table 52. Verb – Set Converter Stream, Channel (Verb ID=706h)
CAd=X Node ID=Xh Verb ID=706h Stream & Channel [7:0] 0’s for all nodes
‘Stream and Channel’ in Command Bit[7:0]

Bit Description
7:4 Set Stream[3:0]
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
1:0 Set Channel[3:0]
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its
left and right channel
Note: This verb assigns stream and channel for output converters (NID=02h~06h 10hh) and input converters
(NID=08h~0Ah). Other widgets will ignore this verb.
8.19. Verb – Get Pin Widget Control (Verb ID=F07h)

Table 53. Verb – Get Pin Widget Control (Verb ID=F07h)
CAd=X Node ID=Xh Verb ID=F07h 0’s Pin Control [7:0]
Codec Response for NID=14h~1Bh, 1Ch, 1Dh, 1Eh, 11h, 1Fh

(Pin Complex: Front, Surr, CenLfe, SideSurr, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, 1st SPDIF-OUT, 2nd
SPDIF-OUT and SPDIF-IN)
Bit Description
7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for a I/O unit)
0: Disabled 1: Enabled
6 Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit)
5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit)
4: Reserved
2:0 VrefEn (Vrefout Enable Control)
000b: Hi-Z (Disabled) 001b: 50% of AVDD
010b: Ground 0V 011b: Reserved
100b: 80% of AVDD 101b: 100% of AVDD 110b~111b: Reserved

ALC887
Datasheet
Bit Description
8.20. Verb – Set Pin Widget Control (Verb ID=707h)

Table 54. Verb – Set Pin Widget Control (Verb ID=707h)
CAd=X Node ID=Xh Verb ID=707h Pin Control [7:0] 0’s for all nodes
‘Pin Control’ in command [7:0] for NID=14h~1Bh, 1Ch, 1Dh, 1Eh, 11h, 1Fh: (Pin Complex: Front, Surr, CenLfe,
SideSurr, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, 1st SPDIF-OUT, 2nd SPDIF-OUT and SPDIF-IN)
Bit Description
7 H-Phn Enable
6 Out Enable
5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit)
4: Reserved
2:0 VrefEn (Vrefout Enable Control)
000b: Hi-Z (Disabled) 001b: 50% of AVDD 010b: Ground 0V
011b: Reserved 100b: 80% of AVDD) 101b: 100% of AVDD
110b~111b: Reserved
8.21. Verb – Get Unsolicited Response Control (Verb ID=F08h)

Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an
unsolicited response to inform software of a real-time event.
Table 55. Verb – Get Unsolicited Response Control (Verb ID=F08h)

CAd=X Node ID=Xh Verb ID= F08h 0’s 32-bit Response
Codec Response for NID=01h (GPIO), 14h~1Bh (Port A to H)

Bit Description
7 Unsolicited Response is Enabled
3:0 Assigned Tag for Unsolicited Response
The tag[3:0] is assigned by software to determine which widget generates unsolicited responses

ALC887
Datasheet
Bit Description
8.22. Verb – Set Unsolicited Response Control (Verb ID=708h)

Enables a widget to generate an unsolicited response.
Table 56. Verb – Set Unsolicited Response Control (Verb ID=708h)

CAd=X Node ID=Xh Verb ID=708h EnableUnsol [7:0] 0’s for all nodes
‘EnableUnsol’ in Command Bit[7:0] for NID=01h (GPIO), 14h~1Bh (Port A to H)

Bit Description
7 Enable Unsolicited Response
0: Disable
1: Enable
3:0 Tag for Unsolicited Response
Tag[3:0] is defined by software to assign a 4-bit tag for nodes that are enabled to generate unsolicited
responses
8.23. Verb – Get Pin Sense (Verb ID=F09h)

Returns the Presence Detect status and the impedance of a device attached to the pin.
Table 57. Verb – Get Pin Sense (Verb ID=F09h)

CAd=X Node ID=Xh Verb ID= F09h 0’s 32-bit Response
Codec Response for NID = 14h~1Bh, 1Eh, 1Fh

Bit Description
31 Presence Detect Status
0: No device is attached to the pin
1: Device is attached to the pin
30:0 Measured Impedance
The ALC887 does not support hardware impedance detection. This field is read as 0’s.

ALC887
Datasheet
Bit Description
8.24. Verb – Execute Pin Sense (Verb ID=709h)

Table 58. Verb – Execute Pin Sense (Verb ID=709h)
Command Format Codec Response Format
CAd=X Node ID=Xh Verb ID= 709h Right Channel[0] 0’s for all nodes
‘Payload’ in Command Bit[7:0]

Bit Description
0 Right (Ring) Channel Select
0: Sense Left channel (Tip)
1: Sense Right channel (Ring)
The ALC887 does not support hardware impedance sensing and will ignore this control.
8.25. Verb – Get Configuration Default (Verb ID=F1Ch)

Reads the 32-bit sticky register for each Pin Widget configured by software.
Table 59. Verb – Get Configuration Default (Verb ID=F1Ch)

CAd=X Node ID=Xh Verb ID= F1Ch 0’s 32-bit Response
Codec Response for NID=14h, 15h, 16h, 17h, 18h, 19h, 1Ah, 1Bh, 1Eh, 11h and 1Fh
Bit Description
31:0 32-bit configuration information for each pin widget
Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function
Reset Verb).

ALC887
Datasheet
8.26. Verb – Set Configuration Default Bytes 0, 1, 2, 3

(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
The BIOS can use this verb to figure out the default conditions for the Pin Widgets 14h~1Bh and
1Eh~1Fh such as placement and expected default device.
Table 60. Verb – Set Configuration Default Bytes 0, 1, 2, 3

(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
CAd=X Node ID=Xh Verb ID=71Ch, Label [7:0] 0’s for all nodes
71Dh, 71Eh, 71Fh
Note: Supported by Pin Widget NID=14h~1Bh, 1Eh, 11h, and 1Fh. Other widgets will ignore this verb.

Bit Description
31:0 0’s
8.27. Verb – Get BEEP Generator (Verb ID=F0Ah)

Table 61. Verb – Get BEEP Generator (Verb ID= F0Ah)
CAd=X Node ID=Xh Verb ID= F1Bh 0’s Divider [7:0]
‘Response’ for NID=01h (Audio Function Group)

Bit Description
31:8 Reserved
7:0 Frequency Divider, F[7:0]
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in
F[7:0]
The lowest tone is 48kHz/(255*4)=47Hz
The highest tone is 48kHz/(1*4)=12kHz
A value of 00h in F[7:0] disables internal BEEP generator and allows external PCBEEP input

Bit Description
31:0 0’s

ALC887
Datasheet
8.28. Verb – Set BEEP Generator (Verb ID=70Ah)

Table 62. Verb – Set BEEP Generator (Verb ID= 70Ah)
CAd=X Node ID=Xh Verb ID=71Bh Divider [7:0] 0’s for all nodes
‘Divider’ in Set Command

Bit Description
31:8 Reserved
7:0 Frequency Divider, F[7:0]
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in
F[7:0]
The lowest tone is 48kHz/(255*4)=47Hz
The highest tone is 48kHz/(1*4)=12kHz
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Bit Description
31:0 0’s
8.29. Verb – Get GPIO Data (Verb ID=F15h)

Table 63. Verb – Get GPIO Data (Verb ID= F15h)
CAd=X Node ID=Xh Verb ID=F15h 0’s 32-bit Response

Bit Description
31:8 Reserved
7:2 GPIO[7:2] Data. Not supported in the ALC887
1:0 GPIO[1:0] Data
The value written (output) or sensed (input) on the corresponding pin if it is enabled

Bit Description
31:0 0’s

ALC887
Datasheet
8.30. Verb – Set GPIO Data (Verb ID=715h)

Table 64. Verb – Set GPIO Data (Verb ID= 715h)
CAd=X Node ID=Xh Verb ID=715h Data [7:0] 0’s for all nodes
‘Data’ in Set command for NID=01h (Audio Function Group)

Bit Description
31:8 Reserved
7:2 GPIO[7:2] Output Data. Not supported in the ALC887
1:0 GPIO[1:0] Output Data
The value written determines the value driven on a pin that is configured as an output pin

Bit Description
31:0 0’s
8.31. Verb – Get GPIO Enable Mask (Verb ID=F16h)

Table 65. Verb – Get GPIO Enable Mask (Verb ID= F16h)
CAd=X Node ID=Xh Verb ID=F16h 0’s EnableMask [7:0]

Bit Description
31:8 Reserved
7:2 Reserved
1:0 GPIO[1:0] Enable Mask
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control

Bit Description
31:0 0’s

ALC887
Datasheet
8.32. Verb – Set GPIO Enable Mask (Verb ID=716h)

Table 66. Verb – Set GPIO Enable Mask (Verb ID=716h)
CAd=X Node ID=Xh Verb ID=716h Enable Mask [7:0] 0’s for all nodes

Bit Description
31:8 Reserved
7:2 GPIO[7:2] Enable Mask. Not supported in the ALC887
1:0 GPIO[1:0] Enable Mask
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control

Bit Description
31:0 0’s
8.33. Verb – Get GPIO Direction (Verb ID=F17h)

Table 67. Verb – Get GPIO Direction (Verb ID=F17h)
CAd=X Node ID=Xh Verb ID=F17h 0’s Direction [7:0]

Bit Description
31:8 Reserved
7:2 GPIO[7:2] Direction Control. Not supported in the ALC887
1:0 GPIO[1:0] Direction Control
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output

Bit Description
31:0 0’s

ALC887
Datasheet
8.34. Verb – Set GPIO Direction (Verb ID=717h)

Table 68. Verb – Set GPIO Direction (Verb ID=717h)
CAd=X Node ID=Xh Verb ID=717h Direction [7:0] 0’s for all nodes

Bit Description
31:8 Reserved
7:2 GPIO[7:2] Direction Control. Not supported in the ALC887
1:0 GPIO[1:0] Direction Control
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output

Bit Description
31:0 0’s
8.35. Verb – Get GPIO Unsolicited Response Enable Mask

(Verb ID=F19h)
Table 69. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)
CAd=X Node ID=Xh Verb ID=F19h 0’s UnsolEnable [7:0]

Bit Description
31:8 Reserved
7:2 GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC887
1:0 GPIO[1:0] Unsolicited Enable Mask
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed

Bit Description
31:0 0’s

ALC887
Datasheet
8.36. Verb – Set GPIO Unsolicited Response Enable Mask

(Verb ID=719h)
Table 70. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)
CAd=X Node ID=Xh Verb ID=719h UnsolEnable [7:0] 0’s for all nodes

Bit Description
31:8 Reserved
7:2 GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC887
1:0 GPIO[1:0] Unsolicited Enable Mask
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb.
Note 2: The unsolicited response of corresponding GPIO is enabled when it’s ‘Enable Mask’ and Verb-‘Unsolicited
Response’ for NID=01h are enabled.

Bit Description
31:0 0’s
8.37. Verb – Function Reset (Verb ID=7FFh)

Table 71. Verb – Function Reset (Verb ID=7FFh)
Command Format (NID=01H) Codec Response Format
CAd=X Node ID=01h Verb ID=7FFh 0’s 0’s
Codec Response
Bit Description
Note: The Function Reset command causes all widgets in the ALC887 to return to their power on default state.

ALC887
Datasheet
8.38. Verb – Get Digital Converter Control 1 & Control 2

(Verb ID= F0Dh, F0Eh)
Table 72. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)
CAd=X Node ID=Xh Verb ID=F0Dh/F0Eh 0’s Bit[31:16]=0’s, Bit[15:0] are SIC bit
NID=06h and 10h (1st and 2nd SPDIF-OUT) Response to ‘Get verb’ – F0Dh (Control 1 for SIC bit[15:0])
NID=06h and 10h (1st and 2nd SPDIF-OUT) Response to ‘Get verb’ – F0Eh (Control 2 for SIC bit[15:0])
Bit Description – SIC (SPDIF IEC Control) Bit[7:0]
31:16 Read as 0’s
15 Reserved. Read as 0’s
14:8 CC[6:0] (Category Code)
7 LEVEL (Generation Level)
6 PRO (Professional or Consumer Format)
0: Consumer format
1: Professional format
5 /AUDIO (Non-Audio Data Type)
0: PCM data
1: AC3 or other digital non-audio data
4 COPY (Copyright)
0: Asserted
1: Not asserted
3 PRE (Pre-Emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
2 VCFG for Validity Control (control V bit and data in Sub-Frame)
1 V for Validity Control (control V bit and data in Sub-Frame)
0 Digital Enable. DigEn
0: OFF
1: ON

ALC887
Datasheet
NID=0Ah (SPDIF-IN) Response to ‘Get verb (F0Dh)
NID=0Ah (SPDIF-IN) Response to ‘Get verb (F0Eh)
Bit Description (part of SPDIF-IN Channel Status)
0: Consumer format 1: Professional format
0: PCM data 1: AC3 or other digital non-audio data
4 COPY (Copyright)
0: Asserted 1: Not asserted
0: None 1: Filter pre-emphasis is 50/15 microseconds
2 Reserved
1 In‘V’alid. V Bit in Sub-Frame of SPDIF-IN
0: Data X and Y are valid, or SPDIF-IN is not locked
1: At least one of data X and Y is invalid
0: OFF
1: ON

Bit Description
31:0 0’s

ALC887
Datasheet
8.39. Verb – Set Digital Converter Control 1 & Control 2

(Verb ID=70Dh, 70Eh)
Table 73. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
Set Command Format (Verb ID=70Xh, Set Control 1) Codec Response Format
CAd=X Node ID=Xh Verb ID=70Dh SIC [7:0] 0’s
Set Command Format (Verb ID=70Yh, Set Control 2) Codec Response Format
CAd=X Node ID=Xh Verb ID=70Eh SIC [15:8] 0’s
‘Payload’ in Set Control 1 for NID=06h and 10h (1st and 2nd SPDIF-OUT)
0: Consumer format 1: Professional format
0: PCM data 1: AC3 or other digital non-audio data
4 COPY (Copyright)
0: Asserted 1: Not asserted
0: None 1: Filter pre-emphasis is 50/15 microseconds
2 VCFG for Validity Control (control V bit and data in Sub-Frame)
1 V for Validity Control (control V bit and data in Sub-Frame)
0: OFF 1: ON
‘Payload’ in Set Control 2 for NID=06h and 10h (1st and 2nd SPDIF-OUT)
‘Payload’ in Set Control 1 for NID=0Ah (SPDIF-IN)

7:1 Reserved
0: OFF 1: ON
‘Payload’ in Set Control 2 for NID=0Ah (SPDIF-IN)

Note: Other widgets will ignore this verb.

ALC887
Datasheet
8.40. Verb – Get Subsystem ID [31:0]

(Verb ID=F20h/F21h/D22h/F23h)
32-bit Read/Write register for Audio Function Group (NID=01h)
Table 74. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h)

CAd = X Node ID=01h Verb ID=F20h 0’s 32-bit Response
Codec Response for NID=01h

Bit Description
31:16 Subsystem ID[23:8]. (Default=10ECh)
15:8 Subsystem ID[7:0]. (Default=08h).
7:0 Assembly ID[7:0]. (Default=87h).
8.41. Verb – Set Subsystem ID [31:0] (Verb ID=723h/722h

/721h/720h for bytes 3,2,1,0)
Table 75. Verb – Set Subsystem ID [31:0] (Verb ID=723h/722h//721h/720h for bytes 3,2,1,0)
CAd = X Node ID=01h Verb ID=723h, Label [7:0] 0’s for all nodes
722h, 721h, 720h
Codec Response for all NID

Bit Description
31:0 0’s

ALC887
Datasheet
8.42. Get/Set EAPD Enable (VID=70Ch/F0Ch)

Table 76. Verb – Get/Set EAPD [31:0]
CAd = X Node ID=Xh Verb ID=F0Ch 0s Bit[1] is EAPD Control
CODEC response in Get Command for NID=14h (LINE-OUT Pin Widget), 15h (HP-OUT Pin Widget)
Bit Description
31:3 Reserved
2 L-R Swap
The ALC887 does not support swapping left and right channel, it is read as 0.
1 EAPD Enable
0: EAPD pin state is not controlled by power state of corresponding pin widget.
1: EAPD pin state is controlled by power state of corresponding pin widget.
0 BTL Enable
The ALC887 does not support BTL output, it is read as 0.
CODEC Response in Get Command for other NID

Bit Description
31:0 0’s.

CAd = X Node ID=Xh Verb ID=70Ch Bit[1] is EAPD Control 0s
CODEC Response in Set Command for all nodes

Bit Description
31:0 0’s.

ALC887
Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1. Absolute Maximum Ratings
Table 77. Absolute Maximum Ratings
Parameter Symbol Minimum Typical Maximum Units
Power Supply
Digital Power for Core DVDD 3.0 3.3 3.6 V
Digital Power for HDA Link DVDD-IO* 1.5 3.3 3.6 V
Analog AVDD** 4.5 5.0 5.5 V
o
Ambient Operating Temperature Ta 0 - +70 C
o
Storage Temperature Ts - - +125 C
ESD (Electrostatic Discharge)
Susceptibility Voltage
All Pins Pass 3500V
*: The digital link power DVDD-IO must be lower than the digital core power DVDD.
**: The standard testing condition before shipping is AVDD = 5.0V, the lowest operating AVDD is 4.5V.
9.1.2. Threshold Voltage

DVDD= 3.3V±5%, Tambient=25°C, with 50pF external load.
Table 78. Threshold Voltage

Input Voltage Range Vin -0.30 - DVDD+0.30 V
Low Level Input Voltage (HDA link) VIL - - 0.30*DVDDIO V
High Level Input Voltage (HDA link) VIH 0.65*DVDDIO - - V
Low Level Input Voltage VIL - - 0.44*DVDD V
(SPDIF-IN/OUT, GPIOs) (1.45)
High Level Input Voltage VIH 0.56*DVDD - - V
(SPDIF-IN/OUT, GPIOs) (1.85)
High Level Output Voltage VOH 0.9*DVDD - - V
Low Level Output Voltage VOL - - 0.1*DVDD V
Input Leakage Current - -10 - 10 µA
Output Leakage Current (Hi-Z) - -10 - 10 µA
Output Buffer Drive Current - - 5 - mA
Internal Pull Up Resistance - - 50k - Ω

ALC887
Datasheet
9.1.3. Digital Filter Characteristics

Table 79. Digital Filter Characteristics
Filter Description Minimum Typical Maximum Units
ADC Lowpass Filter Passband 0 - 0.4*Fs kHz
Stopband 0.60*Fs - - kHz
Stopband Rejection - -90 - dB
Passband Frequency Response - ±0.0005 - dB
DAC Lowpass Filter Passband 0 - 0.4*Fs kHz
Stopband 0.60*Fs - - kHz
Stopband Rejection - -90 - dB
Passband Frequency Response - ±0.0005 - dB
Note: Fs=Sample rate.
9.1.4. SPDIF Input/Output Characteristics

DVDD= 3.3V, Tambient=25°C, with 75Ω external load.
Table 80. SPDIF Input/Output Characteristics

SPDIF-OUT High Level Output VOH 3.0 3.3 - V
SPDIF-OUT Low Level Output VOL - 0 0.3 V
SPDIF-IN High Level Input VIH 1.85 - - V
SPDIF-IN Low Level Input VIL - - 1.45 V
SPDIF-IN Bias Level Vt - 1.65 - V

ALC887
Datasheet
9.2. AC Characteristic
9.2.1. Link Reset and Initialization Timing
Table 81. Link Reset and Initialization Timing
RESET# Active Low Pulse Width TRST 1.0 - - µs
RESET# Inactive to BCLK TPLL 20 - - µs
Startup Delay for PLL Ready Time
SDI Initialization Request TFRAME - - 1 Frame Time
Initialization
4 BCLK 4 BCLK >= 4 BCLK Sequence
BCLK
Normal Frame
SYNC SYNC
SDO
Initialization
SDI Request
RESET#
TRST
TPLL T FRAME
Figure 15. Link Reset and Initialization Timing

ALC887
Datasheet
9.2.2. Link Timing Parameters at the Codec

Table 82. Link Timing Parameters at the Codec
BCLK Frequency - - 24.0 - MHz
BCLK Period Tcycle - 41.67 - ns
BCLK Jitter Tjitter - - 2.0 ns
BCLK High Pulse Width Thigh 18.75 (45%) - 22.91 (55%) ns (%)
BCLK Low Pulse Width Tlow 18.75 (45%) - 22.91 (55%) ns (%)
SDO Setup Time at Both Rising and Tsetup 2.1 - - ns
Falling Edge of BCLK
SDO Hold Time at Both Rising and Thold 2.1 - - ns
Falling Edge of BCLK
SDI Valid Time After Rising Edge Ttco - 7.5 8.0 ns
of BCLK (1:50pF external load)
SDI Flight Time Tflight - 2.0 - ns
T_cycle
T_high
V IH
BCLK VT
V IL
T_low
T_setup T_hold
SDO
T_tco
VOH
SDI
VOL
T_flight
Figure 16. Link Signals Timing

ALC887
Datasheet
9.2.3. SPDIF Output and Input Timing

Table 83. SPDIF Output and Input Timing
SPDIF-OUT Frequency - - 3.072 - MHz
*1
SPDIF-OUT Period Tcycle - 325.6 - ns
SPDIF-OUT Jitter Tjitter - - 4 ns
SPDIF-OUT High Level Width THigh 156.2 (48%) 162.8 (50%) 169.2 (52%) ns (%)
SPDIF-OUT Low Level Width TLow 156.2 (48%) 162.8 (50%) 169.2 (52%) ns (%)
SPDIF-OUT Rising Time Trise - 2.0 - ns
SPDIF-OUT Falling Time Tfall - 2.0 - ns
*2
SPDIF-IN Period Tcycle - 325.6 - ns
SPDIF-IN Jitter Tjitter - - 10 ns
SPDIF-IN High Level Width THigh 146.4 (45%) 162.8 (50%) 179 (55%) ns (%)
SPDIF-IN Low Level Width TLow 146.4 (45%) 162.8 (50%) 179 (55%) ns (%)
*1: Bit parameters for 48kHz sample rate of SPDIF-OUT
*2: Bit parameters for 48kHz sample rate of SPDIF-IN
Tcycle
Thigh Tlow
VOH
VIH
Vt
VIL
V OL
Trise T fall
Figure 17. Output and Input Timing

ALC887
Datasheet
9.3. Analog Performance

Standard Test Conditions • Tambient=25 oC, DVDD=3.3V ±5%, AVDD=5.0V±5%
• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
• 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz
Table 84. Analog Performance
Parameter Min Typical Max Units
Full-Scale Input Voltage
All Inputs (gain=0dB) - 1.6 - Vrms
ADC - 1.4 - Vrms
Full-Scale Output Voltage
DAC - 1.2 - Vrms
Headphone Amplifier Output@32Ω Load - 1.2 - Vrms
S/N (A Weighted)
ADC - 90 - dB FSA
DAC - 97 - dB FSA
Headphone Amplifier Output@32Ω Load - 95 - dB FSA
THD+N
ADC - -85 - dB FS
DAC - -92 - dB FS
Headphone Amplifier Output@32Ω Load - -80 - dB FS
Frequency Response
ADC 10 - 0.45*Fs Hz
DAC 0 - 0.45*Fs Hz
Power Supply Rejection - -50 - dB
Total Out-of-Band Noise (28.8kHz~100kHz) - -60 - dB
Amplifier Gain Step - 1.5 - dB
Crosstalk Between Input Channels - -80 - dB
Input Impedance (gain=0dB) - 40 - KΩ
Output Impedance
Amplified Output - 2 - Ω
Non-amplified Output - 200 - Ω
Digital Power Supply Current (normal operation)
DVDD=3.3V - 40 - mA
Digital Power Supply Current (power down mode)
DVDD=3.3V - - 4 mA
Analog Power Supply Current (normal operation)
AVDD=5.0V - 60 - mA
Analog Power Supply Current (power down mode)
AVDD=5.0V - - 1 mA
VREFOUTx Output Voltage 2.25 2.50 3.75 V
VREFOUTx Output Current - 5 - mA
Note: Fs=Sample Rate.

ALC887
Datasheet
10. Application Circuits

ALC887 is fully pin compatible with the ALC888-VC (version C). To get the best compatibility in
hardware design and software driver, any modification should be confirmed by Realtek. Realtek may
update the latest application circuits onto our web site (www.realtek.com.tw) without modifying this
datasheet.
10.1. Filter Connection

If analog CD is connected as line level input
(9th port), and Jack Detect is required
R275 39.2K,1% MIC1-VREFO-R

CD-JD-Jack
LINE2-VREFO
MIC2-VREFO
LINE1-VREFO
SIDESURR-JD R237 5.1K,1% Sense B MIC1-VREFO-L
+5VA
CEN-JD R238 10K,1%
FRONT-L
FRONT-IO-SENSE R239 0 C229 10u C230
FRONT-R +
+
10u
If analog CD is connected as
U22
36
35
34
33
32
31
30
29
28
27
26
25
line level input(9th port)

AVSS1
AVDD1
VREF
Sense B
LINE2-VREFO
LINE1-VREFO
Sense C
FRONT-L
MIC1-VREFO-L
MIC2-VREFO
FRONT-R
MIC1-VREFO-R
+5VA R257 0 CD-R-Jack

37 24 LINE1-R
PIN37-VO LINE1-R R272 0
38 23 LINE1-L
AVDD2 LINE1-L R273 0 CD-L-Jack
SURR-L 39 22 MIC1-R
C238 + SURR-OUT-L MIC1-R
R240 20K,1% 40 21 MIC1-L
10u JDREF MIC1-L CD-IN Header
SURR-R 41 20 C243 1u
SURR-OUT-R CD-R 4
42 19 C244 1u 3
AVSS2 CD-GND 2
CEN 43 ALC887 18 C249 1u 1
CEN CD-L J23
LFE 44 17 MIC2-R
LFE MIC2-R
SIDESURR-L 45 16 MIC2-L If differential analog CD is used
SIDE-L MIC2-L
SIDESURR-R 46 15 LINE2-R
SIDE-R LINE2-R
GPIO1/DMIC-DATA
47 14 LINE2-L
GPIO0/DMIC-CLK
SPDIFI/EAPD LINE2-L
48 13 Sense A R241 5.1K,1% FRONT-JD
SDATA-OUT
SPDIFO Sense A
SDATA-IN
S/PDIF-IN
SPDIFO2
DVDD-IO
PCBEEP
LINE1-JD
RESET#
R242 10K,1%
BIT-CLK
DVSS2
DVDD
SYNC
R245 20K,1% MIC1-JD

Spilt by DGND
R246 39.2K,1% SURR-JD
1
10
11
12
S/PDIF-OUT
+3.3VD
R248 47K
C252 + C253 1u
Ext. PCBEEP
If secondary S/PDIF-OUT is 10u
connected to HDMI Tx connector R249
RESET#
R250 4.7k
22
R274 0
S/PDIF-OUT2 SYNC
SDIN
R254 22
JP9 BCLK
DMIC-CLK Tied at one point only under
4 DMIC-DATA C260
3 22P the codec or near the codec
2 +3.3VD
1
Pin 3 and pin 4 are
DMIC Interface compatible with with SDOUT
DGND AGND
ALC888S version B
If digital MIC interface
is adapted
Figure 18. Filter Connection

ALC887
Datasheet
10.2. Onboard Front Panel Header Connection

Option 1 in Figure 19 comes from by Intel’s front panel IO connectivity design guide. A drawback of this
option is that the ports connected to the front panel must use the same jack detection pin. According to the
HD Audio standard specification, ports A/B/C/D use ‘Sense A’ as the jack detect pin; ports E/F/G/H use
‘Sense B’ as the jack detect pin. This is not a good option when the system integrators want to use port-A
(pin 39/41) and port-F (pin 16/17) to be the front panel ports, as ‘Sense A’ and ‘Sense B’ cannot be tied
together. Option 2 in Figure 19 shows an alternative front panel header design that is also compatible
with standard front panel I/O cable. The option 2 header design lets the two ports use an individual sense
pin, and is compatible with current HD Audio front panel cable.
For the best compatibility with long front panel cable may not follow Intel’s Front Panel I/O Connectivity
standard, the option 2 header design has good ground loop is strongly recommended. The main drawback
of option 2 is not suitable for AC’97 front cable
Option 1: Follow Intel's HD Audio front panle header design

(Two ports must be in the same jack detect group)
MIC2-VREFO
D3 D4 HD Audio Front Panel I/O Cable

1N4148 1N4148
+3.3VD J2
FIO-PORT1-L
R11 R12 FIO-PORT1-R 1 2 FIO-PRESENCE#
FIO-PORT2-R 3 4 PORT1-SENSE -RETURN
4.7K 4.7K FIO-SENSE 5 6
7 8
KEY
R14 FIO-PORT2-L PORT2-SENSE -RETURN
MIC2-L C35 1u 9 10
10K CON10A
MIC2-R C37 1u J3
1 2 PRESENCE#
3 4 System GPI
LINE2-R C38 100u MIC2-JD
+
FRONT-IO-JD 5 6 Key FIO-SENSE

LINE2-L C39 100u 7 8 LINE2-JD
+
9 10
CON10A R18 JACK 7
Onboard front R19
PORT2-SENSE-RETURN 4
panel header 20K,1% 3
39.2K,1% FIO-PORT2-R L14 FERB
5
FIO-PORT2-L L15 FERB
2
1
C41 C42
Option 2: A more flexible front panel header FIO-PORT2 (Jack-E)
100P 100P
(Each port can be in different jack detect group)
MIC2-VREFO
D5 D6
1N4148 1N4148 FIO-SENSE

+3.3VD
R20 R21 JACK 8
4.7K 4.7K R23 PORT1-SENSE -RETURN 4

FIO-PORT1-R L16 FERB 3
MIC2-L C44 1u 10K 5
FIO-PORT1-L L17 FERB
MIC2-R C46 1u PRESENCE# 2
J5 System GPI 1
1 2 R25 C49 C50
3 4 20K,1%
LINE2-R C48 100u MIC2-JD FIO-PORT1 (Jack-F)
+
5 6 Key Sense B
100P 100P
LINE2-L C51 100u 7 8 LINE2-JD
+
9 10 Sense B
CON10A R26 39.2K,1%
Onboard front
panel header
Figure 19. Front Panel Header Connection

ALC887
Datasheet
10.3. Jack Connection on Rear Panel

MIC1-VREFO-L
MIC1-VREFO-R
R234 JACK 30
R235
4.7K JACK 31 SURR-JD
4.7K MIC1-JD 4
4 SURR-R C218 1u L69 FERB 3
MIC1-R C219 1u L70 FERB 3 5
5 SURR-L C220 1u L72 FERB
MIC1-L C221 1u L73 FERB 2
2 1
1 C222 C223
C224 C225 MIC-IN (Port-B) 2.2~4.7uF for DA (LF) SURROUND (Port-A)
100P 100P
100P 100P frequence response
JACK 32
JACK 33 CEN-JD
FRONT-JD 4
4 LFE C228 1u L74 FERB 3
FRONT-R C231 100u L75 FERB 3 5
+
5 CEN C232 1u L76 FERB

FRONT-L C233 100u L77 FERB 2
+
2 1
1 C234 C235
C236 C237 2.2~4.7uF for DA (LF) CENTER/LFE (Port-G)
FRONT-OUT (Port-D) 100P 100P
100P 100P frequence response
JACK 35
JACK 34
LINE1-JD SIDESURR-JD
4 4
LINE1-R C239 1u L78 FERB 3 SIDE-R C240 1u L79 FERB 3
5 5
LINE1-L C241 1u L80 FERB SIDE-L C242 1u L81 FERB
2 2
1 1
C245 C246 LINE-IN (Port-C) C247 C248
2.2~4.7uF for DA (LF) SIDESURR (Port-H)
100P 100P 100P 100P
frequence response
Figure 20. Jack Connection on Rear Panel
10.4. SPDIF Input/Output Connection

S/PDIF module option 1: Optical S/PDIF option 2: RCA only S/PDIF option 3: Optical & RCA
U2 3 TOTX178
Transmitter U2 4 TOTX178 U2 5 TORX178S
S/PDIF-OUT
C2 61 Transmitter Receiver
1 R2 58 100 S/PDIF-OUT
4 5 4 5 4 5
J26 0.01u
3
1
GND
GND
GND
VCC
VCC
VCC
OUT
C2 62 R2 59
IN
IN
RCA
100P 220 R2 60 10
2
S/PDIF-OUT
C2 63 C2 64 L86 47uH C2 65
0.1u 0.1u +5VD 0.1u
+5VD +5VD
+3.3VD
+3.3VD
U2 6 TORX178S
Receiver R2 61
S/PDIF-OUT R2 62
S/PDIF-IN 12K@ALC882;NC@ALC888/8 83 C2 66 S/PDIF-IN
1 R2 63 100 S/PDIF-OUT R 12K@ALC882;NC@ALC888/8 83
4 5 1 C2 67 0.01u R2 64 10 S/PDIF-IN
0.01u S C2 68 0.01u R2 65 10 S/PDIF-IN
3
1
GND
VCC
OUT
C2 69 R2 71 R2 66 C2 70 R2 67 J5A3
J28 75 J27 RCA C2 71 R2 70
R2 69 10 S/PDIF-IN RCA RCA 100P 220 R2 68
75
100P
10K@ALC882,NC@ALC883 100P
G
2
10K@ALC882,NC@ALC888/8 833
2
L87 47uH C2 72
0.1u
+5VD J5A is RCA jack with switch
Figure 21. SPDIF Input/Output Connection

ALC887
Datasheet
10.5. Secondary SPDIF-OUT Connected to HDMI Tx Connector

U3
RCA to HDMI Tx R69 100 C13
1
S/PDIF-OUT2
C31 R70 0.01u

200
100p
2
Figure 22. Secondary SPDIF-OUT Connected to HDMI Tx Connector
10.6. Differential Analog CD Used as Line Level Input

JACK 41
CD-JD-Jack
4
CD-R-Jack L98 FERB 3
5
CD-L-Jack L99 FERB
2
1
C294 C293
CD-IN (9th Port)
100P 100P
Figure 23. Differential Analog CD Used as Line Level Input

ALC887
Datasheet
11. Mechanical Dimensions
L1
SYMBOL MILLIMETER INCH

MIN TYP MAX MIN TYP MAX
A - - 1.60 - - 0.063
A1 0.05 - 0.15 0.002 - 0.006
TITLE: LQFP-48 (7.0x7.0x1.6mm)
A2 1.35 1.40 1.45 0.053 0.055 0.057
PACKAGE OUTLINE DRAWING,
c 0.09 - 0.20 0.004 - 0.008
FOOTPRINT 2.0mm
D 9.00 BSC 0.354 BSC
LEADFRAME MATERIAL
D1 7.00 BSC 0.276 BSC
APPROVE DOC. NO.
D2 5.50 0.217
VERSION 02
E 9.00 BSC 0.354 BSC
CHECK DWG NO. PKGC-065
E1 7.00BSC 0.276 BSC
DATE
E2 5.50 0.217
REALTEK SEMICONDUCTOR CORP.
b 0.17 0.20 0.27 0.007 0.008 0.011
e 0.50 BSC 0.0196 BSC
TH 0o 3.5o 7o 0o 3.5o 7o
L 0.45 0.60 0.75 0.018 0.0236 0.030
L1 - 1.00 - - 0.0393 -
ALC887
Datasheet
12. Ordering Information

Table 85. Ordering Information
Part Number Description Status
ALC887-GR LQFP-48 with ‘Green’ Package Production
Realtek Semiconductor Corp.

Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw


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ALC887

7.1 CHANNEL HIGH DEFINITION AUDIO CODEC

Realtek Semiconductor Corp.

USING THIS DOCUMENT

7.1 Channel High Definition Audio Codec w/Two ii Rev. 1.0

4. BLOCK DIAGRAM ...........................................................................................................................................................5

12. ORDERING INFORMATION .......................................................................................................................................74

7.1 Channel High Definition Audio Codec w/Two v Rev. 1.0

7.1 Channel High Definition Audio Codec w/Two vi Rev. 1.0

7.1 Channel High Definition Audio Codec w/Two 1 Rev. 1.0

2.2. Software Features

WaveRT based audio function driver for Windows Vista

Direct Sound 3D™ compatible

Emulation of 26 sound environments to enhance gaming experience

Multi bands of software equalizer and tool are provided

Voice Cancellation and Key Shifting effect

Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience

Provides 10-foot GUI for Windows Media Center

HDMI audio driver for AMD platform

Dolby® PCEE program™ (optional software feature)

DTS® CONNECT™ (optional software feature)

SRS® TrueSurround HD (optional software feature)

7.1 Channel High Definition Audio Codec w/Two 3 Rev. 1.0

7.1 Channel High Definition Audio Codec w/Two 4 Rev. 1.0

SideSurr CLfe 14h

7.1 Channel High Definition Audio Codec w/Two

SP-OUT DATA 10h

4.1. Analog Input/Output Unit

Figure 2. Analog Input/Output Unit

7.1 Channel High Definition Audio Codec w/Two 6 Rev. 1.0

Figure 3. ALC887 Pin Assignments

5.2. Green Package and Version Identification

7.1 Channel High Definition Audio Codec w/Two 7 Rev. 1.0

6.2. Analog I/O Pins

7.1 Channel High Definition Audio Codec w/Two 9 Rev. 1.0

7.1 Channel High Definition Audio Codec w/Two 10 Rev. 1.0

7. High Definition Audio Link Protocol

Previous Frame Tframe_sync = 20.833 盜 (48KHz)

Frame SYNC= 8 BCLK Stream 'A' Tag Stream 'B' Tag

SDO Command Stream Stream 'A' Data Stream 'B' Data

Figure 4. HDA Link Protocol

7.1 Channel High Definition Audio Codec w/Two 11 Rev. 1.0

7.1.1. Signal Definitions

Table 6. HDA Signal Definitions

SYNC 8-Bit Frame SYNC

SDI 3 2 1 0 499 498 497 496 495 494

Codec samples SDO at both rising and falling edge of BCLK

7.1 Channel High Definition Audio Codec w/Two 12 Rev. 1.0

7.1.2. Signaling Topology

Single SDO Two SDOs Single SDO Two SDOs

7.1 Channel High Definition Audio Codec w/Two 13 Rev. 1.0

7.2. Frame Composition

Frame SYNC Stream 'A' Tag Stream 'X' Tag

SDO Command Stream Stream 'A' Data Stream 'X' Data 0s

Null Field Padded at the

.. For 48kHz rate, only Block1 is included

msb ... lsb msb first in a sample

Figure 7. SDO Outbound Frame

Preamble Stream=10 Data of Stream 10

Figure 8. SDO Stream Tag is Indicated in SYNC