Data Sheet 4550 Timer

PIC18F2455/2550/4455/4550
11.0 TIMER0 MODULE The T0CON register (Register 11-1) controls all
aspects of the module’s operation, including the
The Timer0 module incorporates the following features: prescale selection. It is both readable and writable.
• Software selectable operation as a timer or coun- A simplified block diagram of the Timer0 module in 8-bit
ter in both 8-bit or 16-bit modes mode is shown in Figure 11-1. Figure 11-2 shows a
• Readable and writable registers simplified block diagram of the Timer0 module in 16-bit
• Dedicated 8-bit, software programmable mode.
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt on overflow
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMR0ON: Timer0 On/Off Control bit

1 = Enables Timer0
0 = Stops Timer0
bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 Prescale value
© 2009 Microchip Technology Inc. DS39632E-page 127

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11.1 Timer0 Operation internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
Timer0 can operate as either a timer or a counter; the timer/counter.
mode is selected by clearing the T0CS bit
(T0CON<5>). In Timer mode, the module increments 11.2 Timer0 Reads and Writes in
on every clock by default unless a different prescaler 16-Bit Mode
value is selected (see Section 11.3 “Prescaler”). If
the TMR0 register is written to, the increment is TMR0H is not the actual high byte of Timer0 in 16-bit
inhibited for the following two instruction cycles. The mode. It is actually a buffered version of the real high
user can work around this by writing an adjusted value byte of Timer0 which is not directly readable nor
to the TMR0 register. writable (refer to Figure 11-2). TMR0H is updated with
The Counter mode is selected by setting the T0CS bit the contents of the high byte of Timer0 during a read of
(= 1). In Counter mode, Timer0 increments either on TMR0L. This provides the ability to read all 16 bits of
every rising or falling edge of pin RA4/T0CKI/C1OUT/ Timer0 without having to verify that the read of the high
RCV. The incrementing edge is determined by the and low byte were valid, due to a rollover between
Timer0 Source Edge Select bit, T0SE (T0CON<4>); successive reads of the high and low byte.
clearing this bit selects the rising edge. Restrictions on Similarly, a write to the high byte of Timer0 must also
the external clock input are discussed below. take place through the TMR0H Buffer register. The high
An external clock source can be used to drive Timer0; byte is updated with the contents of TMR0H when a
however, it must meet certain requirements to ensure write occurs to TMR0L. This allows all 16 bits of Timer0
that the external clock can be synchronized with the to be updated at once.
FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4 0
1
Sync with Set
1 Internal TMR0L TMR0IF
Programmable Clocks on Overflow
T0CKI pin 0
Prescaler
T0SE (2 TCY Delay)
T0CS 8
3
T0PS2:T0PS0
8
PSA Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)
FOSC/4 0
1
Sync with Set
Internal TMR0
1 TMR0L High Byte TMR0IF
T0CKI pin Programmable 0 Clocks on Overflow
Prescaler 8
T0SE (2 TCY Delay)
T0CS 3 Read TMR0L
T0PS2:T0PS0
Write TMR0L
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
DS39632E-page 128 © 2009 Microchip Technology Inc.

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11.3 Prescaler 11.3.1 SWITCHING PRESCALER
ASSIGNMENT
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable; The prescaler assignment is fully under software
its value is set by the PSA and T0PS2:T0PS0 bits control and can be changed “on-the-fly” during program
(T0CON<3:0>) which determine the prescaler execution.
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the 11.4 Timer0 Interrupt
Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0
from 1:2 through 1:256, in power-of-2 increments, are register overflows from FFh to 00h in 8-bit mode, or
selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets
When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF clearing the TMR0IE bit (INTCON<5>). Before re-
TMR0, BSF TMR0,etc.) clear the prescaler count. enabling the interrupt, the TMR0IF bit must be cleared
in software by the Interrupt Service Routine.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0
count but will not change the prescaler interrupt cannot awaken the processor from Sleep.
assignment.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0

Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values
on page
TMR0L Timer0 Register Low Byte 54
TMR0H Timer0 Register High Byte 54
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 53
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 54
TRISA — TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56
Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.
Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled,
all of the associated bits read ‘0’.

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NOTES:

PIC18F2455/2550/4455/4550
12.0 TIMER1 MODULE A simplified block diagram of the Timer1 module is
shown in Figure 12-1. A block diagram of the module’s
The Timer1 timer/counter module incorporates these operation in Read/Write mode is shown in Figure 12-2.
features:
The module incorporates its own low-power oscillator
• Software selectable operation as a 16-bit timer or to provide an additional clocking option. The Timer1
counter oscillator can also be used as a low-power clock source
• Readable and writable 8-bit registers (TMR1H for the microcontroller in power-managed operation.
and TMR1L) Timer1 can also be used to provide Real-Time Clock
• Selectable clock source (internal or external) with (RTC) functionality to applications with only a minimal
device clock or Timer1 oscillator internal options addition of external components and code overhead.
• Interrupt on overflow Timer1 is controlled through the T1CON Control
• Module Reset on CCP Special Event Trigger register (Register 12-1). It also contains the Timer1
• Device clock status flag (T1RUN) Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).

R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
Legend:
bit 7 RD16: 16-Bit Read/Write Mode Enable bit

1 = Enables register read/write of Timer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 6 T1RUN: Timer1 System Clock Status bit
1 = Device clock is derived from Timer1 oscillator
0 = Device clock is derived from another source
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
bit 3 T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from RC0/T1OSO/T13CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1

PIC18F2455/2550/4455/4550
12.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
Timer1 can operate in one of these modes: or the Timer1 oscillator, if enabled.
• Timer When Timer1 is enabled, the RC1/T1OSI/UOE and
• Synchronous Counter RC0/T1OSO/T13CKI pins become inputs. This means
• Asynchronous Counter the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
FIGURE 12-1: TIMER1 BLOCK DIAGRAM

Timer1 Oscillator
On/Off 1
T1OSO/T13CKI 1
Prescaler Synchronize
FOSC/4 1, 2, 4, 8 Detect 0
Internal
Clock 0
T1OSI 2
Sleep Input
T1OSCEN(1) TMR1CS Timer1
On/Off
T1CKPS1:T1CKPS0
T1SYNC
TMR1ON
TMR1 Set
Clear TMR1 TMR1L TMR1IF
High Byte
(CCP Special Event Trigger) on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

Timer1 Oscillator
1
T1OSO/T13CKI 1
FOSC/4 1, 2, 4, 8 Detect 0
Internal
Clock 0
T1OSI 2
Sleep Input
T1CKPS1:T1CKPS0 On/Off
T1SYNC
TMR1ON
TMR1 Set
Clear TMR1 TMR1L TMR1IF
High Byte
(CCP Special Event Trigger) on Overflow
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus

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12.2 Timer1 16-Bit Read/Write Mode TABLE 12-1: CAPACITOR SELECTION FOR
THE TIMER OSCILLATOR(2,3,4)
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit Osc Type Freq C1 C2
(1)
(T1CON<7>) is set, the address for TMR1H is mapped LP 32 kHz 27 pF 27 pF(1)
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of Note 1: Microchip suggests these values as a
Timer1 into the Timer1 high byte buffer. This provides starting point in validating the oscillator
the user with the ability to accurately read all 16 bits of circuit.
Timer1 without having to determine whether a read of 2: Higher capacitance increases the stability
the high byte, followed by a read of the low byte, has of the oscillator but also increases the
become invalid due to a rollover between reads. start-up time.
A write to the high byte of Timer1 must also take place 3: Since each resonator/crystal has its own
through the TMR1H Buffer register. The Timer1 high characteristics, the user should consult
byte is updated with the contents of TMR1H when a the resonator/crystal manufacturer for
write occurs to TMR1L. This allows a user to write all appropriate values of external
16 bits to both the high and low bytes of Timer1 at once. components.
The high byte of Timer1 is not directly readable or 4: Capacitor values are for design guidance
writable in this mode. All reads and writes must take only.
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler. 12.3.1 USING TIMER1 AS A CLOCK
The prescaler is only cleared on writes to TMR1L. SOURCE
The Timer1 oscillator is also available as a clock source
12.3 Timer1 Oscillator in power-managed modes. By setting the clock select
An on-chip crystal oscillator circuit is incorporated bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device
between pins T1OSI (input) and T1OSO (amplifier switches to SEC_RUN mode. Both the CPU and
output). It is enabled by setting the Timer1 Oscillator peripherals are clocked from the Timer1 oscillator. If the
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a IDLEN bit (OSCCON<7>) is cleared and a SLEEP
low-power circuit rated for 32 kHz crystals. It will instruction is executed, the device enters SEC_IDLE
continue to run during all power-managed modes. The mode. Additional details are available in Section 3.0
circuit for a typical LP oscillator is shown in Figure 12-3. “Power-Managed Modes”.
Table 12-1 shows the capacitor selection for the Timer1 Whenever the Timer1 oscillator is providing the clock
oscillator. source, the Timer1 system clock status flag, T1RUN
The user must provide a software time delay to ensure (T1CON<6>), is set. This can be used to determine the
proper start-up of the Timer1 oscillator. controller’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
FIGURE 12-3: EXTERNAL Clock Monitor. If the Clock Monitor is enabled and the
Timer1 oscillator fails while providing the clock, polling
COMPONENTS FOR THE
the T1RUN bit will indicate whether the clock is being
TIMER1 LP OSCILLATOR
provided by the Timer1 oscillator or another source.
C1
PIC18FXXXX 12.3.2 LOW-POWER TIMER1 OPTION
27 pF
T1OSI
The Timer1 oscillator can operate at two distinct levels
of power consumption based on device configuration.
XTAL
When the LPT1OSC Configuration bit is set, the Timer1
32.768 kHz
oscillator operates in a low-power mode. When
LPT1OSC is not set, Timer1 operates at a higher power
T1OSO
level. Power consumption for a particular mode is rela-
C2
27 pF tively constant, regardless of the device’s operating
mode. The default Timer1 configuration is the higher
Note: See the notes with Table 12-1 for additional power mode.
information about capacitor selection.
As the low-power Timer1 mode tends to be more
sensitive to interference, high noise environments may
cause some oscillator instability. The low-power option
is, therefore, best suited for low noise applications
where power conservation is an important design
consideration.

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12.3.3 TIMER1 OSCILLATOR LAYOUT 12.5 Resetting Timer1 Using the CCP
CONSIDERATIONS Special Event Trigger
The Timer1 oscillator circuit draws very little power If either of the CCP modules is configured in Compare
during operation. Due to the low-power nature of the mode to generate a Special Event Trigger
oscillator, it may also be sensitive to rapidly changing (CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011),
signals in close proximity. this signal will reset Timer1. The trigger from CCP2 will
The oscillator circuit, shown in Figure 12-3, should be also start an A/D conversion if the A/D module is
located as close as possible to the microcontroller. enabled (see Section 15.3.4 “Special Event Trigger”
There should be no circuits passing within the oscillator for more information).
circuit boundaries other than VSS or VDD. The module must be configured as either a timer or a
If a high-speed circuit must be located near the oscilla- synchronous counter to take advantage of this feature.
tor (such as the CCP1 pin in Output Compare or PWM When used this way, the CCPRH:CCPRL register pair
mode, or the primary oscillator using the OSC2 pin), a effectively becomes a period register for Timer1.
grounded guard ring around the oscillator circuit, as If Timer1 is running in Asynchronous Counter mode,
shown in Figure 12-4, may be helpful when used on a this Reset operation may not work.
single-sided PCB or in addition to a ground plane.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
FIGURE 12-4: OSCILLATOR CIRCUIT precedence.
WITH GROUNDED
GUARD RING Note: The Special Event Triggers from the CCP2
module will not set the TMR1IF interrupt
VDD flag bit (PIR1<0>).
VSS
12.6 Using Timer1 as a Real-Time Clock
OSC1
Adding an external LP oscillator to Timer1 (such as the
OSC2 one described in Section 12.3 “Timer1 Oscillator”)
gives users the option to include RTC functionality to
their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
RC0 base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
RC1
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
RC2 device and battery backup.
The application code routine, RTCisr, shown in
Note: Not drawn to scale.
Example 12-1, demonstrates a simple method to
increment a counter at one-second intervals using an
12.4 Timer1 Interrupt Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
The TMR1 register pair (TMR1H:TMR1L) increments
the routine, which increments the seconds counter by
from 0000h to FFFFh and rolls over to 0000h. The
one. Additional counters for minutes and hours are
Timer1 interrupt, if enabled, is generated on overflow
incremented as the previous counter overflows.
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled Since the register pair is 16 bits wide, counting up to
by setting or clearing the Timer1 Interrupt Enable bit, overflow the register directly from a 32.768 kHz clock
TMR1IE (PIE1<0>). would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it. The simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.

PIC18F2455/2550/4455/4550
12.7 Considerations in Asynchronous following a later Timer1 increment. This can be done
Counter Mode by monitoring TMR1L within the interrupt routine until it
increments, and then updating the TMR1H:TMR1L reg-
Following a Timer1 interrupt and an update to the ister pair while the clock is low, or one-half of the period
TMR1 registers, the Timer1 module uses a falling edge of the clock source. Assuming that Timer1 is being
on its clock source to trigger the next register update on used as a Real-Time Clock, the clock source is a
the rising edge. If the update is completed after the 32.768 kHz crystal oscillator; in this case, one-half
clock input has fallen, the next rising edge will not be period of the clock is 15.25 μs.
counted.
The Real-Time Clock application code in Example 12-1
If the application can reliably update TMR1 before the shows a typical ISR for Timer1, as well as the optional
timer input goes low, no additional action is needed. code required if the update cannot be done reliably
Otherwise, an adjusted update can be performed within the required interval.
EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE

RTCinit
MOVLW 80h ; Preload TMR1 register pair
MOVWF TMR1H ; for 1 second overflow
CLRF TMR1L
MOVLW b’00001111’ ; Configure for external clock,
MOVWF T1CON ; Asynchronous operation, external oscillator
CLRF secs ; Initialize timekeeping registers
CLRF mins ;
MOVLW .12
MOVWF hours
BSF PIE1, TMR1IE ; Enable Timer1 interrupt
RETURN
RTCisr
; Insert the next 4 lines of code when TMR1
; can not be reliably updated before clock pulse goes low
BTFSC TMR1L,0 ; wait for TMR1L to become clear
BRA $-2 ; (may already be clear)
BTFSS TMR1L,0 ; wait for TMR1L to become set
BRA $-2 ; TMR1 has just incremented
; If TMR1 update can be completed before clock pulse goes low
; Start ISR here
BSF TMR1H, 7 ; Preload for 1 sec overflow
BCF PIR1, TMR1IF ; Clear interrupt flag
INCF secs, F ; Increment seconds
MOVLW .59 ; 60 seconds elapsed?
CPFSGT secs
RETURN ; No, done
CLRF secs ; Clear seconds
INCF mins, F ; Increment minutes
MOVLW .59 ; 60 minutes elapsed?
CPFSGT mins
RETURN ; No, done
CLRF mins ; clear minutes
INCF hours, F ; Increment hours
MOVLW .23 ; 24 hours elapsed?
CPFSGT hours
RETURN ; No, done
CLRF hours ; Reset hours
RETURN ; Done

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TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Reset
on page
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 (1)
SPPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
(1)
IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
TMR1H TImer1 Register High Byte 54
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.

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13.0 TIMER2 MODULE 13.1 Timer2 Operation
The Timer2 module timer incorporates the following In normal operation, TMR2 is incremented from 00h on
features: each clock (FOSC/4). A 2-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and divide-by-
• 8-bit Timer and Period registers (TMR2 and PR2,
16 prescale options. These are selected by the prescaler
respectively)
control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The
• Readable and writable (both registers) value of TMR2 is compared to that of the Period register,
• Software programmable prescaler (1:1, 1:4 and PR2, on each clock cycle. When the two values match,
1:16) the comparator generates a match signal as the timer
• Software programmable postscaler (1:1 through output. This signal also resets the value of TMR2 to 00h
1:16) on the next cycle and drives the output counter/post-
• Interrupt on TMR2 to PR2 match scaler (see Section 13.2 “Timer2 Interrupt”).
• Optional use as the shift clock for the MSSP The TMR2 and PR2 registers are both directly readable
module and writable. The TMR2 register is cleared on any
The module is controlled through the T2CON register device Reset, while the PR2 register initializes at FFh.
(Register 13-1) which enables or disables the timer and Both the prescaler and postscaler counters are cleared
configures the prescaler and postscaler. Timer2 can be on the following events:
shut off by clearing control bit, TMR2ON (T2CON<2>), • a write to the TMR2 register
to minimize power consumption. • a write to the T2CON register
A simplified block diagram of the module is shown in • any device Reset (Power-on Reset, MCLR Reset,
Figure 13-1. Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:
bit 7 Unimplemented: Read as ‘0’

bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
•
•
•
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16

PIC18F2455/2550/4455/4550
13.2 Timer2 Interrupt 13.3 TMR2 Output
Timer2 can also generate an optional device interrupt. The unscaled output of TMR2 is available primarily to
The Timer2 output signal (TMR2 to PR2 match) pro- the CCP modules, where it is used as a time base for
vides the input for the 4-bit output counter/postscaler. operations in PWM mode.
This counter generates the TMR2 match interrupt flag Timer2 can be optionally used as the shift clock source
which is latched in TMR2IF (PIR1<1>). The interrupt is for the MSSP module operating in SPI mode.
enabled by setting the TMR2 Match Interrupt Enable Additional information is provided in Section 19.0
bit, TMR2IE (PIE1<1>). “Master Synchronous Serial Port (MSSP) Module”.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
4 1:1 to 1:16
T2OUTPS3:T2OUTPS0 Set TMR2IF
Postscaler
2
T2CKPS1:T2CKPS0 TMR2 Output
(to PWM or MSSP)
TMR2/PR2
Reset Match
1:1, 1:4, 1:16
FOSC/4 TMR2 Comparator PR2
Prescaler
8 8
8
Internal Data Bus

Reset
on page
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
TMR2 Timer2 Register 54
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 54
PR2 Timer2 Period Register 54
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.

PIC18F2455/2550/4455/4550
14.0 TIMER3 MODULE A simplified block diagram of the Timer3 module is
shown in Figure 14-1. A block diagram of the module’s
The Timer3 module timer/counter incorporates these operation in Read/Write mode is shown in Figure 14-2.
features:
The Timer3 module is controlled through the T3CON
• Software selectable operation as a 16-bit timer or register (Register 14-1). It also selects the clock source
counter options for the CCP modules (see Section 15.1.1
• Readable and writable 8-bit registers (TMR3H “CCP Modules and Timer Resources” for more
and TMR3L) information).
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt on overflow
• Module Reset on CCP Special Event Trigger

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 7 bit 0
Legend:
bit 7 RD16: 16-Bit Read/Write Mode Enable bit

1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
bit 6, 3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the capture/compare clock source for both CCP modules
01 = Timer3 is the capture/compare clock source for CCP2;
Timer1 is the capture/compare clock source for CCP1
00 = Timer1 is the capture/compare clock source for both CCP modules
bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1 TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge)
0 = Internal clock (FOSC/4)
1 = Enables Timer3
0 = Stops Timer3

PIC18F2455/2550/4455/4550
14.1 Timer3 Operation cycle (FOSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
Timer3 can operate in one of three modes: or the Timer1 oscillator, if enabled.
• Timer As with Timer1, the RC1/T1OSI/UOE and RC0/
• Synchronous Counter T1OSO/T13CKI pins become inputs when the Timer1
• Asynchronous Counter oscillator is enabled. This means the values of
TRISC<1:0> are ignored and the pins are read as ‘0’.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction

Timer1 Oscillator Timer1 Clock Input
1
T1OSO/T13CKI 1
FOSC/4 1, 2, 4, 8 Detect 0
Internal
Clock 0
T1OSI 2
Sleep Input
On/Off
T3CKPS1:T3CKPS0
T3SYNC
TMR3ON
CCP1/CCP2 Special Event Trigger Clear TMR3 TMR3 Set

CCP1/CCP2 Select from T3CON<6,3> TMR3L High Byte TMR3IF
on Overflow
FIGURE 14-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

Timer1 Oscillator Timer1 Clock Input
1
T1OSO/T13CKI 1
FOSC/4 1, 2, 4, 8 Detect 0
Internal
Clock 0
T1OSI 2
Sleep Input
T3CKPS1:T3CKPS0 On/Off
T3SYNC
TMR3ON
CCP1/CCP2 Special Event Trigger Clear TMR3 TMR3 Set

CCP1/CCP2 Select from T3CON<6,3> TMR3L High Byte TMR3IF
on Overflow
8
Read TMR1L
Write TMR1L
8
8
TMR3H
8
8
Internal Data Bus

PIC18F2455/2550/4455/4550
14.2 Timer3 16-Bit Read/Write Mode 14.4 Timer3 Interrupt
Timer3 can be configured for 16-bit reads and writes The TMR3 register pair (TMR3H:TMR3L) increments
(see Figure 14-2). When the RD16 control bit from 0000h to FFFFh and overflows to 0000h. The
(T3CON<7>) is set, the address for TMR3H is mapped Timer3 interrupt, if enabled, is generated on overflow
to a buffer register for the high byte of Timer3. A read and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
from TMR3L will load the contents of the high byte of This interrupt can be enabled or disabled by setting or
Timer3 into the Timer3 high byte buffer. This provides clearing the Timer3 Interrupt Enable bit, TMR3IE
the user with the ability to accurately read all 16 bits of (PIE2<1>).
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, has 14.5 Resetting Timer3 Using the CCP
become invalid due to a rollover between reads. Special Event Trigger
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high If the CCP2 module is configured to generate a
byte is updated with the contents of TMR3H when a Special Event Trigger in Compare mode
write occurs to TMR3L. This allows a user to write all (CCP2M3:CCP2M0 = 1011), this signal will reset
16 bits to both the high and low bytes of Timer3 at once. Timer3. It will also start an A/D conversion if the A/D
module is enabled (see Section 15.3.4 “Special
The high byte of Timer3 is not directly readable or Event Trigger” for more information.).
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register. The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
Writes to TMR3H do not clear the Timer3 prescaler. When used this way, the CCPR2H:CCPR2L register
The prescaler is only cleared on writes to TMR3L. pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
14.3 Using the Timer1 Oscillator as the the Reset operation may not work.
Timer3 Clock Source
In the event that a write to Timer3 coincides with a
The Timer1 internal oscillator may be used as the clock Special Event Trigger from a CCP module, the write will
source for Timer3. The Timer1 oscillator is enabled by take precedence.
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Note: The Special Event Triggers from the CCP2
Timer3 clock source, the TMR3CS bit must also be set.
module will not set the TMR3IF interrupt
As previously noted, this also configures Timer3 to
flag bit (PIR2<1>).
increment on every rising edge of the oscillator source.
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.

Reset
on page
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56
TMR3H Timer3 Register High Byte 55
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 54
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 55

PIC18F2455/2550/4455/4550
NOTES:

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PIC18F2455/2550/4455/4550

REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER

bit 7 TMR0ON: Timer0 On/Off Control bit

© 2009 Microchip Technology Inc. DS39632E-page 127

FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)

FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)

DS39632E-page 128 © 2009 Microchip Technology Inc.

TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0

© 2009 Microchip Technology Inc. DS39632E-page 129

DS39632E-page 130 © 2009 Microchip Technology Inc.

REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER

bit 7 RD16: 16-Bit Read/Write Mode Enable bit

© 2009 Microchip Technology Inc. DS39632E-page 131

FIGURE 12-1: TIMER1 BLOCK DIAGRAM

FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

DS39632E-page 132 © 2009 Microchip Technology Inc.

© 2009 Microchip Technology Inc. DS39632E-page 133

DS39632E-page 134 © 2009 Microchip Technology Inc.

EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE

© 2009 Microchip Technology Inc. DS39632E-page 135

DS39632E-page 136 © 2009 Microchip Technology Inc.

REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER

bit 7 Unimplemented: Read as ‘0’

© 2009 Microchip Technology Inc. DS39632E-page 137

FIGURE 13-1: TIMER2 BLOCK DIAGRAM

TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

DS39632E-page 138 © 2009 Microchip Technology Inc.

REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER

bit 7 RD16: 16-Bit Read/Write Mode Enable bit

© 2009 Microchip Technology Inc. DS39632E-page 139

FIGURE 14-1: TIMER3 BLOCK DIAGRAM

CCP1/CCP2 Special Event Trigger Clear TMR3 TMR3 Set

FIGURE 14-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

CCP1/CCP2 Special Event Trigger Clear TMR3 TMR3 Set

DS39632E-page 140 © 2009 Microchip Technology Inc.

TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

© 2009 Microchip Technology Inc. DS39632E-page 141

DS39632E-page 142 © 2009 Microchip Technology Inc.

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