DL413/D

REV 1

Radio, RF
and Video
Applications

® MOTOROLA
 @ MOTOROLA

Radio, RF
and Video
Applications
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Motorola reserves the right to make changes without further notice to any products herein. MOlorola makes no warranty, representation or
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"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals", must be validated for each customer
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supersedes any earlier documentation relating to the products referred to herein. The information contained in this document is current at the date
of publication. /I may subsequenlly be updated, revised or withdrawn.

Includes literature available at June 1994

All trademarks recognized.

© MOTOROLA INC.
All Rights Reserved
First Edition DL413/D, 1991
DL413/D Rev. 1, 1994
Printed in Great Britain by Tavistock Press (Bedford) Ltd. 5000 9/94
2
 Preface

This compilation of Application Notes, Engineering Bulletins, Design Concepts,

etc. was originally published by the European Literature Centre of Motorola Ltd.
in Milton Keynes, England, and has subsequently gained worldwide acceptance.
Because of the worldwide popularity of the Application Manuals Series it is impor-
tant for the reade r to take note of the followi ng:
The various Application Notes, Engineering Bulletins, Design Concepts, etc.
which are included were developed at Design Centres strategically located
throughout the global community and many. were originally written to support a
local need. Whilst the basic concepts of each of the publications included may
have broad global applicability, specific Motorola semiconductor parts may be
referred to that are currently available for limited distribution in a specific region
and may only be supported by the country of origin of the document in which it
is referenced.
Also included in the series for completeness and historical significance are
documents that may no longer be available individually because obsolete
devices are referenced or perhaps, simply, the original document is out of print.
Such items are markep in the Table of Contents, Cross Reference, Abstracts and
on the first page of the document with the letters 'HI' to indicate that these
documents are included for Historical Information only.
All the Application Notes, Engineering Bulletins, Design Concepts, etc. are
included to enhance the user's knowledge and understanding of Motorola's
products. However, before attempting to design-in a device referenced in this
Series, the user should contact the local Motorola supplier or sales office to
confirm product availability and if application support is available.
Thank you.

3
Other books In this series Include:

OL40810 Rev. 1 8-bit MCU Applications Manllal

OL40910 Rev. 1 16132-bit Applications Manual
OL41010 Rev. 1 Power Applications Manual
OL41110Rev.1 Communications Applications
OL41210 Rev. 1 Industrial Control Applications
OL41410 FET Applications Manual

4
 Contents
page
Device Cross Reference ................................................................................................................................ 9
Abstracts of Applications Documents ....................................................................................................... 13
Applications Documents
AN438 300W, 88-108MHz Amplifier Using the TP1940 MOSFETs Push-Pull Transistor ................. 21
AN448 "FlOF" Teletext using M6805 Microcontrollers ....................................................................... 25
AN460 An RDS Decoder Using the MC68HC05EO ............................................................................ 61
AN463 68HC05KO Infra-Red Remote Control ................................................................................... 101
AN479 Universal Input Voltage Range Power Supply for High Resolution Monitors
with Multi-Sync Capability ..................................................................................................... 113
AN749 Broadband Transformers and Broadband Combining Techniques for RF ............. :.............. 125
AN756 Crystal Switching Methods for MC12060/MC12061 Oscillators ............................................ 135
AN790 Thermal Rating of RF Power Transistors .............................................................................. 139
AN879 Monomax: Application of the MC13001 Monochrome Television Integrated Circuit ............. 147
AN925 UHF Preamplifier Centers on Budget Dual-Gate GaAs FET ................................................. 159
AN932 Application of the MC1377 Colour Encoder .......................................................................... 165
AN1019 Decoding Using the TDA3330, with Emphasis on Cable In/Cable Out Operation ................ 177
AN1020 A High-Performance Video Amplifier for High Resolution CRT Applications ........................ 185
AN1021 A Hybrid Video Amplifier for High Resolution CRT Applications ........................................... 189
AN1022 Mechanical and Thermal Considerations in Using RF Linear Hybrid Amplifiers ................... 193
AN1025 Reliability Considerations in Design and Use of RF Integrated Circuits ............................... 197
AN1027 Reliability/Performance Aspects of CATV Amplifier Design .................................................. 205
AN1028 35/50 Watt Broadband (160-240MHz) Push-Pull TV Amplifier Band 111 ................................ 213
AN1029 TV Transposers Band IV and V Po = 0.5W/l.0W ................................................................. 221
AN1030 1W/2W Broadband TV Amplifier Band IV and V ................................................................... 229
AN1032 How load VSWR Affects Non-Linear Circuits ....................................................................... 237
AN1033 Match Impedances in Microwave Amplifiers ......................................................................... 241
AN1034 Three Balun Designs for Push-Pull Amplifiers ...................................................................... 247
AN1037 Solid State Power Amplifier, 300W FM, 88-1 08MHz ............................................................. 253
AN1039 470-860 MHz Broadband Amplifier 5W ................................................................................. 257
AN1040 Mounting Considerations for Power Semiconductors ........................................................... 263
AN1041 Mounting Procedures for Very High Power RF Transistors .................................................. 283
AN1044 The MC1378 - A Monolithic Composite Video Synchronizer .............................................. 285
AN1047 Electrical Characteristics of the CR2424 and CR2425 CRT Driver Hybrid Amplifiers .......... 299
AN1061 Reflecting on Transmission Line Effects ............................................................................... 303
AN1080 External-Sync Power Supply with Universal Input Voltage Range for Monitors ................... 315
AN1092 Driving High Capacitance DRAMs in an ECl System ........................................................... 335
AN1106 Considerations in Using the MHW801 and MHW851 Series RF Power Modules ................ 339
AN1107 Understanding RF Data Sheet Parameters .......................................................................... 343
AN1122 Running the MC44802A Pll Circuit ..................................................................................... 359
AN1207 The MC145170 in Basic HF and VHF Oscillators ................................................................. 371
AN1306 Thermal Distortion in Video Amplifiers .................................................................................. 377
AN1401 Using SPICE to Analyze the Effects of Board layout on System Skew when
Designing with the MCI 0/1 00H640 Family of Clock Drivers ................................................. 383
AN1402 MCI 0/1 OOHoo Translator Family I/O SPICE Modelling Kit ................................................... 395
AN1404 ECLinPS Circuit Performance at Non-Standard VIH Levels ................................................. 411
AN1405 ECl Clock Distribution Techniques ....................................................................................... 419

5
 Contents (continued)

EB27A Get 300 Watts PEP Linear Across 2 to 30MHz from this Push-Pull Amplifier ...................... 427
EB29 The Common Emitter TO-39 and its Advantages ................................................................. 431
EB59 Predict Frequency Accuracy for MC12060 and MC12061 Crystal Oscillator Circuits ........... 433
EB77 A 60 Watt 225-400MHz Amplifier - 2N6439 ......................................................................... 437
EB89 A 1 Watt, 2.3GHz Amplifier ................................................................................................... 441
EB90 Low-Cost VHF Amplifier Has Broadband Performance ........................................................ 445
EB93 60 Watt VHF Amplifier Uses Splitting/Combining Techniques .......... , ................................... 451
EB107 Mounting Considerations for Motorola RF Power Modules ................................................... 457
EB411 A Dighal Video Prototyping System ....................................................................................... 461
Additional Information ............................................................................................................................... 471

6
Device Cross
Reference

7
8
 Device Cross Reference
This quick-reference list indicates where specific
components are featured in applications documents
reproduced in this Manual.

2N6439 ...................................... EB77 MC44250 ................................... EB411

CA2820 ..................................... AN1022 MC44602P2 .............................. AN479
CR2424 ..................................... AN1021 MC44802A ................................ AN1122
............................................ AN1047 MC145170 ................................. AN1207
............................................ AN1306 MHW612 ................................... EB107
CR2425 ..................................... AN1021 MHW613 ................................... EB107
............................................ AN1047 MHW709 ................................... EB107
LT1 001 ...................................... AN1 020 MHW710 ................................... EB107
LT1817 ...................................... AN1020 MHW720 ................................... EB107
LT1829 ...................................... AN1020 MHW801 ................................... AN1106
LT5839 ...................................... AN1020 MHW808 ................................... EB107
MC10E111 ................................ AN1405 MHW820 ................................... EB107
MC10E211 ................................ AN1405 MHW851 ................................... AN1106
MC10H60x ................................ AN1402 MJE18004 ................................. AN1080
MC10H641 ................................ AN1405 MJH18010 ................................. AN479
MC10H64X ................................ AN1401 MOC81 02 .................................. AN1 080
MC10H660 ................................ AN1092 MRF141G .................................. AN1041
MC68HC05B6 ........................... EB411 MRF151G .................................. AN1041
MC68HC05EO ........................... AN460 MRF153 .................................... AN1041
MC68HC05KO ........................... AN463 MRF154 .................................... AN1041
MC68HC05T7 ........................... AN448 MRF155 .................................... AN1041
MC68HC11E9 ........................... AN1122 MRF175G .................................. AN1041
MC100E111 .............................. AN1405 MRF176G .................................. AN1041
MC100E211 .............................. AN1405 MRF227 .................................... EB29
MC100H60x .............................. AN1402 MRF260 .................................... EB90
MC100H641 .............................. AN1405 MRF262 .................................... EB90
MC100H64x .............................. AN1401 MRF264 .................................... EB93
MC100H660 .............................. AN1092 MRF422 .................................... EB27A
MC1377 ..................................... AN932 MRF430 .................................... AN1041
............................................ AN1044 MRF966 .................................... AN925
MC1378 ..................................... AN1044 MRF2001 .................................. EB89
MC1658 ..................................... AN1207 MTP4N90 .................................. AN1 080
MC1723 ..................................... EB27A TDA3301 ................................... AN1044
M C3423 ..................................... AN 1080 TDA3330 ................................... AN1019
MC12060 ................................... AN756 TP 1940 ...................................... AN438
............................................ EB59 TP9383 ...................................... AN 1037
MC12061 ................................... AN756 TPV375 ..................................... AN1 028
............................................ EB59 TPV593 ..................................... AN1 039
MC13001 ................................... AN879 TPV596 ..................................... AN1029
MC14576 ................................... EB411 TPV597 ..................................... AN1 030
MC44011 ................................... EB411 UC3842A ................................... AN1 080
MC44200 ................................... EB411 UC3843A ................................... AN1080

9
10
Abstracts of
Applications
Documents

11
12
 ----.,-:------..,-~~I

Abstracts
AN438 300W, 88-108MHz Amplifier Using the interference on a mUlti-sync colour monitor. It uses a
TP1940 MOSFETs Push-Pull Transistor low cost MC44602P2 current mode controller-designed
Provides the design of an efficient 300W amplifier with specifically for driving high voltage bipolar transistors-
with an MJH1801 0 switch mode power transistor.
high power gain, compact physical layout and opera-
tion on a 50V power supply. It uses the TPt 940, a high
AN749 Broadband Transformers and
power, high gain, broadband push-pull Power MOS-
FET with low Reverse Transfer Capacitance. Includes
Broadband Combining Techniques for RF
circuit, parts list, PCB artwork and component layout. This application note provides a number of practical
examples of broadband transformers for RF applica-
AN448 "FLOF" Teletext using M6805 tions. It includes detailed design formulae and perfor-
Microcontrollers mance data, and discusses power combining techniques
The "-1" members of Motorola's M68HC05 MCU family that are useful in designing high power RF amplifiers.
provide a cost-effective method of adding On Screen
AN756 Crystal Switching Methods for MC12060/
Display (OSD) to TVs and VCRs. This note describes
MC12061 Oscillators
an example of Full Level One Feature (FLOF) Teletext
control software written forthe MC68HC05T7tocontroi This report discusses methods of using diodes to select
type 5243 Teletext chips. Around 3K bytes of ROM are series resonant crystals electronically. Circuit designs
used, allowing the code to fit with tuning, OSD and suitable for use with crystal frequencies from 100kHz to
stereo functions into the 7.9Kbytesofthe MC68HC05T7. 20MHz are developed, with emphasis on minimizing
The example software includes the Spanish implemen- frequency pulling. Although developed for use with the
tation of Packet 26; Packet 26 allows for the substitu- MC12060 and MC 12061 integrated circuit crystal oscil-
tion of specific characters for a particular country. lators, the techniques will generally be useful in any
application where it is necessary to select electronically
AN460 An RDS Decoder Using the one of a group of crystals with minimum disturbance to
MC68HC05EO the series resonant frequency of the selected crystal.
The Radio Data System (RDS) adds digital data capa-
AN790 Thermal Rating of RF Power Transistors
bility to VHF FM transmissions on band II (87.5 to
t 08MHz). The system is in use in the UK and in several Reliability is of primary concern to most transistor
other European countries, and it is intended that it will users. The degree of reliability achieved in practice is
be adopted eventually by most of Western Europe; it is controlled by the device user because he determines
defined by EBU Technical Document 3244. Informa- environmental conditions and the stress levels applied.
tion is transmitted in groups of four 26-bit blocks on a Knowledge of the basic physical properties of the
supressed 57kHz sub-carrier. This note describes an materials, and the methods used to calculate thermal
MC68HC05EO-based clocklradio application; it includes resistance, will assist the user in transistor selection
a complete software listing. and equipment design. This note clarifies and corrects
some long-standing industry-wide assumptions about
AN463 68HC05KO Infra-Red Remote Control thermal resistance and high temperature derating.
In addition to the same CPU and registers as other
members of the M68HC05 family the MC68HC05KO
AN879 Monomax: Application of the MC13001
has a 15-stage multi-function timer and 10 bidirectional Monochrome Television Integrated Circuit
1/0 lines. A mask option is available for software pro- This application note presents a complete 12" black
gram mabie pull-downs on all the 1/0 pins; 4 of the pins and white line-operated television receiver including
are capable of generating interrupts. It is ideally suited artwork for the printed circuit board. It is intended to
for remote-control keyboard applications because the provide a good starting point for the first-time user.
pull-downs and the interrupt drivers on the port pins Some of the most common pitfalls are overcome and
allow keyboards to be built without any external compo- the significance of component selections and locations
nents except the keys themselves. This application are discussed.
makes use of many of the on-chip features to control a
TV infra-red remote control. AN925 UHF Preamplifier Centers on Budget
Dual-Gate GaAs FET
AN479 Universal Input Voltage Range Power The signal-to-noise ratio of a communications system
Supply for High Resolution Monitors with can be improved by increasing the power of the trans-
Multi-Sync Capability mitter, increasing the gain of the antenna, or improving
This note describes an easy-to-build, high performance, the sensitivity of the receiver. A low-noise preamplifier
low cost 1OOW flyback power supply, able to work on is an economical solution for receiver enhancement
any mains supply from 85Vac to 265Vac, and from and this note describes the design, construction and
40Hz to 100Hz. It is automatically synchronised to the performance of a 400-512MHz preamplifier using Mo-
horizontal scanning frequency for minimum screen torola's dual-gate GaAs FET.

13
 Abstracts (continued)

AN932 Application of the MC1377 Colour AN1025 Reliability Considerations In Design

Encoder and Use of RF Integrated Circuits
The MC1377 is and economical, high quality, RGB RF integrated circuits -located at strategic points in a
encoderfor NTSC or PAL applications. It accepts RGB CATV system - feature prominently in the overall
and composite sync inputs, and delivers a 1V p-p reliability assessment. Low noise and distortion require
composite NTSC or PAL video output into a 750 load. state-of-the-art transistor structures. Gold metallization,
It can provide its own colour oscillator and burst gating, thermal equilibrium and automated process control
or it can easily be driven from external sources. Per- have resulted in transistor lifetimes of over 100 years.
formance virtually equal to high-cost studio equipment An overview of the physics of construction involved with
is possible with common colour receiver components. the die and interconnects is discussed, together with a
definition of major reliability terms and an introduction
AN1019 Decoding Using the TDA3330, with to hardware and software microcircuit reliability tools.
Emphasis on Cable In/Cable Out Operation
The TDA3330 is a Composite Video to RGB Colour AN1027 Reliability/Performance Aspects of
Decoder originally intended for PAL and NTSC colour CA TV Amplifier DesIgn
TV receivers and monitors - so its data sheet concen- Discusses the reliability advantages offered by the RF
trates on picture tube drive. This practical application hybrid amplifier used in CATV applications. The active
note supplements the data sheet by providing circuits part of the hybrid is the transistor - metallization,
for video cable drive as used in video processing, frame ballasting and ruggedness are reliability-related factors
store and other specialized applications, and expands that must be considered by the device engineer when
on TDA3330 functional details. Includes PCB artwork designing a high performance CATV transistor. Vertical
and layout of an evaluation board. and horizontal geometry and device distortion are per:
formance-related factors that must also be taken into
AN1020 A High-Performance Video Amplifier for account. The relationship between these factors is
High Resolution CRT Applications examined, and life test data is presented to illustrate the
This note describes a state-of-the-art video amplifier advantages gained by careful device design.
making use of the superior performance characteristics
of Motorola CRT driver transistors. In particular, it AN1028 35/50 Watt Broadband (160-240MHzj
shows the high speed obtainable with low DC power Push-Pull TV Amplifier Band 11/
consumption. The circuit is insensitive to load varia- The main design aim for this broadband ultra-linear
tions and interconnect methods. push-pull amplifier was to keep the design as simple as
possible, in order to obtain the best performance from
AN1021 A Hybrid VIdeo Amplifier for High the two TPV375 transistors and to minimise the cost. A
Resolution CRT Applications further target was to obtain the maximum gain by
Many of the 1024 x 1024 and 1280 x 1024 pixe I, 64kHz reducing input matching circuit losses. Includes circuit,
horizontal sweep rate CRTs used in CAD/CAM and background description, Smith charts and PCB layout.
high resolution graphics applications have not realized
their potential performance because of the speed of AN1029 TV Transposers Band IV and V
their video amplifiers. The CR2424 and CR2425 video Po = 0.5W/1.0W
amplifiers are hybrid circuits designed for high resolu- Describes the performance of a470-860MHz broadband
tion CRT applications. Theyfeature less than 2.9ns rise ultra linear amplifier designed for use in band IV and V
and fall time for a 40V output swing, and provide a low TV transposers. The design is based on the TPV596,
power dissipation solution to the problem. and is intended to be as inexpensive and straightfor·
ward as possible: the load line is defined to provide the
AN1022 Mechanical and Thermal Considerations correct match for peak power; VSWR at the collector is
In USing RF Linear Hybrid Amplifiers less than 2:1; input matching is designed to provide flat
Motorola's thin film hybrid amplifiers are medium power gain with decreasing frequency; and the design is
(0.2W to 2.0W power output) broadband devices (1 to optimized with a CAD program.
1OOOMHz) that are biased in a class A mode for linear
operation. To ensure a proper electrical and mechani- AN1030 1W/2W Broadband TV Amplifier
cal interface with adequate RF and thermal character- BandlVand V
istics, certain guidelines are presented here so that the Describes thedesign and performance of a 470-860MHz
design engineer can obtain maximum electrical per- broadband linear amplifier for use in band IV and V TV
formance and the longest operating life. transposers, based on a TPV597 transistor. The de-
sign uses a reflection technique to achieve an insertion
loss of 6dB per octave with OdB for the highest fre-
quency. Two amplifiers are connected together with

14
 Abstracts (continued)

3dB quadrature hybrids to create a balanced amplifier a pair of TP9383 transistors in push-pull configuration;
avoiding the inconvenience of needing a good match of TP9383 is a double-diffused silicon epitaxial transistor
reflected power. using gold metallization and diffused ballast resistors
for long operating life and ruggedness.
AN1032 How Load VSWR Affects Non-Linear
Circuits AN1039 470-860 MHz Broadband Amplifier 5W
If your amplifiers pass lab tests but fail QC testing, the This note describes an ultra linear broadband (470-
testing environment - not the product - is most likely at 860M Hz) amplifier developed for TV transposer appli-
fault! Often the culprit is correlation oltest systems - RF cations. The amplifier incorporates two TPV593 tran-
Correlation occurs only when target error limits are sistors. Each transistor is used to build a separate
adhered to on a continuous basis among two or more broadband amplifier which are combined with 3dB
testing stations. Such correlation is essential for non- hybrids. Includes circu it, parts list and PCB layout.
linear RF and microwave power amplifiers, whose
circuits are extremely sensitive to the impedance of AN1040 Mounting Considerations for Power
their loads. It is easy to compensate for the insertion Semiconductors
loss errors in an attenuator, but much more difficult to The operating environment is a vital factor in setting
compensate for load VSWR. current and power ratings of a semicond uctor device.
Reliability is increased considerably for relatively small
AN1033 Match Impedances in Microwave reductions in junction temperature. Faulty mounting
Amplifiers not only increases the thermal gradient between the
The key to successful solid-state microwave power- device and its heat sink, but can also cause mechanical
amplifier design is impedance matching. In any high- damage. This comprehensive note shows correct and
frequency power-amplifier design, improper imped- incorrect methods of mounting all types of discrete
ance matching will degrade stability and reduce circuit packages, and discusses methods of thermal system
efficiency. At microwave frequencies, this considera- evaluation.
tion is even more critical, since the transistor's bond-
wire inductance and base-to-collector capacitance be- AN1041 Mounting Procedures for Very High
come significant elements in input/output impedance Power RF Transistors
network design. Includes table of characteristic imped- High power (200-600W) RF semiconductors such as
ance and velocity factor for various width/height ratios the MRFI53 ... and MRFI41G ... series dissipate an
and various materials. abnormally large amount of heat within a small physical
area. Heat sink material, surface finish, mounting
AN1034 Three Balun Designs for Push-Pull screws, washers and screw torque are extremely im-
Amplifiers portantfactors in ensuring reliability. This note explains
Single RF power transistors seldom satisfy today's why.
design criteria; several devices must be coupled to
obtain the required amplifier output power. The push- AN1044 The MC1378 - A Monolithic Composite
pull technique is often chosen because it allows input Video Synchronizer
and output impedances to be connected in series for The MC1378 provides an interface between a remote
RF operation. Balun-transformers provide the key to composite colour video source and local RGB. On-chip
push-pull design. This note develops three balun-trans- circuitry can lock a local computerto the remote source,
formers, culminating with a microstrip version. None of switching between local and remote signals to gener-
the baluns was tuned nor were the parasitic elements ate composite video overlays. This detailed note de-
compensated. In this way, their deviation from their scribes local and remote operation, picture-in-picture
theoretical performance could be evaluated more eas- applications and the design of test fixtures to help
ily. system development. Printed circuit artwork for an
evaluation board is provided. The NTSC/PAL colour
AN1037 Solid State Power Amplifier, encoder is similar to the MCI377, discussed in detail in
300W FM, 88-108MHz AN932.
A solid state power amplifier in a high efficiency FM
transmitter can be made by operating a number of AN1047 Electrical Characteristics of the CR2424
building block amplifiers in parallel. This note describes and CR2425 CRT Driver Hybrid Amplifiers
such a building block amplifier with high output power, Describes the circuit and thermal characteristics of the
high gain, good collector efficiency and broadband (88- CR2424 and CR2425 CRT driver hybrid amplifiers, and
108 MHz) frequency response. The design is simple, discusses three different methods of protecting against
reproducible and reliable, and is suitable for several damage by a tube arc. Provides details of bandwidth
architectures. The amplifier has been developed using and rise and fall times.

15
 ,'! r

Abstracts (continued)

AN1061 Reflecting on Transmission Line Effects AN1122 Running the MC44B02A PLL Circuit
In recent years, microprocessors and digital logic have The MC44802A provides the Phase locked loop (Pll)
seen substantial increases in line drive capability. The portion of a tuning circuit intended for TV, FM radio and
fast rise and fall times of modern devices make an set-top converter applications up to 1.3GHz; a com-
understanding of trans mission lines and their effects on plete tuning circuit is formed by adding a Voltage
system reliability a necessity. Includes a procedure for Controlled Oscillator (VCO) and mixer. The data sheet
assessing possible transmission line problems in prac- recommends use of an MCU for sending the control
tical designs. bytes that set the tuning frequency. This note describes
a serial (IIC) interface with an MC68HC11 E9 in a tuner
AN10BO External-Sync Power Supply with design - the information is sufficiently general to allow
Universal Input Voltage Range for Monitors almost any MCU to be used. Includes M68HC11 pro-
As the resolution of colour monitors increases, the gram listing.
performance and features of their power supplies be-
comes more critical. EMI/RFI generated by switching AN1207 The MC145170 in Basic HF and VHF
power supplies can adversely affect resolution if switch- Oscillators
ing frequency is not synchronised to horizontal scan- Frequency synthesisers such as the MC145170 use
ning frequency. This 90W flyback switching supply digital dividers which are typically under MCU control.
demonstrates the use of new high-performance de- Tuning in less than a millisecond can be achieved, and
vices in a low-cost design, and includes a new universal the device can generate many frequencies from a
input voltage adapter. single reference source; the overall frequency capability
ranges from afew Hertzto 160MHz. Typical applications
AN1092 Driving High Capacitance DRAMs in an include the carrier oscillator in transmitters, locaf
ECL System oscillator in receivers, cellular phones, and multiple
In systems where speed and efficiency are of utmost synchronised clocks in computers and other systems.
importance, designers often mix technologies to achieve
the right combination of speed, power, cost and process- AN1306 Thermal Distortion in Video Amplifiers
ing capability. Motorola's Emitter Coupled logic (ECl) Thermal distortion is a problem in many high resolution
makes it possible to operate up to 1GHz clock rates. video amplifiers. It occurs when there are instantane-
However, ECl speeds are not necessary in memory ous power changes in the transistor stages, and if the
that is not accessed every clock cycle - a large CMOS problem remains uncompensated it leads to the visual
DRAM is cheaper and uses less power and board effect known as smearing. This note discusses what
space than ECl memory. The MC1 OH/1 OOH660 4-bit smearing is, what causes thermal distortion, how to
ECl-TTL Load Reducing DRAM Driver was designed measure it, and how to compensate for it.
as a translator for such applications.
AN1401 Using SPICE to Analyze the Effects
AN1106 Considerations in Using the MHWB01 of Board Layout on System Skew when
and MHWB51 Series RF Power Modules Designing with the MC101100H640 Family
The MHW801 and MHW851 series of power modules of Clock Drivers
are designed for use in cellular portable radios. A Illustrates the complex influences of board layout on
considerable amount of applications information is in- the total skew of a system when designing with the
cluded in the data sheet; this note provides additional MC1 OH/1 OOH64x family of clock drivers. Discusses
information concerning general electrical considera- transmission line theory and the various termination
tions, noise characteristics, gain control, circuit consid- techniques, and presents guidelines to assist design-
erations and mounting. ers in analyzing board layouts and loading schemes
using SPICE simulations to predict and minimise the
AN1107 Understanding RF Data Sheet total skew of a system.
Parameters
The data sheet is often the only source of information AN1402 MC101100HOO Translator Family 110
about the characteristics and capability of a product. SPICE Modelling Kit
This is especially true of RF devices, which have many The difficulties of designing high-speed, controlled-
unique specifications. It is therefore important that the impedance PC boards - and the expense of reworking
manufacturer and designer speak acommon language. them - makes it essential for designers to model circuit
This paper reviews the significance of the quoted performance prior to committing to a layout. This note
values and highlights critical characteristics. Descrip- provides sufficient information for basic SPICE analy-
tions cover the procedures used to obtain impedance sis on the interconnect traces driving or being driven by
and thermal data, the importance of test circuits, low the 'H600, 'H601, 'H602, 'H603, 'H604, 'H605, 'H606
noise considerations and linearity requirements. and 'H607 translator chips. It includes schematics of
the input, output and ESD structures, and package

16
 Abstracts (continued)

models which may affect the waveforms. A SPICE ICs, temperature and DC supply voltage to help the
parameter set for the referenced devices is provided. designer to predict the amount of frequency pull in a
particular design.
AN1404 ECLinPS Circuit Performance at Non-
Standard VIH Levels EB77 A 60 Watt 22S-400MHz Amplifier-
When ECLinPS devices are interfaced to other tech- 2N6439
nologies there may be times when the input voltages do This bulletin describes a 60 watt, 28 volt broadband
not meet the specification detailed in the ECLinPS data amplifier covering the 225-400 MHz military communi-
book. This application note discusses the conse- cations band. The amplifier may be used singly as a 60
quences of driving ECLinPS devices with an Input watt output stage in a 225-400 MHz transmitter; by
Voltage HIGH level which is outside the specification. using two of these amplifiers combined with quadrature
couplers a 100 watt output amplifier stage may be
AN140S ECL Clock Distribution Techniques constructed. The circuit is designed to be driven from a
Clock skew - the time difference between supposedly 50 ohm source and work into a nominal 50 ohm load.
simultaneous clock transitions within a system - is one
of the main factors limiting system performance at high EB89 A 1 Watt, 2_3GHz Amplifier
frequencies. If clock skew can be reduced, designers This S-band amplifier features simplicity and
can increase performance without using faster logic or repeatability, delivering 8dB minimum gain at 1 watt
more complex and more expensive architectures. output on a 24V supply. It uses an MRF2001 transistor
Emitter Coupled Logic (ECL) technologies offer a in a common base, class C configuration, and is tunable
number of advantages over the CMOS and TTL alter- from 2.25 to 2.35GHz. Applications include micowave
natives; this note describes the advantages, the three communications and other systems requiring medium
skew problem areas, and methods of clock distribution power, narrow band amplification. The Bulletin stresses
to minimise skew. the importance of physical construction as well as
electrical design.
EB27A Get 300 Watts PEP Linear Across 2 to
30MHz from. this Push-Pull Amplifier EB90 Low-Cost VHF Amplifier Has Broadband
Includes circuit, PCB artwork and layout for a 300W Performance
push-pull linear amplifier based on two MRF422s, de- This bulletin presents two VHF amplifier designs in-
signed to operate over the 2 to 30MHz band. An tended for FMor CWservice inthe 136-174 MHz band.
MC1723 VOltage regulator is used as a bias supply. Bothfeaturethe Motorola MRF260 and MRF262 plastic
encased VHF transistors which are rated at 5.0 Wand
EB29 The Common Emitter TO-39 and its 15 W power output respectively. The devices are pack-
Advantages aged in a standard TO-220 silicone epoxy case with the
The Common EmitterTO-39 package differs from con- emitter wired to the metal tab and centre lead of the
ventional TO-39s or TO-5s in that the emitter - not the device. This common emitter configuration results in
collector - is connected to the metal case. With NPN good RF performance, improved thermal conductivity,
transistors this configuration allows direct connection and ease of mounting in an RF amplifier by connecting
of the can to RF and negative DC ground in many class the transistor mounting flange to RF and DC ground.
Band C circuits. There are two important advantag es:
by connecting the case to RF ground, emitter induct- EB93 60 Watt VHF Amplifier Uses
ance is reduced and gain increased by 3 to 5 dB over Splitting/Combining Techniques
that of comparable, conventionally wired transistors. Proven combining techniques can be used to obtain
And the case may be directly pressed, clipped, or higher output power and added reliability at VHF.
soldered to the heat sink with no effect on RF perform- Simple matching networks and power transistors with
ance. moderate gain can produce performance comparable
to that of a single-stage amplifier with a larger, more
EBS9 Predict Frequency Accuracy for expensive device. Though not the ultimate answer, the
MC12060 and MC12061 Crystal Oscillator splitter/combiner method has distinct advantages over
Circuits designs that force transistors into a parallel configura-
Crystal oscillators are used to generate a precise and tion. This 60 W amplifier operates from 150 to 175 MHz
highly stable signal. Such circuits typically provide this and features two low-cost MRF264 transistors. The
signal at a frequency close to the resonant freq uency of design uses a modified Wilkinson combiner technique
their crystal. However, circuit components and other to produce 60W output with a drive level of 15W.
factors external to the crystal influence Its natural
resonance to some degree, an effect often referred to
as "pulling" or "warping". This bulletin discusses the
variation in crystal frequency as a function of different

17
 Abstracts (continued)

EB107 Mounting Considerations for Motorola

RF Power Modules
The packaging used for Motorola RF Power Modules
consists of a copper flange on which the ceramic
substrates are soldered, and a non-conductive cover
which is either a snap-on design or attached by epoxy.
The substrates are either 96%Alumina, 95.5%Alumina,
or 99% Beryllium Oxide, and are attached to the copper
flange using lead-tin or indium based soft solders. This
bulletin discusses the mechanical factors that should
be considered when mounting these modules in equip-
ment.

EB411 A Digital Video Proto typing System

This bulletin describes a Digital Video Prototyping
System (DVPS) developed using Motorola's latest multi-
mediadevices, together with a PC-based Field Program-
mable Gate Array (FPGA) development system. It is
designed 10 provide a fast and effective means of
prototyping and demonstrating digital video processing
functions. A Reference Section lists datasheets and
user manuals containing deJailed descriptions and
information on the devices. The DVPS has been suc-
cessfully used to implement two TV sub-systems,
namely a Picture-In-Picture Processor and a 4:3 to 16:9
Picture Processor, which are also described.

18
Applications
Documents

19
20
 AN438
300W, 88-108MHz Amplifier using the
TP1940 MOSFETs Push-pull Transistor
By Georges Chambaudu
Motorola Semiconducteurs Bordeaux SA

INTRODUCTION

The TP1940 is a high power, high gain and broadband The 300 W amplifier described in this Application Note
device with low Reverse Transfer Capacitance, Crss ' has these features:
It makes possible fully solid-state transmitters of • Operates from a 50 V supply
above 5 kW for FM broadcasts.
• High power gain
Like all M OS devices, it is susceptible to damage from • Compact physical layout
electrostatic discharge. Observe reasonable • High efficiency
precautions in handling and packaging it.
Typical data. for the circuit in Figure 2 are given below.

FUNCTIONAL TESTS (V DD = 50 V, Pout = 300 W, Idq = 2 x 200 mAl

Option 1 (with C9p and without C9s) Option 2 (with C9s and without C9p)
f (MHz) GA (dB) 11 (%) GA (dB) 11 (%)

108 19.2 62 18.3 65.4

I
98 19.7 62.6 19.1 68
88 19.4 64 19.6 66.6

Note:
1. Bias increases counter-clockwise with R4.
2. Bias shown is set for 200 mA at 50 V.
3. A copper heat spreader must be mounted on, or laid on top of, a heat sink with thermal grease interface.
4. Drain efficiency can be increased by:
a. Lowering Drain Idle current (power gain will be reduced by 1-2 dB).
b. Increasing the value of feedback resistors R8 and R9. This will change the Gain-Frequency slope and
Input VSWR. The value of C1 must be raised.
5. In addition to the normal cooling of the units, some air flow is recommended over the top side of the amplifier
boards.

21
 I-
> ::::>
+ a..
I-
::J
o
:;:'@'
c:c:
00
"';::; -.;::;
a. a.
00
"mm
en "a.

--
00

Li..i
-l
(§
en

Figure 1. Component layout of 300 W amplifier

22
 R3

-:p C9s'

e9p'
0UTPUT

lC5 I

* see Table on page 1

R9

Cl 24pF Ceramic Chip R5 6.B - B.2 Kn 1/4W (depending on FET gt5)

C2 1OOOpF Ceramic Chip R6 Thermistor, 1OKn at 25°C/2.5Kn at 75°C

C3, Cl0, R7 2Kn 1/2W

Cll O.lIJ.F Ceramic Chip
RB, R9 KDI Pyrofilm PPR515-20-3 or EMC Technologie
C4, C5 1OOOpF Ceramic Chip model 5310 or equivalent 100n

C7 5000pF Ceramic Chip L1 10 turns AWG #16 enamelled Wire, 0.2" I.D.

CB 0.471lF Ceramic Chip or lower values in parallel L2 Ferrite beads, 1.5 IlH Total
to reach the value indicated.
L3, L4 Lead lengths of RB and R9, 0.6" total.
C9p ARCO 404, B-60pF or equivalent
FET TP1940
C9s ARCO 425, 40-200pF or equivalent
Tl 9:1 impedance ratio (input transformer)
Note 1: All ceramic capacitors of 5000pF or less In 25n, 0.062' 0.0. semi rigid co-ax., with
value are A TC type 100 or equivalent. L = 2B mm, I = 11 mm (see Figure 3)

Note 2: The Table on Page 1 shows the effect of T2 4:1 impedance ratio (output transformer)
operating with C9p only or C9s only. 25n, 0.090' 0.0. semi rigid co-ax., with
L = 19 mm, I = 9 mm (see Figure 3)
Rl lKn l/2W
(Tl transformer must be loaded with ferrite
R2 1.5Kn 1/2W
toroids of suitable dimensions and lJ.i of 35-40,
R3 1.5Kn2W or other type ferrite cores, such as Fair-Rite
R4 1Kn Trimmer Potentiometer Products Corporation E and I types 9467012002
and 9367021002 respectively)

Figure 2, 300 W, 88-108 MHz amplifier schematic and parts list

23
Centre
Tap

4:1
IMPEDANCE
RATIO

Figure 3. Constructional details of transformers

Epoxy glass 1'16'

Figure 4. Printed Circuit Board (not full size)

24
 AN448

"FLOF" Teletext using M6805 Microcontrollers

By Peter Topping
MCU Applications
Motorola Ltd. East Kilbride

1. INTRODUCTION

The "r members of the MC68HCOS family of MCUs provide a convenient and cost effective method of adding
on-screen-display (OSD) to TVs and VCRs. As well as the 64-character OSD capability. they include 8 Kbytes of
ROM (adequate forTeletext. frequency-synthesis. stereo and OSD). 320 bytes of RAM. a 16-bit timer and 8 pulse-
width-modulated D/A converters. The MC68HCOST7 also includes IIC hardware and. by using a S6-pin package.
4 ports of I/O independent of the OSD. serial and D/A outputs. It is thus suitable for large full-feature chassis.
The MC68HCOST1 is in the middle of the price/performance range and includes most of the features of
the MC68HCOST7 but in a 40-pin package. This is achieved by sharing I/O with the other pin functions (SPI. OSD.
D/Al. Even if all these features are used. there is sufficient I/O for most applications.

The MC68HCOST2 is a 16K upgrade of the MC68HCOST1 and the MC68HCOST3 a 24K version with increased
RAM (S12 bytes) and enhanced OSD (112 characters and 2 rows of OSD buffer). The low cost MC68HCOST4
has S Kbytes of ROM and 96 bytes of RAM making it suitable in simpler (eg mono. non-Teletext) applications.
The T4 and T7 also include a 14-bit D/A converter to facilitate voltage synthesis tuning. There are EPROM (and
OTP) versions of the T3 (including T1 and T2 emulation). T4 and T7.

This application note describes an example of Teletext control software written for the MC68HCOST7 which
directly controls Teletext chips of the type S243. Spanish FLOF Teletext (leveI1.S) is handled using packet X/26.
If no CCT teletext chip is present on the IIC bus (as indicated by the lack of an acknowledge). all Teletext functions
are disabled in software. About 3Kbytes of ROM are used allowing the code to fit into the 7.9K bytes available
in an MC68HCOST7 along with tuning. OSD and stereo functions.

The software in the included listing has been written for the MC68HCOST7 but could. with a little modification,
be implemented on other M680S microcontrollers. A microcontroller without IIC hardware can be used as long
as additional software is included to facilitate the IIC bus using I/O pins. An example of IIC master I/O driven
software can be found in application note AN446.

2. "FLOF" TELETEXT FEATURES

Full Level One Feature (FLOF) Teletext utilises "ghost" packets to provide features in addition to those available
with the original CCT Teletext. The primary enhancement is the provision of a menu with a choice of four linked
pages selectable by the user with a single press of one of four coloured buttons on the remote control. The menu
itself is sent in the ghost page using packet 24 while the linked page numbers are contained in packet 27. In
addition to linked pages. packets 26 and 30 are used. Packet 26 allows for the substitution of selected characters
in the display by special characters specific to a particular country. This example application includes the Spanish
implementation of packet 26. The broadcast service data packet (8130) is used to get the initial (index) page for
each channel and to display station identification information.

25
"Ghost" packets handled

)(/24 :

The FLOF menu information contained in this page extension packet is transferred by the microcomputer to
row 24 ofthe display chapter. When links are disabled because there is no packet 27 (destination code 0) or when
bit 4 of byte 43 is 0, row 24 is blank.

)(/26 :

Optional handling of modes 1xxxx, 01111 and 00010 in accordance with the Spanish Teletext specification. All
the additional characters which are available in the 5243 CCT chip are handled. The feature can be disabled with
a hardware link on an I/O pin (see figure 1) so that the software can be used at level 1.0 in non-Spanish countries
also using packet 26.

><127:

This packet contains the linked page numbers for the red, green yellow, blue and index (black) keys. Bit 4 on the
link control byte (byte 43) is used to determine if these links are enabled (1) or disabled (0). When enabled, the
Spanish specification requires that bits 1, 2 and 3 be used to enable the green, yellow and blue links respectively.
This use of these bits is not defined in the World Teletext Specification. For this reason their use is selectable by
a hardware link (see figure 1). If these bits are not used. all links (if enabled by bit 4) will be taken from packet 27·
but will be automatically disabled if the broadcast links are default (FF3F7F) or invalid.

8/30:

The broadcast service packet is used to supply the index page number on exit from standby and (if teletext is not
stopped) after a channel change. Bytes 10-30 ofthis packet are displayed for 5 seconds on exit from standby and
(if teletext is not stopped) after a channel change.

3. IMPLEMENTATION

The software listing is in two parts. The first part contains the "idle"loop and IIC routines from the main 'TV control
part of the MC68HC05T7 application. The idle loop controls the timing of everything performed by the
microprocessor, scans the local keyboard, checks whether or not an IR command has been received, etc. It also
monitors the relevant flags in the Teletext chip and performs the tasks (eg fetching linked pages) which have to
be performed independently of requests for the user.

The second and main listing is the Teletext module itself. It contains all the subroutines required to carry out
automatic and user requested Teletext activity. Both modules use the same RAM allocation file (RAMT8.S05)
which is included in the listing of the Teletext module. This listing also includes a symbol cross-reference table.

Figure 1 shows a simplified circuit diagram ofthe application. Most of the MC68HC05TTs I/O is used for purposes
other that Teletext and is not shown in detail. Communication with the 5243 Teletext chip is via an IIC bus in which
the T7 is always the master. The function ofthe three I/O pins used forTeletext is described under "Ghost packets
handled" and "Inputs and Outputs".

A version of this Teletext software has been implemented on an MC68HC05C4 for use in a 'TV where the other
control functions were handled by a separate microcontroller. The signal from the IR pre-amp was fed into the
C4 which used Teletext commands to control a 5243 via a software IIC bus. Non-Teletext commands were re-
generated by the C4 and sent to the other microcontroller. This arrangement allows Teletext to be added to a
chassis which was originally designed without considering Teletext.

26
 O.S.D., Local keyboard,
Analogues, Standby, Mute, 5V
Stereo, AV, etc. Contrast Reduction
Fast Blank
R
G
2 x4k7

2 x 22pf I/O

~ ':'TOM
OSC1 BkxB
SCL SCL RAM
5243 (eg.
SDA SDA MCM6264)
OSC2

MC68HC(7)05T7

I.R. Picture
TCAP PB3 Control
Pre-amp
!1 5231

PB6 PB7

5V

Video

Figure 1. MC68HC(7)05T7 - Teletext application circuit

4. IDLE LOOP

In the example application the idle loop code is in the main TV control software module rather than in the teletext
module. Listing 1 shows the relevant parts of this module. The loop time is 12.BmS and it is at this rate that the
timing counters used by Teletext (CNT1 and CNT4) are incremented. The standby condition is checked first; if
the TV set is in standby then there is no IIC activity and hence no reading from, or writing to, the 5243. If the TV
has just exited from standby, as indicated by the flag 3,STAT2, then Teletext is initialised using the sub-routine
RESTRT. This sub-routine writes to the 5243's control and mode registers (R5, R6 and R7) and checks that the
IIC acknowledge is present. Ifthere was no acknowledge, as indicated by flag 6,STAT7, then no further Teletext
activity is attempted.

If an acknowledge is present. Teletext polling goes ahead, although it is suspended if there is a mute or time
display. A mute indicates that the channel has just been changed, or no channel is tuned. During time display,
all other Teletext activity is suspended. Re-initialisation using sub-routine START2 is performed if flag 7,STAT5
is set by a change of the tuned frequency.

27
Counter CNT4 is used to delay the transfer of packets 24 (page extension - FLOF menu), 27 (links), 26 (enhanced
display characters) and the control bits from row 25 (display page) after the initial arrival of a page. When row 24
is read the 5243 FOUN D fl~g is set to indicate that the arrival has been acted upon. If UPDATE is on then an update
indicator appears if the update control bit (C9) is set or if the sub-page has changed or if it is the first arrival of the
page. The update display is performed by the sub-routine ARRVD which clears the transient flags and enables
the required display, i.e. page no. in normal mode and the whole of row 0 in sub-page mode. Any boxed
information (eg sub-titles or newsflash) in the current page is also displayed. The last Teletext function performed
by the idle loop is the checking of the FOUND flag in the 5243. This is accessed via the IIC bus: it is on the last
(not displayed) row of the"di!\play page along with the current page and sup-page numbers and the control bits.

If there is a current Teletext transient (time, row 0 box or packet 8/30), the transient control branch from the idle
loop is executed. This routine checks to see if it is time to end the transient. If it is, the subroutine OSDLE is
executed. It resets transients for both the OSD generated by the MC68HC05T7 and Teletext. The sub-routine
RSTMD2 performs this function for Teletext. It is called from within the sub-routine OSDLE (not listed).

5. REMOTE CONTROL FUNCTIONS

TV;rxT
Toggle between TV & Teletext mode.

0-9

Number keys for entry of page and sub-page numbers

Red, Green, Yellow, Blue

Linked page access keys. The decoder stores four pages of text. These are the display page and the three pages
corresponding to the red, green and yellow links. The blue linked page is not acquired in advance. In the absence
of FLOF data or if the links are disabled by the control bit in packet 27, the red key is page+ 1 and the green key
page-l. Under these circumstances the requested page and the next three pages are acquired.

PC+/-

These keys always select page+ 1/page-l regardless of the availability of FLOF information. As with the red, green
and yellow keys, the page is displayed immediately if it is already in RAM.

INDEX

This key operates as an additional link with the difference that if the link is invalid the initial page from packet 8/
30 is selected.

SUB-PAGE/TIME

Text mode: Enter sub-page mode, (max. 3979). TV mode: Display time in top-right-hand corner for 5 seconds.
Pressing this key during a station identification display (packet 8/30 bytes 10-30) can be used to extend this display
beyond the five seconds it appears for, after a channel change.

STOP

Halt acquisition, "STOP" is displayed instead of page number. Press again to restart. If acquisition has been
stopped by partially entering a new page number then this key can be used to return to the original page.

28
MIX/NO-MIX

Toggle between Teletext and mixed display. Use of this key causes the display of the top status row for 5 seconds
if it is not being displayed because the current page is a newsflash or a sub-title. 5243 contrast reduction is enabled
in mixed mode.

FULL/TOP/BOT

Selects one of the three display formats. normal. top half enlarged. bottom half enlarged.

REVEAL

Reveal hidden text. toggle action.

UPDATE

Return to picture until a new version of the requested page arrives. When it arrives. its page no. is displayed in
the top-right-hand corner. the key operates in both TV and Teletext mode. set is put into TV mode. Any boxed
information (alarm clock. newsflash or sub-title) will be displayed. In sub-page mode the complete header is
displayed so that both page & sub-page numbers can be seen. Cancel update by entering Teletext mode and then
going back to TV mode by pressing the TVIText key twice.

6. TELETEXT SUBROUTINES

6a. Subroutines: TVTX. UPDATE. DIGITO and GETIT

The Teletext module (listing 2) comprises various sub-routines which are used both by the idle loop and to perform
any Teletext actions initiated by commands from the IR remote control. They are described in the order in which
they appear in the listing.

TVTX is executed when the TV{TEXT button is pressed. Its function is to toggle between TV mode and Teletext
mode. The flag O.STAT indicates the current mode. This flag routes the microprocessor to execute eitherTXTOFF
or TXTON according to the current mode. TXTON checks that Teletext hardware is present and does nothing if
there has been no IIC acknowledge. If. however. a 5243 is present in the TV. it clears all transients (OSDLE) and
sets up the Teletext mode. It initialises the control registers (R5 and R6) to display text and background both in
and out of boxes. For newsflashes the set-up is text and background within boxes and picture outside. TXTOFF
also resets transients but forces TV mode and sync. Polling and updating continue as a background activity.

When the UPDATE key is pressed the update flag 4.STAT2 is set and TXTOFF executed so the TV is forced to
TV mode. If there is a current transient hold (eg time). the hold is cleared before TXTOFF is executed.

The number entry sub-routine DIG ITO branches to DIGITS in sub-page mode but otherwise accepts any number
key as a page number input. Three digits are required. the pointer PDP holding the current position (0. 1 or 2 for
hundreds. tens or units). During entry the flag 2.STAT is set to stop Teletext activity. The numbers have to be
written to the top-left-hand corner of the display page as well as saved in RAM. Once all three digits have been
entered the page is requested and page acquisition restarted.

The code at label GETIT makes this request afterfirst checking whether or notthe selected page has already been
requested (it could be the current display page or an already requested linked page). If it has. then a switch is made
to the chapter associated with the appropriate acquisition circuit and no new request is generated. If not. the new
request is made and the FOUND flag set.

29
6b. Subroutines: Colours, INDEX, NPAGE and PPAGE

The four colour keys (Red, Green, Yellow and Blue) are primarily intended for selecting Teletext linked pages.
When pressed the chapter which corresponds to the appropriate acquisition circuit is selected for display. If links
are disabled (by the link control bit or because there is no packet 27), then the RED and GREEN keys select current
page + 1 and-1 respectively. This choice is taken according to the state offlag 3,STAT3 which reflects the condition
of the link control bit in packet 27. The code executed by RED, if links are not in use, is the same as that executed
by the" +" function (NPAGE) which always selects the next page. Similarly the alternative GREEN function
(PPAGE) is the same as for the "-" key. The YELLOW and BLUE keys do nothing under these circumstances. In
Spanish Teletext the GREEN, YELLOW and BLUE links can be individually inhibited, but the RED link is only
inhibited if all links are off.

The chapter associated with the selected page is displayed immediately if it has already been requested. This will
normally be the case if a linked page (red, green or yellow) has been selected. The code at label LPT is executed
if the page has already been requested. If not. a jump to CLRPD is performed. CLRPD is a label within DIGITO;
the code at CLRPD requests a new page just as if the page number had been entered manually. If the required
acquisition circuit is the one already current, then the "unstop" code is executed. This causes the green page-
being-looked-for header to roll as though the page number had just been entered. This means that something can
be seen to happen in the case where the linked page differs only from the current page in its sub-page number.
Linked sub-pages are not fully supported in this implementation as they are rarely used by broadcasters and would
significantly increase the size of the software. When the chapter is changed the Teletext PBLF (page being looked
for) flag is checked. If it is low the FOUND flag is cleared. This forces the fetching of the links associated with
the new display page. If the page is not already in, this will automatically happen when it arrives so the FOUND
flag does not need to be cleared.

The BLUE (or cyan) key is different in that its page will not normally be immediately available (the four pages:
display, red, green and yellow occupy the four acquisition circuits and RAM chapters).

The INDEX (or black link) function is similar to BLUE except that if its link is not valid it defaults to the initial (index)
page number supplied by packet 8/30 (see sub-routine GIP).

6c, Subroutines: LINK, GLP1, GLP2, SRCH, CHCK1 and NOTOKx

The sub-routine LINK allocates the three linked pages (RED, YELLOW and GREEN) to the three free acquisition
circuits (not in use by the display page). To do this it checks the page numbers in turn to see if they have already
been requested. If so they are left in their current acquisition circuit. If they have not already been requested the
page number is put into a LIFO. Only 0-9 are regarded as acceptable digits for page numbers; this is consistent
with the Spanish specification although the additional HEX numbers (A-F) may be used experimentally or by
Teletext page generators. Within this first loop the sub-routine GLP1 is used to get the linked page numbers from
packet 27, perform a decode of the Hamming encoded data and calculate the new magazine number (page
hundreds) if different from that of the display page. GLP1 uses sub-routine SRCH to check if the page has already
been requested. If there are no links, or if links are disabled, then displayed page + 1, +2 and +3 are requested.

The second loop in LINK allocates new page numbers to the remaining unused acquisition circuits. It uses GLP2
to clear the relevant chapters in the Teletext memory and make the new requests. Subroutine CHCK1 is used
to check whether or not an acquisition circuit is in use before it is loaded with a new page number from the LIFO.

This method of organising new page requests prevents unnecessary requests being made for pages already
requested. This is particularly important when links are disabled and pages are being requested using the "+"
or "-" functions. Under these circumstances when the page number is incremented (or decremented) only one
new page has to be requested (new display page+3)' while page, page+ 1 and page+2 do not need to change and
can be left in their current acquisition circuits.

30
NOTOK3 and NOTOK2 handle the RED and GREEN functions when links are disabled. They are disabled if the
link control bit (packet 27 bit 3, byte 43) is zero or if there is no packet 27. These subroutines respectively increment
and decrement the current page number (units and tens). The current magazine number (page hundreds) is
not affected.

6d. Subroutines: ROW24. W2B. R2B. GCYI. CLINK and DECODE

ROW24 is used to transfer ghost row 20 (packet 24) into the display chapter. This has to be done via the IIC bus.
The loop reads two bytes via the IIC (sub-routine R2B) bus from the ghost page and writes it to the display page
(sub-routine W2B). The FOUND flag is then set to indicate that the arrival of the page has been recognised and
acted upon. This sub-routine is only called by the idle loop and is used along with the other sub-routines which
get information from the ghost page (CLINK, LINK and GET25).

R2B and W2B use IIC routines READ and SEND which are outwith the Teletext module. These subroutines will
differ according to the microprocessor in use. An MC68HC05C8 implementation would neet! to use I/O lines (see
reference for suitable software) while the MC68HC05T7 can use its IIC hardware. The routines used in this
example are included in the listing extract from the TV control software module (listing 1).

The sub-routine GCYI is used by LINK to store the data associated with the BLUE an INDEX links. As explained
above, these pages will not be acquired in advance, the page number only being sent to an acquisition circuit if
requested by an IR command.

CLINK fetches the link control byte from packet 27 if the destination code is OK and, after decoding the Hamming
encoded data, transfers the bits to STAT3.

The Hamming decode sub-routine DECODE corrects for single bit errors. This is done with in-line code using the
table HAM (at the end of listing 2) as this uses less ROM than an algorithmic method.

6e. Subroutines: MIX. TRANx. TXTx. HOLD. and NOHOLD

The mixed display capability ofthe Teletext chip (5243) is toggled using an IR key which calls the sub-routine MIX.
When mixed mode is entered, interlaced broadcast sync. (312/313) is selected because the non-interlaced sync.
used for teletext is not suitable if a TV picture is present on the screen. This is set upvia the 5243 mode register R1.
The control registers R5 and R6 are updated to provide the mixed display.

When returning to a non-mixed display, the code at NOM IX is used to re-configure the control registers and to set
up a Teletext only 312/312 non-interlaced sync. This sync. reduces adjacent line flicker in a pure Teletext display.

The subroutine TRAN2 sets up a transient which retains a black background on the top row so that the page
number, time etc. can be seen clearly. This type of transient is also started if the page number or sub-page number
is being entered in mixed mode. Sub-routines TRAN 1, TRAN2 and TRAN3 are used to initialise the various
transient displays. These displays are cancelled as discussed above by actions taken within the idle loop controlled
by the free-running timer within the MC68HC05T7.

The TXTx sub-routines are used in conjunction with the IIC SEND routine to write to various sub-sets of the
registers within the 5243.

If the Teletext STOP function is requested by an IR command the routine HOLD is executed. This is a toggled
function when requested in this way. HOLD displays the word "STOP" in place of the page number and stops
the display acquisition circuit by clearing the 5243 HOLD flag accessed via its page request register R3.

NOHOLD is executed to restart the display acquisition circuit. It returns the page number to the top-left-hand
corner. If a new page number has been partially entered, a press of STOP (executing an UNHOLD) will allow a
return to the most recent page request. This takes only a single press as the start of the entry of a new page
number cause a HOLD. The completion of a page number entry (3 digits) causes a NOHOLD.

31
6f. Subroutines: REVEAL. EXPTB and TIME

The REVEAL function causes any hidden display information to appear. It is controlled by a bit in the display mode
register (R71. The software example leaves any revealed information permanently displayed. If, however, it is
required that such information disappear when the page is updated (this may be better for a quiz pagel. then the
two commented out lines (80 and 81) in the idle loop should be enabled.

The display expand facility is controlled by another two bits in R7. The EXPTB sub-routine cycles through normal,
top-half double height and bottom-half double height.

The example application uses a single IR key (subroutine TIME) for both the display of the Teletext clock and the
entry into sub-page mode. IF the set is in TV mode then the time is displayed for 5 seconds. If the TV is in Text
mode then sub-page mode is selected. Sub-page number entry is described in the following section. When the
Teletext clock is requested it appears (boxed) at the top-right-hand corner. It is removed by the idle loop 5 seconds
after the last press of the time button. When the time is being displayed all other Teletext activity is stopped
using UCHOLD.

69, Subroutines: DIGITS, SUBPG, GET25 and GET26

DIGITS is the sub-page version of DIGITO and uses similar code. More checks on the input data are required as
the four digits of the sub-page number have different maximum values. These maximums are 3 for thousands,
7 for the tens and 9 for the hundreds and units. These values reflect the sub-page number's original use as a time
(24hr formatl. For tens and thousands a keyed 8 becomes a 0 and a 9 becomes a 1 ; for thousands only 4, 5, 6
and 7 become 0, 1, 2 and 3 respectively.

The code at the label SETIT is the sub-page equivalent of GETIT, described above. It requests the new sub-page
and sets the FOUND flag.

The sub-routine SUBPG is called when the TIME (or clock) key is pressed (TV in Teletext model. It toggles
between normal mode and sub-page mode. When sub-page mode is entered the page number display (P-) is
replaced with * * * * to indicate the mode change and to prompt for the entry of a sub-page number. Once all four
digits have been entered the new sub-page is requested by SETIT. The code at the label RSTR is used to exit from
this mode back to the normal (page number) mode, restoring the page number display to the top-left-hand corner.

GET25 is used by the idle loop to get the information stored in row 25 of the display chapter. This row is not
displayed but contains various information used by the control microprocessor. The current page number,
magazine number, sub-page number, Teletext control bits and the FOUND and PBLF flags are available. GET25
gets the required information and stores it in the RAM of the MC68HC05T7.

At the end of this sub-routine the I/O line 7,portB is checked. If it is low, packet 26 is handled. If it is high, this
packet is disabled. This would be required if this application were to be used in a country other than Spain which
used packet 26. It would require to be switched off as the enhanced display feature uses different characters
depending on the country. In countries which do not use packet 26 (eg the UK) it does not matter whether or not
packet 26 is enabled.

If packet 26 is enabled, GET26 processes all packet 26 data present in the ghost page. The tables G2TAB, G3TAB
and CTAB contain the characters used to replace the character at the display location defined by each packet.

32
6h. Subroutines: GIP, R24T and SR24T
The sub-routine GIP gets the initial (index) page from packet 8/30. It will be doing this as the set is brought
out of standby or just after a channel change. It may thus initially get a poor signal (or there may be no
Teletext) so it tries repeatedly until it finds a valid packet 8/30 format 1. If this is not found after 96 tries it
gives up and sets the flag 6,STAT2 to indicate that there is no packet 8/30 (or no Teletext). In this
circumstance it defaults to an index page number of 100.

R24T transfers bytes 10-30 ofthe broadcasting service data packet (8/30) into the display chapter. It is called once
a second for five seconds after power-on or a channel change. The data is transferred to row 0 of the display page
which can be displayed either at the bottom or, as in this example, the top of the screen. This transient display
is setup using the sub-routine SR24T ifTeletext is present. Ifthe flag 6,STAT2 has been set by GIP as described
above then SR24T does nothing. The transient display is terminated by code executed at the appropriate time
from within the idle loop.

7. INPUT AND OUTPUTS

Apart from the IIC bus, only three pins on the controlling microprocessor are relevant to Teletext. Two inputs
select the usage of packets 26 and 27 and one output can be used to control any hardware which requires to be
changed according to whether or not there is a iV picture currently being displayed. In many applications some
or all of these functions will not be required and could be eliminated from the software thus freeing up the pins
for other uses.

PB3)

This pin is active (high) during a pure (no-mixed, no-boxed) teletext display, otherwise it is low.

PB6)

When this pin is low, Spanish use of link control bits 1, 2 and 3 is enabled. When it is high, these bits are ignored.

PB7)

Packet 26 control. When low, packet 26 is enabled and handles all the Spanish alternate characters which are
available in the 5243. When PB7 is high, packet 26 is ignored.

8. REFERENCES

Application note AN446, MCM2814 Gang-programmer using an MC68HC05B6.

33
 LISTING 1
30
31
32 Idle loop.
33
3.
3S
36 00000000 Od13fd ILP BRCLR 6,TSR, " OUTPUT COMPARE FLAG
37 00000003 >3eOO INC CNTl TELETEXT TRANSIENT
38 00000005 >3eOO INC CNT4 P!OW 24 DElAY
39 00000007 >3eOO INC CNT5 MUTE TRANSIENT
40 00000009 >cdOOOO JSR KBD KEYBOARD' TIMERS
41 OOOOOOOc 030104 BRCLR l, PORTS, FaN STANDBY 'I
42 DCOODCOf :>1600 BSET 3,STAT2 MAKE SURE FLAG AGREES
43 00000011 ZOS! B.... Fl AND IDLE WITH NO lIC ACTIVITY
44 00000013 >070009 FaN BRCLR 3, STAT2,ALRON NO, JUST ON '1
45 00000016 >1700 BCLR 3,STAT2 YES, RESTART
46 00000018 >1500 BCLR 2,STAT2 CLEAR THIS FLAG ALSO '1
47 0000001& >lfOD BCLR 7,STATS RE-INITIALISATION NOT NECESSARY
48 0000001c >cdOOOO JSR RESTRT
49 DOOOOD1! >cdOOOO ALRON JSR VCRPOLL POLL SCART LINES
50 00000022 >02004d BRSET l,STAT2,Fl REMOTE REPEATING 'I
51 00000025 >02004& BRSET l,STAT4,Fl LOCAL REPEATING ?
52 00000028 >Oe0047 BRSET 6,STAT7,Fl TELETEXT CHIP ON BUS 'I
53 0000002b >040044 BRSET 2,STAT2,Fl SEARCH/STANDBY '1
54 0000002e >0.0041 BRSET S,STAT,Fl TIME DISPLAY HOLD
55 00000031 >06D03e BRSET 3,STAT4,Fl TRANSIENT MUTE?
56 00000034 >Oc003b BRSET 6,STAT4, Fl COINCIDENCE MUTE 'I
57 00000037 >Of0005 BRCLR 7,STAT5,DNTRS TO BE RE-ITIALISED ?
58 0000003a >HOD BCLR 7,STAT5 YES, CLEAR FLAG ,
59 0000003c >cdOOOO JSR START2 RE-INITIALISE TELETEXT
60 DOOOOO3f >01001e DNTRS BRCLR 0,STAT2,N024
61 00000042 >bEiDa LOA CNT4 PAUSE WHILE PACKET 24
62
63
00000044
00000046
a130
252a
CMP
BU) •••
Fl
(PAGE EXT.) ARRIVES

64 00000048 >cdOOOO JSR CLINK CHECK LINK CONTROL BYTE

65 0000004b >cdOOOO JSR LINK FETCH LINKS
66 0000004e >cdOOOO JSR ROW24 FETCH ROW 24 AND SET FOUNDB
67 00000051 >cdOOOO JSR GET2S GET ROW 2S , PACKET 26
68 00000054 >090005 BRCLR 4, STAT2, NOUP UPDATE ENABLED 'I
69 00000057 >ObOOOZ BRCLR 5,STAT2,NOUP DIFFERENCES 'I
70 0000005a adEie BSR ARRVD
71 0000005c >1100 NOUP BCLR 0,STAT2
72 OOOOOOSe >bEiDa N024 LOA ACC
73 00000060 >b700
74 00000062 a60.
STA
LOA
R'ta COLUMN 8 (FOUNDB , PBLF)
75 00000064 >b700 STA R10
76 00000066 a619 LOA '2S ROW
77 0000006. >edOOOO JSR R2B
7' 0000006b >010104 BRSET 4, IOBUF+l,Fl FOUNDB FLAG SET ?
79 0000006e >1000 8SET 0, STAT2 NO, SO FETCH GHOST ROWS
80 BCLR 5,R7 KILL REVEAL
81 JSR TXT2
82 00000070 >3fOO CLR CNT4
83 00000072 >04008b F1 BRSET 2, STAT2, ILP SEARCHING?
84 00000075 >060088 BRSET 3, STAT2, ILP STANDBY?
85 0000007' >090085 BRCLR 4,STAT,ILP TRANSIENT?

..
86
87
88
Transient control .
90

"92
93 0000007b >b600 LOA CNTl YES
94 0000007d alSO CMP taO
95 0000007! 2403 BNS NILP
96
97
98
99
00
00000081
00000014
00000086
00000088
aOOOOO8a
>eeOOOO
>b600
a104
2603
>edOOOO
NILP
JMP
LOA
CMP
BNE
JSR
..
ILP
R.

NOTE
R24T
IS TIMER

IF PAGE 4 THEN IT'S

THE 8/30 TRANSIENT
01 aOOOOOld >3f00 NOTE eLR CNTl CLEAR IS TIMER
02 0000008! >3aOO DEC TMR DECREMENT SECONDS COUNTER
03 0000009::' 2703 BEO ONILP TRANSIENT FINISHED ?
04 00000093 >ccOOOO JMP ILP NO
05
06 0000e096 >cdOOOO ONILP JSR OSDLE OSO TIMEOUT (INC RSTMD)
07 00000099 >ccOOOO JMP ILP
08
09
:0
End Teletext transients.
:2
:J Clear mode bits (channel mode>, 2-diqit
:4 proq. no. entry etc.)
:s
:6
17
18 0000009c >010003 RSTMD BRCLR 0, STAT5, SOS2 2-0IGIT Pr. No. ENTRY ?
19 a000009! >edOOOO JSR RES YES, RESTORE DISP
20 000000a2 >1500 SOS2 BCLR 2,STAT4 MAKE SURE ITS PROGRAM MODE
2:
22 000000a4 >1900 RSTMD2 BCLR 4,STAT4 RESET OSD TRANSIENT FLAG
23 000000a6 >1900 RSTMD3 BCLR 4,STAT RESET MAIN TRANsIENT FLAG
24 000000a8 >Ob0011 BRCLR 5,STAT,TXTR1 TIME HOLD?
25 OOOOOOab >lbOO BCLR 5,STAT YES, CLEAR IT
26 OOOOOOad a603 LOA 1$03
27 aaOOOOa! >b700 STA RS
28 OOOOOObl >b700 STA R6
29 000000b3 >cdOOOO JSR TXT2 STOP TIME EXIT FLASH
30 000000b6 >040003 BRSET 2, STAT, TXTRl OTHER HOLD?
31 OOOOOOb9 >cdOOOO JSR NOTTH NO, SO CLEAR HOLD
32 OOOOOObc >1100 TXTRl BCLR O,R7 BOX OFF ROW 0
33 OOOOOObe >000006 BRsET 0, STAT, TXTR2 TELETEXT 'I
34 000000e1 >b600 LOA ACe
35 000000e3 >b700 STA R'
36 000000e5 >3!00 CLR R7 NO, ALL BOXES OFF
37 000000e7 >ecOOOO TXTR2 JMP TXT2 YES

34
139 • • ft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1O.
140

.. .................................. _-_ ............... _-- ...

141 Updated page hall arrived.

,,.3
,.2
'

145 OOOOOOca >b600 "".VD LDA ACC

146
147
OOOOOOcc
ODOOOOce
>b700
>1900
STA
BCLR ••
4.5r.... T KILL TRANSIENTS
148 ODOOOOdO >lbOO BCLR 5.Sr....r

..
149 OOOOOOd2 4! CLM
150 DCOODOd3 >cdOODO JS' BOXOOR
lSI DCOODOd6 >OcDOOS BRSET 6, STAT. SPHD SUB-PAGE MODE 1

..••
152 DeOODOd9 a606 LDA NO, SHALL BOX
153 OOOOOOdb >cdOOOO JS, BOXOOF
154 DCOODOde a646 SPHD LDA 1$46
lSS OOOOOOeO >biOO ST.
156 000000.2 >b700 ST.
157 000000e4 a603 LDA 1$03
158 000000e6 >050002 BRCLR 2.C3,NNF NEWSf'LASH ?
159 aCOOOOd a602 LOA 1$02 YES, NO ROW 0
160 OOOOOOeb >b700 NNF STA .7
Hi1 OOOOOOed >ccOOOO JMP TXTZ
,.2
,.3
164
165
ODOOOOfO
000000f2
a610
>b700
RESTRT LDA
STA .,
1$10 BROADCAST SYNC.

1EiEi
lEi'
000000f4
oooooon
aEi06
>b'OO
LD'
STA ••
.5
168
169
oooooon
OOOOOOfa
>b'OO
>3fOO
STA
CL'
••
.7
170 OOQOOOfc >edOOOO JS. TXT2 SWITCH PICTURE ON
171
172 OOOOOOff 013e03 BRCLR O,MSR,ACI(OK ACKNOWLEDGE ?
173 00000102 >1cOO BSET 6,STAT7 NO, SET FLAG
1'4 00000104 81 'TS
175
176 00000105 >ceOOOO ACKOK JMP INITXT
177
178
179 00000108 >b600 'ES LOA PROG YES, RESTORE PROG. HO.
180 0000010a >b700 STA DISP
181 0000010e >1100 BCLR 0, STATS
182 0000010e 81 ABS 'TS
183
18' •••••••• * ••• * •••••••••••••••••••••••••• **.* •••••••• *.* ••
185
18. IlC write.
187
188 .*.* •••• * ••••••••• * ••••• ****.* •• * •••• *.* •• *.* •••••• *.* ••
18.
,.0 OOOOOlOf ad23 SEND BS. IlCSU

'"
1512
1513
00000111 >bfOO
00000113 >1100
STX
BCLR
DPNT
O,APDR
SAVE X
SET-UP TO WRITE
194 00000115 >h600 LOA ADO.
,..
195

1517
0000011' ad2S

00000119 >bEiOO lORBU

BS'

LO'
SHIFT

ADO.
SEND CHIP ADDRESS

198 00OOOl1b a180 CMP 1$80 STEREOTONE ?

1519 0000Ol1d 2606 BHE lORB
200 0000011f >b600 LOA SUBADR YES, SO ENABLE AUTO
201 00000121 ad1b BS' SHIFT SUB-ADDRESS INCREMENTING
202 00000123 >3cOO INC SUBADR
203
204 00000125 >beOO LOX DPNT DATA BUFFER POINTER
205 00000127 f. LOA O,X
206 00000128 ad14 BS' SHIFT SEND DATA
207 0000012a >3cOO INC DPNT
208 0000012c >3aOO DEC W1

..
209 0000012e 26e9 eNE WRBU DONE?
210
211 00000130 1b3b BCLR S,MCR STOP
212 00000132 CLI
213 00000133 81 'TS
21'
215
216
00000134
00000135
,b
3f3c
IICSU SEI
IIC SET-UP
CLR HS'
217 0000013' 3f3a CLR FO' 90 I(Hz
218 00000139 a6bO LOA t$BO ENABLE lIC AS MASTER
219 0000013b b73b STA HC' TRANSMITTER & START
220 0000013d 8' .TS
221
222 0000013e b13d SHIFT STA HO'
223 00000140 Of3efd BRCLR 7,HSR, *
224 00000143 81 'TS
225
226 00000144 adc9 WRITE es. SEND
227 00000146 a602 LOA '2
228 00000148 >cdOOOO JS, TPAU WAIT lOms (EEPROM WRITE)
22.

35
no
23.
232 IIC read.
233
234
235
236 0000014b adOc READ BSR READ1 GET FIRST BYTE
231 OOOOOHd >b600 LOA IOBUF
238 OOOOOH! >b701 STA IOBUF+l MOVE IT UP
239 00000151 >b600 LDA ADDR
240 00000153 ala! CMP #SAl 1M! ,
241 00000155 2602 BNE READ'
242 00000157 >3cOO INC SUBADR YES, NEXT SUB-ADDRESS
243
244 00000159 add9 READ' BSR IICSU
245 0000015b >1100 BeLR O,ADDR RII' - 0 ALWAYS WRITE t SUB-ADDRESS)
246 0000015d >b600 LDA ADDR
24. DDOOOIS! acl.cl.d BSR SHIFT SEND CHIP-ADDRESS
248 00000161 >b600 LDA SUBADR
249 00000163 add9 BSR SHIFT SEND SUB-ADDRESS
250 00000165 1b3b BeLR S,MeR NO STOP BUT
251
2S2 00000167la3b BSET S,MCR A RESTART
253 00000169 >1000 BSET O,ADDR SET BIT 0 FOR READ
254 0000016b >b600 LOA ADDR
255 0000016d adc! BSR SHIFT RE-SEND CHIP ADDRESS
256 0000016! 193b BCLR 4.MCR CHANGE TO RECEIVER
257 00000171 l63b BSET 3,MeR SWITCH OFF ACtc.
258 000001.3 b63d LOA MDR INITIATE RECEPTION
25.
260 BRCLR 7,MSR,* WAIT FOR IT
26' BSET 3,MCR SECOND LAST SO SWITCH OFF ACtc.
262 LOA MDR GET FIRST BYTE
263 STA IOBUF+l AND SAVE IT
264
265 00000175 Of3cfd BRCLR 7,MSR, * NAIT FOR IT
266 00000178 1b3b BeLR 5,MeR LAST BYTE SO STOP
267 0000017a b63d LDA MDR GET BYTE
268 0000017c >b700 STA IOBUF AND SAVE IT
269 0000017e 9a CLI
270 OOOOOl7t 81 RTS
27.
272
273
274 !IC interrupt.
275
276
277
278 00000180 3f3c MBINT CLR MSR
279 00000182 80 RETURN RTl

36
 LISTING 2
1
2
3 TV/Te!etext/OSD/Stereo program (MC68HCOST7).
•, CCT Teletext control module (Spain).
•
7 Used with RANTa.50S, OST.50S , TMT7.505
•• '" This software vas developed by Motorola Ltd. for demonstration purposes.
10 '" No liability can be accepted for its use in any specific application.
11 original software copyright Motorola - all rights reserved.
12
13 P. Topping 19th October' 90
14
15
16
17 EXPORT DIGITO,RED,GREEN, YELLOW, CYAN
,.
18

20
EXPORT
EXPORT
NPAGE. PPAGE,REVEAL, EXPTB, UPDATE, TVTX, GIP
TIME, MIX, INDEX, HOLD. SR24T, START2, INITXT

21 EXPORT CLINK, LINK, ROW24, GET2S, R2B, TXT2

22 EXPORT R24 T, NOTTH, BOXOON, BOXOOF
23
2. IMPORT SEND, READ, OSDLE, TPAU2
2'
2'
27 LIB HAMT8.S0S
27
27
27
27 RAM allocation for OST.SOS, TMT7.S0S , TXT7.S0S.
27
27
27
27 SECTION.S .RAM,COMM
27
27
27
27 Equates.
27
27
27
27 00000000 PORTA EQU $00 Port A address
27 00000001 PORTB EQU $01 Port B ..
27 00000002 PORTC EQU $02 Port C
27 00000003 PORTD EQU $03 Port D
27 00000004 DORA EQU $04 Port A data direction reg.
27 00000005 DORB EQU $05 Port B" .. ..
27 00000006 DORC EQU $0' Port C
27 00000007 OORD EQU $07 Port D
27
27 00000008 LED1 EQU $08 0/ A 0 STEREO LED
27 00000009 LED2 EQU $0' O/A 1 BILINGUAL LED
27 OOOOOOOa LE03 EQU $" D/A 2 FM -1- NICAH LED
27
27 "VOLU EQU $" O/A 2 JPOB IN T1 EVB
27 OOOOOOOb CONT EQU $08 O/A 3 JP09 IN T1 EVB
27 OOOOOOOc BRILL EQU sOC O/A 4 JPIO IN Tl EVB
27 OOOOOOOd SATU EQU $00 0/11. S JPll IN Tl EVB
27 OOOOOOOe VOLU EQU $OE O/A 6
27
27 00000012 TCR EQU $12 Timer control register.
27 00000013 TSR EQU $13 Timer status register.
27 00000014 ICRH EQU $14 Input capture register, high.
27 00000015 ICRL EQU $15 Input capture register, low.
27 00000016 OCRH EQU $1' Output compare register, high.
27 00000017 OCRL EQU $17 Output compare register. low.
27 00000018 TDRH EQU $18 Timer data register, high.
27
27
00000019
0000001c
TORL
MISC
EQU
EQU
".
$lC
Timer data register, low.
Misc. register
27
27 00000020 OSD EQU $20 IB OSO data registers
27 00000032 CAS EQU $32 Color' status register
27 00000033 C34 EQU $33 Color 3/4 register
27 00000034 RAD EQU $34 Row address' character size
27 00000035 WCR EQU $35 Window/Column register
27 00000036 CCR EQU $3' Column/color register
27 00000037 HPD EQU $37 Horizontal position delay
27
21 00000039 MADR EQ" $3.
27 0000003a FOR EQ" $3A
27 Q000003b MCR EQU $38
27 0000003c MSR EQ" $3C
27 0000003d MDR EQ" $30
27
27 0000003e TRl EQU $3E Test 1, OSO/Timer/PLM
27 aOOOOD3! TR2 EQU $3F Test 2, EPROM

37
27
27
27 Teletext RAM allocation.
27
27
27
27 00000000 SUB1 RMB
2700000001 Rl RMB mode register
2700000002 R2 RMB page request address register
27 00000003 R3 RMB pilge req. data reg. col. 0 : mag.
27 00000004 Cl RMB .. .. .... 1 pqt.
27 00000005 C2 RMB 2 pqu.
27 00000006 c3 RMB 3 ht.
27 00000007 C4 RMB 4 hu.
2700000008 C5 RMB S mt.
27 00000009 C6 RMB 6
27 DOOOOOOa SUB2 RMB
27 QOOOOOOb R4 display chapter register
27 OOOOOOOc R5 RMB display control register (normal)
27 DOOOOOOd R6 RMB display control register (news/sub)
27 QOOOOOOe R7 RMB display mode register
27 aCOODCOf SUB3 RMB
2700a00010 R' RMB active chapter register
27 00000011 R' RMB active row register
2700000012 RIO RMB active column register
2700000013 Rll RMB active data register
2700000014 PH RMB 2nd .. ..
27 00000015 PT RMB 3,d
27 00000016 PU RMB 4th
2700000017 LIFO LINKED PAGE No. LIFO BVFFER
2700000020 PAGE RMB PAGE No. INPUT BUFFER
2700000027 PAGO RMB ACO PAGE No.
270Q00002a PAGl RMB ACl PAGE No.
27 D000002d PAG2 RMB AC2 PAGE No.
2700000030 PAG3 RMB AC) PAGE No.
2700000033 PAGC RMB CYAN PAGE No.
27 00000036 PAGI RMB INDEX PAGE No.
2700000039 PDP RMB PAGE DIGIT POINTER
27 DOOOD03a ACC RMB DISP, RED, GREEN, YELLOW AC. CIR.
27 D000003e WACC RMB WORKING ACC No.
27 OOOOOO)! ADDR RMB lIC ADDRESS
2700000040 DPNT RMB lIC DATA POINTER FOR WRITE
27000000-41 SUBADR RMB IIC SUB-ADDRESS
2700000042 IOBUF RMB IIC BUFFER, +2 , +3 RSRVD FOR PLL
27 00000046 STAT2 RMB 0: ROW24 FETCH FLAG
27 1: REMOTE REPEATING
27 2: SEARCH/STANDBY IIC LOCK
27 3: STANDBY STATUS
27 4: UPDATE PENDING
27 5: DIFFERENCE FOUND
27 6: NO TELETEXT TRANSMISSION
27 7: MIXED
27
27 00000047 STAT3 RMB 0: CYAN LINK ON
27 1: YELLOW LINK ON
27 2: GREEN LINK ON
27 3: LINKS/ROW24 ON
27
27
27
27 General RAM. allocation.
27
27
27
2700000048 PLLHI RMB PLL DIVIDE RATIO MSB
27 00000049 PLLOW RMB PLL DIVIDE RATIO LSB
27 OOOQ004a WI RMB WORKING
27 0000004b W2 RMB
27 0000004c W3 RMB
27 OQOOQ04d COUNT RMB LOOP COUNTER
27 D000004e KOUNT RMB LOCAL KEYBOARD COUNTER
27 QOOOOOH CNT RMB 12.8mS (inc, free running)
27 00000050 CNT! RMB 12.8mS (inc, reset every IS during transient)
27 00000051 eN!J RMB 3.2S S (dec, automatic standby timeout)
27 00000052 CNT4 RM.B 12.8mS (cleared for row24 delay when page arrives)
27 00000053 CNTS RHB 12.8mS (inc, transient mute)
27 00000054 TMR RMB TRANSIENT DISPLAY SECONDS COUNTER
2700000055 STAT RHB 0: TV/TELETEXT
27 1: lIC R/W
27 2: HOLD
27 3: IR REPEAT INHIBIT
27 4: TRANSIENT DISPLAY ON
27 5: TIME HOLD
27 6: SUB-PAGE MODE
27 7: IR TASK PENDING
2700000056 STAT4 RMB 0: KEY FUNCTION PERFORMED
27 1: LOCAL REPEATING
27 2: pIc PROG 0, CHAN
27 3: MUTE (TRANSIENT)
27 4: OSD STATUS TRANSIENT
27 5: MUTE (BUTTON}
27 6: COINCIDENCE MUTE
27 7: SEARCH
27 00000057 PWR RMB $55 AT RESET, $AA NORMALLY
2700000058 PROG RMB CURRENT PROGRAM NUMBER
27 00000059 CHAN RMB CURRENT CHANNEL NUMBER
270000005a DISP RMB CURRENT DISPLAY NUMBER (PROGRAM)
27 OOOOOOSb DISC RMB CURRENT DISPLAY NUMBER (CHANNEL}
27 DOOOOOSc FTUNE RMB FINE TUNING REGISTER
27 OOOOOOSd AVOL RMB VOLUME LEVEL
27 OOOOOOSe BRIL RMB BRILLIANCE LEVEL
27 OOOOOOSf KEY RMB CODE OF PRESSED KEY (LOCAL)
27 -NUMO RMB LED DISPLAY RAM
27 00000060 IRRAl RMB IR INTERRUPT TEMP.
2700000061 IRRA2 RMB " " "
2700000062 IRRA3 RMB
27 00000063 IRRA4 RMB
27 00000064 DIFFH RMB IR TIME DIFFERENCE
27 00000065 DIFFL RMB " " "
27 00000066 IRH RMB IR CODE BIT
2700000067 IRL RMB COLLECTION
27 00000068 IRCODE RMB
27 00000069 IRCNT RMB
27 0000006.1 IRCMCT RMB
27 0000006b OLOIR RMB

38
27
27
27 RAM allocation for Stereoton.
27
27
27
27 0000006c SHADMAT RMB TEMPORARY MATRIX
27 a000006d LBAL RMB Loudspeaker balance variable
27 0000006e SHDKD RKB SOUND MODE O:ST, l:DA, 2:DB, 3:w, 4:M. 5:FM
27 0000006! ABAV RMB SCART SOUND MODE O:STER.EO. l:DlJAL ..... 2:DU.... L B
27
27 00000070 .. RMB Kl level (req 0)
27 00000071 LVL RMB Loudspeaker left volume (req 1)
27 00000072 LYO RMB Loudspeaker right volume (req 2)
21 00000073 HVL RMB Headphone volume left (reg .3)
27 00000014 HYO RMB Headphone volume right (req 4)
27 00000075 TONE RMB Tone variable (Bass/Treble) (reg 5)
27 00000076 MATRIX RMB Current m.atrix (req 6)
27 00000077 '2 RMB K2 level (req 7)
27
27
27 00000078 STATS RMB 0: 2-DIGIT PROGRAM ENTRY
27 1: ANY MUTE REQUIRED ?
27 2: OSD NAME TABLE
27 3: OSD DEFAULT pIc NUMBER
27 4: ANALOGUE eso ON
27 5: NAME-TABLE STANDARD
27 6: STANDARD CHANGED
27 7: RE-INITIALISE TE(.ETEXT
27
27 00000079 STAT6 RMB 0: AV MODE BIT a (O:TV. l:S-VHS)
27 1: AV MODE BIT 1 (2:SCRTl. 3:SCADT2)
27 2,
27
27
27
27
.,
3,
e,
6: SCART INPUT f l
27 7: SCART INPUT '2
27
27 DOOaOOia ST....T7 RMB 0: AV MODE CHANGE
27 1: FORCE FM SOUND
27 2: CS : TELETEXT NEWSFLASH
27 .3: C6 : TELETEXT SUBTITLES
27 4: LANGUAGE .... /B (TV)
27 5: WIDE-PSEUDO
27 6: NO TELETEXT ....CKNOWLEDGE
27 7: POWER UP IN STANDBY
27
27
27
27 OSD RAH allocation.
27
27
27
27 0000001b CAS1 RMB ROW 1, colour 1/2 , outline enable
27 OOOOOOic >AD1 RMB Row address , character size
27 aOOOOOid CCRl RMB Window colour , end column
27 0000007. CAS2 RMB ROW 2, colour 1/2 , outline enable
27 DOOOOD?! >AD2 RMB Row address' character size
27 00000080 CCR2 RMB Window colour, end column
27 00000081 C....S3 RMB ROW 3, colour 1/2 , outline enable
27 00000082 RAIl3 RMB Row address' character size
27 D0000083 CCR3 RMB Window colour, end column
27 00000084 c....se RMB ROW 4, colour 1/2 , outline enable
27 00000085 RAIle RMB Row address' character size
27 00000086 CCRe RMB window colour, end column
27 00000087 CAS. RMB ROW 5, colour 1/2 , outline enable
27 00000088 >AD' RMB Row address' character size
27 00000089 CCR5 RMB Window colour , end column
27 OOOaDala CAS. RMB ROW 6, colour 1/2 , outline enable
27 0000008b RAD. RMB Row address' character size
27 aOOOOOle CCR6 RMB window colour , end column
27 ooaOOD8d CAS 7 RMB ROW 7, colour 1/2 , outline enable
27 0000008e RAD7 RMB Row address' character size
2? ooooooa! CCR7 RMB Window colour' end column
27 00000090 C....SI RMB ROW I, colour 1/2 , outline enable
21 00000091 RAD' RMB Row address' character size
27 00000092 CCRa RMB Window colour, end column
27
21 00000093 'oSDL RMB CURRENT OSD ROW POINTER
27 00000094 LIND RMB ROW TABLE INDEX
27 00000095 BROW RMB CHARACTER FLASH ROW
27 00000096 BCOL RMB CHAr ....CTER FLASH COLUMNS
27 00000097 WROW RMB WINDOW FLASH ROW
~7 00000098 ROWl RMB FIRST ROW No. (NAME TABLE)
27
27 00000099 ANAL RMB
27 OOOaOaga ANAF RMB
27
27 0000009b TMP1 RMB
27 0000009c TMP2
27
27 OOOOOQ9d RMB 12 UNUSED
27
27 000000&9 ST....CK RMB 22 2.3 BYTES USED FOR ST....CK
27 OOOOOObf SP RMB 1 (l INTERRUPT AND 9 NESTED SUBS)
27
27 SECTION .RAH2, COHM
27 00000000 DRAM RMB 12.
2.
29 SECTION .ROH2

39
31
32
..........................................................
33
3.
3'
3.
.......................................,. ...................
Teletext/TV .witchinq.

31 00000000 >000037 TVTX BRIET O. STAT, TXTOFF

38 00000003 >OcOO74 TXTON BRSEl' 6. STAT7, PANIC TELETEXT CHIP ON BUS 1
39 00000006 >1000 aSET 0, STAT TELETEXT MODE
40 00000001 >cdOOOO JS' OSDLE
41
42
DODODOOb
OOOOOOOd
.. 616
>blOD
LDA
srA "16
Rl
CCT, 312/312 SYlfe
ENABLING GHOST ROWS
43 DeOODCO! >1900 BCLR 4, STAT ABORT TRANSIENTS
44 00000011 >1900 BeLR 4,5T"12 KILL UPDATBS
45 00000013 >1fOO BeLR 7,STAT2 NOT MIXED
46 00000015 >Obooas BRCLR 5, STAT, NOTT
47 00000011 >lbOO BCLR 5,IT"T
48 000000101 >040003 BRSET 2, STAT. NOTT
49 DDODOOld >cdOOOD Jsa NOTTR
SO 00000020 aicc NOTT LDA uce
Sl 00000022 >b70C STA .S
52 00000024 4646 LDA 1$46
53 00000026 >b700 srA R.
54 00000028 >b600 LOA ACC
55
56
0000002a
0000002c
>b700
>ccOOOO
srA
JMP
••
rlWl'

"
58
59
OOOOOOH
00000032
>OcOO48
>1800
UPDATE BRSET
as..
6, STAT7, PANIC
4,STAT2
TELETEXT CHIP 1
UPDATE ON
60 00000034 >090003 BaCLR 4, STAT, TXTOFF TRANSIENT HOLD 1
61 00000037 >edOOOO JS' NOTTH YES, RESTART
62 0000003a >1100 TXTorF BeLR 0, STAT TV MODE
63 0000003e >cdOOOO os. OSDLE
64 0000003! >1100 TXTOF BeLR O.STAT TV HODE
65 0000004.1 a610 LDA 1$10 BROADCAST, 3121313 SYNC
66 00000043 >b700 srA .1 ENABLING GHOST ROlfS
67 00000045 >1900 BCLR 4.ST"T 1dSORT TRANSIENTS
68 00000047 >lbOO BeLR 5, STAT 1dSORT TIME TIMEOUT
69
70
00000049
0000004b
a603
>b700
.sr LOA
SrA .,
t$03 $06 FOR TRANSIENTS

71
72
0000004d
OOOOOOH
>b700
>3f00
srA
CLR .,••
73 00000051 >cdOOOO JS' TXT2
74 00000054 a602 LDA t2
75 00000056 >ccOOOO JMP SPM
7'
77 00000059 >e602 TEST LOA PAGO+2.X
78 0000005b a139 CMP t$39
79 OOOOOOSd 221b BHI PANIC
80 OOOOOOS! a130 CMP t$30
81 00000061 2517 BLO PANIC
82 00000063 >8601 LOA PAGO+l,X
83 00000065 a139 CMP ta39
84 00000067 2211 BHI PANIC
8S 00000069 a130 CMP #$30
86 0000006b nOd BLO PANIC
" 0000006d >e600 LDA PAGO,X
88 0000006! a137 CMP #$37
89 00000011 2207 BHI PANIC
90 00000013 a130 CMP t$30
91 00000075 2503 aLO PANIC
92 000000"17 >b700 SrA PAGE
93 00000079 81 ABO .ra OK, CARRY CLEAR
94
95
0000007.
0000007)) ••
81
PANIC SEC
.rs
NOT OK. CARRY SET

40
 97
90
99 Number entry routine!!.
100
101
102
ooa0007c >OdOOO) DIGITO 6, STAT, DIGIT
104 0000007f >ccoaaa DIGITS
105 00000082 >1700 3,R3 HOLD DURING
106 00000084 >b600 ACC
107 00000086 >cdOOOO UP
108 00000089 aG04 f4
109 0000008b >cdOOOO
110
111
0000008e
00000090
112 00000092
>1400
>b600
a010
8SET
LOA .,
2, STAT

tl6
113 00000094 >beOO LOO
114 00000096 2606 BNE NOCH NOT HUNDREDS SO DON'T CHANGE
115 00000098 al07
116
117
0000009a
OOODOQ9c
2302
a008
CMP
BLS "to
NOCH
YES, MORE THAN 7 ?
NO, SO DON'T CHANGE
YES, 8->0 , 9->1
118 000000ge ab30 '$30 CONVERT TO ASCI I
119 OOOOOOaO >e700 STA PAGE,X
120 000000a2 a302 CPX f2 UNITS
121 000000a4 270e BEQ CLRPD YES, SO CLEAR PDP
122 000000a6 a62d LOA '$20 DASH
123 000000a8 a301 tl TENS 1
124 OOOOOOaa 2702 BEQ YES, SO LEAVE TENS
125 OOOOOOac >b70l STA PAGE+1 CLEAR TENS
126 OOOOOOae >b70Z PAGE+2
127 OOOOOObO >3eDa POP
128 OOOOOOb2 2002 DPGN
129 OOOOOOb4 >3fOO CLR PDP
130 OOOOOOb6 >b600 DPGN LOA R4
131 OOOOOOb8 >b70Q STA RO
132 OOOOOOba >3fOO R9 ROW 0
133 OOOOOObc a602 LOA t2
134 ODQDOObe >b700 STA Rl0 COLUMN 2
135 OOOOOOcO a650 LOA '$50
136 OOOOOOc2 >h7QQ R11
137 OOOOOOc4 >b600 LDA PAGE
138 OOOOOOc6 >b7QO STA PH
139 OOOOOOc8 >b601 LDA PAGE+l
140 aoaaGQca >b700 STA PT
141 ODOOOOcc >b602 LDA PAGE+2
142 OOOOOOce >b700 STA PU
143 OOOOOOdO >edOOOO JSR TXT38
144 000000d3 >edOOOO JSR TRANI
145 000000d6 >b600 LDA PDP
146 OOOOOOdS 269f ABO
147
148
149
OOOOOOda
OOOOOOdc
OOOOOOdf
a606
>edOOOO
>b600
"
150 OOOOOOel >b700 STA PH
151
152
153
154 Get requested page.
155
156
157
158 000000e3 >edOOOO GETIT SRCH IS PAGE ALREADY eN ?
159 000000e6 2545 BLO LPT2 YES
160 000000e8 ad23 BSR DISPLAY CHAPTER
161 OOOOOOea >b600 PAGE PAGE HUNDREDS
162 OOOOOOee >e700 STA PAGO, X SAVE lN RAM
163 OOOOOOee >b601 LOA PAGE+: PAGE TENS
164 OOOOOOfO >e701 STA PAC,O+l,X SAVE IN RAM
165 000000f2 >b700 STA Cl PAGE REQUEST TENS
166 000000f4 >b602 PAGE+2 PAGE UNITS
167 000000f6 >e702 STA PAGO+2,X SAVE IN RAM
168 000000f8 >b700 STA C2 PAGE REQUEST UNITS
169 OOOOOOfa >b600 LDA PAGE PAGE HUNDREDS
170 OOOOOOfe a018 SUB f$18
171 OOOOOOfe >b700 R3 PAGE REQ:JEST HUNDRE:::S
172 00000100 >b600 LOA R4
173 00000102 >edOOOO JSR UP
174 00000105 >cdOOOO TXT1 REQUEST IT
17500000108 >1500 BCLR 2, STAT RESET HOl..D fLAG
176 0000010a >ccOOOO JMP SFND WRITE ONE TO fOt:N8
177
1"
179 OOOOOlOd >b600
190 OOOOOlOf 48 x2
181 00000110 >bbOO x3
182 00000112 97
183 00000113 81
184
18500000114 48 LSLA
186 00000115 48 LSLA
187 00000116 48 LSLA
18800000117 48
189 00000118 >b700 R2
190 OOOOOlla 81

41
"2
,.,
"3
,.5 Red, Green' Yellow keys.

19'
,'7
198 0000011'0 >3fOO RED CLR PDP
199 DOODalld >06000b BRSET J, STAT3, RED2 LINKS ON '}
200
201 00000120 >cdOOOO NPAGE JSR INDXP
202 00000123 >cdOOOO JSR NOTOKJ NO, SO FORCE AN INCREMENT
203 00000126 252c BLO LPT ALREADY REQUESTED 1
204 00000128 >ccOOOO JMP CLRPD NO, GETIT
205 0000012b >b601 RED2 LDA ACC+l
206 0000012d 2025 LPT2 BRA LPT
207
208 OOOOOI2! >3fOO GREEN CLR PDP
209 00000131 >06000b BRSET J, STAT3, GLOK LINKS ON 1
210
211 00000134 >cdOQOO PPAGE JSR INDXP
212 00000137 >cdOOOO JSR NOTOK2 NO, SO FORCE A DECREMENT
213 OOOQ013a 2518 BLO LPT ALREADY REQUESTED ?
214 0000013c >ccOOOO JMP CLRPD NO, GETIT
215 aOOOOD! OcOl03 GLOK BFtSET 6.PORTB. IGO GYC BITS ENABLED ?
216 00000142 >010061 BRCLFt O.STAT3.ABC GREEN LINK ON ?
217 00000145 >'0602 IGO LOA ACC+2
218 00000147 200'0 BRA LPT
21'
220 00000149 >07Q05a YELLOW BRCLR 3,STAT3.ABC LINKS ON 1
221 0000014c OcOIO) BRSET 6,PORTB, IGI GYC BITS ENABLED '}
222 OOOOOlH >030054 BRCLR l,STAT3,ABC yELLOW LINKS ON '}
223 00000152 >b603 IG1 LDA ACC+3
224 00000154 >'0700 LPT STA .3
22500000156 48 LSLA X2
226 00000157 >'0'000 ADD .3 X3 FOR PAGE POINTER
227 00000159 97 TAX
228 OOQOD15a >cdOOOO JSR TEST IS PAGE No. OK '2
229 0000015d 2547 BCS ABC IF NOT ABORT
230 OOOOOIS! >b600 LOA .3 ACC No
231 00000161 >'0100 CMP ACC IF SAME ACC CCT
232 00000163 2604 BNE NTSAC THEN FORCE UNSTOP
233 00000165 >1400 BSET 2,STAT
234 00000167 2009 BRA CARO
235 00000169 >Od0003 NTSAC BRCLR 6, STAT, SKOSP SUB-PAGE MODE '}
236 0000016c >cdOOOO JSR OUTSP YES, ABANDON IT
237 COODOI6! >cdOOOO SKOSP JSR RSTR pUT PAGE No. BACK
238 00000172 >3fOO CARO CLR PDP
239 00000174 >050003 COK BRCLR 2, STAT. NOTHLD IF OLD PAGE ON HOLD
240 00000177 >cdOOOO JSR NOHOLD CANCEL HOLD
241
242
243
0000017a
0000017c
0000017e
a60!
>b700
>b600
NOTHLD LDA
STA
LOA
C,
t$OF

W3
CORRUPT C6 FOR UPDATE

244
245
00000180
00000182
>b700
>b700
STA
STA
R'
ACC
246 00000184 >cdOOOO JSR CFND CHECK PBLF, IF HIGH DO NOTHING
247 00000187 >1500 BCLR 2, STAT IF LOW (PAGE FOUND) CLEAR FOUNDB
248 00000189 >ccOOOO JMP TXT2 TO FORCE FETCHING OF LINKS.
249
250
251
252 Index' Cyan Keys.
253
254
255
256 0000018c aeO! INDEX LOX tIS
257 0000018e >cdOOOO JSR TEST
25800000191 2414 BCC lAC
259 00000193 >ccOOOO JMP GIP
260
261 00000196 >07000d CYAN BRCLR 3.STATJ,ABC LINKS ON '2
262 00000199 Oc0103 BRSET 6, PORTB. IG2 GYC BITS ENABLED 7
263 0000019c >050007 BRCLR 2, STAT3,ABC CYAN LINK ON '}
264 0000019f
265 OOOOOlal
aeOc
>edOOOO
IG2 LOX
JSR
"2
TEST
266 000001a4 2401 BCC lAC
267 00000la6 81 ABC RTS
26'
269 OOOOOla7 >ldOO lAC BCLR 6, STAT RESET PAGE MODE
270 OOOOOla9 >3!00 CLR PDP
271 OOOOOlab >e602 LDA PAGO+2, X
272 000001ad >b700 STA PU
273 DOOOOla! >b700 STA C2
274 00000lb! >e601 LOA PAGO+l,X
275 00000Ib3 >b700 STA PT
276 OOOOOIb5 >b700 STA C1
277 00000lb? >e600 LDA PAGO,X
278 000001b9 >b700 STA PH
279 OOOOOlbb aOl8 SUB .$18
280 OOOOOlbd >b?OO STA R3
281 OOOOOlb! >cdOOOO JSR INDX
282 000001e2 >b600 LDA PH
283 OOOOOlc4 >e?OO STA PAGO,X
284 000001c6 >b600 LDA PT
285 00000lc8 >e701 STA PAGO+l,X
286 00000Ica >b600 LDA PU
287 00000Icc >e702 STA PAGO+2,X
288 OOOOOlce >b600 LDA ACC
289
290
00000IdO
000001d2
>b?OO
>cdOOOO
STA
JSR
R'
UP
291 OOOOOldS a6S0 LDA #$50
292 OOOOOld? >b700 STA R11
293
294
00000ld9
OOOOOldb
>3fOO
a602
CLR
LDA
R'
.2
295 OOOOOldd >b700 STA R10
2.'
297 000001d! >1500 CYOK BCLR 2.STAT RESET HOLD FLAG
298 OOOOOlel >edOOOO JSR TXT38
299 000001e4 >cdOOOO JSR TRAN1 DISPLAY TOP ROW
300 OOOOOle? >edOOOO JSR SFND SET FOUNDB
301 00000Iea >ecOOOO JMP TXT 1

42
303
304
30S Get linked page nos , allocate to ....CC •.
300
307
30.
309 DOOOOled >b6Da LINJ( LD.... >CC CHAPTER
310 DOOOOle! ab04 ADD t4 ADD 4 FOR GHOST ROWS
311
312
oaDeaUl
OOOOOlf3
>b700
>3iOO
ST>
CLR
R'
COUNT
313 ODOOOlf5 a601 LD> H
314 OOOOOlf7 >b10D STA .3
315 OOOOOlf9 a6ff LD> t$FF
316 ODOOOlfb >b10I ST> ACC+l
317 QOOOOlfd >b702 ST> ....CC+2
318 OaOOOlf! >b703 ST> ACC+3
319 00000201 >cdOOOO JSR INDXP
320 00000204 >3eDD INC COUNT LOOP ROUND RED. GREEN " YELLOW
321 00000206 >b6QD LO> .3
322 00000208 >b700 ST> RIO
323 0000020a ad43 BSR GLPI GET LINKED PAGE No.
324 0000020c 2406 BHS NOTFND ALREADY IN RAM "2
325 0000020e >beDa LOX COUNT YES, SAVE ACC No.
326 00000210 >&100 STA ACC.X AG .... INST COLOUR
327 00000212 2003 BRA NEXTC
328 00000214 >cdOOOO NOTFND JSR PUSH NOT IN RAM, SO SAVE
329 00000217 >b600 NEXTC LD .... .3 PAGE NUMBER IN LIFO
330 00000219 ab06 ADD to
331 0000021b >b70D STA N3 NEXT LINJI;
332 0000021d >bEiDa LOA COUNT
333 COODa2l! al03 CMP t3 .... LL DONE "2
334 00000221 25e1 BLO LLOP
33S
336 00000223 >cdOOOO JSR GCYI GET CYAN AND INDEX LINKS
337 00000226 >3fOO CLR MACC
338 00000228 a604 LD> t4
339 0000022a >bIOC ST> COUNT
340
341 0000022c >3aOO LLOOP DEC COUNT
342 0000022e >beDa LOX COUNT
343 00000230 >&600 LOA ACC,X
344 00000232 alff CMP #$FF IF STILL AN ACC AT SFF THEN
345 00000234 2612 BHE >LOC RECOVER PAGE No. FROM LIFO
346 00000236 >cdOOOO JSR PULL
34'1 00000239 >b60a LO> WACC
348 0000023b >cdOODO JSR CHCJI;l ALREADY USED "2 IF SO INCREMENT
349 0000023e >beOO LOX COUNT
350 00000240 >e700 STA ACC,X
351 00000242 >cdOOOO JSR UP
352 00000245 >cdOOOO JSR GLP2
353 00000248 >bEiOO ALOe LD.... COUNT
354 0000024a a101 CMP #$01
355 0000024c 22de BHI LLOOP
350
357 0000024e 81 RTS
358
35"
300
3.'
302
Fetch linked page' magazine nUJ'\\bers.

303
304
365 0000024f >b600 GLPI LO> RIO
366 00000251 a113 CMP t19 IF INDEX IGNORE LINK CONTROL
3Ei7 00000253 2203 BHI COR
368 00000255 >07006c BRCLR 3.ST.... Tl.NOTOK LINKS OK 1
3fi9 00000258 a610 COR LOA HO YES, ROW 16 FOR LINKED PAGES
370 0000025a >cdOOOO JSR R2B FETCH 2 LINK BYTES
371 0000025d >b601 LOA 10BUF+l
372 0000025f >cdOOOO JSR DECODE DECODE UNITS
373 00000262 >b700 STA .2
374 00000264 >bfiOO LOA IOBUF
375 00000266 >cdOOOO JSR DECODE DECODE TENS
376 00000269 >b700 STA PT
377 0000026b >bfiOO LOA .2
378 0000026d >b700 STA PU
379 0000026! >cdOOOO JSR INDX CHECK FOR ZERO "]
380 00000272 >efiOO LOA PAGO.X FETCH CURRENT MAG. NO.
381 00000274 >b700 STA PH PAGE HUNDREDS
3.2
383 00000276 >cdOOOO R2BJ1 JSR RADIO
384 00000279 >070009 BRCLR 3. IOBUF.OJl;O MAG BIT ZERO OK "]
385 0000027c >000004 BRSET O.PH.Hl NO, SO TOGGLE
386 0000027f >1000 BSET O.PH
387 00000281 2002 BRA OKO
388 00000283 >1100 HI BCLR O.PH
389 00000285 >cdOOOO OKO JSR RADIO
390 00000288 >050009 BRCLR 2. IOBUF,OJl;l MAG BIT ONE OK ']
391 0000028b >020004 BRSET 1.PH.PT1 NO, SO TOGGLE
392 0000028e >1200 BSET 1.PH
393 00000290 2002 BRA OKI
394 00000292 >1300 PTI BCLR 1.PH
395 00000294 >070009 OKI BRCLR 3, IOBUF,OK2 HAG BIT TWO OK ']
396 00000297 >040004 BRSET 2,PH,pul NO, SO TOGGLE
397 0000029a >1400 BSET 2,PH
398 0000029c 2002 BRA OK2
399 000002ge >1500 PUI BCLR 2.PH
400 000002aO >ccOOOO OK2 JMP SRCH
401
402 000002a3 >cdOOOO R2BJ2 JS' R2B FETCH 2 LINK BYTES
403 000002a6 >b601 LOA IOBUF+1
404 000002a8 >cdOOOO JSR DECODE DECODE UNITS
405 000002ab >b700 STA PU
406 000002ad >b600 LOA IOBUF
407 000002af >cdOOOO JSR DECODE DECODE TENS
408 000002b2 >b700 ST> PT
409 000002b4 20CO BRA R2BJ1
410
411 000002b6 >cdOOOO NOTTH JSR RELI
412 000002b9 a018 SUB #$18
413 000002bb >b700 STA R3
414 000002bd afi04 LDA #4
415 000002bf >ccOOOO JMP SPH

43
417
41.
........................ ..... ....... "."" .............
" " "
419 New bits for default , -1) links.
."." .. " ..... .. .... .. .. ... "" .... "."."" ..............
("
420
421 " " " " "
422
423 0OOOO2e2 >1dOO NOTOK3 BCLR 6, STAT CANCELL SUB-PAGE
424 0OOOO2e4 >edOOOO NOTOK JSR INOX
425 0OOOO2e? >e600 LDA PAGO,X
42' 0OOOO2e9 >b100 STA PH
427 0OOOO2eb >b602 LDA PAGEt2
42. 0OOOO2ed 4c INCA
42' 0OOOO2ce >b100 STA PO
430 0OOOO2dO >bl0l PAGEt2
431 0OOOO2d2 al39 CM!' 1$39
432 0OOOO2d4 2312 BLS NOV9
433 0OOOO2d6 a630 LOA 1$30
434 OQOQ02dS >b100 STA PO
435 COOOO2da >b102 STA PAGEt2
436 0OOOO2de >3eOl INC PAGEt1
43' 0OOOO2de >b601 LDA PAGEt1
438 0OOOO2eO a:39 CM!' 1$39
439 OOOCC2e2 2304 BLS NOV9
440 OOCC02e4 a63C LDA t$30
44: OOOOC2e6 >b?Ol NOV9A STA PAGEt1
442 000OC2eS >b6Cl NOV9 LDA PAGEtl
443 OOCOO2ea >b100 PT
4" OCJOO2ee 20b2 OK2
4<5
44' Clee >ldOO NOTOK2 BCLR 6, STAT CANCEL SUB-PAGE
02tO >e600
".
44'

'"
<lS'-:
C2f2 >b1CC
Olf4 >b6C2
02!"6 4.
LOA
STA
LDA
DECA
PAGO,X
PH
PAGEt2

~ S: e2f? >b700 STA PO

>b7C2
'"
4S3
~ S4
C2f9
C2fb
Clfd
a:3C
24e9
STA
CM!'
BHS
PAGEtl
1$30
NOV9
455 02f!" a639 LOA t$39
4" 030: >b70C STA PO
<I S ~ 0303 >b702 STA PAGEt2
':S8 0305 >3aO: DEC PAGEtl
459 0307 >b601 LOA PAGEtl
':62 0309 aDO eM!' t$30
~ 6: 030b 24db BHS NOV9

'"
463
030d
030:
a639
2CdS
LDA
BRA
t$39
NOV9A

'"
465 ••• * ••• * •••• * ••••••••• * ...................................

,,-
'"
".
'"c:
~ -2
Request new linked page.
• ••••••••••• * ....... * •••••••••• * •••• * ••••••••••••••••••••

>b?OC GLP2 STA R2

~ 72
,0,
~ 73 "44
44
LSRA
LSRA
LSRA
415 >b70C STA C2 x2
4'6 44 LSRA
t, ~ ~ >bbOC ADD C2 x3
P' X <- 3 x ACC No.
es
~ S:
"
>b60C
>b700
TAX
LDA
STA
PO
C2
~s: >e1C2 STA PAGO+2,X

'"
~ S3
>b6CC
>b?OC
>e70:
LDA
STA
P!
Cl
PAGOtl, X
'"S 5
~ >b6CO
STA
LDA PH

'"'"
>e7CO STA PAGO,X

". aO:S
>b7CO
SOB
STA
U1S
R3

'"
.; 9~
~ 9:
0000330
0000332
a309
221e
CPX
BHI
t9
ABORT
"2 0000334 a6SQ LDA USO
493 0000336 >b100 STA Rl1

'"
495
0000338
0OO033a
>b600
abGS
LOA
ADD
WACC
'$08
ACC
CLE.AR CHAPTER
49' OOOC33e >b700 STA R. INTO IIC

".
'"
49'
588
000033e
0000340
0000342
OC00344
>3[00
a602
>b700
>b600
CLR
LDA
STA
R'
n
RlO
ROW 0
COLUMN 2

LDA C2
50: 0000346 a:39 CM!' '$39
sn 0000348 2206 6HI ABORT
503 OCC03';a >b60C LDA Cl
S04 0OO034e a:39 CM!' '$39
50S OOOG34e 230: BLS LOK
506 00003S0 '1 ABORT
507
508 000003 5 ~ >cdOQOO TXT3 CLEAR CHAPTER
509 00000354 a606
510
S11
COOOO356
00C00359
>edOCOO
>1100
LDA
JSR
BCLR
"
TPAU2
3, R8
WAIT
FOR IT
~ON'T CLEAR THIS TIME
S:l 0OOO035b >edOOCC JSR TX138 PDT PAGE. NUMBER IN CHAPTER
S:3 0000035e >edOOOO JSR SFNo SET FOUND FLAG
514
515
00000361

516 00000364 ae08

517 00000366 >e600
518 0000036S >e100
>eeOOOO

PUSH
PSHL
JMP

LOX
LOA
STA
..
TXTlL

PH,X
LIFO, X
AND REQUEST IT

51. 000OO36a 5. oECX

520 0000036b 2<1f9 BPL
521 0OOO036d 81 RTS

44
523 ."' ••••• ** ..................... "''''.** •••• ** ••••••••••••••••
52'
525 I a page already in RAM 1
526
527 ••••••••.••••••••••••••••.•••••.• "' .•..•••••.••••..•..• *.

..
52.
529 0000036e >3fOO SRCH CLR WAce
530 00000370 >b600 LOOPS LOA wAce
531 00000372 LSLA
532 00000313 >bbOO ADD WAce
533 00000375 97 TAX
534 00000376 >e600 LOA PAGD,X
535 00000378 >blOO CMP PH
536 ODOOO37a 260c BHE FIN!
537 0000031c >e601 LOA PAGQ+l,X
538 0000037e >blOO CMP PT
539 00000380 2606 BNE FIN!
540 00000382 >e602 LOA PAGO+2,X
541 00000384 >blOO CMP PU
BEQ

.
542 00000386 270B FND2
543 00000388 >3c:OO FIN I INC wAce
544 OOQ0038a >b6QO LOA WAce
545 0000038c alD4 CMP
546 00000388 25eO BLO LOOPS
547
548 00000390 >b600 FNDZ LOA WAce IF MATCH THEN CHECK FOR
549
550
00000392 alD4
00000394 81
CMP
RTS
•• SUB-PAGE MATCH (SHOULD
DISPLAY PAGE BE DIFFERENT)
551
552 •••••••• * •• ** ................ * .......... * .............................
553
554 Is Acequisition circuit in use '1
555
556 .......................... *." •• * .................. """ .... "".
557
558 00000395 >3eOO SAM INC WACC
559 00000397 Sf CHCKI CLRX
560 00000398 >b600 CHC((2 LOA WACC

..
561 0000039a >e100 CMP ACC,X
562 000003ge 27f7 BEQ SAM
563 000003ge 5c INCX
564 0000039f a304 CPX
565 000003a1 25f5 BLO CHCK2
566 000003a3 81 RTS
567
568 000003a4 >3eOO RADIO INC RIO
569 000003a6 >3eOO INC RIO
570 000003a8 >edOOOO JSR R2BN9
571 000003ab >b600 LOA IOBUF
572 000003ad >edOOOO JSR DECODE
573 000003bO >bfOO STX IOBUF
574 000003b2 81 001 RTS
575
576 ..... " •••• " •• " •••••••• " ••••• *.* ..... **.* ••• *.* ..... **"."**.
577
57. Transfer ghost row 20 to display row 24.
"9 , Bet found flag.
580
581 **"*.""." ••• ,, .......................... * ........................ * ......

..
582
583 000003b3 >3fOO ROW24 CLR RIO
584 000003b5 >b600 MRE LOA ACC CHAPTER
585 000003b7 ab04 ADD ADD 4 FOR GHOST ROWS
586 000003b9 >b700 STA R'
587 000003bb a614 LOA .20 ROW 20
588 0OOOO3bd ad5a BSR R2B
58.
590 000003bf a620 LOA t$20 SPACE
591 OOOD03el >b700 STA Rll
592 000003e3 >b700 STA PH
593 000003c5 >070008 BRCLR 3,STAT3,BLANK ROW24 ENABLED '1
59.
595 000003e8 >b601 LOA IOBUF+l YES, SO USE DATA
596 000003ca >b700 STA Rll
597 000003cc >b600 LOA IOBUF
598 000003ce >b700 STA PH
599 000003dO >b600 BLANK LOA ACC BACK TO
600 000003d2 >b700 STA R' DISPLAY CHAPTER
601 00OO03d4 a618 LOA .2.
602 000003d6 ad31 BSR W2B
603 000003d8 23db BLS MRE
60.
60S 000003da >1800 SFND BSET 4.Rll SET FOUND FLAG
606 000003dc a619 SFND2 LOA .25 WRITE IT
607 000003de >b700 STA R' RON
60B 000003eO a608 LOA ta
609 000003e2 >b700 STA RIO COLUMN
610 000003e4 a605 LOA ts
611 000003e6 >ecOOOO JMP TXT32
612
613 000003e9 >cdOOOO erND JSR CPBLf"
614 000003ec 250f BCS ABCF
615 000003ee >1900 BC:LR 4,Rll CLEAR FOUND FLAG
616 00OO03!0 20ea BRA SFND2
617
618 000003f2 >edOOOO INDXP JSR INDX
619 000003f5 >e601 LOA PAGO+1. X
620 000003f7 >b701 STA PAGE+l
621 000003f9 >e602 LOA PAGO+2,X
622 000003fb >b702 STA PAGB+2
623 000003fd 81 ABCF RTS
62.
625 000003fe Sf PULL CLRX

.
626 000003f! >e600 PLLL LOA LIFO,X
621 00000401 >e700 STA PH,X
628 00000403 5c INCX
629 00000404 a309 CPX
630 00000406 25f7 BLO PLLL
631 00000408 81 RTS

45
."
• 34
. _ • • • fI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

'3' R.ad and write .ubroutin•••

.
'3'
'37 Cyan 6 Index link. , link control byte •
• 3'
'3'
641
642
643
" 00000409
aOOOO40b
D000040d
>b700
a606
>cdOOOO
W2S STA
LOA
JSR
..
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • iII • • • • • • • • • • • • • • • •

TXTJ2
ROIf2 •

64.4 00000410 >3eOO INC RiO

645 00000412 >3eOO INC RiO
646
647
,
648

650
651
. 00000414
00000416
00000411

00000419
0OOOO41b
>b600
a126
11
>b700
.a608
V,
R2S
R1BN9
LOA
CMP
Rn

STA
LOA
RiO
'3.

.
R' ROIl

652 0000041d. >biOO STA SUBJ

653
654
655
0OOOO41!
00000421
00000423
a604
>b700
>.eOO
LOA
STA
LOX
.,••
fSUB3
656 00000425 >cdOOOO JSR SEND22
657 00000428 .2 MUL DELAY TO SATISFY
658 00000429 .2 MUL lIC TIMING
659
660
661 a622
0000042.
0000042c
0000042e
a6Db
>b70a
READ22
LOA
STA
LOA
."
SUBACR
'$22
662 >b700 00000430 STA ADOR
663 00000432 >coOOOO JMP
".
665
666
00000435
00000437
a'll
>b700
GCYI LOA
STA
READ

."
.,0
CYAlI

667 00000439 >edOOOO JSR GLPl

668 0000043e a640 LOA 1$40
669 0000043. >edOOOO JSR GLP2
670 00000441 a6l! LOA .31 INDEX
671 00000443 >b700 STA Rl0
672 00000445 >edOOOO JSR GLPl
673 00000448 a650 LOA USO
674 0000044a >eeOOOO JMP GLP2
."
676 OOQOOUd
671 0000044!
>b600
ab04
CLINK LDA
ADD ..
ACC

678 00000451 >b700 STA RI

6'9 00000453 >3fOO CLR STAT3
680 00000455 >3fOO CLR Rl0
681 00000457
682 00000459
683 0000045e
a610
>edOOOO
>b601
LOA
JSR
LOA
."
R2S
I08UF+1 DESTINATION BYTE
684 0000045. 260. SNE NPl(27 IF HOT ZERO, NO PI(21
685 00000460 &fi25 LDA tl7 CHAIN CONTROL BYTE.
686 00000462 >b70a STA Rl0
U700000464 a610 LOA fl'
688 00000466 adbl .SR R2S
689 00000468 >b601 LOA IOBUF+1
690 0000046a adOl BSR DECODS
691 0000046e >bfOO STX STAT3

....,.........,,, ........................................................
692 0000046e 81 NPK27 RTS
. .3

........................................................
Hamminq decode •

700 000004H >b700 DECODE STA Wl

'01 00000471 Sf CLRX
702 00000472 >d60000 TRA LOA HAM,X
703 00000475 >b100 CM!' Wl
704 00000477 2732 SEQ FNDJ
70'
706 00000479 >b700 TRZE STA SUB2
707 0000047b >000004 BRSET 0,sua2.ZE1
708 0000047e >1000 aSET 0, SUa2
709 00000480 2002 BRA ZIt1+2
710 00000482 >1100 ZEl seLR 0,SUa2
711 00000484 >edOOOO JS. SSUS
712 00000487 2722 SEQ FNDJ
7"
714 00000489 >d60000 TROW LOA HAM,X
715 0000048e >b700 STA SUB2
716 0000048e >020004 BRIET 1,SUB2,ON1
717 00000491 >1200 BSET 1,SUB2
718 00000493 2002 BRA ON1+2
719 00000495 >1300 ONl seLR 1,SUB2
720 00000497 ad7a SSR ssua
721 00000499 2774 SEQ FNO
722
723 OOOOOUb >d60000 TRN LOA HAM,X
724 000004ge >b700 STA SUB2
725 OOOOOhO >040004 BRSET 2,5UB2.TW1
726 OOOOOhl >1400 aSET 2,5UB2
127 00000h5 2002 SRA TW1+2
728 00000h7 >1500 TWl SCLR 2, SUB2
729 000004a9 ad68 BSR SSUB
130 OOOOOhb 2762 FNDJ SEQ FNO
731
732 000004ad >d60000 TRTH LOA HAM, X
733 000004bO >b700 STA SUB2
734 000004b2 >060004 BRSET 3,SUB2,1H1
735 000004b5 >1600 SSET 3,SUB2
736 000004b7 2002 SRA TK1+2
737 000004b9 >1700 THl seL" 3,SUB2
738 000004bb ad56 .SR SSUB
739 0OOO04bd 2750 SEQ FNO

46
741 ** .......... ***** .. ***** ... ******"'******* .. ** ••••••••• *** ••••••
742
743 More Hamming decode.
744
745 .............. "' ................ "........................... _.
740
147 OOD004bf >d60000 TRFO LOA HAM, X
748 000004c2 >b700 STA SUa2
749 OOOD04c4 >080004 BRSET 4,SUB2,FaI
750 000004e7 >1800 8SET 4,SU82
751 000004e9 2002 B.... F01+2
752 000004cb >1900 FOl BCLR 4,SU82
753 DODODted ad44 BS' SSUB
754 OOOOD4cf 273e BEQ FND
755
756 000004dl >d6DOOO TRFI LOA HAM, X
757 000004d4 >b10Q STA SU82
758 000004d6 >OaOO04 BRSET 5.SUB2.FIl
759 000004d!J >laOO 8SET 5,5UB2
760 DOOOD4db 2002 BRA FIl+2
761 000004dd >lbDQ FIl BeLR S,SUB2
762 0OOOO4df ad32 BS' SSUB
763 000004e1 2720 BEQ FND
704
165 000004e3 >d60000 TRSI LDA HAN,X
766 000004e6 >b70Q STA SUB2
767 000004e8 >000004 BRSET 6, SU82, SIl
768 000004eb >lcOO BSET 6,SUB2
769 000004ed 2002 BRA SI1+2
770 000004ef >ldOO SIl BCLR 6,SUB2
771 000004!l ad20 BS' SSUB
772 000004f3 271a BEQ FND
773
774 000004f5 >d60000 TRSE LOA HAN,X
775 000004f8 >b700 STA SUB2
776 000004fa >OeOO04 BRSET 7, SUB2, SEI
771 000004fd >leOO aSET 7,SUB2
778 000004ff 2002 BRA SEl+2
779 00000501 >lfOO SEl BCLR 7,SUB2
780 00000503 adOe BS. SSUB
781 00000505 2708 BEQ FND
782
783 00000507 50 INCX
784 00000508 a30! CPX f$OF
785 0000050a 2203 BHI FND
786 OOOOOSOc >eeOOOO JMP TRA
787 OOOOOSOf >d60000 LOA NUM,X
788 00000512 81 'TS
78'
790 00000513 >b600
791 00000515 >bl00
792 00000517 81
LOA
CMP
RTS
.,
SUB2

793
794 ....................................... * ..........................
795
790 Mix/nomix.
,.7
.* ••••••••••••.••••••••.•.••••••••••••.••••••••••••••.••.
,..
,.8

800 00000518 >OeOO15 MIX BRSET 7, STAT2, NOMIX ALREADY MIXED ?

801 0000051b >leOO BSET 7,STAT2 NO, SO MIX IT
802 0000051d a610 LDA 1$10 BROADCAST, 312/313 SYNC
803 000005lf >b700 STA ENABLING GHOST ROWS
804
805
00000521
00000523
a606
>edOOOO
LDA
JS'
"
1$06
Noax
B06 00000526 a66e LDA t$6E
807 00000528 >b700 STA 'S
808 0000052a a617 LOA 1$17 $46 FOR NOMIX FLASH/SUBT.
809 0000052c >b700 STA .0
810 00OO052e 2015 BRA TRAN2
811
812 00000530 >lfOO NOHIX BCLR 7,STAT2 MIXED, SO NOMIX
813
814
815
00000532
00000534
00000536
a616
>b70Q
a6ee
LDA
STA
LDA
.,
1$16

UCC
CCT, 312/312 SYNC
ENABLING GHOST ROWS

816 00000538 >b700 STA .5

817 0000053a a646 LDA #$46
818 0000053e >b700 STA .0
819 0000053e 2005 BRA TRAN2
820
821 00000540 a606 TRANl LDA to
822 00000542 >edOOOO JS' BOXOOF
823 00000545 a602 TRAN2 LOA t2
824 00000547 >edOOOO JS' SPM SET-UP SYNC
825 0000054a 4f CLRA
826 0000054b >edOOOO JS' aOXOON
827 0000054e >1800 TRAN3 aSET 4,STAT
828 00000550 ad15 BS' F'O FORCE HEADER DISPLAY
829 00000552 a606 LDA to
830 00000554 >b700 STA TM> 58 TIMER
831 00000556 a60"l LDA 1$0"1
832 00000558 >b700 STA .7 ENABLE ALL BOXES
833
834
835
836
0000055a
0000055e
0000055e
a605
>b700
a604
TXT2 LOA
STA
LOA
.,
tS

t4
DISPLAY 'CONTROL

837 00000560 >b700 STA SUB2

838 00000562 >aeOO LOX 'SUB2
839 00000564 >eeOOOO JMP SEN022

..
840
841
842 00000567 a619 F.O LOA .,5 FORCE DISPLAY OF HEADER
843 00000569 >b700 STA
844 0000056b a606 LDA to
845 0000056d >b700 STA .10
846 0000056f >b600 LDA ACC
847 00000571 >b700 STA .8
848
849
00000573
00000515
>3fOO
a605
CL'
LDA ."
t5
850 00000577 >eeOOOO JMP TXT32

47
852 ••••••••• " ••• ** •••••••••••••••••••••••••••••••••••••••••
.,.
85'

.
Hold.
855
856 ** ••••••••••••••••••••••••••••••••••••••••••••••••••••••
"
858 0000057.1 >3fOO HOLD CLR PDP
859 0000057c >040062 BRSET 2. STAT. NOHOLO
.60 OOOaOS7f >1400 SSET 2, STAT
861 00000581 >b600 LOA ACC
.62 00000583 >b700 STA R'
86.3 00000585 >cdOOOO JSR UP
'6' 00000588 >3fOO CLR R' ROW 0
.65 OOOOOSBa >ldOQ BCLR 6, STAT RESET SUB-PAGE HODE
866 0OOOO58c Sf CLRX
.67 DaOQased ad2b BSR DISP8
868 DODD ass! >b60a UCHOLD LOA ACC
869 00000591 >b7QO STA R' DISPLAY CHAPTER
870 00000593 >cdOOOO JSR UP
871
872
00000596
00000598
>3fOO
>1700
C'"
BCLR
R.
3,R3
ROW 0
HOLD
87' 0000059.1 a604 LOA f4
87' 0OOOO59c adl! BSR SPH WAS TXTl
875 OaOOO5ge 20ae BRA TRAN'
876
877 000005aO >OcOOOa TXTl BRSET 6, STAT. SPM2
."
."
880
000005013 >.3fOO
000005.15 >3[00
OOOD05.17 >3fOO
TXTIL CLR
CLR
CLR
C3
C'
C5
881 OOODOSa9 aGOf LOA tSOF CORRUPT C6 SO THAT NEXT
882 OOOOOSab :>b700 STA C6 ARRIVAL IS SEEN BY UPDATE
88'
88'
.85
OOOOOSad
OOOOOSaf
OOOOOSbl
a60a
:>b700
a60l
SPM2
SPH
LOA
STA
LOA
.,
OlD
Ol
886 OOOOOSb3 :>b700 STA SUB1
887 OOOOOSbS :>aeOO LOX fSUBI
888 OOOOOSb7 :>eeOOOO
."
"0 OOOOOSba :>bfOO DISP8
JHP

STX
SEND22

.3
••
..."'",
OOOOOSbe :>3fOO
'"
892 OOOOOSbe
OOOOOSbf
4f
ad07
CLR
CLRA
BSR DISP4
00000Se1
00OOOSe3
:>b600
ab04
LOA .3
f4
ACO
896 OOOOOSeS
." 00000Se6
898 00000Se8
"a604
:>b700 DISP4
TAX
LOA
STA
f4
RlD
899 OOOOOSea :>d60000 LOA LHOLD, X
900 OOOOOSed :>b700 STA Rll
.01 OOOOOSe! :>d60001 LOA LHOLD+l,X
902 OOOOOSd2 :>b700 STA PH
OOOOOSd4 :>d60002 LHOLD+2,X
'"
'04 OCOOC5d7
905 OCOOOSd9
:>b700
:>d60003
LOA
STA
LOA
PT
LHOLD+3, X
906 000005dc :>b700 STA PV
907 000005de :>ccOOOO JHP TXT3
'08 ••••••••••••••••••••••••••••••••• t ••••••••••••••••••••••

'"
910
91: Nohold.
912
9:3 •••••••••••• * ••••••••••••••••••••••••••••••• ** ••••••••••
9:4
915 OeOOOSe! :>IS00 NOHOLD BCLR 2,STAT
916 00000Se3 :>b600 LOA ACC
OOOOOSeS :>b700
'"
91. 00000Se7 >3fOO
919 OOOOOSeS aG02
STA
CLR
LOA
R'
R'
t>
ROW 0

920 000005eb >b700 STA R10 COLUMN 2

91' 000005ed a650 LOA 1$50
922 000005ef :>b700 STA Rll
923 000005fl adOb BS' RELl
91' 0000050 ad14 BS' REL2
925 000005f5 >edOOOO JSR TXT38
926 000005f8 >cdOOOO JSR SFND
927 000005fb >eeOOOO JHP TRAN2
n.
929 OOOOOSfe >b600 RELI LOA ACC
930 00000600 >cdOOOO JSR UP

'" 00000603 >edOOOO

932 00000606 >e600
933 00000608 81
JSR
LOA
RTS
INDX
PAGO,X

'3' 00000609 >b700 REL2 STA PH

'" 0000060b a018

936 0000060d >b700
937 0000060f >e601
SVB
STA
LOA
fS1I
.3
PAGO+l,X
938 00000611 >b700 STA PT
939 00000613 >b100 STA Cl
940 00000615 >e602 LOA PAGO+2, X
941 00000617 >b700 STA PU
942 00000619 >b700 STA C2
943 0000061b >ceOOOO JHP TXTl

'"
945
946
0000061e
00000620
>b600
:>b700
CPBLF LOA
STA
ACC
R.
947 00000622 a609 LOA U
948 00000624 >b700 STA R10
949 00000626 a619 LOA '2S
950
951
952
00000628
0000062b
0000062e
.,
>cdOOOO

>OaOlOl
JSR
SEC
BRSET
'2B

S,IOBUF+l,HIGH
953 00OO062f
'SO 00000630 "
81 HIGH
CLC
RTS

48
..••.......,"0
"7
• ••••••••••••••••••• ** ••••••••••••••••••• ** •••• **** .... **

Reveal.top/bottom. , clock .
••••••••••••••••••••••• " .......... "' ...................... **

962 00000631 >DaDOO4 REVEAL BRSET S,Ri.REV

963 00000634 >laDO BSET 5.Ri
964 00000636 2016 BRA OUT
965 00000638 >lbOO 'EV eeL. S,Ri
966 000006301. 2012 BRA OUT
967 0000063c >DiODOb EXPTB BRCLR 3.R?,EXP
968 0000063! >090004 SRCLR 4.RI,BOT
969 00000642 >1700 BCLR 3,R? SINGLE HEIGHT
910 00000644 200B BRA OUT
971 OOOOOU6 >1100 80T BSET ",Ri BOTTOM
972 00000648 2004 BRA OUT
973 0000064a >1600 EXP B5ET 3,R?
974 0000064c >1900 BCLR ",Ai TOP
915 0000064e >c:cOOOO OUT JMP TXTZ
.7.
971 00000651 >OcOOde TIME BRSET 6.STAT7,HICH TELETEXT CHIP ?
918 00000654 >010003 SRCtR 0, ST1.T. CLOCK TELETEXT MODE ?
979 00000651 >ecOOOO JMP SUBPG YES
980 0000065a >Oa0025 CLOCK BR5E'1' 5,5'1'AT,TAO NO, TIME A.LREADY ON ?
981 0000065d >b600 LD. ACC
982
983
0000065f
00000661
>b700
>cdOOOO
S"
JS.
••
UCHOLD
984 00000664 >1800 BSET 4.STAT
985 00000666 >laOO BSE'l' 5,S'1'AT
986 00000668 Of CLM
987 00000669 adlc BS' NOax
988 0000066b a61e LOA BO
989 0000066d adle BS. BOXOOH
990 0000066f >cdOOOO JS, F'O
991 00000672 a609 LOA #$09
992 00000674 >b700 S" 07
993 00000676 >cdOOOO JS. TXT2 STOP FLASHES ON FIRST PRESS
994
995
00000679
0000067b
a646
>b700
LOA
STA .,
#$46

996
997
0000067d
0000067f
>b700
>cdOOOO
STA
JS. ••
TXT2
998
999
00000682
00000684
a606
>b700
T.O LOA
S"
••
TMR
1000
1001
1002
00000686
00000687
00000689
81
>b700
a620
HOBX
.TS
S"
LOA
.,0
#$20
1003
1004
1005
0000068b
0000068d
0000068f
200a
>b700
a60b
BOXOON
BRA
STA
LOA
.,0
80X

#$OB
1006
1007
1008
00000691
00000693
00000695
2004
>b700
460a
BOXOOF
BRA
STA
LD.
.,0
BOX

#$OA
1009 00000691 >b100 80X ST' 011

.••
1010 00000699 >b100 STA PH
1011
1012
0000069b
0000069d
>b600
>b700
LOA
STA
••••
1013 0000069f >3fOO CL'
1014 000006a1 a606 LD.
1015 000006a3 >ccOOOO JMP TXT32

49
1017
1018
1019 Sub-page nUl'flber entry routine.
1020
1021
1022
1023 000006a6 >edOOOO DIGITS JSO TPSTP
1024 000006a9 >b600
1025
1026
000006ab
000006ad
a010
>beOa
LO.
SUB .,6
W2

500 LOX PDP

1027 aa0006af 2704 BEQ THOU
1028 000006b1 a302 CPX f2
1029 000006b3 260f

.
BNE SORTD
1030 000006b5 al07 THOU CMF t7 THOUSANDS OR TENS
1031 000006b7 2302 BLS SOCH NO, SO DON'T CHANGE
1032 000006b9 a008 SUB YES, 8->() , 9->1
1033 000006bb 5d SOCH TSTX WAS CPX to

."
1034 000006bc 2606 BNE SORTD
1035 000006be al03 CM? MORE THAN 3 1
1036 000006cO 2302 BLS SORTD NO
1037 000006c2 a004 SUB YES, 4->0 TRRU 7->3
1038 000006e4 ab30 SORTD ADD .$30 CONVERT TO ASCII
1039 000006e6 >e703 ST. PAGE+3, X
1040 000006e8 a303
1041
1042
000006ea
000006ec
2714
a62a
CPX
BEQ
LO'
"
SLRPO
ts2A
UNITS?
YES, SO CLEAR PDP
ASTERISK
1043 000006ee a3al CPX t! HUNDREDS ?
1044 000006dO 2706 BEQ HUN YES, SO LEAVE HUNDREDS
1045 000006d2 a302 CPX Ol TENS 1
1046 000006d4 2704 BEQ SEN YES, SO LEAVE TENS , HUNDREDS ?
1047 000006d6 >b704 STA PAGE+4 CLEM HUNDREDS
1048 000006d8 >b705 HUN ST. PAGE+5 CLEAR TENS
1049 000006da >b706 SEN STA PAGE+6 CLEM UNITS
1050 000006de >3eOO INC PDP
1051 000006de 2002 B .... SPGN
:.052 000006eO >3fOO SLRPD CLO PDP
1053 000006e2 >b600 SPGN LOA ACC
1054 000006e4 >bl00 STA O'
~055 000006e6 4f CLRA
1056 000006e7
>b700 ST. 0' ROW 0
:057 000006e9
:>edOOOO JS. BOXOON COLUMN 0
1058 000006ec a602 LD, .2
1059 000006ee
:>b700 ST. '10 COLUMN 2
:060 000006fO
>b603 LOA PAGE+3
106: 000006f2
>bl00 STA 011
1062 000006f4
>b604 LOA PAGE+4
1063 000006[6
>bl00 STA PH
1064 000006f8
:>b605 LOA PAGE+5
:065 000006fa
>b700 ST. PT
:066 000006fe
>b606 LOA PAGE+6
1067 000006fe
>bl00 STA PU
1068 00000700
:>edOOOO JS' TXT3
1069 00000703
>edOOOO JSO TRAIl!
:070 00000706
>b600 LOA PDP
~ all 0 a 0007 D8
2661 .NE SSO
:072
:073
0000070a
OOOOOlOe
a606
>edoaoo
LOA
JSR
'6
NOaX
:074 0000070f
>b603 LOA PAGE+3
1075 00000711
>bl00 STA 011
:016 000001:3
>b604 LOA PAGE+4
:077 00000715
>b70D ST. PH
:078
:079
:080
:08: Get requested sub-page.
:082
:083
:084
:085 000007:7 >b60: SETIT LOA PAGE+l
:086 00000719 :>b700 STA C!
:087 0000071b >b602 LOA PAGE+2
:088 eeOD071d >blQO ST. C2
:089 OOOOOll! >b603 LOA PAGE+3
:C% 00000721 :>b700 STA C3
:091 00000723 >b604 LOA PAGE+4
:092 00000725 >b700 STA C'
:093 00000727 >b605 LOA PAGE+5
:094 00000729 >b70C ST. es
1095 0000072b >b606 LOA PAGEH'
1096 COOOa72d >blOO ST. C6
:097
:098 0000072f >b600 LOA PAGE PAGE HUNDREDS
:0990Q000731 a018 SUB ts18
:100 00000733 >b700 STA .3 PAGE REQUEST HUNDREDS
1101 00000735 >b600 LOA ACC
:102 00000737 >edOOOD JSO UP
~ 103 0000073a :>cdOOOO JSO TXTl REQUEST IT
:104 000007Jd >1500 BCLR 2,STAT NOHOLD
1105 00000l3f >ccOOOO JM? SFND WR I TE ONE TO FOUND
1106
1107 00000742 >b600 TX138 LOA PH
1108 00000744 al30 CM? t$30
1109 00000746 2604 BNE TXT3
1110 00000748 a638 LOA

....
ts38
1111 0000074a >b700 STA PH
1112
1113 0000074e a608 TXT3 LOA
1114 0000074e >b700 TXT32 STA .!
1115 00000750 a608 LOA WRITE CCT RAM VIA I Ie
1116 00000752 >b700 STA SUB3
1117 00000754 >aeOO LOX fSUB3
1118
1119 00000756 a622 SEND22 LOA t$22
1120 00000758 :>b700 STA ADD'
1121 0000075a :>ccOOOO JM? SEND
1122
1123 0000075d >b600 TPSTP LOA PAGE HOLD DURING
1124 0000075f >b70D SUB-PAGE NUMBER

.
STA .3
1125 00000761 >b600 LOA ACC ENTRY
1126 00000763 >cdOOOO JSO UP
1127 00000766 a604 LOA
1128 00000768 >ccOOOO JM? SPM
1129 0000076b 81 SSO OTS

50
1131
1132
1133 Sub (timed) pages.
1134
1135
1136
1137 0000076e >Oe002e SUBPG SRSET 6, STAT, OUTSP
1138 0000076f >1eOO SSET 6,STAT
1139 00000771 adea BS' TPSTP
1140 00000773 >3fOO CL. PDP
1141 00000775 >cdOOOO JS. INDX
1142 00000778 >e600 LOA PAGO,X
1143 0000077a >b700 STA PAGE
1144 0000077e >e601 LOA PAGO+l,X
1145 0000077e >b701 PAGE+l
1146 00000180 >e602 PAGO+2,X
1147 00000782 >b702 STA PAGE+2
1148 00000784 a62a LOA t$2A
1149 00000786 >b700 STA .11
1150 00000788 >b700 STA PH

...
1151 0000078a >b700 STA PT
1152 0000078e >b700 STA PU
1153 0000078e >b600 LOA ACC
1154 00000790 >b700 STA
1155 00000792 >3fOO CL.
1156 00000794 a602 LOA .2
1157 00000796 >b700 STA .10
1158 00000798 adb2 BS. TXT.3
1159 0000079a >eeOOOO JHP T!WI1
1160
1161 0000019d adOd OUTSP BS.
1162 0000019f >b600 LOA ACC
1163 000001a1 >edOOOO JS. UP
1164 000001a4 >1500 BCLR 2, STAT RESET HOLD FLAG
1165 000001a6 >edOOOO JS. TXTI
1166 000001a9 >eeOOOO JHP T!WI1
1161
1168 000001ac >ldOO BCLR 6, STAT
1169 000001ae >3fOO CLR PDP
1110 000001bO a650 LOA 1$50
1171 000001b2 >b100 STA .11
1172 000001b4 >cdOOOO JS, INDX
1113 000001b1 >e600 LOA PAGO,X
1114 000001b9 >b100 STA PH
1115 000001bb a018 SUB 1$18
1116 000007bd >b100 STA .3
1111 000001bf >e601 LOA PAGO+1,X
1118 000001e1 >b100 STA PT
1119 000001c3 >b100 STA C1
1180 000001c5 >e602 LOA PAGO+2, X
1181 000007c1 >b700 STA PU
1182 000001c9 >b100 STA C2
1183 000001cb >3fOO CLR
••
..
1184 000001ed a602 LOA f>
1185
1186
000007ef
000007d1
>b100
>b600
STA
LOA
"'0
ACC
1187 000007d.3 >b700 STA
1188 000007d5 >ceOOOO JHP TXT38
1189
1190
1191
1192 Read in Row 25 information.
119.3

..
1194
1195
1196 000007d8 >b600 GET25 LOA ACC
1197 000001da >b100 STA
1198 000007de >lbOO BCLR 5,STAT2 CLEAR DIFFERENCE FLAG
1199 000007de a602 LOA '2 COLUMN 2 (MINUTES)
1200 000007eO >b700 STA 010
1201 000001e2 a619 LOA '25 'OW
1202 000007e4 >edOOOO JS. .2B
1203 000007e7 >b601 LOA IOBUF+l
1204 000007e9 >bl00 CHP C6
1205 000007eb 2704 BEQ SM6
1206 000007ed >laOO BSET 5,STAT2
1207 000007ef >b700 STA C6 MINUTES UNITS
1208 000007fl >b600 SM6 IOBUF
1209 000001f3 >b100 SUB2 MINUTES TENS" CelT 4
1210
1211 000001f5 a604 LOA f4 COLUMN 4 (HOURS)
1212 000007!? >b100 STA .,0
121.3 000001f9 a619 LOA .25 'OW
1214 000001fb >cdOOOO JS. .2B
1215 000001fe >b601 LOA IOBUF+l
1216 00000800 >b100 CHP C.
1211 00000802 2104 BEQ SM'
1218 00000804 >laOO SSET 5,STAT2
1219 00000806 >b100 STA C. HOURS UNITS
1220 00000808 >b600 SM' LOA IOBUF
1221 0000080a >bl00 CHP C3
1222 0000080e 2104 BEQ SM3
1223 0000080e >laOO BSET 5,STAT2
1224 00000810 >b100 STA C3 HOURS TENS " CBITS 5 " 6
1225
1226 00000812 a40c SM3 AND t$OC SAVE CBITS 5 " 6 IN STAT7
1221 00000814 >1500 BCLR 2,STAT7 CLEAR NEWSFLASH BI T
1228 00000816 >1100 BCLR 3,STAT7 CLEAR SUBTITLE BIT
1229 00000818 >baOO ORA STAT7
1230 0000081a >b100 STA STAT7
12.31 0000081e a606 LOA .6 COLUMN 6 (CONTROL BITS)
12.32 0000081e >b100 STA 010
1233 00000820 a619 LOA '25 ROW
1234 00000822 >edOOOO JS. .2B
1235 00000825 >1100 BCLR 3,SUB2 XFER CBIT8 (UPDATE)
1236 00000821 >0.30102 BRCLR 1, IOBUF+ 1, TR5 TO BIT 3 OF MINUTES TENS
1231 0000082a >1600 BSET 3,SUB2 (REPLACING CBIT4 (ERASE)
1238 0000082e >b600 TRS LOA SUB2
1239 0000082e >bl00 CMP C5
1240 00000830 2704 BEQ CGET26
1241 00000832 >laOO SSET 5,STAT2
1242 00000834 >b100 STA C5
124.3
1244 00000836 Of 0101 CGET26 BRCLR 7, PORTS, GET26 PACKET 26 ENABLED:
1245 00000839 81 RTS

51
1247
1248
........................................................
1249
1250
1251
1252
........................................................
Proce •• packet 26 info.

1253 0000083a a6ff GET26 LDA UFF

1254 0000083c >b700 STA LIFO
lZ55
1256 0000083e >3f01 LOOP26 CLR LlFO+! START NEW ROW
l25'? 00000840 >b600 LDA ACC
1258
1259
00000842
00000844
00000846
ab04
>b'?OO
>b601
>DD
STA ••
O'
LlFO+l
GHOST CHAPTER

1260 LDA
00000848 >b'?OO

...
1261 STA OlD
1262 00000844 >3cOO INC LIFO
1263 0000084c >b600 LDA LIFO
1264 0000084e alOe CMP STILL l'ACnT 26 'l
1265 00000850 2303 BLS OK"""
1266 00000852 >ccOOOO JM!' EN026
1267 00000855 >b600 OKROW LDA LIFO
1268 00000857 >cdOOOO JSR 02B
1269 0000085a >b60! LDA IOBU1"+1
1270 0000085c >bl00 CM!' LIFO IS BYTE ~ERO OK '1
1271 0000085e 26de BNE LOOP2, NO, TRY NEXT ROW
1272 00000860 >3aOl DEC LIFO+1
1273
1274
1275
1276
00000162
00000864
00000866
>b600
ab04
>b700
LOOP62 LDA
>DD
STA
,.
ACC

R'
1277 00000868 >YeOl INC LIFO+l
1218 0000086a >3cOl INC LIFO+l
1279 0000086c >b601 LDA LIFO+1
1280 0000086e >b700 STA RlD
1281
1282
00000870 a126 CMP '38 PAST END OF ROW '1

1283
1284 00000872 230d BLS NXTCH
1285 00000874 >3fOO CLR RlO YES. BLOW AWAY ROW
1286 00000876 a6ff LDA 1$1"1"
1287 00000878 >b700 STA Oil CORRUPT SEQUENCE No.
1288 0000087a >b600 LDA LIFO
12119 0000087c >cdOOOO JSR W2B
1290 0000087f 20bd BRA LOOP26 NEXT ROW
::.291
1292 00000811 >b600 NXTCH LDA LIFO
1293 00000883 >cdOOOO JSO R2. GET 2 BYTES
:294 00000886 >b601 LDA IOBUF+1
1295 00000888 >b708 STA LIFO+8
1296 OOOOOlla >b600 LDA lOBUli'
:297 aOOOOllc >b70'? STA LIFO+7
:29B OOOOOlle >3c01 INC LIFO+l
:299 06000890 >b60! LDA LIFO+!
:30C 00000892 >b700 STA RIO
:30:. 00000894 >cdOOOO JSR R2BN9 GET THIRD BYTE
:302
:303 00000891 >b600 LDA IOBUF
:3 O~ 00000199 >b706 STA LIFO+6
:305 OCOOCB9b >b607 LDA LIFO+7
:306 0000089d a47c AND f$7C
:30"'1 OOOOOn!

""
LSRA
:308 ooeOOBaO LSRA
:37:9 OOOOOBal >b702 STA LIFO+2 SAVE MODE
:3:0 OOOOOla3 >cdOOOO JSR E><AD
:3:: OeOOOBa6
:3:2 OOOOOBaB
:3:3 OOOOOha
>b605
a128
2106
LDA
C....
B.O
LIFO+5
"0
RN2.
""" 2.
,
:3 :~ 00OOC8ac 250a BLO NOTROW
:3:5
:3:6 OOOOOSae
:3:7 000008bO
a028
2002
SUB
BRA
"0
SKIP
SUBTRACT 40 FOR ROW

:3:1 000008b2 a61e RW24 LDA '2'

:3:9
:320 OCOO08b~ >b704 SKIP STA LIFO+4
:32: 00CCC8b6 20u BRA LOOP62
:322
:323 000008b8 >b604 NOTROW LDA LIFO+4
:32~ OOOOC8ba
:325 CCOCOBbc
>b700
>b600
STA
LDA
R'
ACC
:326 CCCC08be >bl00 STA R'
:327 ~CCCClcO >0605 LDA LIFO+5
:328 '::COCCBc2 >bl00 STA RIO
:329
:33'; CCCCC8c~
>09024: BRCLR 4.LIFO+2.NOTD DIACRITICAL '1
:33: ~C:::C08c7 >b602 LDA LIFO+2
:332 C'::CCC8c9 a:10 CM!' #$10 NULL 7
:333 C~C:::C8cb 2775 BEO NULD YES, .JUST SEND IT (BIT7-1)
:33~
:335 ';CC:::~8cd.
:336 CCCC~8ce
:337 C~CCOldC
"
>: f06
>d60000 TaNCH
CLRX
BeLO
LDA
7, LIFO+6
CTAB,X
:338 ~CC~0813 >b:06 CMP LIFO+6
:339 OOOO'::ld5 270a BEQ CHFND
:3~ C '::'::CC'::8d.7
:34: COCC08dB
9!
ab07
TXA
>DD ,7
:H2 CC'JCiClc!a
:343 CCCntdc
:344 CCCC08dd
97
a:Sb
23!:
TAlC
CMP
BLS
,.,
TRNCH
:345 COCCOid!" g63 BRA CHNF
:346
:347 CCCCC8e:. >0602 CHFND LDA LIFO+2

...
:348 OOCOOle3 a40!" AND tsOF
:'349 00000le5 >0103 STA LIFO+J
1350 OeOOOle7 275b BEO CHNY NULL DJA.
:351 000DCle9 al04 CMP
:352 0OOO08eb 2312 BLS GTT
<.353 OOOOOBed al08 CM!'
13 5~ OOOOOle! 2604 BNE NOTCF
1355 OOOODHl a003 SUB t3
1356 000008n 2001 BRA UOC

52
1358 00000Sf5 al0b NOTCF tll
1359 OOOOOSr? 2702 BEO CEDI
1360 00000Sf9 2049 BRA CHNF ILLEGAL MODE
1361 OOOOOBfb 01005 SUB ts
1362 ODOOOSfd >b703 STA
1363 000008ff 9f TXA
1364 00000900 >bb03 ADD LIFO+3
1365 00000902 97
1366 00000903 >d60000 LOA CTAS, X
1367 00000906 203e BRA GOTCH
1368
1369 00000908 >b602 NOTO LOA LIFO+2
1370 0000090a a10f CMF '$OF
1371 0000090e 271e BEO G28IT
1372 0000090e 01102 CMF '$02
1)73 00000910 263e END26
1374
1375 00000912 >lf06 G3BIT BCLR 7, LIFO+6
1376 00000914 5f CLRX
1377 00000915 >d60000 TN32 LOA GJTAS, X
1378 00000918 2603 BNE STRM
1379 000009101 >eeOOOO JMF LOOP 62
1380 0000091d >bl06 LIFO+6
1381 000009lf 2704 BEO G32F
1382 00000921 5e INCX
1383 00000922 5e INCX
1384 00000923 20fO TN32
1385 00000925 >d60001 G32F G3TAB+l, X
1386 00000928 201e GOTCH
1387
1388 000009201 >lf06 G2BIT BCLR 7, LIFO+6
1389 0000092e 5f CLRX
1390 0000092d >d60000 TN23 G2TAB, X
1391 00000930 2603 STMR
1392 00000932 >eeOOOO LOOP 62
1393 00000935 >bl06 STMR LIFO+6
1394 00000937 2704 BEO G23F
1395 00000939 5e INCX
1396 000009301 5e INCX
1397 0000093b 20fO TN23
1398 0000093d >d60001 G23F LOA G2TAB+l,X
1399 00000940 2004 BRA GOTCH
1400
1401 00000942 >le06 NULD BSET 7, LIFO+6
1402 00000944 >b606 CHNF LOA LIFO+6
1403 00000946 >b700 R11
1404
1405 00000948 a605 LOA ts
1406 000009401 >edOOOO JSR TXT32
1407 0000094d >ecOOOO LOOP 62
1408
1409 00000950 END26
1410
1411 ......................... "* •• " ............. " ••••••••••••••••••••••• "
1412
1413 Packet 26 character look-up table_
1414
1415 ..... * ............ " ••••• " ••••••• *** •••• ** .................. * ... **
1416
1417 00000951 202021e02383 G2TAB FCB $20, $20, $21, $EO, $23, $83
1418 00000957 248426932740 FeB $24, $84, $26, $93, $27, $40
1419 0000095d 289429a72aa2 FCB $28, $94, $29, SA7, $2A, $A2
1420 00000963 2cbc2d5e2ebe FeB $2C, $8C, $2D, $5E, $2E, $8E
1421 00000969 2f7630cb37c7 FeB S2F, $76, $30, $C8, S37, SC7
1422 0000096f 388a39a73aa2 FeB $38, $8A, S39, $A7, S3A, SA2
1423 00000975 3c823d8c3e89 FeB $3C, $82, S3D, $8C, $3E, $89
1424 0000097b 3fe161f963e5 FeB S3F, $El, $61, SF9, $63, $E5
1425 00000981 69fd6be66cfe FCB $69, SFO, S68, $E6, $6C, SFE
1426 00000987 71f879fc7cff FCB S71, SF8, 579, SFC, $7C, SFF
1427 0000098d 7f7fOO FCB $7F ,S7F, 500
1428
1429 00000990 51815b8dSe8b G3TAB SSI, $81, $58, $80, SSC, $88
1430 00000996 Sd8eSf2000 $50, SSE, $5F, 520, $00
1431
1432 0000099b 61eaebd2c59261 eTAB FCB S61, $EA, 5-EB, S02, $C5, $92, $61
1433 000009a2 41flf041dS9b41 FeB S41, $Fl, $FO, $41, $05, S98, $41
1434 000009019 65egeede65db65 FeB $65, SE9, $EC, $OC, $65, SOB, $65
1435 00OO09bO 45f290454S4S45 FeB 545, $F?, $<)0, $45, $45, $45, S45
1436 000009b7 696gedde69d469 FeB $69, S69, $EO, $OE, $69, $D4, S69
1437 000009be 4949f34949f449 FeB $49, S49, 5F3, $49, $49, $F4, 549
1438 00000ge5 6fe8eed8c6986f FCB $6F, $C8, $EE, $08, $C6, 598, S6F
1439 00OO0gec 4ff6f5d8d69c4f FeB $4F, $F6, 5F5, 508, $D6, $9C, 54f
1440 000009d3 75elefd975e275 $75, $Cl, 5EF, $09, $75, $E2, 5":5
1441 000009da 5555f75555ge55 $55, $55, 5F7, $55, 555, $9E, $55
1442 00000gel 6e6e6e6ee86e6e FeB $6E, $6E, $6E, $6£, 5£8, $6E, 56!':
1443 00000ge8 4e4e4e4ee74e4e FCB $4£, $4£, $4E, $4£, $S7, $4E, $~E
1444 DOOO0gef 636363636363e3 $63, $63, 563, 563, $63, 563, 5E3
1445 000009f6 434343434343d7 $43,$43,$43,$43,$43,$43,5;::-
1446
1447 OD0009fd >3f05 eLR LIFO+5
1448 000009ff >030702 BRCLR 1,LIFO+7,N032
1449 00000a02 >la05 5, LIFO+5
1450 00000a04 >010702 N032 0,LIFO+7,N016
1451 00000a07 >1805 4, LIFO+5
1452 00000a09 >Od0802 N016 BRCLR 6, LIFO+8, N08
1453 OOOOOaOc >1605 SSET 3, LIFO+5
1454 OOOOOaOe >Ob0802 NO' 5, LIFO+S, N04
1455 00000a11 >1405 BSET 2, LIFO+5
1456 OOOOOa13 >090802 N04 BRCLR 4,LIFO+8,N02
1457 000000116 >1205 1, LIFO+5
1458 00000a18 >050802 N02 BRCLR 2, LIFO+8, NOI
1459 OOOOOalb >1005 BSET 0, LIFO+5
1460 OOOOOald 81 RTS

53
1462 ******".**.**** ............. * .... * .. "* .... ** •• * .. * ... """ •• ,,***,,*"
1463
1464 Fetch initial paq8 from 8/30 format 1.
1465
1466 ............ * ................... **.* ...... *.**"* •• ,, •• * ... *.**** ...
1467
1468 OOOOOale >lbOO GIP BCLR 5,STAT CLEAR TIME HOLD
1469 00000a20 >ldOO BeLR 6, STAT CLEAR SUB-PAGE MODE
1470 00000a22 >ldOO BCLR 6,STAT2 CLEAR NO TXT FLAG

.."".
1471 00000a24 >3fOO CLR POP
1472 00000a26 a602 LDA
1473 00000a28 >cdOOOO JSR SPM TXTI 1 BYTE ONLY
1474 00000a2b a604 LDA
1475 00000.12d >b700 STA R. CHAPTER
• (GHOST)
1476
1477
1478
OOOOOa2f
00000a31
00000.133
a660
>b700
>3.100 TRYAG
LDA
STA
DEC
.,., 9. TRYS

1479 00000.135 2735 BEQ IPNF AGAIN ?

1480 00000a37 a601 LDA fl
1481 00000.139 >edOOOO JSR TPAU2
1482 00000a3e >3fOO CLR R10
1483 00000a3e a617 LOA I"
1484 00000.140 >edOOOO JSR R2B
1485 00000a43 >b601 LDA IOBUF+1 8/30 FORMAT 1 FOR INITIAL PAGE
1486 00000.145 26ec BNE TRYAG
1487 00000a47 a60l fl COLUMN 1
1488 00000.149 >b700 STA R10
1489 000OO.14b a630 LDA 1$30 RESET PAGE HUNDREDS
1490 OaOOOa4d >b700 STA PH
~4 91
1492
0000 Oa4 ~
00000.151
a617
>edOOOO
LDA
JSR
fl'
R2BJ'2
LINE
" (PACKET 8/30)

:493 00000a54 >b600 GETIND LDA PH INITIALISE INDEX (BLACK)

1494 OOOOOa56 >b700 STA PAGI
::'495 00000a58 >b700 STA PAGE
:496 00000a5a >b600 LDA PT
:497 OCOOJa5e >b70~ STA PAGI+1
1498 00000a5e >b600 LDA PU
1499 00000a68 >b702 STA PAGI+2
:500 80008.162 >b6DO LOA ACC
:50: ;;0000.164 >b700 STA WACC
:502 0000Ja66 >edOOOO JSR UP
:503 00008.169 >ecOOOC JMP GLP2
:5J4 0::OOOa6c >b60~ IPNF LDA IOBUF+l
:525 00COOa6e .1110 CMF +SID
:526 20200a'(: 2502 BLO P8300K

..
:527 2COCCa'2 >lcOO BSET 6,STAT2
::. 5 ~ 8 J::CCOa74 a63::' P8300K LDA t$31 REQUEST
:529 :::COOa76 >b700 STA PH PAGE 100
:5:8 CCCCOa78 DECA IN CASE
:5:: C2000a79 >b700 STA PT INITIAL PAGE
:5:2 COOOOa'o >b'00 STA PU NOT FOUND
:5:3 ::::::.1'0. 2Cd5 BRA GETIND
:5:4
:5:5 .*,,* •••• * ... ** ... **** •••••• ***.***.*** •••••• ** .. ****.**** ...
:5:6
: 5_ ~

:5:8
:5:9
Row
" transient.

........ ** ... * ...... * ..... ******** •••••• ** •• ****** ....... ** .. **

:52:
:52: :: :: : a ~!" .1604 R24T LOA to
:522 :::::as: >0'88 STA R' CHAPTER
•
••,
:523 :: ~ ~: a S::
:524
: 52 ~
:::::a84
:::::.186
"
::>)::100
a6eb
LSLA
STA
LDA
R10
#$OB
BOX ON AT

:526 :::::.188 n:7CO STA Rll

:5r ::::: .. 8.1 ::>0700
:528
:529
:::;::a8::::
:::::a8e
a6:8
>b'7:;:
STA
LDA
STA ".
PH

R9
ROW
"
:53: : ::::a9: a6:6 LDA
••
·
:53: ::::;:a92 >Co.COO:: JSR TXT32 WRITE BOX ON
:532
:53::
:::::a95
:;:;:; :;: .. 9 ~
a 6: ~
::>0700
LDA
STA
"1
R10
BOX OFF AT 31 32
:5J4 ::::::a99 a6ea LDA t$OA
:535 :::::a9:::: >::::7:: STA Rll
:536 :::::.190. >07:: STA PH
: 53 ~
:538
:::::a9!"
:::::aa:
a606
::>caCCO::
LDA
JSR ••
TXT32 WRITE BOX OFF
:539
:54.:
:SC
:::::.1.14
:::::aa6
:::::aa8
a6:4
>b7'JC
>07::: EA
LDA
STA
STA
.,
020

R10
START READING
• COLUMN 20

:542 :::::a .. a a6:7 RO. - PACKET 8/30

:543
: 5 <'0 ~
:::::aa::::
:;::: :.1.1 ~
>::::c.::e:::
>06::
LDA
JSR
LDA
I"
R2B
IOBUF+l
"
:545 ::::: ::::: .. a<'o7!" AND t$7F
:546 : : : : : .. ::::3 >:::7:: STA Rll
:50 : : : : : .. ::::5 ::>060: LDA IOBUF
:sa : : : : : .. ::7 .. 47: AND t$7F
:549 :. ::::ao<;, >07:; ~ STA PH
:55: :::::aoo ;:.06C: LDA W,
:55: :::::aod a:'Ja SUB flO START WRITING AT COLUMN 10
:552 :::::ao~ ::>070C STA R10
:553 ::::::ac: .. 6:8 WRITE TO ROW
:554
:SS5
0::::C .. c3 >::::dO~CC
:C:S::a:::6 >}cOO
LDA
JSR
1NC
I"
.,
.2B "
:556
:557
:558
~ ~ -:: ') o a:::: 8 >3e'JO
')~CG'jaca >06')0
C;~CO:acc .1:27
INC
LDA
CMF
.,
W'

"9 ALL DONE ?

l559 OOC:')ace 23d8 BLS EA
:56(, OO'),)Oad.,) 0: NOTR RTS
~ 5 6:
:562 OOOOOad: >edO~SC START2 JSR TXTOF
~ 563 CCCCCad4 a6:4 LDA 120
:564 OCOOOad6 >edOOC'J JSR TPAU2
:565 QOOOOad9 a60e NIICD LDA t$OC
:566 OOOCOadc >b700 STA R'
:567
1568
OOOOOadd
OOCOOaeO
>edOOOO
.1606
JSR
LDA
TX!3
I.
CLEAR CHAPTER
•
1569 OOOOOae2 >cdOOOO JSR TPAU2
1570 OOOOQae5 ::>cdOQOO INITXT 'SR GIP GET PAGE No. FROM 8/30

54
 1512
1513
151. 1ft up ... I. tranl1.,.t.
1515
151'
1511
1511 00000••1 :>ocDOZl I1124T .AT 6,IITATI,IIOTXTI
1519 OoOOOa.b :>t.00 . . .T 5,STAT

.."••.
1510 00000.... U eLM
1511
1512
0000011_
oaoooan
:>CdOooO
:>1100
•••
IcLO
UP
3,.3
ACe •
STOP IT
15.3 OOOOOa(3 aID. LOA • lIT'"
lSI.
lS.5
151'
ooOOoats
oooooarl
aoooaara
>ed0000
a60.
:>bl0D
•••
LOA
• TA
...
1511 ODDDOafe .'DI LOA
15 ••
Ult
OOODO.f.
oaoaObOD
)ob100
:>b100
.TA
.,••
... .
.TA
••••
-
Uta 00000b02 a". LOA PUT 14 AT TOP UU FOR CURSOJU
1 Itl
Ut2
OOOOObO.
oaOOObOl
:>b100
:>cdOOOO
• TA ••TIT'
15t3 OODDOblt _'01 LOA
1St. OOOOObOb :>b100 .TA
Ut5 aoaOObOd :>1100 IIOTXTX U&T ' ,STAT
Uti OaOOabaf .1 OT.
lS51
Uti
un
1100
1'01
......................................................... .
1602 Tabl.. fDr IIBX-AlCll ccmM,.alcm, ·STOP-
1'03 and "_11141 Hcode.
1'04
1605
1101 _ FCC
1101 00000bl0 3031323334353531 ·OU3.5111IA8CDB"-
160. 00000bZ1 ObOb5UUnOOaOa LHOLD
_ rca
rca "8,108,IU, nt, IU, ISO, IDA. lOA
160t OOOOOb2t 1502.".'4133'2f 115,102. '4', '5£, "", ,13, '31, S2r
1610 OOOOOb31 dOel,elbal . . f.a lIMe rca IDO, lel. "e, IN,lAl, '.,IFD. llA
1611
1512 DID

• !WI
...,.,
.., ... . , ,.
.1WI2
.R0M2 'n
ABAV
,n .",
. . ... ... ...••• ..
261

... ... ...

ABC '16

.•••.,'I' u•••
ABC' ·'23
ABO "14'
AIOIIT . .I ·SOI

....., .
ACe 10' 17. 111 ••• .., "" • 17 231 .17
'" "0
AD.A ...,., ,
•U
1153 1112 1111
1120
11K un ." ""
••• 111. 1325 1500
.16 .n .11 1053 1101 1125

ALeC
ARAr
ARAL ..,
..,
·353

... ...
AVOL

-
BCOL
aLARK • Ol • St•

....,.,., . , ...
_.or
lOT

_.00 1003
·"1
1001 ·100'

... ...,. , ..".. .....

22 ·1007
22 ·lOot 1051

...
BA'L

"""" ...,..,., u. 11'7,

...
CI 1011
C' 161 '13 .n ••• 10" 11"
C'C'C. ...,., "" lOto

....,.,.,... ... ...

12.'
10'1 121' 1211
10'• 123' 1242
C6 lOll UOC 1207
CARD ·UI
CASI
CAS'
CAS'
CAS'
CAS.
..,
....,.,.,
......,.,.,.,.,
CAS'
CAS'
CAS'
ceRl
CCR2
ceA'
ceo.
ce.. ..,
..,
CCR6
CCRl
ceo'
C",
.,.,.
'27
USt
crN.
CGET2i
CHAN
CHCK1
..,...
12 .. 0

CHCK2 ·510
CarRD 133'

..
CHRr 1345 13'0 ·1402
eLI.1t
CLeCK
CLRI"
CNT ..,".71121 , .u

55
 Symbol eroaa-re!erence
CNTl '27
CN!3 '27
CN!4 '27
CNT5 '27
COK -239
COR 367 -369
COUNT '27 312 320 32S 332 33' 341 3.2 349 ,.3
CPBLF 613 -945
CTAB 1337 1366 -1432
CYAN 17 -261
CYOK -297
DDI -574
DECODE 372 375 .0. .07 572 0.0 -700
DlFFH '27
DlFFL '27
DIGIT 103 -lOS
DlGlTO 17 -103
DIGITS 10. -1023
DISC '27
DISP '27
DISP4 . .3 -898
DISP8 8'7 -890
DPGN 128 -130
DPN'I' '27
DRAM '27
EA -1541 1559
END26 1266 1373 -1409
EXAD 1310 -1447
EXP '07 -973
EXPTB 18 -967
FII 758 700 -761
FINI
FND
FND2
"0
721
542
".
730
-548
-543
739 75' 703 772 711 785 -787

FNDJ 70. 712 -730

FOI 74. 751 -752
FRO .. 8 -142 "0
FTUNE '27
G23F 1394 -1398
G2BIT 1311 -1388
G2TAB 1390 1398 -1417
G32F 1381 -1385
G3BIT -1375
G3TAB 1377 1385 -1429
GC'tI 330 -665
GET25 21 -1196
GET26 1244 -1253
GETIND -1493 1513
GETIT -15a
GIP 18 259 -1468 1570
GLOK 2.09 -215
GLP::' 323 -365 .07 672
GLP2 352 -471 00. 074 1503
GOTCH 1367 1386 1399 -1403
GREEN 17 -208
GTT 1352 -1363
HI 38. -388
HAM 702 71. 723 732 747 "0 70S 774 -1609
HAM8 -1610

H:rGH 952 -954 977

HOLD 19 -a58
HUN 1044 -1048
HVL '27
HVR '27
lAC 258 2.0 -269
IGO 215 -217
IGI 221 -223
IG2 262 -264
-256
INDEX
INDX
INDXP
"
100
201
-179
211
281
319
379
-618
'2' 018 931 1141 1172

lNITxr 19 -1570
IOBur '27 371 37. 384 390 39' 403 '00 .71 573 59. 597 0" 689'· 952 1203
1208 1215 1220 1236 1269 1294 1296 1303 1485 1504 1544 1547
IPNF 1479 -1504
IRCMCT '27
IRCNT '27
IRCOOE '27
IRH '27
IRL '27
IRRAI '27
IRRA2 '27
lRRA3 '27
IRRA4 '27
Kl '27
K2 '27
KEY '27
KOUNT '27
LBAL '27
LOO
LHOLO
LIFO
..,
-113

'27
901 903
020
90.
1254
-1608
1256 1260 1262 1263 1267 1210 1272 1277 1278 1279·. 1281 1292
'18
1295 1297 1298 1299 1304 1305 1309 1311 1320 1323 1327 1330 1331 1336 1338 1347
1349 1362 1364 1369 1375 1380 1388 1393 1401 1402 1447 1448 1449 1450 1451 1452
1453 1454 1455 1456 1457 1458 1459
LIND '27
LINK 21 -309
LLOOP -341 355
LLOP -320 33.
LOK 50s -soa
LOQP26 -1256 1211 1290
LOOP62 -1274 1321 1379 1392 1407
LOOPS -530 '.0
LPT 203 200 213 218 -224
LPT2 159 -206
LVL '27
LVR '27

56
 Symbol cross-reference
MATRIX
MIX
MRE
""
I.
*584
*800
603
HEXTC 327 *329
NIlCD *1565
N01 1458 *1460
H016 1450 *1452
N02 1456 *1458
N032 1448 *1450
NO. 1454 *1456
NO. 1452 *1454

NOBX
NOCH
HOHOLD
'"
11.
2'0
005
116
05.
.87
*118
*915
*1001 1073

NOMIX 000 *812

NOTCI!' 1354 *1358
NOTD 1330 *1369
NOTf'ND 32. *328
NOTHLD 23. *241
NOTOK 36. *424
NOTOK2 212 *446
NOTOK3 202 *423
NOTR *1560
NOTROW 1314 *1323
NOTT
NOTTH
.6
22 •••• "SO
61 *411
NOTXTX 1578 *1595
NOV9 .32 .3. *442 .5. .61
NOV9A *441 .63
NPAGE 10 ~201
NPK27 68. *692
NTSAC 232 *235
NULD 1333 *1401
NUM 787 *1601
NXTCH 12B4 *1292
OKO 38' 387 ~389
OK1 3'0 3.3 *395
OK2
OKROW
3'5
1265
3 ••
*1267
*400
•••
OLDIR "27
aNI 716 71' *719
OSDL "27
OSDLE: "2' .0 63
OUT '6' ,66 .70 '72 *975
OUTSP 236 1137 *1161
PI300K 1506 *150B
PAGO "27 77 .2 87 16, 16. 167 271 27. 277 283 285 287 300 .25 •• 7
.01
1180
••• ..6 53. 537 5.0 61. 621 '32 ,37 "0 1142 1144 1146 1173 1177

PAGI "27
PAG2 "27
PAG3 "27
PAGC
PAGE:
"27
"27 .2 11. 125 126 137 13.
.57
,., I •• 161 163 166 16' '27 430 435

.,
.36 .37 .41 442 44. • 52 .5 • 45. 620 622 1039 1047 1048 1049 1060
1062 1064 1066 1074 1076 10B5 1087 10B9 1091 1093 1095 109B 1123 1143 1145 1147

PAGI
PANIC
PDP
1495
"27
38
"27
1471
1494
58
113
1497
7,
127
1499
01
12.
84
145
.6

'"
••
200 238
" ..
"0 05. 1026 1050 1052 1070 1140 1169

PH
""
'48
1490
138
485
1493
150
517
1509
278
535
1527
282
5.2
1536
301
5 ••
1549
385
6"
386
'02
388
.3.
3.,
1010
3'2
1063
3 ••
1077
3.6
1107
3'7
1111
3 ••
1150
426
1174

PLLHI
PLLL ""
*626 630
PLLOW
PPAGE ""
10 *211
PROG
PSHL ""
*517 520

.04
PT

PT1
"" 140 275 28. 376 '00 443 .82 538 .38 1065 1151 1178 1496 1511

3" *394
.34 47, ."
PU
PU1
""
1181
396
142
1498
*399
272
1512
286 378 • 05 42 • '51 .56 5" .06 1067 ~: 52

PULL 346 *625

PUSH 328 *516
PWR
""
01
010 ""
""
6.6
1285
42
13'
845
1300
66
295
89.
1328
003
322
920
1482
...
01.
365

1488
.99
1001
1524
56.
1004
1533
'6'
1007
1541
583
1059
1552
609
1157
644
1185
645
1200
646
1212
666
1232
671
1261
680
1280

011
""
1287
136
1403
292
1526
493
1535
591
1546
596 605 615 84' 900 .22 1009 1061 1075 1149 11'1

02
R24T
02B
""
22
21
189
*1521
370
.71
402 '88 *650 6" 1202 1214 1234 1268 1293 1484
R2BJ1 *383 .09
R2BJ2 *402 1492
RlBN'9 570 *651 1301
.00
03
R4
os
""
""
105
55
171
130
280
172
413
24. '82
.72
1011
"6
1586
1100 1124 1176 1582

06 ""
""
51
53
70
71
007
00.
81G
01.
995
99G
15B8
1589

O.
07
""
""
72
131
832
289
.62
311
.G3
49G
'6' .67
58G
• G.
600
.6 •
670
971
.47
973
.62
97. 992 1591

O. 1154 11B7 1197 1259 1276 '"

1326 1475 1522 1566
'6,

.10
.17 946 1012 1054

""
1324
132
1529
293 .97 607 641 6SO 843 '6. .71 '91 1013 1056 1155 1183

RAD1
RAD2 ""
""
RAD3
RAD' ""
""
RAD'
RADG ""
""
RAD7
RAD'
RADIO
""
""
383 389 *568

57
 Syl'!lbol cross-reference

..
READ '2' 663
READ22 -661
RED
RE::l2
RELl
,
17
411
"198
"205
'23 ·929
RE:2 '24 "934.
REV '62 "965
REVEAL 18 "962
ROWl '27
Row24 21 ·583
RS7 '6'
RS7R 237 1161 "1168
RW24 1313 "1318
SA., *558 '62
SSO 1071 *1129
S:O *1026
·1564
SE: 776 778 *779
SEN 1046 *1049
SEND '2' 1121

SEND22 6'6 83. '88 *1119

s:::-r: ~ 1 085
SFND 176 300 513 *605 .26 1105
SFND2 -606 616
SHADMAT '27
s:: 767 76. "770
S!.;:? :317 *1320
S!<OSP
S:RPC:
s~3
'"
:041
:222
"237
*1052
"1226
SM4 ~217 "1220
SM' 1205 *1208
SS::.~ '27
SOCH :031 *:033
SOR:: :029 1034 1036 "1038
'27
"
SPGN
SP."!
1051
75
"1053
10. • 15 .2' 87 • *884 1128 1473 1584
SPM2
SR24:
5RC:i
,.
877

:58
*883
*1578
400 *529
SS:;9 711 720 72. 73. 753 762 771 780 *790
S:}l.C!< '27
STAR:2 :9 *1562

..
S:A7 '27 37 39 43 '6 47 48 60 62 6. 67 6. 103 110 17. 233
.15 .78 .0<
..
235 23. 247 26. 2.7 .23 446 .27 85. .60 .65 877 .80
.85 1104 1137 1138 1164 1168 1468 1469 IS79 1595
S:A72
S:A':'3
S7AT4
'27
'27
'27
,
44 45
20. 216
800
220
801
222
812
261
1198
263
1206
36.
1218
593
1223
679
1241
6.,
1470 1507 1578

S:A75 '27
S:A76 '27
57A:7 '27 .77
s:MR
S7RM
1391
1378
38
*1393
*1380
" 122' 1228 1229 1230

S:;9: '27 886 887

5:"92 '27 70. 707 710 717 72. 72. 72. 733 73. 735

S:;B3
737
77'
'27
74.
790
652
74.
.37
70'
750
.38
1116
752
1209
1117
71'
757
1235
71'
75'
1231
".
1238
71'
761
72'
766 767 768 770 77. 776 777

'55
S::S/CR "27 660
S:;9?G .79 *1131
7AC .80 *998
7EN 124 *126
:"ES:- "77 228 257 26.
7H: 734 736 -737
THe;; :027 *1030
::M.E *977
:Jo.'.P!
TMP2
"
'27
'27
7MR '27 '30 99. 1594
7N23 *1390 1391
7N32 *1377 1384
:ONE. "27
TPAU2
:PS'!?
"24
1023
'10
*1123
1481
1139
1564 1569

:R5 1236 *1238

7RA *702 78'
:RAN: 14. 299 *821 1069 1159 1166

7RAN2 810 81. -823

7RAN3
:RF:
"
*827
*756
.75
'27

7RFC ·747
7RNCH *1337 1344
IRON *714
:RSE ·774
':'RSI *765
7RTH *732
:R:W "723
7R'fAG *1478 1486
TRZE *706
':"VTX 18 '37
TW! 725 727 -729
':'X!l 17. J01 *977 .43 1103 1165
TXTlL 51' *878
TXT2 21
,OS 73 248 -934 97' •• 3 .97 1592
TX!3 .07 1069 1109 *1113 1158 1567
TXT32 611 643 850 1015 *1114 1406 1531 1538
TxT3-S 143 298 *1107
TXTOr- "64 1562 '" ." 1188
TXTOFF
TXTOH
UCHOLD
37
"38
*868
60

983
'"
uae 1356 *1362
UP 107 173 *185 290 351 863 870 930 1102 1126 1163 1502 1581
UPDATE. 18
'"

58
 Symbol cross-reference

.,
.2
*648
'27
'27
'50
111
700
373
703
377
791
1024
.35 1114

.29 602 *641 1289 1554

.3 '27 22. 226 230 243 314 321 329 331 '90 89. 1477 1478 1540 1550 1555
1556 1557
'27 337 347 .9. 529 530 532 543 544 548 558 1501
'27
YELLOW 17 *220
YIP *183
ZE1 707 709 *710

59
60
 AN460
An RDS Decoder using the MC68HC05EO
Peter Topping,
MCU Applications Group,
Motorola Ltd., East Kilbride

INTRODUCTION

The Radio Data System (RDS) adds a digital data capability to the FM VHF transmissions on band II (87.5
to 108 MHz). This capability is in use in the UK and several other European countries, the intention being
that most of western Europe will eventually adopt it. The specification is defined in EBU Technical
Document 3244 (see reference 1).

To transmit the data, a sub carrier is added at 57 KHz. This sub carrier is amplitude modulated with a shaped
bi-phase coded signal. The sub carrier itself is suppressed to avoid data modulated cross-talk in phase-
locked loop stereo decoders and to maintain compatibility with the German ARI system which uses the'
same sub carrier frequency. Information is sent in groups of four 26-bit blocks. Each group of 104 bits is
one of several types containing different information. It is up to the broadcaster which features are
transmitted. The only constraints are that the specified format must be adhered to and that PI, PTY and TP
should always be included. Each group contains a different sub-set of the RDS features; table1 lists all
currently defined RDS features.

Table 1. RDS features

Feature Information
PI Program identification
PTY Program type
PS Program service name
RT Radiotext
CT Clock time and date
AF Alternative frequencies
TA Traffic announcement
TP Traffic program
MS Music/speech switch
DI Decoder identification
PIN Programme item number
EON Enhanced other networks
TDC Transparent data channel
INH In-house data

The retrieval of data is carried out by a demodulator circuit which generates clock and data signals that can
be used by a microprocessor. Suitable demodulators which can perform this function include SAA7579T,
TDA7330, LA2231 and RDS hybrids. The block diagram of a typical application is shown in figure 1. The
microprocessor, in this case an MC68HC05EO, decodes the RDS data using the clock and data signals from
one of these demodulators and sends selected data to dot-matrix display modules.

61
 Data
MPX
FM tuner RDS demodulator Clock

Audio amp.

Figure 1. Typical application

This application incorporates an alarm clock which. if permanently powered. can be used to switch on the
radio supplying the RDS data. at the required alarm time. There is a second alarm output intended to sound
an alarm. This output is cancelled when any key is pressed. leaving the control output active. The control
output could be used to switch the power supply of the radio or the audio stage. If an audio mute is used.
RDS information can be updated even when the radio is "off". Alternatively the decoder can be used simply
to display RDS data with its power being supplied from the radio and manually switched on and off.

RDS FEATURES

This application supports PI. PTY. PS. RT. CT. TP. TA. MS. DI. PIN and EON (see table 1). These features
facilitate permanent display of the a-digit station name (PS) and time (CT) and. on request. can display
program type (PTY). radiotext data (RT) and the status of the other RDS features. EON data can be
displayed. but the retuning features associated with AF and EON are not supported as there is no capability
to control the tuned frequency. In a car radio EON data would be used to switch the radio to a station which
is broadcasting local traffic information and AF data to tune the radio to the strongest signal carrying the
selected service.

PI is a two byte number which identifies the country. coverage area and service. It can be used by the
control microprocessor but is not normally intended for display. A change in PI code causes the initialisation
of all RDS data as it indicates that the radio has been retuned. This application also facilitates the display of
the current PI code.

PTY is a 5-bit number which indicates the current program type. At present 16 of these types are defined.
Examples include "no programme type". "Current affairs" and "Pop music". although the actual syntax
which is displayed is determined by the software of the controlling microprocessor. In this example PTY
can be displayed on request. Table 2 shows the display used for each PTY code.

PS is the eight character name of the station and is permanently displayed (except in the standby mode).

RT is radiotext and constitutes a string of up to 64 characters which give additional information regarding
the service or programme currently being transmitted. In this application. RT is displayed on request on the
16-digit dot-matrix displays using scrolling.

62
 Table 2. PTY Types

PTY Display
0 No program type
1 News
2 Current affairs
3 Information
4 Sport
5 Education
6 Drama
7 Culture
8 Science
9 Varied
10 Pop music
11 Rock music
12 Easy listening
13 Light classics
14 Serious classics
15 Other music
16-31 No program type

The data often contains extra spaces to centre the text on a 2x32 character display. As this is not suitable
for a 16-character scrolling display the software reduces all sequences of two or more spaces to a single
space.

CT data is transmitted every minute on the minute and provides a very accurate clock, traceable to national
standards. The (Modified Julian) date and local time variation are also transmitted. Time is permanently
displayed. In standby mode (see below) the date is displayed instead of the PS name. The MJD number,
which is the form in which the date is received. can also be displayed. The microprocessor converts this
number into day-of-week, day-of-month, month and year.

AF would be used by a car radio to retune to the strongest signal carrying the selected service. AF data,
along with TDC and INH, is not used in this application.

TA and TP are flags. TP is set if the transmitter normally carries traffic information and TA is set if a traffic
announcement is in progress. The combination, TA=1 and TP=O, is used to indicate that EON data is being
used to supply information on other networks including traffic announcements. The status of these flags
can be displayed and the combination, TA= TP= 1, is brought out to a pin and can be used to control a LED
or external hardware. An example of this could be to demute the radio or switch from cassette when a
traffic announcement is taking place.

MS is a single bit indicating either music or speech and is intended to be used to make a tone or volume
adjustment to a radio's audio stage. The MS bit is displayed on request.

Decoder information (01) constitutes four bits indicating the type of transmission (mono, stereo, binaural,
etc.). It is not currently in use in the UK but can be displayed as a number between 0 and 15.

Programme item number or PIN is used to identify the programme currently being broadcast. The format
is a 2-byte number which includes the scheduled time and date (day-of-month) of the start of the
programme. It can be displayed as four hexadecimal digits or fully decoded to day-of-month and time.

63
EON (Enhanced Other Networks) replaces the older ON format. If type 14 groups are used to provide EON
data then type 3 groups (ON) will not be used (table 6 shows the currently defined group types). Type 14A
groups are used to send information about other networks. The PS name and principal frequency of up to
11 other networks can be displayed. Type 14B groups are intended to be used to switch to traffic
announcements in a radio in which the microprocessor can control the tuned frequency.

DECODING
Each 26-bit block contains 16 bits of data and 10 extra bits which are used for synchronisation and error
detection. There are no gaps between blocks or groups, the synchronisation being done by looking for
specific checkwords in the incoming data. In order to look for a checkword a stream of 26 consecutive data
bits has to be multiplied by the fixed 10x26 matrix shown in figure 2.

The result of this multiplication is a 1O-bit word which is compared with allowed values. There are 5 of these
1O-bit "syndromes", one for each of the blocks 1, 2 and 4 and two for block 3 (see table 3). The alternative
syndrome for block 3 is used in the B version of a group. In this version the PI code is sent in block 3,
replacing what would be sent in the A version of the same group type. This is done to increase the
frequency of sending the PI code so that it can be acquired more quickly.

10 0000 0000 ($02,$00)

01 0000 0000 ($01,$00)
00 1000 0000 ($00,$80)
00 0100 0000 ($00,$40)
00 0010 0000 ($00,$20)
00 0001 0000 ($00,$10)
00 0000 1000 ($00,$08)
00 0000 0100 ($00,$04)
00 0000 0010 ($00,$02)
00 0000 0001 ($00,$01)
10 1101 1100 ($02,$DC)
01 0110 1110 ($01,$6E)
00 1011 0111 ($00,$B7)
10 1000 0111 ($02,$87)
11 1001 1111 ($03,$9F)
11 0001 0011 ($03,$13)
11 0101 0101 ($03,$55)
11 0111 0110 ($03,$76)
01 1011 1011 ($Ol,$BB)
10 0000 0001 ($02,$01)
11 1101 1100 ($03,$DC)
01 1110 1110 ($Ol,$EE)
00 1111 0111 ($00,$F7)
10 1010 0111 ($02,$A7)
11 1000 1111 ($03,$8F)
11 0001 1011 ($03,$lB)

Figure 2, 10x26 decoding matrix

64
 Table 3. Syndromes

Block Syndrome Binary Hex

1 A 11 1101 1000 $03,$D8
2 B 11 1101 0100 $03,$D4
3 C 10 0101 1100 $02,$5C
C' 11 1100 1100 $03,$CC
4 D 01 0101 1000 $01,$58

This syndrome test has to take place after each bit is received. The test inspects the last 26 bits received,
until a valid syndrome is found. In this application, only syndrome A is accepted during the bit-by-bit
syndrome check and the data is used only after four valid syndromes have been acquired. A more complex
algorithm could allow all syndromes to be accepted during initial synchronisation and require less than four
valid syndromes before the data is used. This can reduce the time taken to acquire the PI code, which is
also included in block 3 of type B groups, but increases the likelihood that random data, giving a valid
syndrome, will be used in error. The bit rate is 1187.5 Hz so the control microprocessor has a lot to do
during this initial synchronisation. Once the first valid syndrome has been found, subsequent syndrome
checks need be done only after the next 26 bits have been received, as this is when the next valid
syndrome would be expected. If it is not found, then the bit-by-bit synchronisation check is re-started. Once
consecutive A, B, C (or C') and D syndromes have been detected, a complete group has been acquired and -
the data can be used.

Four bits in block 2 determine the group type. Block 2 also contains TP and PTY data. The use of the other
bits in blocks 2, 3 and 4 depends upon the group type while block 1 always contains the PI code. Table 7
shows the structures of the group types which are handled in this application.

CIRCUIT

Figure 3 shows the circuit diagram. As different demodulator devices can be used, the circuitry for the
demodulator is not shown. The clock from the demodulator interrupts the microprocessor on each positive
edge. At this time a data bit is available and is read on bit 2 of port B. Both an LCD and a VFD module are
shown but normally only one will be used. If the LCD module is not connected, a pull-down resistor should
be connected to bit 7 of port C. as the microprocessor uses this bit to check that the controller in the
module is ready to receive a command. If this bit is left open circuit, it may cause the software to hang up.
Alternatively the LCD drive software could be removed, allowing the use of port C for other purposes.

With more I/O available, additions to the software would allow access to the other control bits intended for
controlling external hardware. These include the MS bit, DI data (4 bits) and PIN (match with current time
and date). They could be brought out to port pins in a manner similar to that used for the TA= TP= 1 signal.
The unused port A and D pins could also be used for this purpose but in this application they were used
during debug by the EOBUG monitor (reference 2). The application could make use of the port A and D pins,
if debugging was done on a development system which did not have this limitation.

65
 fN

L C
LCD Module

r .--- 0 VFD Module

00 07 RS R/W E - E
fN
O.I~F ~ lLL Iv,1
lOOk 191 541 3
+122~F 2B~
~ 35
PCO PC7
3B 39 40 20 21 23

~
Vdd Vdd TS P02 P03 P04 Peo PSI PS3
B Vdd
Reset 45 20 CE
CSROM
I~F~
A12
63 2
A12
PGM eE-
RDS
C 7 INT 65 23 Vpp ~
All All
O.l~F
Demodulator 64
"'II 0 22 PB2 Al0 21 Al0 2
is" A9 66 24 A9
7
c fN C
~ 25 6

.:~
AS 67
AS
~ 4
62 3
n A7
m ~.
:~
(J) C
;:j:
0-
68
P05
MC68HC05EOFN
I: :~
AD

07
ar OE

~
:V////h
53 11
00 v••
3 0% Off
RDS
(+)
27 PB7 fN

~J
Alarm
Sleep
H
26
PB6
PEO 41
PEl 42
2xl00k
q, Sleep at Alam
Alarm Enobk
25 PB5 43
PE2 Alarm Outptl
24 PB4
PE3 9 Am< on OUlp'

1 2x 10k
Vss Vss Test OSC2
10 44 4 5
OSCI
6 35
PC7 PAO PA7 POO POI
11 ~ 836 37
P06 P07
1 2
10M >--C:J- ~
-In. lOOk ~
22p:: = 1'"1 ;;ff lOp ~
r 4.194MHz ~
NOT USED (SEE TEXTI
 SOFTWARE

The complete software is listed. The reset routine (START) sets up the I/O ports including the enabling of
some of the special functions available on port D. These signals (A 15, A 14, RNJ and the P02 clock) were
used during debug. The pins are not used in the final application. This also applies to all the port A pins which
are configured as outputs. External interrupts are enabled on positive edges so that the RDS clock can
interrupt the microprocessor when each data bit is available. Timer B runs as a real-time clock with interrupts
every 125 ms. Correct operation of this clock in the absence of an RDS signal requires that a 4.194 MHz
crystal be used (the trimmer on pin 6 should be adjusted for accurate timekeeping). Timer A's pre-scaler is
set up to divide by 64; this causes the idle loop to cycle at 64Hz. The reset routine also initialises the LCD
module (the display shows Mon 0 inv 00:00 until a valid group 4A is received). clears the RAM and calls a
subroutine (lNITD) to initialise the RAM locations used for displaying data.

Lines 114-118 and 193-208 are commented out as they are only relevant when de-bugging using the
EOBUG monitor (reference 2).

The idle loop (IDLE) regularly checks the local keyboard for a keypress, compares the current time with the
alarm time and performs other time-dependent functions related to the display modules and the sleep timer.

The keyboard software (KBD) scans the 4-key matrix for a keypress every 16ms. If the same key is held
pressed for 3 successive scans, it acts on this key function by calling the relevant subroutine (ALARM, .
ONOFF, SLEEP or RDS). This software also controls the repeat rate of the SLEEP and RDS keys. This rate
is set at 6Hz (after an initial 750ms delay) when the keys are used to change the alarm time and 1 Hz for
their normal function. The other keys do not repeat if held down. Table 4 shows the functions available in
each mode.

Table 4. Key functions

KEY
MODE
On/Off Sleep Alarm RDS

Standby (Off) mode normal (On) -

mode alarm
RT
PTY
Normal (On)
PI
mode stndby (Off) TA/TP
mode sleep (On)
PIN(h)
PIN(d)
Alarm OFF mode alarm ON
MJD
MS/DI
EON 1
Alarm ON mode alarm set-up
EON 11
mode alarm OFF

Alarm SET UP toggle hr/min dec. hr/min inc. hr/min

67
The On/Off key uses the subroutine ONOFF to toggle between ON and standby. A port pin (3,PORTE) can
be used to control the power to the VHF radio and/or other external hardware. In standby rnode, with the
alarm disabled, the time and date are displayed. If the alarm is enabled, the alarm time is displayed. In the
ON mode the time is displayed along with the current RDS PS-name. Table 5 shows these display formats.

Table 5. Display formats

Display mode Format

Standby Alarm off Thu 30 Apr 18:05
(Off) Alarm off, no CT Mon o inv 0:00
Alarm on 0659 ALARM 18:05
Normal With RDS PS name BBC R4 18:05
(On) Without RDS -------- 18:05
Alarm Alarm off Alarm - OFF
Alarm on Alarm - 6:59
Sleep sleep 60 min.
RDS RT BBC Radio 4 .. ,.
PTY News
PI PI code - C204
TA&TP TP - 0 TA - 1
PIN(hex) PIN no. - F480
PIN(decod) 30th at 18:00
MJD MJ day - 48742
MS&DI MIS M DI 15
EON 1 BBC R3 92.10
2 BBC R.Sc 103.60
3 BBC Nwcl 96.00
4 BBC Scot 94.30
5 BBC Mtme 92.50
6 BBC Twed 93.50
7 BBC R5 909kHz
8 BBC Eng. 100.00
9 BBC R1 99.50
10 BBC R2 89.90
11 --------

The Alarm key calls the subroutine ALARM which displays the current alarm status. A second press
changes the alarm armed status. When the alarm is armed, the alarm time is displayed. In this mode the
On/Off key can be used to select either hours or minutes (indicated by flashing) and the Sleep and RDS
keys used to increment and decrement the settings. If the alarm has triggered then the first press of any
key cancels it. The alarm display has one of the two alarm formats shown in table 5 according to whether
or not the alarm is armed. As all the keys have a special function in the alarm mode the only way to exit
this mode is to wait for a timeout. If no keys are pressed for 5 seconds, the mode returns to normal.

The Sleep key controls the sleep timer. If the decoder is in the standby mode the first press of Sleep
switches it on and initialises the sleep time to 60 minutes. When the sleep timer is running, this is indicated
by a flashing decimal point in the right-most character of the display modules. Subsequent presses of the
Sleep key decrement the time remaining by 5 minutes. When the sleep time has elapsed, the decoder
returns to standby. In the alarm set-up mode this key decrements the alarm time.

68
The RDS key uses subroutine RDS to step through the various RDS data which can be displayed. Holding
down this key steps through the displays at 1Hz. The displays are RT (scrolling). PTY, PI. TNTP, PIN (hex),
PIN (decoded). MJD, MS/DI and EON (11 networks) as shown in table 5. In the alarm set-up mode this key
increments the alarm time.

The timer interrupt routine (TINTB) updates the RT scrolling pointers (DISP1 and DISP2). These pointers are
incremented regularly whether or not an RT display is active. In this way, the software can be easily
converted to using a 2-line LCD module in which the top line is the normal display of PS-name and time and
the lower line a permanent display of scrolling RT. The timer interrupt also decrements the sleep timer and
updates the RAM locations used to store hours, minutes, seconds and eighth-seconds. All RDS data
(except date and time) is cleared by this routine if no valid RDS data is detected for a period of 10 seconds.

SYNDROME AND CONFIDENCE

Hardware interrupts are vectored to jump to SDATA where serial data is received from the RDS
demodulator. The clock edge causes an interrupt and the first instruction reads the data into the carry bit
of the condition code register. The bit is shifted into a 4-byte RAM register and the matrix multiplication
performed. The state of flag O,STAT2, determines if the multiplication is to take place after every bit or only
after all 26 bits have arrived. The multiplication is performed using two EOR instructions for every bit (two
are required as the 1O-bit syndrome requires two bytes). As the top of the matrix (see figure 2) is the unity
matrix, the first 10 bits are transferred directly into the syndrome RAM locations (SYN). This, the omission
of any EOR #$00 instructions, the reordering of the bits and the use of the index register for temporary
storage help to reduce the length of inline code in this routine. The routine could be shortened by using a
loop but this would incur an unacceptable penalty in execution time. Microprocessors with two
accumulators would find this task a lot simpler and quicker but an MC68HC05EO, at half its maximum
speed, can easily perform the calculation in the required time.

After the multiplication has been performed the resultant 1Q-bit number is compared with the allowed
syndromes (see table 3). The variable LEV records the current block level. It is initially zero but incremented
each time a valid syndrome is found. When it is zero only syndrome A is accepted, if this is found then
syndrome B is expected 26 bits later so when LEV is one only syndrome B is accepted. If an invalid
syndrome is found LEV is cleared, the syndrome confioence level CONF is decremented and the interrupt
ended.

When a valid syndrome is found, CONF in increased by 4 and the 16 data bits saved in the relevant bytes
of TMPGRP. If the valid syndrome is type D then a complete group has been received and all 8 bytes are
transferred to the 8 RAM locations at GROUP. This double buffer means that the data in GROUP can be
used while interrupts are overwriting TMPGRP with new data.

The confidence level CONF is used to decide what should be done if the data becomes unreliable due to a
poor RF input to the receiver. When the first valid syndrome is found it is initialised to 42. Subsequent valid
syndromes increment it by four and invalid ones decrement it by 1. If CONF falls below 41, then it is
assumed that synchronisation has been lost and a bit-by-bit re-synchronisation is carried out. If it falls below
10, the signal is deemed unacceptable and the displays are re-initialised. The confidence level is not
incremented by the detection of a valid syndrome if it is higher than 56.

69
 GROUPS HANDLED

If a complete group has been received the data can be processed. The buffering used would allow this to
be done outside the interrupt but in this case there is sufficient time to do it within the interrupt. The PI
code is checked to see if it has changed. If it has changed the displays are initialised. In an application using
the AF capability of RDS, more use would be made of the PI code.

Next PTY and TP are updated and the group type identified. Group types OA. DB, lA. 1B, 2A. 4A. l4A and
15B are handled. Table 6 shows the type of information contained in each group and table 7 shows the
detailed structure of the groups actually used.

Table 6, RDS Groups

Group Features
All PI, PTY, TP
0 TA. 01, MS, PS, AF
1 PIN
2 RT
3 ON (replaced by EON)
4A CT
5 TDC
6 INH
14 EON
15B TA. 01, MS

Group 0 & 158

As AF data is not handled, there is no difference in the treatment of groups OA and DB. PS data is extracted
and placed in RAM according to the address bits in block 2 (see table 7). TA, 01 and MS data are then read,
01 is sent a single bit at a time and uses the same address bits as the PS name to determine which of the
four bits is being updated. Groups of type 15B also contains all this switching information. They are used
to increase the repetition rate of this data but contain no PS or AF information.

Group 1

Group types 1A and 1B contain the same data except for the repetition of the PI code in type 1B. The PIN
data is recovered and saved in RAM. This is intended for future use to control external hardware, for
example a tape recorder. This would facilitate the unattended recording of a pre-selected program. At
present this application simply allows the display of PIN data both in its raw hexadecimal form and fully
decoded to day-of-month and time. Full use of PI N data would require continuously comparing the PIN day-
of-month and time with the current day-of-month and time enabling an I/O pin to be switched when there
is a match.

Group2A

RT data from blocks 3 and 4 is written to RAM according to the address included in block 2. There are
four address bits and four ASCII encoded bytes giving the possibility of 64 characters. If the Text AlB flag
changes state, the RT area in RAM is cleared, indicating that the message has changed. Group 2B is not
handled as it is rarely, if ever, used.

70
Group 4A

Two of the more complex tasks to be performed are required by the CT calculations for group 4A. These
are for the local time difference and the conversion of the MJD number into a recognisable date.

The broadcast time is Universal Coordinated Time (UTC). effectively the same as GMT. Time differences
from UTC, including summer (daylight saving) time, are sent as an offset of up to +/- 12 hours in half-hour
increments.

The software includes 4-function, 9-digit integral BCD arithmetic which is used to decode the date from the
MJD number using the formulae:
Y' intl(MJD-15078.2)/365.25)
M' int[(MJD-14956.1-int{Y'x365.25})/306001)
Day MJD-14956-int(Y'x365.25) int(M'x30.6001)
If M'=14 or M'=15,
then K=1;
else K=O
Year y'+K
Month M'-1-12K

Group 14A

This group contains EON data. A large amount of information can be sent using this group, and it can take
up to two minutes for all the data to arrive after the radio has been retuned. This application saves the PI
code, PS name and principal frequency of up to 11 networks although more networks, each with many
frequencies, and other data (e.g. PTY(ON). PIN(ON). TA(ON) etc.) may be sent. Table 5 shows the format
of the EON display. All the information shown is real data from the Black Hill transmitter in central Scotland.

Displays

The software drives both a parallel LCD module (based on an HD44780 driver with or without an HD441 00)
and a serial VFD module (based on an MSC7128 driver) io give a choice of display types. The displays show
the same data (within the limitations of their character ROMs).

The display routine (MOD) is executed in the idle loop if flag 3,STAT2 is set. It is set every 125ms by timer
B interrupts. If flag 4,STAT2 is set. the display is initialised, indicating no valid RDS data. The LCD module
is then updated with new data. Each time anything is written to the module, the subroutine WAIT is used
before the write is executed; this checks that the controller In the module is not busy. This is indicated by
a low on bit 7, so bit 7 on port C should have a pull-down resistor to satisfy this condition if an LCD module
is not being used.

71
 Table 7.

Block 1 Block 2 Block 3 Block 4

bit(s) use

15-12: group no.

11 : group type
AF chck
10: TP flag PS name
Group 0 and PI C chck
chck A 9-5: PTY code chck 8
158 code or 0
4: TAflag (PI code in type 08 and 1581 (as block 2 for 158)
C'
3: M/S bit
2: 01 bit
1-0: PS/OI address
15-12: 0001 chck PIN data
11 : group type not used C
PI chck
Group 1 chck A 10: TP flag chck 8 or 15-11 : day-of-month
code
C' 0
9-5: PTY code (PI code In type 18) 10-6: hour
4-0: not used 5-0: minute
15-12: 0010
11: 0
RT
~ PI 10: TP flag chck
RT
chck
Group 2A chck A chck 8
code 9-5: PTY code C
2 ASCII characters
0
2 ASCII characters
4: text AlB flag
3-0: text address
15-12: 0100 CT CT
11: 0
PI 10: TP flag 15-1 : MJO (14-0) chck 15-12: hour (3-0) chck
Group 4A chck A chck 8
code 9-5: PTY code 0: hour (4) C 11-6: minute (5-0) 0
4-2: not used 5: offset sense
1-0: MJO (16-15) 4-0: offset (4-0)
15-12: 1110 EON information
11: 0 code: 0-3: PS
PI 10: TP flag 4: AF chck chck
Group 14A chckA chck B PI (On)
code 9-5: PTY code 5-9: AF (map) C 0
4: TP (On) flag 10-11 : not used
3-0: usage code 12-15: not imp.
------ --- '----
The listing is shown for use with a divide by 8 multiplexing LCD module. This module will normally contain
an HD44780 and an HD441 00.

If a divide by 16 module (HD44780 only) is to be used then line 1294 should be replaced by line 1293 and
line 1371 commented out to include the execution of the code on lines 1379 to 1392.

The different display formats are selected by checking the various flags and the relevant routine executed.
The normal display permanently shows PS name and time. As the locations in RAM used for hours and
minutes contain binary numbers they are converted to BCD before being written to the relevant bytes in
DISP. Once all 16 bytes in DISP have been loaded, a loop is used to send the data to the LCD module.

The VFD routine sends the same data as is shown on the LCD module to the serial VFD module. The display
driver used has a different character set from the standard ASCII set used by the LCD module. The table
VTAB is used to convert ASCII data into the required character in the VFD module. The small table INITF is
used to send the required initialisation bytes to the VFD module. This module does not require a busy check
but does require a delay between successive bytes. This is satisfied by the wait loop within the serial
output loop VFDF.

Alarm functions

The alarm time can be entered as described above. If the alarm is enabled (alarm time displayed on first·
press of the ALARM key, and permanently displayed in standby mode) then, at the alarm time, the auxiliary
control line will go high. This can be used to control external hardware, for example to switch on the VHF
radio supplying the RDS data. If the auxiliary line is already high (decoder fully on or on via the sleep timer),
then it simply stays high. The operation of the sleep timer is not affected if bit 0 of port E is high. If this
I/O line is low at the alarm time, then the sleep timer is activated for an hour. This takes place whether the
decoder was previously on, off, or running the sleep timer, and has the effect of switching the auxiliary line
Iowan hour after the alarm time, regardless of its condition prior to the alarm.

At the alarm time the alarm output will also be activated (active low) as long as it is enabled by bit 1 of port
E being held low. This is intended to drive an alarm sounder. When this output is active, a press of any key
cancels it until the next alarm. This cancellation does not affect the auxiliary output.

REFERENCES
EBU Technical Document 3244, Specifications of the Radio Data System RDS for VHF/FM Sound
Broadcasting.
2 AN459, A Monitor for the MC68HC05EO

APPENDIX (listing) follows

73
0001
0002
....................................................
0003 HC0:,EO RfIS De~xiE>r,
0004
0005 Tq..--Plrlg l~th F'elJn.JiUj' '92
.....................................................
P
0006
0007
0008
00090000 "''''A a:u ,00 fORI' A AOORESS
00100001
00110002 "''''B
"'Rl'C
Et<J
""-'
SOl
SO:
$03
B
C
00120003
0013 0004
"'RrD ""-'
a:u $04
0
£
"''''£
00140005
00150006
00160007
"'' 'Alla:u
"'RrOO Et"J
S05
SDe
FOR!' A DATA DIREC'!'ICN REG
B
roRl'CD ""-' S07 C
00170008
00180009 """00 ""-'
"'Rrrn Et"
SQ8
$09
D
£
0019 OODa TAP a:u SQA TIMER A ~-9:ALI.ER
0020 OOOb 'I'BS ;-J£l TIMER B OCALLER
0021 DaDe
0022 OOOe
1n
Ie" ""
"'.
W'
S0":-
SJE
TlMER (Ufl'roL REGISTER
W!'EAAUPT C\l'lI'R:JL REGISTER
00230012 FORI'DSF El,.oc :-\:: RJR!'D SPEl:LAL MI.'TICNS
0024
00250009 NO E!:'J B::O DIGITS
0026 ""
00270030
0028
00290030
00300039
00310042
,
"" """
P
""
--
RHB
SuOh'

e.::D W..'RK INC I-lJMBERS

XRAK'H
VL'RKINC ~ 2
,...
---
0032 004b THP MJLT, OIER, ~ OIV, RD1AINtER
0033 00~4 R "ORK INC NJMBER 3
0034 OOSd 1<.10 l<IoIFIED JULIAN DAY tUMBER
00350066 YR YEAR
0036006f
00370C71
00380073
""H
[0< """
"'"
RMB
"""'"
"'1'£
~Y OF' WEE><
"'"
--
00390074
0040007'1
0041 0018
"""
DI,",
SL£?!
RHB
BINr\RYl-UD
DISPLAY TRANSIENr TIMEO..lT (."C!U'f!'ER
SLn:P TIMER MINJTES t"C"UnU
004200'19 RDSI'C "., ImS TIMEX.:UI' C'Ol.N1'ER
0043 007a ""T """ SERIAL DATA Q.fFF'EJl

--
0044 007e n-lf.'(;RP TEJ-IF\..RAAY CRClJP EVl.TA
00450086 ORe";P ("("1MP1£I'E CF(1(}P DATA
0046008e
004700Sf
PrY
PI
"""
w.B
l-'R,X;r<A,M-1'YFE Cl.OE (C\..IRRENJ')
i-'R(~RII.M IDI:NI'IFlCAThN C'OOE
00480091 ffi,\.iAAM ITEM Nlt-ffiEF<
00490093
00500094
PIN
lEV
BIT
'""
~
VALID BUX'K I.EIlEL
BIT LEVEL
00510095
00520096
1_'
SYN
RMB TD1P BYTE: FOR USE IN 1f'Q

005)0098
00540099
=
TH8
"'"
RMB
f<MB
'YND«>IE
SYNDfOiE CCNFIrDl.'E
TICS (EIGHTHS Cf" SEX:c.NDS)
0055 009a
0056009b
,£c
~'GN
,..,
"'" SEL,-!NDS
MlNo.r:t'ES
0057 00ge <>JR
"'" HOOl<S
'"IN
-
,..,
0058 0090.
005900ge NJUR
'*' A.I..AAM MIWI'ES
ALARM HOORS
0060009f
0061 OOaO
DIS?:
D!SP2 ,.., R!' D!SPLAY romrrn 11
..
R!' DISPLAY F0urrrn 12
006200a1 HI
0063 0032 W2 "'"
»Ill

-
0064 00a] WJ RMB
0065 00a4 RMB
0066 00a5
0067 00a6
0068 00a7
"'"W,
W7
F>lll

0069 00a8 Wo ""'"

»Ill
0070 00a9
"" ...,
f<MB ("G[IE OF' ffiESSEfi KEY

--
0071 OOan KCX..t-IT I<EYB(lARf) C("IJN!'Er<
0072 00at> B;[ ...AMY
0013 OOac
CAAJ<'(
cowr "'" u.:x:,P f.'(IJNTER
0074 OOad
007S OOae
"-'111
NJM2
""" :5T N:;, KmrrER {ADD 4. SUBTR4i"!' ,
~ND NJ roDtI'O<. (,IU.(I I.. SUBTl~AI.:.. r:
0076 OOaf R'I':!IS RDS DlSf>!.AY TYPE
0077 OObO DI FWl QE...."(J[€R HlOOJFICATm~
0078 OObl DISr- aUF,..,.:p
007900cl
'"~ l[ ll."[J ~PWLE
~N
0080
0081 OOd STAT~
""" PS NAME

VALW SYNDRCME
0082 '/ALID GF(.".Uj:'
0083 RT DISPlAY
0084 Vf>[)ATE DISPLAY
0085 CLEAR DISPl.AY
0086 SPACE FLAG
0087 OOca STAT3 !>IE MIS, 0, M, 1 S
0088 TEXTA/TEX'l'B BIT (R'I')
0089 TA FlJ<C
0090 TP F'LAG
0091 KEY REPEATlt-C
0092 KEYF'tNC.'TION ~"1!
0093 UPDATE DATE
0094 OOcb S'I'AT4 DISPLAY Tw.NSIrnI'
0095 SlEEP TIMEl<: R\.NNUI;
0096 SLEEP DISPLAY
0097 A[.AFO<! DISPLAY
0098
0099 ,,. AI.ARt-l Ai<MET!
AlAfIt-i SET-I)f.'
0100
0101 , AlARM HCl..ffiS (SET-UP)
RDS DISPLAY;
0102
0103 OOce
0104 ODed
010500[[
0106
01070100
0108
01090100
.sTACY
St'
-
I'¢~

H"
$0100
use.:!
I"-'l
19 BYrES USED (I INI'ERRlPr
ANTI 7 J<li:c:TEI!

!<ADIurE);,l'
~:UBR.:JlTl' l.NES)

01100145
RT
"'" "
rul
"'" In EU-I DATA (MAX' 11~S)

74
0112 eOOO
0113
0114 'STRS~!' JM).J RE.SE.T VEJ:.1'QB [ljf(It'lJ DE-BJG)
0115
0116
0117
*Iki.'
'TJ}fl:}{A
"1'IMERB
JHP
JMI-'
SMl'
'''''
TIM!:}< A INI'EW-<l.Wr (t>l:1!' U5!:lJ,
l' IMEr~ l:> INTJ:'RHJPr
OJRIN::
OJRU.c
LURIN::;
DE-EJJG)
VE-EJJG)
VE-El.,!G)
0118 'sEI<nrr JM:I' JEJ<.LAL wrEAAuvr (N:!!' USlli, Ll..JRlt.c [JE-ltJG)
0119
0120
0121
0122
0123
0124
0125
0126 eOoo a6 c3 11)11. I$CJ ENABLE PClRTD S!>EX..'lAL F'\..tK.."!'IWS
0127 e002 b7 12 Sf A KlRrDSF P02. RM, A14 .. AI!> (O.l.6.7)
0128 e004 016 45 CDA 1$4<; ENABLE POSITIVE Era/LEVEL
0129 e006 b7 Oe srA ICR INTERf<twrs
0130 e008 016 01 LIlA 11 TIMER B SCALER· II.
0131 eOOa b7 Db Sf> TB5 12!> nS H1!'ER"'JP1'S (4 I ~4 MHz XTAI.)
0132
0133
eDOe
eDOe
016
b7
)f
Dol
CD.'
m ",
TAP
TlHEJ'< A PRE-SCALER 164
64H;: IDl.E !.iDp
0134
0135 eOlO ) f 00
0136
0137
e012 a6
e014 b7
f[
05 U'"
srA
EO~J(; DISI>LAY/KEYBC.IAFdJ 1/0
NJJ' USEr! IN Rl)S A}>fJl..lCATIW
0138 e016 3f 01 eLf< O. 1 SERIAL CLL.CK AND DATA
0139 e018 016 cb IDA <! RDS DAT.II, IN. J. VFl.J SELEL"T
0140 eOla b7 06 STA 4, S Y.t.YB:;ARD ll.J i." 7 Y-EY~J ovr
0141 eDle 3f 02 eLI<
0142 eOle ",6 ff illA ALL a.rr, U:D DATA EUS
0143 e020 b7 07 STA
0144 e022 016 )e WA bITS ~. J I. 4 '.)Jf. LCD
0145 e024 )f 0) eLf< t! RS. J. R/W. 4 CLLCK. 5 LED (TA=-TP=l)
0146 e026 b7 08 Sf A O. 1. 6 & 7 UsED DURlliG OE-BIJ:J
0147 e028 a6 Oc lnA BITO INP..n', ENABLE SLD;P TIMER AT A~ TIME
0148 e0201 b7 04 srA BIT1 INP..n', ENABLE Al...ARM OJTI>I.Tr
0149 lDA BLT2 ALARM OJI'PVJ' (ACTIVE U-W,
0150 e02c b7 09 erA BIT] KAr'IU ~ cmPJJ' (Al"!'IVE HI(:H)
0151
0152
015)
0154 lu).tlall"E' LL'V
0155
0156
0157
0159 e02e 016 )0
0159 eO)O cd eb 65 rNITlALl:::E LL"
0160 eO)) cd eb e6 'LEAR EHl DIITP.
0161 eO]6 cd eb e6
0162 eO]9 cd eb €'6 4 'l'l!1L' TO PR..IV![1E A L Ir"'; DECAY
016] eG3c cd eb e6 P >I< [;'T' MJl.uu.: INlTLt<.LISATlr.~.J
0164 eO]f a6 30
0165 "OU cd eb 6:"
0166
0167 e044 ae )0
0169 e046 7f
0169 e047 5c
0170 e049 a) ed
0171 e04a 26 fa
0172
0173 e04e 016 )0
0174 e04e cd eb 65 INITIALISE LCI'
0175
0176 e051 00. eb 6c
0177 eG54 a6 30 I-UNE DISPLAY
0178 ..056 cd eb 65 UI'KHIT
0179 e059 00. eb 6c
0180 eOSe a6 08 ~ITCH !'!Sf.'UlY uF'F
0191 e05e cd eb 6S LAR'H IT
0182 e061 a:l eb 6c
018) e064 016 01
0184 e066 cd eb 65
0195 e069 cd eb aa
0196
0187
0188
0189 V"'~tUli; (('I ,jE'"bll',) ll£llJg EOBIJ.., n(JrJltO(
019()
()1':11
0192
0193
0194
0195
0196 WA VEr."!DkS FUR EO KJI'II1DR
()197 STA
0198 STA USHl.~ J1.MP TABLE AT $0400
0199 STA
0200 SiA
0201 cr.
0202 STA II'\.! ($040,1
0203 Lt.
0204 STA TIMEF A (S0406)
0205 LOA
0206 STA
0207
0208 'OEF LAL IS04l)(.:\
0209
0210
0211
0212
0213
0214
0215
0216 e06c a6 Db [lJA 1;0£
0217 eG6e b7 Dc ::."!'A ,"r
0218
0219 e070 9a

75
0221
0222
0223 Idle lC'l..'f'
0224
0225
0226
0227 eOn 09 Oe Cd IDlE BRCLR 4,1(,R,' 64Ht
0228 e074 19 Oe leU< 4, I~'R
0229
0230 e076 01 cb 07 BRCLR Q,:.-'l'AT4,N.)PS DISPLAY TIW'lSlENr ?
0231 e079 b6 77 DIS'r
0232 eG7b 26
0233 e07d eel
03
e8 Oa
""
"'"
JSR
l<)pS
CLTR
YES, TIMID wr ?
YES, CI.E.AR TRANSIENt' DISPLAYS
(2)4
0235 e080 07 c9 05 ~PS BRCLR J, :.-'TA12 , :>rAN DISPLAY UP~TE Ra,.JUlRED
0236 e(8) eel e6 b6 JSR mD YES, 00 IT
0237 eOa6 17 c9 leU< 3,-:,'TAT2 AND Cl.E'AR F't..A(;
0238
0239 e088 09 cb Id BRI-':.,R 4, S"I'AT4, l-llSLP ALARM ARMED ~
0240 e08b b6 ge W., ;":"VR YES, ('OoIPARE A~ HClJRS
0241 eOSd bl 'k (}<p ~IJR .... ITH TOO:
0242 e08f 26 17 SAME ~
0243 e091 b6 9d
0244 e093 bl 9b
"'"
LDA
(}<,
CHSl.P
AMIN
MIN
YES, CCl'lPARE
WITH TIME
A~ MrnllT'E$

0245e<l952611 SAME
0246 e097 b6 Sa
0247 e<l99 26 Od
"'"
WA
('HSl.l-'
SEC
~l1S~,J'
(l\!LY AWloJ WAf(E-UP IN FIRST SEl.\.lNO
1\) ~'REVENI' SWI'K'H-ClFF ID~'''O,"I'I'
0248 e09b 16 04
0249
"'"
"'IT ), tORTE YES SWI'l":H a-l

02~O e09d 02 04 02 BRSE'r 1, fl,.")F<rE fVL0:..«2 AJ....AJ<M ENABlD> (SWI'l":H)

0251 eOaO 15 04 leU< ,", f{ 'RI'E YES, SIJ,)ND AU\RoI
0252 eOa2 ao 04 0) FULLJN2 BRSET O. fl,.)RrE. (,HSLP SLEEP TIMER AT AlAffoI TIME ?
0253 eOa5 cd
0254
e2 09 J" INSLI' YES, ,,'TA..RT SLED> TIME:F

0255 e<la8 03
0256 eOab b6
cb
78
De CHSl.P ERe'
11'A
" 1. STA1'4 , Fll'l
SW'l'
SLEEP TIMER R.WING ?
YES
0257 eOad 26 04 Em Pill TIME TO FINISH ?
0258 eOaf 13 cb OC'U< 1. S1'A1'4 YES, ClEAR FlAG
0259 eObl :7 04 OCLR 1, KlRTE AND ~I'I'C.'H OFF
0260
0261 eGb) cd el 11 JSR IQ<r' READ t:EYEOAAD
0262 eOb6 cd el 6 E JSR i<EYP E:':EJ:'VJ'E:m
0263
0264 eOb9 b6 ca :""'iA ,,";'A1' 3
0265 eObb a4 Dc 1$')('
0266
0267
eOtd alOe
eObE 27 07
""
-><, 1$,).:::
TNfl'
Til. AND if' [(JI'H HII":" ,

0268
0269
eOcl Oa 0) 09
eOe4 la 0)
"""
BRSE'r
BSIT
" ~ORTD lex.+-:
:" ~IJRTI\
t-l.).
~\.
1/(1 LINE Au<£b.DY HIGH .,
~ IT HIGH
0270 eOe6 20 OS 8R'" :.('1'
0271 eQe8 Ob 0) 02 BM..';.j( f-\ rI~[1 :,'" 1A~TI'~1 110 L:Nl:: ALRl::AIW li~J
0272 eOch 10 0) ECLF k'RTl:' lot" ~I1'li\<"
027)
0274 eOcd Od ca 02 BROeR WLSJ lIpr~TE ['lATE "
0275 eOdO ad 02 &>1< YES CCN./E1{T FF«.l<I MJr-
0276 ~0d2 20 9d IDl.E..)
0277
0278
"'"
0279
0280
0281
0282
028)
0284 eOd4 b6 76 !..DA B'1Jr).J
0285 eOd.6 b7 68 ~TA YF-.. ~
0286 eOd8 b6 75 CDA Et1"[l.'
0287 eOda b7 67 STA YR.,
0288 eOdc b6 74
0289 eOdE!' hi 66
LDA
gr;..
8MJ'
'fR
0290 eOeO ae 54 Wi. OC 2~
0291 eOe2 bf ad Sit. NI.rHl
0292 eOe4 cd ef 86
0293. eOe7 3c 5c
0294 eOe9 ae Sd
JSR
[NC
~[!;>,
::Lf.A3
"'.Nr'-l
ltoi,.1D
,
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0295 eOeb cd ef 86
0296 eOee a6 11
)Sf<
:.I,A
·_'I.PA.'
OJ"
"~E.t.Jl "10
biTS '!'(J C(NVU{f
0297 eOfO );.7 a6 Sf;" v;,
0298 eOf2 34 66 !jX!PJ LSf' Yl' KNE C~J1'
0299 eOf4 36 67 RCP Yf.•• l
0300 eOf6 36 68 rop YF<.':: F'IKST iL's) BIT
0301 eOf8 24 07 tr,:1'J 2£;0
0302 eOta ae Xl :1:,:'; OMIT '..tIE, ,II,I)[,
0303 eOCe bf ae srx t-J,1t-\2 (,-,'FIRENT' VA.UJE
0304 eOfe cd
0305 elOI ae
ee )3
54
)Sf' AD,' uFP
,
'" AI'('
l[JX
0306 elC) bf ae S'J'X t'JJ~12 1\,
0)07 el0S cd ee ))
0308 e10a 3a a6
JSR
DEC w,
AtJ(J ITSEU'"
ALL
0309 e10a 26 e6 mE ux·", rrn£
0310 elOc Id ca
0311 elOe cc ef 95
ocU<
~<P
';',s'Y'An
MJfJ.'
KJD IJPIlA.TED
OONVE><T MJD 1'(, DAY. DATE. I<JNfH , YEAR

76
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0]14
0]15 Keyboard rout llle
0]16
0]17
0318
0]19 elll a6 20 Lll'\ 1$20
0]20 el13 ae 02 lllX 12
0]21 ellS 48 KEYI !.SUI SEI...EX'T RCW
0322 e1l6 a4 cO AND l$eO BITS 6 & 7 OOLY
0323 ella aa 08 en IS08 VFD ENAB!.E HIGH
0]24 ella b7 01 grA roRrB
0325 ellc b6 01 lllA roRrB READ KE'iOOARD
0326 elle as )0 BIT 1$30 !>NYrn~ LINE H ICt! ..,
0327 e120 26 07 <NE Ll
0]28el22 Sa DECX /10, TRY NEX1' COLl..fo!N
0329 e12) 26 fO <NE LAsr COLlt1N "
0330 e125 )f a9
0331 e127 20 Oc
CLR
BAA
"""
KEY
£XIT
YES, NO KEY ffiESSED

0)32
0333 el29 b6 01 Ll lllA roRrB READ KEYBJARD
03]4 e12b a4 fO AND 1$.0
0335 e12d bl a9 C>lP KEY
0336 e12f 27 04 BUl £XIT
0))7 eDl b7 a9 grA KEY 1>1), SAVE THIS KEY
0338 e13] 3f aa CLR Kotm
0339 eD5 )c aa EXIT INC Kotm YES, THE SAME
0]40 eD7 b6 aa IDA Kotm
0)41 eD9 09 ca 04 BRCLR LSTAT],NRML REf.£ATING ?
0]42 eDc aIDa C>lP 110 YES, REPEAT AT 6 Hz
0]4] e13e 20 08 BAA GOI2
0]44 e140 al 0] O<P IJ NJ, ) THE SAME ?
0]45 e142 25 29 BW KCU:; IF NOr 00 N.JJ'HING
0346 e144 27 lb
0347 e146 al ]0
"""
C>lP =
148
IF ] THEN F£RF'Cf<M KEY FUN::'l'Ial
IoORE THAN 3, HeRE THAN 48 (750mS)
0348 el48 22 06
0]49 e14a b6 a9
8HI
IDA
=
KEY
TIME TO 00 SCMEI'HINJ ?
on
0350 e14c 27 19 RKEY
"""
KEY ffiESSED ?
0351 e14e 98 CU:;
0352 el4f 81 RrS YES 9JI' CO NOI'HIN:3
0353
0354 el50 b6 a9 =2 IDA KEY
0355 el52 alSO "'P I$~O SLEEP mEr: )
0356 e154 27 04 aun
0357 el56 al 90
0358 el5826 Of
0359 elSa Db cb Oc
"""
C>lP
ENE
1$90
rNr2
RDS (It'l: I
I. NOr A REPEAT KEY, 00 N.JJ'HING
=J BRCLR ), STAT4,lNI'2 REPEAT KEY, Elf!' IS MOOE ALARM SET-UP "
0360 el5d 18 ca
0361 el5f H aa
BS'"
CLR
4, STAT3
Ko.m
YES, SET REPEAT F1.AG

0362 e16l b6 a9 LDA KEY

0363 el63 27 02 B£Q RKEY sa-!E'I'HlNG TO 00 ~
0364 e165 99 SEC YES, SET C
0365 e166 81 RrS
0366 el67 Ib ca RKEY OCLR 5, STAT) NJ CLEAR CONE FLAG
0367 e169 19 ca 1Nf2 OCLR 4.STAT3 CLEAR REPEAT FLAG
0368 e16b 3E aa CLR Ko.m CLEAF COl.tII'EJ'<
0369 el&! 98 KCU:; C1£
0370 e16e 81 RrS
0371
0372
0373
0374 Execute key functlorl,
0375
0]76
0377
0]713 e16f 24 26 i<EYP fCC 1Nf ANYi'HIN:; TO !Xl ?

0379 el71 b6 a9 KEYP2 WA KEY YES, GEl' KEY

0380 e17) alSO C>lP IS50 SLEEP WEI:: )
O]81e175 27 07
0382 e177al90
O)8)e179 27 03 """
C>lP
Rl'r
Isqo RDS (IN:,)

"""
RPT
0)84 e17b Oa ca 19 BRSET 5, STAT),[NI' t>m A REPEAT KEY, [:()NE FU.G SET ..,
0385
0386 e17e Sf RPT CLR)(
0387 e17f d6 el 98 PJ WA F'E'I'('H KEYCODE
0388 e182 bi a9 OIP THIS CNE ?
0389 elB4 27 Db B£Q YES
0390 elB6 c1 el
0391 el89:n Dc
a4 "'P UlST NJ, u.SI' CHAN::'E
YES, ABJRT
?

"""
1Nf
0392 elBb Sc lNCX NO
0393 elBe 5c !NC~ TRY
0394 elBd Sc lNCX THE
0395 e18e 5c lNCX NEXr
0396 elBf 20 ee BRA PJ YEY
0]97 el91 la ca
0)98 e193 5c
BS'"
lNCX
5, SI'AT3 KEY FUN::TICN !XNE

0399 e194 dd e1 98 JSR CI'AB,X

0400e19781 RTS
0401
0402
040)
0404 KE'y~rd JUITp ta.ble
0405
0406
0407
0408 el98 60 crAB Ft'B ALARH
0409 e199 cc el a8 OMP
0410 elk aO FeB a.JfOFF
0411 e19d ce e1 c7 JMP
0412 elaO 50 FeB SLEEP TIMER Sf ART
0413 elal cc el fa JMP
0414 ela4 90 u.SI' FC.'8 RDS ClISf'c.AYS
0415 elaS cc e2 26 Jl1P

77
0417
0418
0419 Alann key.
0420
0421
0422
0423 e1aS OS 04 4e ALARM BRCLR 2, roR'l'E,ALR3 AI..Aru4 RIN:;mG ?
0424 elab 07 cb Ob BRCLR ),SI'AT4,AIXN NO. ALARM DISPlAY CN ?
0425 elae 09 cb 04 BRCLR 4,grAT4,~ YES, AJ.ARroI CN ?
0426 e1bl 19 cb OCUl 4.SI'AT4 YES. SWITCH CFF
0427 elb3 20 09 BAA UIXNl'
0428
0429
e1b5
e1b7
18
20 OS
cb AUF BSE:]'
BAA
4,grAT4
UIXNl'
NO. "'l'l'OI 00
JSR
0430
0431
0432
elM
e11x:
e1he
00 e8 Oa
16 cb
1b cb
""'"
UIXNl'
BSE:]'
OCUl
CLTR
3,STAT4
5.STAT4
ALARM DISPLAY F'l.JIC
CAN:::EL SEr-UP
0433 eleO a6 19 WA m ) SEL'OOD T lMEl:m
0434 elc2 b1 11 STA OIST
0435 de4 10 cb BS'" 0,STAT4 SET DISPlAY TRANSIENT F'l.JIC
0436 e1e6 81 ABOA .rs
0431
0438
0439
0440 (XI/off key (alarm set-up).
0441
0442
0443
0444 ele1 OS 04 2d CNCFr BRCLR 2. roRJ'E.AlK: ALARM RIN:;n.:K> ?
0445 e1ea 07 cb 1c BRCLR ),SI'AT4,1UI'~ I'D. ALAAM DISPlAY?
0446 elOO 09 cb 19 BRCUl 4.STAT4,N:1I'ALR YES, A~~?
0447 eldO Oa cb Db BRS'" 5, STA14,AI9o! YES. AlRFAD't S£I'-UP M:l1E ?
044 S e1d3 loll. cb BSE:!' 5,STAT4 N:l, ENI'ER SET-UP HOOE
0449 eldS Ie cb BSE:!' 6,STAT4 WITH HOJRS
0450
0451
eld1
eld9
a6
b7
SO
11
"'SO WA
ST.
18O
DlST
0452 eldb 10 cb BS'" 0.STAT4 SET DISPI.A.Y TRANSIENI' FLAC
0453
0454
elckl 81 "'B2 RTS

0455 e1de Oc eb 04 AI!>! BRS'" 6. STAT4. MSM SET-UP Ha.rRS ?

0456 ele1 1b cb OCLA 5,STAT4 f'l). CAN:ELL SET-UP
0451 ele3 20 f2 BRA ASSO
0458 ele!> Id cb MS" OCLA 6.STAT4 YES, MAKE rr MINIJl'ES
0459 eIe1 20 ee BRA ASSO
0460
0461
0462
0463 On/off key (normal functlOJI).
0464
0465
0466
0461 ele9 cd e8 Oa Im.LA JSR CLTR CLEAR 01 SPLAY TRANSIENTS
0468 elee 13 cb OCUl 1.STAT4 CAN:'EL SrEEP T1ME}t
0469 elee 06 04 03 BRSEr J,roRTE,~ <l<'
0410
0411
elfl
elf3
16 04
81
so'" BS'"
RrS
J. roRTE NO. "'r=! 00

0412 elf4 11 04 ALR:>I OCLA 3. (.QRTE ITS. ~ITCH OFF

0473 elf6 81 "'S
0414 elf? 14 04 AU<; BS'" 2. KiRTE CAN:EL A~
0475 elf9 81 "'S
0416
0477
0478
0479 Sleep key.
0480
0481
0482
0483
0484
0485
e1Ea
elfd
e200
05
Ob
ee
04 fa
cb 03
e2 79
SLE>;. BRCLR
BRCLR
OM.
2. roRTE,,l>.LR;
5.STAT4.IVl'AL
PO'"
..,.
ALAfIM RIN:> INc; ?

ITS
ALARM SET-UP ?

0486 e20) 04 eb 10 Im.L BRSET 2,STAT4.00:::S NO. ALREADY SLEEP DISPLAY?

0487 e206 02 cb 06 BRSE:r 1, STATo:!, STR2 NO. SLEEP TIMER ~Y RI.NlrnG ?
0488 e209 a6 3c INSLP IDA 16O NO. INITIALISE S!£El> TDoIER
0489 e20b b7 7EI srA SLEl'r
0490 e20d 12 cb BSET 1,STAT4 START SLEEP TIMER
0491 e20f cd eB Oa srR2 JSR CLTR YES. ClEAR DISPLAY TRANSIENI'S
0492 e212 14 co BS'" 2.STAT4 SLEEP DISPI.A.Y
0493 el14 20 08 BAA SLPI'Cl{ N:l DFrREMENI' IF FIRST TIME:
0494 el16 b6 78 =S Wi>. SLEPT rttREMENI' SLEEP TIMER
0495 ellS aO OS ;va 15
0496 e2la b1 78 sr. SLEPT
0497 e21c 2b eb .... 1 INSLP IF UNDERF'LCW WRAP Fntm TO 60
0498 el1e a6 19 SLPra< IDA 125
0499 e220 b7 77 sr. DIST
0500 e222 10 cb BS'" Q,STAT4 START DISPI.A.Y TRANSlliNr
0501 e224 20 cb BRA scm
0502
0503
0504
0505 RDS display key.
OS06
0507
0508
0509 el26 OS 04 ce RDS BRCLR 2,FORl'E,ALR:: ALARM RIN:> INc; ?
OSlO e229 Oa eb 29 BRSE:r 5, STATf, PIN:: 00, ALARM SI::I'-UP ?
0511 e22c 07 04 17 BRCLR J, FORTE, SRT3 N), STANOOV ?
0512 e22f Oe cb 03 BRSE:l' 7.STAT4.~ ALRF.AO'i ReS ?
0513 e232 05 c9 12 BRCLR 2.STAT2,I'DRT ALR£J>.OY RI' DISPLAY?
0514 el)5 Ie eb BS'" 7.STAT4 SET ReS DISPLAY FLAG
0515 e237 b6 aE WA RI'DlS l<JVE ' "
0516 e239 4e INCA
0517 elJa a1 13 eM. 119
NCf<r
0518
0519
0520
e23e
e23e
e240
27
b7
a6
09
aE
64
"'sr."
UlA
RTDIS
1100 12 SEl:CND TIMECUI'
0521 e242 b7 77 ST. DIST
0522 e244 10 eb BS'" a,STAT4 RE-START TRANSIENI' TIMEDJI'
0523 e246 81 SRT] RTS
0524
0525 e247
cd e8 Oa I<>RT JSR CLTR ('!.£AFt DISPLAY TRANSIENTS
0526 e24a
14 e9 BS'" 2.STAT2 £.I::I' Rl' DISPU\.Y FI.A.G
0527 e24c
a6 09 WA 19
0528 e24e
b7 9f sr. nISP1
0529 el50 a6 01 ill. 11
0530 e252 b7 aO sr. DISP2
OS:H e254 81 "'S

78
OS33
OS]4
05]5 II,crerloe!,t alarm tillot:
0536
05]7
0536
0539 e255 Oc cb Oe PIt-l: BRSE:'I' 6,STAT4,IHR SET-UP HWRS ?
0540 e256 b6 9d l.DA AMIN rD. M.IWl'ES
0541 e25a al )b OIP 159
0542 e25e 24 04 BHS TCOH
0543 e25e 3e 9d ItI:: AHIN
0544 e260 20 Oe BRA T5S
0545 e262 3f 9d elF AMIN
0546 e264 20 OB BRA T5S
0547 e266 b6 ge IHR ~ AaJR
0548 e268 a1 17 OIP 123
0549 e26a 24 09 BHS H1UH
0550 e26e 3e ge IN: AaJR
0551 e26e a6 SO T5S l.DA 180 10 S9:CND TIMEUn'
0552 e270 b7 77 STA DIST
055] e272 10 eb BSE:'I' O. STAT4 SET DISPLAY TRANSIENT FLAG
0554 e274 Bl RrS
05S5 e275 )f ge HTOH ClF AaJR
0556 e277 20 f5 BRA T5S
0557
0558
0559
0560 Decrement alarm time
0561
0562
056)
0564 e279 Oe cb Oe roB: BRSET 6, STAT4. IHRD SET-UP HWRS ?
0565 el7c 3d 9d TST AMIN N.J. MIMJ'l'ES
0566 e27e 27 04
0567 e280 3a 9d B<Q '"
DEL AMIN
0568 e282 20 Oc BRA T5SD
0569 el84 a6 )b HZ LDA 159
0570 e286 b7 9d STA AMIN
0571 e268 20 06 BRA TSSD
0572 e2Ba 3d ge IHRD TST ACUR
0573 el6e 27 09 B<Q HZ
0574 e28e 3a ge 09: ACUR
0575 e290 a6 50 TSSD LOA 180 10 SEIX1ID TIMEClJT
0576 e292 b7 77 STA DIST
0577 el94 10 cb BSET 0, S'I'AT4 SET DISPLAY TRlINSIENJ' FLAG
0578 e296 81 RrS
0579 el97 a6 17 HZ LOA 123
0580 e299 b7 ge STA AClJR
0581 e29b 20 f3 BRA T',SD
0582
0563
0584
05B5 Timer lnten-Uj:.t rout tHe
0586
0587
0588
0589 el9d 3c 9f TINT'B ilK: DISPl LlISPLAY
0590 el9f b6 9f LDA DISPI pry
0591 elal al 06 CliP 18 t-OVIN:.:: RT
0592 e2a3 2) 06
059)
0594
e2a5 OIl 4e
e2a7 22 02
BLS
CMP
BHI
"'"'~""
178
END OF' RADIOTEX'J' ?
END CF R'r

OS95 e2a9 )e 010 _ CMP

INC DISP2 I'D. MJVE RADIOTEXI' ONE CHARAcrER
0596 elab OIl 58 188 2 SECl.)NDS AT END OF RAOlarEXT
0597 e2ad 25 02 BID
0598
0599
e2af 15 c9
elb1 1b Oe r>IR2
Beill
Beill
"""
2. STATZ
S.ICR
RE'l\JRN TU I'DRMAL DISPLAY
CLEAR TIMER B nrrEf<P1..WT FLAG
0600 e2b3 16 e9 MEr ), swrAT2 UPDATE DISPLAY
0601 e2b5 )c 99 Cl..CJ< me TH8 UPDATE EIGI{fHS OF SECONDS
0602 e2b7 )01 77 DEC DIST DECREMENT TRANSIENT DISPLAY TIMER
060) elb9 3c 79 INC RflSTO
0604 elbb b6 79 LDA RDS70
0605 ell:d OIl 50 CMP 180 H'S WITHa.Jl' A GRO:.IP \) OR 15
0606 e2bf 25 10 BID RDSOK
0607 e2cl 15 ca Bell< 2. STAT)
0608 e2c3 3f 6e N14B CLR pry
0609 e2c5 3f 8f CLR PI
0610 elc7 ) f 90 CLR PId
0611 e2c9 3f 91 OLR PIN
0612 e2eb 3f 92 OCR F!N.1
0613 e2a::l ) f bO CLR DI
0614 elcf 11 ca Bell< O.o1'AT-'
0615 e2dl b6 99 RDSC)I< lIlA TH8
0616 eld3 OIl 08 mp 18
0617 e2d5 26 32 ENE NOm: PAST 7
0618 e2d7 3£ 99 CLR n;s YES. Cl..E.AR
0619 e2d9 )e 901 INC SIT U1T";TE SErCNDS
0620 e2db b6 901 LDA SEC
0621 e2d:l OIl 38 CMP 156
0622 e2df 26 02 BNE NOrI
0623 e2e1 301 78 oo."'REMEN'T
0624
0625
e2eJ OIl 3c
e2e5 26 22
turS ""
CM:P
INE
SCEPr
'<0
SLEEP TIMER MIlVI'ES

0626
0627
e2e7 3f 9a
e2e9 3c 9b
CLR
INC
"""
MIN
0628 e2eb b6 9b illA MIN
0629 e2ed OIl 3e CMP 160
OBO
0631
0632
e2ef 26 18
e2f1 3f 9b
elf) 3c 9c
ENE
OLR
INC
=
MIN
a~
PASf ')~
YES CLEAR
IJPrlATE HCVRS
0633 elf5 b6 9c IDA WR
0634 elf7 OIl 16 mp 124
0635 e2 f9 26 De ENE N::lK'
0636 e2fb ) f 9c CLR
0637 e2fd 3e 76 me EMJI).L
0638 e2ff 26 06 BNE t¥lrD
0639 e301 )c 75 INC EMJ[J.l
0640 e303 26 02 ENE N::11'[J
0641 eJ05 )c 74 INC EfotJD
0642 eJ07 Ie ca N.Jl'D BSET E..STAT_'
064) e)09 80
= "'I

79
0645
064'
....................................................
0647 RDS dock .interr~t (IfQ).
0648 Get a bit and calculate G}'lIdl"OlTle.
0649
0650
0651
....................................................
0652 e30a 04 01 00 SDATA B'''''' 2. roRTB.·')
0653 e30d 39 7d ROL DAT.3
0654 e30f 39 7c RJL n\T.2
0655 e311 39 7b RJL Mr. 1
0656 e3l) 39 7/1. RJL ""T
0657 e3IS 01 c9 Ob BRCLR 0.STAT2.TRY2 BIT BY BIT CHil:J( ?
0658 e318 3a 94 BIT 00, WAIT ~ BIT 26
06S9 e3la 27 03 "" THIS TIME ?
"'"
TRY!
0660 e3k 17 Oe OCLR 3. ICR ClEAR IRQ INTERRUPl' F'l..N3
0661 e31e 80 "'I
0662
0663
0664
e3lf
e321
11.6
b7
III.
94
TRY1 lIlA
S'fA
12'
BIT
0665 e323 b6 711. TRY2 IDA ""T HSB (2 BITS)
0666 e32S 11.4 03
U667
0668
e327
e328
97
b6 7b
AND
TAX
I1lA
"
MT.l
0669 e32a b7 97 S'fA SYN.1 [.<;B
0670 e32c 01 7d 011. SOl BRCLR 0.DA.T+3.Sl)
0671 e32f b6 97 I1lA SYN.1
0672 e331 11.8 lb IDR '$IB
0673 e333 b7 97 STA SYN.1
0674 e33S 9f TXA
0675 e336 11.8 0) IDR ISO)
0676 e3l8 97 TAX
0677 e3)9 0) 7d Oil. S13 BRCLR LOA.T.3.S23
0678 e33c b6 97 LOA SYN.1
0679 e33e 11.8 8f ID' IS8F'
0680 e340 b7 97 STA ""'d
0681 e342 9f TXA
0682 e343 a8 03 IDR ISO)
0683 e345 97 TAX
0684 e346 05 7d Oil. S" BRCLR 2.OA.T.).S4l
0685 e349 b6 97 IDA SYNd
0686 e34b 11.8 11.7 ID. 'SA7
0687 e34d b7 97 STA SYN.,
0688 e34f 9f TXA
0689 e3S0 a8 02 IDR IS02
0690 e3S2 97 TAX
0691 e3S3 09 7d Oa S43 BRCLR 4.DAT.J.sS3
0692 e356 b6 97 IIlA sm. 1
0693 elS8 11.8 ee IDR '$EE
0694 e3Sa b7 97 STA smd
0695 e35c 9f TXA
0696 e35d a8 01 IDR ISOI
0697 e35f 97 TAX
0698
0699
0700
e360
e36)
el65
Db
b6
11.8
7d Oil.
97
de
SS) BRCLR
IDA
IDR
sm.,
5.DAT.3.S6)

'$OC
0701 el67 b7 97 STA "",.1
0702 eJ69 9f TXA
0703 e36a 11.8 0) IDR ISO)
0704 e36c 97 TAX
0705 eJ6d Od 7d Oa S63 BRCW< 6. OA.T.J.S7)
0706 eJ70 b6 97 IDA smd
0707 eJ72 11.8 01 IDR tSui
0708 eJ74 b7 97 STA smd
0709 e376 9f TXA
0710 e377 11.8 02 IDR ISO;:
0711 e319 97 TAX
0712 e37a Of 7d Oa S73 BRCLR 7,CATd.S02
0713 e37d b6 97 IDA smd
0714 el7f 11.8 bb IDR 1$88
0715 e381 b7 97 STA ""'.1
0716 e383 9f TXA
0717 el84 11.8 01 IDR ISOI
0718 e386 97 TAX
0719 e387 01 7c Oil. S02 BRCLR 0,DAT'Z,SI2
0720 e3Sa b6 97 IDA ""'d
0721 el8c 11.8 76 IDR IS76
0722 el8e b7 97 STA SYNd
0723 el90 9f TXA
0724 e391 11.8 03 IDR ISO]
0725 e391 97 TAX
0726 e394 03 7c Oil. m BRCLR 1. OA.T.2,S22
0727 e397 b6 97 IDA sm. 1
0728 e399 a8 55 IDR IS55
0729 e39b b7 97 STA ""'.1
07]0 el9d 9f TXA
0731 e3ge a8 03 IDR 1$03
07)2 e3a.0 97 TAX
0733 e3al 05 7c Oil. m BRCLR 2.DAT.2.S32
0734 e3a4 b6 97 IDA sm. 1 0754 eJc8 Od 7c Oa S62 B1<:LR 6.DAT.Z.S72
0735 e3a6 11.8 13 !DR UD 0755 e3cb b6 97 LIlA SYN.1
07)6 e3a8 b7 97 STA 0756 e,.)cd 11.8 6e 1$6£
0737
0738
e3aa
elah
9f
.018 03
TXA
roR
SI%'

ISUJ
0757
Q7!>8
eJd b7 97
e3dl !If
"'"
STA
TXA
SYN.l

0739 e3ad 97 TAX 075!! e3d2 &.8 01 EX.. IS01

0740 elae 07 7c Oil. S32 BRCLR ],DAT.2,$42 0760 e3d4 97 TAX
0741 e3bl b6 97 IDA ""'.1 0761 e3dS Of 7c 09 S72 .I<:LR 7.DAT.2.S3]
0742 e3b3 11.8 9f IDR IS9F 0762 e3d8 b6 97 L!lI\ SYN.1
0743 e3b5 b7 97 STA SYN.1 0763 e3da a8 de !DR ISDC
0744 e3b7 9f TXA 0764 eldc b7 97 STA SYN.l
0745 e3b8 a8 03 IDR IS03 076S e3de 9f TXA
0746 elba. 97 TAX 0766 e3df a8 02 EX>< IS02
0747
0748
e3bb
e3be
09
b6
7c Oa
97
S42 BRCLR
IDA
4.Ol'.T.2.S62
sm<l
0767
0768
e3el b7 96
e3e3 b6 97
S:13
,...
STA SYN
SYN.1
0749 e3cO a8 87 IDR 1$87 0769 e3e6 01 7d 02 BR::LR 3.DAT.).S52
0750 e3c2 b7 97 STA SYN.1 0770 e3eEl a8 f7 EX>< 1$'"
07S1 e3c4 9f TXA 0771 e3ea. Ob 7c 02 S52 5.DAT+2.F'IN
0752
0753
e3c5
e3c7
a8
97
02 EDR
TAX
1$02 0172
077)
e3ed a8 b7
eJeE b 7 97 FIN
""''''
"'"
STA
ISB7
SYNd

80
0775
0776
....................................................
e c
....................................................
0777 Check fo"[ syndrccnes A, B, !.
0778
0779
0780
0781 elf1 17 Oe ICli< ), lCi< Cl.£AR IRQ Nl'ERRUPT F1...AG
0782
078) elf) b6 9) IDA lEV
0784 elf5 al 03 O<P 13
0785 e3f7 27 Sd
"'"
TRYD
0786 e3f9 al 02 o<P 12
0787 e3fb 27 22 Bm TRYC
0788 e3fd al 01 o<P 11
0789 e)ff 27 10 TRYB
0790 e401 3f 93
0791
0792 e403 b6 97 TRYA
"'"
CLI>

CDA
lEV

SYNd BlCCK 1
0793 e405 a1 d8 CMP I$D8
0794 e407 26 )1 8NE N01'V
0795 e409 b6 96 IDA SYN
0796 e40b a1 0) CMP 1$0)
0797 e40d 26 2b 8NE N01'V
0798 e40f 20 53 BAA VALID
0799
0800 e411 b6 97 TRYB IDA SYNd BLeCK 2
0801 e413 a1 d4 CMP 1$04
0802 e415 26 23 8NE N01'V
0803 e417 b6 96 11)A SYN
0804 e419 a1 03 CMP 1$0)
0805 e41b 26 Id 8NE NOI'V
0806 e41d 20 45 BAA VALID
0807
0808e4lf 06 800c TRYC BRS'" 3. 'n«FCRP. 2, TRYCD BLeCK 3 'NPE A
0809 e422 b6 97 11)A SYNd
0810 e424 a15c CMP 1$5c
0811 e426 26 12
0812 e428 b6 96
0813 e42a al 02
8NE
CDA "'''''
SYN
CMP IS02
0814 e42c 20 Ool
0815
0816 e42e b6 97
BAA

CDA
'"
SYNd BLlX:K 3 TYPE B
0817 e430 al cc eMP .sec
0818 e4)2 26 06
0919 e434 b6 96
0820 e436 a1 03
8NE
lIlA "'''''
SYN
ISO)
CMP
0821 e438 27 2a
0822
0923
'"...........................................................
"'" VALID

0924
0825 Invalld syndroue nandlwg, check for
0826 blu:k 4 and save group cl;;t(l If valld
0827
0828
0829
....................................................
0830 e4Ja 3f 93 turV eLR lEV RES1'ART AT BUX"K 1
0831 e43c b6 98 caw
0832 e43e al 29
OB33 e440 24 Oe
"'"
o<P
BHS
141
DEJ::C
CONFIDENCE 41 OR GREATffi ~

0834 e442 11 c9 OCli< 1j,S1'AT2 BIT BY BIT S'(N[.RCloIE CHEL'K

0835 e444 al Oa Oil' 010
0836 e446 23 Ob BLS SKFOC ro.JFIDENCE 10 OR LESS ~
0837 e448 3a 94 DEC BIT
0838 e44a 26 06 ENE USE BIT C:CX,NJ'E}( 'jV.) SVJ,.J CONFIDENCE
0839 e44c a6 1a
0840 e44e b7 94
IDA
CJrA
"""
126
BIT
DR(JP [JURrn::; BIT BY Brr A1'l'EMP!' TO
RE-SYNCRCNISE
0841 e450 ]a 98 DB::C DO: CWF
0842e45280 1m
0843e45318c9
0844 e455 80
""'"
SI"''''
lOr<
BS'"
RrI
4.srAT2 10 OR U:SS, INITIALISE DISPl.AY

0845
0846 e456 b6 97 TRYD 11)A SYNd
0847 e458 a1 58 CMP 1$58
0848 e45a 26 de ENE NOI'V
0849 e45c b6 96 11)A SYN
0850 e45e al 02 CMP 1$02
0851 e460 26 d9 BNE NOl"J
0852 e46212 c9 BSIT 1,srAT2 GRWP CC11Pt£rE
0853
0954 e464 00 c9 06 VALID 8RSET O,srAT2,\TLD VALID SYNDRCtolE FLAG ALREADY SET .,
0855 e467 a6 26 InA 018
0856 e469 b7 98
0857 e46b 10 c9
STA
BSIT
OJNF
o STATZ
'"AND
INITIALISE CCNFIDEN::E
SET F1.x.
(3~.4:421

0858 e46d b6 98 VID LDA CCNF

0859 e46f al )9 CMP t:J(,
0860 e471 22 04 8HI
0861 e473 ab 04
0962 e475 b7 98
ADD
S'rA
"'"
14
('CM"
0863 e477 be 93 Lm: IEJ
0964e47959
0865 e47a 3c 9)
"'" 1<01.'<
1»: lEV
0866 e47c a6 la lnA 126
0867 e47e b7 94 STA BIT
0868 e480 36 7a I<>R OAT
0869 e482 36 7b FOR OAT. 1
0970 e484 ]6 7c FOR DAT.2
0871 e486 36 7a FOR nAT
0872 e488 36 7b roR OAT. 1
087] e48a 36 7c OOR [lA,T.2
0874 e48c b6 7c 11)A OAT. 2
0875 e48e e7 7f STA TMFGRP.1,X
0876 e490 b6 7b InA OAT. 1
0877 e492 e7 7e STA TMK)RP.X
0878 e494 03 c9 be BRCLR 1, srAT2,lVI'4 GROJp CClMPlEI'E -,
0879 e497 ae 08 IB
0880 e499 e6 7d
0981 e49b e7 85
"""
TI<LP
CDX
IDA
srA
'rnPGIU'-LX
GRClJP-l,X
0882 e49d Sa DFCX
0883 e4ge 26 f9 ENE TXLP

81
0885
0886
0887 lpdate PI code, lI11tlallse If ~~h.al\ged
0888 All block 1£ Ul>ed, block Js not used
0889
0890
0891
0892 e4aO b6 86 lIlA ...;ROOP CCffi'ARE PI WITH I'REVIUJS
0893 e4a2 bl 8f mp PI
0894 e4a4 2606 BNE WDX
0895 e4a6 b6 87 lIlA GRUJP.l
0896 e4a8 b1 90 CMP 1'1+1
0897 e4aa 27 10 'El;) erYL
0898 e4ae b6 86 IN!lX lIlA GRalP DIF'Frnrnr, SAVE N&I PI
0899 e4ae b7 8f grA PI
0900 e4bO b6 87 lIlA GRaJP .. l
0901 e4b2 b7 90 STA PI .. 1
0902 e4b4 ed eb e6 JSR CLRfX>j CLEAR B.JN.
0903 e4b7 cd e8 Oa JSR CLTR TRANSIENTS
0904 e4ba 18 e9
0905
BS'" 4, STAn AND INITIALISE DISPLAY DATA

0906
0907
0908 tp:iate PrY and TP
0909 All block 2£ Ul>ecL /lot block 4 (grp lSB)
0910
0911
0912
091) e4bc b6 88 PrYL lIlA GRClJP.2
0914 e4be b7 95 STA ITHPI
0915 e4eO 05 95 04 BRCLR 2, ITMPl. TPI..1 TP HIGH ~
0916 e4e) 16 ca
0917e4e52002
BS'"
BAA
3.SJ'AT3
TPL
YES, FI..AG HIQl

0918 e4c7 17 ca TPLI BCLF 3. SfAT 3 1<1, Cl»;J l.CW

0919 e4e9 b6 89 TPL IDA Gf<OJP.)
0920 e4cb 36 95 f<1R l'J'MPl
0921 e4cd 46 RCRA
0922 e4ee 44 LSRA
0923 e4cf 44 [.SRA
0924 e4dO 44 [.SRA
0925 e4dl 44 LSRA
0926 e4d2 b7 8e m PrY
0927
0929
0929
0930 Grcx.lp; handled.
0931
0932 All PI. Pl'Y " TP
0933 oA " B TA, PS 01" MIS
0934 1 A "- B PIN
0935 2 A RT
09]6 4 A cr
09)7 14 A roN
0938 15 B TA. Dr " Mrs
09)9
0940
0941
0942
0943
0944 Process grcJl.lpS 0 " 15B (PS !. TAl
0945
0946
0947
0948 e4d4 b6 88 WA GROJP.2
0949 e4d6 a4 f8 AND I$FS
0950 e4d8 27 Oa BEQ ORPO GRWP OA
09S1 e4da al 08 G\P 1$08 GROJP OB
0952 e4dc 27 06 BEl;) GRPO
0953
0954 e4de al f8 'ffiRP1S G\P 1SF'll GRClJP 15B
0955 e4eO 27 10 BEl;) TACK
0956e4e2 2057 BRA ""CCI
0957
0958 e4e4 b6 89 GRPO illA GRrl)P.3 (J"RO_:P (J PS " TA
0959 e4e6 a4 0) AND 1$01
0960 e4eB 48 [.SLA
0961 e4e9 97 TAX
0962 e4ea b6 8e InA
0963 e4ec e7 el srA
0964 e4ee b6 8d lIlA
0965 e4fO e7 c2 STA
0966
0967e4f2 3f 79 eLf< f<l)STO
096Be4f4 08 89 04 BRSIT 4.GRQIP.j,'I'AH
0969 e4f7 15 ca Eel}< 2, STAT) 1.("'"
0970e4f920 02 BRA "rD
0971 e4fb 14 ca srAT"' Til. FLAG H I~;H
"'''' i, YES

82
097)
0974
0975 PrOCe!iE g::oop 0 &. 15B (Dr &. MIS)
0976
0977
0978
0979 e4fd b6 89 WA GROJP.J
0980 e4ff a4 0) AND 13
0981 eSOl 97 TAX
0982 eS02 b6 89 illA GROJP.)
098) e504 a4 40 AND 1$40
0984 eS06 5d TS'I'X
0995 eS07 26 07 BNE NOrO
0986 e509 11 bO OCLR 0.01
0987 e50b 4d TSTA
0988 e50e 27 02 .EJ;) NOrO
0989
0990
e50e
eS10
10
a3
bO
01 .ora
.S""
OP'
0.01
II
0991 e512 26 07 BNE NOn
0992 e514 13 bO BCLR 1.01
099) eS16 4d TSTA
0994
0995
0996
0997
e517
eS19
eSlb
e5ld
27 02
12 bO
a) 02
26 07
.,::'" .=
.EJ;)

OP'
BNE
NOr!
1.01
12
NOr2
0998 e5lf 15 bO BCLR 2,01
0999 eS21 4d TSTA
1000 eS22 27 02 .EJ;) NOr2
1001
1002
eS24
e526
14 bO
a3 03 1m2
BS""
OP'
2,01
13
1003 e528 26 07 BNE NOr)
1004 e52a 17 bO BCLR ).01
1005 eS2e 4d TSTA
1006 e52d 27 02 .EJ;) Non
1007
1008
e52f 16 bO .S"" 3,D!

1009 eS31 11 ca 1m) BeLR O.STAT) MIS

1010 e533 07 89 02 BROLR ). GROJP~). MSZ
1011 e536 10 ca
1012 eS)8 ee e6 18 M52
BS""
JMP
Q,STAT)
our!
1013
1014
1015
1016 PlOCeES group 1 (PIN)
1017
1018
1019
1020 eS3b al 10 PROC! mp 1$10 GRWP lA
1021 eS3d 27 04 aEJ;) GRP!
1022 e53f al 18 mp 1$18 GRCl.lP 1£1
1023 e541 26 Ob BIlE ?ROC,
1024
1025 eS43 b6 8e GRP! tnA GRCJJP~6
1026 eS45 b7 91 rJrA PIN
1027 e547 b6 Sd tnA GRCUP... 7
1028 e54" b7 92 rJrA PIN. 1
1029
1030 e54b ee e6 18 JMP om
1031
1032
1033
1034 Process gloup 2A (RT)
1035 Group 2B rjot handled
1036
1037
1038
1039 e54e al 20
1040 eSSO 26 )0
PRCC2 "'P
BNE
1$20
PRCC4
GROJP2A

1041
1042 e552 08 89 07 GRP2 BRS"" 4. GRWP~ 3. TEXI'B
1043 eSS5 02 ca Oc TE<rA BRSET 1. S'l'AT),N::H
1044
1045
eSS8
eSSa
12
20
ca
OS
BS""
BRA
1.S'l'AT3
LeDIN!
1046 eSSe 03 ca OS TE<ra BRCLR l,STAT3,t>CH
1047 eS5f 13 ca BeLR 1. STAT]
1048 eS61 cd eb aa LeDIN! JSR mITO
104"
1050 eS64 b6 89 !<::H WA GRCUP.3 GRWP 2A RT
1051 eS66 a4 Of AND I$OF
1052 eS68 48 LSLA
1053 e569 48 LSLA
1054 e56a 97 TAX
1055 e56b b6 9a WA GRCfJP.4
1056 e56d d7 01 OS srA RJ'.S.X
1057 e570 b6 9b lIlA GRUJP.S
1058 eS72 d7 01 06 srA RT.6.X
1059 eS75 b6 8e lIlA GRClJP+6
1060 eS77 d7 01 07 rJrA R!'+7.X
1061 e57a b6 8d illA GReJJP.7
1062 e57e d7 01 08 rJrA RT.8.X
1063 e57f ee e6 18 ,'MP 0l!Tl

83
1065
1066
1067 Precess grOOJp 4A (CI')
1068
1069
1070
1071 eS82 al 40 PR<X:4 Q'lP IS40 GRWP 4A CT
1072 eSS4 27 03 BEl;) GRP'
1073 eS86 ee e6 Ib JMP PRCC14
1074
1075 eS89 b6 89 GRP4 iDA GROJP • .,
1076 eS8b 46 lORA
1077 eS8e a4 01 AND ISOI
1078 eSSe b7 74 sr. iMJD KJD MS 8IT
1079 eS90 b6 Sa lDA. GROJP.4
1080 eS92 46 lORA
lOBI eS93 b7 75 SI'A. g.un .. 1
10B2
10B3 e59S b6 8e IDA. GROJP.6 GROOP 4
10S4 e597 36 8b R)R GRClJP.S 3210xxxx 4
lOBS eS99 46 lORA 43210xxx x
1086 e59a 44 ['sRA -43210xx x
10B7 e59b 44 ['sPA --43210x x
lOBS e5ge 44 ['sPA ---43210 x
10B9 e59d b7 ge ST. CUR
1090
1091 e59f b6 Sb
1092 e5al b7 76 KJV LSD
109).
1094 e5a3 h6 Be IDA GROJP+6 ;.o;:xx5432 x
1095 e5aS )8 3d LSL GRO)P.7 )()(xxS432 1
1096 e5a7 49 ROLA xxx:"4321 x
1097 eSa9 )8 3d LSL GROJP.7 xxxS4321 0
1098 eSa.a 49 lOLA xx543210 x
1099 e5ab a4 :H AND I$>F' --543210 x
1100 e5ad b7 9b SlA. MIN
1101 e5a! 3f 911. CLR SEC
1102 e5bl 3f 99 CLR TIl8
1103 e5h) Ie ca BSE'!' 6, STAT) UPDATE KJV
1104
1105
1106
1107 l..ocal time dlfferenee adJustment,
1108
1109
1110
1111 e5b5 b6 8d lDCAL UlA
1112 eSb7 48 [.SIA
1113 eSb9 27 Se BE>;) am ADJUSl'MENI' ?
1114 e5ba 24 n Bee rus YES. POS IT IVE -:
1115
1116 e5lx 44 [.SRA 00. NEGATIVE
1117 eSb:l. 44 LSRA
1118 e5be 44 [.SRA
1119 eSbf 44 [.sPA
1120 e5cO 97 TAA HOURS n! x
1121 eSc! 24 Oe Bee NOTHN 1/2 HOUR ",
1122 eSc3 b6 9b CDA MIN YES
112) eScs aO Ie SUB 'lO SlfB'rRAC"T )0 KlturES
1124 eSe7 2a 04 BPL LT60 lNDERFLfW ?
1125 eSc9 ab 3e }\DD .60 YES ADD 60 MIlVI'ES
,126 e5eb 3a 9c 00:: CUR AND SUBI'RAcr 1 HCUR
1127 e5cd b7 9b LT60 srA MIN
1128
1129 eScf 9f NCmlN TXA NEGATIVE HOJR (f'FSE'!'
1130 eSdO bO 9c SUB MUJJS ure HOURS
1131 eSd2 43 CU<A W'l.CNG WAY rot.ND >Xl CQ>1PLE}!ENT
E32 eSdJ 4e INCA AND JNCFrnENT
1133 eSd4 2a 14 BPL t.NOCl<Fl.JJr.I?
1134 eSd6 ab 18 IIDD YES. ADD 24 HOURS
11J5 e5d8 b7 9c srA
1136
11j7 eSda. 3d 76 TST lIND SVW'RAcr A DAY
1138 eSdc 26 08 ENE LSB WI LL UNDEl<F1f..w ?
1139 eSde 3d 75 TST YES
1140 eSeO 26 02 B>IE MSB WI LL UNDrnF'I.£W ?
llH e5e2 3a 74 00:: YES DECREMENT MS BIT
1142 e5e4 3a 75 TIl 00:: D£Cru>!ENr MSB
1143 eSe.6 3a 76 TT2 00:: D£Cru>!ENr [.SB
:144 e5e8 20 2e BPA
1145
1146 e5ea (,7 ge ZOM srA
1147 e5ee 20 211. BRA
114g
1149 e5ee 44 fOS LSRA
11:.D eSef 44 l.SRA
1151 eS!O H l.SPA
11'>2 eSf1 44 [.SRA
U53 e5f2 97 TAA HOURS rN X

.
:"1:'4 eSD 24 Oe Bee wrHP HALF HWR ?
1155 eSf5 11.6 Ie lI>A .30 YES ADD)O MllUI'ES
ll.56 eSt7 bb 9b lIDO MIN
1157 e5f':! 11.1 3b o<P ..,~

1158
1159
e5 fb
e5fd
23
11.0
04
3c
BLS
Ml
=
160
~?
YES. SUBTRPCT 60 MlNlJI'ES
1160 e5ff 3c 9c INC WR AND ArlD AN" HCl.JR
1161 e(iOl b7 9b IlIXN sr. MJN
1162
1163 e(i03 9f rurHP TY.A. HOUR OFFS£1'
1164 e604 bb ge IIDD CUR ADD vrc HOURS
1165 e606 11.1 17 OlP 123
116& e608 23 Oe BLS }\DDON CNE!lFtJ:>' ?
11&7
11&8
11&9
e60a
e60c
e60e
11.0
3c
26
18
7&
06
9JB
INC ".
"""'., YES, SUBTRAC'T 24 HOJRS
AND ArlD A DAY
ENE ADOON
1170 e610 3c 75 INC EMJD+l
1171 e612 26 02 ENE APOON
1172 e614 3c 74 IN:: BMJD
1173 e(i16 b7 ge ADCON SlA CUR
1174 e6lS 13 c9 curl s:.:Il< I. SlAT2 c,'RCl)P HANDlED, CJ...E.IlJ< FLAG
1175 e61a eo
""

84
ll77
1178
~ ................ ......................................
~

....................................................
1179 PrOCei;.IO group 14 (Er:'tl).
1180
1181
1182
1183 e61b al eO PR:C14 00> ISEO
1184 e61d 27 0) BEQ GRPHA
1185 e6lf ee e6 b) JMP am
1186
1187 e622 )f 9S GRP14l1 ITMP1 !JXl< F'Cl<. PI CO[lE IN TABLE
1188 e624 be 9S [oPIL WX ITMP1
1189 e626 d6 01 4S W' Ern. X
1190 e629 bl 8e C>!P (''RWP.6
1191 e62b 26 69 8NE NUfH
1192 e62d d6 01 46 U)A El:.t'.LX
119) e6)0 bl Bd C>!P GRClJP.7
1194 e6)2 26 62 ENE NOrH
1195
1196 W' GRooP.) TP (CN), NOI' USEIl
1197 AND IS10
1198 WX ITMP1
1199 Sf> FJJN.11,X
1200
1201 e634 b6 89 lDA GRClJP.) PI COOE FUND
1202 e6)6 a4 Of AND I$OF'
1203 e63S al 04 C>!P 14 PS ?
1204 e6)a 24 10 IlIlS NPS
1205 e63c 48 LSLA
1206 e63d bb 9S ADD ITMP1
1207 e6)f 97 TAX
120S e640 b6 Sa ill. GRClJP.4
1209 e642 d7 01 47 E'r' ECN.2,X SAVE 2 PS-N1\ME CHARAC"rERS
1210 e645 b6 Sb lDA GRooP.:'
1211 e647 d7 01 4S srA EON.), X
1212 e64a 20 ee BRA cvr1
1213
1214 e64c al 04
1215
1216
e64e 26 )4
C>!P
IlNE "
'T'RYPIN

1217 e650 b6 8a CRClJP.4 YES, METHOD A

121E!
1219 e652 al fa eM!' 1250
1220 e654 26 la IlNE f><U< MEDILM OR I.J:N:; WAVE ?
1221 e656 d6 01 51 W' il:tJ,12,X YES
1222 e659 al ff c><P l$eF FIRST 2 BYTES ALREADY IN ?
122) e65b 27 56 BEQ cur2 IF Nur, ro NOI'HHC
1224 e65d d6 01 53 W' EON.H,X YES
1225 e660 al ff OIP l$eF MIL FRaJt.JEN:Y ALREADY ill ?
1226 e662 26 4f ENE om IF SO, DO N:JI'HillG
1227
1228
e664
e666
a6
d7
fa
01 5)
Ul. 1250 rD. S1'ORE F'IRST FREl;lUEN:"Y AFTER
E'r' ECN.14,X ARRIVAL Of' INITIAL BYTES
1229 e669 b6 8b W' GROJPt5
1230 e66b d7 01 54 E'r' E.U*.15,X
1231
1232
e66e 20 43 BRA =2
1233 e670 al eO OIP '224 F1<
1234 e672 25 Oe "'''' BCD rooLS lEGAL ? (No. OF F'REQtJEN.::IES)
1235 e674 al f9 CK!' 1249
1236 e676 22 Oa BIll =LS
1237 e678 be 95 illX ITMPI
1238 e67a d7 01 51 srA EDN.12,X YES. SAVE tb Of' FRE(1JENCIES
1239 e67d b6 Bb ill. GRooP.:,
1240 e67f d7 01 52 Sf> EDNd3,X ANr FIRST F'RE(lUEN::Y
1241 e682 20 2f TOOLS BRA our2
1242
1243 *TRYPI'Y ISOD
1244 TRYPIN
1245 GR(lJP.4 PrY (EXN), NOT USED
1246
1247
1248
1249
1250
1251
1252
1253 e684 alOe TRYPIN CMP 1$0£
1254 e6S6 26 2b BNE our2
1255 e688 be 95 lllX
1256 e6Sa b6 Sa lll. GRruP.,
ITMP! PIN

1257 e68e d7 01 4f Sl'A EON.I0,X

1258 eMf b6 Bb ill. GRa.rp.5
1259 e691 d7 01 SO ITA EONol1.X
1260 e694 20 1d BRA am
1261
1262 e696 al ff wrH OIP END Of' PI LIST ?
1263 e698 26 Oe IlNE
1264 e69a b6 8e W' YES ADD THIS PI CCI[lE
1265 e69c d7 01 45 ITA
1266 e69f b6 8d illA ro Ern TABLE
1267 e6al d7 01 46 ITA
1268 e6a4 20 Od BRA
1269
1270 e6a6 b(;95 ,,,,nn ITMP1 tt:rr rnI), TRY NE\T ENT'RY
1271 e6a8 ab 10 ADD 116
1272 e6aa b7 95 STA ITHPl
1273 e6ae al bO OIP ISBO END eJF TABLE (11 ENI'RIES)
1274
1275
1276
e6ae
e6bO
27 03
cc e6 24 .'"
JMP
C'Jr2
LPIL
1277 e6b3 13 e9 om Kill I,STAT2 GRoop HANDlED. CtEAR Fl.A.G
1278 e6b5 80 RrI

85
1280
1261
....................................................
1282 Display type select ian.
128]
1284
1285
....................................................
1286 e6b6 09 c9 05 8RCLR 4.SI'AT2.NXL SHOJUl DISPALY BE.: INITIALISrn "
1267 e6h9 cd eb aa JSR lNITO YES. WIT
1288 e6b::: 19 c9 OCLR 4.STAT2 AND CI..EAR FLAG
1289 e6be crl eb 6c JSR WAIT
1290 e6cl a6 Oc U>A ISOC ~:rrt:HDISPLAY W
1291 e6c] cd eb 65 JSR CUXK lATCH IT
1292 e6c6 <Xl eb 6c JSR WAlT
129] LOA IS,A 116 DISPlAY
1294 e6c9 a6 )0 LOA 1$30 !8 DlSP~Y
1295 e6eb cd e:b 65 JSR CI..Cl2K
1296 e6ee <Xl eb 6e JSR WAIT
1297 e6d.1 a6 80 illA 1$80 AD[lf{£SS DISPLAY RAM
1298 e6d3 cd eb 65 JSR CUX"K U>..TCH IT
1299
1300 e6d6 06 04 Ob "'SET 3. FORTE, TRYRT SI'IINDBY ~
1301
1302
e6d9
e60c
04 cb 59
06 cb 66 "'=
"'SIT
2, SI'AT4. SLPO
3,STAT4.~
YES. SlEEP DISPLAY ~
NO. AI...ARM DISPLAY ~
130] e6df cd e8 69 JSR STBYD NO. t>l.1RMAL STANDBY DISPLAY
1304 e6e2 20 64 BRA ""'I
1305
1306 e6e4 Of cb 46 8RCLR 7,STAT4.RI'ITS RDS DISPlAYS?
1307 e6e7 b6 aE LOA Rl'DIS
1308 e6e9 a1 01 D<P II
1309
1310
e6eb
e6e::i
26
cd
05
e8 19
I><E
JSR
"PrY
Pl'YD PrY
1311 e6fO 20 56 BRA '(><1
1312
1313 e6f2 al 02 CHP 12
1314 e6f4 26 05 lNE NPI
1315 e6f6 cd e8 f. JS'
1316 e6f~ 20 4d BRA
1317
1318 e6fb cd 03 :>1P n
131Q e6fd 26 OS CJ'<: ~';t'
1320 e;:.ff cd e9 Sa JSR ['!TAF
1321 e702 20 4.l.
1322
1323 a: v4 mAP ':JoIy
1324
1325
26 OS
cd e9 "'2
ENE
JSR
"
N""t'IN:
~)F':t:: i"W HEX
:)26 2C Jb BRA R:","1
1327
1328 al05 NPWl O1P oS
1329
1330
26 OS
cde992
"''E
JSR
N1.::N;:
~)F~ P:t-.: • [lIl.Y ANT' TIME
1331 2032 B!<A RCW:
1332
1333 e716 al 06 NPDN2 0<, 06
1334 e718 26 05 BNE NKJD
13)5 e71a cd e9 f6 JSR rKJI' ><1D
1336 e71d 20 29 BRA
1337
1338 e7lf al 07
1339
1340
e721
e723
26
cd
05
eb 0]
""" O1P
BNE
JSR
P
NHSD
CMSD MIS!. Dr
1341 e726 20 20 BRA RG<1
1342
1343 ens cd ea 25 JSR DEn'
1344 e72b 20 Ib BRA PCWl
1345
1346 e72d 05 c9 05 "'ITS
1347 e730 cd e8 4a JS'
1348 e733 20 13 BRA
1349
1350 e735 O~ cb 05 BRCLR :<, STAT4.NRMD SLEEP TIMER DISP[.AY ?
1351 e738 cd ea ee JSR SLEEPO
13S2
135)
1354
e7)b 20 Ob

e7)d 06 eb 05 NlWl
B!<A

BRSET
00_
R(W1

3,srAT4,~ lU....I.J<M DISPLAY ~

1355 e740 cd e7 cc JSR
1356 e743 20 03 BRA PCWl
1357
1358
1359
e745 cd e9 ,. ALJ><J ALO<ID

1360
1361
e748
e749
Sf
cd eb 6c
=
LCD
CCR><
JSIl WAIT
1362 e74c 14 0) MEr 2,FORJ'D ~ITE u>\TA
1363 e74e e6 bl illA DISP.X GET' A BYTE
1364 e7S0 al [f eM!' 1 SIT
1365 e7S2 26 02 BN'E OOK
1366 e754 a6 2d LOA 1$2D
1367 e756 cd eb 65 CO, JSR CUXK SEND IT 1'0 MCUJLE
1368 e759 5c 1NC~
1369
1370
e7Sa
e75c
a3
26
10
eb
CPX
1M
",1£D
DONE
1371 e75e 20 Ie BAA VF'D REMJVE F'OR I 16 LCD;;
1372
1373
1374
....................................................
1375 Adciltlonal blt& fc>r 116 J£D m::dules
1376
1377 ....................................................
1378
1379 enD cd eb 6c LCD401 JSP
13BO e76] a6 a8 illA ISAB 1i..l40
1381 e765 cd eb 65 JSR ctLCK SEMI IT TO MC{JULE
1382 e768 Sf CCR><
1383
1384
e769
e76c
0:1 eb 6c
14 0)
LCD" JSR
BSEr
'~IT
2. PORrO vmrrE rYl-TA
1385 e76e e6 b9 illA DISP+8.X GET A BYTE
13B6 e770 al [ f CMP OSIT
1387 e772 26 02 BNE C""
1388 e774 a6 2d LD>. 1$2D
1389 e776 cd eb 65 001<2 JSR CUCK SEND IT TO MOflVLE
1390 e779 Sc lNCX
1391 e77a a3 08 CPI. .8 DONE'
1392 e77c 26 eb ENE
"'''' 1

86
1394
1395
1396
1397
1398
1399
1400 e77e D 01 VFO BeU< 1, roRTB OA.TA r..a< ?
1401
1402
e7S0 10 01
e7S2 17 01
BS'"
OCU<
0, roRTB
), roRTB
CLCCK HIGH ?
ENABlE u:w
140)
1404 e784 5f CLRX SEND VFD SET -UP BYTES
1405 e785 d6 e7 c5 DIS5 IllA rnITF, X
1406 e788 bf a7 srx WJ SAVEINDE);
1407 e78a ad 20 BSR VFDL
1408 e78c a) 07 CPX n
1409 e7ge 26 f5 00: DISS l.ASf BYTE -:
1410
1411 e790 Sf CLRJ( SEND 16 CHARJiCTER BYTES
1412 e791 bf a7 W03 srx WJ SAVEINDD<
14D e793 e6 bi IllA DISP,X ASCII
1414 e795 al ff CMP ISF'F'
1415 e797 26 02 FNE >rnFP
1416 e799 a6 2d IllA IS2D REPLACE $FT WITH
1417 e79b a4 7f AND 1$7F' IGNJRE BIT 7
1418
1419
e79d
e7ge
97
d6 00 ae
T""
IllA VfAE,X <XMVERT TO VFTl CHARAcrrn SET
1420 e7al ad 09 BSP VFDL
1421 e7a3 a) 10 CPX 11'
1422 e7a5 26 ea FNE VFD) l.ASl' BYTE?
1423
1424
1425
e7a7 16 01
e7a9 11 01
BS'"
OCU<
3,PORI'B
0, PORTB
ENABLE HIGH
CLCCK I.LW ?
1426 e7ab 81 FITS
1427
1428 e7ac ae 08 VFDL IllX 18
1429 e7ae 44 DIS) LSPA
1430 e7af 24 02 roo DIS4
14)1
1432
e7bl
e7bJ
12
11
01
01 DI"
BS'"
OClJ<
i. KlRTB
0, PORTB
j)/I.TA HIGH
CLOCK
1433
1434
e7b5
.,,7b7
10
13
01
01
BS'"
Be'"
0, roRTB IT

1435
14)6
e7b9
e7ba
5a
26 f2
DEC'
FNE DIS3
COMPlEl'E
NJ
>

14)7 e70c ae 40 11'X 164

1438 e7be Sa ffiL D<X:X WAIT 200uS
1439 e7bf 26 Ed ENE [n
1440 e7el be a7 11'X WJ RESfORE nmEX
1441 e7c3 5c INCX
1442 e7c4 81 ras
1443
1444 e7cS aO Of bO 00 80 00 INITF SAO. SOF'. $BO, sao, S80. S00, $'10
90
1445
1446
1447
1448 Nornal display (PS arrl t)JTte)
1449
1450
1451
1452 e7cc a6 20 NCru-ID LI:l'<
1453 e7ee b7 bl STA
1454 e7dO b7 ba STA
1455 e7d2 b7 cO STA
1456 .,,7d4 a6 :ie lllA
1457 e7d6 03 cb 05 BRCCR INDICATE SlEEP TIMER RlNNIN::
1458 e7d9 05 99 02 BRCCR IT
1459 e7dc b7 cO STA
1460
1461 e7de 5f TIP1
1462 e7df e6 el MPS PSN,Y. GET PS NAME
1463 e7el e7 b2 ~ISP+l ,X
1464 e7e3 5c
1465 e7e4 a3 07 n
1466 e7e6 23 f7 MPS
1467
1468 e7e8 b6 9c OJ LDA OJR GET TIME
1469 e7ea oj eb 84 JSR COCD
1470 e7ed a) }O CPX 1$30
1471 e7ef 26 02 £WE ONZ
1472 .,,7f1 ae 20 WX 1$20
1473 e7f3 bf Cb wz STX DISPdO
1474 e7f5 b7 be srA DISP.l1
1475 e7f7 b6 9b "'IN CDA MIN
~476 e7f9 cd eb 84 JSR COCO
1477 e7 fc bf be srx DISP.13
1478 e7fe b7 bf srA DISP.t4
1479 e800 a6 20 CSIX LDA 1$20
1480 e802 05 99 02 BReW< 2,TIl8, ax
1481 e805 a6 3a 11'A I$)A O. 5 Hz FLASH ING CO[£N
1482 e807 b7 b:l STA DISPd2
1483 e809 81 ras
1484
1485
1486
1487 Clear d15play tran51ent Elags
1488
1489
1490
1491 e80a 11 cb CLTR ECLF cu;:1tR (1ISPLAY TRAN.SIEN'J' F'LAC
1492 e80c 15 c9 OClJ< N;:l'J' RT DISPlJ>.Y
1493 e80e 3f af CLR CL.EAf( RDS DISPLAY INT)f:."
1494 e810 17 cb OCLR N:JT .r..LARM DISPLAY
1495 e812 Ib cb BeLR N:l'J' ALARM SET-ln'
1496 eS14 1£ cb EClF NCJr RDS DISPLAYS
1497 e816 15 cb EClJ< mr SL.EEP TIMER DISPLAY
1498 e818 81 RrS

87
1!100
1!101
....................................................
1!102 PrY display
150)
1504 ....................................................
1505
1506 e81' be Be PI'YD ID. PrY PrY
1507 e8lb ill) 10 CPX '16
1508 e81d 25 01 BID XCt::2
150' e81f !If CUO<
1510
1511
e820
e822
0116 10
42 ""'" IDA 11'

"'.
KlL
1512 e82) b7 a8 ....
15ll e82S If a7
1514 e827 be 0118 I.eD)
CLR
ID' ....
WI

1!115
1516
ee2'
aB2e
d6 ec ae
be 0117
IDA
lDX
Pl'V'l'.'
WI
1517
1518
151'
e82e
e8)0
e8)2
e7 hI
)c a8
)c 0117
"'.
INC
INC
[lISP.X
....
WI
WAS Klf12

1520
1521
1522
e8)'
e8)6
e8)8
b6 0117
0111 10
25 ed
LOA
o<P
Bll!
"".>'
U:'1)"1
152) e8)a 81 RrS
1524
1525
1526
....................................................
1527 MIS display.
1528
1529
1~)0
....................................................
15)1 e8)b be aD DiSP2
15)2 e8)d e6 ff """' lDX
RI'-1.X
15))
15)4
e8)f al
e841 26
20
13
IDA
CHI' '$20
rmsp '"
SPACE?
15)5 e84) Db e9 Oc "'"
IIRCLR 5. S"l'AT2.F'SP YES. FIRSI' ct£ ?
15)6
1537
e846 )c
e848 3c
9f
0110
INC
INC
DISPI
DISP2 "'. SlCIP THIS CH:

1538 e84a b6 a.0 ",OS IDA DISP2

15)9 e84c al 45 ,"Pl o<P .69
15.0 e84e 22 18 BIll "'D4 ENI"! CE' RT ElJFF'El"t
11)41 eS50 20 e9 1-1:,. G£T NEXT CfiAAA(."I'El"t
1542
154) e852 la e9 FS,
IlAA

BS'"
"'"'"
r..S7AT2 F!f.'Z; SP,t£.·E. SET F':..4G
1544 e854 20 02 BAA CCl'I'I'
IS45
1546
1547
e8S6
e858
e85a
Ib
b7
5t
e9
a8
wrs>
CC>Ir
!ClJ>
!IT'
CUV:
...
S.S'r'AT2 rvr A SPACE. CILAA F:.AG
S;..:.;r.. ~ CHARAC"I'E}!

1548 e85b e6 b2 ILPI IDA [,ISP.l.X ""VE

1549
1550
e8S<!
e8Sf
e7 bl
"'.
W:.(
DISP.X i>ES'T
LEPr

.
5e
1551 e860 a) Of CPX lIS eN:
1552 e862 26 f7 IN£ I:"PI Pl.ACE
1553 e864 b6 aB ID.
1554 eB66 b7 eO "fA DISP.!5 ArlD f'&l ~HAf<. (WAS HOC2;
1555 e868 81
"". RrS

....................................................
1556
1557
155B
1559
1560 Starldby display.
1561
1562
156)
....................................................
1564 e869 08 cb 4f
"''''0 ,,",..-r 4.STA14.AUW\ ALARM AAJ£II ?
1565 e86e b6 73 UlA 1('w ~'. ~ tiAy CF WiEI<
1566 eB6e 48 I..SLA
1~6'1 e86£
1568 e071
hb
97
71
""0
1A.":
1569 e872 d6 ec: 72 IDA [NAME. ~:
1570 e87~ b7 bl ST" D:SP
1571 eOn d6 ec: 73 IDA UU'1'JE.l.Y.
1572 e87a b7 b2 sr. DISP.l
1573 eB7c d6 ec: 74 LOA ~NAME-02.X
1574 eB7f
1575 e881
b7
a6
b3
20 "'. r!ISP.2
1$20

"'"'..
WI
1576 e&BJ b7 b4 rJISP.)
1577 eB85 b7 b7 DISP.f.,
IS78 e887 b7 bb sr. DISP.lO
1579 eBB9 bf.. 72 IDA D".t4.1 D1.7r:
15BO e88b ab )0 .rc> '~)O
15Bl 88Bd b7 b6 sr. DISP.5
1582 e88t b6 71 IDA IU<
158) e891 27 02 BOlO AD020 If' Zrn0 USE A SPACE
1584 e89) ab 10 ADD IS10 iF NOI' MAKE ASC II
1585 eB95 ab 20 AOO 1$20
1586 e897
1587 e899
1588 889b
b7
be
b6
I»
70
6f
""'20
"'.
lllX
IDA
DISP.. 4
IW''''
IM'H
KmH. LSD
MJNl'H. MSD
158' e8\1d 27 04 .m ""'z
15\10 e89f \If TXA
151ll e8aO ab Oa ADO 110
1592 e8a2 97 TAX
1!>9) e91') bE a.8 "'HZ sr. wa
1594 e8a5 9f TXA
15\15 e8a6
1596 e8a7
1597 e8a9
4B
bb
97
a8
l.SlA
ADO
TAX
...
159B e8aa d6 eo:: 87 r-tlAME·j.X
1599 dad b7 be
l.C>'
sr. DISPo7
1600 e8af d6 ec: fIB IDA toIIlAM£-2.X
1601 e8b2 b7 b\l sr. t>lSP .. 8
1602 e8b4 d6 eo:: 89 U~ 1f"W(E-1, x
160) e8b7 b7 b6I sr. DISP.9
1604 e9b9' 20 Id BAA
"''''''

88
1606
1607
....................................................
1609 Stllndby (alann arnted~ diGplay
1609
1610
1611
....................................................
1612 efibb b6 ge ALI><A illA POOR GET ALARM HOURS
1613 eBbd cd eb 84 JSR CECD
1614 e8cO bf bl S'I'X OISP
1615 e8c2 b7 1>2 srA 01SP .. 1
1616 eBc4 b6 9d LOA AMIN
1617 eBc6 cd eb 84 JSR CECO
1618 e8c9 bf b3 srx DISP .. 2
1619 e8cb b7 b4 srA DISP,3
1620 e8cd 5f CLRX
1621 e8ce d6 eb f) AWP2 WA AU\RMS+l,X
1622 e8dl e7 bS srA DISP+4, X
1623 e8dJ 5c n<:X
1624 e8d4 a3 06 CPX 16
1625 e8d6 23 f6 BLS AWP2
1626 e8dB b6 9c illA CJJR GET TIME
1627 eBda cd eb 84 JSR COC'O
1628 e8dd a3 30 CPX 1$30 lEADING ZERJ ?
1629 eBdf 26 02 ENE 1m
16JO e8el ae 20 illX 1$20 YES. MAKE IT A SPACE
1631 eBe) bf be 1m srx DISP .. 11
1632 e8e5 b7 W STA DISP .. 12
1633 e8e7 b6 9b UJA MIN
1634 e8e9 cd eb 84 JSR COCD
1635 e8ec bf bf STX DISP.14
1636 eflee b7 cO srA DISP,lS
16)7 eBfO a6 20 LOA 1$20
1638 eB f2 05 99 02 BRCLR 2,TH8,DI'F FLASH?
1639 e8f5 a6 3a UJA 1$3A 0.5 Hz FLASHING COl.Ctl'
1640 e8f7 b7 be DrP STA DISP.13
1641 e8f9 81 FITS
1642
1643 .................................... u ..............

1644
1645 PI dll.plilY
1646
1647
1648
....................................................
1649 5f oIPI CLRX
1650 d6 ec 02 DWP UJA PlSI',X
1651 e7 bl STA DISP,X
1652 Ie INC)(
1653 a3 Of CPX III
1654 23 f6 BLS DWP
1655 b6 Bf illA PI
1656 27 10 BED PlNV
1657 cd <,,1:> 48 JSR SPLIT
1658 bf be STX DISP>ll
1659 b7 W STA DISP>l2
1660 b<5 90 LOA PhI
1661 cd eb 48 JSR SPLIT
1662 bf be srx mSf'.13
166.3 b7 bE Sf A DISf'd4
1664 81 PUN RTS
1665
1666
1667
~ .... ... ....... ..................................
~ ~ " ~ ~

1668 Alarm di5play

1669
1670
1671
....................................................
1672 e9la Sf ALl>ID CLRX YES
1673 e9lb d6 eb f2 ALOP tnA ALARMS. X
1674 e91e e7 bl STA DISP.X
1675 e920 5c INC)(
1676 e921 a3 Of CP;'; 115
1677 e923 23 f6 BLS ALLW
1678 e92:S 09 cb 31 BRCLF 4, SI'AT4,A'J;F2 ALARM ARMED .,
1679 e928 a6 }a tnA 1$3A YES
1680 e92a b7 W STA DISP.12
1681 e92c b6 ge tnA "'<JR G£1' AL.ARM HOURS
1682 e92e cd eb B4 JSR C£CD
1683 eg31 a3 30 CPY, 1 S~O LEAD me ZEKl :-
1684 e933 26 02 EM: nn
1685 e935 ae 20 LDX 1$20 YES, KAKE IT A SJ:'ACE
16B6 e937 bE bb s-rx DIS,'. "0
1687 e939 b7 be STA DISPdl
168B e93b b6 9d U<A MIN
1689 e93d cd eb 84 J';R CEl.;D
1690 e940 bE be Sf> D1SP.13
1691 e942 b7 bf STA DISP,14
1692 e944 Ob cb 12 BRCLF 5,SI'AT4,A.r.,a"2 SET-UP ?
1693 e947 OS 99 Of BRCLR 2,TH8,AJ.££2
1694 e94a a6 20 LIlA IS20
1695 e94c Oc cb 06 BRSOT 6,~AT4,FH OOVRS ?
1696 e94f b7 be STA DISh 13 N:>. F'LASH Ml!VI'ES
1697 eg5l b7 bf m DISP.14
169B eg53 20 04 BAA AWe2
1699 e.955 b7 U:>
1700
1701
e.957
eg59
b7
81
be '"
AWe2
STA
STA
DISP.tO
DISP.II
YEs. FLASH HClJRS

1702
1703
1704
.. ~""'"''''''''''''''''''''''''''''''''''''''''''

1705 TA 0. TP flagG dlSpl",y

1706
1707
1708
............. ......................................
~

1709 e95a 5f O1TAP CLRX

1710 e95b d6 ec 12 BLOP L['A TAPST, X
1711 e95e e7 bi '''fA DIS~'. X
1712 e960 Sc IN(~

1713 e96l a3 Of CPX Ii ~,

1714 e963 23 f6 BLS 841P
1715 e965 a6 )1 LOA IS:!1
1716 e967 07 ca 02 BRCLR 3.S"I'AT).TPI..LW T1' FLAG HIGH
1117 e96a b7 b7 STA OISP .. 6 YES. DIS1'l.A.Y
171B e96c 05 ca 02 TPlL>< BRCLR 2.SJ'AT3,TAti:loJ TA FlA.G HIGH
1719 e96f b7 bE Sf A DlSP.14 YES. OISPl.A,Y
1720 e971 81 TAw.; RrS

89
1122
1123
....................................................
1124 PIN display£:.
1125
1726
1127
....................................................
1128 e912 Sf ""])Il CUI><
1729
1730
1731
e973
e976
e978
d6
e7
5e
e<: 22
bl
PLOP
.,..
11\\

INC..
~'INSTI.
DISP,>:
X

1732 e979 .3 Of CPX m

17)) e97b 23 f6 Bl.S PWP
1734 e97d b6 91 IDA PIN
1735 e97f 27 10 BEQ PI_
1736
1737
1738
e981
e984
e986
cd
bf
b7
eb 48
be
b::I
.,..
JS.
.,.. SPLIT
DISP.. U
DISP.. 12
1139 e988 b6 92 l1lA PIN. 1
1740
1741
1142
e98a
e98d
e98f
eel
bf
b7
eb 48
be
bf
.,...,..
JS. SPLIT
DISP.13
[lISP.14
1743 e991 81 PIlON RrS
1744
1745 e992 Sf OPlN2 CL.RX
1746
1747
1748
e993
e996
e998
d6
e7
Se
e<: 32
b1
PlDP'
.,..
lDA

lNCX
PINST2.>:
DISP.>:

1749 e999 .3 Of CPX tl!.

1750 e99b 23 f6 BLS PLON
17S1
1752
e99d
e99f
b6
27
91
to
lDA
.."
PIN
PII'I'N
"',..
1753 e9a1 44 l.SRA
17S4 e9a2 44 l.SRA
175S e9a3 44 l.SRA
1756 e9a4 cd eb 84 JSR COC[l
1757
1758
e9a7
e9.9
aJ
26
30
02 ...,
<ex 1530
""'0
1759 e9ab ae 20 LOX 1$20
1760 e9ad bf b3 Dl'NO sor. [lISP.2
1761 e9af b7 b4 sorA DISP.)
1762 e9b1 a3 31 C,", 1531
176) e9b) 27 24 .." >Ol'RD
1764 e9bS a1 )1 CMP 1531
176S
1766
e9b7
e9b9
26
a6
08
73
1M:
LIlA
=ST
I.
1767
1768
1769
e9bb
e9bd
e9bf
b7
a6
b7
bS
74
b6
"'.
LIlA
ff':A
flISP.4
I,
~:SP.~,
1170 e9el al 32 NOrsor CMP IS)2
1771 e9r:J 26 »8 !tIE t<o:lF.
1172 e9d a6 6e LnA I!:
1773 ege7 bl b!. sorA ~':SP.4
1774 ege\l a6 64 :.oA I'::'
177S egeb bi b6 sr.~ :;:r.sb~·
1776 eged al :n NC1rN[ OHP lSI:'
17,..,
1778
e9cf
e9dl
26 08
a6 '72
"IE
LllA ,,
~t:':'FI

1779 e9d3 b7 b5 !IrA D!SP.4

1180 e9d5 a6 64 LIllI ,·d
1181 e9d7 b7 b6 srA DISP.5
1182
1183
e9d9
e9db
b6 91
a4 '07
>Ol'RD tDA PIN HWR'
1784
178S
e9cH
e9df
be 92
58
AND
lDX
ASLX
"
PIN.. 1

1186 e9eO 49 roLA

1787 ege1 S8 ASLX
1788 e9e2 49 roLA
1789 ege3 cd eb 84 JS, COCO
1190 e9e6 bf btl sr. DISP.1Co
1191 e9eS b7 Ix: sr. IJ1SP.11
1792 e9ea b6 92 LOA PIN. 1 MIW'I'£S
119) e9ee a4 3f AND IS3F'
1794 e9ee cd eb 84 J£R COCD
119S e9 fl bf be sr, mSP.1J
1196
1797
e9fl
e9f5
b7 bf
81
sr. [,ISP.14
Rr'
1198
1199
1800
....................................................
1801 KJD dlsplay.
1802
1803
1804
....................................................
180S e9f6 ad 21 auo BSR SMJO
1806 e9f8 b6 5d IDA MJO
1807 e9fa 27 Ie .." MJINV
1808 e9fe ab 30 ADO 15)0
1809
1810
e9fe
eaOO
b7
b6
bb
5e
S'r'
LOA
DISP.. IO
MJo.l
1811 ea02 ab )0 AlXl 1$30
1812 ea04 b7 be: sr. DISP+ll
1813 -.06 b6 Sf LOA MJo.2
1814 ea08 ab )0 AOO IS)O
1915
1816
-.Ott
MOe
b7 b:l
b6 60
S'r'
LDA
DISP.12
MJo.3
1917 eaOe ab )1) ADO 1$)0
1818
1819
ealO
ea12
b7 be
b6 61
S'r'
tt>A
DISP.13
KJ[I.4
U2» ea14 at> 30 .W ISJO
1921
1822
eaHi
eaIa
b7 tof
91 MJlNV
S'r'
Rr'
NoSP.14
182)
1824 eal~ Sf S><J1) CU<)(
182S eala d() ec 42 MlDP lDA KJDST.X
1826
1827
ea1d e7
MlfSc
bl S'r'
INCX
DISi'.X
1&2& ea20 a3 Of CPX m
1829 ea22 2) f6 Bl.S HWP
18)0 ea24 !n Rr'

90
1832
lS33
....................................................
1834 ED-l display
1835
1836
1837
....................................................
1838 ea25 cd ea 19 OEm JSR "'JD CLEAR F'REl;)I..ID.cY CHARACTERS
1839 ei!1128 b6 af WA Rr[llS
1840 ea2a aD 08
1841
1842
ea2c
ea2e
ae
42
10 """
WX
MJL
18
116

1843 ea2f 97 TIC<

1844 ea30 a,6 20 LOA 1$20
1845 ea32 b7 b9 STA DISP~8
1846 ea.34 b7 bao STA DISP~9
1847 ea.36 d6 01 47 WA EDN~2,X DISPLAY PS (EW'
1848 ea39 b7 bl STA DISP
1849 ea3b d6 01 48 WA EDNd,X
lSS0 ea.3e b7 b2 STA DrsP.1
1851 ea40 d6 01 49 WA ErtJ.4,X
1852 eo43 b7 b3 STA DISP.2
1853 ea45 d6 01 4a WA ErtJ.5,X
1854 ea48 b7 b4 STA OISP.3
1855 ea4a d6 01 4b lnA EDN.6,X
1856 ea4d b7 b5 STA DISP.4
1857 ea4f d6 01 4c WA EJ::N.7,X
laS8 ea52 b7 b6 STA DISP.5
1859 eaS4 d6 01 4d WA EDN.8,X
1860 _57 b7 b7 STA DISP.6
1961 _59 d6 01 4e WA EDN.9,X
1862 _Sc b7 b8 STA or SP~ 7
1863
1864 eaSe d6 01 52 WA EON.13,X
1965 ea61 al od Q<P 1205 FILLER ~
1866 ea6) 26 04 BNE NFIL
1867 ea65 Sc lNCX
1868 ea66 d6 01 52 WA EXt<.l\,X YES, TRY AGAIN
1869 ea69 a.l fa NFIL Q<P 1~50 MEDILH/I..(l4G -:
1870 ea6b 27 43 BETJ ML¥iF
1871
1872
1873
ea6d
ea6f
ea71
al
22
ae
cc
3e
Oa FDK2
Q<P
BIll
WX
1204
"".,
110
"'.
'Me
~C»<?

1874 ea73 42 J<JL

H!7S ea74 ab 2e ADD 1$2E CALCULATE F"REl:UN:Y (BINARY)
1876 ea76 b7 a1 STA WI
1877 ea78 9f TXA
1878 ea79 a9 22 ArC 1522
1879 ea7b b7 a2 STA W2
1980 ea7d cd eb If JSR IX'CN2 CX'NVERI' ro DEr.:D-IAL
1881
1882 ea80 b6 34 TYP£) lnA Q.4 [lISPLAY VHF EON F'Rf.Q,JEN:Y
1883 ea82 26 02 ENE
1884
1885
ea84
eaS6
a6 fO
ab 30 N'lI
LOA
ADD
""
I$FO
1$."\0
1886 eaS8 b7 l::b STA mSP>lO
1887 ea8a 97 TAX
18Sa ea8b b6 35 WA
laS9 eaBd 26 06 ENE
1890 ea8f a3 20 CPX
18'H ea91 26 02 ENE
1892 ea93 a6 fO LOA
1893 ea95 ab 30
1894
1895
ea97
ea99
b7 be
b6 36
'"'' Aro
srA
WA
1896 ea9b ab )0 f.ro
1897 ea9<:l b7 t:d STA
1899 ea9f a6 2e LOA
1899 ea.a.l b7 be srA
1900 eaa) b6 )7 WA
1901 eaaS ab )0 Am
1902 eaa7 b7 bi seA
1903 eaa9 b6 38 lnA
1904 eaab ab 30 AOO
1905 eaad b7 cO srA
1906 eaaf 81 rna<2 RrS
1907
1908
1909
ea.bO
eabl
Sc
d6 01 52
INC'
WA EON+l),X
DISPLAY MIL Ef.t< FREr.l!')EN:;Y

1910 eab4 al Of CMP IlS

1911 eab6 23 02 BLS tmG
1912 eabS ab lb ADD l;ti "'" OFFSET
1913
1914
ea.ba
eabe
ab
ae
10
09
ADD
WX
01'
19
MIL (RF'SE:I'

1915 eabe 42 MJL

1916 eabf bE a2 S'I'X W'2
1917 eac1 b7 al STA WI
1918 eacJ ad Sa BSR rCCN2 C~'T':)BC.T1IN\!
1919 eac5 b6 3S WA Q.\
1920 eac7 26 02 00; IF' TJ-KJUSANDS OF' kHz A ZER:J
1921
1922
eac9
eacb
a6
ab
fO
30 "'3
CDA
AOO
""
I$FO
1$30
DISPLAY AS A SPACE

1923 eacd b7 ba srA DISP.9

1924 eacf b6 36 CDA 0.6
1925 ead1 ab )0 ADD 1$30
1926 ead3 b7 bb STA DISPdO
1927 eadS b6 37 CDA 0>7
1928 ead7 a.b )0 AOO 1$)0
1929 ead9 b7 be STA DISP.l1
1930 _db b6 38 CDA H
1931 eadd ab 30 ADD 1530
1932 eadf b7 t:d STA DISP.12
1933 eael a6 6b in>. I k
1934 eae) b7 be srA DISP.13
1935 eae5 a6 48 LOA I H
19)6 eae7 b7 bE STA DISP.14
19)7 eae9 a,6 7a LIlA I'!
1938 ea.eb b7 cO STA [lISP. IS
1939 ea.e::i 81

91
1941
1942
1943 SIMp display.
''994'4'
'94' eaee 5f
1941 SLEER) CLIlX
1948 eaef d6 ec 52 SLOP IDA SLPST,X
1949 _f2 .1 bl 'irA DISP,X
1950 eaf4 Sc:: lNCX
1951 eaf5 013Of CPX US
1952 _f1 23 f6 B... SIDP
195) mf9 b6 18 IDA SLEPI'
1954 eafb cd fib 84 JSR Cl<:D
1955 eafe bf b9 S'l'X DISP.8
1956 ebOO b1 ba 'Ir' DISP.9
1951 eb02 81 Rl'S

..
1958
1959
,,
1960

1962
MIS " DI display.
1963
1964
1965 eb03 Sf D4SD CLRX
1966 eb04 d6 ec 62 lLOP IDA HSDST,X
1961 eb01 e1 b1 !1rA DISP,X
1968 eb09 5e 1NCX
1969 ebOa a3
Of CPX liS
1910 ebOc:: f6
23 B... IIDP
1911 ebOe 01
ca 04 IlRCLR O. S"I'AT3,HSM2 HIS FI..,A(:: SEl'
1912 ebll a6
4d IDA I'K· YES, MJSIC
1973 eb13 b1
b1 'irA DISP.6
1974 ebl5 bO
b6 IDA 01
1975 eb17 cd at> 84 JSR COCO
1976 ebla bf be STX DlSP.13
1977 eblc:: b7 bf 'Ir' DlSP.14
1978 eble 81 Rl'S
1979
1980
1981
1982 Convert. binazy t.o uPpacked BCD in Q.
1983
1984
1985
1986
1987
1988
eblf
eb21
eb23
ae 54
bf ad
cd ef 86
oca<! 1DX
S'l'X
JSR
.....,
IR

CLRAS
CLEAR

RR
1989
1990
eb26
eb28
3c:: 5c
cd ef 84
11«:
JSR
Ro'
0Ul
R~· 1
CLEAR IQ
1991 eb2b 016 De
1992
1993
eb2d
eb2f
b7 .6
34 a2 lOOP2
IDA
"'A
!.SR
'"
W6
W2
14 BrrS TO CQfoJE:Rl'
I<>VEwr
1994 eb31 36011 IQR W, FIRST (LS) BIT
1995 eb33 24 07 BCC »<T ZEro
1996
1997
1998
eb35
eb)7
eb39
ae 30
bf Ole
cd ee 33
lDX
STX
JSR
....,
IQ

ADD
00:. Are
CI.JRRrnT VAUJE
C>'R
1999 eb)c ae 54
:aooo
2001
eb3e
«AD
bf ae
cd ee 33
"'" lDX
STX
JSR
IR
I<JM2
ADO
ADD R
ro
ITSELF
2002 eb43 3a 016 IEC W6 ALL
2003 eb45 26 e8 alE WOP2 [(.tI£?
2004 eb47 81 Rl'S
2005
2006
2007
2008 Split A ni.bbles int.o A ([.S) and X (MS)
2009 and o:mvert to MCII.
2010
2011
2012
2013 eb4897 SPLIT TAX HSD rnTO X. ['sD INro A
2014 eb4999
2015
2016
eb4a
eb4b
56
99
"'"
""""
2017 eb4c::
56 "'"
2018
2019
eb4d
eb4e
54
54
""""
LSRX
LSRX
2020 eb4fa3 39 CPX IS3'1 S30-S31.1 .. - 0-\0
2021 eb5123 07 BLS XOK
2022 eb53Sc:: 1NCX
2023 ebS4Sc 11«:X
2024 ebS5Sc 11«:X
2025 ebS65c:: 1NCX
2026 ebS7Sc:: 1NCX
2027 ebS85c:: 1NCX
2028 ebS95c:: 1NCX
2029 eb~ 014 Of XOK AND ISOF
20)0 eb5c:: ab )0 Am IS30
2031 ebSe 011 39 c.'MP 1$3'1
20)2 eb60 23 02 BLS AD,
203) eb62 ab 07
2034 eM4 81 ADIC ADO
Rl'S "

92
2036
2031
....................................................
2038 selld and clock data to LCP no::dul~
2039
2040 Check. to see if LCD nodJ Ie 1 S busy
2041
2042
2043
....................................................
2044 eb6S b1 02 C=K "'A roRI'C
2045 eb67 18 03 BS'" 4.roRJ'O
2046 eb69 19 03 OCLR 4. rorao CLeeK IT
2047 eb6b 81 RrS
2048
2049 eb6c 15 03 . .IT O::LR 2.roRrO
2050 eb6e 16 03 BS'" 3. FORTO READ LCD MCnILE wS't FlAG
20S1 eb10 19 03 ocu. 4.fORI'O
2052 eb72 3f 07 CLR IORrCD WRIT CN PCRl'(.'
2053 eb74 18 03 WLOOP BS'" 4. FOrao Cu.cK HIGH
2054 eb76 b6 02
2055 eb79 1903
IDA
OCLR
IORrC
4. FeRrO
READ """ILE
= K U><
2056 eb7. b1 .7
2057 eb7c Oe a7 fS
2058 eb7f 33 07
STA
BRSE:T
CO<
'1IORrCD
"•' ...n.W!.£X)P El)S't ?
aJ1'PlII' ~ IURl'C
2059 ebB1 17 03 OCLR 3, FORTD
2060 ebB3 91
2061
2062
2063
........................................................
RrS

2064 Hex->BCD converSl.on (& declJll!ll adjust)

2065
2066
2067
..........................................................
2068 ebB4 ad Ie CBCD BSR UP)(
2069 eb86 ad 13 BSR ADJI OO:IMAL ADJUst'
2070 eb88 b7 a7 OCD SAVE
2071 ebSa ab 16
STA
ADD '1$16
"' ADD $16 (BCD 10)
2072 eb8e ad 08 BSR ADIU ADIUST
2073 eb8e Sa [£eX
2074 eb8f 2a f7 BPL OCIl 'I\AJ FAR ?
2075 eb91 b6 a7 IDA YES. RES'roRE A
2076 eb93 ee eb 48
2011
JMP '"'SPLIT
2018 eb96 28 03
2079 eb98 ab 06
2080 eb9a 81
ADIU ..."
ADD
RrS
ADJI
16 """"""'"
YES

2081
2082 eb9b ab 06 ADJI ADD 16 1<). BJT IS LS DIGIT
2083 eb9d 29 02 BIlCS ARTS BIO:::~ THAN !i ?
2084 eb9f aO 06
2085 ebal 91 ARTS
st"
RrS
16
"'. RESI'ORE

2086
2081 eba2 91 UP)( TAX
2088 ebaJ 54 LSRX
2099 eba4 54 LSRX
2090 ebaS S4 LSRX
2091!!ba654 LSRX MSB IN X
2092 eba1 a4 Of AND I$OF' LSB IN A
2093 eba9 81 RI'S
2094
2095
2096
....................................................
2091 LCD lnitlallsation.
2098
2099
2100
.....................................................
2101 ebaa a6 aO INITD Ln'. I SAO
2102 !!bae e1 01 00 STA Rr SPN:ES BE:NE:EN Pl'V • RT
2103 eba.f e1 0101 STA RTd
2104 ebb2 e1 01 03 STA RT+)
2105 ebbS e7 01 04 STA RT.'
2106 ebb8 a6 2d
2101 ebba e7 01 02
Ln'.
STA ",.,
1$20
DASH BEl"riEEN EXIst'ING DISPLAY" RI'
Th'ITIALISE RADIO'I'O:T TO SPACES
2108 eblx1 a6 20 LOA 1$20
2109 ebbf ae 05 LOX 15 AFTER COOF' LOSS 00 TE>.'T A/B CHANGE
2110 ebcl Q7 01 00 CLOP STA RT.X
2111 ebc4 5e IN<~
2112 ebcS 43 45
2113 ebc7 26 f8
CPX
BNE
16'
CLOP
2114 ebc9 3f 9f CLR DISPI INITIALISE SCROLLIr.x; FOINJ'ERS
2115 e:bcb 3f aD CLR DISP2
2116 ebccl. 3f 8e OCR PIT CLEAR F'I'Y
2117 ebcf 3f 91 CLR PIN AND
2118 ebdl 3f 92 CLR PIN.l PIN
2119 ebd3 3f bO CLR DI AND DI
2120 ebd5 11 ca O::LR Q,S'I'AT:! AND MIS
2121 ebd7 17 ca OCLR 3.h"'I'AT3 CLE'AR TP FLAG
2122 ebd9 15 e9 O::LR 2,h"'I'AT2 CAtCEL I"('I' DISPLAY
2123
2124 ebdb Sf CLRX
2125 eb::l.c a6 2d LI~ 1$2D
2126 ebde e7 el PLOP) STA PSN. X CLFAR PS NAME
2121 ebeO 50:: IN<~
2128 ebel a3 08
2129 ebe3 26 f9
2130 ebe5 81
....
CPX

RTS
"
PLOP)

2131
2132 ebe6 Sf CLREXN CLRX
2133 ebe7 a6 ff LIlI\ ISIT
2134 ebe9 d7 01 45 EWP STA "".X fXN RAM CLFAR
2135 ebec 5e
2136 ebed a3 bO =
CPX 1116
2137 ebef 26 f8 BNE EWP
2138 ebfl 81 RrS

93
2140
2141
2142
2141
2144
214!;
2146 ebf2 20 20 41 6C' 61 7;! ALAI<>« Ft'C ":,1111' U"'F
6d 20 2d 20 20 4f
46462020
2147 ec02 20 ~O 4!1 20 63
64 6~ 20 2d 20 20
of Phi'!,
""- Pi ,-..: ..it'-

20202020
2148 e::12 20 ~4 ~O 20 2d 20 TAI'S'l' >IX TP - Ll TA 0
30 20 20 ~4 41 20
2d 203020
2149 ee22 20 ~O 49 4e 20 t>e PIN!>'T1 R'C PIN 'I('
6f 2e 20 2d 20 20
:W 2020 20
21~0 <K'32 20 20 20 20 74 68 PINST2 Ft:C ttL .u
20 61 74 20 2d Zd
2e 2d 2d 20
21~1 ec:42 20 4d 4a 20 64 MJ~-
7920 2d 20 20 20
20 202020
61 MJPST
"'"
ZI~2 ec:~2 20 53 6c 6~ 65
202020 )0 20 6d
70 .LPST eo" sleep Ornul.

69 6e 2e 20
2153 ec:62 20 4d 2f 53 20 20 MSDST Dl 0
532020204449
2020)020
"'" HiS S

2154
21S~
2156
21~7 MJD day iUld 1I(,lLt h St r lIIYS,
2158
2159
2160
2161 ec72 4d 6f be 54 75 65
576564546875
46n 69 ~) 61 ;4
5J 7~ 6e
2162
2163 ecai 6~ be 76 F'X
2164
2165 ecBa 4a 61 6e 46 65 62 tf'W(E fT:C
4d 61 72 41 70 72
4d 61 79 4a 75 6e
4a 75 6c 41 75 67
5365704f6374
4e 6f 76 44 65 6)
2166
2167
2168 .................................................. ..
2169
2170 Pro'J[<lJllne'I"JPe :VI'Yi Co.:ies
2171
2172 .................................................. ..
217)
2174 ecae tie 6f 20 70 72 6f Pr'n P:': :LC 1=If<":ICt.I,.tjll:o€:
677261 6d 2074
79706520
217:' ecbe 20 20 20 20 20 2'~ F\'("' ~j~:;:
4e 65 77 73 20 20
2020Z020
2176 ecCE' 4) 75 '2 72 65 6e r:c' ,"lfr"n: ... !f"'_n"
74206166 M 61
69727:120
2177~2020496e666f :lLf~,n"~tl'-C.
72 6d 61 14 69 6f
6e 20 20 20
2178 ecee 20 20 20 20 20 5) FCC; ~,rt
70 6f 72 74 20 20
20202020
2179 ecfe 20 20 20 45 64 75 FCC Fducation
63 61 74 69 6f 6e
20202020
2180 edOe 2G 20 20 20 20 44 ,"0 tlraflla
72 61 6d 61 20 20
20202020
2181 edle 20 20 20 20 4] 75 R:'" ::1..Ilture
6c 74 7S 72 61) 20
20202020
2182 ed2e 21} 20 20 20 5) 6) ",0 i'~I~I-:e
69 65 6e 63 65 20
20202020
218) ed3e 20 20 20 20 20 56 F".,(, 'Jan"o
61 72 69 65 64 20
20202020
2184 ed4e 21} 20 20 SO 6f 70 P':C k>p mlSl<:' I,
20 6d 7S n 69 6]
20 20 20 20
2185 edSe 20 20 20 52 6f 6) Ft:C 1< ..:'" /fIUSl': Ii
EI:> 20 6d 7S 73 69
6)202020
2186 Ed6e 20 45 61 7) 79 20 FCC "''Y lU:t~lIl.lI'i1 I'
6c 69 7) 74 (1) 6e
69 6e 6i 20
2187 ed7e 20 4c 69 67 68 74 Light clasSICS
20 6) tic 61 7) 73
69 63 73 20
"'" D

2188 ed8e 53 61) 72 69 6f 75 'Serious classics' 14

i3 20 6) 6c 61 7)
73 69 63 73
"'"
2189 edge 20 20 4f 74 68 (1) R:"" e·ther ItnJSl.': I'
72 20 6d 75 7) 69
63 20 20 20

94
2191
2192
2193 VFrl character set
2194
2195 FOI01t1Cfl HI table 15 A9:::1I value
2196 Entty 1& the \IFTl character used
2197 Last colu!Hn shows cnar.-acten; nvlaced
219B by Gpace.: SOO to $IP are ASCII oc,utrol
2199 charactel!> and Gh:>uld" t occur
2200 halO been e"tered as
2201 I has been elltered as -
2202 • hal> beel! e"tered as
2203
2204
2205
2206 Edae 7e 7e 7e 7e vrAB Fe, $7£,$7£, $7£, S7£ 'll
2207 e::J.b2 7e 7e 7e 7e Fe, $7£, $7£,$7£, S7£ ,11
2208 edb6 7e 7e 7e 7e Fe, $7£,$7£,$7£, $7£ .11
2209 e:ll::a 7e 7e 7e 7e Fe, $7£, $7£. 57£, 57£ .ll
2210
2211 edbe 7e 7e 7e 7e Fe8 $7£ $7£. $7E, S7£ .11
2212 edc2 7e 7e 7e 7e Fe, $7E.S7£, $7£,57£ .ll
2213 edc6 7e 7e 7e 7e IT' S7£,$7E,$7E,S7E .11
2214 edca 7e 7e 7e 7e IT, $7E.$7E,$7E.$7£ .11
2215
2216 edee 7e 7b 7a 7e IT, S7£,$7B,57A,$7E I
2217
2218
edd2
edd6
7e
7e
7e
7e
7e
7e
701.
7e
IT,
IT,
S7£, $7E. S7E.S7A
$7E. $7E, $7£.$7£
S"
.11
2219 ed:ia. 3f 7d Je 7d ITS S3F'. $70, $3£, S7D
2220
2221
2222
edde 00 01
ede2 04 05
02
06
03
07
Fe,
IT,
0 1
\
.<223
2224
ede6 08 09
edea 7e 7e
7d
7e
7e
7c
"OB
ITB
9

2225
2226
2227
edee
edf2
7e
Od
Oa Ob Dc
Oe Of 10
8:' 8

2228
2229
edf6
aHa
11
15
12 13 14
t6 17 18
""
"'B
K"
F
J
N C
2230
2231 edfe 19 la Ib Ie Fe8
2232 ee02 Id Ie If 20 FeB
2233
2234
2235
ee06
eeOa
21 22 23 7e
7e 7e 7e 7d
FeB
fI" ,,-
I

2236 eeOe 7a 24 25 26 FeB ,

2237 ee12 27 28 29 2a. FeB "f
2238
2239
2240
ee16
ee1a
2b
2f
2c
30
2d
31
2e
32
"'8
"'8 m : 0

2241 eele )) 34 35 36 feB

2242 ee22 37 38 39 3a 8:, v
224 J
2244
ee26 3b
ee2a 7e
3c 3d 7e
7e 7e 7e
fl'B
fl'8
7 C
.ll
2245
2246
2247
2248
2249
225G
2251 t'klt:r.Y D:Vlde,
2252 n('r:~ h ".nd ye""r
2253
2254
225S
2256 Ttar.sfer 0[ ocr· nUJTlUel-S
2257 i~:\ c- :N..:M:, Xpre.,.erv-=d
2258
2259
2260
2261 ee2e bE ae :LEAR ~!ESTINATIW
2262 ee30 cd eE 86 Atm ""-'"'[I IT T(, l'b AT NU,\l
2263
2264
2265
2266
2267
2268
2269
2270
2271
2r2 ee33 3f aD ADD :L..R
2273 ee35 bE a7
2274 ee37 bE as AD ,;,"c:...'EJ', ",:,:tJrEP
2275 eeJ9 a6 09 ~'A
2276 ee3b b7 ac
2277 ee3d be ad
2278 ee3! bE a3
2279 ee41 be Ole
2280 ee43 bE a4
2281 ee45 be 013 Wi
2282 ee47 e6 08 illA
2283 ee49 3<> <>3 C€C
2284 ee4b be a4 ~:X
2285 ee4d eb 08 ArC
2286 ee4f 3a a4 DEC
2287 eeSl bb ab A..T ",DIT,:t< O/UiFU...•..
2288 ee53 3E a.b CLR kESlJLj sUB'rPA.jFN
2289 ee55 ad 11 SSR ADJ1JST
2290 ee57 be as illX
2291 ee59 e7 08 STA SA'if ANSWER
2292 ee5b 3a as D£C
2293 eeSd 3a ac ocr:
2294 eeSf 26 e4 EI<E
2295 ee61 be 017 UIX
2296 ee63 81 fITS
2297
2298 ee64 aO 001 AJ YES SvrAAL"T 1 U
2299 ee66 3c a.b A.>.JD RE('()Rl)CAJ<Ri
2300 ee6B 011 001
2301 ee6a 24 f8 10
2302 ee6c 81 N".

95
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m€'lIt 1119 (X~RB:;-ND) of K'V mlllverf;

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ee6d bE a6 ~'"fX AN~-"'Il-l< f\JjNJ'D!

ee6f ad 06 asR ':Is I,'\l'!,' Sf)"N[I NJMBD!
ee7l 3f a.b CLk :~ET \ :.AfiFY 1\) (JNE
ee7) )c at. INC B£j.l'kE AfJ[IING
ee7S ad cO BSR Al)[IF\k-:I't-JJMB1:J.l

een be ae ':IS C(:MPLll>!ENT

ee79 ad 0) SEL'(>N'[I NttffiER
ee7b be at. k£'s"l'clRE AN~' ~'!NTD<
ee7d Ell

ee7e a6 09 l.IJA INTI

ee80 b7 ac S'"fA ,~x,r...t!f

eeB2 a6 09 lJ,.l::W3 ~ I~09

eeB4 eO 013 SUB Nf\-l.X
eeE!6 e7 OE! S7A ND-1.X
ee88 :,a c<o<
ee89 3a ac [€C cO.m
eeBb 26 fS ENE U:::OP1
ee8d 81 RTS

ee8e ad ee ('-11P }"'MFL:MENT THUl

ee90 a6 09 INO FI::JR TDlS CCl<!PL IMENr
ee92 b7 ac O:ilNf ,,':TH X ~ R.Er~-tJD
ee'l4, 6c 11 2'NlJ-l X
ee96 e6 11 ~ ·~![l.: ..
ee98 ill 001 I;'.'"
ee9a 25 0'1 RE":'".1'el
ee9<: au )01
ee~e ",'" 11
ee",C' Sa
eea: 3a ac
eeaJ 26 et
eeaS 61

eea6 ae ~4 MJ:_:r
eea8 cd e: B~
eeab ae 4b
ee.ad C'd ef 86
eebO ae 12
eeb2 bf a6
eeN ae 0"
eet.-S e6 4:
eeb8 bf a:
eeba b7 at,
eet.:- Ole :,
eet..e et 2:
eec: u ~ a~
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ee::-4 ut at
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eec'" 34 at
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eedB bf a2
eeda be a6
eedc eb 4a
eede cd ee 68
eeel e7 4a C2
eeeJ b6 at;,
eeeS eb 49
eee7 e7 49
eee9 b6 a3
eeeb 1:,7 at;,
eel:d Sa
eeee bf a6
eefO be a2
eeL! 20 OJ
eef4 Ja a6 ~'E' F<,~ :.'r.'EJ.
eef6 Sa ~€ ;., :.'1:'0'
eef726cS
eef9 b6 a6
eefb ab OB
eefd t,,7 d6
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ef06 ~l

96
2406
2407
2408 Divil1.iOfl of B::D flwrbers
2409
2410 R .;- P / Q, rermiILder ilL TMP
2411 on exit X " If{. n-!Q w;ed
2412
2413
2414
2415 efa7 ae 54 DIV [1)X IR CLEAR
2016 efa9 cd ef 86 JSR CLRAS REStJ[..T
2417 efOc ae 42 [1)X IP 1'RANSFffi
2418 efOe bE ad srx tuMI PR>
2419 eflO ae 4b illX 11'>1" W::JRKINt;
2420 ef 12 cd eEl 2e JSR TRA P (TM!")
2421 eU5 ae )0 illX IQ TRANSF'ER
2422 eEl? bE ad srx tuMI Qro
242) ef19 ae 39 illX ITt<> >DF<J<lNG
2424 eUb cd ee 2e JSR TRA Q (Tt-Q)
2425
2426
2427
ef1e
ef20
a6
b7
09
ac
POSS illA
srA
IND
cum "-'ME'"
DICITS
2428 ef22 ae )9 rooP6 illX ITt<> FIND LEASI' SIGNIF'ICANI'
2429 ef24 f6 illA O.X 1'Cl'l-z.E:R:J DIGIT
2430 eE25 26 07 !I'lE NOSH ZEro?
2431 eE27 cd ef 64 JSR SHIPI' YES. SHIFT Q
24)2 ef2a 26 f6 1M: rooP6 UP CNE PLACE
24)J ef2c 20 33 ZQ BRA RTf<' Q WAS Z£R'J
24)4
2435
24)6
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24)7 ef)2 ae 4b [1)X ITMP SUBI'RAC'T Q
24)9 ef)4 bf ad Sf X tuMI rna.
24)9 ef)6 cd ee 6d JSR SUB P
2440 ef)9 b6 ab WA CAAAY TCXl FAR ?
2441
2442
ef3b
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27
be
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al
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illX
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IF' YES. 00 TO ND.1' DIGI1'
INC."REMENT RELEVANT
244) eDE 6c 5) INC R-l. X DIGIT IN RESULT
2444 ef41 20 ef BRA SIJBB CN::'E AGAIN
2445 ef4) ae 4b NEXTD WX ITMP roo FAR ADO
2446 e[45 cd ee )) JSR ADD 1,,) BALI': UN
2447
2448
ef48
ef4a
ae
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2449 efk b7 ac ITA C'CANI' WJRKING Q
2450 ef4e e6 07 RRR lnA ND-2.X torll/E ALL
2451 ef50 e7 OB srA tID-l.X DIGITS
2452 ef52 Sa oa~ ,,><'
245)
2454
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2456 ef59 )c al INC WI IN('REMEN'T WOOER
2457 eE5b b6 al [1)A WI
2458 efSd al Oa Cl<P INO.I FINISHED ?
2459
2460
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2461
2462
e(6) 81 RTS "
2463
2464
2465 Shlft
2466
2467
2468
2469 ef64 b7 a) Sf A '''3
2470 eE66 cd ef 79 JSR [1n WI 1.(£0, .",~, l.S[
2471 ef69 be al lDX
2472 ef6b e6 01 illA 1.)0: MJVE ALL DIGITS
247) ef6d f7 Sf A O. X uP UNE PLACE
2474
2475
ef6e
ef6f
5c
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=,
CP;';
2476 eE71 26 f8 <m: OJNE '
2477 ef7) b6 aJ CDA YEs RR'Cl\fill. N&<' [)lGIT
2478 enS f7 ITA AND ~ur iT IN L..SD
2479 ef76 )a ae 00:
2480 ef78 81 FITS
24B1
2482 en9 bf al Dill SIX WI ::-"1'Chl f.\)lllI'ERS
24B) ef7b a6 08 [1)A IND-l iUSED rn DIGIT AND DC,l)
2484 end 5e AXL INCX
2485 ef7e 4a CECA
2486 ef7! 26 fc !>lE AXL
2487 efBI bf a2 srx W2
2488 efB) 81 FITS
2489
2490
2491
2492
249)
2494
2495
2496 ef84 ae )0 CLQ UlX
2497 ef86 bf a5 CLRAS SI'X
249B efBB a6 09 CDA CL£~ N,::, DIGITS
2499 ef8a b7 ac srA S'I'.IIJ(J'IN::3 AT X
2500 efSc 7f OR OCR
2501 efBel 5c nn
2502 efBe 3a ae OCC COlm
2503 ef90 26 fa ENE -=-'k
2504 ef92 be as U"
2505 ef94 B1 RTS

97
2507
2508
2509 M..T[l - dly (It ..-k and ye,ol .
2510
2511
2512
[001 :::
Y'
(MJ[l+2}KJD7 (= WD-l)
::: 00'( (KJD-15078.2}J3652500)
,""',
(YR)
2513
2514
2515
2516 ef95 ae 5d MJOC LDX ,.,0
2517 ef97 bf ad S'l'X NlMI
2518 ef99 ae 42 lD' .P
2519 ef9b cd ee 2e JS. TRA P ".- MTO
2520 efge ae 5d 1DX ,.,0
2521 afaO cd [0 83 JS. TIOK KJD <- KJD TIMES 10,000
2522
2523 e[a3 ae 39 00m< ill' IP-ND
2524 efaS cd ee 90 JS. ADDI P ~- KJD • 1
2525 efa8 ae 39 lD' IP-ND
2526 efaa cd ee 90 JS. ADDI P <- MJD • 2
2527 efad ae 30 1DX 'Q
2528 efaf cd ef 86 JS. <LOAS
2529
2530
2531
2532
2533
efb2
efb4
efb6
efb9
efbb
a6 07
b7 38
cd ef
b6 <;3
b7 73
07
IDA
STA
JS.
IDA
STA
"
C.J.+N[I-l
OIV
'n'IP.N[J-l
0:"
..-
().:-7
(KJDt2}/7
REMAINrEJ.: (wrl-l) IN 1'MP

2534
2535 efM ae Sd 1DX II1.TD
2536 efbf bf ad S'l'X NlMI
2537 e[c1 ae 30 ill' '0
2538 efc3 b[ ae S'l'X NLt<2
2539 efc5 cd [0 98 JS. TReY Q <- c:Y (1<;0782000)
2540 efc8ae 42 lD' IP
2541 efcacd ee 6d JS. SUB p.- lOK(I-lJD-15078.2)
2542 efodcd fa 43 JS. TRV'I Q ~- 3652500
2543 efdOcd ef 07 JS. DlV FI ,,- Y I (MJD-l~,(J78.2) 1365 .25)
2544
2545
efd3
efdS
bf
ae
2546 e[d"! cd
ad
66
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lDX
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rRA Yf,: •.•

2547
2548
2549
2550 1110 - !Iont hand ci;.y.
2551
2552 M = ::lrr''M....Tn-149~,..;.1-I~n''·' '\'::~' 2~>;;/.I'J6'J'.:, ·P)·
2553 [l = MJD-14«St.-INI'(Y '1\\', ~r,i -II'1!'IM" ':I\J .6Ct(ll) 'C!(;.:lOI') •
2554
2555
2556
2557 efda cd fa 61:.
2558 efdd ae 5d
2559 efdf bf ad
·JSI"<
W.;
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.MJ[I
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2560 efel ae 42
2561 efe3 bf ae
2562 efe!> cd fa b9
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TRWl pc-14956100tJ
2563 efe8 ae ]0 lI'X
2564 efea. cd ee
2565 efed b[ ad
6d JSR
....,
'Q
SUB

2566 efef ae 54
2567 eff1 bf ae
2568 eff] ae 42
STX
lDX
STX
lDX
...." ,
IP
2569 eftS cd ee 6d JS. ruB P c- l(JKlKJD-l49:'6.1-II'1!'(Y·'36S.2S))
2570 eH8 cd fa ae OS. rnn, ';,<- 3')Ii'."Jl
2571 effb cd ef 07 JSI< r:v ? < - M MJ(>-149~~, I-INT'Y ·~6~. 2',
2572 eHe bf ad
2573 fOOO ae 42
2574 f002 cd _ 2e
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wi':
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2575 f005 b6 49 IDA P.Nu-2 SA'JE M
2576 f007 b7 6f STA Mt.r.:'H
2577 [009 b6 4a L£:A P.t/!>-l
2578 fOOb b7 70 SifA M'rrH.:
2579
2580 fOOd cd fO ae JSI< TPIll! • ,- I'J,"u0:
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2582 faD I:.f ad STX "'-"I
258) f015 ae 39 LD:{ I'IM'.!
2584 fa 17 cd ee 2e JSI< TI<A 'l'J'\~ ,- :IJK (I!'r."M 'Jt'. ,,'JO:; .
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2589 (02) cd ee ))
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2591 [028 ae 42
2592 [02a b[ ae
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2593 f02c cd fO b9 JS. TROOI P,,-149S610UO
2594 f02f3f47 <LI> P.ND~4 P <- 14~S6000c..
2595 fOll ae 54
2596 f033 cd ee 33
lDX
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2605 f047 1:07 71 STA [l)M

98
2607
2608
2609 MJD - fi"al conectlOiL of year I. uLClCLth and ,lib,
2610
2611 If W " 14 or 15, then K " L else K " 0
2612 Y " Y' • K
2613 M "M' - 1 - K"12
2614
2615
2616
2617 f049 b6 6f ANU2 lnA IM'H !<mH.
2618 f04b 27 lb KE02 o'
2619
2620
f04d
f04£
b6
27
70
11 """
UJA ..".".1
KEOI
I<J
O?
M'= 10 THRU 15

2621
2622
f051
fa 53
",1
25
04
13
"""
OIP
Bu)
14
KE02
I<J. M'= 11 TIiRU 15
LESS THAN 14
2623 £055 ae 5d KEI lnX IYR-ND I<J M'= 14 OR 1:', Kd
2624 £057 cd ee 90 JSR ADDI ¥ <- Y'd
2625 f05a 3f 6f CCR .."." !<mH. MSD (-10)
2626 f05e 3a 70 m: mI'H+l OCC Me"'H
2627 f05e 3a 70 DEC .."."., AND AGAIN 1-2)
2628 f060 20 06 BRA KE02 -12
2629 f062 a6 Oa KEOI lllA 110 M'= 10
2630 £064 b7 70 STA I'Nl'H.l !Vr 10 IN LSD
2631 f066 3f 6f CCR ""'H CLEAR MSD
2632 f068 3a 70 KE02 00: mI'Hd 9<-10, L2.c-14.1S 3-8<-4-9, lO-12<-lJ -13
263J f06a 81 RlS
2634
2635 f06b ae 66 INr lnX IYR
2636 f06d bf ad STX NI.>ll
2637 f06f ae 42 LDX IP
2638 f07l cd ee 2e JSR TRA P <- Y'
2639
2640
f074
f077
cd
cd
fO a3
ee a6 HJLT1
JSR
JSR
=
>!JLT
Q <- lOK·)65.25
R <- 10K*'(' ·365, 2S
2641 £07a 3f 59 CCR R.ND-4
2642 fOk 3f Sa CCR R~ND-3
2643 f07e 3f 5b CCR R+ND-2
2644 f080 3f 5e CCR R <- lOr::(INT(Y'*36S.2S) I
2645 f082 81 ReS
2646
2647 f083 9f T10K TXA TIMES iG,OOO
2648 f084 ab 05 ADD
2649 f086 b7 al STA
2650 f088 e6 04 lllA
2651 f08a f7 o'CA
2652 f08b 5e INC.';..:
2653 fOBe b3 al CP>:
2654 EOBe 26 f8 SL~
2655
2656
f090 7£
fan 6£ 01
"'"
CLR
CCR
0./
LX
2657 f093 6f 02 CCR 2. X
2658 f095 6f 03 CCR ), X
2659 f097 81 RrS
2660
2661
2662
2663 MJD CO!L£ta!Lt~
2664
2665
2666
2667 f098 ae 09 TRCY LDX IND
2668 f09a d6 fO c3 CYL UJA CY-LX
2669 f09d e7 2f STA Q-l.X
2670 f09£ Sa DECX
2671 fO",O 26 f8 EM:
2672 fOal 81 RrS
2673
2674
2675
fOa3
fOOlS
ae
d6
09
fa ee
=
OiL
illX
lllA
2676 tOa8 e7 2f seA
2677 fOaa Sa DECX
2678 fOab 26 f8 EM: nYL
2679 fOad 81 ReS
2680
2681 fOae ae 09 TRll< !.DX
2682 fObO d6 fO de [ML illA
2683 fOb) e7 2£ STA
2684 fObS Sa [lEX.:>:
2685 {OOO 26 f8 EM: rt-tL
2686 fObS 81 RfS
2687
2688 fOb9 ae 09 TRWI enx IND
2689 fOt:b d6 fO ciS OOIL illA [(ll-l. X
2690 fObe e7 41 seA P-l,X
2691 fOeO Sa DECX
2692 fOcI 26 f8
2693 fOe3 81 "'" DOlL

2694
2695 fOe4 01 05 00 07 08 02 CY ROB 1.5,0,7.8.2.0.0,0
000000
2696 fOed 00 00 03 06 05 02 OY 0,0,),6,5.2,5.0,0
050000
2697 fOd6 01 04 09 05 06 01 001 1, ~,9. :,. t.. 1. O. 0,0
000000
2698 fOdf 00 00 00 03 00 06 [M P2B J.O.6.0,(),j
000001
2699
2700
2701
2702
2703
2704
2705
2706 fff4 Cf<G $F'FF4
2707
2708 fff4 eO 00 FDB START SERIAL
2709 fff6 e2 9d FDB TINT'B TIMER B
2710 fEfB eO 00 FDB S'CART TIMER A
2711 fffa e3 Oa FDB SDATA E\"I'EI<NAL HlI'rnRUPT & RTI
2712 fffe eO 00 FDB START SW1
2713 fffe eO 00 FDB START RESE'T
2714
2715 END

99
100
 AN463
68HC05KO Infra-red Remote Control
Tony Breslin,
MCU Applications Group,
Motorola Ltd., East Kilbride, Scotland

The MC68HC05KO is a low cost, low pin count When a key on the remote control keypad is
single chip microcomputer with 504 bytes of user pressed, the micro controller must first determine
ROM and 32 bytes of RAM. The MC68HC05KO is what key is being pressed a.nd generate an
a member of the 68HC05K series of devices which individual code for the key. The key code is then
are available in 16-pin DIL or SOIC packages. converted to a instruction code that is inserted into
It uses the same CPU as the other devices in the the transmission command which, using a defined
68HC05 family and has the same instructions and protocol, is transmitted to the television receiver.
registers. Additionally, the device has a 15-stage The command is continually transmitted as long as
multi-function timer and 10 general purpose the key is being held down.
bi-directional I/O lines. A mask option is available
for software programmable pull-downs on all of As the remote control is battery powered it needs
the I/O pins and four of the pins are capable of to use as little power as possible. This is achieved
generating interrupts. by entering STOP mode when no keys are being
pressed and effectively switches off the device.
The device is ideally suited for remote-control The micro controller comes out of STOP mode
keyboard applications because'the pull-downs and upon receipt of an interrupt request that is
the interrupt drivers on the port pins allow generated when a key is pressed.
keyboards to be built without any external
components except the keys themselves. There is
Remote Control Keyboard
no need for external pull-up or pull-down resistors,
or diodes for wired-OR interrupts, as these features The 68HC05KO has ten general purpose I/O pins.
are already designed into the device. One of these is used for the transmission signal
output leaving nine pins for the keyboard control.
This application makes use of many of the device
Of these, four pins on PortA have internal interrupt
features to control an infra-red television remote
request hardware. Using these four pins as inputs
control. The application could be very easily
allows key presses to be detected without any
modified to control any device with a similar
external interrupt hardware. This leaves the five
transmission protocol. It will run on any of the 'K'
remaining pins for outputs.
devices without modification.
Using the internal pull-down facility and the rising
Remote Control Specifications edge interrupt request on the four inputs permits
interrupts to be generated. If the five outputs are
The basic purpose of a television remote control is set to logic '1', so driving an input from logic '0'
to transmit a control instruction to the television. to logic '1' when a key is pressed, an interrupt
The instruction is generated by a keystroke on the request can be generated. Using this
remote control keyboard. The detection and arrangement a five by four keyboard matrix can be
decoding of a key press and the transmission used. An extra four keys can be controlled if the
encoding is carried out by the remote control micro Vdd line is used to drive one row of four keys to
controller. logic '1'. Therefore the maximum amount of keys
controllable becomes twenty four.

101
 VDD J311!32lI34l~
~~~~
A7 17il172l174l17a1
l.!LJ~~~
A6 1bil1b2l1b4l1b81
~l!.L.J~~
AS Jd1l1d2l1d4l1d81
~~~~
A4 ~13b e2113a e41~
80 1f1l1f2l1f4l1fSl
~~~~
AO A1 A2 A3

Figure 1 Keyboard layout with associated scanned and transmitted codes

A depressed key will set one of the input columns Transmission Protocol
to logic '1'. By scanning the columns, and setting
each row output to logic '0' and then checking if the The transmission protocol in this application is that
inputs all become logic '0', the associated row for used by the MC144105 IR Remote Control
the key can be determined. If rotating the logic '0' Transmitter. It uses a binary coded 9-bit data word
through the five output pins fails to identify a key with the LSB being transmitted first. Each bit of the
column, then the key must be connected to the transmitted signal is in the form of a bi-phase pulse
Vdd line. This process gives an individual code for code modulated (PCM) signal, whose bit coding is
each key which is a combination of the code from shown in figure 2. For a transmitted '0' there is a
the column inputs and the row outputs. This can 5121lS pause followed by a 32kHz pulse train for
then be decoded to an instruction that is inserted 5121lS. For a transmitted '1' there is 32kHz pulse
into the output signal for transmission. train followed by a 5121.1s pause. This gives a bit
time of 10241lS for all bits. This is shown as figure 2.
Figure 1 shows the layout of the keyboard on the
left and the scanned and transmitted codes on the
right. The keyboard layout incorporates the various
bit-n
television controls plus controls for TELETEXT. On
the left hand side the codes returned from
,.... --I
scanning the keyboard are shown in the upper
right-hand corner of each key and the code sent for
transmission for that key instruction are shown in '0'
the bottom left-hand corner. The I/O pins for each
row and column are also shown for each key. ,....
, ...
.,.,
1111111111111
1024115
512 115
,
'1'
I111111111111
Figure 2 Bit coding of PCM signal

102
A complete transmission command consists of The command timing in figure 3 shows that after the
several messages. Each command begins with a start transmission the message is continually
start message of nine 1's followed by the message re-transmitted at intervals of 131 ms (approximately
appropriate to the key pressed. This message is 8Hz) until the key is released. This is shown as time
repeatedly transmitted until the key is released. (c). The control timing shows the nine bit instruction
The transmission is terminated after the key is 111001110 being transmitted starting with the LSB.
released by a end message of nine 1'so The pre-bit pause is equal to two bit periods and is
followed by a start-bit of logical '1'. The pulse train is
Every message consists of a pre-bit, a pre-bit continuous during the transition between
pause, a start bit and nine data bits. The pre-bit and transmitting a logic '0' and a logic '1 '. The modulating
the start-bit are always logical '1'. The pre-bit allows pulse train has a frequency of approximately 32kHz
for the set up of the automatic gain control in the with a mark-to-space ratio of one to three.
receiving preamplifier. Figure 3 gives the exact
timing relationships for the transmissions. The signal for transmission is outputthrough one port
pin and is used to drive an IR diode amplifier circuit.

(a) (e) (e) COMMAND TIMING

(b) _ _ (b)
J'1..Jl n rL _ _ _ n r-L.-
iii i
iii i
Iii i STARTTRANSMISSION
/.1 ·_·t·r·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-.-.-.-.-.-.-.-._._._._._._._._._._._._._._._._._
i i i
~ !! i
_._._._._._._._._._._._._._._._._._ MESSAGE TIMING

'-'-'~'-'-'-:-'-'-'~'-'-'-'~'-'-'-:-'-'-'~'-'-'-'i
(1) I (0) I (1) I (1) ~ (1) ~ (0) ~ (0) ~ (1) ~ (1) ~
,
(1) i

(d):-. (I)
!J !
,. / ._._._._
._._._._._._._._._._._._.-
(e) (e)

,. .- .•.•. - ..... . MODULATION

.•.•.•.•.•.•.•.......
; ..•.....•.•..
I

,
I

(i)

Command timing lal = 32.8ms start transmission

(bl = 13.3ms start command 13 * bit time
Icl=131ms control transmission
Message timing Idl- 512J.ls Ihalf·bit timel
lei = 1.024ms Ibittimel 16/fcarrier
(fl = 3.072ms Ipre-pulse timel
Modulation 191 = 8J.lS
Ihl = 32J.ls 11/fcarrierl 16/fcarrier
Iii = 512J.ls (half·bit timel

Figure 3 Circuit timing

103
 Remote Control Operation

Figure 4 is a flow diagram showing the operation of

the remote control on power-up or reset. After the
initial set-up of the ports as inputs or outputs the
remote control goes into STOP mode. It will remain
in STOP mode as long as the device is not reset or
a key is not pressed. When a key is pressed an
interrupt request is generated. A short time delay
makes sure that it is a true key press and not noise
and also allows time for any switching effects on
the inputs to pass prior to checking the inputs.

The keyboard is then read to find which key has

been pressed and the code for the key is decoded
into an instruction and transmitted to the television.
key NO
If the key is held down the instruction is
re-transmitted until the key is released. This is pressed
useful for the instructions which count through the
television channels or adjust the volume, colour or
brightness controls.

When the key is released a terminating instruction

is sent to the receiver to inform it that the next
message received is a separate instruction. This is
useful in the case of a one time instruction like
sending a channel number. In this example the
receiver will tune to a channel only once; to tune to
another channel the key must be released and a
new instruction sequence received.

After terminating the transmission the ports are

reset ready for the next key press and the
processor returns to the STOP mode.

key still YES

pressed

Figure 4 Flow diagram

104
 Hardware

The remote control circuit is shown in figure 5. The The infra-red amplifier uses two transistors and two
hardware consists of the keyboard, the oscillator standard diodes to limit the current through the IR
and the infra-red amplifier. The oscillator can be a diodes to approximately 1A. There is a need for a
crystal or a ceramic resonator with a frequency of large capacitor close to the IR diodes because of
2MHz. The oscillator frequency is important since the high switching current of the circuit.
the transmission timing is based around a 1MHz
internal clock frequency.

5v

I RESET OSCl
2MHz

=
--
10M t220PF
-1- GND
_5v

(j)
lJ.I
-
~20PF 1
PBl OSC2
II 0
0
PBO 0') VSS
is
OJ
a:
IRQ I VDD
()
0
PAO (]1 PA7
A
0
PAl PA6
N
PA2 PA5

PA3 PA4

Figure 5 Infra-red remote control

105
 Software
The listing of the remote control assembler code is dependent upon the receiver software. In this
contained at the end of this application note. The example the eight bit instruction '14' changes the
first section of the listing sets up the ports prior to channel to number four. In another receiver
going into STOP mode and waiting for a key to be application the receiver may interpret the
pressed. PortA bits 0-3 are set up as inputs with the instruction code '14' as increase volume.
pull-downs enabled. Bits 4-7 are set up as outputs
logic '1' as is PortB bit O. PortB bit 1 is set-up as The transmission routine is entered with the
output logic '0' to switch off the IR amplifier before instruction for transmission in 'keyst3'. After the
going into STOP mode. pre-bit and the start-bit are transmitted the
instruction byte is rotated (LSB first) into the carry
The next section of code named 'presd' is the flag. A logic '1' is sent for transmission if the flag is
routine pointed to by the interrupt vector and is set after rotation and a logic '0' is sent for
entered when a key is pressed. This routine first transmission if the flag is cleared. Each bit is
calls the keyboard scanning routine to determine transmitted as shown in figure 1. The routines
which key has been pressed. It then calls the 'sendO' and 'sendl' send a pause of 512j.lS
decoding routine to convert the code from the followed by a 32kHz pulse train for 512~s and a
keyboard to a code that will be accepted by the 32kHz pulse train for 512j.lS followed by a 512j.lS
television. The start message is then transmitted pause respectively. In the situation when a '1'
and is followed by the instruction message. There follows a '0' then a pulse train of 1024~s is
is then a check to see if the same key is still being required. To avoid breaks in this pulse train the
pressed. If it is then the instruction message is 'sendO' routine checks the next bit to be
re-transmitted until the key is released and the end transmitted to see if a double length pulse train
message is transmitted. must be transmitted. The 'send1' routine then has
to check that a double length pulse train has not
As the transmission protocol requires nine data bits been sent in the previous one and a half bit periods
and only one byte instructions are being decoded a before sending a pulse train.
flag has to be set for the ninth bit of the
transmission routine. For the start and end The routine 'burst' produces the 32kHz pulse train for
transmissions this flag is set to 1 to give the nine a duration set by a count in the accumulator. As the
l's message. For all instructions the ninth bit is 0 so instruction time for setting the PortB bit 1 pin high or
the flag is cleared. low is five clock cycles then the minimum processor
clock period is derived by dividing the minimum
The decoding routine compares the code from the output state time, which is 8j.lS when the output is
keyboard scan routine with data array 'keydat'. On high, by the minimum number of clock cycles to
a match it takes the corresponding element from change this state. This gives an internal clock period
the array 'tvdat' as the instruction code for of 8j.lS/5 equalling 1.6j.lS. Adding a three cycle delay
transmission. will require an internal clock period of 8j.lS/8 = 1j.lS,
allowing a 2MHz oscillator to be used.
The values of the instruction codes shown in the
right-hand side of figure 1 are specific for the The code size is approximately 300 bytes, leaving
receiver application. Each receiver using the same memory space for more features to be added to the
communications protocol will receive the same controller.
nine bit instruction but what the instruction does is

106
 Debug
On applying power to the circuit the RESET vector signal by pressing a key the first signal out will be
will initialise the program counter at the beginning the start message of nine "s. To capture the
of the software. When examining the output at instruction the key should be held down and as the
PortB bit' with an oscilloscope or logic analyser it instruction will be continually re-transmitted then
should be noted that when trying to capture the the capture can be initiated at this point.

107
 Listing

0026
0027 ... INFRA RED REMOTE CONTROL FOR KO .1<1
0028
0029 '* WRITI'EN BY A.BRESLIN 13.1.92
0030
0031 'It THIS PROGRAM READS AND ENCODES A KEY FROM A 24 KEY KEYBOARD '*
0032 .. ro A FORM OF BIPHASE PULSE CODE MJDULATION (FeN) FOR INFRA '*
0033 '* RED TRANSMISSION. IT USES 'mE TRANSMISSION PRO'IUCOL OF THE '*
0034 ... MC144105 IR REmTE CONTROL TRANSMlTIER
0035
0036
0037
0038 0000 porta equ 00
0039 0001 porth equ 01
0040 0004 dclra equ 04
0041 0005 dclrb equ 05
0042 0008 tesr equ S08
0043 0010 papd equ $10
0044
0045 OOeO org SeO
0046
0047 oOeO keystl rmb initial code fran keyboard
0048 DOe1 keyst2 rmb keycode
0049 00e2 keyst3 rmb code transmitted
0050 00e3 dflag rmb flag for last and 9th bits
0051
0052
0053
0054 ... THE PORTS ARE SET UP USING PORTA 0-3 AS INPUTS MAKING USE 'It

0055 '* OF THE INTERNAL INTERUPT GENERATION ON THESE 110 LINES.

0056 ... STOP MODE IS ENTERED UNTIL A KEY IS PRESSED
0057
0058
0059 0200 org S200
0060
0061 0200 9a start eli
0062 0201 ad 04 wpres bsr setup
0063 0203 9c rsp
0064 0204 8e stop
0065 q205 20 fa bra wpres
0066
0067 0207 a6 fO setup lda ISfO porta 0- 3 inputs
0068 0209 b7 04 sta ddra 4-7 as outputs
0069 020b b7 00 sta porta set outputs high
0070 C20d b7 10 sta papd 0-3 pulldown
0071 020f a6 03 lda IS03 portb 0-1 outputs
0072 0211 b7 05 sta ddrb
0073 0213 a6 01 lda IS01 set porth 0 high
O{l74 0215 b7 01 sta portb
0075 0217 81 rts
0076
0077

108
0078 '* ***._ •• * ..... *** * •••• '* * .... ** ....... * *.* .... * * *. 'II' ***.* .... * 11''' '* •••• **,.. *
11

0079 '* THE KEY READ IS DECODED FOR TRANSMISSION.

0080 ,.. THE TRANSMISSION PRO'IOCOL REQUIRES A START MESSAGE OF 9
0081
0082
0083
,.. ONES FOLIDWED BY '!HE KEYPRESSED CODE. CODE IS
,.. CONTINUALLY RETRANSMITTED IF 'THE KEY IS HELD OOWN. AN END
,.. CODE OF 9 ONES TERMINATES 'IHE TRANSMISSION AND 1HE DEVICE
nns
.
0084 .. RE'IURNS 'IO STOP MODE.
0085 ,.. ** ... 'II . . . . . . . *. *** ...... *1r'" '* ....... ,.. '* ........... * *,..,...",.. ..... *'_ ...... * .... *,..,..,.. .. * •• ,..* 11''''
0086
0087 0218 ad 34 presd bsr keyscn get key pressed
0088 a2la b6 e1 Ida keyst2 save key to check
0089 021c b7 eO sta keystl if key held down
0090 021e ad 67 bsr decode decode key pressed
0091 0220 12 e3 bset Ldflag set nineth hi t to 1
0092 0222 a6 ff Ida I$ff send start data
0093 0224 b7 e2 sta keyst3 to transmission routine
0094 0226 ad 71 bsr trnmit nine one I s
0095 0228 b6 e1 sndagn Ida keyst2 send key press message
0096 022a b7 e2 sta keyst3 byte
0097 022c 13 e3 belr 1, dflag set nineth bit to a
0098 022e ad 69 bsr trnmit
0099 0230 b6 00 Ida porta check if key still pressed
0100 0232 a4 Of and t$Of end if no key pressed
0101 0234 26 Of bne endtrn
0102 0236 ad 16 bsr keyscn else check if same
0103 0238 b6 eO Ida keyst1 key pressed
0104 023a b1 e1 emp keyst2
0105 023c 26 07 bne endtrn end if not
0106 023e ae c8 1dx l$e8 delay
0107 0240 Sa tloop decx before next
0108 0241 26 fd bne tloop transmission
0109 0243 20 e3 bra sndagn
0110 0245 12 e3 endtm bset 1,dflag send end message
0111 0247 a6 ff Ida I$ff of nine ones
0112 0249 b7 e2 sta keyst3
0113 024b ad 4c bsr trnmit
0114 024d 80 rti ; re-enter stop mode
0115
0116 .. * ........ * ** '/I ** * *** '/1* * ** * '/1* '/I" * * '/1* '/I * '/I * '/I * '/I ** * ** * ** * '" * '" * '/I '" '" '" '" "'* * '" '" * '"
0117 '" WHEN A KEY IS PRESSED THE DEVICE COMES OUT OF S'IOP MODE
0118 * WE KEYBOARD IS SCANNED 'TO SEE WHICH KEY IS PRESSED
0119 * "'* * "''''* "'* '" "'* '" * '" * *'" * "' ... "' ...... * '" * "' ......... "' ............ '" "'* ...... '" ... * ...... "' ... "' ... '" "' ......... "' ... * ... "' ......
0120
0121 024e cd 02 fe keyscn jsr datwt wai t for debounce
0122 0251 b6 00 Ida porta check if key press
0123 0253 b7 eO sta keystl store inputs
0124 0255 a4 Of and ISOf mask outputs
0125 0257 27 a7 beg start stop if no key pressed
0126 0259 ae ef ldx I$ef set one row low
0127 025b 9f nxtrow txa read ouput lines
0128 02Sc b4 eO and keyst1 combine with inputs
0129 025e b7 e1 sta keyst2 store key code
0130 0260 bf 00 stx porta to find row which clears inputs
0131 0262 b6 00 Ida porta check for inputs cleared
0132 0264 a4 Of and I$Of mask outputs
0133 0266 27 Ie beg gotit zero in key-press row clears inputs
0134 0268 58 lslx check if last rCM
0135 0269 5e incx set Isb to 1
0136 026a 24 02 bee tryb try portb output if not porta
0137 026c 20 ed bra nxtrow try next porta output row
0138
0139 026e b6 eO tryb Ida keyst1
0140 0270 b7 e1 sta keyst2
0141 0272 ae fO ldx ISfO
0142 0274 bf 00 stx porta set all porta outputs high
0143 0276 11 01 bclr O,portb set portb 0 output low
0144 0278 b6 00 Ida porta check for inputs cleared
0145 027a a4 Of and ISOf mask outputs
0146 027c 27 06 beg gotit zero in key-press row clears inputs
0147 027e b6 e1 Ida keyst2
0148 0280 a4 3f and 1$3 f set individual code since last row
0149 0282 b7 e1 sta keyst2 store code
0150 0284 10 01 gotit bset O,portb set portb column high again
0151 0286 81 rts
0152

109
0153
0154 * '1llE DBCODE ROUTINE USES 'IWO ARRAYS" IT COMPARES '1llE KEY
0155 * VALUE WJ'lH 'mE ARRAY KEYDAT AND WHEN A MA~H IS FOUND THE *
0156 * CORRESi'ONDItG ELEMENT IN THE ARRAY 'lVDAT BECOMES THE
0157 * TRANSMITTED CODE"
0158
0159
0160 0287 ae 18 decode ldx '$18 data array offset to zero
0161 0289 d6 03 02 nxtel lda keydat.x look at each elEment of array
0162 a2Se bl a1 cmp keyst2 compare wi th key read
0163 028e 27 03 beq match decode if match
0164 0290 Sa decx else try next element
0165 0291 26 f6 bne nxtel nonn if no match found
0166 0293 d6 03 1a match Ida tvdat.x get key code
0167 0296 b7 e1 sta keyst2 store code to transmit
0168 0298 81 rts
0169
0170
0171 * THE TRANSMISSlai PROTOCOL REQUIRES A PRE-BIT. A PRE-BIT
0172 * PAUSE, A START BIT AND NINE DATA BITS. WHERE 'mE PRE-BIT
0173 * AND THE START BIT ARE LOGIC "1""
0174
0175
0176 0299 10 e3 trnmit bset O.dflag initialise for first bit
0177 029b ad 32 bsr sendl send pre-bi t
0178 029d cd 02 fc jsr datwt pre-bit pause
0179 02aD cd 02 fc jar datwt equalling four hal f data periods
0180 a2a3 cd 02 fc jsr datwt
0181 02a6 cd 02 fc jsr datwt
0182 02a9 ad 24 bsr send1 send start bit
0183 02ab ae 08 1dx '$08 transmit 9 data bits
0184 02ad 34 e2 nxtbit Isr keyst3 get next bit
0185 02af 25 04 bes datal send 1 if carry set
0186 02b1 ad 28 bsr senda send 0 if carry clear
0187 02b3 20 02 bra bitsnt
0188 02b5 ad 18 datal ber sendl
0189 02b7 Sa bitsnt decx countdown bits sent
0190 02b8 26 f3 bne nxtbit send next bi t if count not zero
0191 02ba 03 e3 04 brelr 1,dflag,sendOO if flag set
0192 02bd ad 10 bsr sendl send 1 as nineth bit
0193 02bf 20 02 bra endend
0194 02c1 ad 18 sendOO bsr sendO else send 0
0195 02e3 ae 18 andend Idx '$18
0196 02c5 ad 35 loopw bsr datwt delay between successive
0197 02e7 ad 33 bsr datwt transmissions
0198 02c9 ad 31 bsr datwt
0199 02cb Sa dee><
0200 02cc 26 f7 bne loopw
0201 02ce 81 rts
0202
0203
0204
0205 * TO TRANSMIT A LOGIC '1' A 32kHz PULSE TRAIN FOR 512us IS
0206 .. FOLLOWED BY A S12us PAUSE.
0207
0208
0209 02cf 01 e3 04 sendl brclr O,dflag, lastO check if last bit was zero
0210 02d2 a6 10 Ida '$10 burst if last bit was 1
0211 02d4 ad 15 bsr burst 32kHz pulse for Sl2us
0212 02d6 ad 24 lastO bsr datwt. wait SUus
0213 02d8 10 e3 bset O,dflag set flag as 1 sent
0214 02da 81 rts
0215

110
0216
0217 '* 'ro TRANSMIT A LOGIC '0' A S12us PAUSE IS FOLLOWED BY A
0218 11"32kHz PULSE TRAIN FOR 512us. IF A LOOIC '1' FOLLOWS A '0'
0219 '* THE 32kHz IS CONTINUED FOR l024us 'IO AVOID A PROCESSING
0220 '* DELAY
0221
0222
0223 02db ad 1 f sendO bsr datwt wait S12us
0224 Oldd 00 e2 04 brset O,keyst3,nextl check if next bit is 1
0225 02eO a6 10 ld. 1$10 single burst if 1
0226 02e2 20 02 bra datset data set
0227 02e4 a6 20 next I Ida *$20 double burst required
0228 02e6 ad 03 datset bar burst 32kHz pulse for S12us
0229 02e8 11 e3 belr O,dflag clear flag as a sent
0230 02ea 81 rts
0231
0232
0233 '* THE 32kHz PULSE TRAIN HAS A MARK 'ID SPACE RATIO OF 1 'IO 3
0234
0235
0236 02eb 13 01 burst belr 1, portb portb 1 low
0237 02ed 21 fe brn
0238 02ef 12 01 bset 1, portb portb 1 high
0239 02fl 21 fe brn
0240 0213 13 01 belr 1, portb portb 1 low
0241 02f5 9d nop
0242 02f6 4a dec. decrement count
0243 02f? 27 02 beq endbur end of burst ?
0244 02f9 20 fO bra burst
0245 02fb 81 endbur rts
0246
0247
0248 02fc a6 52 datwt Ida 1$52 count
0249 02fe 4a loop deca to provide 512us delay
0250 02ff 26 fd bne loop after instruction times
0251 0301 81 rts
0252
0253 0302 31 fl e1 dl bl 71 keydat feb $31, $f!, $e1, $d1, $b1, $71
0254 0308 32 f2 e2 d2 b2 72 feb $32, $f2, $e2, $d2, $b2, $72
0255 030e 34 f4 e4 d4 b4 74 feb $34, $f4, $e4, $d4, $b4, $7'
0256 0314 38 f8 e8 d8 b8 78 feb $38, $f8, $e8, $d8, $b8, $78
0257
0258 031a 11 3e 39 10 17 14 tvdat feb $11, $3e, $39, $10, $17, $14
0259 0320 12 3d 3b 2e 18 15 feb $12, $3d, $3b, $2e, $18, $15
0260 0326 13 3c 3a 2d 19 16 fcb $13, $3e, $3., $2d, $19, $16
0261 032c 00 ad Oc 07 06 01 feb $00, SOd, $Oe, $07, $06, $01
0262
0263
0264 0332 BO softin rti
0265
0266 03fa org $3f.
0267
0268 03fa 02 18 fdb presd scan keybrd on int
0269 OHe 03 32 fdb softin software interrupt
0270 03 fe 02 00 fdb start resett

111
112
 AN479
Universal Input Voltage Range
Power Supply for High Resolution
Monitors with Multi-sync Capability
By J. P. BruniQuel,
Integrated Circuits Application Lab.,
Motorola SA, Toulouse

ABSTRACT

This Application Note describes an easy to build, high performance, low cost 100W FLYBACK power
supply, able to work on any mains supply from 85 Vac to 265 Vac, from 40 Hz to 100 Hz. It is automatically
synchronised on the horizontal scanning frequency for minimum screen interference on a multi-sync colour
monitor, thanks to the versatile, high performance, low cost current mode controller MC44602P2,
associated with the state of the art switchmode power transistor MJH 1801 O.

INTRODUCTION

The MC44602 has been specifically designed to drive high voltage bipolar transistors. Its 1A source and
1.5A sink capability, with all the protection features associated with flyback power supplies, make it ideal
for this kind of application.

New multi-sync high resolution colour monitors have horizontal frequencies in the range of 31.5 kHz to
85 kHz. The switchmode power supply associated with these high resolution colour monitors must be
synchronized to the horizontal frequency in order to reduce any EMI/RFI effects visible on the screen. An
important feature for an off line power supply is that it can be automatically adapted to any mains voltage
without any hardware adaptation.

SPECIFICATION
Universal input voltage: 85 Vac to 265 Vac, 40 Hz to 100 Hz
Output voltages:
135V O.4A
87V 0.2A
25V 0.8A
16V 0.3A
6.3V 0.8A

Output power: 1OOW

Short circuit protection on all outputs
Overload protection
Minimum efficiency: 80% at full load
Line regulation: ~ ± 1%
Load regulation: ~± 1%
External synchronisation: from 31 .5 kHz to 85 kHz
Low overall cost.

113
 TOPOLOGY AND MODE OF OPERATION CHOICE

For multi output voltages at 100W output power, the best choice is the SINGLE ENDED FLYBACK
TOPOLOGY. The best price/performance ratio is offered by a combination of a high performance current
mode controller MC44602 and a MJH1801 0 switching planar power transistor.

Depending on timebase frequency and mains voltage, the power supply works in either a discontinuous or
a continuous current mode. Continuous current mode is for low mains voltage, and discontinuous current
mode is for high mains voltage and low power. The continuous current mode at low mains voltage lowers
the peak current (I Peak) on the transistor and as a consequence lowers the Vce sat. the Ibl and the losses.
At high mains voltage the discontinuous current mode allows lower switch-on losses and lower stress on
the high voltage output diode. When the output diode has to switch current, its losses are higher (Trr).

The losses on the output diode depend on its current during conduction and current during switching. In
discontinuous current mode there is no current in the diode at switch on. In continuous current mode there
is always current in the diode at switch on and the Trr of the diode (switching losses) depends on this
current. To accommodate a wide range of applications, the frequency of operation will be between
31.5 kHz and 85 kHz.

The MC44602 has a separate synchronisation input which resets the oscillator when a 5V positive pulse is
applied. Since the oscillator of the MC44602 is working at twice the output frequency, the power supply
will be synchronised at half the horizontal scanning frequency resulting in less disturbance on the screen
with the synchronisation occurring only every two lines. Another advantage is for the power transistor
which results in fewer switching losses, as it works at half the scanning frequency. Switching losses are
directly related to the switching frequency, since they are the same for each cycle. The higher the
frequency, the greater the losses.

A zener limits the input voltage to 4.7V on the sync. input. (See figure 1.) The synchronisation transformer
is a toroidal bifilar core which receives the pulses from the time base of the monitor. The sync. pulse will
have 5V amplitude and about 2 ~ width. The main noise source is the high di/dt occurring at switch off.
The power supply works at half the scanning frequency, so the impact of that disturbance is divided by two.

NOISE

TIME BASE

~----~<_/-----~
COLLEcroR
CURRENT

Figure 1 Switch off screen polution

114
 TRANSFORMER DESIGN

Since the transformer plays one of the most important parts in the performance of a flyback power supply,
due to coupling and leakage inductance, the transformer was designed around a SMT47 multislots former
and a B3 GETV 53.18.18. ferrite core from THOMSON OREGA.

The feedback from the output voltage is magnetically realised by the auxiliary winding which performs good
load, line and cross regulation, without the need for an optocoupler.

This auxiliary winding has three main functions (see MC44602 data sheet):

Self supply of the MC44602

Image of output voltage for regulation

Image of output voltage for overload detection.

Since the power supply will work from 85Vac to 265Vac, the minimum rectified voltage U is 85,t2=120V.

To provide a safety margin in worst case conditions (low mains-high power). let us choose a minimum DC
voltage U of 90V.

The maximum DC voltage is 265,t2=375V.

Assuming an 80% efficiency with an output power of 100 W, the input power Pin is 100/0.8=125W.

The maximum primary current occurs at minimum voltage U and minimum switching frequency Fs which
is 31.5 kHz/2 = 15.25 kHz.

The transformer must be calculated for 15 kHz minimum frequency.

Let us choose a maximum duty cycle of D= 0.4 for a minimum mains voltage, a minimum switching
frequency and maximum power. Then Ip, the peak current in the transistor, becomes:

A ferrite material with AL=460 nH/T can be chosen. The number of primary turns is:

115
 TRANSFORMER CONSTRUCTION

The technique used is the multi slot developed and widely used by OREGA THOMSON. Figures 2 and 3
depict the way to couple the different windings in order to achieve a high coupling; this ensures an
acceptable magnetic feedback signal and a low leakage inductance.

;».
13 ;».+.
53 35

;+ 13 ...
10 ;». ~ 31
;+ 1~ ...
7+'
.. 3 '~7 ~ 31
~
121 1 22 1 111
1 1 1 1 1
+VCC GND+VAUX COll +6.3V GN1Jt.16\GN1Jt.25V GNDt-135+87

Figure 2 Multi slot winding

Lp Primary winding split

into 4 sections <D. (i). @. ®

Laux Auxiliary winding

L1 High voHage secondary

winding split into 3 sections
0 .•.•
L2 Secondary winding V2

r::l L3 Secondary winding V3 V4

LJ

Figure 3 Physical winding position

116
For multislot construction we chose 2.13 Turns =26 Turns

Ns 135V =Np*(l-Dl*(Vs+VflNin min *D

=26*0.6* 136/100*0.4 = 53 turns =2.5V/Turn

Np=26T 0.5mm diameter

Ns 135V=53T 0.315mm diameter

Ns 87V=35T 0.5mm diameter

Ns 25V=10T 0.5mm diameter

Ns 16V= 7T 0.5mm diameter

Ns6.3V= 3T 0.5mm diameter

N Vaux =7T 0.5mm diameter

All wires are enamelled grade 2

Leakage inductance < 2%

SEMICONDUCTOR SELECTION

THE CONTROLLER

The MC44602 high performance, fixed frequency, current mode controller is the heart of the flyback power
supply.

This circuit, specially designed for off-line and high voltage DC-DC converter applications with bipolar
transistors, offers:

• Separate high current source and sink outputs

• Unique overload and short circuit protection
• Thermal protection
• Oscillator with sync input
• Current mode operation to 500 kHz output switching frequency
• Output dead time adjustment
• Automatic feed-forward compensation
• Latching PWM for cycle by cycle current limiting
• Input and reference undervoltage lockouts with hysteresis
• Low start-up and operating current

117
 16 15

S~RT~T~~-,-----;
2P,y

SYNCHRO o-----r---------i

14
Vc

11
SOURCE OUT

10
VOLTAGE SINK OUT
FEEDBACK 0--------.--1
4.5
12.13
POWER
GROUND

MC44602

GROUND

Figure 4 Simplified block diagram

THE SWITCHING TRANSISTOR

With a peak current of 7A. the state-of-the-art planar switch mode bipolar power transistor MJH18010 is a
good choice.

On control: its power gain of 10 at 7A needs an Ib current of only 0.7 A.

With Ibl = 0.7A. the base resistor R6= (Vaux-Vsat MC44602 -Vz -Vbe on - Vpinsl/lbl.
Vpin5=R9*l peak max·

R6 = (16V-2V-4.7V-O.7v-l.5Vl/0.7A =10Q

Off control: for reverse base current Ib2, a zener limits the reverse voltage to 4.7V, and the 2.2 J.1H L2
inductor limits the di/dt of reverse current to avoid Ic current crowding during T off.

A clamping circuit is added on the collector of the power transistor to limit the peak voltage and stress
during the RBSOA.

The maximum collector voltage is: Vcoll = U+(Vout/N)

N=Np/Ns =0.5

For Vout = 135V, Vcoll= 375+(135/0.5) = 645V

The snubbing capacitor of 330pF limits the dv/dt of the transistor at switch off; see ANE424 and AN1080.

118
THE OUTPUT DIODES

Since the power supply can work in continuous current mode, the output diodes need to be ULTRAFAST
diodes thanks to their low TRR.

For 135Voutput, maximum reverse voltage is Vout +(max V cc/ n) n=Ns/Np

135+(375/0.5)=885V + ripple. The diode is a MUR4100E.

For 87V output, maximum reverse voltage is 87+(375/0.75)=587V. The diode is a MUR460.

For 25V out the diode is a MUR420.

For 16V out the diode is a 1N4934.

For 6.3V the diode is a MUR415.

119
 SCHEMATIC DIAGRAM
85Vacto
265Vac

R16
10/5W C6
lnF/lKV

310Vdc

Rl Di Ll
47KIYZN 1_ lpH

Rll
2SKll

AS
121<0

R6
11<0
AS
0.20
12.2
C7
nF

SYNCH~I

Figure 5 1OOW power supply schematic

120
 PERFORMANCE

Test Conditions Results 31,5 KHz to 85 KHz

Line Reg Vin = 85Vac to 265Vac

135V lout = O.4A 6.= 0.3V or +/-0.15%
87V lout = 0.2A A= O.lV or +/- 0.1 %
25V lout = 0.8A A= 0.15V or +/-0.3%
16V lout = 0.3A 6.= OV
6.3V lout = 0.8A 6. = OV

Load Reg Vin = 110Vac

Vin = 220Vac
135V lout = 0.2A to 0.4A 6.= 2V or +/- 0.75%

Ripple lout = 0.4A

135V Vin = 85Vac 1V (31 KHz) 0.4V(85 KHz)
Vin = 85Vac 0.3V (50 Hz)
Vin = 265Vac lV (31 KHz) 0.3V (85 KHz)
Vin = 265Vac OV (50 Hz)

Efficiency Vin = 11 OVac/220Vac 80%

Pout = 100W

Stand-by Mode
P input Vin = 90Vac, Pout = OW 2.5W
P input Vin = 220Vac, Pout = OW 5.5W

Output short circuit Safe on all outputs

LIST OF SEMICONDUCTORS

Integrated Circuit MC44602P2 1

Transistor MJH18010 1

Diodes MR508 4
lN4934 2
1N4732 2
MUR460 2
MUR4100E 1
MUR420 2
MUR415 1
lN4148 3
1N4731 1

121
OSCILLOGRAMS

Yin 110Vac F-3l.5kHz Voc-l00VlDiv Ic-5A1Div 1b-1AIDiv \(in 220Vac F-3l.SkHz VCC=200V/Div Ie-SAIDiv IbalA/DIv

Vin 110V F=85kHzVcc=l00VlDiv Ie=05A1Div lb=lA1Div Vin 220Vac F=85kHz Vcc=200V/Div IC=5A1Div Ib-l AlDiv

Vin 220Vac F-3l.5kHz VCC=200V/Div 1002AIDiv Ib-1AIDiv Vin 220Vac F=85kHz VCC=200VlDiv Ic-2A1Div Ib=lA1Div

Figure 6 Typical results obtained

122
 CONCLUSION

This paper demonstrates that the use of the new current mode controller is an easy way to realise a high
performance. low cost. universal input. voltage range power supply with multisync capability.

The regulation performance can be improved at extra cost by using an optocoupler and a TL431 voltage
reference in the feedback loop.

This power supply can be adapted to other output voltages by changing the transformer.

REFERENCES

AN 1080/D Application note

MC44602 Data sheet

MJH18010 Data sheet

ANE424/D Application note

123
124
 AN749
Broadband Transformers and Power
Combining Techniques for RF

Prepared by:
H. Granberg
R F Circuits Engineering

This Application Note discusses broad·

band transformers for R F power appl ica·
tions. Practical examples are given with
performance data and power combining
techniques are discussed in detail.

125
 BROADBAND TRANSFORMERS AND POWER
COMBINING TECHNIQUES FOR RF

INTRODUCTION ences I, 2, and 4. Experiments have shown that the di-

The following discussion focuses on broadband trans- electric losses in certain types of magnet wire, employed
formers for RF power applications with practical examples for the twisted lines, can limit the power handling cap-
of various types given with performance data. Detailed ability of such transformers. This appears as heat generated
design formula are available in the Reference section. within the transformer at higher frequencies, although part
Power combining techniques useful in designing high of this may be caused by the losses in the magnetic core
power amplifiers are discussed in detail. employed to improve the low frequency response. At low
frequencies, magnetic coupling between the primary and
secondary is predominant. At higher frequencies the leak-
BROADBAND TRANSFORMERS age inductance increases and the permeability of the
The input and output transformers are among the most magnetic material decreases, limiting the bandwidth unless
critical components in the design of a multi-octave ampli- tight capacitive coupling is provided. In a transmission line
fier. The total performance of the amplifier (linearity, transformer this coupling can be clearly defined in the
efficiency, VSWR, gain flatness) will depend on their form of a line impedance.
quality. Transformers with high impedance ratios and for The required minimum inductance on the low imped-
low impedances are more difficult to design in general. In ance side is:
the transmission li~e transformers very low line impedances L = Inductance in J.tH
are required, which makes them impractical for higher than L=~ where R = Impedance in Ohms
21rf
16: I impedance ratios in a 50-Ohm system. Other type f = Frequency in MHz
transformers require tight coupling coefficients between
the primary &Ild secondary, or excessive leakage induct· This applies to all transformers described here.
ances will reduce the effective bandwidth. Twisted line Some transformers, which exhibit good broad band per-
transformers (Rgure IC, D, F, G) are described in Refer- formance and are easy to duplicate are shown in Figure 1.

FIGURE 1 - HF Broadband Transformers

126
 Transformers E and F are intended for input applica- Ferrite plates (Ilr = 2000 to 3000) are cemented on each
tions, although A in a smaller physical form is also suitable. side to improve the low frequency response. TILis type
In E, the windings are photo etched on double sided transformer in the size shown, can handle power levels to
copper-Kapton* (or copper-fiberglass) laminate. The dielec- 10 W. Figure 2 shows curves for laminate thickness versus
tric thickness is 3 mils, and the winding area is 0.25 in 2. winding area for various impedance ratios.
10
Impedance ratios of this transformer are not limited to
integers as 1:1,4:1 -- N:L, and the dc isolated primary
~ 9
~ B
25 n: 5 0 n _
10n: son .....
.-..- and secondary have an advantage in certain circuit config-
5 n: 50 n r-..~ urations. TItis design will find its applications in high
~

~ 6
....... K, ......... ~ volume production or where the small physical size is of
"...,...
~- ~
u
:c: 5 main concern. Table I shows the winding configuration
I- 4 ./ ~ ~
~ ~..,........
and measured data of the transformer shown in Figure 3.
~ 3 /'
o
'E 2 ./ V
~ 1 V./ TABLE 1 - Impedance at Terminals BB'
0.1 0.3 0.5 0.7 0.9 Transformer Terminated as Shown
Transformer size (Area I n. 2 )

FIGURE 2 - Laminate Thickness versus Winding Area

A'
5.1n
6~~
pF

I J
3 Turns
! I
I
I
I
CI'
10 Turns
B'

f (MHz) Rp (Ohms) Xp (Ohms)

1.0 50.7 +j 81
2.0 53,0 +j 185
4.0 53.1 +j 1518
8,0 53.5 .j 214
16.0 50.5 -j 79
32.0 52.9 .j 30

Area 62
In the transformer shown in Figure 1F and Table 2, a
regular antenna balun core is employed (Indiana General
F684-1 or equivalent). lines A and B each consist of two
twisted pairs of AWG #30 enameled wire. The line
impedances are measured as 32 Ohms, which is suffi-
ciently close to the optimum 25 Ohms calculated for 4: 1
impedance ratio. (Zo =v' Rin RL).
Windings a and b are wound one on top of the other,
around the center section of the balun core. Line c should
have an optimum Zo of 50 Ohm~. It consists of one pair of
AWG #32 twisted enameled wire with the Zo measured as
62 Ohms. The balun core has two magnetically isolated
toroids on which c is wound, divided equally between
each. The inductance of c should approach the combined
inductance of Lines a and b (Reference 4, 6).
The reactance in the 50 Ohm port (BB') should measure
Copper a minimum of + j 200. To achieve this for a 4: 1 trans·
Strip 56 former, a and b should each have three turns, and for a
9: 1 transformer, four turns. When the windings are con-
nected as a 9: 1 configuration, the optimum Zo is 16.6
Patent Applied for.
Ohms, and a larger amount of high frequency compensation
FIGURE 3 - Detailed Structure of TransformarShown in Figure 1 E will be necessary. Lower impedance lines can be realized
with heavier wires or by twisting more than two pairs to-
*Trademark of E. I. DuPont, De Nemours and Co., Inc. gether. (e ,g., four pairs of AWG #36 enameled wire

127
would result in the Zo of approximately 18 Ohms.) De·
tailed information on the manufacture of twisted wire
transmission lines can be found in References 2,4, and 8. Multi-Turn Winding
Threaded
Through Tubings
TABLE 2 - Im..dance at Tannin"s BB'
Transformer Tanninatad as Shown

a. 4 Turns
A to

A' Balun S·
Ferrite Sleeves,
b,4 Turns Stackpole 57·0472·24A.
or Equivalent.

f(MHz) Rp (Ohms) Xp (Ohms)

1.0 53.0 +j 185 FIGURE 4 - Physical Construction of a 16: 1 Transfonner

2.0 52.6 +j 330 (Actual Number of Turns Not Shown)
4.0 52.9 +j430
A similar piece of laminate is soldered to the opposite
8.0 53.1 +j 600
ends of the tubes, and the copper foil is divided into two
16.0 53.2 +j 750
sections, thus isolating the ends where the primary connec·
32.0 53.5 +j 3060
tions are made. The secondary winding is formed by
threading wire with good RF insulating properties through
the tubes for the required number of turns.
Figure I A shows one of the most practical designs for
Although the measurements indicate negligible differ·
higher impedance ratios (16 and up). The low impedance
ences in performance for various wire sizes and types
winding always consists of one turn, which limits the avail·
(stranded or solid), the largest possible diameter should be
able ratios to integers 1,4,9 -- N. Data taken of this type
chosen for lower resistive losses. The initial permeability of
of a 16: I transformer is shown in Table 3, while Figure 4
the ferrite sleeves is determined by the minimum induct·
illustrates the physical construction. Two tubes, 1.4" long
ance required for the lowest frequency of operation accord·
and 1/4" in diameter - copper or brass - form the primary
ing to the previous formula. Typical JJ.r's can vary from
winding. The tubes are electrically shorted on one end by a
800 to 3000 depending upon the cross sectional area and
piece of copper-clad laminate with holes for the tubes and
lowest operating frequency. Instead of the ferrite sleeves
the tube ends are soldered to the copper foil. The hole
a number of toroids which may be more readily available:
spacing should be larger than the outside diameter of the
ferrite sleeves. can be stacked.
The coupling coefficient between the primary and sec·
ondary is almost a logarithmic function of the tube dia·
TABLE 3 - Im..danca at Terminals BB' meter and length. This factor becomes more important
Transfarmer Terminated as Shown
with very high impedance ratios such as 36: 1 and up,
where higher coupling coefficients are required. The losses
in the ferrite are determined by the frequency, permeability

'rn CE'
1 Turn 4 Turns
an~. flux density. The approximate power handling cap·
I ability can be calculated as in Reference 4 and 6 but the
3.3n I ferrite loss factor should be taken into conSideration. The
I
820 pF I JJ.r in all magnetic materials is inversely proportional to the
frequency, although very few manufacturers give this data.
A' s·
Two other variations of this transformer are shown in
Figure 5. The smaller version is suitable for input matching,
f (MHz) Rp(Ohms) Xp (Ohms) and can handle power levels to 20 W. It employs a stack·
pole dual balun ferrite core 57-1845-24B. The low imped·
1.0 54.0 +j 1030
ance winding is made of 1/8" copper braid. The portions
2.0 54.0 +j 3090
of braid going through the ferrite are rounded, and open·
4.0 54.0 +j 5800
ings are made in the ends with a pointed tool. The high
8.0 53.9 oj 300
impedance winding is threaded through the rounded
16.0 53.1 1760 portions of the braid, which was uncovered in each end of
32.0 53.2 oj 600
the ferrite core. (See Figures 4 and 5.)

128
 Toroids-Indiana
Genaral F627-19 01,

R 4R

~
Cable - 25,n,
Microdot 26C)..41 18-000.
or Equivalent. (16 Turns
on Each Toroid.)

FIGURE 5 - Variations of Transformers in Figure 1A FIGURE 6 - Transformer Construction (Figure lB)

Note the connection arrangement (Figure 6), where ilie

The construction technique of the larger version trans-
braid of the cable forms the high current paili of ilie
former is similar, except two separate ferrite sleeves are
primary.
employed. They can be cemented together for easier
handling. This transformer is intended for output applica- TABLE 4 - Impedance at Terminals BB'
tions, with a power handling capability of 200-250 W Transformer Terminated as Shown
employing Stackpole 57-0472-27A ferrites. For more
detail, see Reference 7.
The transformer shown in Figure 1B is superior in band-
width and power handling capability. Table 4 shows data
taken on a 4: I transformer of this type. The transmission
lines (a and b) are made of 25-0hm miniature co-axial
cable, Microdot 260-4118-000 or equivalent. Two 50 Ohm
cables can also be connected in parallel.
The balun, normally required to provide the balanced
to unbalanced function is not necessary when the two
transmission lines are wound on separate magnetic cores,
and the physical length of the lines is sufficient to provide
the necessary isolation between AA' and BB'. The minimum
line length required at 2.0 MHz employing Indiana General
F627-19-Ql or equivalent ferrite toroids is 4.2 inches, and
the maximum permissible length at 30 MHz would be
approximately 20 inches, according to formulas 9 and 10
presented in Reference 2. The 4.2 inches would amount
to four turns on the toroid, and measures 1.0 ~H. This
complies with the results obtained with the formula given IDGH-FREQUENCY POWER COMBINING
earlier for minimum inductance calculations. TECHNIQUES EMPLOYING HYBRID COUPLERS
increasing the minimum required line length by a factor The zero degree hybrids described here are intended for
of 4 will provide the isolation, and the total length is still adding the powers of a multiple of solid-state amplifiers, or
within the calculated limits. The power loss in this PTFE to combine the outputs of groups of amplifiers, usually re-
insulated co-axial cable is 0.03 dB/ft at 30 MHz in contrast ferred to as modules. With this technique, powers to ilie
to 0.12 dB/ft for a twisted wire line. The total line loss in kW level at the high-frequency bands can be realized.
the transformer will be about 0.1 dB When reversed, the hybrids can be used for splitting
The number of turns on the toroids has been increased signals into two or more equal phase and amplitude ports.
beyond the pOint where the flux density of the magnetic In addition, they provide the necessary isolation between
core is the power limiting factor. The combined line and the sources. The purpose of the isolation is to keep the
core losses limit the power handling capability to approxi- system operative, even at a reduced power level during a
mately 300 W, which can be slightly increased by employ- possible failure in one amplifier or module. The isolation
ing lower loss magnetic material. is especially important in output combining of linear

129
amplifiers, where a constant load impedance must be main-
tained. Sometimes the inputs can be simply paralleled, and
a partial system failure would not have catastrophic effects,
but will merely result in increased input VSWR.
For very high frequencies and narrow bandwidths, the
RL
hybrid couplers may consist of only lengths of transmis-
sion line, such as co-axial cable. The physical lengths of the
lines should be negligible compared to the highest operat-
-!-
ing frequency to minimize the resistive losses, and to avoid RL
possible resonances. To increase the bandwidth and im-
prove the isolation characteristics of the line, it is necessary -!- RL
to increase the impedance for non-transmission line cur·
rents (parallel currents) without effecting its physical
length. This can be done by loading the line with magnetic
material. Ideally, this material should have a linear BH FIGURE7A
curve, high permeability and low losses over a wide freq-
uency range. For high-frequency applications, some ferrites
offer satisfactory characteristics, making bandwidths of RL
four or more octaves possible.
Depending upon the balance and phase differences be·
tween the sources, the currents should be mostly cancelled 2 X RL
in the balun lines. In a balanced condition, very little power
is dissipated in the ferrite cores, and most occurring losses
will be resistive. Thus, a straight piece of transmission line RL
loaded with a high permeability ferrite sleeve, will give
better results than a multiturn toroid arrangement with
its inherent higher distributed winding capacitance. FIGURE 7B
It is customary to design the individual amplifiers for 50
Ohm input and output impedances for testing purposes
and standardization. 50-and 25-0hm co·axial cable can
then be employed for the transmission lines. Twisted wire FIGURE 7 - Variations of Basic Hybrid
lines should not be used at power levels higher than lOa
Watts average, due to their higher dielectric losses. figures for 2 to 30 MHz operation are 30-40 dB. Fig-
Variations of the basic hybrid are shown in Figure 7 A ures 8A and B show 4 port "totem pole" structures de-
and B where both are suitable for power dividing or rived from Figures 7 A and 7B. Both can be used with even
combining. number of sources only, e.g. 4, 8, 16, etc. For type 8B, it
The balancing resistors are necessary to maintain a low is more practical to employ toroidal multi-turn lines, rather
VSWR in case one of the 50-Ohm points reaches a high than the straight line al terna tives, discussed earlier. The
impedance as a result of a transistor failure. As an input power output with various numbers of inoperative sources
can be calculated as follows, if the phase differences are
power splitter, neither 50-Ohm port will ever be subjected
to a short due to the base compensation networks, should negligible: (Reference 2)
a base-emitter junction short occur. An open junction will
result in half of the input power being dissipated by the Pout =(~)Nl
balancing resistor, the other half still being delivered to the
where: P = Total power of operative sources
amplifier in operation. The operation is reversed when the
N = Total number of sources
hybrid is used as an output combiner. A transistor failure
N I = Number of operative sources
will practically always cause an increase in the amplifier
output impedance. Compared to the 5G-Ohm load imped- Assuming the most common situation where one out of
ance it can be regarded as an open circuit. When only one four amplifiers will fail, 75% of the total power of the re-
amplifier is operative, half of its output power will be dis- maining active sources will be delivered to the load.
sipated by R, the other half being delivered to the load. Another type of multiport hybrid derived from Figure
The remaining active source will still see the correct load 7 A is shown in Figure 9. It has the advantage of being cap-
impedance, which is a basic requirement in combining able of interfacing with an odd number of sources or loads.
linear amplifiers. The resistors (R) should be of nonin- In fact, this hybrid can be designed for any number of
ductive type, and rated for 25% of the total power, unless ports. The optimum values of the balancing resistors will
some type of automatic shutoff system is incorporated. vary according to this and also with the number of ports
The degree of isolation obtainable depends upon the fre· assumed to be disabled at one time. Two other power
quency, and the overall design of the hybrid. Typical combining arrangements are shown in Figures 10 and 11.

130
 25n~

50n

-1- Rl

50l!

-1- R3

50n

-1-
1-
50n

25.n~
C3-~-
-,-
.... _-
I
50n

Zo (a, b, c, d) = 50n
Zo (e, f, g) = 25n

FIGURE 8A

100ll

1 50n
0---+------.
50n
50n

1 - 50n
1 :4

1, o---.---+~
" - _ f ' o r ' V " " _ _ __
50n
Cl

.1 Line impedances:

a, b = 50n
loon c, d = 25rl

FIGURE 88

FIGURE 8 - Four Port "Totem Pole" Structure

R R

R R

R R

T2 = 1:3

R = 22.2, 16.6 Ohms

Zo (a,b,c) = 50 !2
Zo (d. e) = 25 n (optimum 28.9 H)

FIGURE 9 - Three-Port Hybrid Arrangement

131
 R
25n

50n Input Output

-!- C1
J T2 = 1:2

20 la,b) = 50 n
Zo (c,d) :: 25 n (optimum 35.4 S'l)

FIGURE 10 - Two-Port Hybrid System

V2~,T'T
50n

Q:, -". "'m.

1 PORT INOPERATIVE. 2 PORTS INOPERATIVE. 3 PORTS INOPERATIVE.
Optimum R :: 28.3 Ohms Optimum R = 25 Ohms Optimum R = 18.75 Otvns

Pl, P2, P3 = Power at any operative port. P R = Power dissipated in A, excluding R L "
V = RMS voltage at any 50 Ohm point.
(The phase differences are assumed negligible.)

20 la,b,c,d) = 50 n
Zo (e,f) = 25 .n (optimum)

FIGURE 11 - Four-Port Hybrid System

132
The isolation characteristics of the four-port output com-
biner were measured, the data being shown in Table 5_
The ferrite sleeves are Stackpole 57-0572-27 A, and the
transmission lines are made of RG-142/U co-axial cable_
The input power dividers described here, employ Stack-
pole 57-l5l1-24B ferrites, and the co-axial cable is Micro-
dot 250-4012-0000_

TABLE 5 - Isolation
Characteristics of Four Port Output Cam bin.

Isolation,
Port-to-Port
f (MHz) (dB)

2_0 27_0-29_4
4.0 34.8-38.2
7.5 39.0-41.2
15 32.1-33.5
20 31.2-33.0
30 31.0-33.4 FIGURE 12 - Two-Four Port Hybrids

The one at the lower left is intended for power divider applications
with levels to 20 - 30 W. The larger one was designed for amplifier
The input and output matching transformers (TJ - T2) output power combining,and can handle levels to 1 - 1.5 kW. (The
will be somewhat difficult to implement for such impedance balancing resistors are not shown with this unit.)
ratios as 2: 1 and 3: 1. One solution is a multi-turn toroid
wound with co-axial cable, such as Microdot 260-4118-000. consists of two 300 W modules (8). This combined ampli-
A tap can be made to the braid at any point, but since this fier can deliver 600 W peak envelope power. The· CW
is 25-0hm cable, the Zo is optimum for a 4: 1 impedance power output is limited to approximately 400 W by the
ratio only. Lower impedance ratios will normally require heatsink and the output transformer design.
increased values for the leakage inductance compensation The power combiner (Figure l3A) and the 2: 1 step-up
capacitances (C I - C2). For power levels above 500-600 transformer (Figure l3B) can be seen in the upper right
W, larger diameter co-axial cable is desirable, and it may be corner. The input splitter is located behind the bracket
necessary to parallel two higher impedance cables. The (Figure l3C). The electrical configuration of the hybrids
required cross sectional area of the toroid can be calculated is shown in Figures 7 A and 10. Note the loops equalizing
according to the Bmax formulas presented in References the lengths of the co-axial cables in the input and output
4 and 6. to assure a minimum phase difference between the two
The 2 to 30 MHz linear amplifier (shown in Figure 13) modules.

FIGURE 13 - 2 to 30 MHz Linear Amplifier Layout

133
REFERENCES
1. Ruthroff: Some Broad Band Transfonners, IRE, 6. Granberg, H.: Broadband Linear Power Amplifiers
Volume 47, August 1957. Using Push-Pull Transistors, AN-593, Motorola Semi·
2. Pizalis·Couse: Broadband Transfonner Design for conductor Products Inc.
RF Transistor Amplifiers, ECOM-2989, U.S. Anny 7. Granberg, H.: Get 300 Watts PEP Linear Across 2 to
Electronics Command, Fort Monmouth, New Jersey, 30 MHz From This Push-Pull Amplifier, EB·27,
July 1968. Motorola Semiconductor Products Inc.
3. Lewis: Notes on Low Impedance H.P. Broad Band 8. Lefferson: Twisted Wire Transmission Line, IEEE
Transformer Techniques, Collins Radio Company, Transactions on Parts, Hybrids and Packaging, Vol.
November 1964. PHP-7, No.4, December 1971.
4. Hilbers: Design of H. F. Wide band Power Trans· 9. Krauss-Allen: Designing Toroidal Transformers to
formers, Philips Application Information #530. Optimize Wideband Performance, Electronics,
5. Philips Telecommunication Review, Volume 30, No. August 1973.
4, pp. 137-146, November 1972.

134
 AN756

CRYSTAL SWITCHING METHODS FOR

MC12060IMC12061 OSCILLATORS
Prepared by:
John Hatchett
Roger Janikowski

This report discusses methods of using diodes to select series

resonant crystals electronically. Circuit designs suitable for
use with crystal frequencies from 100 kHz to 20 MHz are
developed with emphasis being placed on minimizing fre-
quency pulling. Although developed for use with the
MC12060 and MC12061 integrated circuit crystal oscillators,
the techniques will, in general, be useful in any application
where it is desired to electronically select one out of a group
of crystals with a minimum of disturbance to the series res-
onant frequency of the selected crystal.

CRYSTAL SWITCHING METHODS FOR

MC12060/MC12061 OSCILLATORS
INTRODUCTION
Crystal switching can be achieved electronically for 500 mVp-p (typical) when an external resistor is used
the MC12060 and MC12061 crystal oscillator integrated to increase the current in the emitter follower output.
circuits by utilizing diodes as RF switches. The switching The ECL and TTL outputs are capable of driving five
is controlled by applying a forward bias to the diode as- and ten gate loads respectively.
sociated with the desired crystal and applying a reverse Series resonant crystals connected between Pins 5 and
bias to the remaining diodes related to the unselected 6 are required for use with these oscillators. The total
crystals. effective ac series resistance (crystal series resonance
In addition to functioning with the MC12060( resistance plus any additional resistance contributed by
MC12061 IC's, the switching circuit designs described switching components) between these pins must be less
here can also be used in other applications where it is than 4 k ohms for the MC12060, and less than 155 ohms
desired to electronically switch series-resonant crystals for the MC12061.
with a minimum of frequency pulling. For additional information on these IC's, see the de-
Advantages to this switching scheme include the vice data sheet and Engineering Bulletins EB59 and
following: EB60.
1. Eliminates the need to run high frequency signals Schematic diagrams for the MC12060 and MC12061
through a mechanical switch; crystal switching circuits are given in Figures 1 and 2
2. Permits switching crystals from a remote position respectively. The same basic technique is employed for
with a minimum of disturbance to the oscillator; each IC except that an additional diode-resistor pair (06,
3. Minimizes RF radiation; RIB through 010, R22) is incorporated for the MC12060
4. Adapts easily to electronic scanning methods; to offset its greater sensitivity to ac loading.
5. Operates from a single polarity, low voltage supply The MPN3401 PIN diode and the MSD7000 PN junc-
(5.0 volts). tion diode are used to switch the crystals. The MSD7000
was selected for use with the MC12060 oscillator because
GENERAL of its low capacitance (1.5 pF max. for VR = 0 volts). It
The MC12060 and MC12061 crystal oscillators are is also an economical dual diode in the configuration
specified for operating frequency ranges of 100 kHz to needed for this circuit.
2.0 MHz, and 2.0 MHz to 20 MHz respectively. Their The MPN3401 is used with the MC12061 circuit be-
outputs consist of a single-ended TTL signal, plus com- cause it offers a lar~e off-to-on impedance ratio for low
plementary sine wave and ECL signals. The sine wave dc bias currents at frequencies within the range of the
outputs are capable of driving an ac load of 50 ohms at MC12061.

135
 XlcJs
F X2~ ,J:
X3~ x4ck X5~
J:
r - 06--' r-i57--' r -08- -, r -09--' r DiD--'
I
r--...J
I
1
__ .J I ..
r __ ...J I .. .J
r: __ , I
r--...J
I
r I I
01 1
I
I
1 R18
Rl R2
I
021 ~I
1 I
R19
R3 R4
I
03 1 U, 1 R20
R5 R6
041 ~I
I
R21
R7 R8
OSI 1 R22
I ~I R9Rl0

RL-
I C
L.J
~
.J
~ ~L .....-
J
~L ..J
~
i1- L ~
.J
,*0
A17

A14
-=
Ll "" R1S
R1S
"
v = 5.0 Vdc " ~ 3@ 4~
R13 2 ~
CS!
A12 r-o. 5---
"'"
Cl 'l
1\ C2,
7 51
1~

-1 s\
1 11 ·MC12060 I Sine. MECL. or TTL Output
VCC = 5.0 Vdc
C4± T II
4
1 I ·See device data sheet for proper
C3 9.,t----J 8 connections pertaining to
various applications.
L 1: Delevan #2500-44 Rl. R3. RS. R7. R9 = 82 kU A18 - R21 = 10 kn
Nytronics #Wee 2200 R2. R4. R6. A8. Rl0 = 4.3 kn Cl- C10 = 0.1 p.F
Miller #S302 R12-A16=lkU 01 - 010 = 1/2 MS07000
(2.5 mH nominal inductance) R17 = 5.1 kU Xl - X5 = 0.1 MHz-2.0 MHz

FIGURE 1 - Schematic Diagram of Crystal Switching for the MC12060.

d:.
Xl==.::! X2==:
,d, d,
X3==.::! X4==.::! d: X5~

. R9~
Ol~~
Rl
R2

~5
L
02
R3
A4 ~ .. 03
~7
l'
RS
R6
~C8
T
04~ ..
R7
R8 05~

1f9
~

11"
r
C
R10

R14
-=
R15
R17 R16

V = 5.0 Vdc 3@ ___

2<~
~ R13 4""

J C5
Cll(
---
1""'
5~
~

" C2 7 SI
-=1 61

Vec = 5.0 V
1 1\
11 ·MC120S1 I Sine. MECL. or TTL Outputs

C4t YH C3 9J::------18
I ·See device data sheet for proper
connections pertaining to
various applications.

Rl. R3. RS. R7. R9 = 10 kU C6 - C10 = 0.Q1 p.F

R2. R4. RS. R8. Rl0. R17 = 2.2 kU 01 - 05 = MPN3401
R12. R13. R14. R1S. R16 = 1.0 kU Xl- XS = 2.0 MHz- 20 MHz
Cl = 0.001 p.F
C2 - CS = 0.1 p.F

RGURE 2 - Schematic Diagram of Crystal Switching for the MC12061

136
 DC BIAS REQUIREMENTS
Forward bias for the desired crystal selecting diode 1
(01, 02, 03, 04, or 05) is applied by setting the five Xo = wCo 1
position switch. The bias current is primarily set by R17 Xs = wCs
and R2 (R4, R6, RS, and RlO have identical functions to
R2 when they are switched-in). The four remaining sets ~E--<>
of bias resistors, corresponding to the unselected crystals, RS cs
add a smaller amount of current to the forward-biased
where: Xs =
Xo and RS = RO
diode. The total forward bias current, 10, can be described
by the formulas: 2
(~~) + 1
(RX~ )2 + 1
V - 2VD Vn
In = - (ru) (For MCI2060);
R2 + {R17 II (R3 + R! + RI9)} FIGURE 3 - Diode Equivalent Circuits

V - VD Vn JJ.F. Typical series resonant crystals in this frequency

In = - (R) (For MCI206I).
R2+{R17 (R3+R!+RI3)} 1 range exhibit equivalent Cx capacity values of 0.012 pF
11
to 0.003 pF and the maximum series resistance specifi-
cation for the MC12061 is 155 ohms. Again, the require-
While one diode (or one diode pair in the case of Figure ments of both items 1 and 2 above are met.
1) is always forward biased, the remaining diodes are
reverse biased to minimize their capacitance. This is ac-
complished with a single polarity supply by using pullup DECOUPLING UNSELECTED CRYSTALS
resistors (R12, R13, R14, R15, and R16) from the positive Isolating unselected crystals is very important from
potential to each switch terminal. Therefore, the cath- the standpoint of minimizing frequency pull of the se-
odes of the diodes corresponding to the unselected crys- lected crystal, and insuring that the oscillator will lock
tals are pulled up to approximately the supply voltage. on a new crystal frequency when switched from a pre-
Since one diode (or diode pair) is always selected, current vious one.
The objective for decoupling unselected crystals. is to
is flowing through R17 continuously, causing a voltage
drop. Therefore, the anodes of the unselected diodes will place a high impedance in series with them. The
be negative with respect to their cathodes. When using MSD7000 typically has 0.72 pF of shunt capacitance CD
a 5.0 volt supply, this reverse bias will be 1.6 volts for (refer to Figure 3) at VR = 1.6 volts, and the MPN3401
the MC12060 and 1.2 volts for the MC12061 crystal typically 0.75 pF at 1.2 volts of reverse bias. Since RO
is extremely large for the reverse bias condition, the re-
switching array.
sulting diode .RS resistance will not be exceptionally
large and Cs will approximately equal CD. This series
ADDITIONAL CONSIDERATIONS
capacitance is 30 to 300 times greater than typical values
A sufficient amount of forward current through the
of equivalent crystal series resonant capacitance (CX).
diode selecting the desired crystal is required to insure
a low value for diode resistance RO (see Figure 3). This Therefore, the total series equivalent capacitance
is important for two reasons: CSCX
(CT = C C) decreases by only 3.2% to 0.33% re-
1. To minimize the effects of diode capacity on the S + X
crystal's natural series resonant frequency. spectively. This, combined with a low value for RS, main-
2. To minimize the total effective external resistance tains considerable coupling between the unselected crys-
between Pins 5 and 6 of the integrated circuit. tal (s) and the oscillator. Thus, the oscillator may remain
From Figure 3 it is apparent that as RD is made at the previous crystal frequency, or operate at some ran-
smaller, Xs is decreased and Cs is increased. A large dom frequency.
value for Cs relative to the crystal's equivalent series To reduce this problem, a shunt resistor (Rl, R3, R5,
capacitance is required to satisfy item 1. R7, Rg) is added to each switching\cl.iode (Dl, D2, D3,
The impedance of the MSD7000 diode with 0.45 mA D4, D5) in Figures 1 and 2. This shunt resistor estab-
of bias current has a typical value of 115 - 3° = 114.6- lishes a new and lower value for RD in Figure 3, which
j6 ohms at 100 kHz and 115 - 8° = 113.8-j16 ohms at results in a new RS value - much greater than the
2 MHz; resulting Cs values are respectively 0.265 pF maximum allowable effective resistance specification for
and 0.005 pF. Since typical series resonant crystals in the MC12060tMC12061.
this frequency range exhibit equivalent series capaci- Worst-case coupling effects occur at 2 MHz for the
tance values, CX, ranging from 0.024 pF to 0.012 pF, MC12060 and 20 MHz for the MC12061. Referring to
item 1 is satisfied. Also, since the equivalent series re- Figure 3: assume CD is equal to 1 pF; this gives XD =
sistance of the diode is much less than the maximum 1
effective resistance specification (4 k ohms) for the -2-- = 79.5 k ohms at 2 MHz, and 7.95 k ohms at 20
MC12060, item 2 is satisfied. .nCD
For the MC12061 circuit, the diode forward bias cur- MHz. To maximize the series equivalent resistor (RS),
rent is 1.15 mAo This current is sufficient to keep the the parallel resistor RD is made equal to the reactance
series impedance of the MPN3401 PIN diode low. At XD at the highest operating frequency. For the MC12060,
2 MHz the impedance is nominally 22 - 28° = 19.4-j10 the values of RO = XD = 79.5 k ohms give RS = Xs
ohms and at 20 MHz 3.3 -37° = 2.6-j1.98 ohms. The = 39.7 k ohms. Since RS is now much greater than 4 k
resulting Cs values in this case are 0.008 JJ.F and 0.004 ohms, the unselected crystals will be virtually isolated

137
from the oscillator. This isolation will become greater as the total number of crystals to be switched is in-
with a decrease in frequency. creased. However, by using the switching techniques
Using the same formulas to determine the required shown in Figures 1 and 2, any frequency pulling in ad-
RD and to calculate RS and Xs at 20 MHz for the dition to that for a single crystal connected directly to
MC12061 results in RD = XD = 7.95 k ohms, giving a Pins 5 and 6 (Le. pulling caused by the ICs alone) is
new value ofRS = Xs = 3.97 k ohms. This value ofRS negligible below approximately 1 MHz for the MC12060
is much greater than 155 ohms, the maximum effective and 15 MHz for the MC12061. Measurements of this
resistance specification for the MC12061. Therefore, the additional pulling are summarized in Table 1. Typical
oscillator will now have sufficient isolation from the un- frequency pulling values attributable to the ICs them-
selected crystals to prevent erratic performance. selves are given in Table II. In this case the devices are
The values used for Rl, R3, R5, R7 and R9 are 82 k operating with a single crystal connected directly to Pins
ohms, and 10 k ohms for Figures 1 and 2 respectively. 5 and 6 with no crystal switching circuits. The Table II
values have been taken as a reference in establishing
the pulling (noted in Table n caused by the switching
OSCILLATOR AC LOADING networks. When using the crystal switching circuits,
Oscillator ac loading must be minimized to reduce complete pulling from the crystal's series resonant fre-
frequency pulling and sine wave distortion. For the cir- quency is obtained by algebraically adding the respective
cuits shown in Figures 1 and 2 the ac loading is primarily values in Tables I and II. For example, absolute crystal
attributable to the biasing networks for the five diodes pulling for the five crystal switching system when se-
(DI-D5). All bias elements contribute to an effective ac lecting the nominal 1.0 MHz crystal is approximately
load, regardless of which crystal position is selected. This - 0.0040 + 0.0031 = - 0.0009 percent. Similarly, ab-
occurs because the RF signal is coupled through the par- solute pulling for the 8.0 MHz crystal becomes - 0.004
allel capacitance (Co) of the unselected crystals. + 0.0001 = - 0.0039 percent. Pulling effects of the
Due to a greater sensitivity to ac loading of the switching circuits when selecting the 0.2 MHz crystal
MC12060, additional elements are used in the switching offset pulling caused by the IC to give approximately zero
networks for this device. An RF choke, Ll, is incorporated absolute crystal pull.
to minimize the loading effects of the common bias re- When desirable, a trim capacitor can be added in se-
sistor, R17. In addition, a modified approach is used to ries with the crystals and adjusted to pull the oscillator
bias diodes Dl through D5. The networks (D6, R18) up in frequency.
through (010, R22) are added to minimize ac loading Several options are possible to reduce ac loading for
and, at the same time, supply sufficient forward current both the MC12060 and MC12061 crystal switching cir-
with a 5-volt supply. One diode (01-D5) in the MSD7000 cuits. Using a higher voltage supply for the bias networks
dual diode package is used to switch the crystal and the will allow larger values of bias resistors to be used at
second diode (06-DI0) is used for reducing ac loading. the same diode current, resulting in reduced loading.
R18 through R22 are essential to supply a small amount Also, RF decoupling chokes may be added between re-
of current for reverse bias of diodes DI-D5 corresponding sistors R2, R4, R6, RS, and RIO and capacitors C6
to the unselected crystals. through CI0. Where frequency pulling is not as critical,
Loading and therefore frequency pulling will be L1 in Figure 1 may be eliminated. These options are left
greater for higher frequency crystals and will increase to the discretion of the user.

TABLE I. Typical Frequency Pull In Percent Attributable to

Crystal Switching Networks
Device MC12060 MC12061
Nominal crystal frequency (MHz) 0.1 0.2 0.5 1.0 2.0 2.5 8.0 13.4 20.0
One crystal (connected directly to Ref. Ref. Ref. Ref. Ref. Ref. Ref. Ref. Ref.
Pins 5 and 6)
Two crystal switching system , +0.0005 +0.0006 +0.0035 -0.004 +0.0008 +0.0013 +0.0004 -0.005
Five crystal switching system , +0.0005 +0.0006 +0.0031 -0.018 +0.0008 +0.0001 -0.0006 -0.023
'Less than one Hertz pull, measurement limited to resolution of test equipment.

TABLE II. Typical Frequency Pull In Percent for ICs Only

Device MC12060 MC12061
Nominal crystal frequency (MHz) 0.1 1 0.2 1 0.5 1 1.0 1 2.0 2.5 1 8.0 1 13.4 1 20.0
, 1- 0.00051- 0.00121- 0.0040 1 -0.03 - 0.00021 - 0.004 1 - 0.01 1 -0.05
Pull in percent
*Less than one Hertz pull, measurement limited to resolution of test equipment.

138
 AN-790

THERMAL RATING OF RF POWER TRANSISTORS

Prepared by
Robert J. Johnsen
Senior Staff Engineer
and Technical Specialist in
R F Design Group

Reliability is of primary concern to many users of transistors. The

degree of reliability achieved is controlled by the device user because
he determines the stress levels applied by his circuit and environmental
conditions. This application note will permit the device user to estimate
transistor reliability from the circuit designer's point of view, namely
power dissipation and case temperature.

Introduction Temperature-Dependent Thermal Properties

The temperature-dependent thermal properties of Of Silicon and 8eryllia J-.

silicon and beryllium oxide have been measured and The temperature·dependent thermal conductivities of
documented by many laboratories during the last twenty silicon and beryllium oxide are seen in Figures I through
years. Only in rare cases has this information been dis- 3 and Table I. The temperature ranges are somewhat
seminated by semiconductor device manufacturers to the wider than are necessary for typical transistor operation,
users. The purpose of this note is to clarify and correct but are shown to emphasize the wide variation in thermal
some long-standing industry-wide assumptions which have conductivities. Fulkerson et al 3 tabulate the values for
been commonly maintained about thermal resistance and thermal conductivity and resistivity of silicon from
high temperature derating. 1000K to 13S00K (see Table I), and they find that the
Most manufacturer's data sheets include a single thermal resistivity of silicon as a function of temperature
thermal resistance number (ROJC) and use this number to can be estimated by a linear approximation over the
calculate a linear derating constant out to some specified temperature range shown.
maximum junction temperature. The number cited on the
(400 - 660 0K)
data sheet was probably measured in the 2SoC to SOOC
range, and assumed constant over the whole range of Ilk = -0.1171 + 2.9S4 X 10-3 T(OK) (I)
temperatures up to the maximum specified junction tem· (600 - IOS00K)
perature. How often have you calculated a junction Ilk = -0.9609 + 4.229 X 10-3 T (OK) (2)
temperature from a data sheet, as TJ = TA + (0 JC)PD?
Unfortunately, the thermal resistance of silicon increases A similar least·square fit to Fulkerson's data over the
by 80% from 2SoC to 200°C. The thermal resistance of range 200 to 700 0K, within 1%, is given by:
BeO changes by 30%, if the case temperature goes from (200 - 700 0K)
2SoC to 100°C. Knowledge of the basic physical prop-
Ilk = -0.2286 + 3.1683 X 10-3 T (OK) (3)
erties of the materials and the methods used to calculate
and measure thermal resistance will assist the device user Similarly for beryllia, one can fit the data of Elston et
in transistor selection and equipment design. al2 over the range of 200 to 800 0K, with equation (4).
(200 - 800 0 K)
Ilk = 1.943 X 10-S T (OK)1.7 (4)
NOTE: OK = °c + 273. where k is the thermal conductivity in units ofwatts/cmoK.

139
 TABLE 1 - Smoothed Data for Thermal Conductivity and FIGURE I - Temperature Dependent
Resistivity of Silicon (Ref. 3) Thermal Conductivity of Silicon (Ref. I)
100.------------------------,
Smoothed ORNL Values
Pure
T k W = 11k
(OK) (W cm-1 dog-I) (cm deg W- I ) 30

100 7.52 0.133

150 10
3.88 0.258
200 2.44 0.410
250 1.78 0.563
300 1.40 0.716
350 1.15 0.870
400 0.939 1.065
450 0.825 1.212
500 0.736 1.359
550 0.663 1.508
600 0.604 1.656
650 0.555 1.803
700 0.500 1.999
750 0.452 2.210
800 0.413 2.420
0.01
850 0.380 2.634
900 0.351 2.845
950 0.327 3.055 0.003
1000 0.306 3.268
1050 0.287 3.479
1100 0.273 3.65
1150 0.261 3.82
TEMPERATURE. "1(
1200 0.251 3.97
1250 0.245 4.08
1300 0.241 4.14 FIGURE 3 - Thermal Conductivity
1350 0.239 4.18 2.3

2.2

2.1

2.0

FIGURE 2 - Thermal Conductivity of BeO (Ref. 2) 1.9

1.8
20
1.7

:g 1.6
'"
~3C 1.5

~
1.4
...
.
:::>
c 1.3
8
i
3.0
;;J, 1.2

~
2.0
I 1.1

1.0
1.0
0.8 0.9

n6 0.8 Silioon
0.5 • IRef.3)
0.4 0.7
0.3 0.6

0.2 0.5

0.4
0.1 0.3
0 200 400 800 800 1000 1200 1400 1800
TEMPERATURE 10 K) TEMPERATURE, "C

140
Geometric Factors and Thermal Resistance Calculation resistivity. The calculated thermal resistance of the
The thermal resistance of most silicon RF transistors is beryllia piece (from the previous section) is mathematically
controlled by the bulk properties of silicon and beryllium divided into fifty layers, each with 1/50 of the total BeO
oxide, geometry of the heat generating (base) areas, and thermal resistance. The first layer at the bottom is
the temperature of the heat sink (case). The interfaces assumed to have its temperature at the heat-sink ambient
generally are well behaved and contribute little to the with its thermal resistance value corrected to the proper
overall total thermal resistance if the device, die and temperature using the equations for the temperature-
package elements are assembled and handled properly. dependent resistivity. The power flux through the first
Die temperature calculations are performed in two layer then leads to its temperature rise, and this new
steps. The first uses the method of Linsted and Surtey4 temperature determines the thermal resistivity value for
to calculate the temperature distribution of a die by using the second layer. Its temperature rise is calculated, and so
a double Fourier series solution to Laplace's equation. on, until the result for the top surface of the fiftieth layer
Figure 4 shows the device geometry and some of the gives the temperature rise above the ambient for the
boundary conditions. Equation (5) will calculate the beryllia piece.
temperature rise at any (x,y,z) point in the die, where The same method is used for the silicon die, using the
A,B,C,D,F are die and heat·generating area boundaries. beryllia top surface temperature as the starting pOint,
Q is the heat input in watts, and k is the thermal conduc· and correcting the thermal resistance of each of fifty
tivity of the material in watts/cmoK (Linsted's equation). layers based upon the temperature of the layer directly

T = - f{(CD)(z - F)
K AB

;...( -
+ £. Q)( 2BC )
- --- e",:rrz/B (' - exp [2m".(F - Z)/B)) (m"'D)
- - - [ sm
. - - cos (m"'Y)J
--
m~l K m'".' A , + exp (2m".F/ B) B B

+ ;...(
L.J -
Q)(2AD) e (' - exp [2n".(F -
- -- nrz / A Z)/A))[. (lI".C) cos (1'-' '-:<)J
SIn -- (5)
n~l K n'".'B , + exp (2/1".F/..1) .1 A

+ i: i:(- f{) (_4_) (1 - exp [2)"(F - Z»))

'n~l n~l K ".'mn")' 1 + exp (2")'F)

where

")" = ".' [ ( : ) ' + G)'].

The Fourier series solutions are amenable to computer beneath it, until the top surface of the silicon die result
calculation and converge adequately within ten to twenty gives the calculated die temperature for that particular
terms. Figure 5 shows the treatment of multiple base cell case of ambient temperature and power dissipation. The
transistors. Lines of symmetry between adjacent base cells results of these calculations indicate that the thermal
are considered to be adiabatic die boundaries as assumed resistance of a given device is not a constant number, but
by Lindsted. The power dissipated is assumed to be is a function of the dissipated power and the ambient
equally shared among the several base cells. The result of (case) temperature. Another result is that the junction
this calculation is the temperature rise of the silicon chip, temperature of a device dissipating power will rise more
assuming a constant thermal resistance for bulk silicon. than 10 C for a 10C rise in ambient temperature. because
The same model is used to calculate the temperature rise of the increase in thermal resistance. Figures 6 through 9
for the beryllia piece, using the silicon die area as the show the calculated thermal resistance and die tempera-
power dissipating area for the beryllia, again assuming ture for several different devices as a function of ambient
the thermal resistance of the beryllia as a constant. The temperature and power dissipation.
thermal resistances of the silicon die and the beryllia
substrate are in series, so adding the above numbers gives
a value for the thermal resistance of the device at a
particular temperature and a power level low enough to
avoid the effects of the temperature variations of the
respective thermal resistances.
The second step in the thermal resistance calculation
takes into account the temperature-dependent thermal

141
 FIGURE 4 - Modal for Heat Flow

z
Uniform Power Density
Input to This Area

No Heat Loss from

Die Surfaces
Except Bottom

All Power Flows Dut the Bottom of the Chip

Uniform Substrate at DoC

FIGURE 5 - Array of Sa•• Ar.a. in a Silicon Oi.

o o -r±-~ArtifiCial Boundary
o o
-:
I ~ By Symmetry

o 0-1[]-I-O
I 1

0000

142
 FIGURE 6 - Junction Temperature and Thermal FIGURE 7 - Junction Temperature and Thermal
Rasistance 85 a Function of Power Dissipated, Resistance as a Function of Power Dissipated,
Flange (Heat Sink} Temperature Flange (He.t Sink} Temperatur.
2OOr-r-~--r---------------------------, 200,--------------------------------,
19I1 Goometry-6TH 1911 Geometry-5NN
BeO Thickness - 60 mil BoO Thkknos, - 60 mil
180 180
- - - Thermal Resistance
170 - - - Thermal Resistance 170 - - - Junction Temperature
- - - Junction Temperature

~
;0:
z
0

~
~ 9Il

~ 80
70

60 60

50 50

40 40
30 30

20 20

10 10

°0~----~25~--.&----~----~---7.~--~~--~ 0
0 25

FIGURE 8 - Junction Temperatura and Thermal FIGURE 9 - Junction Temperature and Thermal
Resistance as a Function of Power Dissipated, Aesistance as a Function of Power Dissipated,
Flange (Heat Sink) Temperature Flange (Heat Sink) Temperature
40or-----------------------------------,
Geometry-1KF
380 BeO Thickness - 40 mil
360 Geometry - 9Nl
BoO Thicknes, - 60 mil
340
___ Thermal Resistance
320 - - - Junction Temperature

200

100

0~0----~----~5~0~--~7~5----~----~~~~--~175
FLANGE (HEAT SINK) TEMPERATURE !OCI

143
Ex perimental Verification Figures 10 through 12 are plots showing the cor-
Of Calculated Die Temperature relation of measured to calculated temperature for several
Actual temperature measurements are made with an geometries. under various conditions of flange tempera-
infrared microscope. Barnes Eng. Co. Model RM:CA. This ture (JOoC to ISaaC). supply Voltage. drive power, and
instrument uses an indium antimonide diode photo--
detector at liquid nitrogen temperatures to measure the
FIGURE 11 - Actual vs Calculated Die Temperatures
infrared radiance emitted from a 1.5 mil spot on the
surface being examined. The IR radiance versus tempera-
ture curve is calibrated by measuring the radiance at Geometry-9NL
BeD Thickness - 60 mil
various known temperatures monitored by a calibrated 400 • Average Temperature
thermocouple while the device is heated by external I - Temperature Range
means. An experimental calibration is necessary because
the radiance output of the device at a given temperature is
a function of the average emissivity in the area seen by
the microscope. and this average emissivity is a function
of the geometry and processing history of the device
in question. The effective emissivity depends upon the c

;
~

relatil'e amounts of metal and silicon and the infrared 250

transparency of the varying thicknesses of SiO:c glass
in the tleld of view. The calibration data of radiance <i.
versus temperature can be least-squares curve fit to an ~ 200

equation of the fonn T = ~A)~R)b. where A and b are the

fitted constants. and R the measured radiance. 150
The del'ice is then powered up in its circuit. and the
radiance data collected point-by-point around the surface
100
ot' the silicon die. A computer program inputs the array
of radiance data. calculates the actual temperature from
the calibration equation. and prints a map of the tem- 0050~--~100~--~15~0----f.20~0----~----~--~~--~~0
perature prot1le. as well as some statistical information CALCULATED DIE TEMPERATURE lOCI
about the temperature distribution.

FIGURE 10 - Actual vs Calculated Die Temperatures

~------------------------------------~

Geometry - 6TH
BeO Thickness - 60 mil
450-
• Average Temperature
- Temperature Range FIGURE 12 - Actual vs Calculated Die Temperatures
400- ~or-------------------------------------,

Geometry - I Kf
BeO Thickness - 40 mil
350 • Average Temperature de DiSSipation
I - Temperature Range
\

250 -

~ Ei
~
=> 200
~
'"<i.
=>
150
li
100

400
CALCULATED DIE TEMPERATURE lOCI

144
output load magnitude and phase angles from 50 n to MTBF as a function of power and ambient temperature.
over 30: I VSWR. The calculated temepratures seem to be The temperature lines are valid for any combination of
somewhat higher than measured at the higher power supply voltage, efficiency and drive power, by reading the
levels. The calculated temperatures are based on the power axis as power dissipated. The MTBF lines, because
calculated power dissipation, disregarding RF losses in the of the current dependence, have been constructed based
actual loads and circuits. upon the assumptions of l2.5-volt supply and 50% effi-
Metal Migration and Mean Time to Failure ciency, so that the power axis should be interpreted as
The calculated/observed temperature agreements are output power. It is possible to use the MTBF set of lines
seen to be close enough so that the calculated temperature at other conditions. Enter the graphs by reading the
can be used as the basis for reliability calculations of Mean power output parameter as power dissipated, and find the
Time Before Failure (MTBF) for metal migration based MTBF, then scale the MTBF by the ratio square of
upc,n Black's5 work. the 1'/ = 50% current to the actual current.

MTBF = (cross section)3

]2 . f(TO)
(6) MTBF =MTBF (from graph) X (I ('" 1'/ = 50%) 2
] actual
(8 )

Equation (6) is the equation used for calculating metal

migration lifetime, where the cross section refers to the
conducting stripe dimensions in cm 2 , and] is the current
in the stripe in amps. f(TO) is an Arrhenius function of TABLE 2 - Material Dependent Parameters

the stripe material, having the form:

Material B <P
f(TO) = B exp (-1>/KT) (7) Large Crystal Glassed AI 8.5 X 10- 10 1.2
IRef.51
The material dependent parameters Band 1> are shown in
Table 2. K is Boltzman's constant, and T is in degrees AI-2% Cu Alloy 7.9 X 10- 17 0.6
Kelvin. A series of graphs (Figures 13 through 16) have IRef.61

been constructed, one for each device, that present the

results of the calculations of device temperature and

FIGURE 13 - Metal Migration - MTBF FIGURE 14 - Metal Migration - MTBF

Geometry - 6TH Geometry - 5NN

Metalization -large Crystal Glassed AI Metalizatlon-LargeCrystal
Finger Dimensions; Width - 0.5 mil 125'C Glassed AI
Height-l.51' Finger Dimensions:
BeO Thickness - 60 mil Width-I.Omil
Operating Conditions: Vee = 12.5 V Height-1.51'
1,000 ~ ~ 50% 1,000 BeO Thickness - 60 mil

100 100
'"~
I
in

~
~ ~
" "
10 10

1.0 1.0

0.1 :-0---;;2=-5---;;50':------!7=-5---::100::----:-:,2::-5---::150;:---:::175 0.1 ;;"0---;;2=-5----;50':------;7~5--7,,00;;;------:-:::--;;=~:;::-'~--;;

CASE TEMPERATURE I'CI CASE TEMPERATURE rCI

145
 FIGURE 15 - Metal Migration - MTBF FIG U R E 17 - Geometry Code to Standard Part Cross-Reference

Geometry 12,5 28 50 Vcc(VII

125"C
Code AI AI Au AI Metal I
lKF MRF421 MRF422 MRF428A
5NN MRF243 MRF316
MRF453/A
1,000 MRF455/A
MRF460
9NL MRF245 MRF463 MRF317
MRF454/A MRF464/A
6TH MRF648 MRF327

100 MRF328
\ 175'C
To Scale Metal Migration MTBF
"
\ \2OO'C From 12.5 V to Other Operating Voltages
Keeping PD and 1'/ constant, then the current for 28 V
operation compared with that for 12,5 V operation
10
is given by:
112.5 X 12.5 = 128 X 28

G,ometlY-9Nl
112.5
-----
28
1.0 Metaliletion -l''1Ie Crystal Glassed AI 128 12.5
Finger Dimensions: Width -1.0 mil
H,ight-1.51' From Black's5 equation:
BeO Thielen... - 60 mil
Operating Condilions: Vee ~ 12.5 V
,,~ 50%
MTBFa 1.
12
0.1 =-0---!;25,------·-;50!::--~75;----;1+.00,-------;:12::-5--==~--''-:::! For like geometries, the ratio of the MTBF at 28 V to
CASE TEMPERATURE I'CI the MTBF at 12.5 V is:
FIGURE 16 - Metal Migration - MTBF
28 2
100,000 .---.---..--'T"--.-=;;--G-eom-etlY---1K-F----, MTBF28 = MTBFI2.5 X 12.5
M.talizetion -la'1l' CIY.I.I
Glassed AI MTBF28 = MTBFI2.5 X 5.02
Finger Dimensions:
Width-1.0mil
Similarly, for 50 V operation:
Heighl -1.51'
10,000 BeO Thickness - 40 mil MTBF50=MTBFI2.5 X 16.
Opereting Cond~ions:
VCC ~ 12.5 V
,,~ 50% Conclusion
We have discussed the elements of thermal resistance
and metal migration lifetime with particular attention
1000 paid to their variation with temperature as functions
of power dissipation and ambient temperature.
Graphical presentations of the results are included
which should be useful to the device user who is interested
in better reliability in his application.
100
References
1. G. A. Slack, Journal of Applied PhYSiCS, 35, 3462,
1964.
2. J. Elston, J. DeGoer, and Z. Miliailovic, 1. Nucl.,
10 Mater., 11,333,334, 1964.
3. Fulkerson, Moore, Williams, Graves, and McElroy,
Phys. Rev., 167,768-780.
4. Linsted and Surtey, IEEE Transactions on Electron
Devices, ED-19, 42,1972.
5. Biack,Proc. IEEE, 57,1587,1969.
6. Hall, ECOM, DAAB07-7OC 0164, October 1971.

146
 AN·879

MONOMAX - APPLICATION OF
THE MC13001 MONOCHROME
TELEVISION INTEGRATED CIRCUIT
Prepared by
Ben Scott
Technical Consultants:
C.1. Tsui, Hong Kong
Peter Bissmire, Geneva
Lowell Kongable, Phoenix
Mike McGinn, Tempe

This application note presents a complete 12" black and

white line-operated television receiver, including artwork for
the printed circuit board. It is intended to provide a good start-
ing point for the first-time user. Some of the most common
pitfalls are overcome, and the significance of component
selections and locations are discussed. The design has only 4
factory adjustments: H. Hold, Height, AGC Delay, and V.
Linearity, and there are no alignments.
Note that while this discusses MC13001 (525Iine, positive
tuner AGC) there are also parts for 625 line and negative
tuner AGC, in all combinations.

INrRODUCTION pation. Special attention was given to ESD (electro-

Monomax has been on the market since mid-1981.1t static discharge) immunity on all pins. An extremely
was originally developed in a joint effort between stable horizontal oscillator was devised_
Zenith and Motorola for the purpose of creating a high Additional features which resulted from this design
performance B&W.receiver. It was intended for all effort included: a completely integrated IF and detector
types of monochrome receivers, including the demand-- with no detector tuning or external filtering components,
ing portable and mobile applications, which require an on-chip dc contrast control which permits remote lo-
immunity to noise, "airplane flutter" and multi path cation of the control without shielded cable, and fully
signal conditions. Features suggested by these require- black level clamped video with blanking and beam cur-
ments included: noise filtering and cancelling, dual- rent limiting. The combination of system functions in the
loop horizontal PLL, countdown vertical, and a flexible Monomax chip permitted some elegant solutions which
AGC system_ would not have been practical or economically feasible
It was also required· that the resulting receivers be in more conventional designs.
low in component and manufacturing cost. To meet It is. not the purpose of this AN to describe the overall
this objective, effort was made to minimize external Monomax chip in any greater detail than is required
components (especially precision components) and for understanding receiver design decisions. The reader
adjustments; is urged to obtain a copy of the MC13001 data sheet
Above all, the receiver was to be reliable, so the chip available from Motorola Literature Distribution or
was designed to operate at low voltage and low dissi- Linear Applications. It contains some of the basic

147
 FIGURE 1 - Simplified Block Diagram

II~
+

+
FIGURE 2 - Monomax Functional Block Diagram

148
application information which will not be repeated in output. The audio output section is usually a Class B
this note. Also recommended is a paper entitled type, operated directly from 12 Vdc. An IC combining
"Monomax - An Approach to the One-Chip TV" by the sound IF, detector, and audio output is ideal in this
Gerald Lunn and Mike McGinn of Motorola. This can architecture. TDA1190 is an example which fits well
be obtained from the proceedings of the IEEE Chicago with Monomax.
Spring Conference on Consumer Electronics, June, Figure 4 shows the basic power supply structure for
1981, or from Linear Applications, Motorola. the ac line operated type of design. This is the most
Monomax is not difficult to apply. A functional TV economical and the most common approach for B&W
set is virtually assured on the first try. But as anyone television in most of the world, and it is the subject of
closely associated with television design can attest, much of this AN. Special thought was given to this
there are, in every new design, a number of small but type of set in the design of the MC13001 itself. Note
objectional problems which stubbornly resist solution. that the horizontal oscillator and driver are supplied
The receiver described here does not represent the "last through high value resistors directly from the rectified
word", but it is pretty close to production quality, and power line dc (120 V). Only 4.0 mA are needed into
it includes solutions to some of the most common Pin 18 to power the horizontal oscillator system. The
beginner's problems. In the following text, an attempt balance of the horizontal circuit is also line operated
will be made to explain component value choices and so it is fully operable from the line supply. The hori-
locations in terms of problems solved or behavior zontal section then produces the 12-14 Vdc for the rest
avoided, so that the future experimenter will be alerted. of Mono max (50 mAl, and for the tuners, the sound IF,
the vertical output, etc., about 150 mA in all. This
THE BASIC DECISIONS/POWER SUPPLY
method avoids the problem of developing 12 Vdc
One of the first considerations in a new TV design is directly from the line; i.e., the waste of power in a
whether the set is to be acldc (12 Vdc operable) or ac linear approach, the extra components for a switch·
line only. Monomax fits well into either, and has been mode dc-dc converter, or the cost of a line transformer.
used in production designs of both types. As in the previous example, the TDA1190 can be used
Figure 3 shows the architecture of an acl dc type for the entire sound system, but many designers prefer
with all systems operated from 12 V dc. In this case, to use a Class A, line operated, discrete output stage,
the horizontal output st.age is of the "boost" type, to and one of the standard sound IF Idetector ICs, slich as
minimize horizontal deflection current and make the MC1358, CA3065 or TBAI20. This removes the 12 V
yoke easier to manufacture. The flyback transformer supply ripple caused by loud low-frequency audio pas-
contains auxiliary windings which provide supply sages, but costs a small audio output transformer. This
voltages for the video output, picture tube grids, and is the approach presented in the complete receiver in
vertical deflection. Sometimes the boost voltage of 20 this AN, but it could be easily changed to the single·
to 30 Vdc is used as a power supply for the vertical chip sound system.

To Audio
• Boost
Output Stage

10
H. Output
17
H. Driver
181--+--~-,
+

MC13001
.I. .I. 0.01
MONOMAX REXT-
(See Data Sheet)
19f--......---<~---- +8.0 V
+ .I. 0.01
I

FIGURE 3 - Basic AC/DC Architecture

149
 140 Vdc
~ To Audio Output

I 120Vdc
To Video Output

120 Vae
,...--+1-----<-. H.V.

+12 V

FIGURE 4 - Line Operated Architecture

It is important to use good bypass techniques on all This means keeping color and sound subcarriers low
power supplies, not only for low frequencies, but also enough to avoid 920 kHz beat generation in the detec-
for RF. It is critical in prevention of faint but objec- tor, and yet not attenuating the sound so deeply that
tional vertical lines in the picture, caused by hori- good sound quieting is irretrievably lost. A well-
zontal deflection system waveforms getting into the proven characteristic for achieving this goal is as
supplies. Good high-frequency bypasses on Pins 18 shown in Figure 5, taken from tuner-mixer input to
and 19, with respect to Pin 16, are essential. detector. Of this, some selectivity comes from the
mixer-tuned circuits, but most of it is provided by the
THE IF
SAW filter.
The four stage IF in the MC13001 has 80 Ii V sensitiv- Table I shows some available types, data normalized
ity, sufficient for excellent overall performance when to 0 dB picture carrier. The major difference is the
used with an ordinary tuner and a conventional L/C depth of 41.25 MHz. In this regard, the Toshiba
input bandpass network. It is recommended that the F1032U, Kyocera, and the muRata parts are best for
input always be used differentially to reduce the pos- B& W design. The mixer-tuned circuits will supply the
sibility of feedback problems: The differential input
capacitance decreases from its normal 5.0 pF, to about
2.0 pF, in the top 10 dB of gain-range of the IF. This .10
can be used to narrow the input L/C filter, at very - ---- - - ---- - -- - ---~-~----

weak signals, to reduce overall detected noise, and

improve picture lock.
If a SAW (surface acoustic wave) filter is used, as in
this AN, the above bandpass "walking" technique can- -10 !g

not be used. Furthermore, if a SAW filter is used, an l:l

additional fixed gain-preamplifier is needed to over- -20 ~ - ----.-
come the 20 to 25 dB loss thus imposed. Nevertheless, ~
this approach has become increasingly popular with -30 '"
the introduction of low cost SAW filters, because it
eliminates a crucial and time consuming production
alignment. Adj. Pix
There is a steadily increasing supply of SAW filters
in the marketplace, so some criteria for choosing the -'0
Freq -MHz
best one for the design are in order. Bear in mind that .7
all of the video selectivity is concentrated in the tuner
40 42 43 44 4' 46 48

and the IF input filter in this design. In a B& W receiver,

it is important to obtain a good compromise of picture
and sound quality with a single selectivity channel. FIGURE 6 - IF Bandpass Characteristic

150
 TABLE 1 - Some Available SAW Filters

Toshiba Kyocera muRata

Relative Response FI032B FI032U FI032V FI052 KAF45MR-MA SAF45MC 027
39.75 Adjacent Picture -40 -48 -45 -40 -37 -37
41.25 Sound -12 -16 -6.5 -25 -18 -19
42.17 Color +1.0 0 0 0 0 0
Peak +4.0 +4.0 +4.0 4.0 4.0 4.0
45.75 Picture 0 0 0 0 0 0
47.25 Adjacent Sound -45 -48 -47 -40 -42 -38
Insertion Loss -18 -19 -18 -21 -23 -20

additional slight amount of narrowing required. The Remember that AGC loops have a large amount of
F1032V part is too wide, and FI052 is too narrow. gain, and fast AGC loops, with good airplane flutter
These are intended for color receiver architectures of performance, are especially vulnerable to deflection
different types. The SA W manufacturers loading currents. Only a few millivolts on the AGC lines from
recommendations should be adhered to closely to stray fields or ground loops can cause a significant
prevent ghosts (before and after the picture) caused "bar" in the picture. Keep the tuner AGe lead away
by capacitive feed·through and/or "triple transit" from yoke leads. The small bypass capacitor on Pin 11
reflections. further reduces this problem, and should be placed as
At the input of the MC 13001, it is important to use close to the Me13001 as possible.
good bypass capacitors on Pins 2, 4 and 6 with respect Monomax was designed so that in the strong signal
to Pin 1 of the MC13001. The best value was found to be region, "above the delay", the IF gain is held constant
a straight lead, low-inductance 0.02 "F disc ceramic while AGe acts upon the RF stage in the tuner. This
for reducing the infamous channel 6 beat. Pickup in means that a small amount ofIF AGe range may not
this area is also a possible source of vertical scan bars be accessible in the normal implementation. Optimum
in the picture caused by horizontal sweep currents. It setting of the delay pot keeps the RF section at maxi-
is desirable to keep the SAW filter close to Pins 1, 2, 4 mum gain for RF signal levels of from <10 "V to
and 6. See the PC board layout Figure 14, Also, the IF 1.0 m Vrms , using 40 dB ofthe IF AGe range. The tuner
preamplifier must be kept compact and well grounded is not likely to be able to provide more than 40-46 dB of
to prevent feedback and oscillation with the tuner. additional AGe, which will accommodate signal levels
AGC up to approximately 200 mV rms . This is adequate for
the Monopole antenna applications, but certainly
The AGC system was implemented here essentially doesn't offer a lot to spare. Above this level, the AGe
as described in the Data Sheet, including the AGC system loses control, the receiver overloads and even-
speed-up capacitor between Pins 9 and 10. This keeps tually falls out of sync. One way to improve this, and
the AGC airplane flutterresponse time fast, even when pick up the remaining 6.0 dB or so ofIF AGe capabil-
the signal is strong enough to move the AGC into the ity, is to put a resistor from Pin 11 to Pin 10. The value
tuner control region. The RF AGC delay setting is one of the resistor will be about 33 k for delay resistor values
of only 4 factory adjustments. Ideally it should be shown, but will have to be tailored to the particular tuner
made with a calibrated signal level, but acceptable used. This can also be accomplished by a resistor from
results can be obtained with a strong off-the-air signal Pin 9 to Pin 10. This, in fact, is the only solution in parts
and a switch type attenuator. A discussion of this providing negative tuner AGe.
adjustment is contained in Appendix 1.

iii
;; 40
o

i
a::
z
~

1.0 200 1.0

SIGNAL STRENGTH (mV) SIGNAL STRENGTH (mV)
FIGURE 7 - Modified AGC Curves
FIGURE 6 - Monomax AGC Behavior (Rasistor from Pin 11 to Pin 10j

151
THE SYNC SEPARATORS
Composite sync is stripped from noise-cancelled
video in a peak detecting sync separator, as shown in
Figure 2. The time constants for setting the slice level
of the detector are connected at Pin 7. As always, there
is the compromise between optimum noise immunity
and tilting of the slice level during vertical interval.
For best horizontal separation, a short time constant
is required. There is also an AGC anti·lockup system
which responds to the voltage at Pin 7. It also requires
a short time constant. A second, longer time constant
0.47

8.2 k 1+ -=-
:::

can be diode connected to the same pin, to prevent too

(A) ORIGINAL CIRCUIT
much charge-up during the vertical interval.
Composite sync is subsequently integrated internally
and fed to another amplifier whose emitter is brought
out at Pin 23. Satisfactory vertical sync can be
obtained (internally) by simply connecting Pin 23 to
a divider. Weak signal performance can be improved by
using an RC network on Pin 23 to make the separation
self compensating, as in the horizontal separator. Also
AGC from Pin 9 can be fed to Pin 23 to improve airplane
flutter vertical hold.
FLYBACKINPUT
(B) NEW CIRCUIT
The only flyback pulse input to the MC13001 is at
Pin 15. It takes care of keying the AGC, blanking the FIGURE 8 - Horizontal Phase Detector
video output stage, and phase locking the horizontal
system. The Pin 15 input is a base-emitter junction, The second horizontal phase detector compares the
with a reverse polarity diode for protection. The input fly back output phase with that of the oscillator, and
requirement is for a negative-going pulse of 0.6 rnA, develops a proportional dc voltage, which is filtered at
but it is best to choose a pulse voltage and series resis- Pin 14. This dc voltage then sets the slice level on the
tor to give about -2.0 rnA peak. This will make the oscillator ramp to produce the output timing desired.
effective width be the pulse width near its base. See Figure 9(a). Picture phasing can be adjusted
slightly by a high value resistor on Pin 14 to +8.0 V or
HORIZONTAL OSCILLATOR/ AFC ground. A 220 k to +8.0 V will move the picture about
Monomax contains a really unique group of features 2.0 p's to the left. A 220 k to ground will move it 2.0 p's
in this area: dual-loop; variable-loop-gain (bandwidth) to the right.
on the first (sync) PLL; externally adj ustable phasing Another application of Pin 14 provides a method of
in the second PLL; simple flyback pulse input, requir- changing the duty cycle of the horizontal output wave-
ing no ramp generation. These are described in detail form from Pin 17. Normally, the desired waveform
in the data sheet, and will not be repeated here. would be 50%. This has been assured in the MC13001
Shown in Figure 8(a) are the first PLL components by operating the slicer at 31.5 kHz. This permits output
as presented in earlier publications, and in 8(b) a new phasing correction without changing duty cycle, as
variation which has been implemented in this receiver. shown in Figure 9(a). In some receivers, when large
This very simple change retains the dual time constant amounts of dc power are drawn from the fly back, the
on the phase detector. The improvement is the 13 k/22 k "on" time of the horizontal output may have to be more
divider which sets a 5.0 V point for the return of the than 50% of the cycle. This can be accommodated by
longer time constant filter. Since 5.0 V is the reference feeding back some driver collector signal to the second
level in the oscillator, it is also the operating voltage at phase detector filter, as shown in Figure 10. This
Pin 12, and at Pin 13 when in-lock. The benefit, then, is imposes alternate slice levels and hence, the desired
that the 0.47 JLF doesn't have to charge up, so there's change of duty cycle. Some tentative values for a set
very little frequency pulling during power-up or power- configured like the one in this AN are given in Figure
down. This reduces audible chirps and momentary stresses 10. This was not actually used in the final design,
due to long cycles on the horizontal output device. Also because it wasn't needed. It is supplied here as a ref-
the picture locks-in quickly, which is highly desirable erence for future designs having more power drain
with fast warm-up picture tubes. from the horizontal output. Bear in mind that the
Note that the proper setting of the horizontal hold driver collector voltage would be much lower in the
control occurs when no average current flows through 12 Vdc receiver architecture mentioned earlier, requir-
the 390 k resistor, either to, or from, the oscillator. A ing much different values to implement this idea. A
simple alignment procedure is to set the average Pin 12 practical limit of control by this technique is about
to Pin 13 voltage to zero by adjusting the hold control, a 60/40 duty cycle. The 0.001 capacitors on Pin 17 and
when locked to a standard broadcast signal, using a the driver base are to "soften" waveform edges, to
high impedance voltmeter. reduce their radiation into signal circuits.

152
 OSC.
many customers like to have one, but also because it
permits using a smaller coupling capacitor for the
/\ /\ / \ / Ramp
Z1 \ Z1 \ ;?1 \ ) Pin 14 yoke. The smaller coupling capacitor saves money and
/i I \/, , \7i I \ reduces picture bounce, but introduces some curvature
I " I' which must be compensated. Feedback to Pin 21 pro-
I " ,
I " I vides overall output stage linearization and prevention
Pin 17 of deflection current change with temperature. It is
} Output also a handy place to feedback a variable parabolic
;.----
waveshape for linearity control, as shown in Figure 11.

J
(A) NORMAL APPLICATION. PHASING
SHOWN AT TWO CONDITIONS
Vj
I
,
I
,
I
I
I
I
uncompensated
Yoke Current

I I I
I I
I I
I I I I Correction
I

~ linearity
mmfbk I Signal at
~ I I~____ .__Jr - P1n17 I I I I
~ I I : Control
: r mal( fbk r I
(B) DRIVER COLLECTOR FEEDBACK TO PIN 14 . I I I Compensated
I . \'G'V- I Yoke Current
t ",\rt I
FIGURE 9 - Second Phase Detector Slicer I I
I ",a' \~... I

FIGURE 11 - Vertical Linearity Control

MONOMAX
17 14

to"" 'II~0.,,",
470 THE SOUND SECTION
0.001
1 47 k
r 820
001r
a l.I.
The buffered video detector output at Pin 28 is a
wideband signal used for sound take-off. A ceramic
sound take-off filter and detector "tank" were chosen
to eliminate alignment steps. The MC1358 is a popu-
lar, multi-sourced, FM IF, detector and dc volume
control. It can be used with conventional L-C circuits
FIGURE 10- Driver Feedback For Extended or the ceramic devices shown here. The L-C application
Horizontal Output "On" Time costs less in piece parts, but has a higher manufactur-
ing cost in assembly and alignment.
Keep in mind that a limiting IF produces a wide
spectrum of 4.5 MHz harmonics. The sound IF grounds
THE VERTICAL SYSTEM should be kept together and returned to Pin 1 by a
Aside from all of the sophistication of the count- single path as shown in the copper layout of Figure 14.
down vertical system within the Monomax chip, what Also it is a good idea to keep the input of the sound IF
remains to be accomplished outside of the device is IC close to Pin 28 to reduce radiation of video IF har-
fairly conventional. At Pin 20, there is an external monics, generated in the video detector, from getting
capacitor, charged from a high voltage, to produce a back to the tuner or IF input.
good linear ramp. It is discharged within the chip, In the receiver described here, an ac volume control
usually by vertical sync, but sometimes by the count- has been used. A potentiometer is placed between the
down circuit when sync is momentarily absent. It is MC1358 detector output, Pin 8, and the post ampli-
important for the capacitor to be a good stable low ESR fier input, Pin 14. The dc volume control, Pin 6, is
type and to be located close to Pin 20 and grounded as grounded for maximum volume. If the volume control
closely as possible to Pin 1 to avoid pickup ofhorizontal is to be mounted some distance away, and deflection
sweep which could hurt interlace. pickup is likely, then the dc volume control could be the
The approximately 1.5 V p _p waveform on Pin 20 is better choice. This can be done by ac coupling Pin 8 to
inverted and buffered to Pin 22 to drive the external Pin 10, and placing a variable 50 k pot from Pin 6 to
output circuit. In the receiver design in this AN, a fairly ground. The disadvantage is that the control contour
conventional vertical output stage has been used. An is less predictable in the dc control configuration. It is,
optional linearity control has been added, because nonetheless, a production proven method.

153
THE VIDEO OUTPUT tortion of high· frequency detail, due to excessive load·
ing ofthe video driver. This can be reduced by adding
Pin 24 provides up to 1.4 V, black·to·white video
a resistor between Pin 24 and the trap, and by return·
drive, black level clamped, with a widened and ampli·
ing the bottom of the trap to the video output stage
fied blanking pulse added. This is sufficient to drive a
emitter. The compromise chosen is shown in the full
single stage common·emitter video output transistor.
schematic. Again, it is good to keep these parts close
A dc voltage of 0 to 5.0 V applied to Pin 26, varies the
to Pin 24 to reduce radiation of video detector products
black·to·white amplitude at Pin 24 from 1.4 V to 0.1 V
back to the tuner and IF front end.
without changing the absolute black level ofthe output
voltage. Beam current limiting can also be used to The video output circuit can take many forms.
control maximum brightness. This is accomplished by Monomax was designed to accommodate full dc cou·
circuit shown in Figure 12. As beam current increases, piing, as described earlier. However, many TV design·
the H.V. winding current flowing in the 39 k resistor, ers, and users, don't like full dc coupling, because it
pulls the Pin 27 voltage down. When Pin 27 falls sometimes seems to go too black, creating the suspicion
below about 1.0 V, the contrast begins to be reduced. that some information is hidden. Also, a directly
This circuit was not used in the complete receiver in coupled video output to picture tube cathode usually
this AN, for reasons which will be explained shortly. requires a negative voltage for at least one of the grids
The black level clamp capacitor on Pin 25 is usually for proper set·up at high contrast settings. Finally,
shown connected to ground. It can also be connected to fully dc coupled designs are harder to protect from
+8.0 V to cause the screen to be blanked for about 1 power·off flash or spot burn.
second after turn·on. This permits the scan systems to For these reasons the receiver described in this AN
stabilize before the picture becomes visible. Note: If was a partially dc coupled type. This puts the bright·
the brightness control design window is set too high, ness control in the cathode circuit, removes the need
the raster may still be visible during start·up. for the brightness limiting configuration, and makes
There are several approaches to sound trapping in spot/flash prevention easier. (The diode and electro·
the video output stage: series tuned L·C from the lytic in Glare for this latter purpose).
video output base to ground; parallel tuned L·C in the
video output emitter; or a ceramic shunt element in the In the video output stage emitter, some dc set·up
video output base circuit. All of these can be detri· from the +12 V supply has been used to adjust the out·
mental to picture quality, if not carefully done. The put dc level, to minimize overall dissipation. Also some
ceramic element is in keeping with the "no alignment" additional vertical blanking has been fed through a
philosophy successfully implemented thus far, so there diode, from the top of the vertical yoke. This blanking
was a strong motivation to use it. However, shunt will be accomplished in the IC internally in later
loading Pin 24, if too severe, causes considerable dis· Monomax devices.

28

FIGURE 12 - Beam Current Limiting

154
APPENDIX I - AGC DELAY ADJUSTMENT means a horizontal (saddle) winding of about 3.4 mH
and a vertical (toroid) winding of approximately 3.0 n,
Ideally, a known antenna signal level of 1.0 mV
10 mHo Numerous substitutions are available, but
(300 n balanced) or 500 p. V (75 n unbalanced) is sup-
plied to the tuner input_ This signal level corresponds the above values must be adhered to for this set
to the threshold of "snow" in the picture, for most architecture.
receivers. With this signal level, the AGC delay pot is Horizontal Output Transistor - The board was
turned until the RF AGC voltage just begins to rise, designed for a TO-3 type, such as a BU205, BU204, or
and then is backed off slightly. The picture should be MJ12003. A plastic TO-220 type MJE12007 will do the
snow-free. If the RF AGC is permitted to rise, the job with some mechanical revision. The important
picture will start to show some snow, which therefore parameters are V(BR)CEX =1300 V and IC =2.0 A. A
represents less than optimum overall performance. If small amount of heat sinking, such as a U channel
the setting is backed-off too much, the delay may be with 2 flags of 1 square inch each is recommended. A
too large and mixer overload may occur at stronger mica or Thermalloy isolator is suggested to reduce
signals. shock hazard to the experimenter. If an acldc design is
The correctness of this setting should be checked contemplated, as referred to back in Figure 3, a lower
at weaker and stronger signals. At weaker signals, say voltage, higher current part like BU806 will be required
6.0 dB down, it should not be possible to improve the for the horizontal output, along with a different yoke and
picture noise by resetting the RF Delay. At stronger ftyback.
signal, say 40 dB stronger, there should be neither
snow or overload evident in the picture, although the Vertical Output Transistors - It is possible to
distance between these two conditions, as a function of "get by" with a TO-92 complementary pair, such as
delay setting, may be very narrow. The AGC system MPS6560 and MPS6562, or the new, tall TO-92,
should automatically avoid these troubles. It may be MPSW01 and MPSW51. However, the author's opinion
necessary to make a slight compromise to avoid over- is that these operate too hot, with dissipation ap-
load, which may produce a slight amount of snow in proaching 1 watt, each, worst case. Recommended
the 1.0 mV picture. alternatives include D40E 1 and D41E 1 in the TO-202, or
The above compromises can be achieved successfully TIP29 and TIP30 in TO-220. No heat sink is required.
without calibrated signals, with just a switch able The devices need only V(BR)CEO = 30 V and good
attenuator and a strong signal. Starting at strong hFE at 1.0 A.
signal, note the available AGC Delay setting range Video Output Transistor - For the load value
between picture overload and snow. Using the switched shown in this design, a case 152 uniwatt, such as
attenuator, reduce the signal strength and make sure MPSUlO, is best. The 300 V V(BR)CEO is not needed,
that neither problem appears. If necessary tweak the but the device must be "small geometry"; i.e., high fT
Delay, but don't move outside the original range. and low Ccb to preserve picture resol ution. A tall TO-92
Eventually the picture will get snowy, but the control or even an MPSA43, TO-92, can be used ifthe collector
will only be able to make it snowier. Setting it to the load is increased to 6.B k, but some picture quality will
optimum (just barely) should still be within tile noted be lost.
range.
Audio Output Section - The transformer should
be approximately 30: 1 turns ratio, capable of handling
APPENDIX II - COMPONENT & 1 watt into B.O n. The output transistor should be set
CONSTRUCTION DETAILS up at about IQ = 12-14 mA, and should be capable of
1.5 W continuous dissipation. A TO-220 type MJE2360T,
In order to make the enclosed PC board pattern easy
mounted on at least 3 square inches of aluminum is
to use, the following components are recommended:
suggested.
Remember that these are pertinent to this design
architecture and this specific design. Many variations H. Driver Stage - In the prototype receiver, the
are possible with a little redesign work. available driver transformer had only about 12:1 turns
ratio. This necessitated a large wattage dropping
Flyback - Gold Star Type 154-02BA with self-
contained H.V. rectifier. Certainly, substitution is resistor to provide the rather low-voltage, high-current
possible, but very careful attention to pin-outs and taps primary waveforms. It would be better to obtain a
is required. The primary is, of course, a 120 Vdc type, transformer of 30: 1 or so, to permit a more efficient
which corresponds to about BOO Vp _p positive pulse at driver stage. The 4.3 k/2.0 W resistor could then be
Pin 2. Pin 3 is a negative going pulse of 35 V Pop and reduced considerably. In either case a TO-92 driver,
Pin 7 is a negative-going pulse of about 120 VPop' The type MPSA42, is a good choice.
H.V. terminal, which is internal in the above model, SUMMARY:
would be a positive going pulse of about 12 kVp_p' Figures 13 and 14 provide the copper pattern for the
Very little flexibility can be permitted on these values. PC board and the component locations. Note that
Be careful to watch pin-outs and horizontal polarity. signal input circuits are compact and grounded near
Yoke -Gold Star Type 153-020A for 90° 12" - Pin 1. Subsequently these and all other circuits are
20 mm neck picture tube. It requires approximately connected to the central ground at Pin 16, without being
1.0 A p _p in both horizontal and vertical windings to interconnected beforehand. The full receiver schematic
give proper overscan in the 90° tube at 10-11 kV. This is given in Figure 15.

155
.....
01
m

BRIGHTNESS H, YOKE
CONTROL

FIGURE 13 - Component Layout (not full size)

 ~
0.
0.
o
o

w
[[
::::J
Cl
u::

157
 ~
. .~
w. I .,w ~
t
,,- 1 .....~" ••• ,.,
tr
.. : ,a
F~~';\A-:
-
1~~7
Lj
.01 r If£ ~5

......
en
CD

''f'W

FIGURE 15 - Complete Receiver Schematic

 AN925

UHF PREAMPLIFIER CENTERS ON BUDGET

DUAL·GATE GaAs FET
Prepared by
Gary Barbari, Applications Engineer, RF Products
and
Steve Lazar, Principal Staff Engineer, Advanced RF GaAs Development*

INTRODUCTION
This note describes the design, construction and per- ating frequencies. Table 1 lists the required information
formance of a 400-512 MHz preamplifier utilizing Moto- for the MRF966.
rola's GaAs dual-gate field-effect-transistor.
In two-way communications, the ability to receive a Parameter f = 400 MHz f = 450 MHz f = 500 MHz
transmitted signal depends on the systems' signal-to- 511 0.99 Lo 12' 0.98 Lo14' 0.98 Lo 15'
noise ratio (SIN). The SIN can be improved by increasing 521 1.60 L 165' 1.59 L 163' 1.59 L162'
the output power of the transmitter; by increasing the 512 0.004 L83' 0.004 L84' 0.004 L85'
gain of the antenna; or by improving the sensitivity of 522 0.97 Lo7' 0.97 Lo8' 0.97 Lo9.4'
the receiver. The first two solutions could be quite expen- fms 0.87 Lo 14' 0.81 Lo20' 0.81 Lo 16'
sive. A low noise preamplifier would be an economical fml 0.8 Lo9' 0.8 Lo 11' 0.76 Lo21'
solution for improving the receiver system noise figure. NFmin dB 0.9 0.9 1

TABLE 1
DESIGN S-Parameter and NF Data @
The main criteria in the selection of a transistor for a VOS = 5 V, lOS = 10 mA
preamplifier is low noise figure coupled with sufficient
gain to minimize the second stage contribution to the The MRF966 was matched by means of slug tuners to
system noise figure. The Motorola MRF966 is a GaAs obtain the minimum noise figure. The optimum source
dual-gate field-effect transistor designed for UHF (fms) and load (fm!) impedances were then measured
applications. on a network analyzer.
Designing impedance transformation networks The slug-tuned circuit used in this procedure is illus-
requires S-parameter and noise figure data at the oper- trated in Figure 1.

V05

1--cF-->r-< RF Output
~,....--:::-----L.-=-....J
RF Input >-To....:>H

FIGURE 1 - NF Test Circuit

159
 The network required to transform the optimum
impedances to the required 50-ohm source and load was
designed using a Smith Chart. The input matching net-
work is shown in Figure 2. At the input of the pream-
plifier it is necessary to transform the 50-ohm input
impedance to the optimum source reflection coefficient
(fms). Taking the values from Table 1 for 450 MHz an
input matching circuit can be designed using a series

450 n 50 n

C'

+5.0 V

FIGURE 2 - Input Matching Network

A 0 . . . - - - - - - - - - 0 A'

BO OB'

CO OC'
50 n Load
Transformed #30 AWG Polythermaleze
by 9: 1 Transformer

B
A
450 n
50 n

FIGURE 3 - Output Matching Network FIGURE 4 - 9:1 Transformer

160
capacitance, shunt inductance, and shunt capacitance. The output matching circuit could be designed using
Starting at the input of the device (rms), the shunt a shunt capacitor with a series inductor, but a more con-
inductance moves the impedance to the value of 50 + venient matching technique involves a 9:1 transformer.
j145 ohms (point A); (the shunt capacitor is used to fine This simple matching technique although not presenting
tune the inductor along the constant admittance circle). the optimum load reflection coefficient (rLl to the
Finally the series capacitance transforms point A to the MRF966 provides improved stability at the expense of
desired 50 + jO ohms center (point B). The required slight gain reduction. The 50 ohm impedance of the load
reactance value for the three components can be obtained is transformed to a value of 450 + j150 (point C, Figure
directly from the Smith Chart. From Figure 2 the shunt 3). The materials needed to construct the transformer
inductance moves the vector along the path to position are inexpensive and readily available. The lumped ele-
A. This move requires an XL of 104.2 ohms. Therefore ment form of the transformer and the winding procedure
the shunt inductor has a value of 37 nH at 450 MHz. The are shown in Figure 4.
shunt capacitor needs to be variable from 0.8-10 pF to Source self-bias is used utilizing a 100 n resistor. The
accommodate variations between devices. The series resistor will set the operating current at approximately
capacitance rotates the input impedance from 50 + j145 20 mAo Decoupling the source and Gate 2 is accomplished
ohms to the center of the chart (50 + jO) ohms at point using 1000 pF and 56 pF chip caps. Gate 2 is positively
B. Therefore, the required capacitive reactance is j2.9 or biased using a simple voltage divider circuit. A low pos-
j145 ohms which leads to a value of 2.4 pF at 450 MHz. itive voltage on the gate will lower the noise figure and
A variable capacitor (0.8-10 pF) will also be used here increase the power gain. The complete preamplifier sche-
to fine tune the preamplifier for a specific frequency over matic and the parts list are shown in Figure 5.
the 400-512 MHz band.

J2

t
RF
OUTPUT

J1
C1

1
RF
INPUT
C2 02

"::" "::"
R2 +7-15 V

R3

C1, C2 - 0.S-10 pF R3 - 7.5-Kilohm 0.125 Watt

C3, C4, C7 - 1000 pF Chip Capacitor Ll - 2 Turns No. 16 AWG 0.375" Diameter
C5 - 56 pF Chip Capacitor T1 - 4 Turns No. 30 AWG, Indiana General Core, F2062-1-01
C6 - 470 pF Chip Capacitor U1 - MC7SL05
CS - 0.1 MFO Mylar 01,02 - 1N4001
C9 - 10 MFO Tantalum 01 - MRF966
FTl - 1000 pF Feed Thru Jl, J2 - SMA-Type Female Connectors
R1 - 150-0hm 0.125 Watt B - Ferroxcu be Bead 56-590-65
R2 -12-Kilohm 0.125 Watt

FIGURE 5 - Schematic Diagram

161
CONSTRUCTION Do same for the input shunt capacitor. Solder the 450
The preamplifier is assembled on a 43 mm (1.7") x n wire on the transformer (Wire A in Figure 4) directly
38 mm (1.5") double-sided circuit board. The board to the drain lead.' All of the components should be on
material is 1.5 mm (0.062") Teflon-Fiberglass. A 1:1 the board.
photomaster of the top side of the board is shown in The preamplifier was built using "open chassis" con-
Figure 6. The under side of the board is used as a ground struction as shown in Figures 8 and 9 from brass extru-
plane and the copper foil is not removed. A 0.2" clear- sion stock. This technique was chosen to allow visibility
ance hole, centered between the device mounting tabs, of the various components. SMA style connectors were
is drilled to allow the MRF966 to fit flush with the pc utilized although other types are suitable at this
board. This location is shown on the photomaster. The frequency.
four sides of the board are wrapped with thin copper
foil and then soldered on both sides.

Top of PCB

FIGURE 6 - Pholomasler (nol full size)

Handling precautions should be taken before mounting

the MRF966. A grounding bracelet should be worn at all
times when handling the device. A well grounded sol-
FIGURE 8
dering iron should be used when soldering the FET.
Before mounting, cut the gate, drain and source leads in
half.
Place the MRF966 (Figure 7) flush with the pc board
(with marking face up) and solder the leads to the con- TUNE-UP PROCEDURE
ductive tabs located on the board. Using tweezers, place Apply a voltage, between 7 and 15 volts, to the de
the decoupling bypass chip capacitors as close to the input and check for 5 volts at the output of the voltage
device as possible. Installing the bias circuitry is very regulator and at the drain lead. Now adjust capacitors
straightforward. The locations of the components are Cl and C2 for maximum gain. By using this maximum
shown in Figure 8. Construction details of the 9: 1 trans- gain tuning procedure, a gain of about 20 dB with a
former are shown in Figure 4. Solder the Coil (Ll) noise figure of 0.8 dB at 450 MHz is obtained. To obtain
directly onto the Gate 1 lead and ground the other end. a minimum noise figure (measured to be about 0.5 dB
The placement of the coil depends upon the size and shape with an associated gain of 19 dB at 450 MHz) a com-
of the variable input capacitor (refer to Figure 8). mercial noise and gain analyzer is recommended, such
as the HP8970A or Eaton 2075 Noise Figure Meters.
With the noise analyzer in place, adjust Cl and C2 for
best noise figure. The variable capacitors on the input
of the preamplifier allow precise tuning at any fre-
quency in the 400-512 MHz band.

PERFORMANCE
The preamplifier was tuned for minimum noise figure
at 430 MHz and 480 MHz using the HP8970A noise figure
meter. The voltage was set at 12 V and the operating
current was found to be approximately 20 rnA. The var-
1 ~ Drain iable capacitors were adjusted to obtain a noise figure of
2 ~ Source 0.5 dB at 430 MHz and a value of 0.6 dB at 480 MHz.
3 ~ Gale 1 The gain at noise figure and noise figure optimum versus
4 ~ Gate 2 frequency curves are shown in Figures 10 and 11. Figure
12 shows the input and output return loss versus fre-
FIGURE 7 - Pin Configuration quency for the preamplifier tuned at 430 MHz, while
Figure 13 shows the same parameters at 480 MHz.

162
 A. Drill and tap for 4-40
screws. 3 places
B. Drill and tap for 2-56
screws. 8 places
C. Drill .125" hole. 2 places

4-A
0.03 I.B3
II I -0.5

-.--
+B B+
0.42

. f -0.25
-<--t;------------~,.,...-J .. ~ --0.17 . ~~-- --- -----~~-
:': -<'.c:
I
O.OB
1 - -0 .00
l;: +B B+ :1:
I
I 0.1 1.9 I 0.25 10~B I II
0.92
1.25
1.5
I
0.00 0.25 1.65 , ·B 0.00 0.5 0.75 1
FIGURE 9 - Amplifier Housing

0 2.0 0
,...... GI
2.0
8 1.8 8 .......... p 1.8
V
'" /"V
......... I
6 1 \
G 1.6 6 t"--. I
V ~p V i'--,
4 \ L I ,4 ~ ~ 14
4 ~
I
2 /' i,\ V 1.2 :i! ~ 12
V'\ "- L I .2
'\ \ L
"'"
::::>
V
0
8
6
I'.

'" "-
--
...-V
/ 1\
\
i"l.
1,0
0.86
0.6
if
~

z:
~
'"
ocl 0 /
\t!
2
<=JD...
8
6 N~
I -
/'
./ l'\'" 1.0

0.8 ~
0.6
£'

z·
w

NF - 0.4 0.4
I 0.2 0.2
o o o o
390 410 430 450 470 490 420 440 460 480 500 520
f. FREQUENCY (MHz) f, FREQUENCY (MHz)
FIGURE 10 - Gain at Noise Figure and FIGURE 11 - Gain at Noise Figure and Optimum
Optimum Noise Figure versus Frequency Noise Figure versus Frequency (Tuned @ 480 MHz)
(Tuned @ 430 MHz)
0
1'-.. "Sill
U r--- :::--...
.......
/
- 4.0 "- -4. 0 10- LL
"
/ ~
I'-.
~
i2
-8.0

-12
\. \
\
/I
1/
I ~
<n
<n
-8. 0

-I 2
'\.
, ;5111 /
(I
"
g I I IL g ~ '.L
z:
§ -16 \\ ~ -I 6 \\ 11
>- \ ::::> \\ /I
~ -20 i ~ -2 0 i1 I I
\ \ I
- 24 \ ,5221 -2 4 15221 \ I
\ II
- 28 -2 8
390 410 430 450 470 490 420 440 460 480 500 520
f, FREQUENCY (dBI
FIGURE 12 - Input and Output Return Loss FIGURE 13 - Input and Output Return Loss
versus Frequency (Preamp Tuned @ 430 MHz) versus Frequency (Preamp Tuned @ 480 MHz)

163
164
 AN932

APPLICATION OF THE MC1377

COLOR ENCODER
by Ben Scott and Marty Bergan
Linear I.e. Applications. Tempe. AZ

The MC1377 is an economical, high quality, RGB encoder for NTSC

or PAL applications. It accepts red, green, blue, and composite sync
inputs and delivers IVpp composite ·NTSC or PAL video output into
a 75 ohm load. It can provide its own color oscillator and burst gating,
or it can be easily driven from external sources. Performance virtually
equal to high cost studio equipment is possible with common color
receiver components. The following note is intended to explain the
operation of the device and guide the prospective user in selecting
the optimum circuit for his needs.

PREFACE
Since this device has applications in color cameras, Y = .59G + .30R + .11B
video games, video text and computer generated graph- R-Y = .70R - .59G - .11B
ics, it may attract potential users who are skilled in com- B-Y = .89B - .59G - .30R
puter architecture, but not familiar with the encoding of Texts on the NTSC system will show that studio mod-
color television. Perhaps they have spent extensive hours ulation is done on a different set of orthogonal axes called
viewing graphics on a full R, G, B wideband monitor. I and Q. Also they will point out that I is a somewhat
This preface is intended to caution that PAL or NTSC wider bandwidth than Q. The MC1377 does not permit
encoding, no matter how rigorously executed, will cause the circuit designer this refinement, but it should be
some degree of picture degradation. The process of en- noted that very few monitors or receivers contain any
coding involves some bandwidth reduction, which means circuitry to process the unequal bandwidths. (This is the
loss of high frequency detail, and it creates the possibility only compromise of standards in the MC1377 which can-
of spurious picture patterns, due to coding and decoding not be circumvented by application means.) Rotation of
system limitations. The original standards were estab- the coordinate system from IIQ to (R-Y)/(B-Y) does not
lished about 25 years ago and will probably be in use for constitute any further compromise whatsoever, and it
many years to come. It is not the objective here to detail makes the encoding formulae for PAL and NTSC the
these standards as many references l - 4 are available. Ap- same. It also aligns (B-Y) with the axis of the NTSC
pendix A shows pictorially why some loss of information color burst, for internal circuit simplicity and system
and detail is incurred. accuracy.
The MC1377 is capable of encoding NTSC and PAL
to virtually studio standards. It also can be used for very REFERENCES
low cost applications where appropriate, with some com- 1. Donald G. Fink, Television Engineering Handbook,
promises to picture quality. It can readily drive the 750 McGraw-Hill 1957.
input of a composite video monitor, or be used to drive a 2. Hazeltine Staff, Principles of Color Television,
UHF or VHF modulator so that color television receivers Wiley 1956.
can be used. 3. Gerald Eastman, Television Systems Measure-
ments, Tektronix 1969.
CIRCUIT DESCRIPTION 4. G. N. Patchett, Color Television, The PAL System,
Figure 1 shows a block diagram of the color encoder. Norman Price 1976.
The three color inputs at Pins 3, 4, and 5 are matrixed
to produce chrominance envelopes, (R-Y) and (B-Y), and
luminance (- Y) by the standard NTSCIPAL formulae:

165
 color
bandpass
transformer

8'>o-C""'/'v--, 1OOlsJ
0.1

4.43
MHz
0.1

12 Composite
Video
Output

1 1 1
• + +
Composite 15 "F
15"F
a 001 I 51 k 8.2 V Sync Input
R
15 "F
G
'- ___ -.-___
B
1.2 k
delay line
Inputs: 1.0 V p-p

FIGURE 1 - BLOCK DIAGRAM AND APPLICATION CIRCUIT

The (B-- Y) and (R- Y) signals drive two double bal- can be reversed by sensing when Pin 20 is high and Pin'
anced (double sideband suppressed carrier) modulators 1 is low, and momentarily pulling Pin 20 to ground with
whose carriers are set at 0' and 90', respectively. In the an external switch.
NTSC mode, the outputs ofthese chroma modulators are The color subcarrier source for the modulators can be
added to produce composite chroma. Burst envelope or implemented by free running the on-chip crystal oscil-
"burst flag" is applied to the (B--Y) modulator in the lator, or by external drive into Pin 17, or by a combination
negative direction to produce a burst pulse at a reference of both methods. The common collector Colpitts oscillator
angle of 180'. Composite chroma is amplified and buf- is completed by connecting a standard tv receiver color
fered to Pin 13 (to permit external bandwidth control as crystal and capacitor divider as shown. The oscillator is
desired) and is then fed back into the IC at Pin 10 to be followed by a 90' phase shifter to provide the quadrature
combined with the luminance component. The luminance signal to the (R-Y) modulator. The direct oscillator out-
signal is also "looped out" from Pin 6 to Pin 8 to permit put is taken as reference 0' and is fed directly to the
insertion of a delay line to match the delay incurred in (B--Y) modulator.
the chroma channel due to bandwidth reduction. The The composite sync input at Pin 2 performs three im-
passive components used in the chroma and luma chan- portant functions: it provides the timing (but not the
nels are like those used in the most common implemen- amplitude) for the sync in the final output; it drives the
tation of color television receivers. black level clamps in the modulators and output ampli-
In PAL mode, burst flag is driven into both modulators fier; and it triggers the ramp generator at Pin 1, which
equally to produce a 225'/135' burst phase. The output produces burst envelope and PAL switching signal.
phase, or polarity, of the (R- Y) modulator output is al- The ramp generator at Pin 1 is a simple R - C type in
ternately switched from 90' to 270' on successive hori- which the pin is held low until the arrival of the leading
zontal lines, before being combined with (B--Y), which edge of sync. The rising ramp function passes through
remains at 0'. The switching of the modulator polarities two level sensors - the first one starts the burst pulse
for PAL mode is driven by the latching ramp generator and the second stops it. Since the "early" part of the
through the PALINTSC control. This control allows PAL exponential function is used, the timing provided is rel-
switching when Pin 20 is open, and stops when Pin 20 atively accurate from chip-to-chip and assembly-to-
is grounded. The PAL phase can be detected at Pin 20 assembly. Fixed components are usually adequate. The
and controlled by means of external logic. The PAL phase ramp continues to rise for more than '12 of the line in-

166
 terval, thereby inhibiting burst generation on "half in-
terval" pulses on vertical front and back porches. Burst

(.1
4. 4V t---- Limits
is also inhibited if sync is wider than the time required
for the ramp to reach the sense levels, as is the case
100% during vertical sync. The ramp method will produce burst
for de Green
1.0 V (p_pl coupled Input on the vertical front and back "porches" at full line in-
inputs (Pin 41 tervals. In most applications, this discrepancy from stan-
dards will not cause any problem. If it is objectionable,
(bl 2.2 V
and if a proper burst envelope signal is available, then
100% it can be injected into Pin 1 directly. Another method,
1.0 V (p_pl Red suitable for either PAL or NTSC, will be described later.
Input
(Pin 31
STANDARD INPUT LEVELS

Inn n n The signals into Pins 3, 4, and 5 should each be 1 Vpp

(cl
1.0V(p_pl W UUUL
100%
Blue
Input
(Pin 51
for standard, fully saturated, color output levels as shown'
in Figure 2. The levels are important because the IC will
generate a predetermined 0.6 Vpp sync and 0.6 Vpp burst
at the output, and it will need 1.0 Vpp input signals to
produce the corresponding full luminance and chromi-
nance amplitudes. The inputs are internally biased and
(dl 5.0 present a 10 k input impedance. The 15/LF input coupling
Composite capacitors are sufficient to prevent tilt during the 50 or
4.0 Output 60 Hz vertical period. Input signals can be dc coupled (to
(Pin 91 save the cost of the capacitors), provided that the signal
levels are between 2.2 V and 4.4 V at all times. It is
3.0
essential that the portion of each input which occurs
B.2 Max during the sync interval represent black for that input,
(el
1.7 Min because it will be clamped to reference black in the color
Sync
modulators and the output stage. A refinement such as
0.9 Max Input a difference between black and blanking level must be
II I'
II I' (Pin 21 incorporated in the RGB input signals if required.
0
-0.5 Min
II
.. J -------------LJ-
THE SYNC INPUT
As shown in Figure 2, the sync input can be varied
(fl 10.5 over a wide latitude, but will require bias pull-up from
most sync sources. The important requirements are that
Chroma during the period between sync pulses, the voltage must
10.0 Output be above 1.7 V and below the 8.2 V internal regulator.
(Pin 131
During sync, the voltage (negative going) must extend
9.5 below + 0.9 V and should not exceed - 0.5 V (to prevent
substrate leakage in the IC). For PAL operation, cor-
(91 4.35 rectly serrated vertical sync is necessary to properly trig-
Chroma
ger the PAL divider. In NTSC mode, simplified "block"
4.0 Input
(Pin 101 vertical sync can be used but the loss of proper horizontal
timing may cause "top hook" or flag waving in some
3.65
monitors. An interesting note is that composite video can
be used directly as a sync signal, provided that it meets
the sync input criteria.
(hi
5.2h ~ Luminance
Output
mE LATCHING RAMP (BURST FLAG)
GENERATOR
4.3~ V- (Pin 61
The recommended application is to connect a close
tolerance (5%) 0.001 J.tF' capacitor from Pin 1 to ground
and a resistor of 51 k or 56 k from Pin 1 to the 8.2 V
(i) 2.St--"1 ~ luminance internally regulated supply (Pin 16). This will produce

1 l..,..r"""
2.1
Input
(Pin 81
a burst pulse of 2.5 to 3.5 IJ.S in duration, as shown in
Figure 3. As the ramp on Pin 1 rises toward the charging
voltage of 8.2 V, it passes first through a burst "start
threshold" at 1.0 V, then a "stop threshold" at 1.3 V, and
finally a ramp reset threshold at 5.0 V. If the resistor is
FIGURE 2 - SIGNAL VOLTAGES reduced to 43 k, the ramp will rise more quickly, pro-
(Circuit Values of Figure 1)
ducing a narrower and earlier burst pulse (starting about

167
 ~5.0
~
o
>-
o.U
..
E"O
a:
~

a:" 1.3
1.0

0+=---¥~4--------------------4~~==~

~U,',-
IPin2)
I I
L
I I

o 5.58.5 Time IJLsl 50 63.5

FIGURE 3 - RAMP/BURST GATE GENERATOR

0.4 J.I.S after sync and only about 0.6 J.I.S wide). The burst It is also possible to do both; i.e., let the oscillator "free
will be wider and later if the resistor is raised to 62 k, run" on its own crystal, and also be capable of being
but more importantly, the 5.0 V reset point may not be overridden from an external source. An extra coupling
reached in one full line interval, resulting in loss of al- capacitor of 50 pF from the external source to Pin 17,
ternate burst pulses. . and a signal of 1.0 Vpp was adequate with the limited
As mentioned earlier, the ramp method does produce experimentation attempted.
burst at full line intervals on the vertical porches. This
is not rigorously correct for studio applications. If exter- VOLTAGE CONTROLLED 90'
nal burst flag is available, a positive pulse of between The oscillator drives the (B-Y) modulator and a volt-
1.0 V and 1.3 V (absolute value) can be applied to Pin 1 age controlled phase shifter which produces an oscillator
in the NTSC mode. This approach must be handled care- phase of90' ± 7' at the (R- Y) modulator. Ifit is necessary
fully, because a square pulse smaller than 1.0 V will not to adjust the angle to better accuracy, the circuit shown
trigger the burst generator, and a square pulse larger in Figure 6 can be used.
than 1.3 V will shut off the burst generator almost before Pulling Pin 19 up will increase the (R-Y) to (B- Y~
it starts. This direct injection technique does not provide angle by about 0.25'/pA. Pulling Pin 19 down reduces
the ramp to operate the PAL flip-flop. Another method, the angle by the same sensitivity. The nominal Pin 19
suitable for either PAL nor NTSC, is shown in Figure 4. voltage is about 6.3 V, so the 12 V supply is best for good
It requires a "vertical drive" pulse, starting at the lead- control, even though it is unregulated. In most situations,
ing edge of vertical blanking and as wide as the interval the result of an error of 7' is very subtle to all but the
where burst is not wanted (usually 9 line intervals). The most expert eye. For effective adjustment, the simplest
extra transistor and diodes in the circuit add an abrupt approach is to apply RGB color bar inputs and use a
step at the beginning of each line ramp which inhibits vectorscope. A simple bar generator giving R, G and B
burst generation. outputs is shown in Appendix D.

THE COLOR REFERENCE RESIDUAL FEEDTHROUGH

OSCILLATORIBUFFER COMPONENTS
As stated earlier in the general description, there is As shown on the MC1377 data sheet (and in Figure
an on-board common collector Colpitts color reference 2 (d), the composite output at Pin 9 for fully saturated
oscillator with the transistor base at Pin 17 and the emit- color bars is about 2.6 Vpp , output with full chroma on
ter at Pin 18. When used with a common low-cost tv the largest bars (cyan and red) being 1. 7 Vpp. The typical
crystal and capacitive divider, about 0.65 Vpp will be device, due to imperfections in gain, matrixing, and mod-
developed at Pin 17. The adjustment of oscillator fre- ulator balance, will exhibit about 20 mV pp residual color
quency can be done with a series 30 pF trimmer capacitor subcarrier in both white and black. Both residuals can
over a total range of about 1.0 kHz. Oscillator frequency be reduced to less than 10 mVpp for the more exacting
should be adjusted for each unit, keeping in mind that applications. The black imbalance is primarily in the
most monitors and receivers can pull in 1200 Hz. modulators and can be nulled by sourcing or sinking
If an external color reference is to be used exclusively, small currents into clamp Pins 11 and 12 as shown in
it must be continuous. The components on Pins 17 and Figure 7. The nominal voltage on these pins is about 4.0
18 can be removed, and the external source capacitively Vdc, so 8.2 V is capable of supplying a pull up source.
coupled into Pin 17. The amplitude at Pin 17 should be (Pulling Pin 11 down is in the 0' direction, up is 180'.
between 0.5 Vpp and 1.0 Vpp, either sine or square wave. Pulling Pin 12 down is in the 90' direction, up is 270'.)

168
 +8.2 V

47 k 6.8 k
= MC1377

47 k

-8.0 V
°U
- - - - -

1-9H~
Vertical
- - Drive
Pulse
2.2k

.001 51 k
=
FIGURE 4(_) - VERTICAL PERIOD BURST INHIBITOR

FIGURE 4(c) - STANDARD RAMP CIRCUIT FIGURE 4(8) - BURST INHIBITOR RAMP CIRCUIT
INOTE FAINT RAMP CAUSED BY VERTICAL DRIVE PULSE)

169
 o.e In 17 ,. OIcOut
""'"
19 Deeoup

--, 010 ~" 71~l--+-+-+.JI

~r1-r+------
V V 5.Ok . , - _......

~
+~ ~. R2J
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t
1.211.

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Go'
1.011. 6.811. 2" 22k 10k

"7

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2"
~"

RllS
10k

AOO -
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'" 117 R120

r-- Al14 10k

~7108
20

"t-"'"

Rll' lo,
,".12 R12J Rl26 R129~
lS II.
5.3k 18k J9k 2111.

rJ. m

fiGURE 5 -

170
 ChI'OlNl Out 1:1

-
I22k 10k 22k
,I 27k
R29 R33 R34
R28
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"

~
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R43
10k
R44
22k
R45
'00
R49
'Ok
,,~
R52
'Ok

"
J:Tl J:'
R.,
10k

" J= A-VCMimp
12

I Chromlln
10

~.
_ _ _ _ _ _ _-+_1-..:.>.=,85
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R124
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R13S
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R'"
4.7k
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22k
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27k
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L- t..!:'" ml
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I~~~ nl6
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15kTl'S ~R:~~ n21 R'"
220 Composite Video Out

I-t:~'~:h
220 0'34 220 VI_Damp
220 220 7

R127 R'S9
R'"
10k Rl39 R145
40k Uk R'Sl
27k lOr.
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r
_______________________________ ,"
~-~v~'n~.

L-___________________________________________________________
~
-
~
v
~
~
~
.
INTERNAL SCHEMATIC

171
Any direction of correction may be required from part to pass circuit between Pins 13 and 10. For proper color
part. (Note that pulling Pin 11 up can produce a residual level in the composite output, a mid-band insertion loss
carrier on the horizontal back porch which is the same of3.0 dB is desired. The bandpass circuit shown in Figure
phase as burst, and can result in an almost normal color I, using the TOKO fixed tuned transformer (see Appen-
display even with burst not present.) dix B) gives this result. One of many tv color IF bandpass
circuits could also be used. When such a bandwidth re-
duction is inserted, the chroma is delayed by approxi-
+12 V mately 350 ns (as shown in Figure 8).
This 350 ns delay results in a visible displacement of

~--'--'1~~"il0k
the color and black and white information on the final
display. The solution is to place a delay line in the lu-
minance path from Pins 6 to 8 to realign the two com-

I 1.Q1 ponents. Again, a normal tv receiver delay line can be

used. These delay lines are usually of 1.0 k to 1.5 k
characteristic impedance, and the resistors at Pins 6 and
8 should be selected accordingly. A very compact, lumped
FIGURE 6 - ADJUSTING MODULATOR ANGLE constant delay line is available from TDK (see Appendix
C for specifications). Some types of delay lines have very
low impedances (approximately 100 ohms) and should
+8.2 V not be used, due to drive and power dissipation require-
ments.
470 k In some applications, it may be possible to delete both
12}--....- - - - \ M - - -......~10 k the bandpass transformer and the delay line. For in-
stance, when the RGB information itself is very low
resolution, i.e., very narrow band (less than 1.5 MHz),
no cross-talk would be generated in the encoder (see Fig-
ure 9). Keep in mind, however, that the standard monitor
11}-~----~~~------~10k or receiver will still "see" an incorrect luminance side-
470 k band at X'. This points up the value of at least some
chroma bandwidth reduction in the encoder. A simpler,
+8.2 V lower cost bandpass circuit is shown in Figure 10(a). It
provides the proper insertion loss, approximately ± 1.0
FIGURE 7 - NULLING RESIDUAL COLOR CARRIER IN BLACK MHz bandwidth, and about 100 ns delay.
The circuit shown in Figure lO(b) is even less costly,
but has about 6.0 dB greater loss, provides very little
bandwidth reduction except to remove the baseband
LU~ feedthrough, and produces essentially no delay.
I
I

Chroma:
x X
c:
---+------...
'iii
FIGURE 8 (.:J

White carrier imbalance at the output can only be 1.0 2.0 3.0 3.58 4.0 5.0
corrected by juggling the relative levels of R, G and B la) ENCODER OUTPUT WITH LOW RESOLUTION INPUTS
inputs for perfect balance. Standard devices are tested AND NO BANDPASS TRANSFORMER
to be within 5% of balance at full saturation. Black bal-
ance should be adjusted first, because it affects all levels
of gray scale equally. There is also usually some residual
baseband video at the chroma output (Pin 13), which is
most easily observed by disabling the color oscillator.
Typical devices show 0.4 Vpp of residual luminance for 1.0 2.0 3.0 3.58 4.0 5.0
saturated color bar inputs. This is not a major problem Ib) STANDARD RECEIVER RESPONSE
since Pin 13 is always coupled to Pin 10 through either
a bandpass or a high pass filter, but it serves as a warning
FIGURE 9
to pay proper attention to the coupling network.
It will be left to the designer to decide which, if any,
THE CHROMA COUPLING CIRCUITS compromises are acceptable. Color bars viewed on a good
Without going deeply into the subject, it is generally monitor can be used to judge acceptability of step lu-
true that monitors and receivers have color IF 6.0 dB minance/chrominance alignment and step edge tran-
bandwidths of ±0.5 MHz. It is therefore recommended sients, but signals containing the finest detail to be en-
that the encoder should also limit the chroma bandwidth countered in the system must also be examined before
to approximately ± 0.5 MHz through insertion of a band- settling on a compromise.

172
 0.001 0.001
Pin~f--'V\I'Ir--""'''''''--i~10

(a) Insertion Loss: 3.0 dB ~

Bandwidth: :: 1.0 MHz M~';;torl
Delay: ~ 100 nsec MC1377
=
56 pF 1.0 k 0.001 FIGURE 11
Pino;;-if--'W'\r-......-.----:l~ 10
4.7 k printed circuit board will be even more effectively cooled.
(b) Insertion Loss: 9.0 dB The MC1377 is designed to operate from an unregu-
Bandwidth: :: 2.0 MHz lated 10.8 to 13.2 volt dc power supply. Device current
Delay: 0 into Pin 14 with open output is typically 30 to 32 mAo
= .To provide a stable reference for the ramp generator and
FIGURE 10 - OPTIONAL CHROMA COUPLING CIRCUITS
the video output, a high quality 8.2 V internal regulator
is provided. The 8.2 V regulator can supply up to 10 mA
THE OUTPUT STAGE for external uses, with an effective source impedance of
The output amplifier normally produces about 2.0 Vpp less than 1.0 ohm. This regulator is convenient for a
and is intended to be loaded with 150 ohms as shown in tracking dc reference for dc coupling the output to an RF
Figure 11. This provides about 1.0 Vpp into 75 ohms, an modulator. Typical turn-on drift for the regulator is ap-
industry standard level (RS-343). In some cases the input proximately + 35 m V over 1-2 minutes in otherwise sta-
to the monitor may be through a large coupling capacitor. ble ambient conditions.
If so, it is necessary to connect a 150 ohm resistor from
Pin 9 to ground to provide a low impedance path to dis- SUMMARY
charge the capacitor. The nominal average voltage at Pin The preceding Application Note was intended to detail
9 is over 4.0 volts. The 150 ohm dc load causes the current the application and basis of circuit choices for this ver-
supply to rise another 30 rnA (to approximately 60 rnA satile tv signal encoder. A complete MCI377 application
total into Pin 14). Under this (normal) condition the total with the MC1374 VHF modulator is shown in Figure 12.
device dissipation is about 600 mW. The calculated worst The internal schematic diagram of the MC1377 is pro-
case die temperature rise is 60'C, but the typical device vided in Figure 5. Iffurther assistance is needed, contact
in a test socket is only slightly warm to the touch at room Motorola Linear and Military IC Division, Applications
temperature. The solid copper 20-Pin lead frame in a Engineering.

3.58
':.J-__.....-f-ll"

MC1374
4 MC1377

.001

r-~~f--+---lHI " defitvllne

14
75
"
J;'O
®
VIdeo Audio
":"

1'1219157
..olar 0"'
bandpass
transformer 0.1 .01 .01

+ 12IJdc (see Appendix 81

FIGURE 12 - APPLICATION WITH VHF MODULATOR

173
 APPENDIX A

In full RGB systems, three information channels are and sync are applied. The individual components of lu-
wired from the signal source to the display to permit minance and color can then be separated by use of a comb
unimpaired image resolution. The detail reproduction of filter in the monitor or receiver. This technique has not
the system is limited only by the signal bandwidth and been widely used in consumer products, due to cost, but
the capability of the color display device. Higher than it is rapidly becoming less expensive and more common.
normal sweep rates may be employed to add more lines The unequal bandwidths of I and Q cannot be imple-
within a vertical period. Three separate projection pic- mented with the MC1377, first because I and Q axes are
ture tubes can be used to eliminate the "shadow mask" not used, and second, because outputs of the two color
limitations of a conventional color CRT. modulators are added before any bandwidth reduction is
Figure (b) below shows the "baseband" components of imposed. Most monitors and receivers compromise the
a studio NTSC signal. As in the previous example, energy "standard" quite a bit, by using responses as shown in
is concentrated at multiples of the horizontal sweep fre- Figure (c). Some crosstalk ofluminance information into
quency. The system is further refined by precisely locat- chroma, and vice versa, is always present. The accept-
ing the color subcarrier midway between luminance spec- ability of the situation is enhanced by the suppression
tral components. This places all color spectra between of the color carrier and the generally limited ability of
luminance spectra and can be accomplished in the the CRT to display information above 2.5 MHz. If the
MC1377 only if "full interlaced" external color reference signal from the MC1377 is to be used primarily to drive
conventional non-comb filtered monitors or receivers, it
Spectral Energy Is Always Concentrated
would be best to reduce the bandwidth at the MC1377
At Horizontal Sweep Frequency Multiples
to that of Figure (c) to lessen crosstalk.

Red Chroma
Channel
Gain ~-----.....
L.uminance
I Channel

G~" ~111I"'lt'"
I

I
I
: l :~ DI
I
1.0 2.0
f(MHz)
3.0 3.58 4.0

~1I"nIIiT
I
FIGURE FIGURE 13(c) - TYPICAL MONITORfTV
Blue

1.0
1
2.0
f(MHz)
1
3.0
n D
4-8 -::;." (R-Y)
~ '&. (90°)

FIGURE 13(a) - SPECTRA OF A FULL RGB SYSTEM

...o ~
.~
'feiIOIN
(7680)
\ \
\

- .
8.8
.~
~
"0

" ..
c
o "
VI.Q
~ Color Burst
(180°)
(B-Y) 0°

Q
Luminance "
VI "
VI

'"
"0
.€
Q.
E
«
g
"0
>lillJWllWllIllli.ljl.UWllUillIoW
a 1~ ~o ~o FIGURE 13(d) - COLOR VECTOR RELATIONSHIP.
f(MHz) IfQ SYSTEM versus (R-Y)f(B-Y) SYSTEM
SHOWING STANDARD COLORS
FIGURE 13(b) - NTSC STANDARD SPECTRAL CONTENT

174
 APPENDIXB
A PROTOTYPE CHROMA BANDPASS TRANSFORMER
TOKO SAMPLE NUMBER 186NNF-10284AG

0.7 mm Pin Diameter

Toko America Unloaded a (Pin 1-3): 15 @ 2.5 MHz

5552 West Touhy Avenue Connection Diagram Inductance: 30/,H ± 10% @ 2.5 MHz
Skokie, IL 60077 Bottom Viaw Turns: 60 (each winding)
(312) 677-3640 Wire: #38 AWG (0.1 m/m)

APPENDIX C
A PROTOTYPE DELAY LINE
TOK SAMPLE NUMBER OL122401D-1533

I' 1.26 Max

32.0
"I H 0.35 Max
9.0

----
'-' '-' '-'
"Marking -~t---...
T

y.
0.93 Max
23.5

!
- ,O~,.~", ~: -=: .=°1="·~: :U;
-_·1- j i
+
-I; II foil t 0.04
0.2 ±
""".00'
0.65 ±0.03
5.0±1.0
I
0.788 ± 0.08//
20.0 ± 2.0 0
I
b /
0
~ I- r--I f--~ I -
~ 0.08 Radius Max
TDK Corporation of America 2.0
4711 Golf Road
Skokie, IL 60076
(312) 679-8200 "MARKING: PART NUMBER, MANUFACTURER'S IDENTIFICATION,
DATE CODE AND LEAD NUMBER.
Item Specifications
1 Time Delay 400 ns ± 10%
2 Impedance 1200 Ohms ± 10%
3 Resistance Less Than 15 Ohms
4 Transient Response with 20 ns Rise-Time Input Pulse I-P_re_-S_h_o_o_t_:_10_0_IIo_M_a_x_ _ _ _ _ _ _ _ _ _ _ _ _--i
Over-Shoot: 10% Max
Rise-Time: 120 ns Max
5 Attenuation 3 dB Max at 6.0 MHz

175
 APPENDIXD
AN RGB PULSE GENERATOR

BNC 4.7 "F 10 k

1S~.I'"-+""""""......-.t
Composite 10 k
Blinking 2.2 k +5.0 V
Reg.

MC74LS112A 112 MC74LS112A

3.3 k 0.1 0.1

MC1455 2.2 k
~ 14
~
l1J 5 Q9'1--+......-I
3.3 k

750 pF

1.8 k

470

RGB PULSE GENERATOR

TIMING DIAGRAM

~ (From Composite Blanking)

154 kHz Clock

Blue Output

Red Output

----,'------' Green Output

----,~------------~

176
 AN1019
NTSC Decoding Using the TDA3330, with
Emphasis on Cable In/Cable Out Operation
Prepared by
Ben Scott and Khalid Shah
Bipolar Analog Ie Division

PREFACE THE SANDCASTLE INPUT

The TDA3330 is a composite video to RGB Color "Sandcastle" is a familiar term to European TV engi-
Decoder originally intended for PAL and NTSC color TV neers. It is basically a 0 V baseline with a 4.0 V blanking
receivers and monitors. The data sheet is oriented toward pulse and a 10 V burst-gating pulse on top of it, as shown
picture tube drive, rather than cable level outputs. This in 'Figure 1. Sometimes the expression "super sandcas-
application note is intended to supplement the data sheet tie" is used, which means that composite blanking is
by providing circuits for video cable drive, such as used present, i.e. vertical and horizontal blanking, in addition
in video processing circuits, frame store, and other spe- to the burst-gating pulse. Sometimes the vertical blank-
cialized applications, and to expand upon the functional ing is 2.5 V and the horizontal is 4.0 V, sometimes both
details of the TDA3330. are at 4.0 V. In the TDA3330, the blanking portion is only
used to provide a blanking waveform at the blanking
CIRCUIT CONSTRUCTION TECHNIQUES output, Pin 11, which is used to supply "extra" blanking
The best solution is a single or double sided PC board, in the picture tube driver application. Pin 11 is not used
such as shown in Figure 11, with as much ground plane in other applications, so the blanking portions of the
as possible. The oscillator components at Pins 8 and 9 "sandcastle" are not required. For the "cable to cable"
must be close to the pins. A low profile socket is accept- decoder, all that the TDA3330 really needs at Pin 15 is
able for prototyping. Wirewrap is definitely not recom- the burst-gate pulse. Pin 16 should be grounded.
mended. In most respects the part is not sensitive to The burst-gate pulse has 3 functions:
layout, except for the oscillator, however, unwanted pic- 1. Gating the color IF gain control (ACC) so that IF gain
ture artifacts, beats and noise are much easier to control is adjusted to keep burst amplitude constant;
with a good ground plane layout. 2. Setting the black level in the R, G, B outputs, and
3. Gating the color phase detector (APC) so that the VCO
MEASURING THE OSCILLATOR can be phase-locked to the burst. See the block dia-
gram in Figure 2.
The oscillator amplitude at Pin 9 should be about
400 mV pp , measured with an ordinary 4.0 pF/10 Mil
scope probe. Keep in mind that the oscillator frequency
is 3.58 MHz and is part of a phase-locked loop with only
a few hundred Hz pull-in range. The scope probe load-
ing is enough to push the oscillator into or out of lock. 10
It is recommended that Pin 9 be observed initially to
ascertain that it is running, and then leave Pins 8 and
9 alone. A procedure for adjustment will be covered 40 - - BLANKING

later. Of course, an output buffer (emitter follower) can I BASELINE

be connected to Pin 9, permanently, and the Pin 9 tuning I
capacitor reduced accordingly. I I
I I ~
I
I mJi ~.lllITnril i1 COMPOSITE
VIDEO

Figure 1. Sandcastle

177
 CO~6~~1TE o---.....- - l
INPUT

SANOCASTLE OR
BURST-
GATE INPUT

LUMINANCE IYI
INPUT
17
12

OUTPUT 13
CHROMA OUTPUTS
IF OUTPUT MATRIX
14

Figure 2. Simplified Block Diagram for NTSC Mode

It is important that the burst-gate pulse into Pin 15 be at maximum at 5.0 Vdc; the output is reduced 6.0 dB .
at least 8.0 V and timed correctly with respect to incoming when the control is 3.5 Vdc, and is reduced about 40 dB
video, as shown in Figure 3. If the gate pulse is too late when the control voltage is 1.0 Vdc.
or too wide it will still be present after the blanking has
ended, leading to serious errors in black level, color level
and VCO lock. The burst-gate pulse can sometimes be
obtained from the same equipment that supplies the
video, or it can be generated by a couple of one-shots
BLANKING 1 . - - - - 1 1 1 / ' s - - -.....--I
and a sync separator; see Figure 4. Another method is
to separate sync. Use a one-shot pulse stretcher to make
an 8-8.5 !,-S wide pulse for Pin 15, and then put the sep-
arated sync into Pin 16. (Pin 16 could be called the "burst-
gate inhibit"). This will prevent the first part of the Pin SYNC
15 pulse from gating sync, which would upset the black
level clamping function; see Figure 5.

THE LUMINANCE PATH :::U:t 50~OI'S ~

The outputs at Pins 12, 13 and 14 are positive-going
B.OV MIN - .----,
video, with the sync pulse almost completely' removed.
The black level of the output remains constant as the
contrast, saturation and hue are changed. The contrast
control changes both luminance and chrominance
10-3.5/,s
BURST·GATE WIOTH

together, so that, for example, output color bar wave-

forms maintain the same shape. The DC level of all out-
puts is moved by the brightness control, with no change
in the peak to peak signal amplitude. The brightness con-
trol can change black level from 1.4 V to about 6.7 V as
the control voltage on Pin 18 is raised from about 2.0 V
to 5.0 Vdc. See Figure 6. The contrast control, Pin 19, is Figure 3. Burst-Gating

178
 COMP Idl
VIDEO

VVIDEO
ilCLAY GATE WIDTH
+ 5.0V o---.~:;:==~-----==::;----' I II
/, :.A'" 1.7 k --U--;-SYNC
0.0039
I II
~DELAY

II
n i d i BURST·
----.J L...::.GATE

-12Vo---.--~---.--~

BURST·GATING PULSE
22k TO TOA3330 PIN 15

',. MC3346
TRANSISTOR ARRAY

Figure 4, Method of Obtaining Burst-Gate from Composite Video

The maximum output voltage, black to white, is about due to the ACC of the color IF. Therefore, it is important
7 times greater than the black to white level at Pin 17. to note that the TDA3330 can be ·set up to work with
For a composite input signal of 1.0 V pp ' there is 0.5 Vpp different levels of input, but it is not automatically com-
at Pin 17, due to the delay line matching resistors. This pensated for input changes. Also note that at 5.0 Vpp out
is about 0.35 Vpp white to black and gives about 2.5 Vpp and max brightness (black level out 6.7 V) there will be
max at the outputs. The input to the total circuit can be clipping of the positive peaks. The upper limit for the
doubled to 2.0 V pp ' which then yields about 5.0 Vpp at output is about 10 V.
Pins 12, 13, and 14. However, note that any change in Troubleshooting note: If a proper (positive) video sig-
input amplitude requires readjustment of the saturation nal is AC coupled into Pin 17, and a proper burst-gate is
control for correct chromailuma proportion. This is applied to Pin 15, there should be video out, regardless
because the luminance component directly follows the of any aspects of the color processing portions of the IC
input, while the color component is almost unchanged

,',
SYNC SEPARATOR J-H,-_S_TR_P~_i~_~_ER_.J:I----"" BUR;TO;l~E'~NPu T V'" VIDEO

~
I TO PIN 16
'BURST·GATE ,v--
INHIBIT INPUT o Ib' SYNC

'BV=rL
Ie' STRETCHED
o SYNC

Figure 5. Alternate Method of Gating from Video

179
 THE CHROMA PATH
The chroma input is derived from the composite input
by a simple 3.58 MHz single-tuned bandpass circuit with
about ± 0.5 MHz (6 dB) bandwidth. The chroma portion
of a color bar pattern should look like Figure 7. The circuit
components recommended in our application circuit
should yield about 100 mVpp of burst at Pin 22, but any-
thing from 10-200 mVpp will work. The output of the
chroma IF is at Pin 24, where the burst shculd be about
150 mVpp. There mayor may not be chroma present,
depending on the contrast and saturation control set-
tings. (Both controls have exactly the same effect at Pin
24, changing the picture chroma amplitude between the
burst pulses.)

GREEN OUTPUT PIN 13 - NORMAL

WHITE BRIGHTNESS CHANGES BLACK LEVEL fROM
1 4 V TO 6.7 V WITHOUT CHANGING p.p
CONTRAST CHANGES p.p AMPlITUOE , ,,~vRE
WITHOUT MOVING BLACK LEVEL CHROMA
BLACK IADJUSTABLE
AMPlI'UDE'

Figure 7. Chroma IF Output, Pin 24

Troubleshooting note: If there is 1.5 Vpp of burst at Pin

24, the burst-gating pulse is either too small or incorrectly
positioned in time.
The chroma IF output from Pin 24 is coupled to the
chroma demodulators, Pins 4 and 5 by a small capacitor.
(Note: 100 pF performs better than tr,e 1.0 nF on the data
sheet; it reduces luminance component feedthrough.)
Tweaking of demodulator balance to reduce residual
chroma subcarrier in the outputs can be done at Pins 4
and 5 by the trimmer technique shown in Figure 8. This
is a fine tuning which is usually not needed, but is avail-
able for the demanding application.

r--1>----l 24

B
nU
wiWn nU U n RlIHliTI
C U T PIN '2 SATURATION TOO HIGH 1k

56k

IV ,OOk
BLUE OUTPUT. PIN 12 HUE MISADJUSTED
47pF

Figure 6. Some Normal and Other Waveforms Figure 8. Optional Tweak of Demodulator Balance

180
 OUT OF LOCK - 600 mVpp

IH+· 63.5", f.- HORIZO~TAL PERIOD

Figure 9. veo Lock - Voltage at Pin 7

COLOR LOCKUP APPENDIX

If the required chroma is present at Pins 4, 5 Isame as Initial Setup Sequence for TDA3330 Evaluation Board
Pin 24). and if the oscillator is known to be running, then After connecting a Composite Video Signal In and con-
lockup is just a matter of adjusting the trimmer ori Pin 9. necting the Sync, Red, Green and Blue outputs to an
As noted earlier, the scope probe cannot be put on the appropriate RGB monitor, follow the subsequent steps,
oscillator for this adjustment. Instead, put the scope on in order, to adjust the 11 variable components to optimize
the AFC filter, Pin 7. Waveforms as shown in Figure 9 will performance of the RGB decoder:
be observed as the trimmer is adjusted. 1. Look at the signal out of the collector of the 2N4402
Lock-in range is about 18-22 pF with the typical socket transistor. Adjust POT #9 so that the Composite Video
and PC board and ordinary IRadio Shack) 3.58 MHz TV Signal at this point is 1.0 Vpp.
crystal.
2. Set POTS #2 and 3 to approximately the middle of
their values Ii.e., 50 kfl). This helps in making the sub-
BUFFERING THE OUTPUTS
sequent adjustments.
In order to be able to drive a cable, it is necessary to
3. POT #7 sets the Burst-Gate Width and POT #8 sets
provide an output amplifier. The design shown in Figure
the Burst-Gate Delay relative to the Video Sync Signal.
10 has two additional benefits:
Use a dual input oscilloscope and look at the Video In
1. It provides an opportunity to reduce the residual 2nd signal and the Burst-Gate Signal at Pin 15 of the
harmonic ofthe color subcarrier 17.16 MHz) by means TDA3330. Adjust POT #8 so that the Burst-Gate Signal
of a trap, and begins -·250 ns after the Sync Signal ends. Next adjust
2. It reduces the DC level another 0.7 Vdc at the emitter POT #7 so that the width of the Burst-Gate Signal is
of the 2N4401, and an additional 2:1 reduction due to 3.5-4 IlS. Note: See Figure 3.
the 75 n series R into the 75 n cable. Therefore, the
4. Put the oscilloscope probe on Pin 7 of the TDA3330.
black level into the cable can be as low as 0.35 V, for
Adjust the Variable Capacitor, connected to Pin 9, until
the minimum brightness control setting.
the VCO is In Lock. This will happen when the trace
signal drops from -650 mVpp to less than 100 mVpp.
MISCELLANEOUS GREMLINS Try to make the signal as small as possible, possibly
It has been reported from the field that the internally down to dc. (Make tilt flat) Note: See Figure 9.
supplied NTSC mode switch current 113 in Figure 12 of 5. Put the oscilloscope probe on Pin 17 of the TDA3330.
the data sheet) is occasionally insufficient. This is char- Adjust the 10 IlH Variable Inductor to minimize
acterized by a decoder which intermittently decodes and Chroma Signal Feedthrough.
then "color kills." In the killed mode, Pin 3 is above 1.5 V
6. In order to fine tune chroma demodulator balance,
and Pin 2 is below 0.7 V, which holds the saturation con-
remove the chroma signal from the Composite Video
trollow loff). This can be fixed by putting 22 k from Pin 3
Signal In lor, alternatively, turn the Saturation POT all
to VCC. This supplies additional current into Pin 3, caus-
the way down). Look at the Red output on the oscil-
ing an internal latch to pull Pin 3 low Ihave faith), and
loscope and adjust POT #2 to minimize subcarrier
returns Pin 2 to an open state so it can be varied by the
from the V Signalli.e., R-V) input. Next look at the Blue
Saturation control.
signal and adjust POT #3 to minimize subcarrier from
the U signal Ii.e., B-V) input.
SUMMARY
7. POTS #1,4,5 and 6 can next be adjusted to optimize
The TDA3330 has a wide range of functional capability
picture color quality. Suggestion for doing this is to
with relatively simple application circuitry lance under-
set Saturation IPOT #1) and Brightness IPOT #5) to
stood). It is hoped that this paper will assist users in
middle and then adjust Contrast IPOT #4 and Hue POT
becoming familiar and satisfied with it.
#6) till picture colors are approximately right. Next
adjust POT's 1 and 5. Repeat the above sequence until
satisfied with color quality of picture.

181
 I~v-----------------I
r-------------~

I 0.1 I
I 1m I 011 I
~ I ~I
I 39k I
I
!If_'~7:F 2
,: kO 2N44_0_0_.....
L 4.7k 470
I
I
I 10 k I I
I
l~P~N~I~T AMP~E~ _ _ _ =-__ J 2.2k
I
BURST·GATE &
I
I
SYNC OUT
GENERATOR
______ =-___ J
400ns
OELAY LINE
12k ~ 12 Vdc
~2k
15 k

B2

IBM

'NOTE RED &

GREEN OUTPUT
CIRCUITS ARE
IDENTICAL TO
BLUE OUTPUT
24 23 22 21 20 19 1B '7 16
ORIVE CIRCUIT
-5Vcc

II
10k
TDA3330P

50k
12

SATURATION -12 Vdc

220k

33
r-----------,
I ·12 Vdc I 1Bk ----...,
1000
I I I
I I 2N4401 BLUE
I I ,J.l0,uF I
75
OUTPUT
I I )
1
I
I I L____ _ 47
"
I I 150
I ONBOARO 5 V REGULATOR l... ______ _ ., 1.Ok
I I
I NOTE: 5.0 V Regulator IS induded for convenience
I
I and for the SN74LS221N. If the TDA3330P is
to be operated from unregulated 12 V, the controls I
I should be operated from unregulated (tracking) 5.0 V. I
I ___________________ I
L
~
Figure 10. TDA3330 RGB NTSC Decoder Circuit

182
NOTES~ 1. For the 390 pF and the 22 pF capacitors in the 3.58 MHz and in the 7.16 MHz traps. silver mica capacitors should be used for better trap
performance.
'. 2, The board layout is for Toko part #BTKANS-9439HM .
...3. Board layout will accommodate a Toko or a TDK 400 ns delay line.
4. A.3.58 MHz crystal available through Radio Shack was used.

Figure 11a. TDA3330P RGB NTSC Decoder Evaluation Board, Component Layout

183
 . i· ~:i 1.. 11 1':'

........ ... .-
'" .......
••. . " . .

• _ .
•••
-~..
•I
-
• •••
.
•• •••• • ~
IEI1Ii!lB •

-_ I.
...........
...
..•,._.. .. ...- -
~-
I

• •••
.....-

...- -.....--- _.....

•• ........ ..I ••
••• ..... . I, Figure 11b. TDA3330 RGB NTSC Decoder
Evaluation Board, Component Side
(not full size)

1....
- - - - - - - - - - - 4.000" -----------·~I

Figure 11 c. TDA3330 RGB NTSC Decoder

Evaluation Board, Bollomside (not
full size)

184
 AN1020
A High-Performance Video Amplifier
For High Resolution CRT Applications
I. INTRODUCTION The emitter followers provide a combined output 80th the emitter current and the collector cur-
This application note describes the superior signal from a low Impedance, or "stiff" source. ThiS rent of thiS stage follow the base voltage almost
performance characteristics of Motorola CRT stiff source makes the entrre circuit Insensitive to instantaneously. Computer simulation has shown
driver transistors in a state-of-the-art video load variations and to different methods of connect· that the transition times are less than 1 ns. The
amplifier. In particular, the high speed obtain- ing the Video amplifier to the CRT. transconductance may be Increased during the
able with low DC power consumption is shown. transition times by adding the "peaking-network"
A circuit which is insensitive to load variations R6, C2, C3. Adding thiS network is very much
III. THE CIRCUIT
and interconnect methods is given. Irke adlustln9 the rise time in the probes of fast
oscilloscopes. In the cascade circuit under discus-
A. The Input Circuit Sion the "peaking" network compensates lise
II. APPROACH Refer to the cirCUit diagram In Figure 1. A fast time deterioration at the collector by speeding
The performance requirements for the amplifier are pulse generator is required for accurate perform-
these: up the emitter current of Ot. ThiS procedure
ance data_ The Tektronix Model PG502 IS a good must be applied with moderation ~nce it may
example of a pulse generator for optimum perlor- aHect the large-signal swing capability. The
Voltage Gain 20 mance, versatility and p"ce considerations. The resistor, R6, should be equal to or larger than
Rise and fall times 3 nS pulse generator has a rise time in the range of .8 R4. The capacitor, C2, determines the length of
Output 40 V p.p min. ns and an output impedance of 50 ohms_ A time dw'ng which "peaking" occurs. The product
Overshoot 5% max. minimum-loss L-pad IS used between the generator of R6 and C2 is typically a few nanoseconds.
Load capacitance 8 pF min. and the base of the driver transistor, Ot. The Im- The trimmer, C3, can be used for fine-tuning,
Power supplies 60 V. 5 V. - 5 V pedance level at this pOint is designed to be 75 but is usually not important and may be omit-
ohms. The voltage attenuation of the matching crr- ted. If there IS lead inductance associated With
The voltage gain IS obtained In a transconductance
CUlt IS 0.64. the path from the emitter of Ot through C3 to
amplifier In the form of a common-emmer,
common-base cascade CIrcuit. In this crrcuit the load ground, use of C3 may cause ringing at high
capacitance is Isolated from the casco de by a set of B. The Cascode Circuit frequencies.
complementary emitter ·followers. Thus, the
capacitive loading on the cascode IS low. which 1. The Common-emitter stage uses an 2. The common-base stage uses an LT1817
allows operation at a moderate dissipation level. LTlool transistor In a TO-39 package. The transistor In a TO 11 7 package. Since the tran-
em mer current of 70 mA IS supplied from a - 5 sistor must dissipate continuously some two
The emlller followers are biased at a Class "8" V source via resistors .R4, and R5. For ac, only Watts of DC power, good heatsinklng IS man-
operating pOint. They conduct only dUring voltage R4 at 15 ohms IS operative. R4 and the bUilt-in datory_ The TO-117 package provides a hlgh-
tranSitions. while charging or discharging the CRT emmer-ballast resistor of 1.6 ohms, determine conductance thermal path to a heatsink or
capacitance. ThiS operation IS Similar to the way The transconductance of 01, which IS then 60 chaSSIS. At the same time, it adds only minimal
highly effiCient C·MOS logic ICs functIOn mAN. capacitance to the Circuit.

·60V

Figure 1. Circuit Diagram of Video Amplifier

185
Figure 2A. Rise Time at 10 V pop Figure 2B. Fall Time at 10 V pop

Figure 2C. Rise Time at 40 V pop Figure 20. Fall Time at 40 V pop

Figure 2E. 10 nsec Pixels 10 V pop Figure 2F. 10 nsec Pixels 40 V pop

186
The common base stage has near unily current display With high contrast and many tranSitions, One may be tempted to use slower Instruments,
gam and acts as an Impedance translormer, pro the current In Q3 and 04 may become ap such as a 200 MHz type, and correct mathe·
vldlng a current snurce at Its collector This cur preclable, causing the transistors to heat up The malically for the addlliOnal transition lime can
rent charges the combmed collector capaCilances elevated lunctlon temperature shilts the bias tobuted by the scope We do not recommend
01 D2, and the emlttel lollowers, OJ and 04, pOint Irom Class "B" In the drrectlon 01 "AB" thiS approach since slower scopes appear 10 pro-
which add up to about 5 pf at the opera ling duce wave shape distortions which lead to
pOint. To this total one must add about one pf II the emitters 01 these transistors were can mISleading ose time values
01 stray capacitance A load or "pull up" resistor nected drreClly. a DC component 01 current
01 430 ohms IS used at the collector 01 the would lIow Irom the 50 V supply through the IV. AMPLIFIER PERFORMANCE
common base transistor, OJ The rrse time at deVices III ground ThiS "pole current" would lur figure 2 contatOs photographs showtOg ose and fall
this pornt may be calculated to be ther heat up the lunctlons and might lead 10 times at 10 V and 40 V peak to-peak sWing. Also
thermal lunaway In the WCUIt descrrbed, thiS shown are some response curves generated by the
tr " 35· 2 • P, • 430 • 6 pf 5 7 nS Situation IS prevented Irom occurrrng through the well known CIrCUit analYSIS program SPICE Careful
use 01 the emitter stab,IrZlng reSistors Rill and modelling 01 the semiconductors used, according to
RII USing CapacllOr, C4, prevents detefloratlon the theory 01 Gummel and Poon, resulted In good
This value IS Improved by the addillon 01 a
01 the dynamiC operation 01 the weult agreement between computer and laboratory
peaking COil 01 22jJH Theoretically, the rrse
generated pertormance data. In addition, computer
lime could be reduced by up to 40°'0 IWlthout
A Simpler, more pflmltlve way to aVOid thermal analYSIS olfers InSights, which cannot be obtained by
overshoot I by optimizing the Inductance Due III
problems. IS to use IlIlly one bias diode, or none practical measurements
the nonlinear nature 01 the capacitances 10 be
at all DOing [hiS, however, has serra us eHects
compensated lor here, dlHerent ellects result lor
on the gray scale I,nearrty at mid range Shown III figure 3 are the superrmposed plots of the
flse and lall times ThiS situation requrres a com
Input voltage at the base 01 01 and the output
promise resulting III a practical Improvement 01
4. The output circuit The lT1839 and voltage across the CRT capacitance The second set
less than the theoretical transit Inn time Never
lT5839 translslOrs have excellent peak current 01 plots, figure 4, displays the collector current wave
theless, 3 ns tranSillon times are obtained at the
handlrng capabllrtles The" emitter currents react lorm 01 0 I and the combined emitter CliCUltS of the
collector 01 Il~ by means 01 the emlller peaking
vrrtually Instantaneously 10 the base voltage complementary set of emlller followers The collector
discussed earlier
Even when supplYing several hundred mlill current 01 01 shows clearly the effect 01 "peaking,"
amperes 01 peak charging current, the base to rntroduced by the emitter CIrculi components, R6, C2
The lT1817 IS packaged In a common base con
emitter gam holds up well It IS therelore and CJ Note that under lull sWing condilions (40 V
figuration ThiS means that the transistor base IS
pOSSible to drrve more elaborate load configura pp output I, the wavelorms are not qUile sym-
connected to two symmetllcal low Inductance
tlons than a bare capacrtance ThiS abllily may metflcal The effect on the tranSition times 01 the
base leads As IS well known, base lead Induc
ease Interconnect problems The errcult described output voltage, however, IS mlOimal
tance may cause Instabllilles In common base
configurations To prevent thiS Irorn happening, In figure i IS powertul enough to accommodate
a piece 01 shielded cable between the CRT and The example shown In both figures 3 and 4 cor
base damping reSistors, Rand Ra, have been
the Video amplrller A tWin-lead line or a Single responds to a pIXel time 01 IOns, which IS the prac-
added The value 01 these resistors depends on
wrre connection may also be used Instead of the tical mlOimum lor a system With 3 ns tranSillons.
the deVice bias pornt and the crrcult layout II
shielded cable The crrCUII IS nOl only able to When operating conlinuously at thiS rate, approx-
oscilialions occur, they would be near a Glga
drrve elaborate Interconnect networks, but also Imately 25mA 01 average current flows In each one
hertz or higher and therelore may nOl be seen
10 handle substantially larger CRT capacitances 01 the emlller lollowers ThiS causes a Significant flse
on anything but a sampling OSCilloscope They
Without slgnll,cant penalties In flse and fall In case temperature for these deVices. It IS therefore
Will aHect flse times and output sWing capablll
trmes for Instance, thiS errcult IS capable of dflv recommended that clip-on heat radiators be used
ty Instabilities may be eaSily detected WITh a
109 15 pf wrth 3 8 ns tranSition times There IS no electocal penalty lor thiS measure, since
spectrum analyzer connected to the Input lack 01
the collectors are on ground potential
the Video amplifier Enough Signal will feed back
through the collector capacitance 01 O' to reach In all cases, the presence 01 additional reactive
crrCUI! elemems causes the output CIrCUit to have Heatslnklng becomes absolutely mandatory If one ex-
the analyzer
resonances which Will cause onglng or over plores the limits 01 the amplifier by operating at 100
shoots, rI the output errcult IS not properly MHz and beyond
3. The emitter·followers, (b and 0" are a
damped To thiS end, a varrable reSistor, R12, IS
complementary parr of tranSistors, lT1829 and V. CONCLUSION
Included In the CIrCUit When adlusted for crrtlcal
lT5839, In TO·39 packages The transistors are An amplifier was developed which meets all needs of
damping, the wavelorm Will look smooth across
biased to the threshhold 01 conduction by two a high-resolution CRT monitor, While practical can·
the load capacilance
diodes, 0I and 02 These diodes should be siderations played an Imponant pan In the CliCUil
relatively large, slow rectll,er types, each pro realizalion, the pflmary purpose was to demonstrate
In the demonstralion CliCUil, Iflg. 11, a 65 pf
vld,ng no more than 0 5V 01 bias wilh a lor transistor capability It IS hoped that enough
chip capacitor Simulates the CRT cathode
ward diode current of 70mA The diodes have background Information was given to allow the
capacrtance It IS connected across a speCial lack,
low, largely capaCItive Impedances at high Ire reader 10 tailor hiS ClrCUil to hiS speCifiC needs.
which has been deSigned for the TektroOlx fET
quencles, and should be connected with short
probe, Type 6201 Probe, lack and chip have a
leads between the bases 01 III and 04
combined capacitance of 8pf The fET probe
The emiller followers prOVide temporary charging may be used In conJunclion wilh Tektronix
currents to the output CirCUit whenever the sampling scopes or reaHlme scopes with band·
voltage across the load IS changed. In case of a Widths of 300 MHz or more.

187
SPOOLED: 84·07·24.16:22
STARTED: 84·07·24.16:22. ON: AMIC BY: PSI LEGEND
LEGEND: ':1I130Dl
0: V 11001 '.1111101)
+:11'13, TIME "(JODI
TIME VnOD)
°1-------- 0.0000·01 1.5000+01 3.0000+01 4.5000+01 6.0000-01 2.000001 1 0000·01 0.000001 1.0000·01 2.000001

·/··_·---·0.0000·01 3.750102 1500002 1.125001 1.!iooO·Ol

+J-------- -1.5000.00 -7.5000·01 0.0000·01 7500001 1.5000-00

.- 1_
, ...
, ,
,, I

,• '-"r~~~:
I VOhage'ACrOSSICAT Calhode Capacitance ..........

.'lnpuIVoItage(Ql Basel
:1
;1
.!
·1
'---
.'.i
,,
"'r1',
Emiller Curren! of
PNPFoilower
'
,
15 15 \
,
+-----i~40V--.;.....-

~
20 20

Figure 3. Computer Generated Voltage Plots Figure 4. Computer Generated Current Waveforms

188
 AN1021
A Hybrid Video Amplifier
For High Resolution CRT Applications
Motorola RF Devices has used their unique high CONSTRUCTION The power consumption is typically 3.0 watts for
frequency RF semiconductor capabilities and thin average picture content and a maximum of 6.0W
film hybrid expertise to produce a hybrid video A_ Mechanical for 10ns continuous black to white transitions or
amplifier with less than 2.9 ns rise and fall time The amplifier is housed in a proven package, worst case situations. The electrical pin connec·
for a 40 V output swing. This video amplifier pro- which consists of a plastic housing, attached to tions are shown in Figure 2.
vides a low power dissipation solution to a prob- an aluminum heatsink. Dimensions and pin can·
lem that has been limiting the performance of figurations are shown on the attached specifi· C_ Thermal
ultra high resolution CRT monitors: video ampli- cation sheets. The circuit uses special silicon Thermal analysis of an amplifier design is a very
fier speed. Many of the 1024 x 1024 and transistors mounted on heat spreaders on an essential issue to ensure amplifier reliability. Heat
1280 x 1024 pixel. 64 kHz horizontal sweep rate alumina substrate with thin· film resistors and is one of the most critical factors that deter·
CRTs that are used in CAD/CAM and high resolu- gold metalization The substrate is soldered to mines how long the amplifier operates.
tion graphics applications have not realized their the heatsink.
potential performance because of the speed of The ability to examine the CRT circuit thermally
their video amplifiers. Video amplifiers with The heatsink is supplied in two versions, CA Low under operating conditions is absolutely
3.5-4 ns rise and fall times ohen found in these Profile which is designated CR2424, and a taller necessary. The infrared microscanner was used
high resolution CRTs do not provide optimum heatsmk version, CR2425. These two package for evaluation of the CRT hybrid amplifier from
picture quality when the CRT has approximately styles are shown in Figure 1. The electrical the standpoint of thermal resistance and
10 ns to energize each pixel. A slow video amp characteristics of these two amplifiers are iden· operating temperature.
will produce dimmer vertical lines than horizon- tical. The heatsink style choice should be based
tal lines or may force monitor designers to other on ease of mechanical Ielectrical interface. In both With the heatsink temperature stabilized at
compromises such as a slower sweep rate which cases, the heatsink is at ground potential and 60°C, the maximum transistor junction
may produce flicker, or lower cathode voltage should be attached directly to the chassis or ex· temperature was measured at 108°C. This is a
which will produce a dimmer picture. The hybrid ternal heatsink for mechanical stability and heat very safe value, especially for devices with all
described here solves these problems. conduction to ambient. gold metalization as used here. The maximum
temperature occurs when the output voltage is
SUMMARY This CR2424 hybrid driver can also be supplied either at its lower or upper extreme. Under this
The Video Amplifiers, CR2424 and in a hermetically sealed package. The hermetic condition the maximum power dissipation on the
CR2425, are hybrid integrated circuits designed version is designated CR2424H and can be die will be approximately 1.6W. Thus, the
for high resolution CRT Video Amplifier applica· screened to Mil Std 883 method 5008. thermal resistance can be calculated to be
tions. They are capable of delivering 40 volts 30°C/W.
peak·to·peak output with overshoot typically less B_ Electrical
than 5% into an 8.5pf load. Typical 10·90% The Circuit uses bipolar silicon transistors in a Under normal operating conditions (normal
transition times are 2.6 nsec with a bandwidth two·stage feed·back amplifier configuration. The operating conditions means an average picture
of better than 130MHz. They have excellent output is supplied by emitter· followers. Because contentl the hottest transistor will dissipate ap
gray·scale linearity, are dc coupled and do not reo of the complementary circuitry employed, there is proximately 1W. Again, with the heatsink
quire an external load·resistor. no need for a load (or pull·upl resistor. temperature stabilized at 60°C, the transistor
Junction temperature will be 60 ° C + 30 ° C/W x
1W ~ 90°C. This is a very safe value for this
CA low Profile kind of amplifier for a long life time.

INPUT OUTPUT

+Vcc
CR2424
(CASE 714G-01, STYLE 11

Figure 2. Pin Configuration PIN CR2424

Figure 1. Package Types

189
APPLICATIONS to the output voltage. The ratio between these biased at about 30mA. The collector lead must
voltages is approximately 230. From the above be by-passed for RF as close to the transistor as
A. Output Characteristics values. one may calculate a low· frequency input possible. For all common·collector (or common·
The hybrid is intended to be used as the final impedance of '" 15 ohms at Pin 1. basel circuits. a base resistor of "'20 ohms is
stage of very fast video circuits. Properly driven. recommended. It helps suppress spurious oscilla·
it can produce continuously alternating 10 nsec Pin 1 is an internal dc feedback node and thus. tions. which may occur in the GHz range and are
pixels with 40 volts swing and excellent bright· as we can see. has a low impedance looking in difficult to detect. Resistors Rl. R2 and R3. and
ness. The nominal load·capacitance is 8.5pf. from the outside. Pin 1 must be fed from a capacitor C1 and coil Lt are adjustable for
Other values may be accommodated. since the series network made up of a resistor with a desired circuit gain and response. Typical values
output voltage is supplied by a pair of emitter shunt capacitor for high frequency pre·emphasis. may be:
followers. and is fairly insensitive to changes in An appropriate input network is shown in Figure
load capacitance. 7 and is included as part of the standard test Rl:::: 50Q
fixturing. R2 :::: 215Q
Often a wire connection of some length between Cl:::: 90pF
the output of the module and the CRT cathode With the input terminal open. a dc level of R3:::: 50Q
cannot be avoided. In this case a resonant circuit approximately 1.4 volt exists at this point. Under Lt:::: 50nH
is formed. which may cause objectionable ringing this condition the module output voltage is
or overshoot at its resonant frequency. To avoid approximately one·half of the supply voltage The pulse generator used should allow changing
this condition a damping resistor must be used in applied. the dc level in order to set a quiescent bias point
series with the lead inductance. For critical of about l.4V at the input of the module.
damping the value of this resistor becomes GENERAL CONSIDERATIONS
C. Frequency Response
R· 2' if (11 A. Test Circuit
The test circuit used to evaluate the hybrid
In the literature and in many equipment specifica·
tions frequency response and rise· times are often
A resistor is often desired at this position also module is shown in Figure 7. treated as having a fixed relationship. The equa·
for protection against arcing. In practice. the op· tion frequently quoted is
timum value of resistance may be determined ex· The input is driven from a fast pulse generator.
perimentally during the bread·boarding stage. such as the Tektronix model PG502. It is impor- t,[10-90%1 •. 35 f3dB 121
Typical values are 50 to 100 ohms. The lead· tant that the internal generator impedance is 50
inductance may be artificially increased by a few ohms. It is also advisable to keep the cable It can be shown that 121 indeed applies for the
tenths of a microhenry to obtain a desired peak· length between the generator and the test circuit simple case of a single-pole R-C network. In reali-
ing effect. Any change in inductance will require at a minimum; preferably only a barrel connector ty. video amplifiers have much more complicated
readjustment of the damping resistance. as is used. transfer functions. and the above equation holds
stated by Equation 111. true only in a very general way.
Since the module is dc coupled. the input drive
A short piece of cable 175 or 93 ohm I or 300 voltage must be adjusted such that the driving In addition to the proper gain response. another'
ohm twin·lead. terminated by a capacitance. will wave form is centered around 1.4 volts. If the amplifier characteristic is of great importance.
act similar to an inductance in the frequency pulse generator used should not allow the setting Since a symmetrical square wave consists of a
range involved. In this case a damping resistor of the dc level. a biasing current. injected at fundamental frequency and odd harmonics
must also be used. module terminal 1. through a resistor of more thereof. the preservation of the phase·relationship
than 1 kiloohm. may be applied in order to ad· between all frequency components. while passing
The output terminal of the hybrid is not short· just the desired quiescent point of the output through the amplifier. must be guaranteed. This
circuit proof. Any resistance from this point to voltage. requirement is tantamount to specifying a "linear·
either ground or B+ should not be less than 600 phase" response or. in other terms. a uniform
ohms. The output is taken from terminal 9 with an ac· delay. Amplifiers having constant group delay ex·
tive FET oscilloscope probe fitted with a 100:1 hibit smooth. monotonically decreasing frequency·
B. Input and Transfer Characteristics voltage divider. This probe adds 1.5pf to the response curves. One must be wary of responses
The dc transfer characteristics of the module are load capacitance. bringing the total load which show ripple or peaking at high frequencies.
shown in Figures 3. 4 and 5. capacitance to 8.5 pI. Although sometimes impressive in terms of band·
width. such amplifiers often have poor transient
It is seen from Figure 3 that. at dc. an input The input circuit contains a series resistor and response. Shown in Figure 6 is the sine-wave
current swing of ± 6.25mA causes the output capacitor in parallel. which is tuned for good frequency response of the CR2424 in its
voltage to change by ± 20 volts. The next plot response when driving with a 50 ohm pulse· test fixture with the input variables previously
(see Figure 41 relates the input voltage. as generator. These components perform a RC adjusted for best rise and fall times. The output
measured at RF input port to the output voltage. "peaking" circuit. voltage is 20V peak·to·peak. The sine·wave sig·
The amplifier is phase·inverting. The ratio be· nal generator has a 50 ohm internal impedance.
tween these voltages is approximately 13.5. B. Practical Circuits The - 3dB point occurs at about 200MHz. For
From the above values. one may calculate a low The module is best driven from a low-impedance 40V output swings the - 3dB bandwidth is
frequency input impedance of '" 240 ohms at source. such as an emitter follower. The reader typically 145MHz. Actual, photographs of
the RF input port. is invited to experiment with a circuit as shown CR2424 output waveforms driving a 8.5 pf load
in Figure 8. are shown in Figure 9,
Figure 5 is a plot that relates the input voltage.
as measured immediately at module terminal 1. The driver transistor can be an LT2001.

190
 14 1.7
CRT Hybrid Amplifier CR2424
12
1.65
10 l
\ 1.6

"'- 1.55
~

"-
U
c:i
.= 2
0
" ~
~
.5
!!. 1.5
U
c:i
~ 1.4
1.45
...............
...............
-2
....... 1--.
..............
~ 1.35
-4
-6
............ 1.3
............... ....
-8 'r--.. 1.25 "\ I
-10
o 20
Vou, D.C.
Figure 3. Output Voltage versus Input Current
40
" 60
1.2
20 Vou, D.C.
Figure 5. Voltage Ratio at Port 1
40 60

0.0 0
-r-. r- -I-......
Hy~rid AmPlifi.) CR2424
Vou, 20 Vp·p
CRT -0.50
1 r... .... 1--.
\ .........
iii
~
-1.0 0

-1.50
...... ,
~ t -2.00
1\
~
1\
~ -2.50
1
............ -3.00 !\.
~ -3.50 \
.........
\
1
20
Vou, D.C.
Figure 4. Voltage Ratio at RF Input Port
40
'" 60
-4.00
o 20 40 60 80 100 120 140
Frequency IMHz}

Figure 6. Frequency Response of CR2424

160 180 200

C2
C2 - 0.o1~1 Chip Cap

50Q OUTPUT

RF INPUT R, CL - 7.0 pI •
R, - 0 - 500Q r1.5 pI Probe Cap.
R, Typical - 215Q
C, - 10-150pl
C, TVPical = 90pl
Vee - 60V Nominal
Figure 7. Test Circuit Figure 8. Experimental Circuit

191
192
 AN1022
Mechanical and Thermal Considerations
in Using RF Linear Hybrid Amplifiers
Prepared by
Don Feeney
Motorola RF Devices
One additional note of caution. DO NOT attempt to lap or
file the heatsink of the hybrid amplifier. Not only does this
ABSTRACT
void the warranty (considered "mishandling" by the manu-
Motorola's thin film hybrid amplifiers are medium power facturer), but you can induce substrate cracking during the
(0.2 W to 2.0 W power output) broadband devices (1 to machining operation. If you need a shorter heatsink, consider
1000 MHz) that are biased in a class A mode for linear oper- the hermetic package option or the low profile package avail-
ation. To insure a proper electrical/mechanical interface with able on some models. Motorola RF linear hybrid amplifiers
adequate RF/thermal characteristics, certain guidelines are are shipped with a mounting surface flatness of :': .002". To
presented for the design engineer to obtain maximum elec- improve heatsinking, thermal grease can be used.
trical performance and the longest operating life.

THERMAL CONSIDERATIONS PRINTED CIRCUIT BOARD INTERFACE

A question that often arises from engineers using our hybrid All Motorola RF linear hybrid amplifiers are internally
amplifiers is "What is the thermal impedance?" Thermal matched to a nominal characteristic impedance of 50 or 75
impedance (expressed as 0JC) is a very real and important ohms, both at the input and the output. This not only reduces
parameter for the RF design engineer using discrete solid the external components normally required to match to these
state devices. However, this term loses its meaning in a multi- impedances in discrete designs, but it also simplifies the
stage hybrid amplifier. Each stage may be biased at different requirements for interfacing printed circuit board connections
quiescent conditions resulting in different junction tempera- - for short path lengths, strip line width has little effect on
tures under a given set of environmental conditions. Addi- RF performance.
tionally, hybrid circuit design engineers may speak of BJC Motorola RF linear hybrid amplifiers feature .020" diameter
referring to the thermal impedance of a single transistor die gold plated pins' spaced at .100" centers. Nominal pin length
mounted on a hybrid circuit using their particular assembly is .460" (.375" for hermetic package).2 There is provision for
processes. However, this term has no meaning to the cus- a total of nine pins, but unused pins will be missing (refer to
tomer using their product who can only compute the power pin configuration diagram for the particular hybrid amplifier).
consumption of the total amplifier. Viewing the hybrid from the top, pin 1 is identified on the left.
To avoid this confusion, Motorola RF Devices simply rates This is the RF input, usually transformer coupled. 3 The two
the maximum operating case temperature for their RF linear adjacent pins are ground connections. The middle three pins
hybrid amplifiers. These amplifiers are designed so that under are reserved for power supply connections. Positive polarity
the worst case operating conditions, the maximum junction units have the power supply in pin located in the middle'
temperature of any of the transistor die will be below 150°C. Units designed to operate from a negative supply have the
This junction temperature correlates with our two years of power supply connection offset one pin to the left to guard
accumulated reliability data which predicts an MTBF in against inadvertent installation in an improper test fixture. The
excess of 142 years. extreme right hand pin is the RF output, and the two adjacent
pins are ground connections. All ground connections are
HEATSINK YOUR HYBRID internally connected to the flange, except as noted on the
Like all RF power devices, hybrid amplifiers require heat- functional schematic (refer to particular data sheets).
sinking for proper operation. How much heatsinking is nec-
essary? As much as is required to maintain the case oper- EXTERNAL COMPONENTS
ating temperature at the maximum value under worst case Although it is not specified as a requirement on the data
ambient temperature and maximum supply voltage. The pres- sheets, it is usually good RF practice to add a low impedance
ence or absence of the RF signal is insignificant due to the RF bypass capacitor (e.g., 0.1 /LF chip capacitor) located
class A bias conditions. Reducing the supply voltage will near the power supply pin. Additional decoupling is normally
decrease the power consumption, but it will also decrease not required. However, some Motorola RF linear hybrids
the linearity. Attach the hybrid amplifier directly to the chassis, require external chokes and capacitors for proper operation. 5
to a module card sidewall, to a small baseplate, or to a mount- Chip capacitors are recommended. A broadband 30 /LH RF
ing bracket that is connected to one of the above. But before choke may be constructed by winding 30 turns of #36AWG
you complete your design, verify that the maximum case magnet wire on a Ferroxcube 891 T050/4C4 core (alternate
(flange) temperature for the hybrid amplifier is within the man- core is Indiana General PIN CF 12001). With an accompa-
ufacturer's specified limits under your worst case operating nying order of hybrid amplifiers, this choke may be procured
conditions. through Motorola.

193
 For Motorola hybrid amplifier model CA2820. the external provisions for adapting this same test fixture for the low profile
chokes isolate the transistor from the power supply. Posi- package. the bent pin option. and the hermetic package
tioning of these chokes will have an effect on the high fre- option are presented in Figures 8.9. and 10.
quency end of the amplitude response.
1 Pin diameter for hermetic package is .018".
TEST FIXTURES 2 These pins will mate with sockets manufactured by
Figures 1 through 10 detail the assembly of standard test Amphenol (PIN 502-20071-572) and Barnes (PIN 027-018-
fix1ures for Motorola's line of RF linear hybrid amplifiers. Much 02).
3 Except for CA2820. which has an internal DC blocking
of this mechanical information will prove useful to the engi-
neer who is designing one of these units into his equipment. capacitor at the input.
4 Except for CA2820 and CA2870. Refer to individual data
The details of the test fixture assembly for the CA2820 pre-
sented in Figure 7 apply to most of the standard RF linear sheets.
5 e.g. CA2820. CA2870
hybrid amplifiers (just substitute PC boards. adjust pin spac-
ing. and remove external components as required). Special

1.000- ..J.....
.791 I 033 DIA. ,.
4 PLACES
STRIPLINE
WIDTH .055

.116 DIA.
4 PLACES

r---------"''''''..-----,- 1.000

~
.033 DIA .. I

_ + _ _ _ _ _ _ y~ACES(l:) 791
" .l~ _ _ _ 1. .640
-r--t---t___ STRIPLINE
I-I'<-r-+--"""'; .400 WIDTH .120
116 DIA .. 4 PLACES
202.135
.015
L--.,.,+--'-.Lf-U+-+llj-I-4JJ..i-"t--t"-t'.r>"<:-'--+"'-~6 .000
~
M;o
~ ~~~~~~~~~:!~~
.,...:.,...:.,...:.,...: . . '~SN
~
"' ...
0 0

NOTES:
1. All dimenSions In Inches. tolerance:!: .005.
2. Material IS double sided glass epoxy (Gl0).
1116" thickness. 1 oz. cooper, solder plated
3. TF.()6 used forCA2820 only. All other models use
TF·03

Figure 1. PC Board Construction for Hybrid Amplifier Test Fixtures

194
 DRILL '13 TAP THRU
1.500 6-32-UNC 2 PLACES ' "

~~-----$-----$­
I I '" .250

'''-T31~2--"-+----I\l-~-- ---ct>-- I
.313 ____ $ _____ $_ .250

.656 .072
-'-----L--+-__ - --(9- - -
I -ER,-
I R. TVP.
1.500
i .250 DIA.
C' BORE
,

!~
NOTES:
DRILL AND TAP 4 40, 4 PLACES
------,, ..
1 All dimenSions In Inches, tolerance,,: 005
2 Malenalls 318 aluminum ! ; .150
1"".350-1 ,~.115 .157---1 r--515--1
Figure 2. Heatsink Base Plate Construction for Hybrid NOTES:
, All dimenSions In Inches, tolerances:!: .005
Amplifier Test Fixture
2 Material IS aluminum r-.r"'--.+,,~

.156" DIA.
TWO HOLES' Figure 3. Adapter for Hermetic Package to Standard

EI ~ ------1.500-----
Hybrid Amplifier Test Fixtures

I
1---------1.75-------

Figure 4, Adapter for Low Profile Package to Standard

Hybrid Amplifier Test Fixtures ---..; i-- MILL SLOT
, .065"
.10 (BELOW PIN)
300 ..L
I i;=r ~

t
III ----1.500----~-+t~6
:1--
1
.156" DIA.
TWO HOLES-

1.75---------<
-T
i I -

IIII I! I AMPHENOL PIN US-625/U (50Q)

TROPOMETER PIN UBJ·20(75Q)

Figure S. Spacer for Bent Pin Package Option to

Standard Hybrid Amplifier Test Fixtures Figure 6. Modifications to BNC Connector

195
 EIGHT PIN SOCKETS
AMPHENOl PIN 502·20071-512
BARNES PIN 027·018·02
SPACER (FIGURE 4)
PIN SOCKETS SPACED AS REOUIRED
AMPHENOl. PIN 502·20071·512
BARNES PtN 027'()18{)2

PRINTED CIRCUIT BOARD

(FIGURE 1)

o
PAINTED CIRCUIT BOMD

1 ~ ~ ~ ~ ~ ~ ~ ~;~f8D ~O~D~::~N ~KETS

(FtGURE I)
FOUR SCREWS .. 40 THREAD 518 LENGTH

dtJ TO PC BOARD SO THAT

SLOTTED SNe CONNECTORS (FIGURE 61
FOUR SCREWS, 4·40 THREAD.
Sl8" LENGTH
SOLOfR PIN SOCKETS TO PC IJ()ARD
so THAT h = 180" t 005
FOUR SPACERS. 00 = 250 10 '" 116
TWO SLOTTED BN(; CONNECTORS
LENGTH = 250
(FIGURE 6)
~__'u'_ _ _ _ _ _ _ _-,I-,-[_~_-, ALUMI~y~U:S~ PLATE
RF CHOKES TRW PIN 11 F 11294 FOUII SPACERS. 00 • 250. 10 _ 116
II II LENGTH ,. 250"

TWO 0 luF CHIP CAPACITOAS

usee PIN WOSOFH104AZ (or equlvalen1)

,---------------, ~~O~~~;~:~~'i~R8Qu'Va,en'l o
MOUNTING HOLES FOR HYBRID AMPLIFIER
o MOUNTING HOLES FOR HYBRID AMF'lIFIE.R
SECURE WITH 1/0" 6·32 SCREWS
I 0 0 SECURE WITH 6·32 ". SCREW

~~~
NOTE: POSITION RF CHOKES AS
REQUIRED FOR BEST HIGH
FREQUENCY RESPONSE

Figure 8. Text Fixture Assembly for Hybrid Amplifiers

Figure 7. CA2820 Test Fixture Assembly (Case 714F-01) in Low Profile Package (Case 714G-01)

TWO SCREWS 6 j2 THREAD

", LENGTH
SPACER (FIGURE 5\

PIN SOCKETS SPACED AS REOIJIRE.D ADAPTER (FIGURE 3)

4,,",P,...E. .... 0~ P.." =: ~
PIN SOCKETS AS REOUIRED
BARNES PIN 027'0'602
AMPHENOL PIN 502·20071·572
BARNES PIN 027·016·02

~
PRINTEC CIRCuiT BOARD PRINTED CIRCUIT BOARD
IFIGURE' (FIGURE 1)

FOUR SCREWS ... •..0 THREAD.

T
[]3
T 000 0 000 W
FOUR SCREWS 4 4C THREAD
", LENGTH

TWO SLOnED eNC CONNECTORS

518 LENGTH
SOLDER PIN SOCKETS TO PC BOARO
SO THAT h.. 180":t: 005
TWO SLOTTED BNG CONNECTORS
(fiGURE 6)
IFIGURE 61 FOUR SPACERS. 00 ~ 250" 10 "" 116
[] [] FOUR SPACERS 00 = 250 ii II LENGTH ,. 250"
ALUMINUM BASE PLATE (fiGURE 2)
10 '" "6 LENGTH:::: 335
!i Ii ALUMINUM BASE PLATE (FIGURE 21

SECURE ADAPTER WITH TWO HEX

SCREWS. 6-32 THREAD. 5/8" LENGTH
MOUNTING HOLES FOR HYBRID
AMPLIFIER
SOLDER PIN SOCKETS TO PC
SECURE WITH 6·32 THREAD.
BOARO SO THAT d:::: '65 :t 005
'A" L.ENGTH

(JD

Figure 9. Text Fixture Assembly for Hybrid Amplifiers Figure 10. Test Fixture Assembly for Hybrid Amplifiers
with Bent Pin Option (Case 714J-01) in Hermetic Package (Case 826-01)

196
 AN1025
Reliability Considerations in Design and Use
of RF Integrated Circuits
Prepared by
James Humphrey and George Luettgenau

ABSTRACT DEFINITIONS
Reliability is a major factor in the profitability of CATV R = Reliability
Systems. Reliability is related to the probability that an item will
In spite of its proportionally low cost, the RF integrated perform a defined task satisfactorily for a specified
circuit figures prominently in the overall reliability pic- length of time, when used for the purpose intended, and
ture. This complex and important function is located at under conditions for which it was designed to operate.
strategic points in the system. Failure
Fortunately, modern design and manufacturing tech- Failure is a detected cessation of ability to perform a
nology, which draws extensively from resources gener- specified function within previously established limits in
ated by military and space activities, assures a degree of the area of interest.
reliability which is compatible with the most stringent (a) Dead on arrival
requirements. (b) Infant mortalities
. Transistor chips are the most vital elements of the RF (c) lifetime failure rates (random)
integrated circuit. Low noise and distortion require (d) End of life (wearout)
state-of-the-art transistor structures. Gold metallization,
thermal equilibrium by means of diffused balancing MTBF (Mean Time Between Failures)
resistors, as well as automated process control have
resulted in transistor lifetimes of over 100 years. The total measured operating time of a population of
equipment, divided by the total number of failures within
One of the inherent reliability advantages of IC's is the the population during the measured period of time.
reduced number of interconnects. The full benefit of this
characteristic is achieved through the use of gold con-
duction paths in conjunction with gold wire bonding. Average Llle
Perhaps the single most dangerous enemy of high re- The mean value for a normal distribution of lives, and
liability is excessive heat. Careful, computer-aided circuit generally, it applies to failures resulting from wearout.
design coupled with thermally sound, stress-free
mechanical construction guarantee structural integrity
and safe operating temperatures under all practical
conditions. Infrared scanning helps verify the achieve- BASIC RELIABILITY EQUATION
ment of design goals.
R = e-tlm = e-At
Abuse or abnormal stresses may counteract the best of
reliability. In order to avoid problems, the user must Where: R = Reliability or probability of success
control the electrical, thermal, and mechanical environ- , = Mission time in hours
ment surrounding the RF IC. Much progress in this . hours
respect has been made by the equipment industry. MTBF In hours = failures
1
A = Failure rate = MTBF failures
INTRODUCTION hours
Reliability considerations are becoming increasingly
important in the operation of CATV Systems, requiring an
absorption of military and aerospace reliability tech-
SYSTEM RELIABILITY
nology into the CATV business. Market surveys show a
large number of MSO's and consultants consider re- 1. When components are in series, failure of anyone of
liability as a major item in equipment selection. the components will result in failure of the system.

A definition of major reliability terms is important along

with an introduction to microcircuit reliability tools (both
hardware and software).
An overview discussion of PhYSics of Construction
involved with the die and interconnects must be pre- Then: RsYSlfM R, xR, xRJ x---R,
sented. An-STf.M A, +A, +AJ +---A .•

197
2. When the same components are in parallel (redun- RELIABILITY CURVE
dancy) neglecting, for simplicity, the decision-making
The following curve represents the typical condition of
device, the switchover function and the fail safe
operational reliability.
requirements:

RsYSTEM R, +R,-(R,R,)

Infant Mortality Plus

T;:'·"·· ~",om"'"_'"" .:
Wearout Plus
Random Failures

A= I I
Failure
Rate
I I I
I :/ Specified Failure Rate I I
~ _____ .J',__ -_-J I
I " I
--l I ,...-----~Iw e a r : t - - : \ - -
Period ~

-~E-a-rly-"·*I
Failure -~
........' - - - - - - - - - - - - - - -........
Optimum Shipping Point
-tl-..-.------ Point of
Average Life

RELIABILITY PREDICTION ALGORITHM BASE FAILURE RATE MODEL A,

The military has put considerable money and time into A, As + A,A., + lA'TN'T (Substrate contribution)
the study of reliability. One very useful military document + lAocNoc (Attached components contributions)
is Military Handbook 217B, Reliability Prediction of + APFnp, (Package contributions)
Electronic Equipment. This handbook shows how to
develop failure rate predictions by the use of mathe- Where: Base failure rate in failures/ 10' hr.
matical models based on years of data collection by Failure rate due to the substrate
military agencies. A discussion of the interaction of and film processing
components in the model is very useful in gaining an Failure rate contributions due to
understanding of the overall subject. network complexity and substrate
area which includes:
PART FAILURE RATE MODEL Ap (a) Number of lead terminations
Ap = Ab (nT X Ttl: X TtQ X rtF X TtM)
(b) Number of film resistors
(c) Number of discrete chip
Where: A, Part failures in failures per 10' hrs. devices
A, Base failure rate (d) Type of film (thin versus thick)
nT Temperature adjustment factor
n,. Environmental adjustment factor The sum of the failure rates for
TlQ Adjustment factor based on quality each resistor as a function of the
n, Adjustment factor for circuit function required resistance tolerance
0.8 for digital hybrids The sum of the attached device
1.0 for linear hybrids failure rates for semiconductors
1.1 for combination hybrids and capacitors
nM Adjustment factor for maturity of product The hybrid package failure adjusted
to include material and style

198
 PHYSICS OF CONSTRUCTION Diffused Ballasting System
Following the enumeration and identification of symbols (Only one emitter contact shown)
used in reliability algorithms, a discussion of the major
microelectronic components with respect to their re-
liability contributions is in order:

TRANSISTORS
The transistor die is the heart of the hybrid amplifier. With
four to eight devices per circuit, the transistor determines
performance and is most critical to proper circuit op"r-
ation.

During the last few years users have witnessed major

advances in the performance of linear broadband tran-
sistors. Often, efforts to improve one characteristic have
adverse effects on other desirable features. For instance,
distortion may be bettered by thinning the epitaxial
collector region. This, however, leads to sensitivity to
voltage transients and other abnormal operating con-
ditions. Therefore, devices with outstanding performance
in one area are prone to weakness in others. Computer- Metal Film Ballast Resistor
aided device design coupled with' volume production and
tight process controls have resulted in transistors in
which all essential features are in proper balance.

High fT is generally recognized as an important factor in

achieving wide bandwidth and uniform distortion char-
acteristics. Gigahertz transistors, which are now being
used, have very delicate patterns, involving micron and
submicron tolerances. They also occupy sizable areas
on the silicon wafer, since watt-sized powers have to be
handled. It is only realistic to expect that all parts of the
overall transistor structure are not perfectly alike, but
rather resemble the parallel configuration of many,
slightly differing, small devices, as shown in the figure.

Ballast Resistors

METAL MIGRATION

Some time ago a serious failure mechanism, associated

with GHz transistors, was discovered. The metallization
stripes of such devices, as mentioned earlier, are only a
few microns wide. The metal thickness is, because of
It is also apparent that the entire transistor geometry fabrication limitations, of similar dimensions. Conse-
cannot be tightly thermally coupled within itself, therefore quently. the current denSity in these stripes is quite high.
giving rise to the possibility of small sub-areas of the often reading hundreds of thousands of amperes per cm'
transistor assuming different values of temperature than of cross·section. Under these circumstances. metal
others. This possible problem can be effectively com- migration may occur. With such large numbers of elec·
batted by adding emitter balancing resistors to the trons flowing in such crowded space. the probability of
device. Ideally each emitter-site or finger should have its collisions with thermally activated metal ions is great. The
own resistor. This goal is easily realized in interdigitated ions are propelled in the direction of electron current
structures. Film or diffused monolithic resistors may be flow causing, in the long run, the metal to move, forming
used. From a process and reliability point of view, dif- hillocks, whiskers and voids. The lifetime of a transistor
fused resistors are preferred because they avoid the is a function of three things: the current density, the
silicon-oxide barrier which has a very high thermal temperature, and the type and consistency of metal·
resistance. lization.

199
Not much leeway exists in reducing the current density Comparing hybrid versus discrete techniques, one can
(unless Ir is sacrificed). Changing from aluminum to gold show the following:
extends the life at least by an order of magnitude. At high 1. For each transistor used, a minimum of three
temperatures the difference is even more pronounced. interconnects corresponding to the solder joints at
At 1 50"C, the time to metal failure for gold metallization the PC board are eliminated.
microwave transistors is in excess of 1 0' hours = 114 2. For each capaCitor used, a minimum of two inter-
years. While this number is quite comforting, one is not
connects are eliminated.
at liberty to treat the subject of transistor chip heat- 3. For each film resistor used, a minimum of four
sinking too lightly. A proven method for removing heat interconnects are eliminated corresponding to the
while at the same time obtaining a solid mechanical connection to the resistor body and the connec-
mount, has been to employ a heatspreader between the tion to the PC board.
silicon chip and the IC substrate. Automatic mounting 4. Transformer interconnects will be the same for
stations are used to eutectic collet mount the chip to hybrid or discrete.
indexed leadframes. Tight control of pressure and scrub
sequence result in defect free attachment. Although one The increase in interconnects in building 33dB of gain
may employ other methods of heatsinking, e.g. beryllium in discrete form over the same circuit in hybrid form is:
oxide substrates lor part of the circuit, the added
mechanical complexity and the reduced freedom of Add due to transistors 24
optimal circuit layout presently outweight the minor Add due to chip capaCitors 12
advantages resulting from a reduction in transistor Add due to resistors 100
temperature. Add due to transformers 0
Less due to hybrid jumpers -4
Less due to active pins -5
127 Additional inter-
INTERCONNECTS connects per
33dB function
One of the most important parts of hybrid circuits is the
interconnect system. The ability to reduce the number, MIL Handbook 217B also discusses the reduction in
control the quality, and test them by screening complete reliability of printed circuit boards as a direct multiple of
functions, is one of the major advantages of hybrid the holes required. Eighty-one additional holes are in-
circuits over more conventional approaches. Constant volved in making one discrete amplifier.
improvement in the mechanical and metallurgical sys-
tems have drastically improved reliability. Having the interconnects made early in the manufactur-
ing sequence, before the subsequent series of tests and
An analysis of the schematic on the standard 33dB inspections, has beneficial influence on end equipment
Hybrid Amplifier will illustrate the point: reliability.

33dB Gain Block

F, F,

C, c.

Q,

- R, R"

'JJ
R_ R, R" R" R,.
R"
5 5
2 T T,

1 R, II
R,
':'

.:.
R. R"

C'T R"
':'

.:.
R" R"

G.T
II[:
':'
R.
R, R"
" ':'
R"
R" RB ':'

C, C,
R"

Fe

200
The complete functional system including interconnects Advantages of Gold Bonding
is tested, screened and a.c. sampled many times before Compatible with gold die and substrate
it even meets up with the PC board in the manufacturers Strength stable with time/temperature
subsystem. Malleable - not subject to cracking
Easier to control process
Interconnects
Die Disadvantages of Gold Bonding
Heatspreader
/ More expensive
Solder Jumper Bond Die Bond CapacItor More deformation at bond foot
\ Hard to form loops
Solder
/I
/

Pin Histogram of Gold Versus Aluminum

Bond Strengths

COMPONENT MOUNT
The transistor heatspreaders, chip capacitors and pin
connections are soldered to the metallization pattern on
the substrate surface. This process is completed in a Number
of
tightly controlled solder reflow furnace.
Pulis

Due to the fact that the units are processed in an inert

atmosphere and thoroughly cleaned and inspected early
in the production process, workmanship problems are
greatly reduced.

BONDS
Wire bonding was a major reliability issue for years.

Aluminum has been one of the most widely used bonding

systems in the hybrid industry for many years. The main Strength (Gram)
reason for this is that ultrasonic aluminum systems bond
at room temperature and, hence, do not interfere with
other hybrid assembly processes.
Gold thermal compression ball bonding has been a
reliable standard process in the semiconductor industry
for years. However, the requirement for 300"C bonding
temperatures have kept this technique out of most Strength Versus Time on Gold Versus
hybrids. The recent changeover to all gold hybrids Aluminum Wire
prompted the development of a compatible low temper-
ature gold wire bonding system which by far out-performs
aluminum. T = 150'C
Advantages of Aluminum Bonds
Low temperature process
Compatible with AI die metal
Low cost Strength
High speed
Easy to loop (stiff)
Disadvantages of Aluminum Bonds
Degrades with time/temperature
Kirkendall voiding
Intermetallic formation with gold Aluminum
Brittle and subject to cracks
Difficult to screen
Difficult to control Time

201
 RELIABILITY ADJUSTMENT FACTORS (c) Where there has been an extended interruption in
production or a change in line personnel (radical
Following is a discussion of the "n adjustment factors"
expansion).
in MIL Handbook 217B. These relate to the external
influences on hybrid circuit reliability.
The factor of 10 can be expected to apply until con-
ditions and controls have stabilized. This period can
TEMPERATURE ADJUSTMENT FACTOR n, extend for as much as 6 months of continuous pro-
Operating temperature is one of the most important duction.
factors in reliability. As can be seen by the curve shown,
great reliability improvements can be obtained by lower- This maturity factor is extremely important. The industry
ing the case temperature. has used over 400,000 CATV modules since the first
module was shipped in 1970. Since that lime we have
constantly improved and refined the IC. Optimum re-
Failure Rate Multiplier Due to Temperature liability is an evolutionary process depending on time,
volume, defect analysis and feedback to fine tune the
product and eliminate defects.

The question is where does CATV fit Into this table.

Mechanical and thermal casting designs are extremely
important in protecting the RF IC from the external
environment conditions. Still, Wide variations in system
placement introduce a swing factor for environmental
effects, which will cause n, for CATV to fall between 1.0
and 5.0.

The user must strive to keep the components as close to

laboratory zero as possible.
2 4 6 8 10 20 30
n, QUALITY ADJUSTMENT FACTOR nQ
This is the adjustment factor based on the quality grade
This curve shows that a hybrid circuit, operating at a of the product. This factor modifies the reliability levels
case temperature of 100"C; has four times the failure by the different quality levels specified in MIL STD 883,
rate as the same circuit run at 50"C. Test Methods and Procedures for Microelectronics.
These levels take into account different screening levels,
ENVIRONMENTAL ADJUSTMENT FACTOR n, qualification levels and quality conformance inspection
requirements for the specified class.
This adjustment factor is based on the service environ-
mental conditions that the part will be exposed to during no
operation. MIL STD 883 Class A 0.5
MIL STD 883 Class B 1.0
Vendor Equivalent Class B 5.0
n, , Environmental Factor Based on Environmental MIL STD 883 Class C 30.0
Service Conditions Commercial with Screening 50.0
Commercial (No Screening) 75.0
Environment Symbol n,
A study of the MIL STD 883 Quality Requirements allow
Ground, Benign GH 0.2 a very important discussion of cost versus reliability. As
Space Flight S,. 0.2 could be expected the test, manpower, eqUipment, time
and paperwork go up rapidly as the MIL STD Grade is
Ground Fixed G,. 1.0 increased. A relative plot of this relationship is shown
Airborne, Inhabited A 4.0 below:
Naval, Sheltered N, 4.0
Cost Versus Reliability
Ground, Mobile G" 4.0
Naval, Unsheltered N" 5.0
Airborne, Uninhabited A, 6.0
Missile, Launch M, 10.0

MATURITY ADJUSTMENT FACTOR n" Increasing

Costs
The failure rate predicted by this mechanical model can
be expected to increase by a factor of (n .. = 10) under
anyone of the following conditions:
(a) New device in initial production.
(b) Where major changes in design or processes have
occurred.

202
Many of the MIL Standard Military requirements seem CONCLUSIONS
unimportant in influencing CATV reliability. However, the
• Many reliability tools are available today both in equip-
cost versus reliability curve is real and the equipment
ments for evaluation of reliability and in analytical tools
supplier can make choices as to the type of reliability he
such as MIL Handbook 217B for predictions of
is willing to pay for. reliability.
EQUIPMENT • Hybrid circuits offer massive reliability leverage due to:
It takes a massive capital investment in order to meet the (a) Reduction of Interconnects
manufacturing requirements for the CATV industry. The (b) Ability to control quality by screening
volume, quality and performance standards required (c) Large volume of complex standard functions are
have caused us to constantly reinvest for the future. easier to control
Many of the invested dollars are for equipments for
which the return on investment is subjective. • Case temperature is very important for reliability

SCANNING ELECTRON MICROSCOPE • A monometallic system, i.e., gold die metallization and
This instrument allows very high magnification of surface gold wire bonding are optimum for reliability.
conditions not available with optical methods. Magni-
fications up to 100,000 times are possible with the SEM. • Reliability can be improved by adding quality cost to the
module process. This increased cost may easily be
DISPERSIVE X -RAY ANALYSIS returned due to the lower failure rate.

This capability, which is a feature of the SEM, allows us

to make a microprobe to determine the chemical· com-
position of a sample. This is accomplished by detection ACKNOWLEDGEMENTS
of secondary emission x-rays which possess char-
acteristic energies. The relative quantity and location of The authors wish to thank AI Bird, TRW Systems Group,
elements may then be displayed on the CRT. Redondo Beach, California, for his technical guidance.

VARIABLE FREQUENCY VIBRATION

This is a destructive test which is performed for the
REFERENCES
purpose of determining the effect on component parts
of vibration in the specified frequency range. 1. MIL Handbook 217B, Reliabifity Prediction of Elec-
tronic Equipment.
2. MIL Standard 883, Test Methods and Procedures for
X-RAY Microelectronics.
This is a very valuable tool for detecting voids in solder 3. MIL Handbook 175, Microelectronic Device Data
or eutectic bonds. Handbook.
4. M. Flahie, "Reliability and MTF - The Long and Short
INFRARED MICROSCOPY of It," Microwaves, July 1972.
The ability to examine a circuit thermally under oper- 5. R. Y. Scapple and F.Z. Keister, "A Simplified Ap-
ating conditions is absolutely necessary when designing proach to Hybrid Thermal Design," Solid State Tech-
a new product or testing a new process. The infrared nology, October 1973.
microscanner is used for evaluation of new products 6. J. R. Black, "Electromigration Failure Modes in Alumi-
from the standpoint of thermal resistance and operating num Metallization for Semiconductor Devices," Pro-
temperature. Resolution of 0.0005 inch can be achieved. ceedings of the IEEE, Volume 57, Number 9, Sep-
tember 1 969.
7. C.M. Ryerson, S.L. Webster, F.G. Albright, "RADC
Reliability Notebook Volume II," RADC-TR-67-108,
September 1967.
8. George G. Luettgenau, "Microwave Power Tran-
sistors," International Microwave Conference, Stock-
holm, 1972.

203
204
 AN1027
Reliability/Performance Aspects
of CATV Amplifier Design
Prepared by
Michael D. McCombs

ABSTRACT
The reliability advantages to be offered by the RF hybrid The ultimate test is to see how long a part operates in
amplifier as used in CATV applications are discussed. the field without failing. The best way to simulate this is
The active part of the hybrid amplifier is the transistor. by means of a life test. Life test data is Included as a
Metallization, ballasting and ruggedness are reliability means of demonstrating the results of a careful design.
related factors that must be considered by the device
engineer when designing a high performance CATV tran-
sistor. Vertical and horizontal geometry and device II. WHAT IS RELIABILITY
'distortion mechanisms are performance related factors One definition could be that reliability is something that
that must also be taken into account. The Interrelation can cost you money if you don't have it. The dictionary
between these factors is examined. Life test data is then defines reliability as "the quality describing that which is
presented to illustrate the advantages to be gained by dependable or honest." To build honest transistors and
careful device design. amplifiers is a noble concept but one which may be
difficult to measure. So in the everyday sense. reliability
is a somewhat abstract idea that is difficult to describe
I. INTRODUCTION quantitatively. In engineering, however. reliability has an
exact meaning. .
The cable television system operator buys eqUipment
which he knows has demonstrated a certain minimum "Reliability IS the probability of a device per-
level of performance, or In other words, equipment that forming its purpose adequately for the period of
meets his specifications. If he questions this perform- time intended under the operating conditions
ance he can run variOus electrical tests to check it encountered. '"

When an amplifier is designed for a certain level of gain,

Another question that we would like to be able to answer it may happen in practice that the gain is less than that
is, how long will his equipment operate before it fails. called out in the specification. In certain cases this may
costing him downtime and repair. This is the question of be acceptable if the amplifier turns out to be very reliable.
reliability and to understand this it is necessary to under- However, another amplifier, which supplies the full gain
stand the factors that go into designing tor reliability. with ease, may breakdown in operation because its
components are being taxed to their limits. This is where
The primary building block of a reliable CATV amplifier is reliability enters the picture. It is possible to achieve full
the RF integrated circuit. This concept possesses many performance and still have state-of-the-art reliability.'
advantages over the PC board discrete design including We said that reliability is the capability of equipment not
a reduced number of interconnects and the ability of the to break down in operation, The measure of an equip-
manufacturer to effectively test the system before ment's reliability, then, is the frequency at which failures
delivery to the equipment manufacturer. occur in time. A failure is a malfunction which causes the
Going one step further, the basic constituent of the component to violate the requirement for adequate
integrated circuit is the transistor itself. It is in the design performance, The frequency of such failures is called the
of this transistor that the ideals of high performance with failure rate, The reciprocal of the failure rate is called the
reliability can be effectively realized. mean time between failures or MTBF.

.l. Failure Rate

1 MTBF
.l.

205
Referring to Figure 1 , it is seen that there are three basic III. HYBRID CIRCUIT RELIABILITY
types of failures; early, chance and wearout failures.' ADVANTAGES
Early failures occur early in the life of a component and The hybrid circuit is the heart of the CATV amplifier. This
result usually from poor manufacturing. These can be assembly must perform its duty while experiencing a
eliminated by a 'burn-in' process.
variety of electrical and environmental extremes. If the
hybrid circuit should fail, then the cost to the system
Wearout failures are a symptom of component aging.
operator is high. For this reason the hybrid circuit should
These types of failures can be eliminated by either
be an extremely reliable piece of equipment.
replacing at regular intervals or by designing for longer
life than the intended life of the equipment if the com- There are certain qualities of a hybrid circuit which make
ponents are inaccessible.
it an inherently reliable assembly.
Chance failures occur at random intervals and are due to One subtle advantage relates to the wear out life of
sudden stress accumulations beyond the design components. Replacement of a hybrid circuit means
strength of the component. Since the other failure types replacing every amplifier component which resets the
are relalively easy to eliminate, performance reliability clock on the entire amplifier as far as mean life is con-
should be determined by the chance failures. cerned. Replacing a component in a discrete amplifier
does not. All of the other discrete components continue
For chance failures only, reliability may be expressed by to approach their wear out life.
the exponential relationship
The metallization system of the hybrid is another
R(I) = e-At advantage. The gold metallization which is used for inter-
connects on the hybrid circuit allows the deSigner to
where A is the failure rate and t is a given operating time; have the high conductivity of gold for use in tying to-
t must never exceed the 'useful life' of the device. The gether the various components of the circuit, while
derivation of this reliability expression is found in the having the additional reliability advantage of a mono-
Appendix. metallic gold system in wire bonding from the transistor
to the hybrid. Even though the hybrid circuit utilizes heat
System failures are caused by component failures. When sinking to reduce heat buildup, any bi-metallic interface
components can fail only because of chance. the system will be susceptible to failure due to intermetallic for-
will fail only because of chance. The design engineer is mation. These gold-aluminum intermetallics are more
responsible for the reliability which is characteristic of his brittle than the parent metals, and they also are sus-
equipment. If he desires to reduce the number of chance ceptible to void formation due to the faster diffusion of
failures which occur during the useful life period of his aluminum into gold compared with gold into aluminum
equipment. he must keep several key points in mindS (Kirkendall Effect). If a hybrid circuit is manufactured
using die with aluminum metallization, it is certainly pre-
ferable to use aluminum for bonding. This is because the
gold-aluminum interface will then occur on the substrate,
away from the heat of the transistor. This is important
Early Chance Wearout since the formation of intermetallics, Au AI, or Au, AI, ,
Failures Failures Failures is accelerated by temperature. However, these inter-
Burn-In Useful Life
faces, even though they occur on the substrate, are
Period Period nonetheless sensitive to weakening. Which intermetallic
compound is formed depends on the amount of gold
available in the bonding area. If the gold is thin then
Au,AI, will be formed. If the gold is thicker then Au,AI,
will be formed. The end result is the same; voiding and a
weak bond which eventually lifts. The entire process
can be accelerated by thermal cycling whereby cracks
TB Tw m are formed in the brittle intermetallics.' Data presented
m = mean wearout life Operating Life_ later illustrates the comparison between failure rates due
to bond lifts in aluminum and gold systems.
Figure 1. Component Failure Rate as a Function of Age
Another advantage which hybrids enjoy over discrete
designs is the reduction of the number of interconnects.
1. Design components to accept overstress; the
An interconnect is a potential failure point. Reduction of
normal operating point should be well below rated
the number of these pOints will result in a more reliable
values, including temperature.
system. A calculation of the additional interconnects
2. Provide good packaging with 'adequate heat required in a typical discrete amplifier over the hybrid
sinking. equivalent shows an increase of 127 interconnects in
3. Design with as few components and interconnects the discrete version.' Figure 2 summarizes hybrid life
as possible. test data.

206
 So it is apparent that the hybrid structure is inherently which is not so heavily doped so that the resistivity of
more reliable than a discrete assembly. But the heart of this layer is higher than that of the substrate. It is the
the amplifier, be it hybrid or discrete, is the transistor. configuration of this 'epitaxial layer' that is very important
to the performance of the device. It is this layer that will
Reliability Data at 95°C Case Temperature form the collector of the transistor. There are two
MTBFWlth parameters of the epi layer that can be specified by the
PI"
Description
Unit Hours
• 90%
Accumulated Fill Confidence
MTBF-Galn
Product
engineer. One is the thickness and the other is the
resistivity. The resistivity is chosen from operating
Transistor Chip 7,398,000 3 141 Years - voltage considerations. The transistor is intended for a
. r----- ~----
specific purpose and presumably the voltage at which it
CA2200 Hybrid 984,000 4 13 Years 221dB - Yrs
..- ------_.- will be operating is known. If the device will be biased at
CA2600 Hybrid 577,000 4 8 Years 264dB - Yrs 20 volts in an amplifier, then the collector breakdown
voltage of the transistor, BVcBo, should be higher than
Figure 2, Hybrid Circuit Life Test Data 20 volts to provide a safety cushion. The phenomenon
that occurs in a well·designed transistor at breakdown is
called avalanche. This occurs when a sufficiently high
IV. RF TRANSISTOR DESIGN reverse voltage is placed across a p-n junction. A field is
CONSIDERATIONS formed across this junction and carriers are accelerated
across the field. When the applied voltage equals the
The performance which can be obtained from the
amplifier is determined, in the end, by the transistor. Not avalanche voltage a multiplication effect occurs in which
only must the transistor provide performance, however, atomic bonds are broken and the junction breaks down.
This is the collector breakdown voltage and it is pro-
it must provide this performance for a reasonable length
of time. If the transistor fails, then the hybrid fails and portional inversely to the doping level of the collector or
cost to the system operator is the result. . epi layer. By specifying epi material, then, the designer
sets his voltage operating limit.
When the transistor engineer "begins to design a device
for use in CATV amplifiers, then, he is faced with two The other epi parameter of interest is the thickness of
main requirements. The device must offer a certain level the layer. It has been found that epi thickness is closely
of performance and it must do its job reliably. We will now tied in to both device reliability and performance. One
investigate the RF transistor and the considerations that parameter that is commonly. used to describe high-
go into its design. frequency transistors is fT. This is the gain-bandwidth
product of the device or the frequency at which the
. 1, Starting Material common·emitter, short circuit current gain, h", equals
unity. A high fT means to the circuit designer better wide
Modern transistors are built using what is called the band gain perfo"rmance. The fr frequency can be related
planar technology. This name arises from the fact that to the phYSical device in terms of the various delay times
all areas of the transistor are found on the planar surface throughout the transistor. If the delay that a carrier sees
of the Silicon wafer. Figure 3 illustrates a cross-section in traveling through a device is less than in another
Emitter device, then the It for the device with the least delay is
higher. The thickness of the epitaxial region is related
directly to one of these delay times; namely the rscCTc
time constant in the collector. The rsc is the collector
series resistance and to reduce this value for a given
resistivity, we must reduce the epi thickness. There is
another advantage to be gained from reducing the epi
thickness which relates to distortion performance. Figure
4 shows a comparison of intermodulation distortion
performance between two CATV transistors. The tran·
sistors are identical in all respects except that one

60,--------------------------------

70
Figure 3, Planar-Epitaxial Technology iii"
~ 80
of a typical transistor structure as built using the planar 0
~
technology. The first job of the designer is to decide
what starting material he wishes to use for his transistor. 90
The starting material consists of a wafer of silicon,
approximately 10 mils thick and typically 2 inches in
diameter. This silicon has been grown in crystal form 100
while introducing a large concentration of impurities. This 10 100 1000
substrate silicon, then, is very heavily 'doped' so that the lc(mA)
resistivity is very low. On the surface of this low re-
sistivity silicon wafer is then grown a layer of silicon Figure 4. IMO Distortion Performance as a Function
of EPI Thickness

207
device was built on epi material which was 50% thicker overlay and mesh configurations are used primarily for
than the other. It is seen that the device which was built modern power transistors. High frequency devices are
on thin epi material offers better distortion performance sensitive to parasitic capacitances and this favors the
at higher current levels. The reason for this performance interdigitated design.
gain with thin epi is the fact that the maximum current
density available in a device increases as the epi thick- Figure 5 is a representation of typical transistor con-
ness is decreased. This occurs because of debiasing of figurations. The base area is dictated by the power
the collector-base depletion region by the resistive epi
region. The thin epi device, then, acts like a larger device Base
at higher currents, resulting in better distortion per- Contact
formance at these higher levels.

Thin epitaxial material appears to yield very good tran-

sistors for CATV applications. Unfortunately there is a
negative side to the story. The fact is that as the epi
material is made thinner and thinner to achieve good Interdigitated
performance the transistor becomes more and more
sensitive to voltage variations. With thin epi the ballasting
effect of the collector resistor is lost and the transistor
loses ruggedness. The designer. then. wants to choose
an epitaxial material which is as thin as possible for
Base
performance yet which is thick enough to avoid complete
depletion and provide some collector ballasting. ~ I I ~ntact
2. Vertical Geometry [13-------------------GJ

[~~
Once the starting material is decided upon, then it must
be insured that a process is available which will yield a
Emitter
high performance vertical geometry. The importance of
Contact
high fT in the CATV transistor has been discussed.
Another time constant which can be reduced in order to
increase fT is the delay due to carrier movement through
the base region. The relationship for this delay is
G------------------1!]
tb
Wb'
2.43 Deb', (NB' INBC) I I I I
This relationship describes the time required for carrier
transit across the base region in terms of base width, Wb;
diffusion co-efficient, Deb; and doping gradient, NB' and
NBC. The point here is that this delay time varies directly
as the square of the base width. A desirable goal then is
to produce a transistor which has a narrow base width.
The well understood diffusion process can be used to
control this parameter to a point. However, as narrower
base widths are sought, device yields go down due to
non-uniformities which are inherent in the diffusion
process. State-of-the-art base widths with good uni-
formity are possible, though, by taking advantage of ion
implant technology for the formation of the device junco
tions. Another advantage of implantation is that it makes
possible steeper gradients in the emitter and base
regions resulting in higher fields and shorter transit times Figure 5. Typical Transistor Configurations
in those areas.
handling requirements of the transistor. There must be
3, Horizontal Geometry
enough area available to dissipate the heat which is
One' more item must be considered before the CATV generated. The amount of current to be handled by the
transistor is ready to be built. A mask set must be de- device will determine what the minimum emitter per-
signed, or, in other words, it must be determined what the iphery is. This is because at higher bias levels and
device will look like, physically. frequencies a large transverse voltage drop occurs in the
active base region under the emitter. This will have a
First, the basic device configuration must be decided de· biasing effect on the central portion of the emitter·
upon. There are three transistor contact geometries in base junction caUSing most of the current to pass at the
use; these are interdigitated, overlay, and mesh. The emitter edges. Since it is known how much current the

208
device will be required to handle, it is possible to calcu-
late the amount of emitter periphery necessary to safely
handle this current. The task now is to pack this amount
of emitter periphery into the smallest base area possible,
thereby reducing collector-base junction capacitance.
Two examples of possible interdigitated designs having
equal emitter peripheries are shown in Figure 6. It is seen

Ep = 24
SA = 88
Ep/BA = 27

Figure 6. Ep/BA Comparison for Square vs

Rectangular Base Configuration
that slightly higher Ep/BA ratios are possible with a
design which is square compared to one with a higher
aspect ratio. The problem with the square configuration
is that the long emitter fingers required will restJlt in
considerable voltage drop along their length. The result is
that part of the device is not being used and hot spots
will develop. Not only will device performance be re-
duced, but it will soon fail because of overheating. The
design with the higher aspect-ratio is desirable since the
voltage drop problem is eliminated. Another advantage of Figure 7. Ballast Resistor Configurations
this configuration is that it is inherently better able to
dissipate heat since the cells are not so closely coupled thermal barrier since they sit on top of the silicon dioxide
as in the square configuration. This design also has a barrier. Diffused resistors are more reliable since they
problem, however. Although the emitter fingers are now avoid the oxide barrier and are not susceptible to
short enough, the active area of the device is now quite . cracking.
long. The middle portion of the device will tend to draw It is also desirable to reduce the contact spacing and
more current which is not efficient. The solution to this the emitter contact widths of the transistor for two
problem is to add ballast resistors between the emitter important reasons.' A narrow contact spacing will allow
feeder arm and the emitter fingers. (See Figure 7.) The more emitter periphery to be placed within a given base
ballast resistors are thus in series with the emitter can· area. This is good since we have seen that gain per-
tact metallization. If an emitter·base junction site begins formance depends directly on the amount of periphery
pulling more than its share of current the series re- available for current handling. A narrow emitter stripe is
sistance will cause a proportionate drop in the input desirable since the resistance of the base region, rb',
voltage for that site, thus limiting the current and pre- varies directly as the emitter contact width and it is
venting failure. An important point is the type of ballast necessary to reduce the parasitic rb' as much as pas·
resistor used. Two types of resistor are popular, thin sible for gain purposes. Incidentally, reduction of rb' is
film or diffused. Thin film resistors are susceptible to good for noise figure too Figure 8 illustrates the impact
microcracking and they also are faced with a high of emitter width on base resistance.

209
 metallics and the wire bond failures that result. Figure 10
illustrates life test data that shows an increased failure
rate due to bond failures in the aluminum·gold system.

Life Test at 95°C Case Temperature

Unit Wlr.Bond Wlr.Bond
Part Description Hours Fallur. Failur. Rate
Accumulated No's %

601 B, 200 Hybrids

With Aluminum 1,162,000 24 4.1

1
30700ie
2200, 2600 Hybrids
With Gold 1,188,000 0 0
30400ie

Figure 8. Effect of Emitter Stripe Width Figure 10. Wire Bond Failure Rates in
on Base Resistance Aluminum/Gold Life Test

The last step in the construction of the transistor is the

deposition of metallization so that contact can be made Electromigration Resistance
to the emitter and base regions. (See Figure g.) The type
It was shown earlier that it was desirable to achieve a
high Ep/SA ratio so as to obtain maximum performance
from a device. This was achieved by placing the tran·
sistor contacts as close together as possible. The use of
such tight contact geometry forces the use of very
narrow metal fingers. The resulting high current densities
can lead to reliability problems as a result of electro·
migration. Electromigration is a phenomenon which
occurs in metal films as a function of time, temperature,
and current density. For any given temperature, a certain
equilibrium concentration of vacancies exists in all metal
films. Self diffusion of metal ions throughout the film
arise due to the metal ions being thermally activated into
adjacent vacancies. In the absence of any external
Figure 9. Transistor Metallization forces, the metal ion diffusion will be isotropic and will
result in no net accumulation or depletion of mass in any
given site. In the presence of an electric field, however,
the metal ions experience a force due to their charge,
of metal to be used is an important decision. The two
inducing an ionic flux toward the cathode end of the film.
metals that are low enough in conductivity that can be
In addition, the conduction flow of electrons in the metal
used for transistor metallization are gold and aluminum.
due to the electric field will cause electron scattering off
Aluminum metallization has been used for years as a
the activated ions and impart momentum to them in·
conductor for transistors. Its advantages are that it is a
ducing an ionic flux toward the anodic end of the film. In
well·understood process, it offers a good silicon contact
good conductors, the momentum exchange force domi·
without any barrier metallization, and it is inexpensive.
nates the electrostatic force and results in a net mass
However, considering the micron contact geometry of
transport toward the anodic end of the film. The resu~ is
the RF transistor and the fact that it will be mounted on a
an open circuit in the metallization strip. This void for·
gold hybrid circuit, then the decision is considerably
mation is accelerated by high temperatures and current
easier to make. For a CATV transistor, gold provides the
density.'
following advantages over aluminum.'
1. Monometallic wire bonding system. Aluminum has exhibited a high susceptibility to electro·
2. Electromigration resistance. migration for current densities above 1 0" A/cm~ Such a
3. Low contact resistance with elimination of shorts current density is easily realized in state·of·the·art RF
due to silicon'metal alloying. devices. For a given device geometry there are only two
4. Corrosion resistance. alternatives to allow reduction of the current density in a
device. Either the operating level can be reduced or a
5. Oxide step coverage. metal can be selected which has a higher mass and actio
Allows use of tighter contact geometries. vation energy. The operating level cannot be reduced
without a sacrifice in performance. We can still keep high
performance and reduce the current density by using
Monometallic Wire Bonding System gold metallization. At 200"C, experiments conducted on
As has been described, it is desirable to have an all·gold identical transistors with gold vs. aluminum metallization
metal system for reasons of reliability. A monometallic showed an improvement in mean life time of two orders
system eliminates the formation of gold·aluminum inter· of magnitude using gold.

210
 Contact Resistance Step Coverage
Gold cannot be used as a single layer metallization Gold offers tremendous improvements over aluminum in
because of its relatively low silicon eutectic temperature its ability to cover oxide steps without decrease in metal
and its poor adhesion to silicon and silicon dioxide A thickness or cracking. (See Figure 11.) Aluminum is
barrier layer must be employed to prevent gold diffusion deposited by means of evaporation in a vacuum where
into the silicon and this barrier metal must offer good the mean free path of the aluminum particle is long. This
adhesion to silicon, silicon dioxide, and gold. Such a means that equal coverage of all surfaces is impossible
barrier is offered by a system utilizing platinum silicide, even if the target is rotated during evaporation. The
titanium and tungsten. The platinum silicide forms a good plate-up gold system reduces step coverage problems
ohmic contact with the silicon; the Ti/W provides the to insignificance.
necessary diffusion barrier and offers good adhesion to
SiC), and silicon. Narrow Contact Geometries
The RF transistor must have very fine horizontal
Aluminum has historically offered good ohmic contact
geometry to achieve the performance required in a
without the need for barrier metals. In RF devices, how-
CATV system. With aluminum metallization these narrow
ever, at current densities well below electromigration
densities, a problem of formation of silicon/aluminum finger widths are achieved by etching the aluminum to
remove it. Such a process, if done very carefully, will at
alloy is ever present resulting in emitter-base shorts. Any
hot spot formation will result in an increased alloying nte best result in fingers of uneven width which are sus-
and early failure. ceptible to high current densities and the associated
reliability problems. The gold system is capable of pro-
viding microwave geometries with insignificant variations
in line widths. In fact, the geometry on present gold
Corrosion Resistance
CATV devices is narrower than some low-noise micro-
Under biased conditions, in a humid atmosphere, gold wave devices which are on the market today.
has demonstrated a lifetime more than 3 times that of
aluminum. The failure mode in aluminum is electro-
mechanical corrosion and gold is insensitive to this
phenomenon.
Plated
Gold

Silicon Silicon

Figure 11. Oxide Step Coverage

V. SUMMARY APPENDIX REFERENCES

1 The CATV system operator IS Interested In per- Denvatlon of reliability expresSion lor chance failures· , Mike Flahle Reliability and MTF - The Long and
formance with reliability in the amplifier eqUIpment he Short of It Microwaves. July 1972
R(O = e· At
uses 2 James Humphrey and George Luettgenau Reliability
2 The basic bUilding block of the CATV amplifier IS the If an anginal population of x·. Ilems IS conttnuously de· ConSlderatIQ1s In DeSign and Use of RF Integrated
hybrid CirCUit The hybrid amplifier offers reliability caYlng so Ihallhere are X Ilems al lime t the change of CirCUits"· IEEE NCTE Conference. February 1976
advantages over discrete designs Including gold POpulallon In one Interval dt IS dX dt DIVided by Ihe total
3 Elhotl Phllofsky ··Deslgn Limits When USing Gold·
Circuit metalhzatlon and a reduced number of Inter- population X at t. thiS gives the negative rate at which the
Aluminum Bonds Motorola Inc Semiconductor
connects populaltOn changes at time I
Products DIVISion
The heart of the hybrrd circuli IS the RF transistor .A=sQ<---.5!!=~ 1 4 R Flahle and M Weiss A Study of the Advantages
4 The design of a reliable transistor tor use In CATV X X dt of Gold Metallization In t~e Manufacture of Microwave
amplifiers requires a knowledge of basIC design then ·Adt = dX X TranSistors TRW Semiconductors Technical Note
values plus the availability of state-ol-the-art process- 5 Igor BazouSky Reliability Theory and Pracl!ce
ing Points to be considered Include Integratlng over the lime pertod being conSidered.
Prentice· Hall 1961
startmg matenal t 6 J R Black ··Electromlgratlon Failure Modes In Aluml·
vertical geometry -JAdt = InX C = InX fnC
num Metallization for Semiconductor DeVices
honzontal geometry o Proceedmgs of the IEEE Volume 57 Number 9
configuration for t = O. X = Xo September 1969
metallization
Then C = X
5 Life tests show the improvements In reliability to be
gained by carefullransistor design t
And X X. = e.t . JAdt

If the rale of decay. A IS constant then

X X. = e." ·AI
Since X X IS probability of surVival for a decaYing popu·
laltOn then
R (I) = X X, = e.~ ·A t

211
212
 AN1028
35/50 Watt Broadband (160-240 MHz)
Push-Pull TV Amplifier Band III
This note describes the performance of a broadband ultra linear push pull amplifier designed for service in band III TV
transposers and transmitters.
Devices used: two TPV 375.
Basic amplifier specifications
IMD (1) = - 51 dB at Po = 35 W Pgain = 10 dB
IMD(1)=-48dB at Po = 50 W input VSWR < 1.6
V ce = 28 volts; Total = 4.4"A output VSWR' < 1.5
(1) vision carrier - 8 dB. sound carrier - 7 dB. sideband signal - 16 dB.
General design Consideration
The principal aims were
- employ a relatively simple solution permitting us to obtain the optimal performances from TWO TPV 375.
- simplify the design and reduce the cost.
The main consideration was to obtain the maximum output power with the best IMD over the band. To obtain
this requirement the output match and losses must be the best possible in all the band.
The second consideration was to obtain the maximum gain by reducing the input matching circuit losses to a
minimum.

These factors led us to choose matching circuits using quarter-wavelength transformers at the input and output
which permit us to :
- reduce the load and source impedances to low values with low losses
- couple two transistors in a push pull configuration.
Because the output and input transistor impedances are in series. due to the push-pull configuration. the required'
transformation ratio is one half of that required for a single ended stage.
The first approach for the circuit calculation was made from the input and output impedances given in the
TPV375 data sheet and matched to the proper impedance levels using a Smith Chart. The element values were
then optimized with the aid of "COMPACT» program.
Amplifier Design
The basic block diagram for the amplifier is shown in Figure 1 and the circuit schematic is shown in Figure 2.
The input and output circuits are each composed of two networks: a quarter-wavelength transformer-balun
and a matching network.

The quarter-wavelength transformer impedances have been chosen to be easily built using microstrip technology.
Input circuit
The input circuit is shown in Figure 3 and the input impedances are shown in Smith Chart 1.
The low transistor input impedances are transformed into higher impedances near the real axis by Capacitors FF.
The (EE. DO) series elements and (CC. BB) parallel elements collapse the amplifier input impedances around
8.5 n.
Since the devices can be considered in series at this point the impedance is doubled to 17 n.
The quarter-
wavelength transformer balun (AA) completes the match to 50 n.
The transformation ratio is 2.8 : 1.
The maximum theoritical input VSWR is 1.80 : 1 and the maximum experimental VSWR is 1.60 : 1.
Output circuit
The output circuit is shown in Figure 4 and the output impedances on Smith Chart. II. Since the output impe-
dances are higher than the input impedances. the output matching network is simpler and the quarter-wavelength
transformer ratio is lower.
The inductors aid the matching but primarily provide for good stability at the low frequencies. and are used
for collector bias. The output quarter-wave-Iength transformer ratio is 1.6 : 1.
The maximum theoretical VSWR is 1.16:1 and the maximum experimental VSWR is 1.44:1.

213
Amplifier Performances
IMD versus output power: Figure 5
Input and output return loss and VSWR = Figure 6
Gain versus frequency: see Figure 7
1 dB gain point compression: 70 W
Bias conditions: V co = 28 V; Total = 4.4 A.

Technology and layout considerations

The epoxy-Glass 1/16 inch (~r = 4.1) is used as board material except for the input and ouput transformers.
The glass - Teflon 1/50 inch (~r = 2.55) is used for the transformers (see the details Figure 8).
We have considered for a microstrip line that after W (Width) from the conductor strip edge the fields are negli-
gible and we can size the ground conductor to be 3 W without perturbing the propagation. This kind of trans-
former has the following characteristics:
We can have any impedance values within realizable min-max limits.
- The vertical dimensions are small and the mechanical realibility is good.
- Good repeatibility.
The bias circuits are included with RF circuits in order to give a compact amplifier: Figures 10 and 11 show
the layouts and the Figure 12 the physical layout of the push-pull amplifier.

Combined pairs of push-pull Amplifiers

- In general several push-pull amplifiers are used for the final stage of the TV transmitter amplifiers.
They can be combined by pair with quadrature combiners (see block diagram Figure 9).
The advantage of using this kind of coupler is that the input and output VSWR become good (> 20 dB rtn.
loss) in comparison with the relatively high original VSWR of the push-pull amplifier.

General Conclusions
Push pull techniques simplify the required circuitry and associated losses.
The problems associated with 3 dB hybrids in cascade - insertion loss and imbalance - when four devices
in parallel are required are minimized.
With additional effort both the input and output VSWR could be improved to 1.2 : 1.
Good repeatability in production without variable components being required.

I 1

INPUT OUTPUT
50 OHMS. 50 OHMS.

l' r 1
Figure 1. Push-Pull Circuit

214
 Vee

VeE

SO '36

LI
50 ohm

"7pF
30 .... ~/4 al 240MHZ I· .x'4 at 240 MHZ 4OA.
H·
IN ,-, IOOpF

t 47pF
P: l'1.Ae
.,200MHZ

UK
VI(
" LI
CIRCUIT DIAGRAM

470
LI .. 8 turn •. 10 6 mm
I .. 8 mm. wire .6 mm
LJ .. 2.5 turns. 10 6 mm
I -10mm.wire'mm
3X» SW
330

Vee

Figure 2. Circuit Diagram

On the smith chart the impedances are represented by :

AA ss CC DO EE FF

Z, L· Z, L· Z, L·
(01 (mm) (oFI (01 (mm) (pFI (01 (mm) (pFI

I Calc. value 30 313 13. 100 ".3 47 50 80.8 238

I Empirical value 30 313 100 100 15.0 47 50 82.5 200

• L is given for t, "'" 1

Figure 3. Input Circuit

215
 IMPEDANCE COORD....ATES- 50-OHM CHARACTERISTIC IMPEDANCE

SMITH CHART I
o ••
I" ',' I,

IRt:I"~'t' - VOL ". NO. I, ",'lO -Ill, jl" SU, JAN ,'''''''
.'''11lA1. RADIO COMPANY
Wlif to.CO_D. _lU,
_10 . .
'OR""l·~

Figure 4A. Input Circuit

216
IMPEDANCE COORDINATES- SO-OHM CHARACTERISTIC IMPEOAHCE

SMITH CHART II
PARAMETERS

'..Ir·"2 ,"i "~' ',',' !, ',', 0, ~~-'r"""''''''''-"+'''''''''+'-++'H-+---;~;1'I§

a'~"""'~"'t---'-
I I
1,'" 3'1 a::
~

~,
• I
~ I
CENTER
I OlfllllAL JlAUIO c:O .... AN' fORM !l301-7.Z
WIST COIICOIO, ..... ".,.... 111 USA

Figure 4B. Output Circuit

217
 RETURN LOSS VSWR
x
IMo' OdB
PUSH·PULL TPV315
-SOdB IC = UA
VCE = 28V

V
liMO - VISION - 8dB
- SIDE BAND - 16 dB
-SOUND - 7dB - 10dB 1.9

/ INPUT
/ - --........ -INPUT

~
-55dB 1.44

/
/ PUSH·PULL TPV375
-20
OUTPUT
1.22
VCE = 28V
fo = 225 MHz IC = 4.4 A
-60dB 1.12

V -30

-65dB
/ PO WER OUT
FREQUENCY IMHll
10 20 30 40 W PEAK SYNC 160 180 200 220 240 MHz

Figure 5. IMD versus Output Power Figure 6. Input and Output Return Loss versus Frequency
dB
15

10~------------------------~~--____-=

PUSH· PULL TPV 375

VCE = 28V IC = 4.4 A

160 180 200 240 MHz

Figure 7. Low Level Gain versus Frequency

9 w at least

to the
matchIng
circuits

Short epoxy·glass
Circuit
«. = 4.1 ;~.)
a.) Quater Wavelength Balun

=
;
'.~m •••••
ClfCUlts

/
b.) Equivalent Circuit
Figure 8.

218
 TPV 375 push-pull

input

Quadrature Quadrature
combiner combiner

output

TPV 375 push-pull

Figure 9. Combined Pair of Push-Pull Amplifiers

input

input printed
tra nstormer

100mm

output printed
transformer

output

Board material: epoxy·gJass; 1/16 inch; Er = 4.1

Figure 10. PC Board Layout (Not to Scale I

input and output input strip output strip

ground (Zo = 30) (Zo = 40)

r
50 mm

l
Board material: glass teflon; 1/50 inch; tr = 2.55

Figure 11. PC Board Layout for Input and Output Quater-Wavelength Transformer (Not to Scalel

219
 Figure 12. 160-240 MHz Amplifier

J J
• II
BB J 0
On the smith chart the impedances are represented by :

~~Q fAA ~_cc---------, j

QI J AA
I BB
:1° CC

Z, L' Z, L'
(nH) (0) (mm) (Q) (mm)

Calc. value 11.7 21.6 37.5 33 312.5

Empirical value 53.1 25.0 37.5 40 312.5

• L is given for Er = ,
Figure 13. Output Circuit

220
 AN1029
TV Transposers Band IV and V Po 0.5 W/1.0 W

This note describes the performance of a broadband (470-860 MHz) ultra linear amplifier designed for ser-
vice iri band IV and V TV transposers.
Device used:
TPV 596.
Basic specs:
I.M.D. - 60 dB max. at Po = 0.5 watts
Vce = 20 volts; Ic = 200 mA
Pgain = 11.5 dB min.
The approach used is intended to be straight forward and inexpensive as follows.
1) The load line be defined to provide the correct match for peak power (P. sync).
2) The VSWR at the collector be less than 2 : 1.
3) The input match be designed to provide flat gain with decreasing frequency.
4) Use computer aided design.
5) Use a three tone norm
Pvision = - 8 dB
Psound = - 7 dB
Psideband = - 16 d8
6) Circuit realization to be a distributed design built upon teflon glass copper clad circuit boards. However
the design will be analized using Er = 1.0.
The input and output impedances were taken from the TPV596 data sheet and plotted on a smith chart. First consider
the input. To have flat gain with an optimum collector load, the basic physics of a class «A» biased device defines
a gain slope of - 6 dB/octave which must be compensated for. The band of interest is 470-860 MHz which is .915
octaves which implies that 5.25 dB of gain must be compensated for if the device is perfectly matched at 860 MHz.
This means that a transmission less of 5.25 dB or a VSWR for 11.0:1 must be employed at 470 MHz. The input Z is
converted to V on Smith Chart (I). The point at 860 MHz will intersect the constant conductance line equal to 1.0
(20 m U) if it is rotated 0.14 A using a 20 m U (500) transmission line. After this rotation a capacitive stub or chip
capacitor is used to resonate the susceptance at 860 MHz; A capacitive stub or a chip capacitor equal to 16.7 pF can
be used, and the result is shown on Smith chart (I). It is interesting to note that the VSWR vs frequency can be
adjusted for gain flatness by selecting an optimum Zo for the capacitive stub. It is also obvious that the locus of
impedances at the circuit input can vary between the locus of points defined by using a chip capacitor, and the
imaginary axis by using a stub with Zo = ". Graph (II) is a plot of these results. Because infinite isolation doesn't
exist between the output and input of any transistor, and because the required network is very simple, the input
circuit will be optimized empirically. A computed aided circuit will be defined for the output only. It is also indicated
that a combination chip capacitor and stub may provide the best results.
The output circuit considerations were first determined using a Smith Chart approach. It must be clearly understood
that computer optimization is only as good as the circuit configuration and associated computer instructions.

The approach follows:

Smith Chart (II)
1) The device output impedances are first converted to admittances and plotted as the conjugate (V load),
2) In order to allow easy collector lead soldering a Zo = 50 U. 3 mm long transmission line is used. Since
the Smith chart is normalized to 20 m<> (50 n) we can rotate toward the load directly as the chart is confi-
gured.
3) Since the balance of the circuit used Vo = 10 mil (100 n) we next normalize the chart to 10 mii. 100 n
transmission line was chosen as a good compromise between physical length requirements and ease of
realization on Teflon Glass.

221
4) The next element. a shorted shunt transmission line less than )../4 in length reduces the imaginary part
by moving each point of admittance along a line of constant conductance. The length was chosen to locale
the lowest frequency point (400 MHz) near the real axis so that the locus of points would be more equally
distributed about a 2.0 : 1 VSWR circle.
5) The resultant locus of points are then rotated with a 10 mi1 (100 0) transmission line to a degree which
locates the admittance point of 860 MHz near the line of constant conductance equal to 2.0 on Smith
Chart (II). This conductance is exactly equal to 20 m() since the chart is normalized to 10 mn.
6) The final step is to use a parallel resonant circuit which will reduce the imaginary pacts at both the upper
and lower frequencies.
The following approach was used to calculate the element values for the antiresonant circuit.
By observation of the smith chart it was decided to place the 460 and 860 M Hz points on or just inside
the 2.0 : 1 VSWR circle.
It then follows that
1
at f( = 460 MHz W \ C - - - = -0.4
W\L

1
at f2 = 860 MHz W 2 C - - - = 1.7
W2 L
The 2 equations with 2 unknows are solved with the following result.
L =0.189nHy
C = 496.11 pFd
since we are normalized to 10 m(;
Lactual = 0.189/.01 nH = 18.9 nHy
Cactual = 496.11 x 0.1 pF = 4.96 pFd

7) The result is normalized to 20 m(j with the final result shown.

Zo 100 50 0 TPV 596 50 0 100 0 100 0 1000

Calc. Value 45.7 mm 3.78 mm 3 mm 76.1 mm 29.3 mm 4.9 pF 50.4 mm

Empirical Value 8.5 1.5 mm Opti- 3 mm 98.8 mm 39.62 5.5 pF 61.6 mm

48.8 mm mized
Value

Graph (III) shows the various VSWR calculated compared to the theoretical best curve and the actual VSWR
measured .

. Graph (IV) shows the collector load VSWR for the calculated. optimized. and actual result.

Graph (V) is a plot of the single ended amplifier results taken with a network analyzer. No component losses were
considered for the theoretical and optimized analysis. The final circuit was also optimized empirically from
470-860 MHz using a network analyzer.

The following results are a·summary of performance. bias conditions circuit configuration and recommended
hybrid adaptation.

222
starting Imp. 0----0
rotated Adm. X X
final Adm. w/Chip Cap.
final Adm. w/1 0 n Stub •
0----0
•
final Adm. w/50 n Stub b-------A

Figure 1. Smith Chart (I)

223
starting Adm. ••
50 n rotation lC Ie
100 n translation 0----0
equiv. shunt Ind. 11:. t;,.
100 n rotation 8-----0
parallel L-C }I}I
final Adm. 50 n translation • •

Figure 2. Smith Chart (II)

224
 VSWR Transmission
50,0 Loss IdB)
,*,-0 /O.D

30,0 Ideal 9,0

Chip Cap.

I!o.o
18,{)
,,

,,
10nStub
50 n Stub
Actual - 8,0
7,5
1.0
/6,0 ,.s-
",
1'1.0 ,, 6,0
,2,0 , 5:5"
" ,,
, 5;0
laO
9,5
g,o
8.5
e,O 'I,D
;r;S-
~O 3,>
6,S-

6,0
:1,0
S;5

~"
'f.5

'1.0 eo

~5"

",0

t,O
t.,t; 0,9
0,8
o,?-
0,6
:Z,O Q6'
1,9
0."
',1
1,5 , D·l
13
1.0 o
4tJO SOD 600 roo 900
Frequencv (MHz)
AN.50

Figure 3. Graph III - VSWR versus Frequency

225
 Transmission
V.sWR Loss (dB)
5,0
f!,S

Preoptimization
Postoptimization
'1,0 Measured

$,0

f,O
2,5 0,9
0,8
0,-=1
0,6
e.o o,S-
f,9 0,4
l,r
f,!J'.. 0,2

t31 _______~~-------+~~==~:+-------~~------_+
,0. 0
600 ?OO 800 eoo
Frequency (MHz)

Figure 4. Graph IV - VSWR versus Frequency

5,,- __
522----
Return Loss (dB)

o
---4- -- -- -.
tI,
"

---
s ..
-- ..... .....
B
U.
I C, .... ....

to
II
1
------------------~., ,, ,
, \
/ 'I
'I I
1 \ .1, _~
",
\
, \1
\ 1/1 .,t'"
". I
(
\ . I
.. .~~. \ /,1
_II
_I)
)
\ ')~1
a I
I \ -IS
I,
0

.... " -f' Fr,,'t»

s .. ".. -loo 100 Sro
Frequency (MHz)

Figure 5. Graph V - TPV596 Amplifier Performance versus Frequency

226
 Vt.,ASD

IO~F
2nF
~
tf01
1 '"
IN 5o.n.

1
~ '0,,-

1
Class A
VCE ~ 20 V - IC ~ 220 mA
fa ~ 860 MHz - WAVELENGTH (Agi at 860 MHz
(material: Glass teflon 'r ~ 2.55 - 1·16"1
Transistor - TPV596

Figure 6. Circuit Diagram for 470-860 MHz Amplifier

11..n.

Figure 7. Class A Bias Circuit

227
 TPV 596 BROADBAND AMPLIFIER

FREQUENCY RANGE 470 MHz-860 MHz

POWER OUTPUT AT : - 60 dB IMD· ~ 0.5 W
POWER GAIN 11.5 ~ G ~ 12.7dB
INPUT RETURN LOSS" < - 1 dB
OUTPUT RETURN LOSS: < - 11 dB
VOLTAGE SUPPLY - 23 V (VeE = 20 V)
TOTAL CURRENT 220 mA
"IMD : Vision: - 8 dB ; Sound carried: - 7 dB ; Side band: - 16 dB

RECOMMENDED CONFIGURATION

"INPUT RETURN LOSS This amplifier must be used by two connected together with two 3 dB quadra-
ture hybrids to have a balance amplifier with a good input VSWR.

IN
SOU
3 dB 3 dB
Hybrid Hybrid

OUT
50 ~!

"3 dB - 90 0 Hybrid coupler fram

- ANAREN 10264-3
- SAGE wireline 3 dB Hybrid 4450 900

IMD VS OUTPUT FOR A SINGLE STAGE

VeE = 20 V-220 mA

F = 860 MHz; Vision = - 8 dB ; Sound Carrier = - 7 dB; Sideband = - 16 dB

Pout (W) 0.25W 0.5W lW
IMD (dB) - 67 dB - 61 dB - 55 dB

F = 860 MHz; IMD DIN 45004/B

RL = 75 ohms
1.5 V/75 ohms IMD = - 66 dB
2 V/75 ohms IMD = - 60 dB

228
 AN1030
1 W/2 W Broadband TV Amplifier Band IV and V
This note describes the performance of a broadband (470-860 MHz) ultra linear amplifier designed for service
in band IV and V TV transposers.
Device used: TPV 597
Basic specifications
IMD (1) = - 60 dB at Po = 1 W
V ce 20 V; Ie = 440 mA
PRain = 11.5 dB.
(1) Vision carrier - 8 dB. sound carrier - 7 dB. sideband signal - 16 dB.
General design considerations
In general to obtain a flat gain for broadband amplifiers which use .ransistors with about - 6 dB power gain
variation per octave we can use two techniques:
feedback technique (eg emitter resistor and a negative feedback with a selective circuit between the collector
and the base).
or reflect the input or the output power selectivly to have an insertion loss of 6 dB per octave .vith 0 dB
for the highest frequency.
(There is also another technique which uses a selective attenuator).
With the feedback technique we can have a good input and output match. With the second technique
we need to reflect the input power and have a good output match in order to obtain a good IMD. It means
the input VSWR is very high for the low frequencies.
The second solution is simpler than the first and if we use two amplifiers connected together with 3 dB quadra-
ture hybrids to have a balanced amplifier this inconvenience disappears. We have chosen for this amplifier this
second solution. For the larger broadband amplifier (eg 170-860 MHz) this solution must be rejected and
the only acceptable solution is to use the feedback technique.
Amplifier design
The first approach fcr the circuit calculation was made by using the Smith Chart from the input and output
impedances given in the TPV 597 data sheet to have. at the input. a reflected power so that the gain will be flat
and at the output to obtain the best match possible.
INPUT VSWR VERSUS FREQUENCY TO OBTAIN A FLAT GAIN:
The power gain can be approximated by:

G ~
Fmax
(---
)2
F
Fmax is the frequency for which power gain drops to unity.
The transmission loss due to the input reflection is:
~=1_[p[2
P is the reflection coefficient.
To have Gx constant we must have:

Gx ~ (~,;.. )2 [1-lp[2) = Gfl =

GH is the gain at the highest frequency used (F II )
(F;:x r
or [p[ ~

1 + [p[
VSWR = - - - ~
1-[p[

229
Figure 1 shows the theoretical VSWR versus frequency with an insertion loss of 0 dB (implies p = 0) for 860 MHz.
We have defined the input circuit from the TPV597 input impedance to have an input VSWR as close as possible
to this curve, and have assumed that output circuit losses versus frequency is negligible.
After we have calculated separately the input and the output circuits, we optimized some of the parameters by
means of the global amplifier and the TPV597 S-parameters, with the COMPACT Program.
RF equivalent circuit: Figure 2
Program: Figure 3
Calculated gain and empirical gain: Figure 4
Calculated and empirical input VSWR : Figure 5
Calculated and· empirical output VSWR : Figure 6
Amplifier Performance
IMD versus output power: Figure 7A
IMD versus frequency: Figure 7B
Input return loss and VSWR : Figure 5
Output return loss and VSWR : Figure 6
Gain versus frequency: Figure 4
Bias conditions: Vee = 20 V; Ie = 440 mA

Technology and layout considerations

- The glass Teflon 1/16 inch (or = 2.55) is used as board material. This substrate is soldered to the heatsink to
have a good contact and repeatable results.
Figure 8 shows the circuit diagram and the bias circuit; Figure 9 shows the PC board layout.

Combined - Transistor Stage

In many instance the power output requirements of transposers exceed the capability of a single transistor,
which forces the designer to use combinations of transistors. They can be combined by pair with quadrature
combiners (See figure 10). Since quadrature combiners have the ability to channel the reflected power from
the amplifier into the fourth port of the combiner it means the input and output VSWR become very low
(VSWR < 1.2). The power gain is reduced due to the couplers insertion loss by 0.6 dB. Coupler imbalance
should also be taken into account as causing some IMD degradation.

Input VSWR

1+ /1 -(~)T/2
VSWR = ----...;...--

1 -11 -(~)T/
~. -0-. -1!1 From global amplifier and S-parameters

A- - IJ.. -£:. Empirical VSWR

Frequency (MHz)

loaD Soo '00

Figure 1. Input VSWR

230
 AA aa cc DD FF

pF Z, L pF Z, L Z, L
(n) (mm) en) (mm) (n) (mm)

Calc. value 4.5 50 32.0 29.3 25 14 50 72.2

Empirical value 4.7 50 45.4 10.0 25 14 50 34.9

GG HH II JJ KK

Z, L Z, L pF Z, L pF
(n) (mm) (n) (mm) (n) (mm)

Calc. value 110 28.4 45 14 5.1 75 50 3.5

Empirical value 110 27.9 45 1. 3.9 75 38.4 3.3

L are given for C: r = 1.

Figure 2. RF Equivalent Circuit
for Compact Program
MET AA z:z.
CAP AA PA -4.61
TRL BB SE 50 -41.64
CAP CC PA - 25.39
0ST DO PA 25 14 1
TW0 EE S1 50
SST FF PA 50 - 63.43 1 CIRCUIT
TRL GG SE 110 28.44 1 DEFINITION
TRL HH SE 45 14 1
CAP II SE - 5.134
SST JJ PA 75 49.98
CAP KK PA -4.129
CAX AA KK
PRI AA SI 50
END

470 500 600 700

800 860 } FREQUENCY (MHz)
END
.92 176 2.38 72 .033 31 .55 - 166
.91 175 2.21 71 .034 33 .54 - 167
.93 171 1.80 63 .037 34 .56 -170 POLAR S PARAMETERS
.93 170 1.57 59 .039 36 .59 -168 FOR Twfli EE (TPV 597)
.92 169 1.40 54 .043 38 .58 -165
.91 167 1.30 52 .045 40 .58 - 166
END
.5
0 100 1 12 OPTIMIZATION DATA
100 100 2 12
END
Figure 3. Compact Program

231
VARIABLES (-) GRADIENTS
(1) : 4.51899 (1) : - .894864
(2) : 32.0136 (2): .704452E-Ol
(3) : 29.2938 (3): 2.69282
(4) : 72.2399 (4): .287748
(5): 5.16145 (5): 1.68585
(6) : 3.53445 (6) : - .267730
ERR. F. = 7.809
HOW MANY ITERATIONS BEFORE NEXT STOP? O' RESULTS IN FINAL ANALYSIS.
WANT INTERMEDIATE PRINTS (YES = l' NO = O)? TYPE TWO NUMBERS: (I. J) : 0
SEARCH INTERRUPTED. FINAL ANALYSIS FOllOWS:

POLAR S-PARAMETERS IN 50.0 OHM SYSTEM

FREa. Sll 521 S12 S22 S21 K
(MAGN <ANGL) (MAGN <ANGL) (MAGN <ANGL) (MAGN <ANGL) DB FACT.

470.00 0.88 < 134 3.53 < 86.3 0.049 < 45.3 0.11 < 105 10.97 0.75
500.00 0.85 < 128 3.46 < 68.4 0.053 < 30.4 0.12 < 109 10.79 0.90
600.00 0.75 < 92 4.19 < 12.2 0.086 < - 16.8 0.05 < 5 12.45 0.78
700.00 0.59 < 55 4.48 < - 39.2 0.111 < - 62.2 0.19 < -127 13.02 0.78
800.00 0.43 < 11 4.34 < - 93.2 0.133 < -109.2 0.26 < 180 12.75 0.86
860.00 0.20 <- 44 4.08 < -135.2 0.141 < -147.2 0.26 < 114 12.22 1.01

COMPACT PROGRAM

13 dB
--,><-' --. '-<6-...' - ,. ...g
ellc. vllue

12 dB

11 dB
,...-- ......
...... '"7" - ------~ Em pirical value
~--.~.

10 dB .J
I

TPV 597 SINGLE STAGE

Vep,. 20 V Ie = 440 mA

5 dB

l I

I.[
470 500 600
~ 700 BOO 880 101Hz
Frequency (MHz)

Figure 4. Gain versus Frequency

232
 o dB

1'---'-1>_--.
~------~'-""""'-""""
- -........ ___ A-.....
...... ........

-5dB 3.5

TPV 597 SINGLE STAGE

VeE:: 20 V l~ = 440mA

- 10dB
\
_-------------.:._.......J 19

I \\
'.41!:~ Calc. value

- 15 dB 1.44

I:::----,=--------~---------~--------_r_----___j---+ Frequencv (MHz)

470 500 600 700 800 860 MHz
Figure 5_ Calculated and Empirical Input Return Loss

o dB OUTPUT VSWR

TPV 597 SINGLE STAGE

- 5 dB 35

VCJ!. :: 20 V 1,,=440mA
- 10 dB __ 1
y .9

...__- _ - -.!o-- - - -.~ ~Calc. value

.-A- -----
----
- 15dB 1.44

,
.)(
~-\
, ~.",,-
.
I ~ Empirical value

- 20dB ~ 1.22
/
\ ( I
,,-- ...,
"
\
/1 ..----\/ . . _ I
\
, , /
',/:// -', /

- 25 dB
\
\

\
\
\ /
I
r" -'---i .....
~
;r/

Y
"
\
\
\
\ I
/
/
/
/
1.12

I
-30 dB
\

\\ /
\
\ /
I T \
I I
\ I
I I
I
I l
)
\1 \
\
./
700 -- 800
Frequency (MHz)

Figure 6. Calculated and Empirical Output Return Loss

233
 IMD (dB)
55 +---------------+-------------~------------_7y

TPV 597 Single Stage

VISION CARRIER - 8 dB
SOUND CARRIER - 7 d!l
SIDEBAND - 16 dB

-60 +---------------+-------------~~------------4

VCE = 20 V
.65 +---____________1-7--__________-+__ 1,. = 440 mA
F. = 860 MHz

70 +-------~L-----+--------------I--------------_1

-75 +--------I--------I-------~___.... Pout (W)

0 0.5 1 1.5
IMD (dB) Figure 7a. IMD versus Peak Synch Output

----
-60

-~
i
!
SINGLE STAGE

-65
POUT SYNC .. 1W I
VISION CARRIER - 8dB- ---- - - - - - - VCE = 20 V
SOUND CARRIER - 7 dB I, = 440 mA
SIDEBAND -16 dB

I
I
I
I
I
,
i
-70
I
!
1

l
700
Figure 7b. IMD versus Frequency

234
 300t\.
lOv

v BIA"o--r---r---r---,

.
Lengths are given at Fo = 860 MHz
(3.10. )
Ag = - - - -
Fo.Jc..rr
Glass teflon Er = 2.55, 1 16" board material.

a) Circuit Diagram

Vee
4.7
1K

1N4148

330
V81AS

4,7K
10nF

b) Class A Bias Circuit

Figure 8. Circuit Diagram and Bias Circuit

235
 INPUT-- _OUTPUT

50 mm

Board material: Glass Teflon; 1/16 inch; e:, = 2.55

Figure 9. PC Board Layout (Not to Scale)

TPV 597 amplifier

High
input Quadrature VSWR Quadrature
(low VSWR)
combiner combiner

High

VSWR output
(low VSWR)

TPV 597 amplifier

The 3 dB quadrature combiners can be supplied by:

ANAREN (10264-3)
- SAGE wireline (4450900)

Figure 10. Two Broadband Amplifiers Combined with Quadrature Combiners

236
 AN1032
How Load VSWR Affects Non-Linear Circuits
Prepared by
pedance of their loads, either in test systems or
tion of collector current and transistor die
Don Murray
equipment environments. It is easy to compen· temperature.
RF Devices Division
Lawndale, California sate for the insertion loss errors in an attenuator,
The theoretical approach will evaluate the
but it is much more difficult to compensate for
changes in amplifier output power (Po) for a
Reprinted from RF Design Magazine variations in the input impedance difference bet·
given change in load resistance (RL).
ween attenuator pads, that IS, the load VSWR. For simplicity, let us assume the following
H your amplifiers test out fine in the lab but hypothetical conditions, which are typical of
fail DC testing, the testing environment - Let's ex'amine RF correlation on both an empirical today's RF power transistors.
not the product - is likely at fault. and theoretical level.
Hypothetical conditions:
Consider the following scenario: You're designing EMPIRICAL APPROACH VCC = 28V
and implementing into production a broadband The empirical approach is shown in Table I, VCESAT = 1.5V
Class C power amplifier. During your design where several test circuit loads (consisting of POUT = 50W
phase, you follow all the rules of science and series attenuators, directional couplers and RF Frequency - 1.0 GHz
also dig into your bag of electronic tricks to switches) were assembled. The insertion loss and Solving for load resistance:
meet the design specification. Your design is input impedance of each load string was Rl _ IVcc - VCESAT)' 702.25
fabricated and tested successfully in the lab. measured. Following this, the individual loads 7.Dm
Twenty·five more units are built in the lab and were connected to a given test circuit containing 2Po 100
they, too, test out fine. a common base microwave power transistor. The
power meter used was also a constant. Additionally, assume that a simple two·section
Confident that both design and production pro· impedance matching network matches the 7Q to
cedures are satisfactory, you begin series produc· Table I shows insertion loss, insertion loss correc· 50Q. Let this two·section match consist of two
tion. But when the first units reach RF test. not tions, indicated RF power, and actual power data ).f4 wave transformers.
one meets specification. Yet when you retrieve of each load string. A maximum error of 0.52 dB
the units, they test OK in the lab. was detected with a standard deviation of .19 Given the conditions we have hypothesized, the
dB. All these loads had a VSWR less than 1.1: 1 Rl of 7.02Q represents the collector load that
What's wrong with these amps? Probably at the frequency tested. A VSWR of 1.1: 1 is will yield the best simultaneous satisfaction of
nothing. This scenario, in one form or another, is better than the published specifications of com· device efficiency, device gain, gain transfer
all too common in the design and manufacture of mercially available attenuators, directional characteristics, and saturated power.
non·linear RF circuitry. The culprit is correlation couplers, and RF switches from most leading
of test systems. A difference of .5 dB is enough manufacturers. A VSWR gf 1.5: 1 is a typical For minimum Q, with a 2 section match, the
to fail units that are perfectly good, resulting in VSWR specification limit at 1.4 GHz. It must be transformation ratio of each section is

J
unnecessary and expensive retesting or even noted that many users will gladly pay an addi·
reworking. Still worse, a half dB error will pass tional nominal charge for components meeting a
1144Q
units that don't meet specs and never should be tighter VSWR spec. )Q
),4 long 50Q
shipped.
THEORETICAL APPROACH 5O.,aQ }J
Such correlation errors will disrupt an even more The vehicle for the theoretical discussion is the .1.4 long

important function, that of maintaining product well known expression:

~2.67.
continuity. A device built in 1982 should perform
the same as an identical model number device IVcc - VCESAT!'
built in 1976. Another way of saying this is that Po = 2Rl
a device tested in a 1982 test system should
Where: Po = Power output ZO 1st section = 1/""'1""7)"'12-=.6:=71""'17::-)
produce the same results when tested in a 1976
Vcc = Collector supply voltage
system. The key, of course, is RF correlation. 11.44Q
VCESAT = Collector· Emitter saturation
voltage
What is RF correlation? Simply put. RF correia·
Rl = Load resistance.
ZO 2nd section - V (7112.67)150)
tion occurs when target error limits are estab· 3D.58Q
lished and adhered to on a continuous basis This expression is valid for a narrow range of Rl
among two or more testing stations. Such cor· 110% range maximum). Over a wider range of ),/4 @ 1 GHz = 2.95" = .075m
relation is essential to cost ·effect production of Rl, significant changes in VCESAT occur as a
non·linear RF and microwave power amplifiers, function of Rl. Output power varies with the Table II shows the transformed impedance at the
whose circuits are extremely sensitive to the im· square of VCESAT. VCESAT is a very strong func· input of the matching network as a function of

237
Table I, Microwave Load Substitution Study

The vehicle used for this test was a production test fixture and correlation sampte #2 for the TRW MRA1417·6 broadhand, high·gain transistor. Measurements were taken at
1400 MHz with IIput power of 1 1W
Maasured Circuit Maasured Delta . Load Input
Power Return Collector Insertion Calibration Actual from Return Impedance
Load # Level Loss Current Loss Error Power Reference Loss Angle Raal Imaginary
I 1.IW 35 dB - 30.03 dB +.03 dB thru calibration -40.2 99.1 49.8 + 1.0
1 7.7W 16 dB .51 A 30.03 dB +.03 dB 7.75W reference -40.2 99.1 49.8 + 1.0
2 7.6W 15.5 dB .5 A 39.66 dB -.44 dB 6.B7W -30.5 -77.5 50.6 -3.0
3 7.65W 15.5 dB .51 A 39.68 dB -.32 dB 7.10W +.38 dB -34.1 -171.5 50.4 -2.0
4 B.OW 15.5 dB .51 A 39.B dB -.20 dB 7.63W - .07 dB -34.1 68.1 50.7 -1.9
5 7.2W 16 dB .505 A 30.16 dB +.16 dB 7.47W -.16 dB -30.1 -128.0 51.1 -3.0
6 8.3W 15.2 dB .51 A 39.78 dB +.22 dB 7.89W +.08 d,B -31.7 -144.6 47.9 -1.5
7 7.75W 16.2 dB .505 A 39,73 dB -.27 dB 7.28W - .27 dB -32.7 11.9 49.0 -2.4
8 7.78W 16.8 dB .503 A 39.7 dB -.30 dB 7.26W - .28 dB -35,4 -111.9 49.1 -1.5
Largest Delta after calibration correction is 0.52 dB.
Mean value of the measured power = 7.41 W,
Standard Oeviation •. 34W • ,19 dB.

Note: - 30 dB RETURN LOSS = e of 0.03 and VSWR of 1.06: 1.

Table II. RL Effects on Output Power

BI Make a bad circuit look good.
Load Resistance Transformed Load Output Power Cumulative
IQI Resistance IQI IWI MB ~dB
This analysis was done for a single frequency.
45 6.30 55.73 The problem is compounded in a broadband
.095 .095 environment by requirements for a good broad·
46 6.44 54.52
band load impedance.
.093 .189
47 6.58 53,36
.091 .280 TEST EQUIPMENT ACCURACY
48 6.72 52.25 Test equipment manufacturers have produced
,090 .370 some very impressive equipment in recent years;
49 6.86 51.1B however. the accuracy of a well constructed
.087 .457 system using the latest equipment available is
50 7.00 50,16 generally considered to be no better than ± 3% .
.086 .543 Considering the number of variables in RF testing
51 7,14 49.18 and the magnitude of the task faced by the test
.OB5 .628
equipment manufacturers. ± 3% is no small
52 7.28 48.23
,083 ,710 achievement. However. ± 3% is ±.13 dB. This
53 7.42 47.32 ±.13 dB added to the ± .435 dB indicated
.081 .791 earlier yields a total possible error magnitude of
54 7.56 46.45 ± .565 dB. This adds up to a total possible error
.080 .B71 of ± 14% into a load with 1.1: 1 VSWR. The
55 7.70 45,60 output power range of our amplifier is now 50W
± 7.05W.
Maximum Delta dB Vs, VSWR
Now we see how bad things can be. a few com·
VSWR Maximum ~dB
ments on reality are in order.
1.02 ,171±.0851
1.04 .341±,171 The author believes that the correlation target
1.06 .51 1±.2551 for the test of RF power devices should be ± 0.2
LOB .68 I± .341 dB. which we believe is the optimum tolerance
1.10 .B7 1±.4351 for combining strict quality standards and the
need for easy repeatability under series produc·
various load impedances. Our example utilizes a CONCLUSION tion conditions. If more than an occasional device
real·to·real impedance match for convenience. The The data presented' in table represents the power fails this test. do not assume that the devices
analysis also is appropriate for an imaginary·to· variation into a load with a VSWR of 1.1: 1 are at fault. Instead. first analyze the test circuit
real match in that center of the VSWR circle at relative to 50Q. The result is a power output of and then the test system to determine the
the input to the matching network will be 50W ± 5.3W 1±.435 dBI. The total Delta is reason for the additional error. Some suggestions
rotated but won't change in magnitude from the 10.3W I.B 7 dBI. This is enough to: on how to maintain a ± 0.2 dB correlation are
data presented. AI Make a good circuit look bad. or. shown in Table III.

238
 Table III. Notes

Suggestions to the Maintenance of Correlation

1. Serialize and documenl all components lallenualors. 5. Be selective when using cables in lesl systems. For
directional couplers, power meters, detectors, etc.) of example, the MIL·C·ll specification for "RG" cable
Ihe lesl syslem. Do nol dislurb Ihe syslem once Iypes says Ihal RG·58 can have a characleristic im·
calibration has boon performed. Calibrate the system pedance from 4B 10 52Q Imaximu VSWR of
once a month. 1.04: 11 when lerminaled in a "perfect" 50Q load.

2. Require that loads have a calibration return loss 6. Be very seleclive when choosing RF switches. The
~-35 dB IVSWR of 1.05:11 in frequency band of VSWR of a mechanical switch will vary wilh lime.
interest.
7. If possible, lerminale Ihe system wilh a 5DQ load
3. Dedicate test systems to specific circuits or rather than an attenuator. Load manufacturers need
products. This is necessary for bOlh correlalion and only consider Ihe VSWR of a load. However, for
product continuity. allenualor, tradeoffs must be made belween VSWR
and frequencv response. Measure power and other
4. The placement of transistors in the test fixtures performance parameters via calibrated directional
must be uniform. For instance, flanged transistors couplers.
should be placed in Ihe lest fixtures wilh Ihe device
pushed lowards collector load clrcuilry.

The 0,2 dB target is an achievable target in

broadband test systems. However, a constant
awareness of the test system capabilities and
potential problem areas is mandatory. RF correia·
tion problems will never go away, but they can
be made easier to handle.

239
240
 AN1033
Match Impedances in Microwave Amplifiers
and you're on the way to successful solid-state designs.
Here's how to analyze input/output factors and to create a practical design.
Prepared by
Roger DeBloois

The key to successful solid-state microwave

power-amplifier design is impedance matching.
In any high-frequency power-amplifier de-
sign, improper impedance matching will degrade
stability and reduce circuit efficiency. At micro-
wave frequencies, this consideration is even more
critical, since the transistor's bond-wire induc- 1. In this output equivalent circuit, cap~citance Con
tance and base-to-collector capacitance become is almost equal to the selected transistor's collector·
significant elements in input output impedance to·base capacitance Cob'
network design.
In selecting a suitable transistor, therefore,
keep in mind that the input and output imped- this capacitance as is physically practical and to
ances are critical along with power output, gain provide the balance with high-quality chip ca-
and efficiency. pacitors.
Unless the selected transistor is used at fre- The first section of the impedance matching
quencies that are much lower than the maximum network is extremely important because it can
operating frequency, the input impedance is degrade the stability of the amplifier if it is not
largely inductive with a small real part. The well designed. Depending on the design frequency
large inductance is due to bond wires that con- of the amplifier and the transistor selected, the
nect the transistor chip to the input lead of the resonated real impedance can range from less
package and to the common-element bond wires. than 50 n to much higher. When it is below 50 n,
The small real part of the input impedance is due an additional low-pass matching section can be
to the large geometries required to generate high conveniently added to achieve the required 50..n
power at high frequencies; the base bulk resist- impedance at the input.
ance may be the predominant. part of the real The higher-impedance case presents a special
input impedance. problem if microstrip techniques are used to
build the matching network. The problem occurs
because the resonated impedance may be as high
Use microstrip stubs at input network
as 300 n. Reducing this to 50 n by use of a low-
The first and most important step in designing pass network configuration requires a series-
the input matching network for the selected de- transmission line that will behave as an inductor.
vice is to provide a shunt capacitance that will The rule of thumb is that the characteristic im-
resonate the inductive component of the input pedance of the transmission line must be at least
impedance. This step forms the low-pass match- twice the higher impedance before such behavior
ing section of the network and should provide results. Examination of the accompanying table
the smallest possible transformed impedance. To shows that characteristic impedance lines of great-
minimize the inductive component, the input and er than 100 n are very narrow. Narrow trans-
common-element lead lengths must be kept short. mission lines (less than 0.01-inch wide) should
The resonating capacitance is generally best be avoided wherever possible, because repeatabil-
provided by a microstrip stub. In some cases the ity of width dimensions is poor. Also, the loss in
stub producing the required capacitance is so a narrow line may become excessive. A better
large that a practical circuit size cannot be solution is to use a quarter-wave transmission-
realized. It is best then to distribute as much of line transformer with a characteristic impedance

241
equal to the square root of the 50-!l impedance
product: Z. = ,,50 ZR~

Make output bandwidth wider than input

The output impedance of a microwave power
transistor is usually defined as the conjugate of
the load impedance required to achieve the de-
vice performance. A typical output equivalent cir-
cuit is shown in Fig. 1. The capacitance C",,, is
nearly equal to the collector-base capacitance C"h
specified for the selected transistor. L, is the
inductance of the bond wires used to bridge from
the collector metallization area to the package
output lead, and L,.,,,,, represents the inductive
effects of the common element bond wires.
For correct operation of the transistor, the 2. With this typical microwave amplifier breadboard lay·
ultimate load impedance must be transformed to out, the entire board can be soldered to a metal plate
a real impedance across the current generator. to provide a path for thermal cooling.
This real impedance is determin~d by By adjusting the amount of shunt inductance
R - [Y", .y,,(sa_t>1~ and rematching with the low-pass section, the
L- 2P,)ut designer can create a truly broadband output
The load impedance presented to the package match.
terminals will contain the real impedance at the
current generator, transformed to a lower value
Don't overlook base and collector paths
by the low-pass L section formed by C,.,,, and the
parasitic inductances L,. and L", .. Usually the In addition to matching the device impedances,
reactive part of the load impedance is made in- direct-current paths must be provided to the base
ductive to tune out the residual capacitance of and collector of the transistor. The collector path
the device. is provided by the shorted stub in the imped-
The output matching network should be de- ance-matching network. The base path requires
signed so it has greater bandwidth than the in- the addition of a choke from the base to ground.
put matching network. Providing a good collector The choke can he a lumped element or a distribu-
match, both above and below the design frequen- ted shorted stub of sufficient impedance to be
cy, ensures that the input. power will be reflected negligible in the circuit. A quarter-wavelength
before the collector VSWR rises to values that stub is ideal. The narrowest practical line should
endanger the transistor. In this way the tran- he selected. In addition a dc blocking capacitor
sistor is protected from off-frequency operation. is required in the collector circuit. Also needed is
The amount of additional bandwidth required for a bypass capacitor to provide the proper ac
protection of the transistor depends on the rug- shorting point for the inductive stub in the col-
gedness of the transistor used. The manufac- lector-matching network.
turer's specifications for VSWR tolerance and Selection of a blocking capacitor is relatively
input Q can be a guide for determining the band- straightforward. The capacitor should be chosen
width requirements of the input matching net- to provide low loss at the operating frequency
work. while maintaining the capacitance at a value
One technique for obtaining the required band- that inhibits low-frequency oscillation. The latter
width is to resonate a portion of the capacitive is caused by the series capacitor's tendency to
reactance of the transistor output impedance display rising reactance with decreasing fre-
with a shunt inductor. The shunt inductor cali quency.
also be used to feed the collector supply voltage Blocking capacitors must be large enough to
to the transistor. Additional transformation may preserve coupling characteristics down to a fl'e-
he obtained from a low-pass matching section. quency where the shunt-feed chokes can effec-

242
Microstrip Zo and velocity factor vs width-to-height (W/H) ratio.
(Prepared by Don Schulz, Applications Engineer)

Air Teflon Epoxy Alumina

K = 1.0 K = 2.55 K = 4.25 K - 9.6
W/H Z. Vp z; Vp zo Vp z. Vp

0.630 168.425 1.000 110.683 0.657 87.986 0.522 60.977 0.362

0.695 161.878 1.000 106.258 0.656 84.414 0.521 58.441 0.361
0.766 155.370 1.000 101.865 0.656 80.870 0.521 55.927 0.360
0.844 148.909 1.000 97.509 0.655 77.360 0.520 53.440 0.359
0.931 142.506 1.000 93.199 0.654 73.888 0.518 50.985 0.358
1.026 136.171 1.000 88.941 0.653 70.463 0.517 48.566 0.357
1.131 129.916 1.000 84.745 0.652 67.090 0.516 46.187 0.356
1.247 123.753 1.000 80.616 0.651 63.775 0.515 43.853 0.354
1.375 117.692 1.000 76.565 0.E51 60.524 0.514 41.568 0.353
1.516 111. 746 1.000 72.597 0.650 57.345 0.513 39.337 0.352
1.672 105.926 1.000 68.721 0.649 54.243 0.512 37.164 0.351
1.843 100.242 1.000 64.944 0.648 51.223 0.511 35.053 0.350
2.032 94.706 1.000 61.273 0.647 48.291 0.510 33.007 0.349
2.240 89.327 1.000 57.714 0.646 45.451 0.509 31.030 0.347
2.470 84.115 1.000 54.271 0.645 42.709 0.508 29.123 0.346
2.723 79.076 1.000 50.951 0.644 40.066 0.507 27.289 0.345
3.002 74.218 1.000 47.757 0.643 37.527 0.506 25.531 0.344
3.310 69.546 1.000 44.692 0.643 35.094 0.505 23.849 0.343
3.649 65.065 1.000 41.759 0.642 32.768 0.504 22.244 0.342
4.023 60.779 1.000 38.959 0.641 30.550 0.503 20.716 0.341
4.435 56.689 1.000 36.292 0.640 28.440 0.502 19.266 0.340
4.890 52.796 1.000 33.760 0.639 26.439 0.501 17.892 0.339
5.391 49.100 1.000 31.360 0.639 24.544 0.500 16.594 0.338
5.944 45.600 1.000 29.091 0.638 22.755 0.499 15.370 0.337
6.553 42.291 1.000 26.952 0.637 21.069 0.498 14.218 0.336
7.224 39.173 1.000 24.938 0.637 19.485 0.497 13.138 0.335
7.965 36.233 1.000 23.047 0.636 17.998 0.497 12.125 0.335
8.781 33.484 1.000 21.275 0.635 16.606 0.496 11.179 0.334
9.6111 30.904 1.000 19.618 0.635 15.305 0.495 10.295 0.333
10.674 28.491 1.000 18.071 0.634 14.091 0.495 9.472 0.332
11.768 26.240 1.000 16.629 0.634 12.961 0.494 8.707 0.332
12.974 24.143 1.000 15.288 0.633 11.911 0.493 7.996 0.331
14.304 22.192 1.000 14.043 0.633 10.937 0.493 7.338 0.331
15.770 20.381 1.000 12.888 0.632 10.033 0.492 6.728 0.330
17.387 18.702 1.000 11.818 0.632 9.198 0.492 6.164 0.330
19.169 17.148 1.000 10.830 0.632 8.425 0.491 5.644 0.329
21.133 15.172 1.000 9.917 0.631 7.713 0.491 5.164 0.329
23.300 14.385 1.000 9.074 0.631 7.056 0.490 4.722 0.328
25.688 13.162 1.000 8.299 0.630 6.451 0.490 4.315 0.328

243
 Table continued

W/H
28.321
Z.
K

12.036
-
Air
1.0
V,
1.000
Z.
7.585
Tetlo ..
K - 2.55
V,
0.630
Z.
5.894
Epoxy
K - 4.25
Vp
0.490
Z.
Alumina
K - 9.6

3.942
V,
0.327
31.224 10.999 1.000 6.929 0.630 5.383 0.489 3.598 0.327
34.424 10.047 1.000 6.326 0.630 4.914 0.489 3.284 0.327
37.953 9.172 1.000 5.773 0.629 4.483 0:489 2.995 0.327
41.843 8.370 1.000 5.266 0.629 4.089 0.489 2.731 0.326
·46.132 7.634 1.000 4.801 0.629 3.727 0.488 2.489 0.326
50.860 6.960 1.000 4.376 0.629 3.397 0.488 2.267 0.326
56.073 6.343 1.000 3.987 0.629 3.094 0.488 2.065 0.326
61.821 5.779 1.000 3.632 0.628 2.818 0.488 1.880 0.325
68.157 5.264 1.000 3.307· 0.628 2.566 0.487 1.711 0.325
75.144 4.792 1.000 3.010 0.628 2.335 0.487 1.557 0.325
82.846 4.362 1.000 2.739 0.628 2.125 0.487 1.417 0.325
91.337 3.969 1.000 2.492 0.628 1.933 0.487 1.289 0.325
100.700 3.611 1.000 2.267 0.628 1.758 0.487 1.172 0.324

tively short the respective port to ground. Cou- When plastic materials are used, it's a good
pling capacitors should not be excessively large, practice to measure the material thickness and
or they may produce as much as I-dB 10" in dielectric constant, because variations are com-
gain with a corresponding decrease in efficiency mon. In a recent test the dielectric constant of a
in the case of collector coupling capacitors. The sheet of epoxy fiberglass material was measured
Q of the coupling capacitor determines the ac- at 4.55 at 1 MHz and 4.25 at 500 MHz. If the
ceptable range of capacitance values and is gen- manufacturer's value of 5.5 had been used for
erally inversely related to capacitance. the design of matching- networks, considerable
Bypass capacitors are selected by analysis of error would have rewlted.
the same considerations as those for blocking The physical dimensions of the matching cir-
capacitors. A large bypass capacitor (tantalum cuitry may be calculated from the data in the
or electrolytic), placed from the de feedpoint to table. The line lengths are scaled by the velocity
ground, prevents tendencies toward low-frequen- factor, which is equal to Z. Z. in air for a
cy oscillation in the circuit. Also, it may be neces- constant width-to-height ratio, W H.
sary to add smaller bypass capacitors to preserve The final design of a typical breadboard micro-
stability over a wide range of frequencies. wave amplifier is shown in Fig. 2. The ground
areas on the top of the board are connected to
Adjust for bandwidth and physical dimensions the microstrip ground plane by 2-mil-thick foil
wrapped around the edges of the board and the
The circuit design may be adjusted quickly for
areas directly under the emitter lead~ of the
bandwidth requirements through use of a com-
transistor. The foil is secured to the top and bot-
puter optimization program such as Magic, of-
fered by University Computing of Dallas, Tex. tom surfaces with solder. Plating: may be u,ed
for production units. The entire board can bt'
When that step is finished, electrical dimensions
soldered to a metal plate to allow connedor
mllst be converipd to physical dimensions.
mounting and to provide a thermal path for the
At this point in the design sequence, the di-
heat generated by the tran,istor.
electric material must be chosen. Three common-
I~' used mate.rials are Teflon fiberglass, epoxy The initial tune-up of the amplifier matching
fiberglass and alumina. Above 500 MHz, epoxy circuits can be t'xpedited by ll,e of a network
fiberglass exhibits too many losses to be a good analyzer and a precision load on the input or
choic.e. Teflon fiberglass ('an be used up to sever- output connector. The circuit can be adj usted to
al gig-ahprtz: it has reasonable dielectric losses match the nominal impedances "llpplied by the
and is eas~' to pro(·ess. Alumina, a ceramic, offel-s transistor manufacturer. Distributed stubs are
a high rlielpetric constant, good dimensional con- purposely made longer than ne('essary and are
sistency and small circuit geometry. adjusted to the correct length by trimming of the

244
foil 011 the capacitive stubs. The inductive stub with appropriate values indicated for the sample
in the output network iR adjusted by positioning design is shown in Fig. 3. The input match is
of the bypas~ capacitor along the stub and the achieved when the input impedance is resonated
adjacent ground plane. with a capacitive susceptance of 0.18 mhos. This
This procedure result.. in a load line that is susceptance is realized by use of a pair of capaci-
fairly close to optimum. A transistor can now tive microstrip stubs. Each stub must exhibit a
be inserted in the circuit and the collector match- reactance of 2 x 1 '0.18 mhos. or 11.1 n. The
ing network readj usted for maximum collector length of the stub may be calculated by
efficiency. Stub tuners are used to match the
amplifier input impedance. so that only one vari- tan 0 ~•.
= X,
able at a time need be considered. Initially it
may be necessary to operate the transistor at re- For ease of adjustment, the length of the
duced collector \'oltage and power output to avoid stubs should be less than 60 degrees. Because ca-
~xcessive stress. When maximum efficiency is pacitive reactance is a tangential function. the
obtained, the stub tuner is removed and the in- reactive variations per unit length become in-
put network adjusted for minimum input VSWR. creasingly severe past 60 degrees. It is better to
decrease Z, rather than to use longer stubs to
Now let's design an impedance-matching circuit achieve higher capacitance. Therefore Z, ~ 1.732
Let's consider a practical example of a pro- X,. ~ 19.24 fl. Because it is easier to shorten a
cedure for the design of impedance-matching microstrip stub than to lengthen it. the Z, of
circuitry. The sample circuit uses a TRW 15 fl, for example, provides sufficient adjustment
2N5596 at 700 MHz as the active device. r~nge to accommodate device variations.
Specifications for the completed amplifier are: The next step is to transform the resonated
impedance to 50 fl. This is accomplished by a
Z" 50 fl. series-transmission line with a characteristic im-
Z,.", 50 fl. pedance of 50 fl. From Fig. 3. we see that the
P,,,, 20 'A'. length of this line can be directly determined to
Gp 7 dB. be 0.062 wavelengths. or 22.3 degrees, long. A
7) . 55""( minimum. capacitive susceptance of 0.040 mhos completes
Specifications for the TRW 2N5596 are: the transformation. Again, a pair of capacitive
stu bs will provide the susceptance. For ease of
Po" 20 W at 1 GHz, converting the design to microstrip dimensions,
7) 55 c , minimum at 1 GHz. it is convenient to choose a Z" for the second
Gp 5 dB minimum at 1 GHz. stub that is equal to that selected for the first.
Z" 2.5 + J4.0 at 700 MHz. Therefore:
Z,,", 6.0 - J12.5 at 700 MHz.
tan 0 Z" = 50
= x, 15 = 03
.,
In practice. the gain of a common-emitter
amplifier decreases at a rate of 4 to 5 dB per or 0 = 16.7 degrees.
octave. The 2N5596 at 700 MHz produces about
In this case the length chosen is 20 degrees to
7 dB of gain. Therefore approximately 4 W of
allow for some adjustment.
drive will be required to produce 20 W of output
The output match is achieved by partial reso-
power. The collector efficiency can be expected
nating of the device's output impedance with an
to increase at the lower frequency. but it is diffi-
inductive susceptance. While the amount of sus-
cult to estimate because it i~ a complex phenome-
ceptance chosen is arbitrary at this point. the
non. Manufacturers' curves of typical behavior
output network bandwidth is affected by the
are useful. Output power will not increase sig-
value. From Fig. 3. we can determine that 0.05
nificantly with the decreased frequency.
mhos is required for the first matching element.
The efficiency-frequency relationship depends
This susceptance is achieved by use of a shorted
on device fT and ballasting. Heavily ballasted
microstrip stub. The length of the stub may be
transistors tend to give increaspd efficiency as
calculated from the equation
frequency is decreased. However, they level out
at a lower efficiency than a non ballasted part X,
tan () co, Z,,"
because of I'R losses in ballast resistors. The
average increase in efficiency as a result of de·· If Z" of the stub is arbitrarily chosen to be 50 fl.
creasing frequency is about 20 I;. per octave. 20
tan () = . 50 = 0.4,
Values from 10 to 407< per octave have been
measured. () = 21.8 degrees.
The initial phase of the design is best ac- Again. the stub is made somewhat longer be-
complished on an immittance chart. The chart cause it can he adjusted by sliding the chip

245
capacitor (ac short) up or down the line length.
The remaining transformation is achieved by a X,. =2 x O~ti4 = 143 n.
50-11 series-transmission line of 0.15 wavelengths Z 50
(54 degrees long) and a capacitive susceptance tan =-x': = 143 = 0.350 = 19.3 degrees.
of 0.014 mhos. Selecting a pair of 50-ohm micro- A stub length of 25 degrees will provide
strip lines to provide the susceptance requires a an adequate allowance for adj ustment of the
stub length of circuit. ••

3. The immittance chart, with values specified for the capacitive stubs. Impedance transformations are achiev·
design example, indicates tne necessary inductive and ed by 50·n series·transmission lines.

246
 AN1034
Three Balun Designs For Push-Pull Amplifiers

S INGLE RF power transistors seldom

satisfy today's design criteria; sever-
The success of these two balun types should prompt the
microwave designer to ask if balun-transformers can be
al devices in separate packal/:es! or in the same packal/:e included in circuits for frequencies above 400 MHz. Theory
(balanced, push-pull or dual transistors), must be coupled and experimental results lead to the emphatic answer: yes!
to obtain the required amplifier output power. Since high- Not only will baluns function at microwave frequencies, but
power transistors have very low impedance, designers are a special balun can be designed in microstrip form that
challenged to match combined devices to a load. They often avoids the inherent connection problems of coax.
choose the push-pull technique because it allows the input On the next six pages, you will observe the development
and output impedances of transistors to be connected in of three balun-transformers-culminating with the micro-
series for RF operation. strip version. None of the baluns was tuned nor were the
Balun-transformers provide the key to push-pull design, parasitic elements compensated. In this way, the deviation
but they have not been as conspicuous in microwave circuits of the experimental baluns from their theoretical per-
as at lower frequencies. Ferrite baluns' have been applied formance could be evaluated more easily. The frequency
up to 30 MHz; others incorporating coaxial transmission limitations imposed by the parasitic elements also were
lines operate in the 30-to-400-MHz range.' observed more clearly.

1. A balun transforms a balanced system that Is

symmetrical (with respect to ground) to an un-
balanced system with one side grounded. Without
balun-transformers, the minimum device impedance
Ireal) that can be matched to 50 ohms with acceptable
hand width and loss is approximately 0.5 ohms. The
INPUT Til .. ,,· OUH'UT OUTPUT .... lU ... key to increasing the transistors' ~I
'::N~~':~ SllrOIlS '::N;~':: ..... LANel UN .... l ... NCEI output power is reducing this im-
pedance ratio. Although 3-dB hy-
brid com hiners can double the maxi-
mum power output, they lower the
matching ratio to only 50:1. Balun
transfnrmers can reduce the origi-
nal 100:1 ratio to 6.25:1 or less. The
design offers other advantages: the
baluns and associated matching cir-
cuits have greater bandwidth, lower
losses, and reduced even-harmonic
levels .
.,.,.ut
fLOWVIWAI

2. Baluns are not free of disadvan-

tages. Coupling a pair of push-pull
amplifiers with 3-dB hybrids avoids
(for four-transistor circuits) one of
these: the higher broadband VSWRs
of hal un-transformers. A second dis-
advantage, the lack of isolation be-
tween the two transistors in each ·;t";~(;:;rVi~fM~,&~~~.ampll-
push-pull configuration, is outweighed by the advan-
tages of the balun design in reducing the critical
impedance ratio.

247
 3. In this simple balun that uses a coaxial trans-
mission line, the grounded outer conductor makes an
unbalanced termination. and the floating end makes
a balanced termination. Charge conservation requires
that the currents on the center and the outer conduc-
tors maintain equal magnitudes and a ISO-degree
phase relationship at any point
along the line. By properly
choosing the length and charac·
teristic impedance, this balun l',,"A'. A
Ulllfl I • •
can be designed to match de· 1,""'.1'. fA,. B.n"I/P4>~1I

vices to their loads. In the case

shown, if 0A = 90 degrees, the
matching condition is:
ZA' = 2xRx50.

4. By adding a second coaxial line, the basic balun can 4

be made perfectly symmetrical. In this symmetrical coaxial

LINE A Z ..... 'A
balun, the bandwidth (in terms of the input VSWR) is L1NEa.LINEC Z._IC_"._"C

limited by the transformation ratio, 50/2R. and the

leakages, which are represented by lines Band C. If ZA =
50 ohms and R = 25 ohms, the bar.dwidth is constrained
only by the leakages.

5. The equivalent circuit lor the symmetrical balun

tR
shows the effect of the leakages (lines B and C) on its
performance. A broadband balun can be obtained by using
a relatively high characteristic impedance for these leakage
lines. In theory, the construction of the baluns insures
perfect balance.

6. The symmetric balun's Input equivalent circuit further

SYMMI'''leAl I"'UIN lOUIVALE"" CUlcun LU
simplifies its configuration and allows the input VSWR to
be calculated.' In this design, line A has a characteristic
impedance of ZA =50 ohms, a length of LA = 1799 mils, and
a dielectric constant (relative) of .,=2.10. For lines Band

-----=fl
C, Z, = 30 ohms, 171799 mils, and '.rr = 2.23.

I
L=1799 , - - - - - - - - - - - - -
LlNE ... ,t, Z" ... -lA' .......""
I r LINE • •
II L _2!!
1 •• _21" '•• =".

l ... _IO I

"~::::5 \""""-211_2 / I
-~ rl-------------------
./ I
!

FREQUENCY at..
THIOIUTICAL INPUT RESPONSI OF THE SVMMITllle BALUN tDESIGN 11

7. The theoretical Input VSWR has been calculated for

50-ohm values of ZA and 2R, and for two other sets of values
for these parameters. The performance of an experimental
\_--y-----" '--v-" ~ '-v-'
balun will be compared with these theoretical results. IALUN Z!ir\UNIS 'I LllilIE·SICT,OIl: LOAQ
COAlIIlAl MICIlOSTIII' CHEavSHIV IMPlDANCE
MICIIOSTIU,. T:'~~:~~~~~"
LINEA Z .. _liO' .. L ... _11 •• MIL ...... 210
LlNII lINEC Z.=ZC-lO".L.=LC_11 •• MlL •..•"=ZZl

8. Two M16 line-section Chebyshev Impedance tr.ans- LINEO LlNEO' ZO_za, .. LO_1S0 MIL •. · . . . . ZZl
UNE f UNEE' ZI _.1 a".L E _ 4.4 .. ILI . •"_ 210
lormers match the experimental balun to a 50-ohm meas- LINE ~ LINE F' Z,=20 3".L,=44' MIL •..• "= 2 31 IXPIIIIMINTA ..
COAXtAL I,sLUN IDE.IGN It
urement system. The balun was tested from 0.6 to 1.5 GHz. WITH OUTPUT 1111,s"'.'OIllIlllII.

248
 9. The measured phase difference and Insertion loss

!:E : :~ =:4
difference, which indicate the maximum unbalance for
the Design 1 experimental balun, are 3 degrees and 0.2 dB,
respectively.

::c:: :=~
01 07 G, 0' 10 II
'".QUINCY - GHI
12 11 ,. "
10. The maximum VSWR mealured 'or the 'Irst
dellgn II 1.5:1. Note the comparison between the
calculated and measured response. The performance
shown can be considered valid for amplifier applica-
tions up to an octave range.

.. -----------'---,~""" .... :.:::::::....-~

11. The second balun design adds two Identical

coax lines to the simple balun just described. The
I '---'--v----' '--v------' inputs of the identical lines are connected in series
I FlIIST SICTlON SICOfolO SICTlON I to the output of the first balun. By putting their
I'~'·-·-··-·-·-"-··-'-'·-·-··-"-A-'--'-';-:.-:.-':-~.-~_::_:_:_:_:_:_:_'___" __"'_"_._"_"_'_'._'_"~"~AJ outputs in parallel, the final output becomes sym-
metrical. The output impedance is halved.

r ®I 12. The equivalent circuit lor the Design 2 balun

indicates that its bandwidth, in terms of input VSWR,

:-[-.
I : is limited by the transformation ratios of the first and
second sections and the leakages represented by lines
B, C, E, and G. If the balun is designed with ZA =
50 ohms, and Zu = ZF = 25 ohms, and if the load,
2R, is set at 2x 6.25 ohms, all of the transmission lines
will be connected to their characteristic impedances.
In this case, the bandwidth will be limited by the
leakage alone, and a broadband balun can be obtained
by choosing lines B, C, E, and G with relatively high
impedance and A/4 length for the center frequency.
The balun achieves a transformation from 50 ohms to
twice 6.25 ohms without causing a standing wave in
the coaxial cables.
/"
'13 ,
'-../

13. The performance 0'

the Design 2 balun can
be calculated using Its equivalent circuit. The
calculated VSWR shows a response very close to the
simple coaxial balun (Fig. 10) because the new second
section has four times the bandwidth of the first
section. This design and its two companions are
intended to have octave bandwidths centered at 1.1
GHz, the central frequency used in distance measur-
ing equipment (DME, 1.025 to 1.150 GHz) and tactical
air navigation (TACAN, 0.960 to 1.215 GHz). For line
A:ZA = 50 ohms, LA = 1799 mils, " = 2.10; lines B,
C, E, and G: Z. = 30 ohms, L = 1799 mils, "ff = 2.23;
lines E and F: Zo = 25 ohms, L = 1799 mils", = 2.10.

249
 14. Two A/4 transformers '4
match the experImental two-
sectIon coaxIal balun's 6.26-
ohm impedance to the 50-ohm
load. Although these trans-
formers drastically reduce the
bandwidth (in terms of the
TI~'f)'Rri'("t1On ooluJI often used in the
VSWR), they don't affect the
JI)()-ffl-I,rXJ MHz rangf'. balance. SICONO
SfCTION
/4
fIllANa"oRMUI
MICRO.TR'"
LINEA ZIII::" so:, LA _ HI. MILS, ,ZI
Zc-.
15. The measured phase dIfference and meas- UNE .. :
LINED
LINE C Z. - lOl,.lll-. LC":119SMILS"_H-ZZ:J
LINE' lO:: l , - 2!i1 .. LO- L,'. 179!1MILS." -. ZI
ured InsertIon loss dIfference are plotted for the LINE ELINE G ZE -. Z(l":' 30 '. LE ::.. LO -;. 1719 MilS. 'eM' 223
LINEH LINEH' ZH"',:ZH': ZitoLr,L H ;-; LH'=.IOMILS"_H-' 223
two-sectIon coaxIal balun (Design 2). The max- LINE' LINE' 2,- Zr;" 17 "r,L,: If': 1712 MILS. 'e"': 2)0
imum unbalances for these two measurementsoverthe
octave bandwidth are 1 de~ree and 0.2 dB.

16. The calculated and measured values for the

Input VSWR for the DesIgn 2 balun show close
agreement between the experimental and predicted
~ ' 'r IS --I

performances. This indicates that the parasitic induc-

tors at the connections are negligible to at least 1.4 ~ . 'F·=----~=======11
GHz. Moreover, the balun has excellent balance to 1.4
GHz and achieves the 4:1 transformation without
causing a standing wave in the coaxial line. Despite

D~mits
=.
_eS_i_g_n_2_ba_l_u_n_s_,_th_e_n_ec_e_s_s_a_r,_'_c_oa_X_i_a_l_li_n_e_c_o_n_n_e_ct_i_on_. !: =~ ._=.".'~:'O
the many excellent qualities of thE Design 1 and "F : : I
'" , - - - I- - - - '_ _- - - ' - - - - - - - - - ' - _ " - - - - " - - - - - - - ' - - - - - - ' _

.
them to approximately 2 GHz. ,,', _ . . _ .

,,
. ,
./
,,

--'J . ,; i

. . ~: : : ,-". :~ -.-~:J
--------------;=""
I~

17. The problems associated wIth the previous

coaxial baluns can be reduced or eliminated by
using a balun that allows a microstrip coplanar
arrangement of the input and output lines, which
greatly simplifies the connections to the amplifier.
This balun'consists of an input line, A, connected in
series to three elements in the center of the half-
wavelength cavity: a reactive open-circuit stub, B, and
the Al4 output lines, C and D.

~.~
t
1 B. The equivalent circuit of the Design 3 coaxial
version balun shows lines C and D connected to place

rt ,;«':'f ~J.
their input signals in antiphase, thereby producing
two antiphase signals at their outputs. Transmission
/ lel801
line impedances and lengths are optimized to achieve

.."
d77
It/ ".00 iJ·
h ''''
the correct input/output transformation ratio and a
good match across the desired bandwidth. If only one
frequency or a narrow bandwidth is desired, and all
lengths are A/4, the matching condition Z.'/50 =
2Z;/R, will occur. In this case, ZE (Z.=Z.) and Z.
have no significance except for loss.

250
 19. The coplanar arrangement Input and output
lines can be accomplished with mlcrostrlp technol·
0' them by at least one line width. The middle conductor
carries the ground plane for the lines. To avoid
ogy. The uppermost conductor plane contains input radiation loss, the center conductor must extend at
line A, output lines C and D, and the open stub B. least one line width to either side of the upper plane
Coupling between these lines is avoided by separating circuit line. The balun resonant cavity is formed by
the region between the
f,;'\ middle and the lower con-
r"'"
I
\..:.:) ductor planes. A hole for
the cavity is cut in the
circuit fixture, filled with
dielectric, and covered
with the middle conductor
plane. The end-to-end
length of the cavity is nom-
inally a half.wavelength at
midband. To avoid dis-
turbance of the field dis-
tribution, the cavity width
must be at least three
times the width of the
middle conductor plane.
The arms of the balun cavi-
ty are folded to produce
two parallel and proximate
output transmission lines.
This configuration is more
t suited to coupling two
L D,~t~;~~,c transistors than the ori-
ginal layout in which the
L" ... p

-1
two outputs were on op·
posite sides (Fig. 17).

20. The Input equivalent circuit 'or the mlcroBtrlp

0'
~----'/_-"-.'''-~
version the DeBlgn 3 balun allows its theoretical
performance to be calculated. The design parameters
I shown provide a micros trip circuit that can be com-
pared with the coaxial baluns of Design 1 and Design
" 2. Transmission line A and lines C and D are loaded
by their characteristic impedances-in this case, 50
u ........ ili A -50
.\. ... _ ' ••• MIL'"eH_l10
LINI •• Z._ts- .L._1110MIL.".,,_2lJ
and 25 ohms. The cavity and the stub impose the
LlNICC 2Z,_lSl, .. lr_nUMIL".H:2lJ principal frequency limitation. The impedances of
LINIDD 22.,_500 •. lD_IS •• MIL. _,,_22l
these elements are dictated by the properties of the
II~ 2X 11.50' available dielectric substrates (glass-Teflon 0.020 and
'''PUT IQUIVALlNT CII.CUIT IDI15'Gfil 3 a.nu,. ) 0.0625 inches thick).

References
1. "35/50 Watt Broadband fl60-240
MHzl Push·Pull TV Amplifier Band III,"
'l'RW Application Note. TRW RF Semi-
conductor! Calal !WAN
2. "150 W 28
MHz. 13.5
Note. TRW Catalog
Na.9,faJl; l~~~Cation Note. on the
TPM·4100 (100 W, 100 - 400 MHz); the
t~~:= ftfo WW.l~d·~I~~~~ :~: fIllIQUINC., - aHI

l
TPV-5050 (SO W, UHF), available from THIOlillTlCAL IN"UT VSWIII OF MICRO'TIII"
.ALUN IDISION 31
TRW RF Semiconductors.

.
4. The tbe circuit
CT (Com-
Mierowave ~-----------------------.----~
).
S. Gordon J. L.u~hlin, "New
~~rJ:~-~:hec;E~ ~r::!lU!~,]!~ 21. The Input VSWR can be calculated based on
~~N[n~~hTf~6i.logy. Vol. the equivalent circuit 'or the mlcrostrlp balun. For
a one-octave bandwidth, the input VSWR is lower
than 1.75:1. This calculated performance is similar to
that of the two previous balun designs. The design
of the microstrip has theoretically perfect balance.

251
--~-----------------THREEBALUNSFORPUSH-PULLAMPS---------------------

22. The equivalent circuit of the mlcro.trlp balun

shows it during performance measurements with
>./16 matching lines. The experimental model uses
18-mil glass-Teflon (" =
2.55) for the tap circuits
and 62.5 mil glass-Teflon
for the cavity. Balance
properties were measured
with a 50-ohm system,
which was transformed to
LINE A Z.. ~\I. LA " " MilS..... .I 10
25 ohms by the M16 line- LINEa Z. ZlIll,la I.,DMILI ..... 223
section Chebyshev im- LINEr.LlNlf .IE
LlNEC,LlNID .Ie
.IF
20
17"1,1..
Z5',L C
IF 1712MIL5.,_"
LO '."MllS.,..,
.I 33
223
pedance transformers, LINI G, LINE" lG 2H 25". La LH '''<1 MltS.. .,. :I 23
A' III. 1:, . . . MILS'.n .I 07
which have a bandwidth LINE •• LINE J 2,
lINIK,lIN[l a"
zJ lJ

r,:; rhru=~!,'"~~d::::~r~~:/h(Ju'. from 0.960 to 1.215 GHz. ZL ZO!lul" Ll, •• :lMltS. eft 23'

23. The unbalance between output ports for a one-

octave bandwidth is shown in the measured 1.5-
degree maximum phase difference and 0.15-dB max-
imum insertion loss difference.

24. The central frequency Is 10 percent higher

than expected, but response is ciose to the calculated
values if relative frequency is considered. Ifthe output
transformers and their effect on input VSWR are
disregarded, an octave bandwidth with a maximum
input VSWR of around 2.0:1 can be ohtained. The 100-
MHz shift between the two curves may be caused by
the improper determination of the folded cavity's
electrical length. Similar calculation inaccuracies m'ay
arise from effects at the balun junction and from the

,::~
electrical length of the stub. As in the calculated
response, the experimental microstrip balun performs
comparably to the two coaxial designs.

25. The similarity In the performance of the three

balun designs within the considered frequency
bands indicates that the parasitic elements do not
significantly affect the theoretical properties. The
frequency limit is higher than 1.5 GHz for all three.
In the O.960-to-1.215-GHz bandwidth (TACAN and
DME applications), each performed with satisfactory
balance. The table compares the main characteristics
of the balun designs.
The phase differences (± 1.5 degrees) for all three
baluns are similar to those experienced with the
r'U.(~ ~j ~~ ~ ~ \I~( - - - - - - - - - - - - - - - : =
miniature 3-dB hybrid couplers that are normally
used to combine transistors for microwave balanced
amplifiers. But the insertion loss differences of the
Performance of the Three Balun Designs e
baluns are better-0.2 dB for a one-octave bandwidth Type of Balun Maximum experl- Theoretical
compared with 0.5 dB. balun loads, R mental unbalance InputVSWR
The physically simple microstrip balun eliminates (ohms) for one-octave for:
the connection problem inherent in coaxial designs: bandwidth
physical variances that breed standing waves and ~<P(0) ~MAG 960-12150ne-oc-
unbalance. Microstripping the transmission lines al- (dB) MHz tave
lows a designer to choose any value of characteristic band-
impedance of the lines. Consequently, the'microstrip width
balun is both more manageable and more controllable. Coaxial I 25 3 0.2 1.15:1 1.6:1
Since the balun load impedance will vary with (Design 1)
frequency, the best results will be obtained by simul- Coaxial II 6.25 0.2 1.15:1 1.6:1
taneously optimizing the balun parameters with those (Design 2)
of the matching network. The transistor's internal Microstrip 25 1.5 0.2 1.20:1 1.8:1
prematching network must be considered.·· (Design 3)

252
 AN1037
Solid State Power Amplifier
300WFM
88-108 MHz

INTRODUCTION
High efficiency multikilowat FM transmitters with full solid state amplifiers are possible today. The power
amplifier of these transmitters should be made by multiparalleling of a basic building block amplifier.
This building block should have a high output power and a high gain, a good collector efficiency, broad-
band (88-108 MHz) frequency response and a simple, reproducible and reliable circuit design. This
application note describes an FM building block amplifier that meets the requirements mentioned above
and that can be successfully incorporated to a number of amplifier architectures.
The amplifier has been developed with a pair of TP 9383 transistors in push-pull configuration. TP 9383
is a double diffused silicon epitaxial transistor that makes use of gold metallization and diffused ballast
resistors for long operationg life and ruggedness. Its basic specifications are :

Vee = 28 V 'l = 75 % at 108 M Hz and 150 W output power

G = 9 dB Po = 1 50 W
DESIGN CONSIDERATIONS

When designing an FM amplifier the total efficiency must be the first goal.

Overall efficiency is the combination of good collect efficiency and high gain. To get a good collector
efficiency the transistors must be operated in class C and the load impedance should match the transis-
tors output impedance at the operation power level. Class C amplifiers are non·linear units. The harmonic
content of the output signal of this type of amplifiers can be very high and their power wasted with an
important reduction in the efficiency.

253
 This fact made advantageous the use of balanced amplifiers. I n such circuit arrangement all the even
harmonic are largely suppressed and the waste of power minimized. Push-pull amplifiers have also the
additional advantages of connecting in series for RF operation the input and output impedance of the
2 transistors. That makes considerably easier to match the input and output impedances of the tran-
sistor pair. However. as the impedance transformation is lower. the RF power losses are smaller and
the gain and efficiency higher.

Another important consideration in the design of an FM amplifier is the ruggedness of the amplifier.
FM transmitters are often operated 24 hours per day and sometimes remotly controlled and in difficult
access sites. The operating point of the transistors should be chosen in a conservative way and the
heat properly evacuated. A thermo switch should be incorporated to the system. The amplifier must
also be able to withstand output VSWR. Although all transmitters use to incorporate VSWR protection
in their interlocky systems. the amplifier must be designed with the capability of supporting VSWR of
3.1 as a minimum. This point can be very determinent when considering that on a high efficiency circuit
the collector voltage swing can be close to 3 times the collector supply voltage.

CIRCUIT DESCRIPTION

Circuit schematic is given in the Figure 1. At the amplifier input there is a two section balun. The first
section. L,. consists of a short lenght ("" ,,/20) of 50 Q coaxial semirigid cable. The outer conductor
of the coaxial cable is grounded at the input side and floats at the output.

The second section of the balun consists of two identical coaxial cables. L2 and LJ • of the same length
that L. but with 25 Q characteristic impedance. The ends of these two coaxials are interconnected in
series at the input side (thus offering 50 ~l impedance to L,) and in parallel at the output of the section.
The combined balanced impedance will be therefore 12.5 Q at the output of the balun. The input impe-
dance of the transistor pair 0, and O 2 is transformed to 12.5 Q (2 x 6.25) with the LC network repre-
sented in the schematic.
If this balun is well charged by 2 x 6.25 Q it is well capable of multioctave operation. However in this
case the LC network that transform the impedances of the transistor pair has been optimized only bet-
ween 88 and 108 MHz . .

A similar balun circuit is used at the output of the amplifier. The main difference with the input balun
is that the coaxial cables are also used in the collect biasing circuit. Care has been taken with the decou-
piing of the collect bias in order to avoid low frequency oscillations. The collect impedance is higher
than the base impedance and therefore the LC output transforming network is very simp Ie. only L •• L.
and C,.

L1

I I 1 I I
88-108 MHz; 300 W 28 V

Figure 1. FM Broadband Power Amplifier

254
 COMPONENTS LIST

C, = 120 + 80 pF Chip capacitor ATC 100 B

C, = 220 pF Chip capacitor ATC 100 B
C,. C•• C,. C. = 470 pF Chip capacitor ATC 100 B !
C, = 100 pF Chip capacitor ATC 100 B 8
Cs = 27 pF Chip capacitor ATC 100 B
C•• C,o. CII' C,. = 1 000 pF Disc capacitor
....,.
c;
C". CIS = 10 nF ..,"
C". C, •• CIS = 0.1 ,...F .
C 17 = 1 000 fJ.F /63 V Electrolytic !
= 50 n coaxial cable 2J 3.2 mm (Teflon) L = 110 mm
= 25 U coaxial cable 0 3.2 mm (Teflon) L = 110 mm
L. L, = Hair pin: copper foil 18 x 3 mm 0.3 mm thickness
L•. L, = Line on substrate: 15 x 5 mm
L•. L. = Line on substrate: 10 x 5 mm
L,o. L" = 25 0 coaxial cable 0 5 mm (Teflon) L = 110 mm
L" = 50 U coaxial cable;) 5 mm (Teflon) L = 110 mm
L" = 15 turns 0 8 mm 1,4 mm wire

R,.R, =2201/2W
R, = 47 U 2 W

0,.0, = TP 9383

300 W PUSH-PULL FM TP 9383

...
300
I, 35
1I ::l
IL
z

--
Figure 2. Component Layout
I
:-- t-- 2il~_ ~
1
I I I'Ie r-- 80~
>

I J <if ~ I U
..- -r-... :E 10 70 i!i
Pin = z
:;;:
GAIN
I
I , co

~I
<::J 60~
u
= 28V- ~ = 28 V
VCE <::J VCE
t-- 50~
Pout = 300W 8
I
100 110 90 100 110
#
90
f. FREQUENCY IMHzl f. FREQUENCY (MHz)
Figure 3. Output Power versus Input Power and Frequency Figure 4. Gain and Efficiency versus Frequency

255
256
 AN1039
470-860 MHz
Broadband Amplifier
5W

5 W UHF TV TRANSPOSER AMPLIFIER

WITH TWO TPV 593 TRANSISTORS

INTRODUCTION

This application note describes an ultralinear broadband (470-860 MHz) amplifier, developed for TV
transposer applications. The amplifier incorporates two TPV 593 transistors.
Each transistor is used to build a separate broadband amplifier. The two identical amplifiers are later
combined with 3 dB hybrids.

The TPV 593 transistor has been developed for TV class A application. It incorporates gold metallization
and diffused ballast resistors for ruggedness and linearity. Its DC current consumption is very low and
makes it a good candidate for solar cell powered systems. Its basic specifications are:

Vee ; 25 V Ie ; 450 mA
G ; 9 dB at 860 MHz
IMD ; -- 60 dB at 860 MHz and 2 W output

The S parameters of the TPV 593 are given in the table below.

POLAR S-PARAMETERS IN 50.0 OHM SYSTEM

FREO. Sll S21 S12 S22 S21 K

(MAGN ANGL) (MAGN ANGL) (MAGN ANGL) (MAGN ANGL) dB FACT

470.00 0.93 170 1.50 63.0 0.040 50.0 0.55 -166 3.52 1.01
650.00 0.93 165 1.06 50.0 0.050 54.0 0.60 -169 0.51 1.04
860.00 0.92 162 0.79 38.0 0.056 54.0 0.65 -169 - 2.00 1.15

257
 POLAR COORDINATES OF SIMULTANEOUS CONJUGATE MATCH

F SOURCE REFL. COEFF. LOAD REFL. COEFF. Gmax

MHz MAGN. ANGLE MAGN. ANGLE dB

470.0 0.99 -173 0.91 124 15.23

650.0 0.97 -16B 0.83 134 12.01
860.0 0.95 - 165 0.79 146 9.16

DESIGN CONSIDERATIONS

Two identical single transistor class A amplifiers will be combined with 3 dB couplers. First the design
of a single amplifier will be considered.

From the analysis of the variation of the TPV 593 S21 parameter with the frequency it may be seen that
there is a difference of 5.52 dB between 470 and 860 MHz. If a flat gain is required this gain slope has
to be compensated. The compensation can be implemented in two ways:

a) By placing a selective attenuator at the input of the transistor amplifier, with an insertion loss minimum at
860 MHz and which increases to 5.52 dB at 470 MHz. The insertion loss increase should compensate the
transistor gain slope.

b) By selective mismatch at the input of the transistor. The input circuit will provide impedance matching at 860
MHz, in order to get a gain as close as possible to the GA max. Frequency dependent mismatch will compensate
the gain slope. At 470 MHz a VSWR as high as 11:1 will be necessary. It has been proved that impedance
mismatch at the base terminal of a transistor power amplifier does not modify the linearity behavior of the
device.
As it was decided to combine two amplifiers with 3 dB couplers the method b) was selected. 50 ohms
3 dB hybrid couplers when used with two identical loads provide a good VSWR at the common termi-
nal even if the loads differ from 50 ohms. The reflected energy is dissipated as the 50 ohms load connec-
ted to the fourth terminal of the coupler. The coupler behaves as a selective attenuator. Figure 1 shows
the amplifier arrangement. The use of a 3 dB coupler to split the input signal makes almost compulsory
the use of the same type of circuit at the output.

IN
I I
II
I I
II
SAGE II
WIRELINE x
( I
3dB Hybrid It
I I
1=70mm
I I
OUT

Figure 1. Block Diagram of Amplifier

The amplifier must be as. linear as possible over the complete UHF band. A transistor power amplifier
usually requires impedance matching at the collector side for optimum intermodulation. Therefore the
output circuitry has been designed for impedance matching all over the bands IV and V.

258
 COMPONENTS PART LIST

L, 65 line 11 % g at 860 MHz

L, 50 line 1.5 % gat 860 MHz
L, 50 line 17 % g at 860 MHz
L,

L,
-
7 turns ID 2 mm - Closely Wound - wire 5 mm

10 mr; : 5 mm wire 1 mm

C,-C, Variable Airtronic AT 7275 .. 8-4.5 pF

C, 6.8 pF ATC 100A
C,-C, 10 pF ATC 100A
C.-C, 1 nF + 10 nF + 1/l + 10 /IF

Board Material: 1/16" Teflon Fiberglass

CIRCUIT DESCRIPTION
The circuit of a simple amplifier is given in
Figure 2.

r-----~----_.------~-------- VeE

fN
L3

lOUT
lnF

Figure 2. Circuit Schematic

4,4Il 2 IV The input circuit consist of a three section low pass

V suppl y
type matching network. To minimize power losses
all the impedance transformations are made at a
low Q level. Variable capacitor C1 is adjusted for
optimum VSWR at 860 MHz. The tuning is straight
forward and only a small retouch is necessary
after the collector tuning.
The very constant S22 of the TPV 593 transistor
c 680 Il makes extremely simple to match the collector to
a 50 ohms load. L8 tunes the output capacitance
of the device and is determined for good matching
at the low end of the band. Only one low pass
section is necessary. Capacitor C5. variable.
2m allows a good shaping of the output VSWR. Col-
4,7 K lector tuning should be done after tuning the
input.
The bias control circuitry is classical and is given
in Figure 3.

Figure 3. Class A Bias Circuit

259
 CONSTRUCTIONAL DETAILS

The printed circuit board lay-out of the complete amplifier is given in Figure 4. Considerate attention should be
paid to the ground returns. Plated through holes have been used to ensure low emitter inductance. Wrapped
foils ensure proper grounding of parallel capacitors and connectors.
The couplers have been made with parallel wire cable.
This solution is as inexpensive as a straight forward.

9 ._-/' ~ "i·.J-
~
f-! __ GAIN
---,..
~ r- t .
;z
<i' r---j -- l>;ei = 4 W - - - - r - - - - - - - "---~ <ii
'"ao f-, , . - - - -10;;;
~ 8 1---+--1---1---- 9
IN ~ z
~ '"
~
'" '"
20 ci

500 600 700 800 860

f. FREQUENCY (MHzl

Figure 5. Gain and Return Loss versus Frequency

~ -50
z
o Pref = 6 W
~ ~~~ri:------~_~~-~~--I
~ ......
15
z Pref = 4W ----- ----
o
~
5o
_ 60
..
~ _-t--~-~~-!~L- ._
--7"'-----1

1l!
~
~

~ -70
~-4---+---------

500 600 700 800 860

_Return ground
f. FREQUENCY (MHzl
Figure 4. Printed Circuit Board Layout
Figure 6. Intermodulation Distortion versus Frequency

260
 Figure 7. Output Power versus Input Power Figure 8. Vision to Sound Cross Modulation
f = 470 MHz
I Z 18
I
12 z ---
! 10
,
r-
.... I
I o
~ 14
1 -- ~
~
>-
::>
8
I

I . . . . ~. . .-I-+
Io---
I--~- _.. -+-
15
o
~ 10
I-- t t-

~
"7
V
~ l~ --- ._--+--
o .... k'
-r- ~ 1--1-2 ~
t-jTr--
u
1
rf+-
S 2 -~
'" 6
0': ~.
z
::> -
o --_. --- t-- -- --
i '"oZ 2
in
:>
Pin. INPUT POWER [WI Pout. VISION (WI

f = 650 MHz
it.. 18

~
ffi
~
121--+-+-+
10

8
z
o
~
::>
o'"
14 ~~-t
r-+-----t - - x:
. -Tl/r
- I I
L J.t_ :

>-
::>
I--~+-----,.-c-­ ""
~ 10 I-- 1--'- V I
~ ~ -t-
~t}
4 I---r--¥-- u
o
~ 6 ~
l-
J ::>
55
z
o I I
in
:>
Pin. INPUT POWER IWI Pout. VISION (WI

f = 860 MHz

12 I ! I IJ ~ 18 t-- I I I lL
~ I I ~-~~r-~~~
! 10 I I I
J.-t-
1 14
!
~ t--I-- --+--~lr, -+-t----t--t--
!
~ 8 I .... ~...... ~ 10 t--I--t---- r- J
>-
v· ------t-~

.'
::>
~ 4
---+-----r--
I
5 ./ - ----jf----t--r--t--r- t--
~ 6 """"'~--+--J-rl-+-I -+--+J-_+---It- t--t--
::> I !
o

l/ i
I J Il-+--j
tt 55
is 2 iii
---+--;

II
'"
:>
Pin. INPUT POWER IWI Pout. VISION [WI

NOTE: .1% of sound carrier (-7 dB) when vision carrier is switch ON/OFF

261
MEASUREMENTS
The measurements results have been summarized in Table 2.
Figure 5 shows the frequency response of the amplifier as well as the input and output match. Figure 6 displays
the linearity (lMD test; -8, -16, -7 dB) of the amplifier. Static transfer curves are given in the Figures 7 and 8
that show also the vision to sound cross modulation of the amplifier.

Table 2 TYPICAL RESULTS

BANDWIDTH : 470 860 MHz IMD : SOUND REF - 7 dB
GAIN :87dBmln VISION REF 8 dB
IMDOat 4W - 58 dB SIDEBAND REF - 16 dB
- 5 W 56 dB
INPUT RETURN LOSS 16 dB
OUTPUT RETURN LOSS: 17 dB
BIAS CONDITIONS 25 V 2 • 450 mA
CONCLUSION
A high performance amplifier has been described as an example of the possibilities offered to the desi-
gner by the TPV 593. In particular the amplifier combines excellent frequency response and linearity
with high efficient use of the DC power. This circuit may be of interest for output stages of low power
TV transposers or drivers of higher power units.

262
 AN1040
Mounting Considerations for Power
Semiconductors
Prepared by Bill Roehr
Staff Consultant, Motorola Semiconductor Sector

TABLE OF CONTENTS

Introduction . . . . . . . . . . . . . . . . . . . . . . 1 Connecting and Handling Terminals 14

Mounting Surface Preparation . . . . . . . . . . . . 2 Cleaning Circuit Boards. . . . . . . . . . . . . . . . 16
Interface Decisions . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal System Evaluation. . . . . . . . . . . . . 16
Insulation Considerations . . . . . . . . . . . . . . . . . . . 4 Appendix A Thermal Resistance Concepts. . . 17
Fastener and Hardware Characteristics .. 7 Appendix B Measurement of Interface. . . . . . . . .. 18
Fastening Techniques . . . . . . . . . . . . . . 8 Appendix C Sources of Accessories. . . . . . . . . . .. 19
Free Air and Socket Mounting ....... . 13 Package Index. . . . . . . . . . . . . . . . . . . . . . . . . .. 20

INTRODUCTION Figure 1 shows an example of doing nearly everything

wrong. A tab mount TO-220 package is shown being used
Current and power ratings of semiconductors are inse- as a replacement for a TO-213AA (TO-66) part which was
parably linked to their thermal environment. Except for socket mounted. To use the socket, the leads are bent-
lead-mounted parts used at low currents, a heat exchan- an operation which, if not properly done, can crack the
ger is required to prevent the junction temperature from package, break the internal bonding wires, or crack the
exceeding its rated limit, thereby running the risk of a die. The package is fastened with a sheet-metal screw
high failure rate. Furthermore, the semiconductor indus- through a 1/4" hole containing a fiber-insulating sleeve.
try's field history indicated that the failure rate of most The force used to tighten the screw tends to pull the
silicon semiconductors decreases approximately by one- package into the hole, possibly causing enough distortion
half for a decrease in junction temperature from 160'C to to crack the die. In addition the contact area is small
135'C.(1) Guidelines for designers of military power sup- because of the area consumed by the large hole and the
plies impose a 110'C limit upon junction temperature.!2) bowing of the package; the result is a much higher junc-
Proper mounting minimizes the temperature gradient tion temperature than expected. If a rough heatsink sur-
between the semiconductor case and the heat exchanger. fa.ce and/or burrs around the hole were displayed in the
Most early life field failures of power semiconductors illustration, most but not all poor mounting practices
can be traced to faulty mounting procedures. With metal would be covered.
packaged devices, faulty mounting generally causes
unnecessarily high junction temperature, resulting in
reduced component lifetime, although mechanical dam- PLASTIC BOOY
age has occurred on occasion from improperly mounting
to a warped surface. With the widespread use of various
plastic-packaged semiconductors, the prospect of
mechanical damage is very Significant. Mechanical dam-
age can impair the case moisture resistance or crack the
semiconductor die.

(1) MIL·HANDBOOK - 2178. SECTION 2.2.

(2) "Navy Power Supply Reliability - Design and Manufacturing
Guidelines" NAVMAT P4855-1, Dec. 1982 NAVPUBFORCEN, 5801
Tabor Ave., Philadelphia, PA 19120.

Cho- Therm is a registered trademark of Chromerics. Inc.

Grafoil is a registered trademark of Union Carbide
Kapton is a registered trademark of E,!' Dupont Figure 1. Extreme Case of Improperly Mounting
Rubber-Due is a trademark of AAVID Engineering A Semiconductor (Distortion Exaggerated)
Sil Pad is a trademark of Berquist
Sync-Nut is a trademark of 1M Shakeproof
Thermasil is a registered trademark and Thermafilm is a trademark of Thermalloy, Inc.
ICePAK, Full Pak, POWERTAP and Thermopad are trademarks of Motorola, Inc.

263
 In many situations the case of the semiconductor must
be electrically isolated from its mounting surface. The TIR = TOTAL INDICATOR READING
isolation material is, to some extent, a thermal isolator
as well, which raises junction operating temperatures. In
addition, the possibility of arc-over problems is intro-
duced if high voltages are present. Various regulating
agencies also impose creepage distance specifications
which further complicates design. Electrical isolation
thus places additional demands upon the mounting
procedure.
Proper mounting procedures usually necessitate DEVICE MOUNTING AREA
orderly attention to the following:
1. Preparing the mounting surface
2. Applying a thermal grease (if required)
Figure 2. Surface Flatness Measurement
3. Installing the insulator (if electrical isolation is
desired)
4. Fastening the assembly
tance. Tests conducted by Thermalloy using a copper
5. Connecting the terminals to the circuit
TO-204 (TO-3) package with a typical 32-microinch finish,
In this note, mounting procedures are discussed in gen· showed that heatsink finishes between 16 and 64 win
eral terms for several generic classes of packages. As caused less than ± 2.5% difference in interface thermal
newer packages are developed, it is probable that they resistance when the voids and scratches were filled with
will fit into the generic classes discussed in this note. a thermal joint compound.(3) Most commercially avail-
Unique requirements are given on data sheets pertaining able cast or extruded heatsinks will require spotfacing
to the particular package. The following classes are when used in high-power applications. In general, milled
defined: or machined surfaces are satisfactory if prepared with
Stud Mount tools in good working condition.
Flange Mount
Pressfit Mounting Holes
Plastic Body Mount Mounting holes generally should only be large enough
Tab Mount to allow clearance of the fastener. The larger thick flange
Surface Mount type packages having mounting holes removed from the
Appendix A contains a brief review of thermal resis· semiconductor die location, such as the TO-3, may suc-
tance concepts. Appendix B discusses measurement dif- cessfully be used with larger holes to accommodate an
ficulties with interface thermal resistance tests. Appendix insulating bushing, but many plastic encapsulated pack-
C indicates the type of accessories supplied by a number ages are intolerant of this condition. For these packages,
of manufacturers. a smaller screw size must be used such that the hole for
the bushing does not exceed the hole in the package.
Punched mounting holes have been a source oftrouble
MOUNTING SURFACE PREPARATION
because if not properly done, the area around a punched
hole is depressed in the process. This "crater" in the
In general, the heatsink mounting surface should have
heatsink around the mounting hole can cause two prob·
a flatness and finish comparable to that of the semicon-
lems. The device can be damaged by distortion of the
ductor package. In lower power applications, the heatsink
package as the mounting pressure attempts to conform
surface is satisfactory if it appears flat against a straight
it to the shape of the heatsink indentation, or the device
edge and is free from deep scratches. In high-power
may only bridge the crater and leave a significant per·
applications, a more detailed examination of the surface
centage of its heat-dissipating surface out of contact with
is required. Mounting holes and surface treatment must
the heatsink. The first effect may often be detected imme-
also be considered.
diately by visual cracks in the package (if plastic). but
usually an unnatural stress is imposed, which results in
Surface Flatness
an early-life failure. The second effect results in hotter
Surface flatness is determined by comparing the var·
operation and is not manifested until much later.
iance in height (t.h) of the test specimen to that of a
Although punched holes are seldom acceptable in the
reference standard as indicated in Figure 2. Flatness is
relatively thick material used for extruded aluminum
normally specified as a fraction of the Total Indicator
heatsinks, several manufacturers are capable of properly
Reading (TIR). The mounting surface flatness, i.e, t.h/TIR,
utilizing the capabilities inherent in both fine-edge blank-
if less than 4 mils per inch, normal for extruded alumi-
ing or sheared-through holes when applied to sheet
num, is satisfactory in most cases.
metal as commonly used for stamped heatsinks. The
holes are pierced using Class A progressive dies mounted
Surface Finish
on four-post die sets equipped with proper pressure pads
Surface finish is the average of the deviations both
above and below the mean value of surface height. For and holding fixtures.
minimum interface resistance, a finish in the range of 50
to 60 microinches is satisfactory; a finer finish is costly (3) Catalog #B7·HS·9 (19Bn page B, Thermelloy, Inc., P.O. Box Bl0B39,
to achieve and does not significantly lower contact resis- Dallas, Texas 75381-0839.

264
 When mounting holes are drilled, a general practice very thin layer using a spatula or lintless brush, and
with extruded aluminum, surface cleanup is important. wiped lightly to remove excess material. Some cyclic
Chamfers must be avoided because they reduce heat rotation of the package will help the compound spread
transfer surface and increase mounting stress. However, evenly over the entire contact area. Some experimenta-
the edges must be broken to remove burrs which cause tion is necessary to determine the correct quantity; too
poor contact between device and heatsink and may punc- little will not fill all the voids, while too much may permit
ture isolation material. some compound to remain between well mated metal
Surface Treatment surfaces where it will substantially increase the thermal
resistance of the joint.
Many aluminum heatsinks are black-anodized to
To determine the correct amount, several semicon-
improve radiation ability and prevent corrosion. Anod-
ductor samples and heatsinks should be assembled with
izing results in significant electrical but negligible thermal
different amounts of grease applied evenly to one side
insulation. It need only be removed from the mounting
of each mating surface. When the amount is correct a
area when electrical contact is required. Heatsinks are
very small amount of grease should appear around the
also available which have a nickel plated copper insert
under the semiconductor mounting area. No treatment perimeter of each mating surface as the assembly is
slowly torqued to the recommended value. Examination
of this surface is necessary.
Another treated aluminum finish is iridite, or chromate- of a dismantled assembly should reveal even wetting
acid dip, which offers low resistance because of its thin across each mating surface. In production, assemblers
surface, yet has good electrical properties because it should be trained to slowly apply the specified torque
resists oxidation. It need only be cleaned of the oils and even though an excessive amount of grease appears at
films that collect in the manufacture and storage of the the edges of mating surfaces. Insufficient torque causes
sinks, a practice which should be applied to all heatsinks. a significant increase in the thermal resistance of the
For economy, paint is sometimes used for sinks; interface.
To prevent accumulation of airborne particulate matter,
removal ofthe paint where the semiconductor is attached
is usually required because of paint's high thermal resis- excess compound should be wiped away using a cloth
tance. However, when it is necessary to insulate the semi- moistened with acetone or alcohol. These solvents
conductor package from the heatsink, hard anodized or should not contact plastic-encapsulated devices, as they
painted surfaces allow an easy installation for low voltage may enter the package and cause a leakage path or carry
applications. Some manufacturers will provide anodized in substances which might attack the semiconductor
or painted surfaces meeting specific insulation voltage chip.
requirements, usually up to 400 volts. The silicone oil used in most greases has been found
It is also necessary that the su rface be free from all to evaporate from hot surfaces with time and become
foreign material, film, and oxide (freshly bared aluminum deposited on other cooler surfaces. Consequently, man-
forms an oxide layer in a few seconds). Immediately prior ufacturers must determine whether a microscopically
to assembly, it is a good practice to polish the mounting thin coating of silicone oil on the entire assembly will
area with No. 000 steel wool, followed by an acetone or pose any problems. It may be necessary to enclose com-
alcohol rinse. ponents using grease. The newer synthetic base greases
show far less tendency to migrate or creep than those
made with a silicone oil base. However, their currently
INTERFACE DECISIONS observed working temperature range are less, they are
When any significant amount of power is being dissi- sl.ightly poorer on thermal conductivity and dielectric
pated, something must be done to fill the air voids strength and their cost is higher.
between mating surfaces in the thermal path. Otherwise Data showing the effect of compounds on several pack-
the interface thermal resistance will be unnecessarily age types under different mounting conditions is shown
high and quite dependent upon the surface finishes. in Table 1. The rougher the surface, the more valuable
For several years, thermal joint compounds, often the grease becomes in lowering contact resistance;
called grease, have been used in the interface. They have therefore, when mica insulating washers are used, use
a resistivity of approximately 60'ClWlin whereas air has of grease is generally mandatory. The joint compound
1200'ClWlin. Since surfaces are highly pock-marked with also improves the breakdown rating of the insulator.
minute voids, use of a compound makes a significant
reduction in the interface thermal resistance of the joint. Conductive Pads
Because of the difficulty of assembly using grease and
However, the grease causes a number of problems, as
discussed in the following section. the evaporation problem, some equipment manufactur-
To avoid using grease, manufacturers have developed ers will not, or cannot, use grease. To minimize the need
dry conductive and insulating pads to replace the more for grease, several vendors offer dry conductive pads
which approximate performance obtained with grease.
traditional materials. These pads are conformal and
Data for a greased bare joint and a joint using Grafoil, a
therefore partially fill voids when under pressure.
dry graphite compound, is shown in the data of Figure
Thermal Compounds (Grease) 3. Grafoil is claimed to be a replacement for grease when
Joint compounds are a formulation of fine zinc or other no electrical isolation is required; the data indicates it
conductive particles in a silicone oil or other synthetic does indeed perform as well as grease. Another conduc-
base fluid which maintains a grease-like consistency with tive pad available from Aavid is called KON-DUX. It is
time and temperature. Since some of these compounds made with a unique, grain oriented, flake-like structure
do not spread well, they should be evenly applied in a (patent pending). Highly compressible, it becomes

265
 Table 1
Approximate Values for Interface Thermal Resistance Data from Measurements Performed
in Motorola Applications Engineering Laboratory
Dry interface values are subject to wide variation because of extreme dependence upon surface conditions. Unless
otherwise noted the case temperature is monitored by a thermocouple located directly under the die reached through
a hole in the heatsink. (See Appendix'B for a discussion of Interface Thermal Resistance Measurements.)

Package Type and Data Interface Thermal Resistance ("CIW)

Test
Metal-to-Metal With Insulator
JEOEC Torque See
Outlines Description In-Lb Dry Lubed Dry Lubed Type Note
DO-203AA, TO-210AA 10-32 Stud 15 0.3 0.2 1.6 0.8 3 mil
TO-208AB 7/16" Hex Mica
DO-203AB, TO-210AC 1/4-28 Stud 25 0.2 0.1 0.8 0.6 5mil
TO-208 11/16" Hex Mica
DO-208AA Pressfit, 112" - 0.15 0.1 - - -
TO-204AA Diamond Flange 6 0.5 0.1 1.3 0.36 3 mil 1
(TO-31 Mica
TO-213AA Diamond Flange 6 1.5 0.5 2.3 0.9 2 mil
(TO-66) Mica
TO-126. Thermopad 6 2.0 1.3 4.3 3.3 2 mil
114" x 3/8" Mica
TO-220AB Thermowatt 8 1.2 1.0 3.4 1.6 2 mil 1,2
Mica
NOTES. 1. See Figures 3 and 4 for additional data on TO 3 and TO 220 packages "

2. Screw not insulated. See Figure 12.

formed to the surface roughness of both the heatsink and such as mica, have a hard, markedly uneven surface. With
semiconductor. Manufacturer's data shows it to provide many isolation materials reduction of interface thermal
an interface thermal resistance better than a metal inter- resistance of between 2 to 1 and 3 to 1 are typical when
face with filled silicone grease. Similar dry conductive grease is used.
pads are available from other manufacturers. They are a Data obtained by Thermalloy, showing interface resis-
fairly recent development; long term problems, if they tance for different insulators and torques applied to
exist, have not yet become evident. TO-204 (TO-3) and TO-220 packages, are shown in Figure
3, for bare and greased surfaces. Similar materials to
INSULATION CONSIDERATIONS those shown are available from several manufacturers.
It is obvious that with some arrangements, the interface
Since most power semiconductors use are vertical thermal resistance exceeds that of the semiconductor
device construction it is common to manufacture power (junction to case).
semiconductors with the output electrode (anode, col- Referring to Figure 3, one may conclude that when high
lector or drain) electrically common to the case; the prob- power is handled, beryllium oxide is unquestionably the
lem of isolating this terminal from ground is a common best. However, it is an 'expensive choice. (It should not
one. For lowest overall thermal resistance, which is quite be cut or abraided, as the dust is highly toxic:) Thermafilm
important when high power must be dissipated, it is best is a filled polyimidematerial which is used for isolation
to isolate the entire heatsink/semiconductor structure (variation of Kapton). It is a popular material for low
from ground, rather than to use an insulator between the power applications because of its low cost ability to with-
semiconductor and the heatsink. Heatsink isolation is not stand high temperatures, and ease of handling in contrast
always possible, however, because of EMI requirements, to mica which chips and flakes easily.
safety reasons, instances where a chassis serves as a A number of other insulating materials are also shown'.
heatsink or where a heatsink is common to several non- They cover a wide range of insulation resistance, thermal
isolated packages. In these situations insulators are used resistance and ease of handling. Mica has been widely
to isolate the individual components from the heatsink. used in the past because it offers high breakdown voltage
Newer packages, such as the Motorola Full Pak and EMS and fairly low thermal resistance at a low cost but it cer-
modules, contain the electrical isolation material within, tainly should be used with grease.
thereby saving the equi'pment manufacturer the burden Silicone rubber insulators have gained favor because
of addressing the isolation problem. they are somewhat conformal under pressure, Their abil-
ityto fill in most ofthe metal voids atthe interface reduces
Insulator Thermal Resistance the need for thermal grease. When first introduced, they
When an insulator is used, thermal grease is of greater suffered from cut-through after a few,years in service.
importance than with a metal-to-metal contact, because The ones presently available have solved this problem
two interfaces exist instead of one and some materials, by having imbedded pads of Kapton or fiberglass. By

266
 1

--- -
8
f-"'-
r {ll Thermalfilm •. 002 (.05) thick. ,
1
1
= - I 21
131
141
(2) Mica•. 003 (.08) thick.
(3) Mica•. 002 (.05) thick.
(4) Hard anodized •. 020 (.511 thick.
f51 (5) Aluminum oxide•. 062 (, .57) thick.
6

5 --- 111

6 - I-- 16)
(6) Beryllium oxide•. 062 (1.57) thick.
(7) Bare ioint - no finish.
(8) Grafoil. .005 1.13) thick.o- J
::,-

:--..
1
1

-
17) -Grafoil IS not an msulating material 1
1
,161
181
1
"
0 0
4 5 6
MOUNTING SCREW TOROUE IIN-lBSI MOuNTING SCREW TORQUE '1~·l8SI
I I I I I I I I I I I I
72 145 217 290 362 435 72 145 217 290 362 435
INTERFACE PRESSURE IpSI) INTERFACE PRESSURE 'ps"

3a. TO-204AA (TO-3) 3b. TO-204AA (TO-3)

Without Thermal Grease With Thermal Grease

----
4 (1) Thermalfilm •. 022 (.05) thick
~- 121 (2) Mica •. 003 (.08) thick.
- I 31 (3) Mica, .002 (,05) thick.
14) (4) Hard anodized •. 020 (.51) thick
(5) Thermalsilli .. 009 (.23) thick.
(6l Thermalsillll •. 006 {.15l thick.

1
- 101

,~:(71
1
(7) Bare joint - no finish.
(8) Grill.oil •. 005 (,13) thick"
·Grafoll IS not an insulating mater,al

0
, 2 liNUS) 4 5 4
MOUNTING SCREW TOROUE MOLJr"IITlf'.IG SCREW TORQuE
IIN·LBSI I"HBS,

3c. TO-220 3d. TO-220

Without Thermal Grease With Thermal Grease

Figure 3. Interface Thermal Resistance for TO-204, TO-3 and TO-220 Packages using Different Insulating Materials
as a Function of Mounting Screw Torque (Data Courtesy Thermalloy)

comparing Figures 3c and 3d, it can be noted that Ther- Table 2. Thermal Resistance of Silicone Rubber Pads
masil, a filled silicone rubber, without grease, has about
RIICS (a RIICS Cn
the same interface thermal resistance as greased mica Manufacturer Product 3 Mils* 7.5 Mils'
for the TO-220 package.
Wakefield Delta Pad 173-7 .790 1.175
A number of manufacturers offer silicone rubber insu-
Bergquist Sil Pad K-4 .752 1.470
lators. Table 2 shows measured performance of a number
Stockwell Rubber 1867 .742 1.015
of these insulators under carefully controJled, nearly Bergquist Sil Pad 400-9 .735 1.205
identical conditions. The interface thermal resistance Thermalloy Thermalsil II .680 1.045
extremes are over 2: 1 for the various materials. It is also Shin-Etsu TC-30AG .664 1.260
clear that some of the insulators are much more tolerant Bergquist 5il Pad 400·7 .633 1.060
than others of out-of-flat surfaces. Since the tests were Chomerics 1674 .592 1.190
performed, newer products have been introduced. The Wakefield Delta Pad 174-9 .574 .755
Bergquist K-10 pad, for example, is described as having Bergquist Sil Pad 1000 .529 .935
about 2/3 the interface resistance of the Sil Pad 1000 Ablestik Thermal Wafers .500 .990
which would place its performance close to the Chom- Thermalloy Thermalsil III .440 1.035
Chomerics 1671 .367 .655
erics 1671 pad. AAVID also offers an isolated pad caJled
*Test Fixture DeViation from flat from Thermalloy EIR86-1010.

267
Rubber-Due, however it is only available vulcanized to a The conclusions to be drawn from all this data is that
heatsink and therefore was not included in the compar- some types of silicon rubber pads, mounted dry, will out
ison. Published data from AAVID shows ROCS below perform the commonly used mica with grease. Cost may
0.3°CIW for pressures above 500 psi. However, surface be a determining factor in making a selection.
flatness and other details are not specified so a compar-
ison cannot be made with other data in this note. Insulation Resistance
When using insulators, care must be taken to keep the
The thermal resistance of some silicone rubber insu-
lators is sensitive to surface flatness when used under a mating surfaces clean. Small particles of foreign matter
can puncture the insulation, rendering it useless or seri-
fairly rigid base package. Data for a TO-204AA (TO-3)
ously lowering its dielectric strength. In addition, partic-
package insulated with Thermasil is shown on Figure 4.
ularly when voltages higher than 300 V are encountered,
Observe that the "worst case" encountered (7.5 mils)
problems with creepage may occur. Dust and other for-
yields results having about twice the thermal resistance
eign material can shorten creepage distances signifi-
of the "typical case" (3 mils), for the more conductive
cantly; so having a clean assembly area is important.
insulator. In order for Thermasil III to exceed the perfor-
Surface roughness and humidity also lower insulation
mance of greased mica, total surface flatness must be
resistance. Use of thermal grease usually raises the with-
under 2 mils, a situation that requires spot finishing.
stand voltage of the insulation system but excess must
be removed to avoid collecting dust. Because of these
factors, which are not amenable to analysis, hi-pot testing
12 should be done on prototypes and a large margin of
safety employed.
~
'-'
iVl /.
VI21 Insulated Electrode Packages
Because of the nuisance of handling and installing the
t'j
z 0.8
V / accessories needed for an insulated semiconductor
~ V mounting, equipment manufacturers have longed for
~
~ 0.6 '-'" V
V cost-effective insulated packages since the 1950's. The
first to appear were stud mount types which usually have
<t
V a layer of beryllium oxide between the stud hex and the
~ V can. Although effective, the assembly is costly and
'~"
t'j

~
~
0.4

0.2 r-
-V
:~: ~~:;~::::: ::i. °00096'~nCchheeSs \2,35 :~,\h~~ckk -
requires manual mounting and lead wire soldering to
terminals on top of the case. In the late eighties, a number
of electrically isolated parts became available from var-
ious semiconductor manufacturers. These offerings pres-
ently consist of multiple chips and integrated circuits as
a well as the more conventional single chip devices.
a 0.002 0.004 0.006 0008 0.01 The newer insulated packages can be grouped into two
TOTAL JOINT DEVIATION FROM FLAT OVER categories. The first has insulation between the semi-
TO·3 HEADER SURFACE AREA IINCHESI conductor chips and the mounting base; an exposed area
of the mounting base is used to secure the part. The EMS
Data courtesy of Thermalloy (Energy Management Series) Modules, shown on Figure
Figure 4. Effect of Total Surface Flatness on Interface 8, Case 806 (lCePAK) and Case 388A (TO-258AA) (see
Resistance Ul'ing Silicon Rubber Insulators Figure 11) are examples of parts in this category. The
second category contains parts which have a plastic Qver-
mold covering the metal mounting base. The Full Pak,
Silicon rubber insulators have a number of unusual
characteristics. Besides being affected by surface flatness Table 3. Performance of Silicon Rubber Insulators
and initial contact pressure, time is a factor. For example,
Tested per MIL-I-49456
in a study of the Cho-Therm 1688 pad thermal interface
impedance dropped from 0.90°CIW to 0.70°CIW at the end Measured Thermal Resistance (OCIW)
of 1000 hours. Most of the change occurred during the
first 200 hours where Recs measured O.74°CIW. The Material Thermalloy Data(1) Berquist Data(2)
torque on the conventional mounting hardware had Bare Joint, greased 0.033 0.008
decreased to 3 in-Ib from an initial 6 in-lb. With non- BeO. greased 0.082 -
conformal materials, a reduction in torque would have Cho-Therm, 1617 0.233 -
increased the interface thermal resistance. Q Pad (non-insulated) - 0.009
Because of the difficulties in controlling all variables Sil-Pad, K-10 0.263 0.200
affecting tests of interface thermal resistance, data from Thermasil III 0.267 -
Mica, greased 0.329 0.400
different manufacturers is not in good agreement. Table 0.300
Sil-Pad 1000 0.400
3 shows data obtained from two sources. The relative Cho-therm 1674 0.433 -
performance is the same, except for mica which varies Thermasilll 0.500 -
widely in thickness. Appendix B discusses the variables Sil-Pad 400 0.533 0.440
which need to be controlled. At the time of this writing Sil-Pad K-4 0.583 0.440
ASTM Committee 09 is developing a standard for inter- (1) From Thermalloy EIR 87-1030
face measurements. (2) From Berquist Data Sheet

268
 Case 221C, illustrated in Figure 13, is an example of parts Clips
in the second category. Fast assembly is accomplished with clips. When only
Parts in the first category - those with an exposed a few walts are being dissipated, the small board-
metal flange or tab - are mounted the same as their mounted or free-standing heat dissipators with an inte·
non-insulated counterparts. However, as with any mount- gral clip, offered by several manufacturers, result in a low
ing system where pressure is bearing on plastic, the over- cost assembly. When higher power is being handled, a
molded type should be used with a conical compression separate clip may be used with larger heatsinks. In order
washer, described later in this note. to provide proper pressure, the clip must be specially
designed for a particular heatsink thickness and semi-
FASTENER AND HARDWARE CHARACTERISTICS conductor package.
Clips are especially popular with plastic packages such
Characteristics of fasteners, associated hardware, and
as the TO-220 and TO-126. In addition to fast assembly,
the tools to secure them determine their suitability for
the clip provides lower interface thermal resistance than
use in mounting the various packages. Since many prob-
other assem'bly methods when it is designed for proper
lems have arisen because of improper choices, the basic
pressure to bear on the top of the plastic over the die.
characteristics of several types of hardware are discussed
The TO-nO package usually is lifted up under the die
next.
location when mounted with a single fastener through
Compression Hardware the hole in the tab because of the high pressure at one
Normal split ring lock washers are not the best choice end.
for mounting power semiconductors. A typical #6
Machine Screws
washer flattens at about 50 pounds, whereas 150 to 300
Machine screws, conical washers, and nuts (or sync·
pounds is needed for good heat transfer at the interface. nuts) can form a trouble-free fastener system for all types
A very useful piece of hardware is the conical, sometimes
of packages which have mounting holes. However,
called a Belleville washer, compression washer. As
proper torque is necessary. Torque ratings apply when
shown in Figure 5, it has the ability to maintain a fairly
dry; therefore, care must be exercised when using ther-
constant pressure over a wide range of its physical deflec·
mal grease to prevent it from getting on the threads as
tion - generally 20% to 80%. When installing, the assem-
inconsistent torque readings result. Machine screw heads
bler applies torque until the washer depresses to half its
should not directly contact the surface of plastic packages
original height. (Tests should be run prior to setting up
types as the screw heads are not sufficiently flat to pro-
the assembly line to determine the proper torque for the
vide properly distributed force. Without a washer, crack-
fastener used to achieve 50% deflection.) The washer will
ing of the plastic case may occur.
absorb any cyclic expansion of the package, insulating
washer or other materials caused by temperature Self-Tapping Screws
changes. Conical washers are the key to successful Under carefully controlled conditions, sheet-metal
mounting of devices requiring strict control of the mount- screws are acceptable. However, during the tapping-
ing force or when plastic hardware is used in the mount- process with a standard screw, a volcano-like protrusion
ing scheme. They are used with the large face contacting will develop in the metal being threaded; an unaccept-
the packages. A new variation of the conical washer able surface that could increase the thermal resistance
includes it as part of a nut assembly. Called a Sync Nut, may result. When standard sheet metal screws are used,
the patented device can be soldered to a PC board and they must be used in a clearance hole to engage a speed-
the semiconductor mounted with a 6-32 machine nut. If a self tapping process is desired, the screw type
screw.(4) must be used which roll-forms machine screw threads.

180
Rivets
Rivets are not a recommended fastener for any of the
140 plastic packages. When a rugged metal flange-mount
I package or EMS module is being mounted directly to a
'"~ 100
/ heatsink, rivets can be used provided press-riveting is
~ used. Crimping force must be applied slowly and evenly.
~ 160 Pop-riveting should never be used because the high
-;t
z
0
~
110 /'
--- crimping force could cause deformation of most semi-
conductor packages. Aluminum rivets are much pre·
ferred over steel because less pressure is required to set

I 80

40
I
I the rivet and thermal conductivity is improved.
The hollow rivet, or eyelet, is preferred over solid rivets.
An adjustable, regulated pressure press is used such that
I
a gradually increasing pressure is used to pan the eyelet.
10 40 60 80 100 Use of sharp blows could damage the semiconductor die.
DEFLECTION OF WASHER DURING MOUNTING 1'·.1 Solder
Figure 5. Characteristics of the Conical Compression Until the advent of the surface mount assembly tech-
Washers Designed for Use with Plastic Body Mounted nique, solder was not considered a suitable fastener for
Semiconductors power semiconductors. However, user demand has led
to the development of new packages for this application.
(4) ITW Shakeproof, St. Charles Road, Elgin. IL 60120. Acceptable soldering methods include conventional belt-

269
furnace, irons, vapor-phase reflow, and infrared reflow. To prevent galvanic action from occurring when
It is' important that the semiconductor temperature not devices are used on aluminum heatsinks in a corrosive
exceed the specified maximum (usually 260°C) or the die atmosphere, many devices are nickel- or gold-plated.
bond to the case could be damaged. A degraded die bond Consequently, precautions must be taken not to mar the
has excessive thermal resistance which often leads to a finish.
failure under power cycling. Another factor to be considered is that when a copper
based part is rigidly mounted to an aluminum heatsink,
Adhesives
a bimetallic system results which will bend with tem-
Adhesives are available which have coefficients of
perature changes. Not only is the thermal coefficient of
expansion compatible with copper and aluminum.(5)
expansion different for copper and aluminum, but the
Highly conductive types are available; a 10 mil layer has
temperature gradient through each metal also causes
approximately 0.3°CIW interface thermal resistance. Dif-
each component to bend. If bending is excessive and the
ferent types are offered: high strength types for non-field- package is mounted by two or more screws the semi-
servicable systems or low strength types for field-
conductor chip could be damaged. Bending can be min-
serviceable systems. Adhesive bonding is attractive
imized by:
when case mounted parts are used in wave soldering 1. Mounting the component parallel to the heatsink
assembly because thermal greases are not compatible fins to provide increased stiffness.
with the conformal coatings used and the greases foul
2. Allowing the heatsink holes to be a bit oversized so
the solder process.
that some slip between surfaces can occur as tem-
Plastic Hardware peratu re changes.
Most plastic materials will flow, but differ widely in this 3. Using a highly conductive thermal grease or mount-
characteristic. When plastic materials form parts of the ing pad between the heatsink and semiconductor to
fastening system, compression washers are highly val- minimize the temperature gradient and allow for
uable to assure that the assembly will not loosen with movement.
time and temperature cycling. As previously discussed,
Stud Mount
loss of contact pressure will increase interface thermal
Parts which fall into the stud-mount classification are
resistance.
shown in Figure 6. Mounting errors with non-insulated
stud-mounted parts are generally confined to application
FASTENING TECHNIQUES

Each of the various classes of packages in use requires (5) Robert Batson, Elliot Fraunglass and James P. Moran, "Heat
different fastening techniques. Details pertaining to each Dissipation Through Thermalloy Conductive Adhesives," EMTAS
'83. Conference, February 1-3. Phoenix, AZ; Society of
type are discussed in following sections. Some general Manufacturing Engineers, One SME Drive, P.O. Box 930, Dearborn,
considerations follow. M148128,

CASE 42A CASE S6-02 CASE 24S CASE 2S7 CASE 263-04 CASE 311-02
{DO-SI DO-203AA {DO-41 DO-203AB
{DO-41 {DO-SI
6a. Standard Non-Isolated Types 6b. Isolated Type

CASE 144B-OS CASE 14SA-09 CASE 14SA-10 CASE 244-04 CASE 30S-01 CASE 332-04
('380" STUD) (.380·' STUD) (.SOO" STUD) (.280" STUD) (.204" STUD) (.380" STUD)

6c. RF Stripline Opposed Emitter (SOE) Series

Figure 6. A Variety of Stud-Mount Parts

270
of excessive torque or tapping the stud into a threaded
heatsink hole. Both these practices may cause a warpage
of the hex base which may crack ttie semiconductor die.
The only recommended fastening method is to use a nut

~ .---oW
CHAMFER
and washer; the details are shown in Figure 7. dr-·01NOM.
Insulated electrode packages on a stud mount base SHOULDER RING
require less hardware. They are mounted the same as S01
their non-insulated counterparts, but care must be exer- - I : .01 NOM.
~ I
ce·
cised to avoid applying a shear or tension stress to the 505 DIA I HEATSINK
insulation layer, usually a berrylium oxide (BeD) ceramic. .24 {rr-". ~>;~>37"'><~ y ,~
This requirement dictates that the leads must be attached
to the circuit with flexible wire. In addition, the stud hex ! I- 0.0499 + 0.001 DIA.

should be used to hold the part while the nut is torqued. Heat Sink Mounting
R.F. transistors in the stud-mount stripline opposed
emitter (SOE) package impose some additional con-
straints because of the unique construction of the pack-
age. Special techniques to make connections to the strip-
line leads and to mount the part so no tension or shear RIVET
\.. I
~lJ.-, ADDITIONAL
./ HEATSINK PLATE
forces are applied to any ceramic - metal interface are
discussed in the section entitled "Connecting and Han- ~~ijS0,fY-
dling Terminals." .
INTIMATE
COMPLETE
KNURL CONTACT
~ THIN CHASSIS

CONTACT AREA AREA

Thin-Chassis Mou nting

The hole edge must be chamfered as shown to prevent shearing

off the knurled edge of the case during press-in. The pressing
force should be applied evenly on the shoulder ring to avoid tilting

\. + /_ INSULATOR
or canting of the case in the hole during the pressing operation.
Also. the use of a thermal joint compound will be of considerable
aid. The pressing force will vary from 250 to 1000 pounds, depend-

~h-- TEFLON BUSHING

ing upon the heatsink material. Recommended hardnesses are:
copper-less than 50 on the Rockwell F scale; aluminum-less than
65 on the Brinell scale. A heatsink as thin as 1 8" may be used,

CHASSIS
_,et, but the interface thermal resistance will increase in direct pro-
portion to the contact area. A thin chassis requires the addition
of a backup plate.
~
$_ INSULATOR

cL> - FLAT STEEL WASHER

Figure 8. Press-Fit Package

/~'.) - SOLDER TERMINAL Flange Mount

,,0 I A large variety of parts fit into the flange mount cate·
gory as shown in Figure 9. Few known mounting diffi-
culties exist with the smaller flange mount packages,
~_j - CONICAL WASHER such as the TO-204 (TO-3). The rugged base and distance
between die and mounting holes combine to make it
, extremely difficult to cause any warpage unless mounted
~ __ HEXNUT
on a surface which is badly bowed or unless one side is
tightened excessively before the other screw is started.
It is therefore good practice to alternate tightening of the
screws so that pressure is evenly applied. After the
screws are finger-tight the hardware should be torqued
Figure 7. Isolating Hardware Used for a Non-Isolated to its final specification in at least two sequential steps.
Stud-Mount Package A typical mounting installation for a popular flange type
part is shown in Figure 10. Machine screws (preferred)
self-tapping screws, eyelets, or rivets may be used to
Press Fit secure the package using guidelines in the previous sec-
For most applications, the press-fit case should be tion. "Fastener and Hardware Characteristics."
mounted according to the instructions shown in Figure The copper flange of the Energy Management Series
8. A special fixture meeting the necessary requirements (EMS) Modules is very thick. Consequently, the parts are
must be used. rugged and indestructible for all practical purposes. No

271
 ~~ ~~~
~ ~ ~ CASEl"-07 CASEllI-II CASE 215-02
CASE 1. 3. 11 CASE 3578-01 CASE ll'-09
TO-204M CASE 383-01
(TO-3)

9a. TO-3 Variations 9b. Plastic Power Tap

CASE 316-01 CASE 319-04 CASE 32BA-Ol

(CS-ll)

CASE 373-01 CASE 807-01 CASE 807A-Ol CASE 808-01

CASE 333-03 CASE 333A-Ol CASE 336-03

(MAAC PAC)

........
CASE 809-01 CASE 813-01
CASE 81l-01
CASE 337-0l CASE 361A-Ol CASE 368-01
(HOG PAC)

CASE 814-01 CASE 816-01 CASE 819-01 CASE 744-02 CASE 744A-Ol

9c. Energy Management Series 9d. RF Stripline Isolated Output Opposed Emitter
(Isolated Base Plate) (SOE) Series

Figure 9. A Large Array of Parts Fit into the Flange-Mount Classification

special precautions are necessary when fastening these sitive to proper mounting techniques than most other RF
parts to a heatsink. power devices.
Some packages specify a tightening procedure. For Although the data sheets contain information on rec-
example, with the Power Tap package, Figure 9b, final ommended mounting procedures, experience indicates
torque should be applied first to the center position. that they are often ignored. For example, the recom-
The RF power modules (MHW series) are more sen- mended maximum torque on the 4-40 mounting screws
sitive to the flatness of the heatsink than other packages is 5 in/lbs. Spring and flat washers are recommended.
because a ceramic (BeO) substrate is attached to a rel- 'Over torquing is a common problem. In some parts
atively thin, fairly long, flange. The maximum allowable returned for failure analysis, indentions up to 10 mils
flange bending to avoid mechanical damage has been deep in the mounting screw areas have been observed.
determined and presented in detail in EB107 "Mounting Calculations indicate that the length of the flange
Considerations for Motorola RF Power Modules." Many increases in excess of two mils with a temperature
of the parts can handle a combined heatsink and flange change of 75°C. In such cases, if the mounting screw
deviation from flat of 7 to 8 mils which is commonly torque is excessive, the flange is prevented from expand-
available. Others must be held to 1.5 mils, which requires ing in length, instead it bends upwards in the mid-section,
that the heatsink have nearly perfect flatness. cracking the BeO and the die. A similar result can also
Specific mounting recommendations are critical to RF occur during the initial mounting ofthe device if an exces-
devices in isolated packages because of the internal sive amount of thermal compound is applied. With suf-
ceramic substrate. The large area Case 368-1 (HOG PAC) ficient torque, the thermal compound will squeeze out of
will be used to illustrate problem areas. It is more sen- the mounting hole areas, but will remain under the center

272
 the washer is only important when the size of the mount-
NO 6 SHEET METAL SCREWS ing hole exceeds 0.140 inch (6-32 clearance). Larger
holes are needed to accommodate the lower insulating
bushing when the screw is electrically connected to the
case; however, the holes should not be larger than nec-
essary to provide hardware clearance and should never
exceed a diameter of 0.250 inch. Flange distortion is also
possible if excessive torque is used during mounting. A
maximum torque of 8 inch-pounds is suggested when
using a 6-32 screw.
POWER Care should be exercised to assure that the tool used
TRANSISTOR to drive the mounting screw never comes in contact with
the plastic body during the driving operation. Such con-
tact can result in damage to the plastic body and internal
device connections. To minimize this problem. Motorola
TO-220 packages have a chamfer on one end. TO-220
packages of other manufacturers may need a spacer or
combination spacer and isolation bushing to raise the
screw head above the top surface of the plastic.
The popular TO-220 Package and others of similar con-
INSULATING
BUSHING struction lift off the mounting surface as pressure is
HEAT applied to one end. (See Appendix B, Figure Bl.) To
counter this tendency, at least one hardware manufac-
turer offers a hard plastic cantilever beam which applies
more even pressure on the tab.(6)In addition, it separates

(6) Catalog, Edition 18, Aichco Plastic Company, 5825 N. TriPP Ave.,
Chicago, IL 60546.

SOCKET

Figure 10. Hardware Used for a TO·204AA (TO·3)

Flange Mount Part

ofthe flange, deforming it. Deformations of 2-3 mils have

been measured between the center and the ends under
I
CASE 221 A·02
(TO-220ABI
221B·01
(TO·220ACI

such conditions (enough to crack internal ceramic).

Another problem arises because the thickness of the
flange changes with temperature. For the 75°C temper-
ature excursion mentioned, the increased amount is
around 0.25 mils which results in further tightening of
the mounting screws, thus increasing the effective torque
CASE 314B CASE 3140 CASE 339
from the initial value. With a decrease in temperature, (5 PIN TO-2201

,
the opposite effect occurs. Therefore thermal cycling not
only causes risk of structural damage but often causes
the assembly to loosen which raises the interface resis-
tance. Use of compression hardware can eliminate this
problem.

Tab Mount
The tab mount class is composed of a wide array of
packages as illustrated in Figure 11. Mounting consid- CASE 340-01 CASE 387-01 CASE 806·02
erations for all varieties are similar to that for the popular (TO·2181 (TO·254AAI (ICePAKI
TO-220 package, whose suggested mounting arrange- CASE 388A-01
(TO·258AAI
ments and hardware are shown in Figure 12. The rectan-
gular washer shown in Figure 12a is used to minimize
distortion of the mounting flange; excessive distortion
could cause damage to the semiconductor chip. Use of Figure 11. Several Types of Tab-Mount Parts

273
 Plastic Body Mount
The Thermopad and Full Pak plastic power packages
I) Preferred Arrangement b) Alternate Arrangement
for Isollted or Non·isollted for Isolated Mounting when shown in Figure 13 are typical of packages in this group.
Mounting. Screw is It Screw must be at Heatsink They have been designed to feature minimum size with

...
Semiconductor Case Potential. 4-40 Hardware is no compromise in thermal resistance. For the Thermopad
Potential. 6-32 Hardware is

...
Used. (Case 77) parts this is accomplished by die-bonding the
Used.
Use Parts Listed Below. silicon chip on one side of a thin copper sheet; the oppo-
Choose from Parts Listed
Below. site side is exposed as a mounting surface. The copper
sheet has a hole for mounting; plastiC is molded envel-
oping the chip but leaving the mounting hole open. The
~_ .... PANORHE'HEAOSCREW low thermal resistance of this construction is obtained at
&J2HEX the expense of a requirement that strict attention be paid
HEAOSCREW

I FLAT WASHER
to the mounting procedure.
The Full Pak (Case 221C-01) is similar to a TO-220

==f==Y~ULAnNG
except that the tab is encased in plastic. Because the
BUSHING
mounting force is applied to plastic, the mounting pro-
cedure differs from a standard TO-220 and is similar to
[,--.---:;::::J that of the Thermopad.
L-1.J Several types of fasteners may be used to secure these
111 RECTANGULAR STEEL
WASHER
SEMICONOUCTOR packages; machine screws, eyelets, or clips are preferred.
With screws or eyelets, a conical washer should be used
SEMICONOUCTOR

,
,CASE 221. 221AJ

I
'Cj'~'A='====:::> which applies the proper force to the package over a fairly
wide range of deflection and distributes the force over a
fairly large surface area. Screws should not be tightened
121RECTANGULAii with any type of air-driven torque gun or equipment
INSULATOR
which may cause high impact. Characteristics of a suit-
'CI==~========~
HEATSINK , RECTANGULAR
able conical washer is shown in Figure 5.
Figwe 14 shows details of mounting Case 77 devices.
'c=J INSULATOR
Clip mounting is fast and requires minimum hardware,
2 BUSHING however, the clip must be properly chosen to insure that
HEATSINK
the proper mounting force is applied. When electrical

~
'3,FLATWASHER
COMPRESSION WASHER
isolation is required with screw mounting, a bushing
inside the mounting hole will insure that the screw
threads do not contact the metal base.
,4' CONICAL WASHER I / The Full Pak, (Case 221C, 221D and 340B) permits the
mounting procedure to be greatly simplified over that of
'-\::llJ
6·32 HEX r-"UT i 4·4{I HEX NUT
a standard TO-220. As shown in Figure 15c, one properly

'~-----
chosen clip, inserted into two slotted holes in the heat-
sink, is all the hardware needed. Even though clip pres-
sure is much lower than obtained with a screw, the ther-
mal resistance is about the same for either method. This
(1) Used with thin chassis and or large hole.
(2) Used when isolation is required. occurs because the clip bears directly on top of the die
(3) Required when nylon bushing is used. and holds the package flat while the screw causes the
package to lift up somewhat under the die. (See Figure
B1 of Appendix B.) The interface should consist of a layer
Figure 12. Mounting Arrangements for of thermal grease or a highly conductive thermal pad. Of
Tab Mount TO-220 course, screw mounting shown in Figure 15b may also
be used but a conical compression washer should be
included. Both methods afford a major reduction in hard-
the mounting screw from the metal tab. Tab mount parts ware as compared to the conventional mounting method
may also be effectively mounted with clips as shown in with a TO-220 package which is shown in Figure 15a.
Figure 15c. To obtain high pressure without cracking the
case, a pressure spreader bar should be used under the
clip. Interface thermal resistance with thecantilever beam
or clips can be lower than with screw mounting.
The ICePAK (Case 806-02) is basically an elongated
TO-220 package with isolated chips. The mounting pre-
cautions for the TO-220 consequently apply. In addition,
since two mounting screws are required, the alternate
CASE 77
tightening procedure described for the flange mount (TO-225AA1
package should be used. TO-1261
In situations where a tab mount package is making (THERMOPADI
direct contact with the heatsink, an eyelet may be used,
provided sharp blows or impact shock is avoided. Figure 13_ Plastic BOdy-Mount Packages

274
 l
~ ~ MACHINE SCREW OR
~ /' SHEET METAL SCREW

~~
\
HEAT SINK COMPRESSION WASHER
SURfACE I
!~ THERMOPAD PACKAGE

.---l-.. "-.. INSULATING WASHER

~""" IOPTIONAl!

" MACHINE OR SPEED

NUT
~.
14a. Machine Screw Mounting

15a. Screw-Mounted TO-220

~
~COMPRESSIO~
14b. Eyelet Mounting
WASHER

'" ~uT

15b. Screw-Mounted Full Pak

14c. Clips

Figure 14. Recommended Mounting Arrangements for

TO-225AA (TO-126) Thermopad Packages

Surface Mount
Although many of the tab mount parts have been sur-
face mounted, special small footprint packages for
mounting power semiconductors using surface mount 15c. Clip-Mounted Full Pak
assembly techniques have been developed. The DPAK,
shown in Figure 16, for example, will accommodate a die
up to 112 mils x 112 mils, and has a typical thermal resis- Figure 15. Mounting Arrangements for the Full Pak as
tance around 2°CIW junction to case. The thermal resis- Compared to a Conventional TO-220

275
tance values of the solder interface is well under l°CIW. ofthe various metal power packages are not designed to
The printed circuit board also serves as the heatsink. support the packages; their cases must be firmly sup-
Standard Glass-Epoxy 2-ounce boards do not make ported to avoid the possibility of cracked seals around
very good heatsinks because the thin foil has a high ther- the leads. Many plastic packages may be supported by
mal resistance. As Figure 17 shows, thermal resistance their leads in applications where high shock and vibration
assymtotes to about 20°CIW at 10 square inches of board stresses are not encountered and where no heatsink is
area, although a point of diminishing returns occurs at used. The leads should be as short as possible to increase
about 3 square inches. vibration resistance and reduce thermal resistance. As a
Boards are offered that have thick aluminum or copper general practice however, it is better to support the pack-
substrates. A dielectric coating designed for low thermal age. A plastic support for the TO-220 Package and other
resistance is overlayed with one or two ounce copper foil similar types is offered by heatsink accessory vendors.
for the preparation of printed conductor traces. Tests run In many situations, because its leads are fairly heavy,
on such a product indicate that case to substrate thermal the CASE 77 (TO-22SAA) (TO-127) package has supported
resistance is in the vicinity of l°CIW, exact values depend- a small heatsink; however, no definitive data is available.
ing upon board type.(7) The substrate may be an effective When using a small heatsink, it is good practice to have
heatsink itself, or it can be attached to a conventional the sink rigidly mounted such that the sink or the board
finned heatsink for improved performance. is providing total support for the semiconductor. Two
Since DPAK and other surface mount packages are possible arrangements are shown in Figure 18. The
designed to be compatible with surface mount assembly arrangement of part (a) could be used with any plastic
techniques, no special precautions are needed other than package, but the scheme of part (18b) is more practical
to insure that maximum temperature/time profiles are
not exceeded.

r. HEATSINK

TO-225M
CASE 77 "-~-1,/'1
HEATSINK SURFACE
,

'I

~
CASE 369·03 CASE 369A·04 / c.-
"

Figure 16. Surface Mount D-PAK Parts . ". " ,,/' TWIST LOCKS
OR
CIRCUIT BOARD ~ SOLOERABLE
100 LEGS
18a. Simple Plate, Vertically Mounted
§O PCB. 1151N THICK
'"
tj
80 GI0 FR4. 2 OUNCE I---
EPOXY GLASS BOARD. "---
HEATSINK
z
DOUBLE SIDED
~ 50
~ \
<I \
~
40

'~"
<t
20
'" ...........

10
PCB PAD AREA (lN21
/ CIRCUIT BOARO

'~
Figure 17. Effect of Footprint Area on Thermal
Resistance of DPAK Mounted on a Glass-Epoxy Board

/'
FREE AIR AND SOCKET MOUNTING

In applications where average power dissipation is on

the order of a watt or so, most power semiconductors 18b. Commercial Sink, Horizontally Mounted
may be mounted with little or no heatsinking. The leads

(7) Herb Fick. "Thermal Management of Surface Mount Power Figure 18. Methods of Using Small Heatsinks With
Devices," Powerconversion and Intelligent Motion, August 1987. Plastic Semiconductor Packages

276
with Case 77 Thermopad devices. With the other package The leads of plastic packages are not designed to with-
types, mounting the transistor on top of the heatsink is stand excessive axial pull. Force in this direction greater
more practical. than 4 pounds may result in permanent damage to the
In certain situations, in particular where semiconductor device. If the mounting arrangement imposes axial stress
testing is required or prototypes are being developed, on the leads, a condition which may be caused by thermal
sockets are desirable. Manufacturers have provided sock- cycling, some method of strain relief should be devised.
ets for many of the packages available from Motorola. When wires are used for connections, care should be
The user is urged to consult manufacturers' catalogs for
specific details. Sockets with Kelvin connections are nec-
essary to obtain accurate voltage readings across semi-
conductor terminals.

CONNECTING AND HANDLING TERMINALS

Pins, leads, and tabs must be handled and connected

properly to avoid undue mechanical stress which could
cause semiconductor failure. Change in mechanical
dimensions as a result of thermal cycling over operating
temperature extremes must be considered. Standard
metal, plastic, and RF stripline packages each have some
special considerations.

Metal Packages
The pins and lugs of metal packaged devices using
glass to metal seals are not designed to handle any sig- 19a. Component Parts of a Stud Mount Stripline
nificant bending or stress. If abused, the seals could crack.

'- . .
Package. Flange Mounted Packages
Wires may be attached using sockets, crimp connectors are Similarly Constructed
or solder, provided the data sheet ratings are observed.

£!j
When wires are attached directly to the pins, flexible or
braided leads are recommended in orderto provide strain
relief. O\ "0" FLAT

EMS Modules '\ 0 ,:

... - . ~
The screw terminals of the EMS modules look decep-
tively rugged. Since the flange base is mounted to a rigid PRINTED PRINTED
heatsink, the connection to the terminals must allow CIRCUIT --< TOP CONDUCTOR
some flexibility. A rigid buss bar should not be bolted to BOARD ~ ~ .. '. VIE~ ~AnERN
terminals. Lugs with braid are preferred.
HEAT R\'C'~ I

SU~~:CE ~ - T -. ~ METAL
Plastic Packages DFLAT U' - ~~:;
The leads of the plastic packages are somewhat flexible SIDE VIEW
and can be reshaped although this is not a recommended CROSS SECTION
procedure. In many cases, a heatsink can be chosen
19b. Typical Stud Type SOE Transistor
which makes lead-bending unnecessary. Numerous lead-
and tab-forming options are available from Motorola on Mounting Method
large quantity orders. Preformed leads remove the users
risk of device damage caused by bending.
If, however, lead-bending is done by the user, several MOUNTING
HOLES
basic considerations should be observed. When bending
the lead, support must be placed between the point of METAL
bending and the package. For forming small quantities HEATSINK
SURFACE
of units, a pair of pliers may be used to clamp the leads
at the case, while bending with the fingers or another CIRCUIT / TOP VIEW 'COPPER
BOARD " MOUNTIN.G ~ CONDUCTORS
pair of pliers. For production quantities, a suitable fixture '\},DlES / I
should be made.
AliGNMENT~-;--
-~7
The following rules should be observed to avoid dam-
age to the package.
SPACER .u
METAL HEAT SIDE VIEW
1. A lead bend radius greaterthan 1/16 inch is advisable SINK SURFACE CROSS SECTION
for TO-225AA (CASE 771 and 1/32 inch for TO-220.
2. No twisting of leads should be done at the case. 19c. Flange Type SOE Transistor Mounting Method
3. No axial motion of the lead should be allowed with
respect to the case.
Figure 19. Mounting Details for SOE Transistors

277
exercised to assure that movement of the wire does not CLEANING CIRCUIT BOARDS
cause movement of the lead at the lead-to-plastic junc-
tions. Highly flexible or braided wires are good for pro- It is important that any solvents or cleaning chemicals
viding strain relief. used in the process of degreasing or flux removal do not
Wire-wrapping of the leads is permissible, provided affect the reliability of the devices. Alcohol and unchlor-
that the lead is restrained between the plastic case and inated Freon solvents are generally satisfactory for use
the point of the wrapping. The leads may be soldered; with plastic devices, since they do not damage the pack-
the maximum soldering temperature, however, must not age. Hydrocarbons such as gasoline and chlorinated
exceed 260°C and must be applied for not more than 5 Freon may cause the encapsulant to swell, possibly dam-
seconds at a distance greater than 1/8 inch from the plas- aging the transistor die.
tic case. When using an ultrasonic cleaner for cleaning circuit
boards, care should be taken with regard to ultrasonic
Stripline Packages energy and time of application. This is particularly true
The leads of stripline packages normally are soldered if any packages are free-standing without support.
into a board while the case is recessed to contact a heat-
sink as shown in Figure 19. The following rules should THERMAL SYSTEM EVALUATION
be observed:
Assuming that a suitable method of mounting the
1. The device should never be mounted in such a man-
semiconductor without incurring damage has been
ner as to place ceramic-to-metal joints in tension.
achieved, it is important to ascertain whether the junction
2. The device should never be mounted in such a man-
temperature is within bounds.
ner as to apply force on the strip leads in a vertical
In applications where the power dissipated in the semi-
direction towards the cap.
conductor consists of pulses at a low duty cycle, the
3. When the device is mounted in a printed circuit
instantaneous or peak junction temperature, not average
board with the copper stud and BeO portion of the
temperature, may be the limiting condition. In this case,
header passing through a hole in the circuit boards,
use must be made of transient thermal resistance data.
adequate clearance must be provided for the BeO
For a full explanation of its use, see Motorola Application
to prevent shear forces from being applied to the
Note, AN569.
leads.
Other applications, notably RF power amplifiers or
4. Some clearance must be allowed between the leads
switches driving highly reactive loads, may create severe
and the circuit board when the device is secured to
current crowding conditions which render the traditional
the heatsink.
concepts of thermal resistance or transient thermal
5. The device should be properly secured into the heat-
impedance invalid. In this case, transistor safe operating
sinks before its leads are attached into the circuit.
area, thyristor dildt limits, or equivalent ratings as appli-
6. The leads on stud type devices must not be used to
cable, must be observed.
prevent device rotation during stud torque appli-
cation. A wrench flat is provided for this purpose. Fortunately, in many applications, a calculation of the
Figure 19b shows a cross-section of a printed circuit average junction temperature is sufficient. It is based on
board and heatsink assembly for mounting a stud type the concept of thermal resistance between the junction
stripline device. H is the distance from the top surface of and a temperature reference point on the case. (See
the printed circuit board to the D-flat heatsink surface. If Appendix A.I A fine wire thermocouple should be used,
H is less than the minimum distance from the bottom of such as #36 AWG, to determine case temperature. Aver-
the lead material to the mounting surface of the package, age operating junction temperature can be computed
there is no possibility of tensile forces in the copper stud from the following equation:
- BeO ceramic joint. If, however, H is greater than the TJ = TC + ROJCXPD
package dimension, considerable force is applied to the where TJ = junction temperature (OCI
cap to BeO joint and the BeO to stud joint. Two occur- TC = case temperature (OCI
rences are possible at this point. The first is a cap joint ROJC = thermal resistance junction-to-
failure when the structure is heated, as might occur dur- case as specified on the data
ing the lead-soldering operation; while the second is BeO sheet (OCIWI
to stud failure if the force generated is high enough. Lack PD = power dissipated in the device (WI
of contact between the device and the heatsink surface
The difficulty in applying the equation often lies in
will occur as the differences between H and the package
determining the power dissipation. Two commonly used
dimension become larger, this may result in device failure
empirical methods are graphical integration and
as power is applied.
substitution.
Figure 19c shows a typical mounting technique for
flange-type stripline transistors. Again, H is defined as Graphical Integration
the distance from the top of the printed circuit board to Graphical integration may be performed by taking
the heatsink surface. If distance H is less than the mini- oscilloscope pictures of a complete cycle of the voltage
mum distance from the bottom of transistor lead to the and current waveforms, using a limit device. The pictures
bottom surface of the flange, tensile forces at the various should be taken with the temperature stabilized. Corre-
joints in the package are avoided. However, if distance H sponding points are then read from each photo at a suit-
exceeds the package dimension, problems similar to able number of time increments. Each pair of voltage and
those discussed for the stud type devices can occur. current values are multiplied together to give instanta-

278
neous values of power. The results are plotted on linear in temperature. Case temperature is monitored. By
graph paper, the number of squares within the curve throwing the switch to the "test" position, the device
counted, and the total divided by the number of squares under test is connected to a dc power supply, while
along the time axis. The quotient is the average power another pole of the switch supplies the normal power to
dissipation. Oscilloscopes are available to perform these the load to keep it operating at full power level. The dc
measurements and make the necessary calculations. supply is adjusted so that the semiconductor case tem-
perature remains approximately constant when the
Substitution switch is thrown to each position for about 10 seconds.
This method is based upon substituting an easily meas- The dc voltage and current values are multiplied together
urable, smooth dc source for a complex waveform. A to obtain average power. It is generally necessary that a
switching arrangement is provided which allows oper- Kelvin connection be used for the device voltage
ating the load with the device under test, until it stabilizes measurement.

APPENDIX A
THERMAL RESISTANCE CONCEPTS

The basic equation for heat transfer under steady-state where TJ = junction temperature,
conditions is generally written as: PD = power dissipation
q hAIl.T (1) ReJC = semiconductor thermal resistance
(junction to case),
where q =rate of heat transfer or power dissi-
pation (PD) Recs = interface thermal resistance (case
to heatsink),
h = heat transfer coefficient,
A = area involved in heat transfer, ReSA = heatsink thermal resistance (heat-
sink to ambient),
Il.T = temperature difference between
TA = ambient temperature.
regions of heat transfer.
The thermal resistance junction to ambient is the sum
However, electrical engineers generally find it easier to
of the individual components. Each component must be
work in terms of thermal resistance, defined as the ratio
minimized if the lowest junction temperature is to result.
of temperature to power. From Equation 1, thermal resis·
tance, Re, is The value for the interface thermal resistance, Recs,
may be significant compared to the other thermal-
Re = .lT/q = 1/hA (2) resistance terms. A proper mounting procedure can
The coefficient (h) depends upon the heat transfer mech· minimize Recs.
anism used and various factors involved in that particular The thermal resistance of the heatsink is not absolutely
mechanism. constant; its thermal efficiency increases as ambient tem-
An analogy between Equation (2) and Ohm's Law is perature increases and it is also affected by orientation
often made to form models of heat flow. Note that T could of the sink. The thermal resistance of the semiconductor
be thought of as a voltage thermal resistance corre- is also variable; it is a function of biasing and tempera-
sponds to electrical resistance (R); and, power (q) is anal- ture. Semiconductor thermal resistance specifications
ogous to current (I). This gives rise to a basic thermal are normally at conditions where current density is fairly
resistance model for a semiconductor as indicated by uniform. In some applications such as in RF power ampli-
Figure Al. fiers and short-pulse applications, current density is not
The equivalent electrical circuit may be analyzed by uniform and localized heating in the semiconductor chip
using Kirchoff's Law and the following equation results: will be the controlling factor in determining power han-
TJ = PD(ReJC + Recs + ReSA) + TA dling ability.
(3)

TJ, JUNCTION TEMPERATURE - - - '---=,"",\:=-1

.~
"" q
TC CASE TEMPERATURE

TS, HEATSINK
TEMPERATURE -

'WffiWA'
TA·AMBIENT ~
TEMPERATURE -_
FLAT WASHER ---'l1tl1 '2111111
SOLOER TERMINAL ~ rill 1
NUT / REFERENCE TEMPERATURE

Figure A1. Basic Thermal Resistance Model Showing Thermal to Electrical Analogy for a Semiconductor

279
 APPENDIX B
MEASUREMENT OF INTERFACE THERMAL RESISTANCE

Measuring the interface thermal resistance Recs the semiconductor case temperature. Consider the
appears deceptively simple. All that's apparently needed TO-220 package shown in Figure B1. The mounting pres-
is a thermocouple on the semiconductor case, a ther- sure at one end causes the other end - where the die is
mocouple on the heatsink, and a means of applying and located - to lift off the mounting surface slightly. To
measuring DC power. However, Recs is proportional to improve contact, Motorola TO-220 Packages are slightly
the amount of contact area between the surfaces and concave. Use of a spreader bar under the screw lessens
consequently is affected by surface flatness and finish the lifting, but some is inevitable with a package of this
and the amount of pressure on the surfaces. The fasten- structure. Three thermocouple locations are shown:
ing method may also be a factor. In addition, placement
a. The Motorola location is directly under the die
of the thermocouples can have a significant influence
reached through a hole in the heatsink. The thermocouple
upon the results. Consequently, values for interface ther-
is held in place by a spring which forces the thermocouple
mal resistance presented by different manufacturers are into intimate contact with the bottom of the semi's case.
not in good agreement. Fastening methods and ther- b. The JEDEC location is close to the die on the top
mocouple locations are considered in this Appendix. surface of the package base reached through a blind hole
When fastening the test package in place with screws, drilled through the molded body. The thermocouple is
thermal conduction may take place through the screws,
swaged in place.
for example, from the flange ear on a TO-3 package c. The Thermalloy location is on the top portion of the
directly to the heatsink. This shunt path yields values tab between the molded body and the mounting screw.
which are artificially low for the insulation material and The thermocouple is soldered into position.
dependent upon screw head contact area and screw
material. MIL-I-49456 allows screws to be used in tests Temperatures at the three locations are generally not
for interface thermal resistance probably because it can the same. Consider the situation depicted in the figure.
be argued that this is "application oriented." Because the only area of direct contact is around the
Thermalloy takes pains to insulate all possible shunt mounting screw, nearly all the heat travels horizontally
conduction paths in order to more accurately evaluate along the tab from the die to the contact area. Conse-
insulation materials. The Motorola fixture uses an insu- quently, the temperature at the JEDEC location is hotter
lated clamp arrangement to secure the package which than at the Thermalloy location and the Motorola location
also does not provide a conduction path. is even hotter. Since junction-to-sink thermal resistance
As described previously, some packages, such as a must be constant for a given test setup, the calculated
TO·220, may be mounted with either a screw through the junction-to-case thermal resistance values decrease and
tab or a clip bearing on the plastic body. These two meth- case-to-sink values increase as the "case" temperature
ods often yield different values for interface thermal resis- thermocouple readings become warmer. Thus the choice
tance. Another discrepancy can occur if the top of the of reference point for the "case" temperature is quite
package is exposed to the ambient air where radiation important.
and convection can take place. To avoid this, the package There are examples where the relationship between
should be covered with insulating foam. It has been esti- the thermocouple temperatures are different from the
mated that a 15 to 20% error in Recs can be incurred previous situation. If a mica washer with grease is
from this source. installed between the semiconductor package and the
Another significant cause for measurement discrep- heatsink, tightening the screw will not bow the package;
ancies is the placement of the thermocouple to measure instead, the mica will be deformed. The primary heat
conduction path is from the die through the mica to the
heatsink. In this case, a small temperature drop will exist
across the vertical dimension of the package mounting
EIA
base so that the thermocouple at the EIA location will be
the hottest. The thermocouple temperature at the Ther-
malloy location will be lower but close to the temperature
. at the EIA location as the lateral heat flow is generally
small. The Motorola location will be coolest.
The EIA location is chosen to obtain the highest tem-
perature on the case. It is of significance because power
ratings are supposed to be based on this reference point.
Unfortunately, the placement of the thermocouple is tedi-
ous and leaves the semiconductor in a condition unfit for
sale.
The Motorola location is chosen to obtain the highest
MOTOROLA temperature of the case at a point where, hopefully, the
case is making contact to the heatsink. Once the special
heatsink to accommodate the thermocouple has been
Figure 81. JEDEC TO-220 Package Mounted to fabricated, this method lends itself to production testing
Heatsink Showing Various Thermocouple Locations and does not mark the device. However, this location is
and Lifting Caused by Pressure at One End not easily accessible to the user.

280
 The Thermalloy location is convenient and is often cho- atures utilizes a soft copper washer (thermal grease is
sen by equipment manufacturers. However, it also blem- used) between the semiconductor package and the heat-
ishes the case and may yield results differing up to 1"CIW sink. The washer is flat to within 1 mil/inch, has a finish
for a TO-220 package mounted to a heatsink without ther- better than 63 IL-inch, and has an imbedded thermocou-
mal grease and no insulator. This error is small when ple near its center. This reference includes the interface
compared to the thermal resistance of heat dissipaters resistance under nearly ideal conditions and is therefore
often used with this package, since power dissipation is application-oriented. It is also easy to use but has not
usually a few watts. When compared to the specified become widely accepted.
junction-to-case values of some of the higher power A good way to improve confidence in the choice of
semiconductors becoming available, however, the dif- case reference point is to also test for junction-to-case
ference becomes significant and it is important that the thermal resistance while testing for interface thermal
semiconductor manufacturer and equipment manufac- resistance. lithe junction-to-case values remain relatively
turer use the same reference point. constant as insulators are changed, torque varied, etc.,
Another EIA method of establishing reference temper- then the case reference point is satisfactory.

APPENDIX C
Sources of Accessories

Insulators
Joint Plastic Siticone
ManufIOCt_ Compound Adhesive. BeO AIO:! Anodize Mica Film Rubber Heat.inks
Aavid Eng. X X - - - - - X X
AHAM-TOR - - - - - - - - X
Astrodynamis X - - - - - - - X
Oelbert Blinn - - X - X X X X X
IERG X - - - - - - - X
Staver - - - - - - - - X
Thermalloy X X X X X X X X X

Tran-tec - - X X X X - X X
Wakefield EIlQ. X X X - X - - X X
Other sources for 81hcone rubber pads: Chomeflcs, BerQUt8t

Suppliers Addresses
Aavid Engineering, Inc., 30 Cook Court, Laconia, New International Electronic Research Corporation, 135 West
Hampshire 03246 (603) 524-4443 Magnolia Boulevard, Burbank, California 91502
AHAM-TOR Heatsinks, 27901 Front Street, Rancho, Cal- (213) 849-2481
ifornia 92390 (714) 676-4151
The Staver Company, Inc., 41-51 Saxon Avenue, Bay
Astro Dynamics, Inc., 2 Gill St., Woburn, Massachusetts Shore, Long Island, New York 11706 (516) 666-8000
01801 (617) 935-4944
Thermalloy, Inc., P.O. Box 34829, 2021 West Valley View
Berquist, 5300 Edina Industrial Blvd., Minneapolis, Min- Lane, Dallas, Texas 75234 (214) 243-4321
nesota 55435 (612) 835-2322
Tran-tec Corporation, P.O. Box 1044, Columbus,
Chomerics, Inc., 16 Flagstone Drive, Hudson, New Hamp- Nebraska 68601 (402) 564-2748
shire 03051 1-800-633-8800
Wakefield Engineering, Inc., Wakefield, Massachusetts
Delbert Blinn Company, P.O. Box 2007, Pomona, Califor- 01880 (617) 245-5900
nia 91769 (714) 629-3900

281
 PACKAGE INDEX

PREFACE

When the JEDEC registration system for package out- designations were re-registered to the new system as
lines started in 1957, numbers were assigned sequen- time permitted.
tially whenever manufacturers wished to establish a For example the venerable TO-3 has many variations.
package as an industry standard. As minor variations Can heights differ and it is available with 30, 40, 50, and
developed from these industry standards, either a new, 60 mil pins, with and without lugs. It is now classified in
non-related number was issued by JEDEC or manufac- the TO-204 family. The TO-204AA conforms to the orig-
turers would attempt to relate the part to an industry inal outline for the TO-3 having 40 mil pins while the
standard via some appended description. TO-204AE has 60 mil pins, for example.
In an attempt to ease confusion, JEDEC established the The new numbers for the old parts really haven't
present system in late 1968 in which new packages are caught on very well. It seems that the DO-4, DO-5 and
assigned into a category, based on their general physical TO-3 still convey sufficient meaning for general verbal
appearance. Differences between specific packages in a communication.
category are denoted by suffix letters. The older package

Motorola I JEDEC Outline MotorOlalc:-:-,JE_DE,.,-C_D::-"'-,"n_e-:-1 Motorola JEDEC Outline

Case Original. Revised Mounting See Case Original ReviMd Mounting See Case Original Revised Mounting Sea
-:N:::-",-m_b_e'~5Y,-"::-._m-:-:5c'y:::-,,:-:em-,-r-N_O_'"_'+-,C_"_"---1_P'-"''-I" I--N_"_m_
.._,+s~y.:....:.'m-+-,S-=-"'_'_m--j_N_O'.:."'_r-C_"_"--j_P'-='--1e Number System System Notes Class Page
001 TO-3 TO·204M Flange 211·11 Flange 337-02 Flange
003 TO-3 Flange 215-02 Flange 340 TO-218AC T,b
_0_09_~T::-O-,.6-,'~T-,O-"'-,'0-,A-,-C+_ _+Sc:,":.:d_+-'--i 221 TO·220AB Tab 11 34QA-02 Plastic 12
_0.,-",,-......,.T:::O,..3,--+,T-'O_'_04_AA_'r---_ _ j-'-=".:.ng-c.---4---'---1 21c:C.-=-02: :--t--t-----t---+pC"",'-'''-,---t-,:-::,--1
C:,=- 340B-03 Isolated Plastic 12
.- I TO-218
~:~A ;:~:: :::::: 2210-01 l;b~2t;g Plastic 12 C:3C":4'cO
:..,-'-+--t-----+---+,-"-"-,---t-c:---1

036 TO-50 ,TO-210AS Stud 235 TO-20B Stud 3576-01 Flange

042A ' 00-5 IOO-203AB 235-03 Stud 361-01 Flange

Stud
238 TO-208 Stud 368-01 Flange
044 100-4 IOO-203M Stud
'054 239 TO-208 Stud 369-03 TO-251 14
TO-3 Flange
244-04 Stud 369A-04 TO-252 Surface 13
056 00-4 Stud
100-5 245 00-4 Stud 373-01 Isolated Flange
1058 Stud
61-03 257-01 00-5 Stud 383-01 Isolated Flange '0
Flange
263 Stud 387-01 TO-254M Isolated 2 Tab
63-02 TO-54 TO-208A8 I Stud
263-04 Stud 388A-Ol TO-258M Isolated 2 Tab 11
63-03 TO-54 TO-2088AB I Stud
283 00-4 Stud 8 744-02 Flange
077 TO- I 26 TO-225M I I Plastic
080 TO-66 TO-213AA Flange
289 TO-209 ----~ S~d ~--- ------s- 744A-Ol Flange

086 TO-208 305-01 Stud 806-02 Isolated Flange

Stud
310-02 Press!l! 807-01 Isolated Flange
086l ,TO-298 I Stud
1448-05 311-01 Isolated Stud 807-02 Isolated Flange
Stud
145A-09 I 311-02 Pressflt 807A-Ol Isolated Flange
I Stud
i 145A-l0 311-02 Stud 808-01 Isolated Flange
I Stud

f::'c::=~'f:.~:-:+----+----1---f:~"'::=--+-':-:'-1
Isolated Flange
1145C lTO-232 Stud
809-01
Isolated Flange
'57 Stud
316-01 Flange 813-01 Isolated Flange
: 160-03 I TO-59 TO-210M Stud
319-04 Flange 814-01 Isolated Flange
1167 I~ 00-203 Stud
174-04 328A-Ol Flange 814A-Ol Isolated Flange
I Pressflt
'175-03 332-04 Stud 0848-01 Isolated Flange
Stud
333-03 Flange 816-01 Isolated Flange
197 I· TO-204AE Flange

[21'.07 i Flange 333A-Ol Flange 819-01 Isolated Flange

Flange 336-03 Flange 043-02 00-21 DO-208M Pressflt

Notes , Would fit w'thm th,s fam'ly outline ,j registered w'th JEDEC
2 NotwlthlnaliJEDECdlmeosloos

282
 AN1041
Mounting Procedures for
Very High Power RF Transistors

Prepared by
Helge O. Granberg
RF Engineering
Advanced Products Group

RF power semiconductors such as MRF153, MRF154, sion mentioned above, the amount is around 0.25 mils,
MRF155, MRF156 and MRF430 are housed in Case 368· which results in further tightening of the mounting
01, whereas MRF141G, MRF151G, MRF175G and screws, thus increasing the effective torque from the ini·
MRF176G use Case 375-01 (both shown below). All of tial value. However the amount of increase is difficult to
these are high power devices (200-600 W), which results measure and depends on the exact type of mounting
. in an abnormally large amount of heat dissipated within hardware used. The copper·tungsten flange of case 375·
a small physical area. For such high power transistors, 01 has a much lower expansion coefficient than copper,
special attention must be paid to the heat sink material but if mounted on a copper or aluminum heat sink, it can
as well as the finish and flatness of the mounting surface. be similarly bent during a cooling cycle as the heat sink
The material should have at least a thermal conductivity material contracts.
equal to or better than copper and for the mounting sur· Deformation can also occur during the initial mounting
face flatness :': 0.0005" can be considered sufficient. The of the device if an excessive amount of thermal com-
heat sink can be made of material with lower thermal pound is applied along with sufficient screw torque. The
conductivity such as aluminum, but in that case a copper thermal compound will squeeze out olthe mounting hole
heat spreader should be used. The heat spreader should areas, but will remain under the center of the .flange,
have a minimum thickness of 0.25" for case 375-01 and deforming it in a similar manner, Depending on the
0.375" for 368·01 and should extend at least 0.5" to 1.0" amount of thermal compound and its type, deflections
beyond the flange edges, depending on the device type of 2-3 mils have been measured between the flange cen-
and the amount of dissipation involved. For die temper· ter and corners created by such conditions. The same can
ature calculations of devices in case 368-01, the .l tem· happen with all flange mounted RF devices, but with
perature between the mounting screw areas and the bot- thicker Beryllium Oxide insulators and lower dissipation
tom center of the flange is approximately 5°C and 10°C levels the problem is less severe.
under normal operating conditions and dissipations of The maximum operating junction temperature and the
150 Wand 300 W respectively. total dissipation are usually given in the data sheets. It
Although the data sheets contain information on the should be able for the device to be operated within these
subject above as well as the mounting procedures of limits if the case temperature can be kept at 25°C or the
these devices, very few designers actually follow them. derating factor is taken into account. The 150°C storage
The maximum recommended torque on the #4 size temperature indicated implies that the device can be
mounting screws is 4-5 in.-Ibs. along with split lock· and operated at that case temperature, which is true but at a
flat·washers, of which the latter should be in immediate much derated dissipation rating. However good engi-
contact with the flange's top surface. Experiments have neering practices would limit the case temperature to
shown that merely compressing the split lock washer to 70-80°C and the die temperature to not higher than twice
its full flatness produces enough torque for sufficient that.
pressure against the heat sink. The split lock washers are
available with various spring tensions. Bell type compres-
sion washers would be an even better choice if found
with 5 in.·lbs. or lower torque specifications.
Calculations indicate that the length of the case 368-01
copper flange increases in excess of two thousands of
an inch with a temperature change of 75"C. In such case,
if the mounting screws are torqued too tight, the flange
cannot expand in length but will bend upwards in the
mid section, cracking the Beryllium Oxide insulators as
CASE 368·01 CASE 375·01
well as the dice. It must also be noted that the thickness
of the flange increases with temperature. For the excur·

283
284
 AN1044
The MC1378 - A Monolithic Composite
Video Synchronizer
Prepared by Geoffrey Perkins

INTRODUCTION

The MC1378 was designed to enable an interface to be PDl is a digital phase detector that compares the hor-
made between remote composite color video sources izontal TTL sync fed into pin 40with the MC1378's internal
and a locally controlled RGB source of video. It contains horizontal sync and controls the 4 MHz VCO to form a
the necessary synchronizing circuits, plus a cOr"(lplete PLL. The 4 MHz VCO signal is internally divided by 256
color encoder. to horizontal frequency. The eight stage divider is also
The NTSCiPAL color encoding circuitry is very similar used to develop the burst gate and burst flag signals by
to the MC1377 and a detailed discussion of this subject decoding the countdown. Burst gate is used extensively
can be found in AN932. The major differences between within the device for gating and clamping chroma and
the MC1378 and MC1377 color encoding sections are that video signals. Burst gate is 41-'s wide and is centered
in the MC1378 the burst flag and color subcarrier quad- about the 2.2 I-'s burst flag signal. Burst gate is also fed
rature accuracy are determined digitally and are not out of pin 5 to drive other devices that should be locked
externally adjustable, and the MC1378 is designed to to horizontal frequency; e.g. TDA3301i3. Phase detectors
operate from a 5 V supply. PD2, 3 & 4 are not actively used in the LOCAL MODE but
The MC1378 contains all the necessary circuitry to lock PD4 sets an arbitrary oscillator phase to the two elec-
a computer to a remote color composite video source tronic phase shifters.
and to switch between the remote and the locally gen- In the PAL mode the R-Y modulator is phase inverted
erated signals to create overlays in composite video. By line by line and a burst flag is sent to both R-Y and B-Y
using an additional device, the TDA3301i3, simultaneous modulators. The PAL flip-flop runs at an arbitrary phase
overlays in RGB can be created. Because the MC1378, in the local mode when the ident circuit is disabled by
when operated in the remotely locked mode, passes the an external diode connected to pin 29. If a particular PAL
remote signal directly to its output without decoding and phase is required, the PAL flip-flop can be reset at this
re-encoding, no loss in picture quality is experienced as pin.
can happen in less sophisticated systems. The overlay enable (pin 25) should be set low in the
LOCAL MODE to view the NTSC or PAL encoded RGB
SYSTEM DESCRIPTION: LOCAL MODE signals at pin 27.

(SEE FIGURE 1 AND BLOCK DIAGRAM) REMOTE MODE

Because the MC1378 operates in two basic modes,
local and remote, it is logical to describe them separately. In the remote mode all phase detectors are active
No external video is required in the local mode and the except PD5. An external valid video signal or remote sig-
main function of the MC1378 is to encode the 1 V RGB nal must be fed into pin 24 to provide all the timing
signals into NTSC or PAL and to drive the graphics sys- information to the host computer. Composite sync is sep-
tem's clock using the 4X subcarrier crystal oscillator as arated from the remote signal and then fed to the vertical
a reference. sync separator to detect vertical sync. The separated
A double balanced phase detector, PD5, is used to com- composite sync is used to lock the 4 MHz VCO using PD1,
pare the now free running 4X subcarrier oscillator divided the vertical sync being fed out to the graphics system to
by four with the returning subcarrier signal at pin 8 and lock its sync generator. The 4 MHz is divided by 256 to
control the clock oscillator. The clock is divided down by horizontal frequency and this is compared in PD2 with
the appropriate number within the graphics system to the TTL negative going H sync signal at pin 40. The output
subcarrier frequency. This forms a PLL using the crystal of PD2 is used to lock the system clock VCO, the frequency
oscillator at pins 10 and 11 as a reference. A separate of which can range from 14 to 36 MHz depending upon
clock could be used if it is not a multiple of subcarrier the host computer's requirement. The system clock is
frequency - the disadvantage being that the encoded divided down to Horizontal sync frequency within the
video signal's subcarrier will not be related to the hori- host system and fed into pin 40.
zontal frequency, and unpleasant dot crawl or beating on The color burst from the remote signal is used to lock
the display may result. the 4X color subcarrier oscillator using PD3 which is

285
 MC1378 Composite Video Overlay System
Block Diagram

1~~8:~~43 I * Burst Gate Out

l
-----------
--1- +5.0 V

28 l
10 ', I'U", I" "',.. I

f--__---=-""v~ ~ Sync

N PAU
co NTse~ ~Sync
Ol Out

II I~~~:~te

I Camp. Sync In

I
I
I
L _ _ ~7 _E.
-y
Out
-y
In
----7Ts I

T rr Video
Out

Vee
Gnd
 Figure 1. MC1378 Application Schematic

XTAL Specifications
MC1378
Frequency 14.318180 MHz
or 17.734475 MHz
Mode: Fundamental
Frequency Tolerance
40 PPM Max
at 25°C cK +
1.0W
Frequency PAL
0.002
Temperature
40 PPM Max
o 36 MHz
Tolerance !;.f/fo 300 mVp-p
OUTPUT
0-70°C
0.001
Load
18 pF
Capacitance
Equivalent
Series Resistance
50 n Max
Vcc ___ .J"""'''---'''-<I~-I

Cl 15 mpF 3.312.2.uH

TOKO

1M
3.3 k.4.7 ~ 100pF

.---JVl.IIr------I~ Vee
100 k 12k
1.2k
-: TO EQUALIZE
For noisy remote video signals (color lock LOCALLY GENEAATtD AGB
takes longer), use these values for either
NTSC or PAL. CD 400 ns Delay line ® Set in Remote Mode @ 14.3217.73 MHz
TOK Dl1224D1D·1533 or @ 3.5814.43 MHz
TOK401D-2249 (smaller) or 500 mVp-p
TOKO 321lNP1436PBAB

1.0 I'F 1.8 k

Horizontal

h,t---------J
Pull-In (Typ) Ceramic Resonators CK RA RB CA
For MURATA Resonator
2
+400, -400 525 Line CSA4.03MTF102 47p 1.8 k 680 0.022
+400, -400 625 Line CSA4.00MTF102 47p 1.8 k 680 0.022

68 pF

47 pF
25 pF
the two burst amplitudes are compared in the ACC detec-
tor and made equal using a variable gain ACC amplifier
j;: 1 kHz PULL·IN
in the locally generated chroma path.
The absolute burst amplitude of the remote signal only
is detected by the kill detector, the chroma of the locally
gated with burst gate. By using PD4 and comparing the generated signal being turned off when the remote burst
burst of the locally generated composite video from the falls below a predetermined level. The kill level can be
encoder section with the same subcarrier reference used adjusted by changing the value of the resistor at pin 31.
to lock PD3, the subcarrier phases of both the local and 470 kO kills at about 10-20 mVp-p remote burst (normal
the remote signals are made essentially equal. Similarly, = 300 mVp-p).

287
 In the PAL mode the phase of the ident of the remote Figure 2. Typical Mastar Clock Frequency
burst is compared with the half line signal from the PAL Configurations
flip-flop. If an error is detected, indicating that the local
ident is not compatible with the remote ident, the flip-
flop is reset using the ident processor. If a continuous
ident error is detected, i.e. fixed or no burst on remote
signal, the chroma in the local signal is killed.
O'OOl

i~
Because the black levels, burst phases, burst ampli-
tudes, and in the case of PAL, ident states are compatible 14.3 MHz
LOR C
between local and remote signals, the fast video switch 1.0 fLH 33
COULD BE
operated by the overlay enable signal fed into pin 25 can 32
VARIABLE
be used to switch from one signal to the other to create
overlays in composite video. Even portions of the timing
::t 68 pF

i~
waveforms (sync, burst, etc.) can be selected from either -= 0.001 33
the local or remote sources for specific purposes, such 17.78 MHz
as noise reduction due to weak signal remote, or VCR 17.90 MHz
0.82 fLH
tape jitter reduction. LOR C
32
COULD BE
PHASE DETECTOR OPERATION SUMMARY VARIABLE J. 47 pF

i~
(SEE BLOCK DIAGRAM) '001

LOCAL MODE 28.6 MHz

0.33 fLH 33
POl - compares the internal horizontal frequency LOR C

l@
derived from the 4 MHz VCO with the Horizontal sync COULD BE 32
derived from the master clock from the host computer. VARIABLE
The PLL formed locks the internal horizontal signal to the 18PF
host computer's signal.
PD2 - not used in LOCAL MODE. 33
47 pF

i
PD3 - not used in LOCAL MODE.
PD4 - active, but providing an arbitrary phase-shift
setting between the subcarrier reference and the output 35.8 MHz 82pF 32
chroma phase of the locally generated composite video. 35.5 MHz
PD5 - locks the master clock VCO (divided down to 0.3 fLH J. 0.001
subcarrier frequency within the host computer) to the
four times subcarrier crystal oscillator. The crystal oscil-
lator becomes the system timing standard in the LOCAL
MODE.
REMOTE MODE
PD1- compares and locks the internally counted down
4 MHz VCO to the incoming remote horizontal sync. It is
fast acting to follow VCR source fluctuations, etc. PICTURE IN PICTURE
PD2 - locks the master clock oscillator by comparing
the internal horizontal signal with the H sync returning Another test fixture that can be used with the RGB color
from the host computer. bar generator (see schematic, Appendix D, in AN932) to
PD3 - a gated phase detector, which locks the crystal insert video into color bars or vice-versa is the "picture
oscillator frequency divided by four to the incoming in picture" circuit shown in Figure 3. Six-one-shot mono-
remote signal burst. stables create variable delays and blanking pulses to
PD4 - controls an internal phase shifter to assure that drive the overlay input on the MC1378. Tl, T2, T3, and
the outgoing local color burst has the same phase as the T4 are variable delays such that the inserted picture win-
incoming remote burst at PD3. dow's size, position and aspect ratio may be adjusted.
PD5 - not used in REMOTE MODE.
TEST FIXTURES TO SIMULATE A COMPUTER
TYPICAL MASTER CLOCK FREQUENCY
Sometimes major problems can be avoided if, before
CONFIGURATIONS
connecting the MC1378 to a computer system, the
Many applications require a Master Clock frequency MC1378 application is tried using a test fixture. The major
different from the one shown in the standard schematic. problems can be solved using the fixture leaving smaller
The figure to the right shows the circuit and component details to be fixed in the total system. Two types of test
values for typical clock frequencies. It is recommended fixture are shown in Figures 4 and 5. Both use a 36 MHz
that silver mica capacitors be used for accuracy and tem- Master Clock, one for 525/60 Hz NTSC and the other for
perature stability except for the 0.001 /LF coupling caps 625/50 Hz PAL. Other clock frequencies can be accom-
which can be standard ceramics. modated by changing the divide ratios.

288
 HORIZ. SYNC INPUT
FROM TEST FIXTURE
VERT. SYNC INPUT
13 Figure 3. Picture In Picture

_
1J
1J
+5V

FROM MC13781~~~-~~~~~~~~~~~~~~=t~=~===l:;+J
3.9 k

Delay Adjust
T1 Rl Cl 5 ms
T2 R2 C2 5 ms
T3 R3 C3 2Ol'S
T4 R4C4 2Ol'S
T ~ RC 109n2
109n2 ~ 69

COMPo BLANKING

T3 J. i T2 T4 J 1k TO RGB COLOR
BAR GENERATOR
+
L.-_--+--_n;::;-1.r---,~
I I

Rl. R2: 33 k. MIN. 2 k

R3. R4: 7.5 k, MIN. 2 k OVERLAY ENABLE
TO MC1378
EXAMPLE OF FORMAT
PIN 25

The Master Clock output from the MC1378 can be deliv- 4. If a coil is used in the 4 MHz oscillator; adjust it to give
ered using a short length «12") of 50 n coax. The clock the correct horizontal frequency at pin 5 (use pin 40
is amplified using one section of the MC74LS04 hex as a scope trigger). When the oscillator has phase
buffer-inverter connected with shunt feedback, followed locked, adjust the coil to give the correct waveform at
by another stage to drive the first dividers. The first divid- pin 2.
ers bring the frequency down to 3.58 MHz or 4.43 MHz Pin 2 waveform
accordingly, to drive PD5 in the LOCAL MODE. This TTL
output is reduced and rounded off using an RC network.
Additional dividers are used to reach horizontal sync fre-
10~
quency. A one-shot MC74LS221 produces the 5 I'-S wide ~H----j
negative going horizontal sync signal to feed the MC1378
at pin 40. Other variations are possible and the two sche- 5. Switch to "REMOTE" MODE (pin 1 = + 5 V).
matics are shown only as a guide. 6. Adjust the 100 k potentiometer at pin 9 to give the
correct subcarrier frequency to within 50 Hz at pin 20
MC1378 SET-UP PROCEDURE USING as in #2.
TEST FIXTURE 7. Feed 1 V p-p composite color video into pin 24. Color
burst and composite sync should now appear at pin
1. Switch to LOCAL MODE (pin 1 '" 0 V). Ground pin 25. 27. The color burst will be absent if the 100 k pot was
2. Using·a source of accurate subcarrier frequency, as incorrectly adjusted.
an oscilloscope trigger, adjust the variable capacitor
at pin 10 so that the burst appearing at pin 20 is the MC1378 APPLICATION UPDATE: CLOCK
correct frequency to within 10Hz. OSCILLATOR ALIGNMENT
NTSC = 3.579545 MHz PAL = 4.4333619 MHz
3. Disconnect the signal feeding into pin 8 (3.58/ Two new circuits are shown in Figure 6 to improve the
4.43 MHz). Measure this frequency and adjust the pull-in range and speed of the Clock Oscillator phase-
Clock Oscillator until the meter reads 3.58 MHz (NTSC) locked loop. Figure 6b shows a circuit that has no com-
or 4.43 MHz (PAL) ± 10kHz. Reconnect the signal to promise between the characteristics in both the local and
pin 8. This signal should now be phase-locked to the remote modes. Both circuits allow a much wider toler-
burst frequency at pin 20. ance on the alignment of the Clock Oscillator.

289
 Figure 4. Test Fixture. NTSC 525/60 Hz

+5V 1k
36 MHz BUffeR
36 MHz INPUT FROM
MCI378 PIN 35 0.01

~.". 10k
3.58 MHz
5IlOmVp-p
TO MCI378
PIN 8

LSl12A
) PINOUT
4--716MHz
220 f 20PF T
+5V

~5 X SN741S112A

L+--..!lr-lr~~
U I HORIZ. SYNC TO
MCI378PIN40
5",

Figure 5. Test Fixture. PAL 625/50 Hz

+5V
Ik

36 MHz INPUT FROM

MC1378 PIN 35 0.01

~
I 10k
4.43 MHz
5IlOmVp-pTO
MCI378 PIN 8

220 1150 PF f
+5V

290
 16
Figure 6. Clock Oscillator Alignment Figure 7. RGBI to RGB Converter

PIN 37 o-~r--<r-----' HIN~ "/4MC78~S86 I ~ CaMP, SYNC

~~~
PIN37;f1
2200 pFI 15 k 10 VIN~V>---+---'-'~ COMP,SYNC
±10% _ + ,01/LF + 5,6 k ~ MC)4lS04 2 MC)4lS05
- 11,0/LF
2N4401 11,0 /LF RIN'l'

4.7k ~
+-+--.......---,;Q) ROUT
::.a-'-"'W..-J l'50 PF*
LOCAlIREMOTE
(al (bl GIN'l'
t-.,--i-1r--i':P GOUT
"C>o-"-"'W..-J J:'50 ¢
RGBI TTL TO RGB. 1 V ANALOG CONVERSION
390U
Figure 7 shows a circuit to interface a TTL RGBI output +-~~_--'~ BOUT
personal computer to the RGB analog inputs of the "'o-''-'II'~ ~ 330°1,::,,'50pF
MC1378. If the circuit is used with the values shown. no ./'
coupling capacitors are required to the RGB inputs of the
MC1378. The + 5 volt supply to the 390 n resistors should
be very clean to prevent interference on the encoded
signal. IC4 is used to simulate 'brown' to be compatible
with TTL display monitors.

USING THE MC1378IN CONJUNCTION WITH

1.25V
THE TDA3301/3 FOR OVERLAYS IN BOTH RGB
AND COMPOSITE VIDEO

In some video applications both RGB overlay and com· Figure 8. Noninverting Buffer. Level Changer
posite video overlay are required, In these situations the
MC1378 can be used as a time base locked to the remote r---"'~~ + 12 V
source, not only for the graphics computer, but also for
the color decoder.
The burst gate output of the MC1378 appearing at pin TO PIN 27
5 can be used to drive the sandcastle pulse input of the OF TDA3301'3
TDA3301/3 at pin 27, Because the output level of the FROM PIN 5 12Vp·p -Jl
OF MC1378 BURST GATE
MC1378 istoo lowto drive the TDA3301/3 directly, a small
4 Vp·p
noninverting buffer is used, as shown in Figure 8, to ena·
BURST GATE
ble the burst gate pulse to exceed the required slice level
at the TDA3301/3. A vertical pulse for the TDA3301/3
clamping system can be obtained at pin 38 ofthe MC1378
operating in the REMOTE MODE only when a valid video
Figure 9. Vertical Output Inverter
signal is applied. The vertical output must be inverted as
shown in Figure 9, If a continuous vertical pulse is
required so that the output clamps of the TDA3301/3 are 1/6 SN74LS04
always operating, a locked 50/60 Hz oscillator will have 4Vp-p ~Jl 5 Vp·p
to be used. This could consist of a MC1455 type timer IREMOTE MODEl TO PIN 28
circuit. If a vertical pulse is produced by the microcom- FROM PIN 38 OF TDA3301'3
OF Me1378
puter graphics source, it should be used instead. When
in LOCAL MODE, an alternative source of vertical sync
must be found to drive the TDA3301/3. Figurll 10. Overlay Input Inverter and Delay
The overlay fast video switches in the MC1378 and
TDA3301/3 operate in the opposite sense to each other.
TO PIN 23 OF
Therefore an inverter must be used between pin 25 of . - - - - - - - - - { ) TDA33013
the MC1378 and pin 23 of the TDA3301/3. FAST BLANKING
The delay produced by the use of a delay line in the 400 ns IOPT.)
luminance path of the MC1378 must be compensated by X>~Mr--=::::!,::!:!::=-......OTO OVERLAY
using a similar delay in the overlay enable line as shown 1,1k ~k ENABLE
in Figure 10. The RGB inputs are essentially compatible PIN 15 OF
between the MC1378 and the TDA3301l3, and can be MC1378
connected as shown in Figure 11.

291
 Figure 11. RGB Input Connection Figure 12. 3.58 MHz Chroma Trap

TO
14

MC1378 15~
G-;:-i 10 IJ-F
+
10 IJ-F 0,1
0,1 r-<> 25

r-<>26 1
TO
TDA3301/3
Vp·p
(lSOn MAX
COMPOSITE
VIDEO INPUT
l!Wr.-----
10 IJ-H

10 k
10IJ-F

1.5 k
+
PIN 37

0,1
16~ lOIJ-F SOURCE Z, SEE
~ f----O 24 TOA3301I3 390~FIJOPF =
INPUTS 1,8 k
DATA SHEETI
R G B

Figure 13. RGB Output Blanking Circuit Figure 14. NTSC Components for TDA3301/3 for
(One of Three Required Shown) Coupling the Color I.F. to the Demodulators

+12V

POSITIVE
COMPOSITE
BLANKING
100 pf
i+iiv-------~
PIN3~~~N7
TO TO I
GREEN CKT BLUE CKT
r-------
_ _ _ _ _ --1I f' 4 PIN 8
I lN4148 NON·ADJUSTABLE
I PIN 20 NTSC CONNECTION
: RED OUT o-~~H__",,"t-'"VV'"'-~
RED
I @
PIN 22
I RED fEEDBACK
I
J. lVp-p
IN75{J NOTE: Use monochrome signal with
burst to set balance, with saturation
at nominal.
I
I NOTE: Set feedback pots and NOTE: The circuit shown within
~ brightness control for correct the dotted line must be duplica-
L~~n~a!..o~~ _ _ _ _ _ _ _ ~d...!?~I~~~!!'.e~. __

A 3,58 MHz chroma trap for the luminance input is Figure 15. MC1378 Subcarrier Notch Filter
shown in Figure 12. For more general information, see
the TDA3301/3 data sheet. 400 n,
A circuit for blanking, filtering and driving a 75 n load MC1378 100 n 1,1 k DELAY MC1378
with 1 V POp is shown in Figure 13, The 5 V composite PIN17 ~ PIN22
blanking could be developed by using part of the circuit 91 pF k
} 358 MHz '1 12 =
shown in Figure 4. 22IJ-H _
Figure 14 shows a method for balancing the 3.58 MHz '1 FOR 443 MHz, _ -
or 4.43 MHz demodulator leakage appearing at the RGB C=68pF -
outputs. Normally this is not necessary, but for more l = 18IJ-H
exacting applications it may be required,
Figure 16. Improved Remote Video Input
MC1378 SUBCARRIER NOTCH FILTER Isolation Circuit
Cross color can cause annoying rainbow effects on fast
luminance edges especially in noninterlaced pictures. +5V
Figure 15 shows a simple subcarrier notch filter in the
luminance delay path of the MC1378 to remove some of
10 k FROM
the offending cross color artifacts at the expense of lumi-
22 k lOCAU
nance bandwidth. The cross color problem can be espe- }-+_--'VV\O--_ REMOTE
cially bad when attempting to record on consumer type
VCRs because on playback the chroma-horizontal inter-
leaving becomes random, The notch method is equally
effective on PAL or NTSC,

IMPROVED REMOTE VIDEO INPUT

ISOLATION CIRCUIT
at the composite video input. Typically, the cross talk is
Because of certain limitations in the device and its pack- about -35 dB at 4.43 MHz and better at 3.58 MHz. Low
aging, the cross talk from remote composite video input frequencies are better than - 60 dB. The circuit shown in
to composite video output can be troublesome when Figure 16 will improve the isolation in the LOCAL MODE
operating in the LOCAL MODE with a video signal present by an additional - 20 dB.

292
 MC1378 NTSC LUMINANCE COMB FILTER

To avoid loss of luminance bandwidth while removing delay line input, pins 1 and 2, on noninterlaced signals.
color artifacts, a simple comb filter can be used in NTSC The amplitude and phase adjustments are made when
(see Figure 17). For 625 line PAL, a more complex arran- a small amount (550 mVp-p) of 3.58 MHz subcarrier is
agement has to be made which would be beyond the added at the output of the 400 ns delay line. The two
scope of this application note. The NTSC comb filter is adjustments are trimmed for minimum subcarrier at pin
only effective on interlaced color and horizontal signals. 22. By using this technique, virtually all the cross color
Noninterlaced signals could become worse with this artifacts are removed without loss of luminance
arrangement. However, it may be possible to short the bandwidth.

Figure 17. MC1378 NTSC Luminance Comb Filter

(For Interlaced Video Only)

+5V PHASE
+5V

2.2 k MC1378
18 "H

0
400 n, PIN 22

Uk DELAY
50 PF
2N4402
MC1378
PIN 17 T 1.2 k 560 n
-15 "H
'1. PHASE COIL
TOKO TYPE 10k,
BOBBIN: KAN(CI '2. ULTRASONIC OELAY LINE
SET FOR MIN. 3.58 MHz CORE: 03·0009 GTE SYLVANIA SDL345
COMPONENT AT PIN 22. POT CORE: 04·0002 3.579545 MHz
CASE: 06·0088·1 63.556",
WIRE: 38G (0.1 mml OR PHILIPS/AMPEREX
34 TURNS DL750
TOKO TKAN9436HM

NTSC DECODER COMB FILTER FOR THE TDA3301/3 luminance and chrominance are combed of chroma and
Figure 18 shows a circuit similar to Figure 17 to improve luma respectively to remove colored artifacts in inter-
the luminance bandwidth by removing the 3.58 MHz laced video, The setup is accomplished by adjusting the
notch in the luminance channel of the TDA3301/3. Again, amplitude and phase for minimum subcarrier at the lumi-
this filter, as shown, is only applicable to NTSC. Both nance output.

Figure 18. NTSC Decoder Comb Filter for the

TDA3301/3

+12V TO CHROMA
2.2k BANOPASS

PHASE
'--~-1...drT--4b-__-:,18:!,,~H~'~1-+_..{ 2N4402

5.6 k 2.2 k TO LUMA

INPUT
1 Vp·p 22 "F
COMPOSITE C>-1 +
VIDEO
2.2 k

'1. PHASE COIL

TOKO TYPE 10 k,
BOBBIN: KAN(CI
CORE: 03·0009
POT CORE: 04·0002 '2. ULTRASONIC DELAY LINE
ADJUST FOR NULL OF CASE: 06·0088·1 GTE SYLVANIA SDL345
CHROMA IN LUMA CHANNEL. WIRE: 38G 10.1 mml 3.579545 MHz
34 TURNS 63.556",

293
 CARRIER BALANCE OF COLOR MODULATORS Rgure 19. Carrier Balance of Color Modulators

Certain applications require perfect carrier balance of +5V

the color modulators. This is simply realized in Figure 19.
1M MC1378
The two 100 k potentiometers should be adjusted with a
100 k ~-"W"""--o PIN 12
black signal for minimum subcarrier at the video output.
R- YCARRIER BALANCE

+5V

1M MC1378
100 k ~~'VV'v--o PIN 13
B-Y CARRIER BALANCE

Figure 20. Printed Circuit Board Layout

Component Side Pattern (not full size)

Circuit Side Pattern (not full size)

294
 Figure 21. Printed Circuit Board Components Layout

RE @-

G 'Taka H321 LNP-1436PBAB 0

orTDK DL122401D-1533

Figure 22. Photo

295
 MC1378 EXPECTED WAVEFORMS

Pin 1 Local-O Volts, Remote-5 Volts

2 3 Vdc Approximate (See Application Note)
3 4 MHz, 200-300 mVp-p Sine Wave (Oscilloscope Probe will disturb the Horizontal PLL)
4 Distorted 4 MHz Signal
5 4 V, 4 /LS Wide Pulse Locked to Horizontal
6 NTSC-O V/PAL-Open
7 Ground
8 3.58 MHz/4.43 MHz 300-800 mVp-p Sine or Square Wave from RMI in Local Mode - Shows Beat Between
Remote Signal and Local Subcarrier, but otherwise unimportant
10 14.32/17.73 MHz, 150-300 mVp-p Sinewave (Scope Probe will disturb PLL)
11 Distorted 14.32117.73 MHz Signal
12113 3.5 Vdc Approximate
14/15116 1 Vp-p RGB Color Signals, Low for Black, High for Color. All Blanking at Black Level both for Horizontal
and Vertical. These are Analog Inputs, so any Noise on RGB will appear at the Output.
17 Inverted Luma Signal 1 Vp-p for 100% Color Bars (1.8 V White/2.8 V Black)
18 Chroma Output 3.5814.43 MHz with Harmonics, Burst 100 mVp-p, Chroma 300 mVp'p, 100% Color Bars
(Approximate Amplitudes)
19 3.4 Vdc Approximate
20 Chroma Input 3.58/4.43 MHz, Burst 100 mVp-p, Chroma 300 mVp-p, 100% Color Bars
(Approximate Amplitudes)
21 3.3 Vdc Approximate
22 Inverted Luma 0.5 Vp-p, 100% Color Bars (0.9 White/l.4 V Black)
23 3.5 Vdc Approximate
24 Remote Video Input 1 Vp-p, Negative SYNC
25 Overlay Enable Input; Low - Encoded RGB, High - Remote Signal
Threshold = Approximately 1.4 V
26 Ground
27 Composite Video Output
28 VCC +5 Vdc
29 PAL Identification Pin (Not Used in NTSC)
In PAL Stepped Waveform at Vertical Rate
In NTSC DC 0.5 V
30 2.7 Vdc Approximate
31 DC 0.6 V with 100 mV Vertical Ripple When Color Unkilled, 4.2 Vdc Approximate When Color Killed
32/33 36 MHz 200 mVp-p. Difficult to Observe with Conventional Oscilloscope Probe because of Grounding
Problems
34 Ground
35 Clock Output 36 MHz, Sinewave 300 mVp-p, Open Circuit Approximate. When used at Lower Frequencies the
Output may become Bigger and Clipped. Also same Scope Problem as with 32/33 at 36 MHz
36 VCC +5 Vdc
37 2.2 Vdc Approximate (See Application Note)
38 Local Composite SYNC Input in LOCAL MODE TTL Negative
Remote Vertical SYNC Output in REMOTE MODE TTL Negative
39 Composite SYNC TTL Output Negative
40 Horizontal SYNC Input TTL Negative

296
 APPENDIX
DIRECTORY OF COMPONENT MANUFACTURERS

California Crystal Laboratories (800) 333-9825

crystals

Coil craft (312) 639-6400

1102 Silver Lake Road coils
Cary, IL 60013

Comtec (602) 526-4123

crystals

Fox Electronics (813) 693-0099

crystals

GTE Sylvania Electronic Components Division (717) 326-6591

2401 Reach Road crystals,
Williamsport, PA 17701 ultrasonic delay lines (for comb filter)

International Crystals (405) 236-3741

crystals

muRata-Erie (404) 436-1300

2200 Lake Park Drive coils
Smyrna, GA 30080
Distributor - Time Electronics see local directory
Distributor - Sterling Electronics contact muRata for nearest location

Phillips/Amperex Optoelectronics Division (401) 232-0500

ultrasonic delay lines (for comb filter)

Standard Crystal Corporation (818) 443-2121

crystals

TDK Corporation of America (312) 803-6100

1600 Feehanville Drive 400 ns delay lines
Mount Prospect, IL 60056

Toko America Inc. (312) 297-0070

1250 Feehanville Drive coils, transformers, 400 ns delay lines
Mount Prospect, IL 60056
Distributor - Digikey (800) 344-4539
Distributor - Inductor Supply (800) 854-1881
(800) 472-8421 (from within California)

MOTOROLA DOES NOT ENDORSE THE VENDORS LISTED. THIS IS A PARTIAL VENDOR LIST, AND NO
LIABILITY IS ASSUMED FOR OMISSIONS OR ERRORS IN ADDRESS, PRODUCT LINE OR OTHER
INFORMATION.

297
298
 AN1047
Electrical Characteristics of the
CR2424 and CR2425 CRT Driver Hybrid
Amplifiers
By Dan Brayton

CRICUIT AND THERMAL DESCRIPTION Therefore. worse case junction temperature rise over
OF CR2424 AND CR2425 CRT DRIVER case (flange I is 1.6 watts x 35"CIW = 56"C. The type of
HYBRID AMPLIFIERS transistor used in Motorola CRT hybrid driver amplifiers
is rated for operation up to 200"C. At 150"C junction tem-
CIRCUIT DESCRIPTION peratures. MTTF for an individual transistor chip is
The circuit of the CRT driver amplifiers consists of a greater than 140 years.
pair of complementary common emitter Class A stages
DC stacked across the 60 V supply. The "top" PNP device CRT HYBRID TUBE ARC SIMULATION
is connected as a current source at DC through mid fre-
quencies; at high frequencies. the "current source" A tube arc was simulated by electrostatic discharge
becomes active. This complementary Class A pair drives equipment. A variable voltage source charges up a
complementary Class B emitter followers. capacitor.

THERMAL DESCRIPTION
O------"\M.,....- -....
All four transistors (silicon bipolarl have identical hor- R
izontal geometries (active areasl. gold metallization and
plasma nitride passivation. These transistors are each
eRT
mounted on .055 x .055 inch gold plated copper heat
HYBRID
spreaders which serve to maximize the heat flow from 10UTPUTI
the transistor die through the alumina thin-film substrate
to the aluminum flange (heatsink or casel that is soldered
to the back side of the substrate. This structure results in
a thermal resistance of 35"C/watt max (30"C/watt typical I
Figure 1. Electrostatic Discharge Simulator
for junction to case (flange) for each of the four active
transistors.
Junction temperatures can. therefore. be computed if Then the energy inside the capacitor is discharged
the power dissipation for each transistor is known. The through a resistor to the CRT hybrid. Test conditions of
power dissipated in each transistor is a function of the R = 10 ohms and C = 150 pF were used.
amplifier operating conditions as listed in Table 1.
CASE 1. UNPROTECTED;
Table 1. Transistor Power Dissipation The CRT hybrid failed at 2500 volts. Because output of
0, 02 03 <4 the Electrostatic Discharge Simulator is connected to
Oesignation PNP NPN PNP NPN ground during charge period. a 0.01 J.LF DC blocking
Type A A B B capacitor is used to prevent output of the CRT hybrid to
Class of Operation POIW) POIW) PoIW) POIW) ground. which could damage the hybrid.
Case I 0.75 0.75 <0.1 <0.1
Case II 0.2 1.6 <0.1 <0.1 Vee ~ 60 V

~I ~'D'S'
Case III 1.6 0.2 <0.1 <0.1
Case IV 0.8 0.8 0.2 0.2
Case V 1.0 1.0 1.6 1.6

Case I No connection to input pin 1; output = 30 Vdc 0.01 fLF

Case II Black level; output = 55 Vdc
Case III White level; output = 5.0 Vdc
Case IV sa wave input f ~ 60 Hz; output ~ 40 Vp_p
Case V sa wave input 7.5 ns pixel; output ~ 40 Vp_p
General conditions: VCC ~ 60 V; load ~ 8.5 pF

299
CASE 2. PROTECTION RESISTOR: CASE 4. BYPASS CAPACITOR:
A protection resistor of 47 n is connected between the A 0.1 /LF bypass capacitor was added along with diode
E.O.S. and hybrid. The hybrid failed at 4500 volts. Again and resistor. In this case, failure of the hybrid occurred
a 0.01 JLF blocking capacitor is used to prevent the hybrid at 15,000 volts.
discharging to ground.

0.1/L F

VFAll ~ 15.000 V
Figure 3. Circuit for Case 2
Figure 5. Circuit for Case 4
CASE 3. PROTECTION DIODE:
A protection diode (lS583 Hitachi) was added. Failure
of the hybrid occurred at 9500 volts. Electrical character- CONCLUSION:
istics for this diode are listed in Table 2 below.
Obviously the circuit in case 4" offered the best protec-
tion to the hybrid amplifier. The bypass capacitor and
diode should be placed as close to hybrid Vee node as
possible, and ground leads on the bypass capacitor and
hybrid should be able to carry surge current to insure the
best protection.
NOTE: A diode, Oz, should be added if there is reason
to believe that large negative surges may reach the video
driver output port.

PERFORMANCE CHARACTERISTICS
Typical bandwidth and rise and fall times of the CRT
Figure 4. Circuit for Case 3 driver are shown in Figures 6 through 10.

Table 2. Characteristics of Protection Diode 1S583

MAXIMUM RATINGS (TA ~ 25'C)

Item VR(peak) VR IF(peak) 10 TJ

Unit V V mA mA 'C
Rating 250 220 625 200 175
NOTE: JEDEC DO-35 Seahng condItIOn.

ELECTRICAL CHARACTERISTICS (TA ~ 25'C)

Limit
Item Symbol Test Condition Unit
Min Max
Forward Voltage VF IF ~ lOa mA 1.0 V
Reverse Current IR VR ~ 220 V 1.0 p.A
IF ~ IR ~ 30 mA
Reverse Recovery Time trr 80 ns
RL ~ 50 n, ire ~ 0.1 IR

NOTE: Glass Sealing condition.

300
 Figure 60 Bandwidth versus Output Load, CL Figure 7, Rise and Fall Times and Overshoot
versus Output Swing Voltage
(Under Regular Operation Condition -
Vo = 20Vpop Vo = 4OVpop VCC = 60 V, Load = 8,5 pF)
CL (pFI BW(MHzl BW(MHzl
6 175 145
8.5 Output Overshoot (VI
172 145
10 166 140 Swing (VI tr (nsl tl (nsl Leading Trailing
12 160 130 50 2.6 2.4 2.5 1.2
15 150 120 40 2.2 2.0 4.0 2.4
18 140 100 30 1.9 1.9 4.6 3.0
20 1.8 1.7 4.2 2.8
10 1.8 1.8 2.4 1.2
180
- -....... 2.6

~\ ,.., . 1-....",
170 .......
~Vpop
160
i"-. 2.4
," "
,OSL
,
"
"~X
150
~ ....... \
\
~
ox: 140
>-
......... ~ ~
\
\
\

- ......
V)

'" 1\>(
0 \
:g
~ i=
2.2
OST
\

~ 130 ,, \
\
~o
120
"- ""- 40 Vpop ~
0
z
«
OSL
,,
\
'\ ~

~
V)
,/ \

110 '\. DO
~
/
\
,
\

\
~

~tr
I
OST
100 loB
'\... ~
10 12 14 16 lB 20
CL, OUTPUT LOAD (pFI 1.6
50 40 30 20 10
VIDEO OUTPUT SWING IVOLTS poPI
Figure 8. Rise (tr ) and Fall (t,) Times versus
Output Load, CL Figure 90 Rise and Fall Times and Bandwidth
versus Loads
CL (pFI tr (nsl t, (nsl
6.0 pF 1.8 1.6
A. CL = 8.5 pF VCC = 70 V
8.5 pF 2.2 2.0
10 pF 2.4 2.1 tr (nsl tl (nsl BW (MHzl Condition
12 pF 2.6 2.3
2.0 1.8 147 40 V Swing
15 pF 2.8 2.5
18 pF 3.1 2.8 2.6 2.2 133 50 V Swing
2.7 2.5 111 55 V Swing

B. CL = 15 pF VCC = 70 V

ty ~
I--l.---V
t::==I--
~
-- tr (nsl
2.6
3.5
3.6
tl (nsl
2.1
2.5
2.8
BW(MHzl
133
105
83
Condition
40 V Swing
50 V Swing
55 V Swing

~ C. CL = 8,5 P VCC = 60 V VOUT = 40 V Swing

(Standard Operating Conditionsl
tr (nsl tl (nsl BW (MHzl
2.5 2.0 142

10 12 14 16 lB
CL, OUTPUT LOAD (pFI

301
 2.50 Ts.5PF
All standard test conditions, except add R. ¢'
Figure 10. Rise and Fall Times versus Serial
Output Resistance

R (0) tr (ns) tt (ns)

0 2.1 1.8
10 2.1 1.9
20 2.2 2.2
30 2.4 2.3
40 2.5 2.5
50 2.6 2.6
60 2.7 2.8
70 2.8 3.0
80 3.0 3.2
90 3.2 3.4
100 3.4 3.6
110 3.4 3.8
120 3.6 4.0
130 3.8 4.2
140 4.0 4.4
150 4.2 4.6
160 4.4 4.7
170 4.5 4.8
180 4.8 5.0
190 4.8 5.4
200 5.0 5.6

! I !
i I
,
!
j
1 J..'-~
If
",-
1,
I....'

! ~
,,,,,,," I

....... ~J~I
I
I
"
If
1

o
o 20 40 60 80 100 120 140 160 180 200
R. OUTPUT RESISTANCE (OJ

Figure 1,1.

302
 AN1061

Application Note
REFLECTING ON TRANSMISSION LINE EFFECTS
This application note describes introductory transmission line characterization, analysis, and application.
Over the past couple of years, microprocessors and digital 16gic in general have seen substantial in-
creases in line drive capability. This increase has fostered the current logic and microprocessor speeds
readily available today. The relatively quick rise and fall time of today's digital devices makes an under-
standing of transmission lines and their el(ects on system reliability a necessity.

TRANSMISSION LINE CHARACTERIZATION

When discussing transmission lines one should reflect on the following definition. A transmission line is
two or more conductors separated by some insulating medium, used to carry a signal. At first glance this
seems rather trivial, but upon closer examination one finds a host of physical nuances which make the
transmission line a sophistcated element to describe, among which are:

1. Line resistance present in any non-ideal conductor.

2. Line conductance ((1/R) = G) present in any non-ideal insulating medium resulting in leakage
currents.
3. Line inductance present in any current carrying conductor undergoing a change in magnetic flux.
4. The line capacitance present between the two conductors separated by the insulating medium.

Figure 1 shows the line under discussion. The circuit consists of two series elements (Z + L) and two shunt
elements (C + G).

Figure 1. TransmisSion Line Circuit

Our discussion will be primarily concerned with C + L, because these elements are the frequency depen-
dent components of the line (neglecting skin effect). For frequencies above approximately 100 kHz, Zo,
the characteristic impedance of the line, is equal to the square root of UC and is independent of line
length. The propagation constant (tpd) or time delay constant is the square root of L·C, and is a function
of line length. Zo is of particular importance to our discussion because when you match this impedance
to the load, you reduce the effects of transmission imparted to both the source and the load.

303
TRANSMISSION LINE REFLECTIONS

Reflections on a line are caused by a mismatch in Impedance between the line and the load. If all the
power delivered to the line is absorbed by the load then there will be no reflected power back at the source
side of the line. This principle of power conservation is the cornerstone of this application note. Refer
to Figure 2 as the equations are discussed. The equation describes the ratio of absorbed power to re-
flected power based on the ratio of line to load impedance.

Zo
TRANSMISSION LINE

v==-
I-
Figure 2. Transmission Line

The current delivered to the load is IL = IINC -IRFL (incident current minus reflected current), while the load
voltage is, VL", VINC + VRFL (incident voltage plus reflected voltage). We need to find an equation that re-
lates incident voltage to reflected voltage. Therefore noting thatthe load current IL = (VF - VRFL)/Zo (incident
voltage minus reflected voltage divided by the characteristic impedance) we can see the following rela-
tionship.
VINC + VRFL VINC-VRFL
(1)
ZL Zo
Solving for VI~RFL

(2)

(3)

(4)

This expression is called the load reflection coefficient (PL). Note a Ps also exists which relates the ratio
of source impedance to line impedance. This expression is called the source reflection coefficient and
is shown in Equation 5.

304
 Ps = Zs-Zo
(5)
Zs+Zo

One can see that there are three distinct possibilities which require inspection. First, the situation where
the load impedance equals the line impedance (Zl = Zo) and Pl = 0 (no reflections - a properly terminated
line); second, where the load impedance is greater than the line impedance (Zl > Zo) and Pl is positive,
generating a reflection whose polarity matches that of the incident voltage, and, finally, where the load
impedance is less than the line impedance and Pl is negative, generating a reflection whose polarity is
opposite to that of the incident voltage. Let's take a closer look at the last two cases.

Assume that Zl = 4Zo, and that the source impedance = line impedance. V = source voltage, and Vl
= load voltage (see Figure 3).

Pc Zl -Zo = 4Zo- Zo = 0.6

= ~+Zo 4Zo+Zo

Zo
TRANSMISSION LINE

v=-
I- 1=0

Figure 3. Transmission Line Circuit wIth ZL =4 • Zo and Zs =Zo

Thus at I = 0 a voltage wave of 1/2{V) (because Zs and Zo form a voltage divider on V) begins to travel
down the line and arrives at Zl one tpc! or propagation delay laler. When the wave encounters the load
impedance mismatch, a reflected wave equal in magnitude to (V/2tO.6 is reflected back toward Ihe
source, and arrives althe source again one !pet later. This causes the voltage at the source to rise therefore
creating Ihe classic overshoot condition.

Since the source and line impedance are matched no further reflections are generated and the line has
reached its steady state condition. See Figure 4.

Figure 4. Voltage versus Time Plot of ZL =4 • Zo and Zs =Zo

305
 The next scenario is when Zt. < 4J. For this case assume the following conditions. ZL = Zd4 and Zs = Zo.
See Figure 5.

.254J-4J = -0.6
Pc = .25Zo + 4J

1
TRANSMISSION LIN
Vs

v==-
I-
- t= 0

Figure 5. Transmission Line ClrcuH with ZL = Zo I 4 and Zs = Zo

At time t = 0 a voltage wave equal in magnitude to 1I2V begins to travel down the line arriving at the load
one delay time later. The impedance mismatch generates a reflected wave equal in magnitude to the re-
flected wave discussed in the first example, but opposite in polarity. At time 2tpd this wave reaches the
source and sums with the existing voltage present from time t = 0 (V/2), reducing its value to Vs/5 or
((V/2)(-O.6) + V/2). This is the classic undershoot condition. See Figure 6.

Figure 6. Voltage versus Time Plot of ZL = Zof4 and Zs =Zo

At this point we need to 'reflect on one of the equations described earlier. The equation states that VL=
VINe + VRFL · We can see this holds true as noted In the preceding examples, where VL and Vs either
increased or decreased with corresponding mismatches in impedance.

THE LATTICE DIAGRAM

The lattice diagram permits a network to be checked quickly for balance (match). The diagram is essen-
tially a two-line graph with corresponding source and load impedance, connected by a reflection diagonal
with a period of 2tpd (twice the line delay time). This diagonal is used to represent the reflected voltage's
magnitude. See Figure 7.

306
 SOURCE VOLTAGE (Vs ) LOAD VOLTAGE (VJ

Ps side Pt- side

1=0

1= I

1= 2
Vrfl 2 = I?; ·Vrfl l 1= 3

1= 4

elc.

Figure 7. LaHlce Diagram

The example below will illustrate the use of the lattice diagram. For the analysis assume the following cir-
cuit (see Figure 8 and 9).

Zo =500
TRANSMISSION LINE

RL =3.90

Figure 8. Transmission Line Circuit for Zs = 7.5 0, Zo = 50 0 and ZL = 3.9 0

307
 Ps= 7.5-SO 11 = 3900-50
7.5 +SO (Vs) (Vd L 3900 +SO
= -0.739 = 0.974
1=0
Vi = Vs = 1.74V
1= 1 ,VL = 3.43V

Vs = 2.18V,1 = 2

1= 3 , VL = 0.97V

Vs = loB6V,I =4
1=5, VL =2.73V

Vs = 2.09V,1 = 6

1= 7 , VL = l.46V

Vs = 1.93V,1 = B

1= 9 , VL = 2.37V

Vs = 2.05V,1 = 10

1= 11.VL = lo72V

Vs =1.96V,1 = 12

t= 13, VL = 2.1BV

Vs =2.02V,1 = 14

Figure 9. Lattice Diagram for ZS = 7.5 n. Zo = 50 nand ZL = 3.9 n

Transmission Line Types

There are essentially IWO Iypes of transmission lines; the microstrip and the slripline. The microslrip is
shown in Figure 10. It consists of a conduclorseparated from the ground plane on one side by a dieleclric.

- - - - TRACE

h - DIELECTRIC

FIGURE 10. Mlcrostrlp Transmission Line

308
The characteristic impedance of a one ounce line configured as a microstrip on G-10 fiber glass is:

Z 8 7 . Ln(5.98h) (6)
0= JER+1.41 (0.8w+t)

= 0.0015 in. for 1 OZ copper

= 0.0030 in. for 2 OZ copper
h = 0.062 in. for G-10 glass epoxy
w = design dependent (based on current handling requirements.) = 0.015 in.
For our discussion,

ER = 4.7-5.3

For this example, with ER = 4.7, Zo = 116.6 n

The unloaded propagation delay t". = 1.017 jo.475ER+ 0.67 ns/ft = 173 ns/ft.

The stripline is a conductor separated from ground on two sides by a dielectric (see Figure 11).

- GROUND PLANE

- DIELECTRIC
b

••••a- GROUND PLANE

Figure 11. Strlpllne Transmission Line

The characteristic impedance of G-10 fiber glass board trace configured as a stripline is:

ZO=~.Ln[
(7)
4b ]
IE; 067n (0.8w + h)

Using the same parameters as above we find that Zo 60 Q. The propagation delay
1.017 IE; = 2.20 ns/ft

309
Loaded Transmission Line Propagation Delay and Impedance
As stated earlier the unloaded propagation of a microstrip line is:

J
tpel = 1.107 0.475ER + 0.67 ns/ft

This delay increases with capacitive loading. The increase is equal to /1 + Co/Co where CD is the distrib-
uted capacitance and Co is the intrinsic capacitance of the line. Co is obtained from Figure 3-8 of Refer-
ence 1, or alternatively it can be calculated as Co = ~ /Zo. For the micro strip described above with thick-
ness (h) of 0.062 in, and signal trace width of 0.015 in, Co = 15 pf. Assuming this line is loaded with five
10 pf loads the loaded propagation delay becomes:

(1.73ns) J1 + 50/15 = 3/60 ns/ft

The loaded line impedance Zo' = Zo/ /1 + CD/CO = 116.6/2.08 = 56 C.

For the stripline discussed above there is a corresponding increase in tpel and Zo.

The loaded propagation delay ~' = 2.2 /1 + 50/15 = 4.57 ns/ft, while the loaded impedance
ZOo = 60//1 +50/15 = 28.8 C.

It is apparent that capacitive loading increases the propagation delay of the line while decreasing its im-
pedance.

TRANSMISSION LINE TERMINATION

No discussion about transmission lines would be complete without examining the techniques to properly
terminate a line. Essentially there are three (3) methods which can be employed. They are:

1) Unterminated line (controlling board parameters to match line and load impedance).
2) Series termination.
3) Parallel termination.

Unterminated Line Method

This method involves controlling the length of the line such that any reflections caused by the load are
absorbed by the rise and fall time, t, and tf of the driving gate. Forthis method to be effective the propaga-
tion delay (loaded delay) of the line must be short relative to t, and 1t. This allows the reflected wave to
sum with the rising or falling driving gate waveform. If four times the propagation delay of the line is less
than or equal to t, or~, then minimal ringing (overshoot, undershoot) will be observed. Specifications for
t, and ~ for various logic families are readily available. Knowing these times one can set the maximum

310
 line length such that the lines \pt' <= t,/4. For distributed loads that are stubbed, the length of the stub
should be set to minimize any reflections. A t,lt..t' ratio greater than 8:1 should suffice.

Series Termination
In series termination a resistance is inserted between the driving gate output and the line. The combined
output impedance of the driving gate plus the added series resistance is selected to equal the loaded im-
pedance of the line. Since the input impedance of the driven gate is much greater than Zo, the line will
ring. Basically this termination configuration will ring once and reach steady state within 2\pt'. End of line
loading, (lumped loading) is the only method of loading that is recommended for this type of termination.
This is because any distributed load onthe line "sees" a voltage equalto v/2 until steady state. This condi-
tion could violate the valid V1H or V1l specification of these gates. Clearly distributed loads are to be
avoided. Receivers at the end of the line will not experience this condition, as the incident voltage and
the reflected voltage add together to equal the load voltage (Vl ) one \pt' after the signal is asserted.

Parallel Termination
In the parallel termination method two resistors are placed at the end of the line. One resistor from the
line to ground, and the other from the line to VCC. The parallel combination of these resistors is set to be
equal to the loaded impedance of the line. For example, if Zo' of the line is equal to 50 n, then the parallel
combination of both reSistors should equal 50 n. Note this method of termination requires more drive cur-
rent. The driver selected must be able to handle the additional load placed upon it by the added parallel
load. Also it is apparent that this method of termination consumes power even in the steady state, as an
additional current path has been set up between Vee and ground.

A PRACTICAL EXAMPLE
Upon completing the paper design for our new project, we begin to peruse our schematics for possible
transmission line problems. For the purposes of our discussion assume the following configuration:

Vee 5 volts
PC trace microstrip configuration, G-10 fiber glass, 1 oz copper,
ER = 4.7, w = 0.015, t = 0.0015, h = 0.062
Logic family: Fast TIL (drive and receive side of line)
Driving gate: F241 buffer

tf + tr F241: 2 ns (for 50pf lumped load)

Number of
loads (FOS's): 5 ( input capacitance = 5pf/load)
(IlL = 600 1lB, IIH = 100 1lB)
Configuration: Distributed loads approximately every 2 in. for a
total trace length of 10 in.

311
Procedure
1. Calculate the lines characteristic impedance (Zo).
zo = same as example described earlier = 116 n.
2. Calculate unloaded propagation delay (tpd).
tpd = 1.017/0.475ER +0.67 = 1.73 ns/ft
3. Calculate the lines intrinsic capacitance (Co).
Co = VZo expressed as nf/ft
Co = (1.73 nslft)/116 = 15pf/ft = 1.25 pflin. * 10 in. = 12.5 pf
4. Calculate the loaded line impedance (Zo')
Zo' = 116/1.25/12.5 = 67 C
5. Calculate the lines loaded propagation delay (tpd')
tpd' = 1.73/1 +25/12.5
tpd' = 3.0 ns/ft = 0.25 nS/in. * 10in. = 2.5 ns» t,/4

As described earlier, since the loaded propagation delay of the line exceeds t, 14, we will have to terminate
the line. The loads are not lumped at the end of the line, they are distributed. As explained earlier, series
termination cannot be used because of the possible threshold violations. For this example we will use
parallel termination. The parallel resistor combination will be chosen to match the loaded impedance of
the line. Noting the drive current of the F241 , (loL = 64 ma, IOH= 15 mal, we can set the source current
resistor equal to:

VOH (min)/((5*100 l1a) + IOH/2) = 2 V/8 ma = 250 n

Note: Im/2 arbitrarily chosen. Value could be reduced if required.

The sink current resistor part of this terminator is equal to 91 C. This results in a drive sink current equal
to:

(Number of Loads" IIH) + V - VoL (F241)/91 = 5"600 ~ + 5v - .55V/91 n = 52 ma

Note: Weight the source side terminator such that both sink and source current specification are not
violated. As shown the parallel combination of the terminating resistors is set equal to the loaded line im-
pedance. See Figure 12.

312
 Note: Gate spacing = 2 inches
-
Figure 12. Transmission Line - Example

Since the line is now properly terminated, reflections will be minimized.

In this example, the loads were not stUbbed. Had they been located on a stUb, an extra calculation would
have had to been performed to ascertain the maximum permissible stub length.

This calculation runs as follows:

1. Set t,lIpd' = 8.5 and solve for~'

tpd' = 2 nsl8.5 = 235 ps
2. Solve for the maximum stub length (x)
235 ps = 1.73 ns/ft j 1 + 5 pf/(x)in./1.25 pf/in.
235 ps = 144 ps/in. ~
X tpd = 1.017 /0.475E R + 0.67 = 1.73 nslft = 2.42 in.

REFERENCES
1. MECL System Design Handbook, Motorola Inc., 4th ed., 1988.

2. W. Sinnema; Electronic Transmission Technology, Prentice-Hall, Englewood Cliffs, New Jersey, 1979.

3. The Interface Handbook Line Drivers and Receivers Interface, Fairchild Semiconductor, 1st ed., 1975.

313
314
 AN1080
External-Sync Power Supply with
Universal Input Voltage Range for Monitors
By S.K. Tong and K.T. Cheng

ABSTRACT
days, switching power supplies replace the linear regu-
This paper describes the design of a low-cost 90 W lators due to high efficiency and light weight. However,
flyback switching power supply for a mUlti-sync color the EMI/RFI generated by switching power supplies has
monitor. In order to minimize the screen interference adverse effects on the resolution of high-definition color
from the switching noise, the power supply can be auto- monitors (e.g. 800x600 or higher). Asynchronous switch-
matically synchronize at the fixed frequency of the hor- ing noise beat with the horizontal scanning frequency of
izontal scanning frequency (15 to 32 kHz) of the color the color monitor, creating undesirable interferences and
monitor. The line and load regulations of the power sup- jitter on the screen. It affects the horizontal resolution of
ply are excellent. Also, a new universal input-voltage the high-definition color monitor because the random
adaptor enables the power supply to operate at two input pulses generated by the asynchronous switching oper-
voltage ranges, 90-130 Vac or 180-260 Vac. It can min- ation and also deflect the electron beams and blur their
imize the ripple current requirement of the input bulk precisely controlled positions. Thus, the switching power
capacitors and the stresses on the power switch. The supply for the high-definition monitors or TVs must be
design demonstrates how to use recently introduced synchronous with the horizontal frequency.
components in a low-cost power supply. The state-of- Recently, mUlti-sync color monitors became popular
the-art perforated emitter epi-collector bipolar power because they can adapt to several modes of computer
transistor MJE18004 and opto-isolator MOC8102 are displays. For examples, CGA, EGA and VGA display
utilized. modes are used in IBM PCs. The three di'splay modes
have different horizontal resolutions and scanning fre-
1. INTRODUCTION quencies, ranging from 15.7 kHz to 31.5 kHz. Hence, the
switching power supply developed in this note can be
As the resolution of modern color display increases, synchronize to the horizontal scanning frequencies of the
the power supply for these high-definition monitors mUlti-sync color monitor, as shown in Figure 1. It pro-
become critical in its features and performance. Nowa- vides three d.c. outputs. The specifications are:

MULTI,SYNC SIGNALS
FROM COMPUTER IH & V SYNC
AC LINE RGB SIGNALS,

-5V
,FOR LOGIC ICsl HIGH RESOLUTION
·12 v MULTI SYNC
POWER SUPPLY ,AUX POWER' VIDEO MULTI-SYNCH
DEVELOPED IN PROCESSOR COLOR DISPLAY
THIS NOTE RGB DRIVERS
·110 V & HV CIRCUIT

EXT SYNC H SYNC

DC ISOLATION

Figure 1. Block Diagram of Modern Multi-Sync Color Monitor

315
Outputs 4, the performance and further improvements of the
+ 110 V 0.7 A for HV, RGB drivers and deflection. power supply are discussed. In the last section, the con·
+ 12 V 0.3 A for auxilary use. clusions include a summary of the design of the power
+5V 0.2 A for logic ICs. supply and the future developments of switching power
Inputs converters suitable for multi·sync monitors.
90-130 Vac or 180-260 Vac 50/60 Hz
Power 2. DESIGN OF THE FLYBACK POWER SUPPLY
90 W with overload protection
Conversion Efficiency 2.1 TOPOLOGY SELECTION
Minimum 70% at full load The single-ended discontinuous-mode flyback topol-
ogy is selected to perform the major power transfer from
Others the rectified output (Vee) to the load. Advantages and
External synchronization with d.c. isolation (15 kHz to disadvantages of this topology are:
32 kHz) which are regarded power supply standards for
modern color monitors. The two low·voltage outputs are Advantages
obtained by post-regulators of the + 15 V and +8 V 1. It has smaller transformer size and output choke. The
inputs. power density and cost of the power supply are
In Figure 2, the block diagram of the switching power lowered.
supply, according to the specifications, is shown. Besides 2. Current mode operation is excellent because the cur-
the input filter, it mainly consists of three parts - the rent waveform fed to the current mode controller is
rectification circuit, the universal input-voltage adaptor strictly triangular. It can improve the noise immunity
and the 90 W flyback converter. of the current sensing circuit.
The universal input-voltage adaptor can automatically 3. Single-pole roll-off characteristic of the power con·
select the input·voltage range and controls the triac in verter simplifies the design of feedback circuits. [1]
order to provide the rectified d.c. voltage Vee in between 4. Simplified in design if single-ended configuration is
200 to 370 V. In 90-130 V range, the triac is continuously used.
fired and the whole rectification circuit forms a voltage 5. Good cross regulation. [1]
doubler. In 180-260 V range, the triac turns off and the 6. The working duty cycle can be greater than 50%. This
rectification circuit works as normal. This design can sig- is particularly important for mUlti-sync monitor power
nificantly reduce the current ripples ofthe two smoothing supply.
capacitors, Cin, and the switching stresses on the power 7. Lower cost than other topologies.
transistods) due to wide range of Vee. Some previous Disadvantages
designs without the universal adaptor handle the full 1. High RMS and peak transformer currents result in high
input-voltage range only by simple bridge rectification. losses in power switch, windings and voltage clamp.
The current ripple of the smoothing capacitors are usually 2. The large air gap in the flyback transformer causes
several amperes for 90 W power converters. Further- higher EMI/RFI and flux fringe.
more, the output voltage ripple (at VCC) is generally 3. Higher ripple current appearing in output capacitors
higher for the same value of smoothing capacitors at low produces greater output ripple voltage which may
line. cause screen interference. The switching frequency of
In section 2, the design of the flyback converter is the power supply is designed in synchronization with
reviewed, whereas the design of the universal input- the horizontal frequency. The adverse effect due to
voltage adaptor is given in section 3. Then, in section this point becomes less significant.

-110 V
10.7 AI
90-130 VAC INPUT
DR 180·160 VAC FILTER
-15 V
90W FLYBACK 10.3A1
CONVERTER -BV
IO.2M

E<r---,
OV

EXT SYNC

Figure 2. Block Diagram of Switched-Mode Power Supply for Multi-Sync Monitor

316
 4. Transformer and snubber capacitor ring after the mag- If the efficiency is taken into account and it is assumed
netic energy stored in the magnetic core is completely that the typical conversion efficiency is about 70%, the
released. This phenomenon can be often found in the total input power Pin is,
previous designs. Pin ~ 90/0.7 ~ 128.6 W
With the considerations of cost effectiveness, size, and
Then, the following problem is how to determine suitable
cross regulations, flyback topology is selected. It is par·
primary inductance Lp and maximum working duty cycle
ticularly suitable for 90 W switching power converter
D of the power transistor. Assuming that the primary
application. Disadvantages are minimized through care-
inductance and input power are constant,
ful design (see later).
Current-mode control is employed in this power supply Pin ~ Lp Ipk2 fs/2 (Energy law) (1)
because: Vee ~ Lp Ipkltc (Faraday's law) (2)
1. Inherent line ripple rejection (fJVo/fJVCC ~ 0) where tc ~ conduction time of the switch DT,
2. Eliminate the possible double-pole characteristics in T ~ 1/fs = switching period.
continuous mode. This would cause instability of the Hence,
power supply under some critical conditions. Pin = (VCC tcllpk fs/2 = Vec Ipk D/2 (3)
3. Discontinuous mode flyback topology has excellent
If we set D = 0.4 at Vee = 200 V, fs = 15 kHz and Pin
current mode operation due to large current
= 128.6 W, we have, from (3), Ipk = 3.215 A.
amplitude.
4. Synchronization is easier to implement without The current waveform is shown in Figure 4. Put Ipk into
greatly affecting the converter performances and cir· (1) or (2), then the primary inductance is calculated to be,
cuit configuration. Lp = 1.66 mH
5. Simple and low cost as commercial current-mode con· The duty cycle at Vee = 370 V is 0.216 under full-load
troller IC is available. condition. It becomes smaller as the load decreases. Also
UC3842A13843A, Motorola current mode control IC, is from (1), at same power level,
used in the power supply to perform the current mode
operation. The feedback from secondary side to primary 10k at 32 kHz = ~ = 0.6847
is through MOC8102, a new Motorola opto-isolator. Ipk at 15 kHz ...; 32
Ipk at 32 kHz = (0.6847) (3.215) = 2.2 A
Z.Z DESIGN OF FLYBACK TRANSFORMER and Dmax at 32 kHz = 0.4/0.6847 = 0.584
The lowest value of Vee is assumed to be 200 V, i.e. For the flyback converter operating in discontinuous
50 V below the rectified low-line peak voltage (180 x 1.414 mode at 32 kHz, the duty cycle with respect to secondary
~ 255 V), and the highest value is about 370 V. Therefore, side oftransformer D' = tdlT is set to 0.4, which is slightly
the flyback converter shown in Figure 3 should operate less than (1-0.584) = 0.416, because the remaining
within 200-370 Vdc. The total power is 90 W, slightly switching time is used to compensate other non-idealities
higher than the sum of all three outputs. The switching such as leakage inductances. stray capacitances, finite
frequency is from 15 kHz to 32 kHz with external switching fall and rise times, etc. To calculate the sec-
synchronization. ondary inductances, the power relation is used again. If
the output power (90 W) was lumped to + 110 V output,
from (3), at fs = 32 kHz and Vee = 200 V,
Vcc
FLYBACK TRANSFORMER
IVai

.OLTAGE
" D1'O -110 V Vos
CLA~P
I Col10
L_ "2 OV Vspk

Vcc-..nVo
-15 V
;:lC • ",~ ... ·o~~ !
S'cBBER
Co15 VCC
oV
TO CONTROLLER -8V

7~
'd Ie
C0 8
OV tspk

-0 CCRRE,-
SE".SE OF Ct-.1
CO",TROLLER
1 V PEAK
Rs
Vos
RA

Figure 3. Flyback Converter

(Discontinuous Inductor-Current Mode)
Jl
'''"',~-
/l
Figure 4. Switching Waveforms of Flyback Converter
~ I

317
 Po = 90 W = Va Ipk' D'/2 For ETD39 core, Ae is 124.15 mm 2. The required wire
where Po = net output power gauges of each winding are also listed in the following.
Va = output voltage of + 110 V Irms value is equal to (D/3)1/2 Ipk. At fs = 15 kHz, Ipk' =
Ipk' = peak inductor current of + 110 V windings 6 A and td = lB.2 ps, hence,
D' = tdlT = 0.4 (referred to Figure 3). D' = lB.2/66.67 = 0.273
Hence,lpk' = 4.1 A and td = 12.5 ps. Np = (200 x 0.4 x 66.67)/(0.25 x 124.15)
= 172 Irms = (0.4/3)1/2 x 3.215 = 1.17 A
Then, substitute Ipk' into (1) or (2), we have,
(AWG #23)
Ls (110) = inductance of + 110 V winding N s (110) = 77 Irms = (0.273/3)112 x 2 x 0.7/0.273 =
= 0.334 mH 1.55 A (AWG #22)
And, the inductances of other two windings are, N s(15) = 11 Irms = 0.66 A (AMG #26)
Ns(B) = 7 Irms = 0.44 A (AWG #26)
Ls (15) = Ls (110) (16/111)2 = 6.9/LH
NA = lB for MTP4N90 and NA = 13 for MJE1B004
Ls(B) = Ls (110) (9/111)2 = 2.2/LH.
(see later).
The diode drops of the output rectifiers are taken into
The ETD39 core will be used in the power supply due to
consideration for the two low·voltage outputs. The turn
ratio n is equal to, its round bobbin shape and efficient AP product [11. The
temperature rise of the transformer core is about 30°C.
n ~ N p/N s (110) = [L p/L s(110)[1/2 = 2.22 (4) To obtain an approximate length of air gap Ig, the cal-
where Np = number of turns of Lp (primary inductance) culation is based on:
Ns(110) = number of turns of Ls (110). 1. the reluctances of the magnetic core are negligible.
Two magnetic cores are found to be suitable for the 2. the air gap are in the middles of the three limbs, all
implementation of the flyback transformer. They are EE40 equal to Ig .
core and ETD39 core. The spacing factors are just around 3. the relative permeability /Lr is constant and equals
0.4 for both. The maximum working flux density Bmax 2000 for TDK H7C4 material.
is set to 0.25T. For EE40 core, the effective cross-sectional Hence, Lp = /La Np2 Ae/(2Ig) (5)
area Ae is 130.65 mm 2. or Ig = 1.4 mm
Np = (VCC tc)/(B max Ae) = (200 x 0.4 x 66.67)/(0.25 But, a 4 mm air gap is used practically to obtain the
x 130.65) = 163 required inductance due to flux fringe and other non-
N s (110) = 163/2.22 = 73 idealities. The transformer construction diagram is
Ns(15) = 11 shown in Figure 10. To meet with the world safety reg-
Ns(B) = 6 ulations (e.g. VDE, UL, CSA, etc.) for the transformer,
where Ns (15) = number of turns of Ls(15), and readers should refer to corresponding regulation books
Ns(B) = number of turns of Ls(B). and (4).

,-------_._-------------------_._------------

r'-iN4~'4-8~---~-~---~-8'_1Vrel vC;------------I'N4747A

0.1 ~F 1.' MOTOROLA = J M1

10 VCT UC3841A VO 6 10 MTP'N90

'--'=-.---'>--,,-+--"'-~--'-I' _.c; __ /~¢ "; 1_ '70 :F k

Rs
0.18
, GND

IVai -8V
-110
RopD
1 RE
Rx

"~
'F
Dop 03
C, MOC8101 1N3906

Rv TL431CLP

CONSTANT CURRENT SOURCE

Figure Sa. Current-Mode Controller and Sync Circuit for MTP4N90 (MOSFET)

318
 If the output ripple voltage is set to 1% of Va' i.e. 1 V,
-lOV oVa = 1 = 0.5x5.13x18.2/C o (1101
Coll101 = 46.68 p.F
However, the output ripple current 11.55 AI is so large
lN4740A
that two or more capacitors are needed to be connected
in parallel in orderto lower their individual ripple currents
and the additional output ripple caused by ESR and ESL
Vcc of the output capacitors. As a result, two of 22 p.F to 33 p.F
capacitors each with maximum ripple current of 0.8 A are
used in the power supply. Their maximum working volt-
MOTOROLA
age is 160 Vdc.
UC3843A
The dummy resistors Rno, R15 and R8 are used to
maintain minimum load currents of the three outputs.
CS~~--4N~-----+ Rn 0 is set to 5.6 k!1 and dissipates 2 W.
R,
r470PF 028 LC filter is cascaded with each output to lower the out-
put ripple voltage. They are shown in Figure 8. The comer
OTHERS ARE SAME AS IN FIGURE 5\dl frequency for that at + 110 V output is about 6.2 kHz and
the approximate output ripple voltage is,
1/[1 + 115/6.2)4Jl/2 = 0.1684 V Ipeak·to-peak).
Figure 5b. Current·Mode Controller and Sync Cir£uit
for MJE18004 (Bipolar Junction Transistor) 2.4 SELECTION OF SWITCHING TRANSISTOR,
SNUBBERS AND VOLTAGE CLAMP
2.3 DESIGN OF OUTPUT CIRCUITS Two types of power switches are considered for the
The following paragraphs describe how to determine flyback power supply. They are TMOS power FETs, and
the values of output capacitors and to select output rec- the state-of·the·art perforated emitter bipolar transistors
tifiers as shown in Figure 3. The ultrafast recovery rec· introduced in 1988. The new series of Motorola TMOS
tifier MUR140 is chosen for Dll0 due to its fast recovery FETs simplifies the design of driving circuits and provides
time 175 nsl, reliability and low cost. The maximum extremely fast switching transitions. These MOSFETs can
reverse voltage of this diode is 110 + 370 n = 277 V, so operate in the MHz range. In this power supply, although
400 V device is selected. The average current of Dno is the switching frequency is relatively low, it still provides
0.7 A maximum. D15 and D8 are schottky diodes, MBR160 several advantages such as simple drive circuit. less sup-
and 1N5819 respectively, because schottky rectifiers are ply current for the MOS driver, fast switching times which
more suitable for low voltage outputs. result in less energy loss at switching transitions, and
During td, the output voltage rises from its minimum hence a smaller value of snubber capacitor Cl 11000 pF)
value to its peak. is required. Since. the maximum drain voltage of Ml is
near 850 V Isee later), and the peak drain current is 3.2 A,
V0-
- _
Co1 _ J-at [I pk I 1101 -
(1101 !mill.1ill
td t] dt ~ Vo(mlnl
. MTP4N90 is selected for M 1, with 4!1 rDSlon) [5J. Thus,
the approximate conduction loss in Ml is [10.4/3)1/2 x
3.2J2 x 4 = 5.5 W at fs = 15 kHz, VCC = 200 V and full
= -c-l- [l pk(1101 t - !mill.1ill
110 + Vo(minl
0(1101 2 td t2] load. The power dissipation is well below the maximum
power that can be dissipated by the device.
It consists of a linearly increasing term and a convex To demonstrate the switching improvement of the
parabolic curve. Thus, newly introduced perforated-emitter BJT family, the
design of the flyback power supply also provides an alter-
V
olmaxl
= __1_
Co lll01
[I
pklll01
t _ !mill.1ill
2 td
t2] _
t-td native for a new device. MJE18004 is chosen for Ml
because its breakdown voltage VIBR)CES is above
+ Volminl
1000 V, the continuous collector current is 5 A and its
- ! l pklll0l t d + V . switching times are excellent for switchers below 70 kHz
- 2 Co lll01 olmlnl Itfi = 70 ns and tsi = 0.6 p.s at IC = 2 A. Ibl = 250 mA
and output ripple voltage is, and VElEloff) = - 5 V) [6J. Anothertwo important features
are its lower cost and power loss than the MOSFET. Its
oVa = Vol maxi - Volminl performance is quite different from the previous bipolar
_ ! Ipklll01 td transistors. For the triple diffused power transistors,
- 2 Co lll01 which are still widely used in Japan le.g. BU508). these
devices face three major problems: long switching times,
Since the maximum inductor current Ip klll01 at 110 V
dispersion of device characteristics, and hFE degrada-
rail is 5.13 A, and the output ripple voltage is maximum
tions after several thousand operating hours. The epi-
at f s = 15 kHz,
collector technologies which MJE18004 uses, improve
td = 0.273 x 66.67 p.s = 18.2 p's the switching speed and control of device characteristics.
ti = idle time las shown in Figure 41 Since the emitter of BJT affects the device performance
= T - tc - td = 21.8 p.s very much, various emitter structures have evolved. With

319
Motorola SWITCHMOOE III, with hollow emitter struc- this period. Since the discontinuous-mode flyback con-
ture, the speed and RBSOA improvements are accom- verter has greater peak inductor current, the effect of
panied by the increased die size (about' 25% of standard leakage inductance can be the dominant source of power
technology). For the perforated emitter structure, the loss. As shown in Figure 3, a voltage clamp for the leak-
emitter is interleaved by the base, thus, this increases age'inductance limits the spike voltage to a designated
the emitter perimeter to area ratio. That means higher value, Vspk. In [3]. it points out that voltage clamp is more
speed switching transistor can be fabricated in a smaller effective than shunt snubber in limiting the spike Voltage.
die size. It improves the operating frequencies and lowers It is actually a boost converter with an input voltage of
the cost. approximately nVo and the leakage inductance as switch-
In Figure 3, a dissipated RC turn-off snubber is shown. ing inductor. From power relation, neglecting the minor
Its function is to reduce the power loss of the transistor effect of the shunt RC snubber,
M, at turn-off by limiting the rising slope of VOS. It is L3 Ipk 2 fs/2 + nVo tspk fs Ipk/2 = (Vspk - VCC)2!R2
also called the dV/dt limiter. When M, turns off, the induc-
for C2R2 » "/f s
tor current begins to commutate from the power switch
to the snubber capacitor C, through the diode 0, within and from Faraday's law,
tfi. The snubber capacitor slows down the increasing rate Ipk L3/(V sp k - VCC - nV o ) = tspk
of VOS, so the VOS Is product area (during cross-over where L3 = leakage inductance in primary side. On
time) can be limited to certain acceptable value. This substitution,
snubber is particularly important for the old and slow
bipolar transistors. With the advents of TMOS FETs and -21 L3 Ipk 2 fs [, + nVo ]
perforated emitter bipolar power transistors, the snubber Vspk-Vcc-nV o
capacitance can be chosen to be as low as , 000 pF. As _ (Vspk- Vccl 2 (8)
the current fall-time of power transistor given in data - R2
sheets includes the effect of transistor output capacitance Note that although the above result is similar to that
(Cos s ), it is difficult to calculate an optimum value of C, shown in [3]. the leakage inductance which stores energy
which requires the fall-time information without the to be dissipated is merely L3, and the leakage inductances
effect of Cos s [2].[3J. in the secondary side only come into effect between point
Theoretically, the charge stored in C, at turn-off should A and B in Figure 4. The power loss due to L3 is essentially
be completely dissipated in R, when the switch M, turns same for all switching frequencies because Ipk 2 fs is con-
on. However, in the discontinuous-mode flyback power stant for same power level and VCC. At '5 kHz, the pri-
supply, it cannot always have that because severe stray mary inductance was measured to be 0.15 mH with major
oscillation which is caused by Lp and C, occurs when secondary winding (110 V output) short-circuited at zero
the energy stored in the magnetic core is completely dis- bias current. It is about one-tenth of Lp. So, L3 is equal
charged to the loads. This phenomenon is often seen in to 0.15 mH!2 = 75 JLH. If the peak voltage of M 1 is limited
previous designs. Therefore, the resistor R, has another to 850 V for MTP4N90, then,
function that it acts as a damper for the Lp-C, resonant 0.5 x 75 JL x 3.2 2 x 15 k x [1 - 244 (850-370-244)J =
circuit. Then, a compromise between the two opposing (850 - 370)2R2
operations should be considered. For a series LCR res- R2 = 19.67 kn (11.7 W)
onant circuit, the damping ratio can be used to control
the envelope of the damped sinusoidal oscillation. From For MJE'8004, Vspk is limited to 950 V and R2 = 33.8 kn
(9.95 Wi. Practical values of 20 kn (10 W) and 33 kn (10 W)
any standard text on linear control systems,
are used for MTP4N90 and MJE18004, respectively.
Dampmg ratio =
R, Ic,
iL- (7)
2 V p 2.5 CONTROL, BASE DRIVE AND EXTERNAL SYNC
CIRCUITS
If the damping ratio is set to " no undershoot below VCC
will result. The current-mode control IC selected is the UC3842A
or UC3843A. For MOSFET, MTP4N90, UC3842A is used
Thus,
to provide sufficient gate voltage because it is operated
, = 0.5 x R, x (,000pi,.66m),12 or R, = 2.58 kll at 20 V. The circuit configuration is shown in Figure 5(a).
In practice, a smaller value of R, will increase the dis- The maximum current-sense (CS) voltage on pin 3 of
charge rate of C, at turn-on. So, a standard value of 2.4 kll UC3842A is 0.9 V (minimum) [9J. Hence, the current sen-
is used. The maximum power dissipation of R, is equal sing resistor Rs is 0.9/3.2 = 0.28 n with power dissipation
to C, VCC(max)2 f s (max)!2 = 2.2 W, for complete dis- less than 0.5 W. Three' n ('·4 W) and one 2.2 n (1 4 W)
charge of C, during the conduction time of M,. But, due are connected in parallel to obtain the required resis·
to the stray oscillation caused by C" Lp and R" the resis- tance. A RC filter (' kn and 470 pF) is added to "kill" the
tor R, should have a power dissipation of 3 W. voltage spikes. The corner frequency of the filter is 339
Another RC snubber of '80 II and 470 pF used in the kHz.
power supply is to damp the stray oscillation caused by To be able to synchronize externally, the power supply
the junction capacitance of 0110 and the leakage induct- must have a free-running frequency below 15 kHz. For
ance [2J. the simplification of the design and operation of the oscil·
In Figure 4, a high-voltage spike (point A) in VOS is lation in UC3842A. a constant current source I, is used
caused by the discharge of leakage magnetic energy in instead of a resistor RT. Since the internal current source
the transformer. The time between A and B represents 12 in UC3842A provides a discharging current of 8.4 mA,

320
the dead time t2 and switching frequency can be deter- immunity and stability. Since the output voltage of the
mined as follows. error amplifier is from 1.4 (two diode drops) to 4.1 V (1.4
+ 0.3 x 3) typically [9]. and Ve is equal to (5 - output
11 = CT :~6andI2 - 11 = CT :~6 (12) 11) voltage of EA), the voltage Ve across RopE is from 0.9 to
3.6V.
12 - 11 t1 In the past opto-couplers have suffered from current
(9)
-11-=12 transfer ratio (CTR) degradation. The main cause for CTR
T = t1 + t2 = 1/fs degradation is the reduction in efficiency of the LED
The hysteresis voltage of the oscillator is 1.6 V. The time within the opto-coupler due to the increase in space-
periods t1 and t2 are the rise and fall times of the trian- charge recombination within the diode. Past industry LED
gular waveforms (VCT). Due to the effect of leakage burn-in data under accelerated conditions indicated that
inductance, other parasitics and snubber circuits at fs = a 15% to 20% degradation after 1000 hours was not unu-
32 kHz, the dead time t2 is set to 6-8 !JS. Then, if the free- sual. Of even more concern was the fact that the pop-
running frequency is assumed to be 12.5 kHz, t11T = 0.91, ulation also contained "fliers" units through infant mor-
tality mechanisms eventually exhibited degradations
12 - 11 0.91
approximately 50%. A typical percentage degradation is
-11- = 1 - 0.91
40% after 10 5 hours normal operation at If = 25 mAo In
or 11 = 0.756 mA and CT = 0.036 /-,F 1987, Motorola's Optoelectronics Operation decided to
The constant current source 11 is implemented u~ing a resolve the industry-wide problem of LED light output
single PNP transistor 03. The current gain of 2N3906 is degradation. They concentrated their efforts to improve
about 200. The current through RB1 and RB2 is assumed and control certain critical LED wafer processing steps
to be 20 x IB3, and the emitter voltage is set to 4 V since and eventually, 5000 hours of accelerated stress burn-in
the peak voltage of VCT is 3 V. Then, we have, testing shows zero degradation. This means that low deg-
radation characteristics are now achieveable not only on
RE = 1/11 = 1.32 kO
an average (mean) basis, but also that "fliers" can be
and IB3 = 0.756 mAl200 = 4 IJ-A. eliminated. Therefore, the opto-isolator can be regarded
Since VB3 = 5 - 1 - 0.7 = 3.3 V, as a low-cost, reliable, simple but high performance com-
5 x RB2/(RB1 + RB2) = 3.3 ponent to be used in future power supplies. Besides the
zero degradation of CTR, the new MOC810X series opto-
RB1/RB2 = 0.515
coupler that are specifically designed for switching power
RB1 = 20 kO and RB2 = 39 kO supplies provides two additional features. Their specifi-
The practical values for RE and CT are 1.2 kO and 39 nF, cations include tightly controlled window values of CTR.
and the free-running switching frequency is around Also, each device's internal base connection has been
13 kHz. The constant current source 11 can be directly eliminated, effectively minimizing the noise susceptibility
replaced by Motorola current regulating diode (1 N5294), problem. Noise is further minimized by coplanar die
which is a JFETwith gate-source short-circuited. The reg- placement, which puts the LED and phototransistor end-
ulated output current is actually its saturation current to-end, rather than one above the other. The result is a
lOSS at pinch-off. mere 0.2 pF coupled capacitance, which minimizes the
amount of capacitively coupled noise that is injected by
The external synchronization is achieved by the one-
the optoisolator.
shot triggering circuit built around 02. It is active once
MOC8102 is selected due to its moderate CTR (from
when the falling edge of sync pulse appears. Then, a
0:73 to 1.17 at IF = 10 mAl [111. Then, two extreme cases
single high pulse of 2 to 3/-,s charges the timing capacitor
are considered. For the lowest If delivered by TL431, it
CT through the charging resistor RC at a very fast rate
should provide sufficient coupled current to develop a
(about 50-100 times the normal rate). The value of RC
can be calculated by, minimum voltage of 0.9 V on RopE. The operating current
range of If is chosen to be 0.5 to 20 mAo For the highest
(5 - 2.8 - 0.5) ! (100 x 0.756) = 47 0 limit ofthe selected If range, i.e. 20 mA, the value of RopE
The minimum voltage drop on RC is approximately 5 - is 3.6 V/0.5 x 20 mAl = 360 0, if CTR is at the lowest
2.8 - 0.5 = 1.7 V because VCT swings between 1.2 to value, i.e. 0.5 approximately. Then, nearly whole ranges
2.8 V, with respect to ground [9]. and the saturation volt- of CTR and If are covered by the deSign with RopE equal
age of 02 is about 0.5 V. The choices of the input capac- to 360 O. The practical value for RopE is selected to be
itance and BE resistance can vary the pulse period. The 390 O. For the determination of RopD, the maximum LED
anti-parallel BE diode, 1 N4148 is to prevent the BE junc- current is considered. Thus, the value of RopD is (8 - 1)
tion from possible avalanche breakdown if the amplitude V/20 mA = 350 O. A 330 f1 resistor is used in practice.
of V sync is above 5 V. The feedback point is directly taken from the positive
It is also possible to combine the sync circuit into the terminal of the output capacitors Co (110). This point must
constant current source by injecting the sync signal into be placed before the output LC filter because the filter
the base of the current source transistor. forms an additional double-pole in the feedback loop.
The feedback scheme is selected as follows. A voltage Since the internal reference voltage of TL431 is 2.5 V, the
reference with comparator (linear error amplifier) TL431 values of Rx and Ry (the voltage divider) are chosen to
detects and amplifies the error signal, and drives the LED be Rx = 142 kfl and Ry = 3.3 kfl because, 110 Ry/(Rx +
of the opto-coupler MOC8102.. The gain of the error Ry) = 2.5 or Rx/Ry = 43 .
amplifier (EA) in UC3842A is set to unity for better noise

321
 The gate drive circuit consists of a series 10 n resistor rent-mode controller UC3842A13843A has a voltage hys-
to minimize the "gate ring" problem. But for MJE18004, teresis in under-volt lockout, the capacitance of CA must
the base drive circuit is not as simple as that for MOSFET. be large enough to maintain the initial switching oper-
It is shown in Figure 5(b). The supply voltage of the ations, i.e. the supply voltage must be kept above the
current-mode controller is lowered to 10 V in order to lower threshold point, before the power can be fed from
minimize the power loss in base drive circuit, and mean- the transformer. The practical values of CA are 3.3 J.LF for
while, UC3843A is used instead of UC3842A, which has UC3842A and 2200 J.LF for UC3843A. The much larger
a lower ON threshold of supply voltage. Other functions capacitance used in the latter case is due to the small
are identical to UC3842A. The typical hFE value for hysteresis of the supply voltage of UC3843A and the rei·
MJE18004 is 14 [6], and thus, it is assumed that the min- atively large base current. NA and RA for MJE18004 are
imum hFE value is 10 partly because of the tight control 13 turns and 10 n (1 W) respectively.
in manufacture. Then, the minimum base current IB is It is also possible to minimize the value of CA to several
3.2/10 = 0.32 A to maintain transistor saturation at full J.LF and to avoid long start time using a "kick" starter
load. A slightly larger base current of 0.35 A is used prac- described in previous Motorola Application Notes. The
tically. From [9], the voltage drop on the source output "kick" starter is actually a NPN high voltage, small-power
transistor of UC3843A is about 2 V at an output current transistor connected as a simple voltage regulator for the
of 0.35 A. And the value of VBE(sat) of MJE18004 is 0.95 V control circuit. The reference voltage is derived from a
[6]. Therefore, the value of base resistor RB is, zener diode biased by a resistor connected across + VCC
RB = (10 - 0.95 - 2)/0.35 = 20 n (1.2 W) and the base of the "kick" transistor. Its emitter is
regarded as output of the regulator and its collector can
The base drive capacitor CB can be determined by 11
be tied to + VCC. When the power supply is connected
(21TCSRB) '" f s (min)/2, i.e. CB = 1 J.LF. Note that the BE
to a.c. mains, the "kick" starter charges CA above the
junction ofMJE18004 will not have avalanche breakdown
start-up threshold of UC3842A13843A quickly. Then, the
because the breakdown voltage of BE junction is about
power for the control circuitry is fed from the auxiliary
9 V. Other optimum base drive circuits can be found in
windings (NA), which raises the d.c. voltage at the emitter
[7] (e.g., how to use base inductor to improve the turn-
of the "kick" transistor, and the transistor will be turned
off operation of power transistor).
off. Thus, the "kick" transistor conducts for a very short
As shown in Figures 3 and 5, the primary control cir-
time and dissipates very small power.
cuitry is self-supplied. The required power is delivered
from the transformer winding NA through DA and RA. A
zener diode of appropriate voltage rating is used to reg· 2.6 CLOSING THE FEEDBACK LOOP
ulate the supply voltage for IC1' For UC3842A and After determination of almost all the component values
MTP4N90, the supply voltage is 20 V and the total supply and configurations for the flyback power supply, the last
current is about 20 to 50 mA. Thus, NA is chosen to be but not the least piece to design is the feedback loop.
18 turns to provide an extra 5 V for regulation. RA is set Figure 6(a) shows the gain-block diagram of the flyback
to 47 n. Th smoothing capacitor CA is for filtering, but power supply. The input of the system is the internal
an unobvious effect of its capacitance is on the start-up reference voltage in the TL431 , which is 2.5 V ± 1%, and
transients of the primary control circuitry. Since the cur· is compared to the feedback signal. The H-block is purely

ERROR AMP FORWARD GAIN BLOCK IGI

Vref
·2.5V

VOLTAGE DIVIDER IR, & Ryl

Ho = 0.0227

Figure 6a. Approximate d.c. and Low-Frequency a.c. Model of the Flyback Power Supply

322
a voltage divider formed by Rx and Ry , thus the gain RopE = 390 n RopD = 330 D CTR = 1 (for MOC81 02)
value in this block is 3.3/(142 + 3.3) = 0.0227 = Ho. The Rs = 0.28 D Lp = 1.66 mH,
difference or error signal is then amplified by the error we have,
amplifier in TL431 , which is compensated externally. The
compensation network is chosen to consist of an inte- IGol = 229 or 47.2 dB
grating capacitor Cf and a resistor Rf. Thus, we have, It is observed that a local feedback occurs in the TL431
output circuit and the LED of the opto-coupler. Its end
A=~ (10) effects are:
SCfRf
where s = Laplace transform operator Ow for sinusoidal 1. loop-gain enhancement by the additional block con-
analysis), nected in parallel with A-block, i.e. 9/(111 Ho) = 3.57;
Rf = RxRy/(Rx + Ry) = 3.23 kD. 2. a proportional-integral (PI) controller resulted, instead
of a pure integrator.
The capacitance value of Cf can be determined for over- The overall gain (transconductance) of the feedback error
all stability of the power supply once when the forward
amplifier can be derived as follows.
gain G is known under the worst condition.
The low-frequency a.c. model for the discontinuous- iF = Vo (9/111) - Vo Ho A
mode current-injected flyback converter consists of a d.c. = [9/(111 Ho) -AI Ho Va
gain block cascaded with a single-pole roll-off network or iF/(H o Vol = 9/(111 Ho) - A (13)
which has a pole frequency at 1/( nCoRL). where Co is the where vo = a.c. component of Vo
total output capacitance and RL is thetotalload resistance
iF = a.c. component of IF (LED current).
at Vo [1]. The equivalent maximum load resistance
RL(max) is approximated by experimental measure- To simulate the equation (13). an additional block con-
ments at no load, fs = 32 kHz and VCC = 200 V (for sisting of 9/(111 Ho) only is placed in Figure 6(a). The
MTP4N90). The input current was measured to be 0.06 A zero frequency of the error amplifier is,
and thus, wf = 1/(3.57 CfRf) (14)
RL(max) = 110 2/(200 x 0.06) = 1 kD when IAI = 9/(111 Ho).
FQ,r the equivalent total output capacitance (for After knowing all equivalent a.c. gains of the converter
MTP4N90), the capacitances at three output circuits are circuit, we can determine the value of Cf for optimum
lumped to + 110 V output, and by charge relation, circuit dynamic performance. Since there is merely one
Co = [(110 V) (66 ILF) + (15 V) (330 ILF) + (8 V)
(470 1L)]110 V = 145ILF
Hence, the lowest corner frequency fp of the flyback Ip ~ 2.2 Hz II ~ 10 Hz tr ~ 40 Hz
power supply is approximately 2.2 Hz. If the ESR and ESL 100

of the output capacitors are neglected, the G-block has a

transfer function [1] as,
G=G o (l-sWp) (11)
where Wp = 2rrfp = 13.8 rad s.
The forward gain block G is subdivided into its indi-
vidual elemental blocks in Figure 6(a). They are the resis- r-...
tor RopD which converts the output voltage of TL431 into
the diode current for the LED of MOC8l 02, the non·linear
CTR (0.65 to 4.5 from data sheet), the resistor RopE which
r--.
generates a voltage Ve from the coupled current IC, the ~40

internal one-third divider of UC3842A13843A (the minus 001 IIkl 1000 Hz

sign is due to the inverting configuration of the op amp),
the current sensing resistor Rs which relates Vc to Ipk'
and finally, the gain of the power stage which includes --90
V
the signal pole. The d.c. gain of the power stage can be
directly derived from the power relation.
V0 2
RL
= ~ Lp I
2
k2 f
P s
"
~ II
or Vo = iLp RL fs
Ipk ~~2-
Thus,
Go = - (RopE/RopD) (CTR) JRL Lp fs (12) 1\
3 Rs 2
The value of d.c. gain Go can be determined analytically 13 5
by substituting parameters under worst case, i.e. fs = 001 Ilkl 1000 Hi
32 kHz and RL = 1 kn (including +8 V and + 15 V rails).
when the value of Go is highest. On substituting the Figure 6b. Bode Plot of the Flyback Converter at
known parameters. fs =
32 kHz and No Load

323
parameter that can be varied, i.e. Cf, and only one opti- diode lN5953A (1 W) is connected across the 110 V out-
mum condition (either gain or phase) can be satisfied, put rail. If abnormally high voltage (>150 V) continuously
we set the minimum phase of the loop gain to -120° to appears on this rail, the zener diode will be zapped to
guarantee the relative stability. That means Wf should be form a permanent short-circuit. Other better OVP circuits
placed 30/45 = 0.667 decade beyond Wp or, such as SCR crowbar circuit and 0 V shutdown circuit
Wf = 100 .667 Wp can be used with higher unit cost.
= 4.64 Wp = 64 radls Another option which may be required in the power
supply is short-circuit (not just overload) protection.
because the down slope of the phase of the flyback con-
Since the fly back power converter is operated with
verter gain is - 45°/decade and the PI controller has an
current-mode control, it is inherently over-power pro-
initial phase shift of - 90°. Then,
tected. But, if the outputs are short-circuited, maximum
Cf = 1/[(3.23 k) (3.57) (64)1 = 1.355 p.F power will be delivered to the low voltages with high
A practical value of 1.5 p.F is used. Plots for the overall output currents. Then, the output rectifiers and windings
loop gain of the power supply at fs = 32 kHz and mini- are likely to be' damaged. Short circuit protection is gen-
mum load is shown in Figure 6(b), with the following erally best installed in secondary output(s). Shutdown or
equations. foldback signal(s) can be fed to the UC3842A13843A by a
Motorola optocoupler.
A (f) = _1_ + _9_ = 206.4 + 3.57 To improve and control the start-up transients, a soft-
SCfRf 111 Ho JW
start circuit may be added to the current-mode controller.
G=~ where Go = 229
Wp = 13.8
Typical example can be found in [91.
1 + slWp
Ho = 0.0227 3. UNIVERSAL INPUT-VOLTAGE ADAPTOR
Gain (f) = 0.2 1091O I A' (f) x G x Hoi
The universal input-voltage adaptor is used with bridge
Phase (f) = Arg[A' (f) x G xl HoI rectification circuit to provide a rather narrower range of
The unity gain bandwidth is about 40 Hz (at fT) and the rectified d.c. output voltage at either low or high range
phase margin is about 82°. But, the dominant value in of input voltage, i.e. 90-130 Vac or 180-260 Vac. A sim-
the phase plot is its lowest value of - 128° at wf, where plified circuit block diagram has been shown in Figure 2,
the gain is greater than 0 dB. It determines nearly all and the detailed circuits are shown in Figure 7(a) and (b).
transient load responses. The voltage range selection is performed by an over-
voltage detector and the adaptor is supplied from a
2.7 OTHER OPTIONS charge pump circuit. At low range, the triac is fired con-
Under normal circumstances, the output voltage tinuously by the adaptor, and a voltage doubler is formed,
should not exceed 150 V. But, as protection for the mon- while simple bridge rectification is retained at high range.
itor circuits (it would generate X-ray if extremely high The rectified output voltage (VCC) range is from 200 to
anode voltage appears). an optional high-voltage zener 370 Vdc.

- VCC

1~5956A

'~5956A
11'\
90-130 VAC
OR 180-260 VAC 10

IN4001 L - - - - - - O START UP
MTI

T2

IN4735A
4K7 MC3423P 62 V
10k

30k
1'00

IN4001 560k

Figure 7a. Negative Gate (Triac) Current - Preferred

324
 . - - - - - - - - - -.......-.---..---<l+ VCC
47k

90-130 VAC
OR 180-260VAC
10
'--------OSTART·UP

lN4001

100 ~F
25V + 2M2
10k 5',

30k
1',

lN4001

Figure 7b. Positive Gate (Triac) Current

3.1 ADVANTAGES OF USING UNIVERSAL For the worst case, VCC(pk) = 180 x 1.414 = 255 V,
INPUT-VOLTAGE ADAPTOR VCC(min) = 200 V. Pin; 128.6 Wand fin; 50 Hz since
the lowest working voltage of the flyback power supply
Three advantages are gained by using the universal
is 200 V, and the frequency of input voltage is from 50 Hz
input-voltage adaptor. They are:
to 60 Hz. Therefore.
1. smaller ripple current in the smoothing bulk capaci-
tors for fixed output power; Cin = 205.6 IlF
2. less output ripple voltage at the rectified d.c. output The time period t a, the conduction time of the bridge
(VCe) at constant output power; rectifiers, is given by,
3. greatly reducing the stresses (voltage and current) on
the power switch of the flyback converter for constant
output voltage (V o ).

3.2 DETAILS OF CIRCUIT DESIGN

To select a suitable capacitance for the input bulk
capacitors Cin, the ripple voltage at VCC is considered.
Sketches of voltage and current ripples are shown in
Figure 7(c) and (d) for the following analysis. Figure 7(c)
is for normal bridge rectification, while Figure 7(d) is for
voltage doubler.
For simple bridge rectification. the ripple voltage WCC
is related to the capacitance of Cin as follows, from the
power relation. It applies provided that ta is much less
T/2,

"OO~
Pin = 1/2 (Cin/2) [VCC(pk)2 - VCC(min)2j (2fin)
or

Cin - 2 Pin 1 (16)

- VCC(pk)2 - VCC(min)2 fin
IA.C.ONLYI
and aVcc ; VCC(pk) - VCC(min)
where VCC(pk) = peak voltage at VCC = 1.414 x input
voltage (rms),
VCC(min) ; lowest voltage at VCC,
fin; frequency of input voltage. Figure 7c. Waveforms of Bridge Rectification

325
 capacitance is at its minimum. but the voltage on the

. ,C\~
other capacitor is at halfway between peak and minimum

v
voltages. VC(pk) and VC(min) respectively. The value of
VC(minl can be determined as follows.
VCC(min) = VC(min) + [VC(min) + VC(pk)]!2
or VC(minl = [2VCC(min) - VC(pk)]/3 (201
= 91 V for VC(pkl = 90 x 1.414 = 127 V
and VCC(min) = 200 V.
VCCIPkl~~ From energy law.
vee I" T .. I VCC!mm) Pin/2 = 1/2 Cin [VC(pk)2 - VC(minI 2] fin
or
"VCIPkl
C. - . Pin ..!.. (21)
-.:::F=--_/---::::!=- __1- In - VC(pk)2 - VC(min)2 fin
VCI "- • - T = 327.5 /LF at fin = 50 Hz and full load.
VCfminJ \... Vel \ Ve2
The time tao ripple currents Icap(pk) and Icap(rms) are
given by.

cos -1 [VC(min)]
VC(pk)
ta = 2". fin = 2.46 ms (22)
Icap(pkl

J'-----------'~~
Icap(pk) = 211" fin Cin VVC(pk)2 VC(min)2 (23)
= 9.18 A for CiIL= 330 /LF (practical value).
o
leap
IA.C ONLY)
Icap(rms) = Icap(pk) J:IT
ta
(24)

= 1.86 A
As the power supply is designed to operate at both
Figure 7d. Waveforms of Voltage Doubler input ranges. the latter case defines the relevant maxi-
mum ripple current. In order to demonstrate the effec-
tiveness of the universal input-voltage adaptor. the ripple
cos -1 [VcC(minl] current and voltage assuming no doubler are calculated
VCC(pkl to be. with Cin = 330 J.'F. Yin = 90 Vac and Pin = 128.6 W
ta = ---2-".--:f-in---'-- (17) at 50 Hz.
= 2.13 ms VCC(min) = [127 2 - 128.6/(60x165J.')]1!2 = 23.3 V
In order to evaluate the rms ripple current Icap(rmsl of 5VCC = 127 - 23.3 = 103.7 V (compared with 55 V
the smoothing capacitors Cin. a triangular approximation for high range)
is used to simplify the derivation. The a.c. peak current ta = 4.4 ms
Icap(pkl of Cin is.
Icap(pk) = 6.5 A
Icap(pkl
Sa dVCC
= 2 --;;t (18) Icap(rms) = 3 A (nearly double of the value with
voltage doubler).
= ". fin Cin VVCC(pk)2 - VCC(min1 2 Such a large ripple voltage at VCC will greatly stress the
switching transistor and will degrade the overall perfor-
= 5.5 A for the practical value of Cin equal mance. especially the conversion efficiency and
to 220 /LF.
regulation. .

Thl~:'p(rms) = Icap(pk) J~ = Icap(pk) J3~2 (19)

The bridge rectifiers are selected to be 1N5398. a 1.5 A
device because the highest average line input current is
0.9 x 128.6/90 = 1.3 A. The two 1 W resistors. in parallel
= 1.47 A with Cin. are used to discharge the input capacitor after
assuming that the a.c. component contributed by the powered off. Note that one of them is connected to "start-
switching operation of the flyback converter is negligible. up" at one end instead of the ground (the inverted tri-
This assumption holds because the high-frequency angular sign). It provides the starting current for the
(switching frequency) ripple current is filtered by the current-mode controller and drive circuit at initial power-
additional small-valued capacitor (0.1 /LF) connected on. when the control circuitry is still not self-supplied.
across VCC. The start-up current is limited to approximately 2 to
With reference to Figure 7(d). for the voltage doubler. 4.6mA.
the two capacitors are alternatively charged to peak line The inrush input current is limited to an acceptable
voltage. Note that whenever the rectified voltage VCC is level by the thermistor which has a resistance of 5 n at
at instantaneous minimum VCC(min). the voltage of one room temperature and 1 (1 after heated up.

326
 MAC229AS has been found suitable for the triac in the To calculate a suitable value for the charge-pump
universal input-voltage adpator because of the following capacitor C, the working principle of the charge pump is
points: first considered. It consists of two diodes (1 N4001), a
1. It is a sensitive gate device with IGT of 10 mA maxi- coupling capacitorC, and a smoothing capacitor (100 !,-F).
mum for operation quadrants I, II and III [131. The small C is charged during the rise time of input voltage and is
gate current requirement will minimize the power dis- discharged during fall time. Assuming that the voltage
sipation in the adaptor and will lower the capacitance drop on the charge pump circuit is much less than the
of the charge-pump capacitor C. peak of input voltage (Vp), from charge balance principle,
2. 'Its breakdown voltage is 600 V, which exceeds all input
voltage limits. Q = (2Vp) C = IT
3. Guaranteed 25 V//lS, rate of rise of off-state voltage or C = (IT)I(2Vp)
ensures the accurate operation of MAC229AS [131. where I = average d.c. current supplied to the line
4. Low power loss in the device due to its low voltage
adaptor.
drop across MT1 and MT2 at operation.
MC3423 is originally designed for overvolt "crowbar" The boundary case is at low line, low range, where Vp
sensing circuit, but it is also applicable in the universal = 127 V and I = 10 mA for gate current plus 6 mA for
input-voltage adaptor because of the similar working bias current. Thus,
condition [141.lt has a temperature-compensated internal C = [(10 + 6) (1/50)11(2 x 127) = 1.2!,-F
reference voltage of 2.6 V which is connected to one
terminal of the input comparator. Thus, if the trip point At high line, high range, Vp = 370 V and the maximum
at which the triac is turned off is set to 135 Vac or 191 Vdc, value of I is 53 mA at 60 Hz. The maximum power con-
the divider ratio in Figure 7(a) is, sumption of the line adaptor is 7 x 0.053 = 0.37 W. The
2.6 = 191 x R2/(Rl + R2) 10 n resistor in series with C is used to limit the inrush
current when starting.
or Rl/R2 = 72.5
So far in the design of the universal input-voltage adap-
Rl = 2.2 Mn and R2 = 30 kn. tor, an important point which has not yet been considered
The internal constant current source (pin 4) can provide is the hazard of severe overvoltage at VCC during start-
a time delay before tripping the "crowbar" SCR. It results up. If the power supply is started at high line, high range,
in better noise immunity and controlled start-up tran- Yin = 260 Vac, during the falling edge of input voltage,
sients of the adaptor. The practical values of the capacitor and the supply voltage of MC3423 is charged to about
and resistor connected at pin 4 to ground are 50 nF and 7 V, the triac will be turned on for the doubler operation
560 kn, respectively, which has a time delay of approx- in the remaining negative cycle of input voltage, without
imate 650 !,-S. The output is connected, through a resistive the gate capacitor CG, since MC3423 had not yet and
divider, to a small-power SCR (MCR102 with IK(max) = would not be tripped until the next positive cycle. Then,
O.S A). When the input voltage is detected to be above the lower bulk capacitor will be stressed to nearly double
the trip point, the SCR is fired to shunt all the incoming of its normal voltage rating. This harmful effect not only
current from the charge pump, and the triac will remain damages the bulk capacitor, but also produces abnor-
off. mally high input voltage (VCe! for the flyback converter,
The MC3423 can operate from 4.5 V to 40 V of supply in a small instant. Therefore, CG is connected to the gate
voltage [151. Hence, a 6.2 V zener diode is used to clamp and MTl terminal of the triac to serve two purposes:
the supply voltage of the crowbar senser to 6.2 + 0.7 = 1. ·to delay the turn-on of triac for nearly a quarter of one
7 V for stable operation. A 100 pF filtering capacitor for cycle.
the sensing divider and a small-signal diode lN414S for 2. to increase the dV/dt blocking capability of the triac
clamping the input of MC3423 are also added in the (> 200 V//lS) and hence, the overall system reliability
circuit. [131.

HAZARDOUS RANGE
FOR VOLTAGE DOUBLER

Figure 7e. Worst Case Consideration for the Universal Input-Voltage Adaptor (Negative Gate Currentl

327
 4x lN5398

r----------------------------,
I 2A ~: ~~: i
lo-~~--q ~~~~-<

9O-IJO VAC
OR 180-260 VAC 270k
50160 Hl lW

No---~~------~~~~
i
I
' - - - - - _ < > START·UP
I
I

E ~ THE DEM~~O~~-----------------J T1
MAC229AB
....... _________ ..J lN4001
r-~~-+~~------------~------~~~~~~

UNIVERSAL
100"F INPUT·VOlTAGE
25V + ADAPTOR
10k lN4735A

560k

Vce
180

..;..110 V
+-.r--rt~-.,....""",,-..,...- ......--o 10.7 AI
20\ lK2
lN595JA
IOPTIONAll
'---~~~~-----+--+~_<>OV

O.l~
r-~~H-~~~'-~-----+_<>+15V
l' 10.JAI

'-~~~~------+------+_<>ov

r-~~~_~~vv~~~-+_<>+8V
10.2 AI

'-~~~--~------+--+-+_<>OV

10

1\ 142\
JJO
I',
~470PF 0.28
0.5W MOC8102 *
1~5
START·UP
3KJ
1°'0 Tl4J1ClP
MOSFET Bipolar
MJEI8004
FOR MTP4N90 MJE18004

ICI ICI UC3842A UC3843A

RA 47 10
CA 3,,325 V 2200" 16 V
0.28
DZ lN4747A lN4740A
____ J HEATS!NK
NA 18T 13T
Start-up 20 V 10 V
R2 20 k 33 k (lOW)

Figure 8. Complete Circuit Schematics of 90 W Off-the-Line Power Supply

328
The determination of the capacitance of CG is determined 4. PERFORMANCE OF THE FLYBACK POWER SUPPLY
as follows, with reference to Figure 7(e). At high line, high
4.1 COMPLETE CIRCUITRY
range, and 60 Hz, the average current I is maximum
(53 mAl. All discussions below are referred to a falling Figure 8 shows the complete circuit schematic of the
edge and the consecutive rising edge of less than 1/4 90 W flyback power supply. The triac in the universal
cycle of input voltage, because the charge-pump capac- adaptor is negatively driven by the charge pump, since
itor C is discharging to the adaptor circuit during fall time TOP VIEW
and the crowbar senser cannot be tripped if Yin falls
beyond + 200 V. If the supply voltage for MC3423 is just
about 4.5 V, the crowbar sensing IC functions, and mean-
while, the instantaneous input voltage is at the trip point
(200 V) and is going to the negative cycle, the gate capac-
itor CG must be large enough to delay the conduction of
the triac before the input voltage rises again, i.e. at the
negative peak. Assume that, for simplicity, the supply
voltage of MC3423 rises to about 6.2 V (zener voltage)
when the input voltage falls to - 200 V. Then,
tx = charging time of the capacitor across the supply C C N N L NC
voltage of MC3423 Figure 9a. Universal Input-Voltage Adaptor (+ IG)
= 2 x sin -1 (200/367) 1 (2". x 60) = 3 ms TOP VIEW
= (6.2 - 4.5) V x (Capacitance value) 1 (53 - 6) mA
or capacitance value = 100 /LF (connected across
supply voltage of MC3423)
But this capacitance is necessary to meet the ripple volt-
age requirement of the adaptor circuit. Afterwards, the
zener diode (1 N4735A) conducts, and the two capacitors
connected in parallel are needed to delay the remaining
time ty before the input voltage rises from its negative
peak again, within the same negative cycle. Therefore,
ty = (16.67/4 - 3/2) ms = 0.7 V x (CG + 100) /LF/47 mA NC
since the threshold gate voltage of MAC229A8 is 0.7 V Figure 9b. Universallnput·Voltage Adaptor (-IG)
typically.
CG = 79/LF
A practical value of 100 /LF is used in Figure 8. Note that
the discharging current of C at zero-crossing of input
voltage is greater than the average value I. The time con-
stant of the gate capacitance and gate resistor (1 kn) is
0.1 s, which is sufficient for resetting the triac between
consecutive power-off and on. The 10 kn resistor is for
discharge of the 100 /LF capacitor, and the corresponding
time constant is 1 second. Time constants too long in the
above design may result in failure of the universal input-
voltage adaptor if the power supply which was previously
socketed in 110 V line is quickly plugged in 220 V line.
It should be noted that two optional power zener diodes
(1 N5956A) are connected across each bulk capacitor Cin
because:
1. they can absorb short transient voltages (>200 V) on
Cin,
2. they can prevent any failure of the universal input-
voltage adaptor from damaging the flyback converter
and the two bulk capacitors.
Although such failures are rare the consequences are
to be avoided since failure of the line adaptor poses a
safety hazard to the human beings (especially the eyes
radiated by X·ray). N.B. VALUE, VALUE UC3841A. 1N3906, 1 MOTOROLA HK 1·8·89
FOR fOR UC3843A
Common-mode and differential-mode EMI/RFI filters
fET BIPOlAR
are generally required for all switching power supplies.
They are included in Figure 8, but are excluded in the Figure 9c. Main Board (for MTP4N90 & MJE18004)
DEMO board.
Figura 9. PCB and Componant Layouts (not full size)

329
 TRANSFORMER CONSTRUCTION DIAGRAM
BOnOMVIEW

L,11101
N,I1101 = 77
AWG#11
10iBI
lp = 1.5tol.75mH
Np = 171
AWG #13
N,I151 F
1F['"==~==-====1IN'IBI
• N,11101
.
N,IBI = 7
AWG #16
L,I151 LA
NA
•
I Np
PRIMARY·TO·
SECONDARY
INSULATION
' I.1....-_ _ _ _---'-,
N,I151 = 11 NA = 18 AWG #16 If01 MTP4N9fl1
= 13 AWG #16 If01 MJE1BOO41 CENTRE LIMB OF FERRITE CORE
AWG #16
FERRITE CORE: TDK ETD·39 H7C4
BOBBIN: TDK PST·39
AIR GAP. 19 • 4mm APPROX.

Figure' O. Flyback Transformer Construction

it is least sensitive to noise in this mode. Drive circuits 4.2 EXPERIMENTAL MEASUREMENTS AND RESULTS
for MTP4N90 and MJE18004 are also shown. D.C. measurements are summarized in Table 2. Line
Sometimes, it is unnecessary to have the universal and load regulation are excellent (better than 0.5%) for
input-voltage adaptor because the power supply may be the + 110 V output. Regulation for other two rails is within
used only at one range. Then, a modular approach for 10%, if the transformer is properly manufactured. Con-
the adaptor can lower the system cost and can increase version efficiency, is close to the expected figure (70%),
the flexibility of manufacture. The universal input·voltage and the best one is 73.7% at 10 (110) = 0.7 A, fs = 15.7 kHz
adaptor board can be simply removed or unplugged from and VCC = 360 V for MTP4N90; whereas for the bipolar
the power supply board without affecting the normal power transistor MJE18004, the best efficiency is 74.2%
operation of the power supply, if the adaptor is not at 10 (110) = 0.7 A, fs = 15.7 kHz and VCC = 360 V.
needed. Therefore, using this approach, the adaptor Although MJE18004 has lower conduction loss than
becomes optional. The printed circuit board and com· MTP4N90, it has higher power losses in the base drive
ponent layouts of the universal input-voltage adaptor(s) circuit and in the switching transitions. This is why
and the main board of power supply are shown in Figure MOSFETs can compete with advanced BJT even with
9. The construction diagram of the power transformer is higher conduction loss at relatively low switching
shown in Figure 10. Table 1 lists all Motorola semicon- frequency.
ductor components used in this power supply. The maximum ripple voltage at 110 V output is approx-
imately 150 mV (peak·to-peak) which is less than 0.2% of
Table ,. list of Motorola Semiconductor Components the output voltage, as predicted in section 2.3. The power
supply is observed to be stable over the entire range of
Part Numbers Qty. load currents. The dynamic response is also satisfactory,
with an overshoot of less than 8 V at fs = 15.7 kHz and
IC UC3842A (for MTP4N901 1
VCC = 200 V, from half· load to full-load (see Figure 1).
UC3843A (for MJE180041 1
MC3423P 1 Also in Figure 12, the transient responses of the power
TL431CLP 1 supply are introduced for very large-signal disturbances
- from no load to full-load. The overshoot is about 20 V
Opto MOC8102 1 and the undershoot is over 30 V, which is quite satisfac-
MOSFET MTP4N90 1 tory. The overshoot can be further reduced by increasing
SCR MCR102 1
the integrating capacitance Cf in the feedback loop. But,
this will result in slower transient responses.
TRIAC MAC229A8 1 Typical experimental switching waveforms are shown
BJT MJE18004 1 in Figure 11, at different load currents,·input voltages and
2N3906 2 switching frequencies. Also, Figure 13 shows the photo
Rectifier 1N4001 2
of the 90 W off-the-line power supply.
1N5819 1
5. CONCLUSION
1N5398 4
MUR140 1 A low-cost 90 W flyback power supply with external
MUR180 2 synchronization and universal input-voltage adaptor for
MBR160 2
mUlti-sync color monitor has been discussed in detail.
Zener 1N4735A 6.2 V 1 The power supply has excellent line and load regulation
1N4740A 10 V (for MJE180041 1 and is found to be suitable in the application of low-cost
1N4747A 20 V (for MTP4N901 1 mUlti-sync color monitors or TVs. Also, it can operate at
1N5953A 150 V (optionall 1 both a.c. mains, i.e. 90-130 V or 180-260 V, without
1N5956A 200 V 2
greatly affecting the system cost and performance.

330
 Table 2. Performance of 90 W Off-the-Line Flyback Power Supply

MTP4N90 (MOSFET)
10 (11DV) V o (11DV) (15 V) (B.DV) Is lin Vee Efficiency
0.2 110.1 16.01 8.88 15.7 0.12 300 61.2
0.5 110.0 16.23 9.05 15.7 0.26 300 70.5
0.7 109.9 16.31 9.10 15.7 0.35 300 73.3
0.7 109.9 16.32 9.10 15.7 0.55 200 69.9
0.7 109.9 16.30 9.10 15.7 0.29 360 73.7
0.2 110.1 15.99 8.88 25.0 0.13 300 56.5
0.5 110.0 16.19 9.03 25.0 0.26 300 70.5
0.7 110.0 16.25 9.08 25.0 0.35 300 73.3
0.7 110.0 16.26 9.07 25.0 0.53 200 12.6
0.7 109.9 16.25 9.08 25.0 0.29 360 73.7
0.2 110.1 15.98 8.88 32.0 0.13 300 56.5
0.5 110.0 16.17 9.03 32.0 0.26 300 70.5
0.7 110.0 16.23 9.07 32.0 0.35 300 73.3
0.7 110.0 16.24 9.07 32.0 0.53 200 12.6
0.7 110.0 16.23 9.97 32.0 0.30 360 71.3
A V V V kHz A V %

MJE18004 (Bipolar)
10 (11DV) Vo (110V) (15V) (8.DV) Is lin Vee Efficiency
0.2 110.8 14.41 8.82 15.7 0.12 300 61.6
0.5 110.7 14.65 9.00 15.7 0.26 300 71.0
0.7 110.6 14.82 9.11 15.7 0.35 300 73.7
0.7 110.6 14.73 9.06 15.7 0.54 200 71.7
0.7 110.6 14.83 9.11 15.7 0.29 360 74.2
0.2 110.8 14.44 8.83 25.0 0.13 300 56.8
0.5 110.8 14.70 9.02 25.0 0.27 300 68.4
0.7 110.7 14.78 9.09 25.0 0.36 300 71.8
0.7 110.7 14.77 9.08 25.0 0.53 200 73.1
0.7 110.7 14.78 9.09 25.0 0.30 360 71.8
0.2 110.8 14.43 8.83 32.0 0.13 300 56.5
0.5 110.8 14.68 9.01 32.0 0.27 300 68.4
0.7 110.7 14.75 9.07 32.0 0.36 300 71.8
0.7 110.7 14.75 9.07 32.0 0.54 200 71.8
0.7 110.7 14.75 9.08 32.0 0.30 360 71.8
A V V V kHz A V %
<fRlpple voltage at 110 V output IS about 150 mVpp at Vee = 300 V, fs = 15.7 kHz & 10 = 0.7 A.

Figure 11. Experimental Oscillograms

20V A 10",5 938V VERT CHl SV A 10",5 135V VERT

C"' 10",s 40000,.,.5 CHl IOOV

IS 25kHz
Vee 300 V
lo··O.SA
MJE1BOO4

RF3gnd

_ _p..___ __
RF4gnd
CH29nd ......_jIo.o_ _ _ ~;;.. """'~ ~-+

CHIgnd

CH2gnd

Rflgnd ...._L-_-'-_-'-~_....J-_-'-_~....._ _ f-----' CHlgnd ~=:"'--4.._~::!::;::=~_-.J."...III:!!~::r~:::'_-.J

CH2 FREQ 25126kHz

Figure 11a. Key Waveforms at fs = 25 kHz and Figure 11b. VeE and VBE at f5 = 25 kHz and
Vee =
300 V (for MTP4N90) Vee =
300 V (for MJE18004)

331
 Figure 11. Experimental Oscillograms

CH. 10' A !Op.s 898V VERT

CII2 200' CHI
CHl
"V
,oov
A 10J,tS 8911/ VERT

IS lS.1kHI Is ·-157kHz
Vcc- l6OV Vee ~ 200 II
10 C7A '0·07A
MTP4N90 MTf'4N9(l

CH2gnd

CHlgnd4.0"",_ _""""",:::Hl~FR::EQ~'::":::1J:::kH~'J-"""_ _ _ _"""_L._...J

CH2 FREQ 15674 kHz

Figure 11c. VOS and VGS at fs = 15.7 kHz and Figure 11d. VOS and VGS at fs = 15.7 kHz and
Vee = 360 V (for MTP4N90) Vee = 200 V (for MTP4N90)

CH. 20V CH, lOY

A 10JLS 8.9811 VERT
CH2 100' CHl 100 V A 10"s 8.98V vERT

I, 25kHz
Vee
la
,."
07A
's",25kHZ
VCC"'200Y
MTP4N90 '0 '" 07A
MTIl4NSO
1'--1 ~ ~

CH2gnd

"'"" - --,
- ....

CHlgnd
r
CH2 FRED 2S.000kHl
.l r CH2 FREO",25.QOOkHz

Figure 11e. VOS and VGS at fs 25 kHz and = Figure 11f. VOS and VGS at fs = 25 kHz and
Vee = 360 V (for MTP4N90) Vee = 200 V (for MTP4N90)

CHI
CH2 '"
100 V
A 10J,ts 9691,1 VERT CH'
CHl '"
'00 V
A IOp.s 92211 VERT

IS 32kHz
's=32kHl
Vee 36011
'.'CC=200V
'0 07A.
'0 '" 07A
MTP4N90 MTP4N90

CH2 FREO 31646Hlz

CH2 FRED 32051kHl

Figure 11g. VOS and VGS at fs = 32 kHz and Figure 11h. VOS and VGS at fs 32 kHz and =
Vee =
360 V (for MTP4N90) Vee = 200 V (for MTP4N90)

332
 Figure 12. large-Signal Transient Load Responses

CHI
CH'
,,,
lOV
A lOOms 7113mV V£RT
CHI
CH'
lOV
5V •
A lOOms 71)3mV V£RT

HALF·LOAD TO FUlL·LOAD

..-. .-
Is '" 1~ 7 kHz
VCC"200V
MTP4N90
CHlglld

- ~
l-
I I,
Vee
157kHz
'00 V
MTP4N90

CHlgnd CHlgnd

CHlgnd

CH2 FREO '" 19841 Hz CH2 FRED 20161 Hz

Figure 12a. For MTP4N90, From No Load to Full-Load Figure 12b. For MTP4N90, From Half-Load to Full-Load
at fs = 15.7 kHz. at fs = 15.7 kHz.

CHI lOV CH1 10V

A lOOms 414V VERT CHl 5V A lOOms 414V VERT
CHl
'"
Is 157kHz
NO LOAD TO FULL·LOAD Vee 200Y
MJEl8004

HAlF·LDAD TO FUll LOAD

'S,,15.7kHz
VCC",200V
MJE1B004

Cl-+lg~d"",_"",_"",_""_""""_,,,,,_..L.._-'-_""""_--''''''''''' CH1Gnd ....._ ....._ ...._ ...._ ........._ ...._..L.._-'-_........_--'........I.

Figure 12c. For MJE18004, From No Load to Full-Load Figure 12d. For MJE18004, From Half-Load to Full-Load
at fs =
15.7 kHz. at fs 15.7 kHz. =
CHl 10V CH1 lOV
A lOOms 703mV VERT A lOOms 703mV VERT
CHl 10V CH2 5V

NO LOAD TO FULL·LOAD
HAlF·lOADTO FULL·LOAD

.....
y -
's"'32kHZ CH2gn d
Vcc = lOll V

~
MTP4N90 I, 32kHz
Vee 100 V
MTP4N90

I I
CH2gnd

CH2 FRED = 19920Hz CH2 FRED 2 0000 Hz

Figure 12e. For MTP4N90, From No Load to Full-Load Figure 121. For MTP4N90, From Half-Load to Full-Load
at fs =
32 kHz. at fs 32 kHz. =
333
ACKNOWLEDGEMENTS [4] G. Chryssis, "High-Frequency Switching Power Sup-
plies: Theory and Design." (2nd edition) McGraw-
In the course of preparing of the manuscript, several Hill Publishing Company, 1988.
persons gave their contributions to aid the completion of [5] Data sheets for MTP4N90 (Motorola Power MOSFET
this application note. Mr. T.S. Au, a summer student from Transistor Data - DL 135 R3)
H.K. Polytechnic helped to draft all P.C.B. and component [6] Advanced data sheets for MJE18004 (Motorola
layouts and to prepare demo boards. Mr. Cedric Lai, a Semiconductors Ltd.)
cooperative student from H.K. University, reviewed the [7] W. Hetterscheid, "Base Circuit Design for High-volt-
script with great care. Also, continual supports from age SWitching Transistors in Power Converters,"
Power Group of Discrete Business, Motorola Semicon- Mullard Technical Note 6, p. 1-14, 1974.
ductors H.K. Ltd. was proved to be essential to the suc- [8] AI Pshaenich, "The Effect of Emitter-base Avalanch·
cess of our works. We, Cheng and Tong, must express ing on High-voltage Power Switching Transistors,"
our thanks to these helpful people at the end of our article. Motorola Application Note AN803, p. 1-16, 1979.
[9] Data sheets for UC3842A (Motorola Linear and Inter-
REFERENCES face ICs - DL 128 R2)
[10] Advanced data sheets for MC44602(Motorola Semi-
[1] SEM-500, Unitrode Power Supply Design Seminar. conductors Ltd.)
Unitrode Corporation: Lexington, MA. 1986. [11] Advanced data sheets for MOC810X (Motorola
[2] K. Harada, T. Ninomiya & M. Kohmo, "Optimum Semiconductors LTd.)
Design of RC Snubbers for Switching Regulators," [12] "Guide to Thyristor Applications," Motorola Appli-
IEEE Trans. on Aerospace and Electronic Systems, cation Note AN849, p. 1-7, 1982.
Vol. AES-15, No.2, p. 209-218, Mar. 1979. [13] Data sheets for MAC229A8 (Motorola Thyristor
[3] W. McMurray, "Selection of Snubbers and Clamps Device Data - DL 137 R1)
to Optimize the Design of Transistor Switching Con- [14] Data sheets for MC3423P (Motorola Linear and Inter-
verters," PESC '79, p. 62-74, 1979. face ICs - DI128 R2)

Figure 13. Photo of 90 W Off-the-Line Power Supply

334
 AN1092
Driving High Capacitance DRAMs
In An ECl System

INTRODUCTION OOA

In present day computer/controller systems where speed DO 0 0

and efficiency are of the utmost importance, system designers
are using mixed technology in their designs to achieve the nec- EN OOB
essary speed, power, cost and processing capability desired in
R
high speed data processing systems. IVT01--- OVTOI
The logic type most applicable to the high speed function of
such a system is Emitter Coupled logic (ECl). Motorola's'
IGNOO1---
10K, 10H, and ECLinPS devices make it possible to operate 01A
with clock rates up to 1 GHz. However there are sections of a
system where ECl speeds are not necessary. For example, in Dl D 0
the area of bulk memory that is not accessed every clock cycle
a large CMOS DRAM is less costly, uses less power and takes EN 01B
up less board space per bit than an ECl memory. Now, since
R
ECl and CMOS are of different logic forms and their signal lev-
els are nat compatible there needs to be a level translation to
enable the two logic families to be used together. The Motorola
MC10H/100H660 4-BIT ECl-TIl lOAD REDUCING DRAM 02A
DRIVER was designed forthis purpose. The H660 is shown in
a simplified typical system application in Figure 1. D2 0 0
This paper will explain the features that were designed into
the H660 and how to apply them in a mixed technology system EN 02B
to obtain the best performance versus power ratio.
R
IVT23--- OVT23

Eel BUSS - TTL BUSS

IGN023---
03A
H660 MOS
Eel DRAM
03 0 0
SYSTEM
- EN 03B

I Eel BUSS
H600
TTL BUSS
R

Figure 1.

SYSTEM DESIGN MC1 0/1 00H660 logic Diagram

To switch highly capacitive loads at speeds of a few nano-

seconds, the device must supply a large amount of current to FEATURES OF THE H660 DRAM DRIVER
charge the lines then it must sink this current to discharge
them. This fast switching on an unterminated line can result in The H660 translates the ECl signal to a TIL level suitable
a substantial amount of over shoot and ringing. for driving DRAM memories with high input capacitance.
To eliminate the overshoot and ringing, a small value series The input impedance of the 660 varies with frequency, at 10
resistor (Rs) can be placed at the driver. Figure 4 shows an MHz it is typically about 150 to 250 ohms and goes down to
application of the H660 with a series resistor. about 50 to 60 ohms at 200 MHz as shown in Figure 2.

335
 A latch is added to provide the capability for a memory con-
300 troller to propagate new addresses to different banks without
having to wait for the address timing constraints to be satisfied
from a previous memory operation, For system implementa-
tions where this is acceptable, the user has the capability to
w 200 keep the latch open, thus having the part act as an address

~
W
\ translatorlbuffer, with minimal performance impact due to the
additional propagation delay incurred from the internal latch.
D-
~
100
\ The latch is controlled with an already existing ECl level
DRAM timing signal.

"- / I~PEDANCE

100 200
FREQUENCY, MHz Figure 4.
Figure 2, Input Impedance The graphs in Figure 5 and 6 show that by adding the series
resistor the device ICC dynamic current is significantly re-
For every ECl input there are two output lines, each capable duced while the propagation delay is only slightly increased,
of driving 300 pF. Assuming 5 to 15 pF capacitance per pin for 1
megabit of DRAM, each output pair could be connected to 40 250 Rs=O
megabits of DRAM. ./
The H660 has a totem type TIL output stage with no lOS
200
/ Rs=5
limiting resistor. The output Isink capability is 48 mA, The out-
/ ....- "7
--- --
put transistors are driven differentially with a dual phase split- Rs=10
«
ter from the translator, this assures that both the output totem E / / Rs=20
transistors will never be turned on at the same time therefore,
with no load, ICC dynamic power remains constant over fre-
13 150 ./ ~~
quency. We recommend a minimum load of 100 pF the graph
in Figure 3 was made using a special input signal just to show 100
...-:: ~
;iii"
that the typical internal TIL current glitch is not present. The
dual phase splitter is a unique method, patented by Motorola,
of driving totem output transistors to avoid the current glitch 50
o 100 200 300
that happens in all previous TIL drivers as one transistor turns
CAPACITANCE, pF
on while the other turns off. The output can easily be put at a
high impedance state by 'turning' off VEE which will cutoff both Figure 5. MC10/100H660 ICC versus CL, RS
output transistors.

«
::;;
1200

1000

800
./
. / ,.........
./
--- --
/ ' f-
RS=O

RS=5 II! 8
c5
12

10

~
~
~ ..... -
,....-::: --....---
~
RS=O
RS=5
RS=10
RS=20

U 600
...-- RS=10
/'

-
D-
.5?
/ ,......... I--
'"""
400 RS=20 ./
1-'........
./
200
i""""' NO LOAD

5 15 25 35 45 100 200 300

FREQUENCY, MHz CAPACITANCE, pF
Figure 3. ICC versus Frequency Figure 6, TPD versus CL, RS
with 300 pF and No Load
Another important benefit of the series resistor is that it re-
The drivers are arranged to be used in pairs, each output duces the device dynamic current by shaping the waveform,
pair is associated with a ground pin and every two pairs with giving it slower rising and falling edges. The slower edge rate
one VCCT pin, The internal logic VCC and ground pins are eliminates the overshoot and ringing that are associated with
separate from the output VCC and ground pins, this keeps the very fast signal edges on unterminated printed circuit card
noise from the high current output from feeding back to the in- traces, Also, the slower edge allows for longer circuit traces to
ternallogic, If there is ever a need to use only two data lines, be used without the need to be terminated, As shown in the
power would be needed only on half of the device. waveforms in Figure 7, the signal can be shaped to meet many
system requirements.

336
155.600 ns 205.600 ns 255.6 ns

~
SCOPE

H660 /
300pF

;;J;;

Ch. I = 800.0 mVollsldiv Offsel = -3. I 65 Valls

Ch. 2 = 2.000 Vollsldiv Oftsel = 6.375 Valls
Timebase =10.0 nsldiv Delay = 155.600 ns
Ch.2 Parameters Rise Time= 10.7652 ns .Widlh = 47.4560 ns
Fall Time = 8.8850 ns Preshool = 24.48% Overshool = 4.081%
p.p Valls = 7.8750 vans
WAVEFORM 1
155.600 ns 205.600 ns 255600 ns

:\.
SCOPE

- - - - - ~ - - -:....:-.-.------+...... - - -,- - - - - - - - - - - - - - - - - - - --
~
H660
50 /

300 pF

L-r-
Ch. I
Ch. 2
Timebase
= 800.0 mVolIsld,v
= 2.000 VolIsidiv
=10.0nsldiv
Ch. 2 Paramelers Rise Time= 12.0178 ns
Offsel
Offsel
Delay
• Wid1h
= -3. I 85 Valls
= 6.375 Valls
= 155.600 ns
= 47.8818 ns
;;J;;

Fall Time = 8.9770 ns Preshool = 13.58% Overshool = 2.469%

p.p Vails = 5.8750 Valls
WAVEFORM 2

155600 ns 205600 ns 255.600 ns

If .: SCOPE
I
I
I
~
H660
200 /

300pF

- - - - - ~- - -,,-,,-- -------+-"'--- -; - - - - - - - - - - - - - - - - - - --
;;J;;

~
Ch. 1 = 800.0 mVolIsidiv
- - ~E--

Offsel = -3.185 Vails

Ch. 2 = 2.000 VoltsJdiv Offsel = 6.375 Vans
Timebase =10.0 nsldiv Delay = 155.600 ns
Ch. 2 Paramelers Rise Time= 13.9250 ns .Wid1h = 48.2754 ns
Fall Time = 14.9356 ns Preshool = 3.636% Overshool = 3.636%
p.p Valls = 3.6875 Vails
WAVEFORM 3

Figure 7.

337
 There are times when the overshoot is desirable as when tor, the output will go all the way to each rail and will not dis-
driving CMOS memories requiring a rail to rail input signal. charge in a cycle time period. An example ofthis phenomena is
When the load is capacitive with no pull up or pull down resis- shown in Figure 8.

-- -- -- -- - -- -\ - - -
J
L
L_ i- -
\
\;
j
/
\ {3>-1 H660
ETPROBE

I-- - ::-~ Ll- -- - - -\v 'J;

300pF

Ch.4 = 2.00 mVoltsJd,v Offset =1.912 Volts

TImebase = 20.0 nsfdiv Delay = 16.0000 ns
Vmarkerl = 0.0000 Volts Vmarker2 = 6.1250 Volts Delta V = 6.1250 Volts

Figure 8.

When driving a resistive load it is seen on the chart in Figure As a precautionary note, if an output is being used without
9 that the VOH level remains somewhat constant over IOH the series resistor and if it becomes shorted to ground while in
loads that are over the device rating. a high state, it will source over 700 mA and in a short period of
time the device will be destroyed.
3.8
After the proper memory addresses are selected and the
\ TIL data is transferred from memory the data is then trans-
3.7 lated back to ECl by use of a TTL to ECl translator such as a
\ Motorola MC 1OH/I 00H600, 602 nine bit TIL to ECl translator
3.6
\ or a MC10124 or MC10H124, 4 bit translator.
\
:I:
93.5 ---... CONCLUSION

3.4

3.3
-- r-., /VOH
-r---
-
Mixed technology systems are becoming very popular
where system designers must optimize system performance
while keeping overall system cosUpower in line.
This application note described the MCI OH/I 00H600 4-BIT
ECl-TIL lOAD REDUCING DRAM DRIVER and some appli-
3.2
o 20 40 60 80 100 cation techniques that can result in an improvement in system
IOH performance and reliability.
Figure 9. VOH versus IOH

338
 AN1106

Considerations in Using The MHW801 and

MHW851 Series RF Power Modules
by Norm Dye and Mike Shields
RF Products Division

INTRODUCTION prevent low-level Impedances that result in signal feedback

The MHW801/851 Series of power modules are designed with consequent module instabilities. Remember that the
primarily for applications in cellular portable radios. The -1 back of the circuit substrate is ground and this is soldered
module is frequency compatible with the American system to the module flange which then becomes the ground connec-
called AMPS; the -2 module is frequency compatible with tion to external circuitry. Third, the board layout should be
the European TACS system; the -3 module is frequency such that isolation of input lines from output lines is at least
compatible with the Scandanavian system called NMT; and 50 dB.
the -4 module is frequency compatible with the NTACS Normal use of the module is to amplify CW signals that
system in Japan. Other than frequency of operation, all are frequency modulated. The first two stages of the module
models of the MHW801 and MHW851 are identical and meet are biased Class A; however, the last two stages are biased
the general electrical specifications set forth on the data Class C. Significant distortion will result if the signal contains
sheet. The only difference in the MHW801 and MHW851 amplitude information, such as amplitude modulation. How-
Series of modules is the flange design. In the case of the ever, it is possible to operate the module in less than a CW
MHW801, the flange does not extend any appreciable dis- condition. In a pulse mode of operation, any duty cycle up
tance beyond the PCB substrate/cap and it is intended that to 100% should create no problems provided the peak power
mounting to a heatsink will be accomplished by attaching the does not exceed the rated CW output power of the module.
flange to the heatsink with solder. The MHW801 modules Note, however, that case temperature can no longer be tied
are considered to be surface mount modules. The MHW851 to die temperature by the same constant difference used for
modules were introduced to offer similar modules with the CW operation. The thermal time constant of the die is
more conventional method of mounting. The flange extends approximately 10 micro-seconds which says that for moder-
beyond the substrate/cap and attachment to a heatsink is ately long pulse trains with low duty cycles, die temperature
intended to be by means of mounting screws. could be much higher than that predicted from CW measure-
A significant amount of applications information is con- ments.
tained in the MHW801/MHW851 Series data sheet. Also The modules have not been characterized for pulse power
included are a block diagram of the module and decoupling operation. It is to be assumed that greater than rated CW
networks used in the test fixture; typical performance curves output power can be obtained from the module in a pulse
showing parameters such as VCont, efficiency, input VSWR mode of operation; however, this is not recommended without
and output power as functions of frequency; and output power first consulting the factory because of concern for maximum
and VCont as functions of temperature. voltage swings as well as maximum die temperature.

GENERAL ELECTRICAL CONSIDERATIONS NOISE CHARACTERISTICS

Modules are matched to an impedance of 50 ohms for both One parameter of power modules frequently not specified
input and output. Thus their application in a SUb-system such is noise. Most applications of power modules have been in
as the transmitter portion of a portable radio is relatively radios where transmitting and receiving did not occur simulta-
straightforward. However, there are certain precautions that neously. Today, cellular radios are duplexed, i.e, they are
should be observed. First, it is important that DC inputs to capable of transmitting and receiving at the same time. Thus
the module be de-coupled by means of by-pass capacitors radio manufacturers are concerned about the noise charac-
and/or chokes to prevent bias and power supply circuitry teristics of the transmitter in the receive frequency band,
contributing to circuit instabilities (spurious oscillations). It is which is normally 45 MHz above the transmit frequency. For
recommended that the module user pay careful attention to this reason, Motorola has begun to characterize and guaran-
the decoupling information presented in the data sheet. tee noise performance of modules designed primarily for use
Second, grounding of the module should be adequate to in duplexed cellular radios.

339
 Noise power for the MHW801/851 Series modules is The block diagram for noise measurements is shown in
guaranteed in a 30 kHz bandwidth, 45 MHz above fo . This Figure 2. Several comments about the block diagram are in
is shown visually in Figure 1. Note that the noise is specified order. First, the signal source must be extremely low noise,
for two widely different temperatures and for rated output as close to kTB noise as possible. The HP8614A signal
power only. A characteristic of the MHW801/851 Series generator uses a cavity oscillator and satisfies the require-
modules is that the small signal (noise) gain of the amplifier ment of low noise. On the other hand, a frequency synthe-
is approximately 35 dB at rated output power but increases sized source such as the HP8656 (or Wavetek 2520A) signal
by as much as 3 dB as the control voltage (Veont) is generator does not. If this type of signal generator is used
decreased. to make noise measurements, it is necessary to add a
bandpass filter which will reject any signals 45 MHz above
the output frequency.
POUI

11 /
TRANSMIT SIGNAL
(806-940 MHz)

30 kHz RECEIVE BAND

-::a5dBm-- /MAXIMUM NOISE POWER

FREQUENCY

Figure 1. Noise Power In Receive Band

A. SIGNAL SOURCE
B. 20 dB NARDA DIRECTIONAL COUPLER
C. UNIT UNDER TEST
D. 20 dB NARDA DIRECTIONAL COUPLER
E. CIRCULATOR IN FREQ BAND OF OPERATION
F. 50 OHM LOAD
G. TELONIC FILTER
H. TELONIC FILTER
I. HP 71000 SPECTRUM ANALYZER
J. HP POWER METER
K. HP POWER METER
L. 10 dB INTERNAL ATIEN.
M. 6 dB PAD
Figure 2. Block Diagram For Sideband Noise Measurement

340
 Remember that any noise at the input of the MHWS01/S51 istics, efficiency and harmonics will degrade at reduced
Series module is amplified by approximately 35 dB. This output power. As output power is reduced, the class C
noise amplification should not be confused with internally stages of the module operate further and further from their
generated noise which could be caused by a high stage noise optimum load line resulting in significantly poorer efficiency.
figure or by regeneration in one of the module stages, neither As their operation approaches the more non-linear region of
of which is a factor in the MHWS01/S51 Series module the transistor transfer function, noise will likely increase and
design. harmonics will increase with respect to carrier power. Gener-
Second, it is essential that the module be terminated in ally these degradations in performance are not serious be-
a circulator which will prevent out-of-band impedances of the cause they are relative to carrier power level. For example,
subsequent RF network from affecting the stability (and, thus efficiency becomes much less at output power levels of
noise) of the module. Third, care must be taken to prevent 100 mW; but current drain is much lower than for the case
the carrier frequency from saturating the input stages of the of 2 watts of output power, so this is generally not considered
spectrum analyzer used to measure the noise level. Again, a problem in radio applications.
it is critical in accurate noise measurements to be certain Other circuit considerations external to the module that are
that the sensitivity of the spectrum analyzer be at least 10 dB sometimes overlooked are source and load impedances.
better than the noise level being measured. Note that the stability of the module is guaranteed only for
Normally to accomplish this it is necessary to reduce the source VSWR's of 3:1 and load VSWR's of 6:1. Frequently
resolution bandwidth (RBW) of the spectrum analyzer to the load for the module is the transmit portion of a duplex
30 kHz and set the video filter to 100 Hz bandwidth. The filter. The out-of-band impedance presented by the filter can
manufacturer (Hewlett Packard) of the spectrum analyzer affect the stability of the module. The impedance reflected
recommends a video bandwidth 100 times less than the RBW to the module depends on the length of transmission line
for best noise averaging. between the module and the filter thereby causing line length
The filters, "H" and "G" (in Figure 2) are stagger tuned to to be an additional circuit consideration. It should be remem-
obtain adequate selectivity for rejecting the carrier frequency bered that the MHWSOI/851 Series of modules are not
at the input to the spectrum analyzer. Obviously a single filter unconditionally stable for all load and source impedances.
can be used if it has a rejection level of approximately 60 dB, Out-of-band impedances of filters result in Significantly high
45 MHz away from the bandpass of the filter. The actual VSWR's at out-of-band frequencies. If these impedances are
rejection needed depends on whatever is required to prevent reflected to the module such that the module is terminated
saturation of the spectrum analyzer by the carrier signal. in impedances that lead to regions of instability, the module
will oscillate.
Input power to the module can vary from a low value of
GAIN CONTROL o mW to a recommended maximum of 3 mW. Input powers
The data sheet recommends gain control by keeping input greater than 3 mW are not recommended because of the
power at 0 dBm and varying the control voltage. Output potential damage that might result from overdriving the two
power versus control voltage is shown in the typical charac- final class C stages in the module. Overdrive results in
teristics of the data sheet. Gain control in the MHWS01/S51 excessive power dissipation particularly for the simultaneous
Series module is obtained by controlling the bias to the Class condition of maximum supply voltage of 7.5 volts. Overdriving
A input stage as opposed to other modules that controls the the final Class C stages can also lead to circuit instabilities
voltage to Class C driver stages. The benefit of this method tlecause of changing impedances. Likewise, supply voltages
of control is significantly less contro'l current and a lower slope greater than 7.5 volts should not be applied to the module
of the output power versus control voltage curve. for the same reasons of overdissipation and potential instabil-
It is possible to control output power from the module by ities.
controlling input power with the control voltage maintained
at a fixed level (generally maximum). This is somewhat
intuitive; however, a major benefit of this method for power MOUNTING CONSIDERATIONS
out control may not be obvious. This benefit is the best noise GENERAL
performance of the module because the small Signal gain In mounting power modules, consideration must be given
is approximately 3 dB less at high control voltage as com- to heat dissipation and grounding. Motorola specifies the
pared to low control voltage. Other important factors such range of case temperatures over which the module will
as stability, input VSWR, harmonics, efficiency and load perform safely. The upper temperature is determined by
mismatch are essentially unaffected by the method of output thermal resistances between each die and the case with the
power control. guideline that die temperature will be maintained below
200°C, which is considered a safe temperature for silicon
transistors. All the user has to do is provide sufficient heat
OTHER CIRCUIT CONSIDERATIONS sinking for the module to be certain that the flange of the
Performance of the module at less than rated output power module does not exceed the maximum operating tempera-
is sometimes of significance in typical module applications. ture rating. The maximum power dissipated by the module
Regardless of output power control, the noise character- can be determined by determining the maximum DC power

341
input less the RF power output. Another way to determine function electrically being the end result. Also, as stated on
the maximum power to be dissipated is to divide the rated the data sheet, do not permit the module to be immersed
output power by the minimum efficiency and then subtract in a flux removal system. The part is not hermetically sealed,
the rated output power. and liquids could penetrate into the circuitry with potentially
Maximum power dissipation for either the MHWB01 or disasterous results.
MHWB51 Series modules is 2.44 walls (2 Walls divided by
.45 minus 2 Watts). This relatively small amount of power MHW851 Series
can normally be dissipated by minimal thermal contact be- MHWB51 type modules have flanges with "ears" for allach-
tween the flange of the module and the heatsink provided mentto a heatsink by means of screws. The cutouts at each
in the application. Calculations using the MHWB51 module end of the flange will accommodate 4-40 screws and these
attached to a heatsink only at the mounting screws indicate should be torqued to an amount no greater than 2 to 3
that the rise in flange temperature (at center of flange) above inch-pounds. The use of thermal grease is not recommended
the temperature at the ends of the flange should not exceed for the MHWB51 Series module because the relatively low
lO°C. output power does not require intimate (thermal) contact of
Grounding the module to external circuitry through mount- the flange surface to the heatsink. Use of thermal grease is
ing screws only should be adequate to prevent spurious permissible but care must be taken to prevent using an
oscillations provided the ground contact does not become excessive amount. Since it is not needed, it is Motorola's
excessively resistive as a result of nickel oxide forming on recommendation that it not be used.
the nickel plated flange. Nickel oxide (unlike copper and silver Flatness of the heatsink when using MHWB51 's is much
oxide) is resistive and its formation can lead to intermittent less critical than that required for higher power modules.
ground paths between the module and external circuits. Motorola recommends that the heatsink surface be flat to
within + or - 0.003 inches, a dimension that should be
MHW801 Series relatively easy to allain. The MHWB01/B51 Series module
MHWB01 modules are designed without "ears" on the is constructed with a printed circuit board substrate which
flange. They should be attached to a heatsink with solder. negates the stringent requirements for bending that are
When soldering, the primary consideration should be to placed on ceramic substrate modules. Motorola believes that
prevent any part of the module flange from achieving a the MHWB01/B51 Series module can be distorted as much
as 0.020 inches either concave or convex without damage
temperature greater than 165°C. A low temperature solder
to the module.
such as 52% In and 4B% Sn (along with "R" type flux) is
Because bending requirements are relaxed, it is also
recommended because this solder liquifies below 150°C. unnecessary to worry about tightening sequence as de-
Keep in mind that the internal construction of the module has scribed in EB107 - "Mounting Considerations for Motorola
been achieved using 36% Sn, 62% Pb and 2% Ag solder RF Power Modules." This EB was written primarily for ceram-
which liquifies at 179-1BO°C. If the module flange is allowed ic substrate modules and does not apply in total to printed
to achieve a temperature greater than 165°C, serious me- circuit board substrate modules such as the MHWB01/B51
chanical damage could occur with consequent failure to Series.

342
 AN1107

Understanding RF Data Sheet Parameters

by Norman E. Dye
RF Products Division

INTRODUCTION the transistor and on the other hand has breakdown voltages
Data sheets are often the sole source of information about that permit the "gain at frequency" objectives to be met by
the capability and characteristics of a product. This is particu· the transistor. Mobile radios normally operate from a 12 volt
larly true of unique RF semiconductor devices that are used source; portable radios use a lower voltage, typically 6 to
by equipment designers allover the world. Because the 9 volts; avionics applications are commonly 28 volt supplies
circuit designer often cannot talk directly with the factory, he while base station and other ground applications such as
relies on the data sheet for his device information. And for medical electronics generally take advantage of the superior
RF devices, many of the specifications are unique in them· performance characteristics of high voltage deVices and
selves. Thus it is important that the user and the manufactur· operate with 24 to 50 volt supplies. In making a transistor,
er of RF products speak a common language, i.e., what the breakdown voltages are largely determined by material resis-
semiconductor manufacturer says about his RF device is tivity and junction depths (Figure 2). It is for these reasons
understood fully by the circuit designer. that breakdown voltages are Intimately entwined with func-
This paper reviews RF transistor and amplifier module tional performance characteristics. Most product portfolios In
parameters from maximum ratings to functional characteris- the RF power transistor industry have families of transistors
tics. It IS divided into 5 basic sections: 1) DC Specifications, deSigned for use at specified supply voltages such as
2) Power Transistors, 3) Low Power Transistors, 4) Power 7.5 volts, 12.5 volts, 28 volts and 50 volts.
Modules and 5) Linear Modules. Comments are made about Leakage currents (defined as reverse biased Junction cur-
critical specifications, about how values are determined and rents that occur prior to avalanche breakdown) are likely to
what are their significance. A brief description of the proce- be more varied in their speCification and also more Informa-
dures used to obtain impedance data and thermal data is tive. Many transistors do not have leakage currents specified
set forth; the importance of test cirCUits is elaborated; and because they can result In excessive (and frequently unnec-
background Information is given to help understand low noise essary) wafer/die Yield losses. Leakage currents arise as a
considerations and linearity requirements. result of material defects, mask imperfections and/or unde-
sired impurities that enter during wafer processing. Some
sources of leakage currents are potential reliability problems;
DC SPECIFICATIONS most are not. Leakage currents can be material related such
BaSically RF transistors are characterized by two types of as stacking faults and dislocations or they can be "pipes"
parameters: DC and functional. The "DC" specs consist (by created by mask defects and/or processing inadequacies.
definition) of breakdown voltages, leakage currents, hFE (DC These sources result In leakage currents that are constant
beta) and capacitances, while the functional specs cover with time and if initially acceptable for a particular application
gain, ruggedness, noise figure, Zin and Zout, S'parameters, will remain so. They do not pose long term reliability prob-
distortion, etc. Thermal characteristics do not fall cleanly into lems.
either category since thermal resistance and power dissipa- On the other hand, leakage currents created by channels
tion can be either DC or AC. Thus, we will treat the spec induced by mobile ionic contaminants In the oxide (primarily
of thermal resistance as a special specification and give it sodium) tend to change with time and can lead to Increases
its own heading called "thermal characteristics." Figure 1 IS in leakage current that render the device useless for a
one page of a typical RF power data sheet showing DC and specific application. Distinguishing between sources of leak-
functional specs. age current can be difficult, which is one reason deVices for
A critical part of selecting a transistor is choosing one that application in military environments require HTRB (high
has breakdown voltages compatible with the supply voltage temperature reverse bias) and burn-in testing. However. even
available in an intended application. It is important that the for commercial applications particularly where battery drain
design engineer select a transistor on the one hand that has is critical or where bias considerations dictate limitations. it
breakdown voltages which will NOT be exceeded by the DC is essential that a leakage current limit be included In any
and RF voltages that appear across the various junctions of complete device specification.

343
 ELECTRICAL CHARACTERISTICS (TC =25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Collector-Emitter Breakdown Voltage (IC= 20 mAdc, IB = 0) V(BR)CEO 16 - - Vdc

Collector-Emitter Breakdown Voltage (IC=20 mAdc, VBE = 0) V(BR)CES 36 - - Vdc

Emitter-Base Breakdown Voltage (IE = 5.0 mAdc, IC = 0) V(BR)EBO 4.0 - - Vdc

Collector Cutoff Current (VCE = 15 Vdc, VBE =0, TC = 25°C) ICES - - 10 mAdc

ON CHARACTERISTICS

DC Current Gain (IC = 4.0 Adc, VCE = 5.0 Vdc) hFE 20 70 150 -
DYNAMIC CHARACTERISTICS

Output Capacitance Cob - 90 125 pF

(VCB = 12.5 Vdc, IE =0, f = 1.0 MHz)
FUNCTIONAL TESTS

Common-Emitter Amplifier Power Gain G pe 4.8 5.4 - dB

(VCC = 12.5 Vdc. Pout = 45 W, Ic(Max) =5.8 Adc, f = 470 MHz)
Input Power Pin - 13 15 Watts
(VCC = 12.5 Vdc. Pout = 45 W. f = 470 MHz)

Collector Efficiency 55 60 - %
'1
(VCC = 12.5 Vdc. Pout = 45 W, Ic(Max) =5.8 Adc, f = 470 MHz)
Load Mismatch Stress ~,* No Degradation in Output Power
(VCC = 16 Vdc, Pin = Note 1. f = 470 MHz, VSWR =20:1, All Phase Angles)
Series Equivalent Input Impedance Zin - 1.4+j4.0 - Ohms
(VCC = 12.5 Vdc, Pout = 45 W. f = 470 MHz)

Senes Equivalent Output Impedance ZOL* - 1.2+j2.8 - Ohms

(VCC = 12.5 Vdc. Pout = 45 W. f = 470 MHz)
Notes
, Pin'"' 50°0 of Drive ReqUirement for 45 W output @ 125 V
• L,' = Mismatch stress factor the electrical cntenon established to venfy the deVice resistance to load mismatch failure. The mismatch stress test IS accomplished In the standard test
fixture IFlgure 1) terminated In a 20 1 minimum load mismatch at all phase angles.

Figure 1_ Typical DC and Functional Specifications

~oo

-.
r--

-
-
-- 10
.....
100
50

~20
30
PLANE JUNCTION

-
/
7

~~ ~
5

-xi l~m

--
". 10
'" 1016
DOPING DENSITY CB (cm-3)
Figure 2. The Effect of Curvature and Resistivity on Breakdown Voltage

344
 DC parameters such as hFE and Cob (output capacitance)
tL
need little comment. Typically, for RF devices, hFE is relative- .9: 1.8
w
ly unimportant because the functional parameter of gain at ~ 1.6
the desired frequency of operation is specified. Note, though, 1= 1 MHz
~ 1.4
that DC beta is related to AC beta (Figure 3). Functional gain ~
C3 12
will track DC beta particularly at lower RF frequencies.
w I\,
Generally RF device manufacturers do not like to have tight
limits placed on hFE. Primarily the reasons that justify this ~
d:: 0.8 "- ...............
position are: ~ 0.6
a} Lack of correlation with RF performance
<5 0.4
b} Difficulty in control in wafer processing
u 0.2
c} Other device manufacturing constraints dictated by {J
u 00
functional performance specs which preclude tight limits 4 6 8 10 12 14 16
for hFE. VCB, COLLECTOR-BASE VOLTAGE (Vdc)
A good rule of thumb for hFE is to set a maximum-to-mini-
Figure 4. Junction Capacitance versus Voltage
mum ratio of not less than 3 and not more than 4 with the
minimum hFE value determined by an acceptable margin in
functional gain. The value of V(BR}CEO is sometimes misunderstood. Its
value can approach or even equal the supply voltage rating
40r---------------------------------,
POWER GAIN of the transistor. The question naturally arises as to how such
a low voltage can be used in practical applications. First,
30 V (BR}CEO is the breakdown voltage of the collector-base
Hie junction plus the forward drop across the base-emitter junc-
~ tion with the base open, and it is never encountered in
w
'" 20
C3 amplifiers where the base is at or near the potential of the
w
C> emitter. That is to say, most amplifiers have the base shorted
10 or they use a low value of resistance such that the breakdown
value of interest approaches V (BR}CES· Second, V (BR}CEO
involves the current gain of the transistor and increases as
°2~--~--~10~~--~~~~~~~~~·
frequency increases. Thus the value of V (BR}CEO at RF
FREQUENCY, MEGACYCLES frequencies is always greater than the value at DC.
The maximum rating for power dissipation (PD) is closely
Figure 3. Beta versus Frequency
associated with thermal resistance (IlJC). Actually maximum
Output capacitance is an excellent measure of comparison PD is in reality a fictitious number - a kind of figure of merit
of device size (base area) provided the majority of output - because it is based on the assumption that case tempera-
capacitance is created by the base-collector junction and not ture is maintained at 25'C. However, providing everyone
parasitic capacitance ariSing from bond pads and other top arrives at the value in a similar manner, the rating of maxi-
metal of the die. Remember that junction capacitance will mum PD is a useful tool with which to compare devices.
vary with voltage (Figure 4) while parasitic capacitance will The rating begins with a determination of thermal resis-
not vary. Also, in comparing devices, one should note the tance - die to case. Knowing HJC and assuming a maximum
voltage at which a given capacitance is specified. No industry die temperature, one can easily determine maximum PD
standard exists. The preferred voltage at Motorola is the
(based on the previously stated case temperature of 25'C).
transistor VCC rating, i.e., 12.5 volts for 12.5 volt transistors
Measuring IlJC is normally done by monitoring case tempera-
and 28 volts for 28 volt transistors, etc.
ture (T C) of the device while it operates at or near rated
output power (PO) in an RF circuit. The die temperature (T J)
MAXIMUM RATINGS and
is measured simultaneously using an infra-red microscope
THERMAL CHARACTERISTICS
(see Figure 6) which has a spot size resolution as small as
Maximum ratings (shown for a typical RF power transistor 1 mil in diameter. Normally several readings are taken over
in Figure 5) tend to be the most frequently misunderstood the surface of the die and an average value is used to specify
group of device specifications. Ratings for maximum junction TJ.
voltages are straight forward and simply reflect the minimum It is true that temperatures over a die will vary typically
values set forth in the DC specs for breakdown voltages. If 10-20'C. A poorly designed die (improper ballasting) could
the device in question meets the specified minimum break- result in hot spot (worst case) temperatures that vary
down voltages, then voltages less than the minimum will not 40-50'C. Likewise, poor die bonds (see Figure 7) can result
cause junctions to reach reverse bias breakdown with the in hot spots but these are not normal characteristics of a
potentially destructive current levels that can result. properly designed and assembled transistor die.

345
The RF Line MRF650
NPN Silicon
RF Power Transistor
· .. designed for 12.5 Volt Volt UHF large-signal amplifier applications in industrial 50 WATTS. 512 MHz
and commercial FM equipment operating to 520 MHz. RF POWER TRANSISTOR
NPN SILICON
• Guaranteed 440, 470, 512 MHz 12.5 Volt Characteristics
Output Power; 50 Watts
Minimum Gain; 5.2 dB @ 440, 470 MHz
Efficiency; 55% @ 440, 470 MHz
IRL; 10dB
• Characterized with Series Equivalent Large-Signal Impedance Parameters from 400 to
520 MHz
• Built-In Matching Network for Broadband Operation
• Triple Ion Implanted for More Consi.stent Characteristics
• Implanted Emitter Ballast Resistors
• Silicon Nitride Passivated
• 100% Tested for Load Mismatch Stress at all Phase Angles with 20: 1 VSWR @ CASE 316-01
15.5 Vdc, 2.0 dB Overdrive

MAXIMUM RATINGS
Rating Symbol Value Unit
Collector-Emitter Voltage VCEO t6.5 Vdc
Collector-Emitter Voltage VCES 38 Vdc
Emitter-Base Voltage VEBO 4.0 Vdc
Collector-Current - Continuous IC 12 Adc
Total Device Dissipation @ T C = 25'C Po 135 Watts
Derate above 25'C 0.77 wrc
Storage Temperature Range Tstg ---65 to +150 'C
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit

Thermal Resistance, Junction to Case RfjJC 1.3 'CIW

Figure 5. Maximum Ratings of a Typical RF Power Transistor

By measuring T C and TJ along with Po and Pin - both surements described in the preceding paragraphs, or for the
OC and RF - one can calculate 8JC from the formula 8JC case illustrated, a value of BJC ; 1.25'C/W.
; (TJ - TC)/(Pin - PO)· Typical values for an RF power Now a few words are in order about die temperature.
transistor might be TJ ; 130'C; TC; 50'C; VCC ; 12.5 V; Reliability considerations dictate a safe value for an all Au
IC ; 12 A; Pin (RF) = 10 W; Po (RF) ; 50 W. Thus 8JC (gold) system (die top metal and wire) to be 200'C. Once
; (130 - 50)/(10 + {12.5 x 12} - 30) ; 80/80 ; 1'C/W. TJ max is determined, along with a value for 8JC, maximum
Several reasons dictate a conservative value be placed Po is simply
on 8JC. First, thermal resistance increases with temperature Po (max) ; (TJ (max) - 25'C)/8JC·
(and we realize Tc = 25'C is NOT realistic). Second, TJ is Specifying maximum Po for TC ; 25'C leads to the
not a worst case number. And, third, by using a conservative necessity to derate maximum Po for any value of TC above
value of 8JC, a realistic value is determined for maximum 25'C. The derating factor is simply the reciprocal of BJC!
PO. Generally, Motorola's practice is to publish 8JC numbers Maximum col/ector current (lC) is probably the most sub-
approximately 25% higher than that determined by the mea- jective maximum rating on the transistor data sheets. It has

346
 ty, temperature and type of metal. At Motorola, MTBF is
generally set at >7 years and maximum die temperature at
200 o e. For plastic packaged transistors, maximum TJ is set
at 150o e. The resulting current density along with a knowl-
edge of the die geometry and top metal thickness and
material allows the determination of Ie max for the device.
It is up to the transistor manufacturer to specify an Ie max
based on which of the two limitations (die, wire) is paramount.
It is recommended that the circuit design engineer consult
the semiconductor manufacturer for additional information if
Ie max is o! any concern in his specific use of the transistor.
Storage temperature is another maximum rating that is
frequently not given the attention it deserves. A range of
-55°e to 200 0 e has become more or less an industry
Figure 6. Equipment Used To Measure standard. And for the single metal, hermetic packaged type
Ole Temperature
of device, the upper limit of 200 0 e creates no reliability
problems. However, a lower high temperture limitation exists
for plastic encapsulated or epoxy sealed devices. These
should not be subjected to temperatures above 150 0 e to
prevent deterioration of the plastic material.

POWER TRANSISTORS -
Functional Characteristics
The selection of a power transistor usually involves choos-
ing one for a frequency of operation, a level of output power,
a desired gain, a voltage of operation and preferred package
configuration consistent with circuit construction techniques.
Functional characteristics of an RF power transistor are
by necessity tied to a specific test circuit (an example is
shown in Figure 8). Without specifying a circuit, the functional
Figure 7. An Example of Incomplete parameters of gain, reflected power, efficiency - even
Die Attach ruggedness - hold little meaning. Furthermore, most test
circuits used by RF transistor manufacturers today (even
been, and is, determined in a number of ways each leading those used to characterize devices) are designed mechani-
to different maximum values. Actually, the only valid maxi· cally to allow for easy insertion and removal of the device
mum current limitations in an RF transistor have to do with under test (O.U.T.). This mechanical restriction sometimes
the current handling ability of the wires or the die. However, limits achievable device performance which explains why
power dissipation ratings may restrict current to values far performance by users frequently exceeds that indicated in
below what should be the maximum rating. Unfortunately, data sheet curves. On the other hand, a circuit used to
many older transistors had their maximum current rating characterize a device is usually narrow band and tunable.
determined by dividing maximum Po by collector voltage (or This results in higher gain than attainable in a broadband
be V (BR)eEO for added safety) but this is not a fundamental circuit. Unless otherwise stated, it can be assumed that
maximum current limitation of the part. Many lower frequency characterization data such as Po vs frequency is generated
parts have relatively gross top metal on the transistor die, on a point-by-point basis by tuning a narrow band circuit
i.e., wide metal runners and the "weak current link" in the across a band of frequencies and, thus, represents what can
part is the current handling capability of the emitter wires (for be achieved at a specific frequency of interest provided the
common emitter parts). The current handling ability of wire circuit presents optimum source and load impedances to the
(various sizes and material) is well known; thus the maximum O.U.T.
current rating may be limited by the number, size and material Broadband, fixed tuned test circuits are the most desirable
used for emitter wires. for testing functional performance of an RF transistor. Fixed
Most modern, high frequency transistors are die limited tuned is particularly important In assuring everyone - the
because of high current densities resulting from very small manufacturer and the user - of product consistency, i.e ..
current carrying conductors and these densities can lead to that devices manufactured tpmorrow will be identical to
metal migration and premature failure. The determination of devices manufactured today.
Ie max for these types of transistors results from use of Tunable, narrow band circuits have led to the necessity
Black's equation for metal migration which determines a for device users and device manufacturers to resort to the
mean time between failures (MTBF) based on current densi· use of "correlation units" to assure product consistency over

347
 coefficient is set at a magnitude of unity while its phase angle
is varied through all possible values from 0 degrees to 360
degrees. Many 12 volt (land mobile) transistors are routinely
given this test at Motorola Semiconductors by means of a
test station similar to the one shown in Figure 9.

Figure 8. Typical RF Power Test Circuit

a period of time. Fixed tuned circuits minimize (if not elimi-

nate) the requirements for correlation and in so doing tend
to compensate for the increased constraints they place on
the device manufacturer. On the other hand, manufacturers
Figure 9. A Typical Functional Test Station
like tunable test circuits because their use allows adjustments
that can compensate for variations in die fabrication and/or
Ruggedness specifications come in many forms (or
device assembly. Unfortunately gain is normally less in a
guises). Many older devices (and even some newer ones)
broadband circuit that it is in a narrow band circuit, and this
simply have NO ruggedness spec. Others are said to be
fact frequently forces transistor manufacturers to use narrow
"capable of' withstanding load mismatches. Still others are
band circuits to make their product have sufficient attraction
guaranteed to withstand load mismatches of 2:1 VSWR to
when compared with other similar devices made by competi-
tors. This is called "specsmanship." One compromise for the x:1 VSWR at rated output power. A few truly rugged transis-
transistor manufacturer is to use narrow band circuits with tors are guaranteed to withstand 30:1 VSWR at all phase
all tuning adjustments "locked" in place. For all of the above angles (for all practical purposes 30:1 VSWR is the same
reasons, then, in comparing functional parameters of two or as x:1 VSWR) with both over voltage and over drive. Once
more devices, the data sheet reader should observe carefully again it is up to the user to match his circuit requirements
the test circuit in which specific parameter limits are guaran- against device specifications.
teed. Then as if the whole subject of ruggedness is not sufficient-
For RF power transistors, the parameter of ruggedness ly confusing, the semiconductor manufacture slips in the
takes on considerable importance. Ruggedness is the char- ultimate "muddy the water" condition in stating what consti-
acteristic of a transistor to withstand extreme mismatch tutes passing the ruggedness test. The words generally say
conditions in operation (which causes large amounts of that after the ruggedness test the D.U.T. "shall have no
output power to be "dumped back" into the transistor) without degradation in output power." A better phrase would be "no
altering its performance capability or reliability. Many circuit measurable change in output power." But even this is not
environments particularly portable and mobile radios have the best. Unfortunately the D.U.T. can be "damaged" by the
limited control over the impedance presented to the power ruggedness test and still have "no degradation in output
amplifier by an antenna, at least for some duration of time. power." Today's RF power transistors consist of up to 1K or
In portables, the antenna may be placed against a metal more low power transistors connected in parallel. Emitter
surface; in mobiles, perhaps the antenna is broken off or resistors are placed in series with groups of these transistors
inadvertently disconnected from the radio. Today's RF power in order to better control power sharing throughout the
transistor must be able to survive such load mismatches transistor die. It is well known by semiconductor manufactur-
without any effect on subsequent operation. A truly realistic ers that a high percentage of an RF power transistor die (say
possibility for mobile radio transistors (although not a normal up to 25-30%) can be destroyed with the transistor still able
situation) is the condition whereby an RF power device "sees" to deliver rated power at rated gain, at least for some period
a worst case load mismatch (an open circuit. any phase of time. If a ruggedness test destroys a high percentage of
angle) along with maximum Vee AND greater than normal cells in a transistor, then it is likely that a 2nd ruggedness
input drive - all at the same time. Thus the ultimate test test (by the manufacturer or by the user while in his circuit)
for ruggedness is to subject a transistor to a test wherein would result in additional damage leading to premature
Pin (RF) is increased up to 50% above that value necessary device failure.
to create rated PO; Vee is increased about 25% (12.5 V A more scientific measurement of "passing" or "failing" a
to 16 V for mobile transistors) AND then the load reflection ruggedness test is called tNRE - the change in emitter

348
resistance before and after the ruggedness test. VRE is
determined to a large extent by the net value of emitter
resistance in the transistor die. Thus if cells are destroyed,
emitter resistance will change with a resultant change in Vre.
Changes as small as 1% are readily detectable, with 5% or
less normally considered an acceptable limit. Today's more
sophisticated device specifications for RF power transistors
use this criteria to determine "success" or "failure" in rugged-
ness testing.
A circuit designer must know the input/output characteris-
tics of the RF power transistor(s) he has selected in order
to design a circuit that "matches" the transistor over the
frequency band of operation. Data sheets provide this infor-
mation in the form of large signal impedance parameters,
Zin and Zout (commonly referred to as ZOL*). Normally,
these are stated as a function of frequency and are plotted Figure 11. Short Circuit Reference Fixture
on a Smith Chart and/or given in tabular form. It should be
noted that Zin and Zout apply only for a specified set of
operating conditions, i.e., PO, VCC and frequency. Both Zin
and Zout of a device are determined in a similar way, i.e.,
place the D.U.T. in a tunable circuit and tune both input and
output circuit elements to achieve maximum gain for the
desired set of operating conditions. At maximum gain, D.U.T.
impedances will be the conjugate of the input and output
network impedances. Thus, terminate the input and output
ports of the test circuit, remove the device and measure Z
looking from the device - first, toward the input to obtain
the conjugate of Zin and, second, toward the output to obtain
ZOL which is the output load required to achieve maximum
PO·
A network analyzer is used in the actual measurement
process to determine the complex reflection coefficient of the
circuit using, typically, the edge of the package as a plane Figure 12. Adapter Used To Measure
Circuit Impedance From Package
of reference. A typical measurement setup is shown in Figure
10. Figure 11 shows the special fixture used to obtain the aided design programs to design Land C matching networks
short circuit reference while Figure 12 illustrates the adapter for his particular application.
which allows the circuit impedance to be measured from the The entire impedance measuring process is somewhat
edge of the package. laborious and time consuming since it must be repeated for
each frequency of interest. Note that the frequency range
permitted for characterization is that over which the circuit
will tune. For other frequencies, additional test circuits must
be designed and constructed, which explains why it is some·
times difficult to get a semiconductor manufacturer to supply
impedance data for special conditions of operation such as
different frequencies, different power levels or different oper·
ating voltages.

LOW POWER TRANSISTORS -

Functional Characteristics
Most semiconductor manufacturers characterize low pow·
er RF transistors for linear amplifier and/or low noise amplifier
applications. Selecting a proper low power transistor involves
choosing one having an adequate current rating. in the "right"
package and with gain and noise figure capability that meets
Figure 10. The HP Network Analyzer
the requirements of the intended application.
One of the most useful means of specifying a linear device
Once the circuit designer knows ZIN and ZOL* of the
is by means of scattering parameters, commonly referred to
transistor as a function of frequency, he can use computer
as S-Parameters which are in reality voltage reflection and

349
transmission coefficients when the device is embedded into is the power gain of the device when the source and load
a 50 ohm system. See Figure 13. IS111. the magnitude of impedances are 50 ohms. An improvement in gain can
the input reflection coefficient is directly related to input always be acheived by matching the device's input and output
VSWR by the equation VSWR = (1 + IS111) I (1 - IS111). impedances (which are almost always different from 50
Likewise, IS221, the magnitude of the output reflection coeffi- ohms) to 50 ohms by means of matching networks. The
cient is directly related to output VSWR. IS21 12 , which is the larger ttie linear device, the lower the impedances and the
square of the magnitude of the input-to-output transfer func- greater is the need to use matching networks to achieve
tion, is also the power gain of the device. It is referred to useful gain.
on data sheets as "Insertion Gain." Note, however, that IS2112

INPUT

Zo A1 .. A2
LINEAR
TWO·PORT
81 • .. 82

21
1---------- REFERENCE PLANES
S11 INPUT REFLECTION COEFFICIENT = ::

S22 • OUTPUT REFLECTION COEFFICIENT = :~

IS21 j2 • FORWARD TRANSDUCER GAIN = :~
IS1212 • REVERSE TRANSDUCER GAIN = :~
Figure 13, Two-Port S-Parameter Definitions

Another gain specification shown on low power data sheets contours is shown in Figure 14. These contours are circles
is called "Associated Gain." The symbol used for Associated which are either totally or partially complete within the con-
Gain is "GNF." It is simply the gain of the device when fines of the Smith Chart. If the gain circles are contained
matched for minimum noise figure. Yet another gain term is entirely within the Smith Chart, then the device is uncondition-
shown on some data sheets and it is called "Maximum ally stable. If portions of the gain circles are outside the Smith
Unilateral Gain." It's symbol is GU max. As you might expect, Chart, then the device is considered to be "conditionally
GU max is the gain achievable by the transistor when the stable" and the device designer must concern himself with
input and output are conjugately matched for maximum instabilities, particularly outside the normal frequency range
power transfer (and S12 = 0.). One can derive a value for of operation.
GU max using scattering parameters: If the data sheet includes Noise Parameters, a value will
GU max = IS2112 I {(1 - IS1112 (1 - IS2212)}. be given for the optimum input reflection coefficient to achieve
Simply stated, this is the 50 ohm gain increased by a factor minimum noise figure. Its symbol is to or sometimes fopt,
which represents matching the input and increased again by But remember if you match this value of input reflection
a factor which represents matching the output. coefficient you are likely to have far less gain than is achiev-
Many RF low power transistors are used as low noise able by the transistor. The input reflection coefficient for
amplifiers which has led to several transistor data sheet maximum gain is normally called fMS, while the output
parameters related to noise figure. NFmin is defined as the reflection coefficient for maximum gain is normally called
minimum noise figure that can be achieved with the transistor.
To achieve this NF requires source impedance matching fML·
Another important noise parameter is noise resistance
which is usually different from that required to achieve
which is given the symbol Rn and is expressed in ohms.
maximum gain. The design of a low noise amplifier, then,
Sometimes in tabular form, you may see this value normal-
is always a compromise between gain and NF. A useful tool
ized to 50 ohms in which case it is designated rn. The
to aid in this compromise is a Smith Chart plot of constant
significance of rn can be seen in the formula below which
gain and Noise Figure contours which can be drawn for
determines noise figure NF of a transistor for any source
specific operating conditions - typically bias and frequency.
A typical Smith Chart plot showing constant gain and NF reflection coefficient f s if the three noise parameters -

350
 +j50

+j250 +j250

+j500 +j500

-j500 -1500

-j250 -j250

veE =6 V veE = 6 V
-j50 -j50 Ie =3 rnA
Ie =3 rnA
f= 2000 MHz f= 4000 MHz

(A) F = 2 GHz ~ - AREA OF INSTABILITY (8) F = 4 GHz

Figure 14. Gain & Noise Figure Contours

NFmin, rn and r 0 (the source resistance for minimum noise (the NFmin circle being a point); thus, by choosing different
figure) - are known. Typical noise parameters taken from values of NF one can plot a series of noise circles on the
the MRF942 data sheet are shown in Figure 15. Smith Chart. Incidentally, rn can be measured by measuring
NF = NFmin + {4rn Irs - r 012} / {(I - Ifs12) 11 + r 012}. noise figure for rs = 0 and applying the equation stated
The locus of points for a given NF turns out to be a circle above.

MRF942
VCE IC
, NFmin GNF ro RN NFSO Q
(Vdc) (rnA) (MHz) (dB) (dB) (MAG, AN G) (ohms)
(dB)
6 3 1000 1.3 16 36 L 94 17.5 1.7
2000 2.0 11 .37 L -145 15.5 26
4000 2.9 B.O 21.5 4.3
.50 L -134
15 1000 2.1 19 .25 L 150 13 2.6
2000 2.7 14 .26 L -173 16.5 3.1
4000 4.3 9.0 47 5.4
.48 L -96

Figure 15. Typical Noise Parameters

A parameter found on most RF low power data sheets is - things which are more difficult to achieve In making an
commonly called the current gain-bandwidth product. It's RF transistor.
symbol is fT' Sometimes it is referred to as the cutoff frequen- The complete RF low power transistor data sheet will
cy because it is generally thought to be the product of low include a plot of fT versus collector current. Such a curve (as
frequency current gain and the frequency at which the current shown in Figure 17) will increase with current. flatten and
gain becomes unity. While this is not precisely true (see then begin to decrease as IC increases thereby revealing
Figure 16), it is close enough for practical purposes. And it useful information about the optimum current with which to
is true that fT is an excellent figure-of-merit which becomes achieve maximum device gain.
useful in comparing devices for gain and noise figure capabili- Another group of characteristics associated with linear (or
ty. High values of It are normally required to achieve higher Class "A") transistors has to do with the degree to which the
gain at higher frequencies, other factors being equal. To the device is linear. Most common are terms such as "Po. 1 dB
device designer, high fT mean decreased spacings between Gain Compression Point" aQd "3rd Order Intercept Point (or
emitter and base diffusions and it means shallower diffusions ITO as it is sometimes called)." More will be said about

351
 EXTRAPOLATED GAIN
I
1dBGAIN ~ /
Ihfell----""'-- ....- - - - hfeo COMPRESSION POINT ~
- - - hfeol.2
-------f--
I I
-- hfeol2
_~
SLOPE REGION
I I f
2.0 -------r-t--
_______ I-_L __ +-==
1.0
I I 1\
I I
fB 2fB

WHERE Ihfel MAGNITUDE OF SMALL·SIGNAL COMMON·

EMITTER (CEI SHORT·CIRCUIT (SCI CURRENT
GAIN, hfe
hleo LOW·FREQUENCY VALUE OF hIe
IB 3 dB CUTOFF FREQUENCY FOR CE, SC
CURRENT GAIN INPUT POWER IN dBm

IT TRANSITION FREQUENCY =Ihlel • fMEAS Figure 18. Linear Gain and 1 dB

WHERE fMEAS. =F~EQUENCY OF MEASUREMENT Compression Point
(NOTE: 2 -Ihfel s ~I
2 high end of dynamic range is the limit imposed by "gain
11 = FREQUENCY AT WHICH Ihlel =1 compression."

Figure 16. Small Signal Current Gain

LINEAR MODULES - Functional Characteristics
versus Frequency
Let's turn now to amplifiers and examine some specifica-
tions encountered that are unique to specific applications.
10 Amplifiers intended for cable television applications are se-
-;:;- lected to have the desired gain and distortion characteristics
:I:
f2. compatible with the cable network requirements. They are
>-
t.> linear amplifiers consisting of 2 or more stages of gain each
::::>
0
0
....... using a push-pull cascade configuration. Remember that a
0:
C1. cascade stage is one consisting of 2 transistors in which a
:I:
>-
0
V common emitter stage drives a common base stage. A basic
~
V \
circuit configuration is shown in Figure 19. Most operate from
0
Z ./
<C a standard voltage of 24 volts and are packaged in an
a:> ./
z
;;: V IVC~ = ~V I industry standard configuration shown in Figure 20. Because

'"-" I they are used to "boost" the RF signals that have been
attenuated by the losses in long lengths of coaxial cable (the
I I
3 5 7 10 20 30 40 losses of which increase with frequency), their gain charac-
IC, COLLECTOR CURRENT (mAl teristics as a function of frequency are very important. These
are defined by the specifications of "slope" and "flatness" over
Figure 17, Gain·Bandwidth Product versus
Collector Current the frequency band of interest. Slope is defined simply as
the difference in gain at the high and low end of the frequency
non·linearities and distortion measurements in the section band of the amplifier. Flatness, on the other hand, is defined
about Linear Amplifiers; however, suffice it to be said now as the deviation (at any frequency in the band) from an ideal
that "Po, 1 dB Gain Compression Point" is simply the output gain which is determined theoretically by- a universal cable
power at which the input power has a gain associated with loss function. Motorola normally measures the peak-to-valley
it that is 1 dB less than the low power gain. In other words, .(high-to-Iow) variations in gain across the frequency band,
the device is beginning to go into "saturation" which is a but specifies the flatness as a "plus, minus" quantity because
condition where increases in input power fail to realize it is assumed that cable television system designers have
increases in output power. The concept of gain compression the capability of adjusting overall gain level.
is illustrated in Figure 18. The frequency band requirements of a CATV amplifier are
The importance of the "1 dB Gain Compression Point" is determined by the number of channels used in the CATV
that this is generally accepted as the limit of non-linearity that system. Each channel requires 6 MHz bandwidth (to handle
is tolerable in a "linear" amplifier and leads one to the conventional color TV signals). Currently available models
dynamic range of the low power amplifier. On the low end in the industry have bandwidths extending from 40 to 550
of dynamic range is the limit imposed by noise, and on the MHz and will accommodate up to 77 channels, the center

352
 conSidering the first three terms, i.e., make the assumption
we can write
F(x) = C1X + C2x2 + C3x3,

JII~ II~
where F is the output signal and x is the input signal. Cl,
C2 and C3 are constants that represent the transfer function
(gain) for the first, second and third order terms.

Figure 19. Basic CATV Amplifier

PIN, INPUT POWER (WADSI

Figure 21. Transfer Function for

Typical Transistor

Now consider a relatively simple input signal consisting of

3 frequencies each having a constant amplitude A. (In the
case of CATV amplifiers, there could be 50-60 channels each
Figure 20. Standard CATV Package having a carrier frequency and associated modulation fre·
(Case 714-04) quencies spread over a bandwidth approaching 6 MHz.) The
frequencies of which are determined by industry standard input signal x then equals ACOS")lt + AcoS'''2t + AcoSOJ3t.
frequency allocations. If we apply this input signal to the transfer function and
Because CATV amplifiers must amplify TV signals and they calculate F(x), we will find many terms involving x, x 2 and
must handle many channels simultaneously, these amplifiers x3 . The "x" terms represent the "perfect", linear amplification
must be extremely linear. The more linear, the less distortion of the input signal. Terms involving x2 when analyzed on a
that is added to the signal and, thus, the better is the quality frequency basis result in signal components at two times the
of the TV picture being viewed. Distortion is generally speci- frequencies of fl, f2 and f3. Also created by x2 terms are
fied in 3 conventional ways - 2nd Order Interrnodulation signal components at sums and difference frequencies of all
Distortion (IMD), Cross Modulation Distortion (XMD) and combinations of fl, f2 and f3. These are called 2nd order
Composite Triple Beat (CTB). In order to better understand intermodulation components. Likewise, the terms involving
what these terms mean, a few words need to be said about x3 result in frequency components at three times the frequen·
distortion in general cies of fl ' f2 and f3. And there are also frequency compo-
First, let's consider a perfectly linear amplifier. The output nents at sum and difference frequencies ( these are called
signal is exactly the same as the input except for a constant 3rd order IMD). But in addition there are frequency compo·
gain factor. Unfortunately, transistor amplifiers are, even nents at fl +,- f2 +,- f3. These are called "triple beat"' terms.
under the best of circumstances, not perfectly linear. If one And this is not all! A close examination reveals additional
were to write a transfer function for a transistor amplifier, a amplitude components at the original frequencies of fl' f2
typical input-output curve for which is shown in Figure 21, and f3. These terms can both "enhance" gain (expansion)
he would find the region near zero to be one best represented or "reduce" gain (compression). The amplitude of these
by "squared" terms, i.e., the output is proportional to the expansion and compression terms are such that we can
square of the input. And the region near saturation, i.e., where divide the group of terms into two categories - "self-expan·
the amplifier produces less incremental output for incremen· sion/compression" and "cross-expansion/compression."
tal increases in input is best represented by "cubed" terms, Self'expansion/compression terms have amplitudes deter-
i.e., the output is proportional to the cube of the input. A mined by the amplitude of a single frequency while cross·ex-
mathematically rigorous analysis of the transfer function of pansion/compression terms have amplitudes determined by
an amplifier would include an infinite number of higher order the amplitudes of two frequencies. A summary of the terms
terms. However, an excellent approximation is obtained by that exist in this "simple" example is given in Table 1.

353
 Table 1. 40
Terms in Output for Three Frequency
Signal at Input
FIRST ORDER COMPONENTS COMMENTS 20
klA cos a + klB cosb + klC cosc Linear Amplification
SECOND ORDER DISTORTION COMPONENTS
k2A2/2 + k2B2/2 + k2C2/2 . 3 DC components

k2AB cos(a+.-b) + k2AC cos(a+.-c) + 6 Sum & Difference Beats

i
a:
k2BC cos(b+.-c) w -20

k2A2/2 cos2a + k2B2/2 cos2b + 3·2nd Harmonic Component

~
k2C 2/2coS2C 5
~ -40
THIRD ORDER DISTORTION COMPONENTS o
k3A3/4 cos3(a) + k3B3/4 c053(b) + 3-3rd Harmonic Component, ~
k3C3/4 cos3(c) 0..0 -60

3k3A2B/4 c05(2a+.-b) + 3k3A2C/4 12 Intermodulation Beats

cos(2a+.-c) +
3k3B2A/4 cos(2b+.-a) + 3k3B2C/4 -ao
cos(2b+.-c) +
3k3C2A/4 c05(2e+.-a) + 3k3C2B/4
eos(2e+.-b) -100 --'---.----r---,----,---,---,-
3k3ABC/2 cos(a+.-b+.-c) 4 Triple Beat Components -90 -70 -50 -30 -10 +10
PIN, INPUT POWER IdBm)
3k3A3/4 cos (a) + 3k3B3/4 cos (b) + 3 Self Compression (k3 is +)
3k3C3/4 cos (c) or Self Expansion (k3 is -) Figure 22_ Amplifier Response Curves
3k3AB2/2 cos (a) + 3k3AC2/2 eos(a) + 6 Cross Compression (k3 is
3k3BA2/2 cos (b) + 3k3BC2/2 cos (b) + or Cross Expansion (k3 is-) distortion is -40 dBc and the signal level is -10 dBm; then
3k3CA2/2 eos(e) + 3k3CB2/2 eos(e)
the 2nd order intercept point is 40 dB above -10 dBm or
Before going into an explanation of the tests performed +30 dBm. Note in Figure 22 that +30 dBm is the value of
on linear amplifiers such as CATV amplifiers. it is appropriate output signal at which the fundamental and 2nd order re-
to review a concept called "intercept point." It can be shown sponse lines cross. The beauty of the concept of "intercept
mathematically that 2nd order distortion products have ampli- point" is that once you know the intercept point, you can
tudes that are directly proportional to the square of the input determine the value of distortion for any signal level -
signal level. while 3rd order distortion products have ampli- provided you are in a region of operation governed by the
tudes that are proportional to the cube of the input signal mathematical relationships stated, which typically means
level. Hence, it can be concluded that a plot of each response IMD's greater than 60 dB below the carrier.
on a log-log scale (or dB/dB scale) will be a straight line with Likewise to determine 3rd order intercept point, one must
a slope corresponding to the order of the response. Funda- measure 3rd order distortion at a known signal level. Then
mental responses will have a slope of 1, the 2nd order take half the value of the distortion (expressed in dBc) and
responses will have a slope of 2 and the 3rd order responses add to the signal level. For example, if the Signal level is
a slope of 3. Note that the difference between fundamental +10 dBm and the 3rd order distortion is -40 dBc, the 3rd
and 2nd order is a slope of 1 and between fundamental and order intercept point is the same as the 2nd order intercept
3rd order is a slope of 2. That is to say, for 2nd order point or 10 dBm + 20 dB = 30 dBm. Both 2nd order and 3rd
distortion, a 1 dB change in signal level results in a 1 dB order intercept points are illustrated in Figure 22 using the
change in 2nd order distortion; however, a 1 dB change in values assumed in the preceding examples. Note, also, that
signal level results in a 2 dB change in 3rd order distortion. in general the intercept point for 2nd and 3rd order distortion
This is shown graphically in Figure 22. Using the curves of will have the same value unless circuits are used that
Figure 22, if the output level is 0 dBm, 2nd order distortion suppress even-order spurious responses, etc. However,
is at -30 dBc and 3rd order distortion is at -60 dBc. If we even in this situation the concept of intercept point is still valid;
change the output level to -10 dBm, then 2nd order distortion the slopes of the responses are still I, 2 and 3 respectively
should improve to -40 dBc (-50dBm) but 3rd order distortion and all that needs to be done is to specify a 2nd order
will improve to --80 dBc (-90 dBm). Thus we see that a 10 intercept point different from the 3rd order intercept point.
dB decrease in signal has improved 2nd order distortion by With this background information, let's turn to specific
10 dB and 3rd order distortion has improved by 20 dB. distortion specifications listed on many RF linear amplifier
Now for "intercept point." We define the "intercept point" data sheets. If the amplifiers are for use in cable television
as the point on the plot of fundamental response and 2nd distribution systems, as previously stated, it is common
(or 3rd) order response where the two straight lines intercept practice to specify Second Order Intermodulation Distortion,
each other. It is also that value of signal (hypothetical) at Cross Modulation Distortion and Composite Triple Beat. We
which the level of distortion would equal the initial signal level. will examine these one at a time. First, consider Second
For example, if at our point of measurement, the 2nd order Order Intermodulation Distortion (IMD). Remember these are

354
unwanted signals created by the sums and differences of any
two frequencies present in the amplifier. IMD is normally
specified at a given signal output level and involves 3
channels ~ two for input frequencies and one to measure
1 eom
the resulting distortion frequency. The channel combinations
are standardized in the industry but selected in a manner -<JBc
that typically gives a worst case condition for the 2nd order
distortion results. An actual measurement consists of creat-
ing output signals (unmodulated) in the first two channels
listed and looking for the distortion products that appear in
the 3rd channel. If one wishes to predict the 2nd order IMD
r 1
--LJL..L.L.LLJ......L.ll.L.LLU..L.U.J...LU-I..LJ..JLU..L.U.J...L'--_

FREQUENCY
DISTORTION
NOISE FLOOR

that would occur if the signals were stronger (or weaker), CW CARRIERS AT STANDARD CATV FREQUENCIES
it is only necessary to remember the 1:1 relationship that led
to a 2nd Order Intercept Point. In other words, if the specifica- Figure 24, Frequency - Power
Relationships for eTB
tion guarantees an IMD of -68 dB Max. for a Vout =
+46 dBmV per channel, then one would expect an IMD of
-64 dB Max for a Vout = +50 dBmV per channel, etc, Industrie Norm (German Industrial Standard) and the stan-
Cross Modulation Distortion (XMD) is a result of the dard that applies for CATV amplifiers is #45004B. DIN45004B
cross-compression and cross-expansion terms generated by is a special case of a three channel triple beat measurement
the third order non-linearity in the amplifier's input-output in which the signal levels are adjusted to produce a ~O dBc
transfer function. In general, the XMD test is a measurement distortion level. An additional difference from normal triple
of the presence of modulation on an unmodulated carner beat measurements IS the fact that the levels are different
caused by the distortion contribution of a large number of for the three combining signals. If we call the four frequencies
modulated carriers. The actual measurement consists of involved in the measurement F, F 1, F2 and Fm , then F is
modulating each carrier with 100% square wave modulation set at the required output level that, along with F1 and F2
at 15.75 kHz. Then the modulation is removed from one lead to a distortion level 60 dB below the level of F, and F1
channel and the presence of residual modulation is measured and F2 are adjusted to a level 6 dB below the level of F.
with an amplitude modulation (AM) detector such as the Distortion IS measured at the frequency Fm. Frequency
commercially available Matrix RX12 distortion analyzer. Pow- relationships (used by Motorola) between F, F 1, F2 and Fm
er levels and frequency relationships present in the XMD test are as follows: F1 = F - 18 MHz; F2 = F - 12 MHz and Fm
are shown in Figure 23. = F + F2 - F1. Figure 25 illustrates the frequency and power
level relationships that exist in the DIN test.
MEASUREMENT

~
CARRIER
/' POUT POUT

1
POUT - 6 dB -ll dBc
'"w
:;:
i
-r
o
Cl.
f-
=>
Cl.
f-
=>
r
o

FREQUENCY
II
DISTORTION
NOISE FLOOR 11 I
1 DISTORTION

---f---f-----+---;:'---- NOISE FLOOR

ALL CARRIERS ARE 100% SQUARE·WAVE MODULATED AT Fl F2 FM
15.75 kHz, EXCEPT THE MEASUREMENT CARRIER
FREQUENCY
Figure 23. Frequency ~ Power Fl=F-18MHz
Relationships for XMD F2 = F - 12 MHz
FM = F + F2 - Fl

Composite Triple Beat (CTB) is quite similar to XMD except Figure 25. Frequency - Power
all channel frequencies are set to a specified output level Relationships for DIN45004B
without modulation. Then one channel frequency is removed
and the presence of signal at that frequency is measured. Linear amplifiers aimed at television transmitter applica-
The signals existing in the "off" channel are a result of triple tions will generally have another distortion test involVing 3
beats (the mixing of 3 signals) among the host of carrier frequencies. Basically it is another 3rd order intermodulatlon
frequencies that are present in the amplifier. A graphical test with power levels and frequencies that simulate a TV
representation of the CTB test is shown in Figure 24. signal. Relative power levels and frequencies are shown in
European cable television systems usually Invoke an addi- Figure 26.
tional specification for linear amplifiers which is called the Thermal resistance ratings' of CATV modules (as well as
DIN test. DIN is a German standard meaning Deutsche Power modules described in the next section) are, perhaps,

355
 overall gain and mechanical form factor suitable for a particu-
lar application.
SOUND (-7 dB or) Power modules for mobile and portable radios also have
VISION (-8 dB) CARRIER (-10 dB) unique specifications related to their applications. One of the
CARRIER SIDEBAND(_16dB)A most significant is that of stability. The stability of a module
OJ
~ ..,,... SIGNAL ~ [II is affected not only by its design but also by many external
:3- -10 factors such as load and source impedances, by the value
!5! -20 of supply voltage and by the amount of RF input signal.
~
UJ -30 External factors influencing stability are highlighted in Figure
:s
2:
-40 27. Combinations of these factors over a range of values for
each factor must be considered to be certain the module will
~ -50
remain stable under typical conditions of operation. The
-80 1 greater the range of values for which stability is guaranteed,
-70 ~-r-...,....--+-""""'---,----I--'--'-"""""r--1r----'
0.01 0.02 0.05 0.1 0.2 0.5 1 the more stable is the module. Of particular importance is
~F. FREQUENCY (MHz)
the degree of load mismatch which can be tolerated as
evidenced by the stated value of load VSWR (the larger the
Figure 26. 3rd Order IMD Test for TV value, the better). Stability specifications are generally eva-
luated thoroughly during the pre-production phase and then
conspicuous by their absence. Because the amplifiers have
guaranteed but not tested on a production basis.
several heat sources that are contained within the amplifier,
it is necessary for the user to provide sufficient heat sinking
to the case of the amplifier such that the operating case
temperature never exceeds its maximum rating. Actual power
dissipation can be determined by considering the operating
voltage and the maximum current rating of the device. Actual
RF power output of most CATV modules is at most a few
milliwatts which means that most of the power consumed by
the module is dissipated in the form of heat. Typically this >---~
power dissipation runs in the range of 5 watts for conventional
modules such as the MHW5122A but can increase to 10
watts for a power doubler such as the MHW5185.
Because linear (and power) modules have inputs and
outputs that are matched to standard system impedances
(75 ohms for CATV amplifiers and 50 ohms for power
amplifiers), test circuits and fixtures are generally less impor- Figure 27. External Factors Affecting Stability
tant than for discrete devices. Basically test fixtures for
modules are simply means of making RF and DC power
Efficiency is becoming an increasingly important specifica-
connections to the module being tested. It is important if you
tion particularly in modules for portable radio applications.
build your own test fixture that you carefully decouple the
The correct way to specify efficiency is to divide the net
DC power lines and that you provide adequate heat sinking
increase in RF power (output power minus input power) by
for the device under test (D.U.T.). However, if the fixture is
the total DC power consumed by the module. It is generally
for linear modules involving low values of input and output
specified at rated output power because efficiency will de-
VSWR, then it is extremely important, for accuracy, that the
crease when the module is operated af lower power levels.
input and output networks (lines and connectors) be designed
Be careful that the specification includes the current supplied
to exhibit return losses greater than 35 dB. Motorola modifies
for biaSing and for stages other than the output stage.
the RF connectors used in the fixture and, then, calibrates
Overlooking these currents (and the DC power they use)
their fixtures to be sure that the fixture does not introduce
results in an artifically high value for module efficiency.
errors in measuring module return loss.
Most power module data sheets include a curve of output
power versus temperature. Some modules specify this "pow-
POWER MODULES - Functional Characteristics er slump" in terms of a minimum power output at a stated
Power modules are generally used to amplify the transmit maximum temperature; others state the maximum permissi-
signals in a 2-way radio to the desired level for radiation by ble decrease in power (in dB) referenced to rated power
the antenna. They consist of several stages of amplification output. It is important to note the temperature range and the
(usually common emitter, Class C except for some low level other conditions applied to the specification before passing
stages that are Class A) combined in a hybrid integrated judgement on this specification.
assembly with nominally 50 ohm RF input and output imped- Generally power modules·, like linear modules, do not have
ances. Selection of a module involves choosing one having thermal resistance specified from die to heatsink. For multiple
the proper operating voltage, frequency range, output power, stage modules, there would need to be a specific thermal

356
resistance from heatsink to each die. Thermal design of the +4
module will take care of internal temperature rises provided
the user adheres to the maximum rating attached to the
0
ak MH~~=B20MHZ
f-I = -J,.. T - -= ---= -- --

E
+3
operating case temperature range. This is an extremely '"os
a: 0 II
important specification, particularly at the high temperature w
end because of two factors. First, exceeding the maximum
case temperature can result in die temperatures that exceed
;;:
0
0..
>- +2
(/
:::> 0 Vsl = BV
0..
200'C. This, in turn, will lead as a minimum to decreased >-
:::> Vs3 = 12.5 V f--
0 Pin = 1 mW
operating life and as a maximum to catastrophic failure as
a result of thermal runaway destroying the die. Second,
hybrid modules have components that are normally attached
0..0
S +1
0 r r f--

to a circuit board and the circuit board attached to the flange

with a low temperature solder which may become liquid at 2 3 4 5 6 7 B 10
VConl, GAIN CONTROL VOLTAGE (Vdcl
temperatures as low as 125'C. Again, the power to be
ICONT. -130 mA@VCONT. = 9 V
dissipated can be determined by considering the RF output
power and the minimum efficiency of the module. For exam- Figure 2B. Output Power versus Gain
ple, for the MHW607, output power is 7 watts and input power Control Voltage
is 1 mW; efficiency is 40% minimum. Thus the DC power I I I
input must be 7/0.4 =17.5 watts. It follows that power dissipa- Pin=1 mW
tion would be 17.5-7 = 10.5 watts worst case. vsI = vs2 = vs3 = 6 V
Storage temperature maximum values are also important
as a result of the melting temperatures of solder used in
assembly of the modules. Another factor is the epoxy seal _f=B50MHz
./'" BOO _
used to attach the cover to the flange. It is a material similar
to that used in attaching caps for discrete transistors and,
U;. 7' 920

as stated earlier, is known to deteriorate at temperatures ~ /'

greater than 150'C.
Modules designed for use in cellular radios require wide
AV
7{:
dynamic range control of output power. Most modules provide
for gain control by adjusting the gain of one (or two) stages 00 I 2 3 4
by means of· changing the voltage applied to that stage(s). VConl, GAIN CONTROL VOLTAGE (Vdcl
ICONT. -100 ~lA @ VCONT. = 4 V
Usually the control is to vary the collector voltage applied
to an intermediate stage. A maximum voltage is stated on Figure 29. Output Power versus
Control Voltage
the data sheet to limit the control voltage to a safe value.
This form of gain control is quite sensitive to small changes distance from the transmit frequency. Caution must be taken
in control voltage as is evidenced by viewing the output power in making measurements of noise power. Because the levels
versus control voltage curves provided for the user (an are generally very low (--85 dBm), one must be assured of
example is shown in Figure 28). An alternative control a frequency source driving the module that has extremely
procedure which uses much less current is to vary the low noise. Any noise on the input signal is amplified by the
base-to-emitter voltage of the input stages (which are gener- module and cannot be discerned from noise generated within
ally class A) as illustrated in Figure 29. This is of particular the' module. Another precaution is to be sure that the noise
significance in portables because of the power dissipated in floor of the spectrum analyzer used to measure the noise
the control network external to the module. power is at least 10 dB below the level to be measured.
While not stated on most data sheets, it is always possible
to control the output power of the module by controlling the DATA SHEETS OF THE FUTURE
RF input signal. Normally this is done by means of a PIN World class data sheets in the next few years will tend to
diode attenuator. Controlling the RF input signal allows the provide more and more information about characteristics of
module to operate at optimum gain conditions regardless of the RF device; information that will be directly applicable by
output power. Under these conditions, the module will pro- the engineer in using the device. Semiconductor manufactur-
duce less sideband noise, particularly for srnall values of ers such as Motorola will provide statistical data about
output power, when compared to the situation that arises from parameters showing mean values and sigma deviations. For
gain control by gain reduction within the module. discrete devices, there will be additional data for computer
Noise produced by a power module becomes significant aided circuit design such as SPICE constants. The use of
in a duplexed radio in the frequency band of the received typical values will become more widespread; and, the avail-
signal (see Figure 30). A specification becoming more promi- ability of statistical data and the major efforts to make more
nent, therefore, in power modules is one that controls the consistent products (six-sigma quality) will increase the use-
maximum noise power in a specified frequency band a given fulness of these values.

357
 SUMMARY
POUT 33dBm Understanding data sheet specifications and what they
mean can be a major asset to the circuit designer as he goes
about selecting and using RF semiconductors for his specific
application. This paper has emphasized some unique data
sheet parameters of RF transistors and amplifiers and has
explained what these mean from the semiconductor man-

11
o
TRANSMIT SIGNAL
(806-940MHz)

/ 4 5 MHz 30KHz RECEIVE BAND

ufacturer's point-of-view. It is hoped this effort will help the
circuit engineer make his selection and use of RF semicon-
ductors more efficient and effective.
The RF transistor and the amplifiers made with RF transis-
MAXIMUM NOISE POWER tors are unusually complex semiconductor products and
~85dBm

--
FREQUENCY

Figure 30. Noise Power in Receive Band

difficult to fully characterize. Not all information about RF
device characteristics has been explained in this paper. Nor
can all be covered in a data sheet. The circuit design engineer
should contact the device manufacturer for more detailed
information whenever it is appropriate. Most if not all current
manufacturers of RF transistors and amplifiers have exten-
sive applications support for the express purpose of assisting
the circuit designer whenever and wherever assistance is
needed.

358
 AN1122
Running the MC44802A PLL Circuit
Prepared by
Paul Brownlee/Linear Applications
Bipolar Analog IC Division

INTRODUCTION
The MC44802A is the PLL portion of a tuning circuit - 12C interface for MCU control.
intended for applications involving television, FM radio, and - Selectable +8 prescaler and a 15-bit divider accept fre-
Set-Top converters up to 1.3 GHz. Coupled with a VCO and quencies up to 1.3 GHz.
mixer, a complete tuning circuit can be formed. The tuning - Programmable reference divider.
frequency is controlled through an MCU serial interface (12C). - Phaselfrequency comparator output can be set to high
impedance for disabling.
As noted in the MC44802A data sheet, an MCU is recom-
- Op amp provides direct tuning voltage output (0.3 V to
mended for sending the serial control bytes. This application
30 V).
note describes combining an MC68HCll E9 with an
- Seven programmable output buffers (10 mA, 12 V) for
MC44802A in a tuner design. The information is sufficiently band switching, etc.
general however, that most any MCU could be used for this - Output options for 62.5 kHz, reference frequency and the
function. Those with a limited background in the use and programmable divider which are useful for system de-
programming of MCUs will find the information adequately bugging.
detailed to permit a thorough understanding.
Figure 1 shows a simplified block diagram of the
A Look at the MC44802A MC44802A. The 12C Bus receiver is a central block that
The MC44802A is manufactured using Motorola's high controls the HF prescaler, 15-bit divider, the oscillator (typ.
density bipolar MOSAIC process. It features: 4.0 MHz crystal) reference divider, and the output buffers.

VCC1

Progr.
Relerence
1953 Hz
Divider
3906 Hz
7812 Hz
15625 Hz

Phase
Comparalor 17

Figure 1. MC44802A Simplified Block Diagram

359
The 12C Bus transfer is initiated by a master and acknowledged by a slave
The 12C (Inter-Integrated Circuit) Bus required by the device. Each slave is assigned a unique address, allowing
MC44802 is a serial transfer process using two wires for data multiple 12C devices to be connected to a single bus. An ex-
and clock (SDA - serial data, SCL - serial clock). Each ample of a data transfer is shown in Figure 2.
START STOP

uf*\,-__~: .!, ,;-AL_BYT- -,;

r--'

1flJi\ :~ MI' ~
tOLE ADDRESS I
I I I
I

\
SDA I 8
_ _ _-+-,r
I
L ADDRESS
BITS
I
I : I I
I I
SCL
I I

ADX ACK DATA ACK DATA ACK

L_-'
Figure 2. Complete Data Transfer Process

Referring to Figure 2: the master terminates the transfer and generates a Stop
Idle - When there are no transfers taking place on the bus, Condition.
SDA and SCL idle high.
The Microcontroller
Start - A master initiates a data transfer by pulling SDA low
while maintaining SCL in the high state. At this time all The MCU chosen for an 12C data transfer must have a serial
slave devices on the bus are listening for their address. port with the following characteristics:
Address - The first byte is senllo select a slave device(s). - Two-lines, clock and data, with open drain (collector)
Slaves that have read and write capabilities have a unique outputs
address for each. Upon completion of an address trans- - 8-bit transfer buffer
mission, the master must leave the data line high and - An 12C interface or 1/0 serial lines capable of emulating
create the ACK clock pulse. The slave device is to ac- 12C protocol (Idle, StarVStop conditions and ACK pulse).
knowledge by pulling the data line to a stable low state be- Suitable microcontroller examples are the MC68HCll or
fore the end of the ACK pulse. From this point until a Stop MC68HC05 families.
Condition is generated, only the.selected slave(s) device A SAMPLE SYSTEM
is active. Overview
Data - The transfer continues with data bytes sent in the The remainder of this application note is devoted to describ-
same manner as the address byte. An acknowledge is ing a sample MC44802A system. From a high level view this
required at the end of each byte (except the last one). The
system is simple (see Figure 3). Whenever the push button is
master indicates the last data byte by sending the
pressed the circuit responds by changing the tuning frequen-
acknowledge (low) bit rather than leaving SDA high for
slave acknowledge. cy, and provides a display indicating the frequency. The follow-
Stop - The master creates a Stop Condition by sending ing paragraphs describe this system which was built and
SCL high followed by a low-to-high SDA transition. This tested to demonstrate the functionality of the MC44802A. In-
leaves the bus back in the idle state. cluded are descriptions of each segment of this system - PLL
If a required acknowledge bit is not received for any reason, tuning circuit, MCU control, user interface and LED displays.

A Interrupt SDA
Pushbutton A
Switch
Circuit U Latch MCU
II SCL
PLL

Irc

.~
Bus

'5 V

3-Digit
L-. Frequency
Display

Figure 3. Simplified Block Diagram of the Video Frequency Controller

360
PLL Tuning Circuit Implementation
The MC44802A works with an MC1648 voltage controlled phase detector input of the MC44802A. With the feedback
oscillator (VCO) to form a Phase-Locked Loop (see Figure network (G(s)) the MC44802A produces a stable vOltage
4). The MC1648 requires an external parallel tank circuit input to the tank circuit. A general purpose open collector
consisting of an inductor (L) and capacitors (Cv and Cx). output buffer (B2, Pin 9) is used in this application to switch
Varactor diodes (Cv) are used in this case to provide a volt- a capacitor (Cx) in and out of the tank circuit. When that out-
age variable capacitance for the VCO. The MC1648 may be put buffer is switched low (by writing a "1" to it), the pin diode
operated from a +5.0 or -5.2 Vdc supply, depending upon (Dl) conducts making Cx part of the tank circuit (Cx//(Cv/2)).
system requirements (+5.0 V in this case). Its maximum When the output buffer is open Dl does not conduct, thereby
frequency is typically 225 MHz. presenting a high impedance to Cx, making it ineffective. The
The VCO output is connected through a capacitor to the tank circuit's capacitance is then Cv/2.

1
r - - -.......-~10
14

MC1648
VCO

+-__......_--J'-j 12
Fosc

0.1 ~F

r------------------,I
I G(s) 47 nF
I I
I 22 k I
I I
I _ _ _ _ _ _ _ _22_k _ _
~ _JI

_~ I :~ I
1.0 of

+33 V >'-_...v:tu=n_e__- ++_-_-_-_-_-_- ...._-_-_-_-_--j-ll :sJ--d4802A

2 PLL
1.0 nF
>---+--....,.---,--1
+5.0 V

I 2.0 k
,
14 15 16

4.0 MHz
1:
I r
I
--..,
12C I
l_ 12pF
I
0.1 ~F
I I
I
Bus I
I
I ~ _ _ ...I
Band I
Switching
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ -'I seL SOA

Figure 4. Sample PLL Tuning Clrcuil

12C Data
CA - Chip Address a a
Configuration data is sent by the MCU to the MC44802A 12C
Bus Interface in five bytes as shown in Figure 5. Communica-
CO - Control Info. R2 Rl RO
tion of the data is covered in the section describing MCU BA - Band Info. B2 Bl BO
Implementation.
FM - Frequency Info. 0 N14 N13 N12 NIl Nl0 N9 N8
FL - Frequency Info. N7 N6 N5 N4 N3 N2 Nl NO

Figure 5. MC44802A j2C Byte Definitions

361
Referring to Figure 5: Rl RO Divider Ratio
CA - 12C chip address for the MC44802A, $C2 (fixed
internally). 0 0 2048
0 I 1024
CO- Sets up the 4.0 MHz oscillator divider ratio (R1, RO),
I 0 512
prescaler (P), test outputs (R2, R3) and phase compara-
1 1 256
tor output state (R2, R6, T) according to Figure 6.
BA - Each band buller (Pins 7-13) can be setto active low
P Prescaler
by writing a 1 to it.
FM, FL - These two bytes set the tuning frequency. Their 0 Enabled
relationship with frequency (at Pin 4) depends on whether 1 Bypassed
or notthe prescaler is enabled, and the setting olthe refer-
ence division ratio: R2 R3 Pin 10 Pin 11

N = Fout x Divider ratio (prescaler disabled)

0 0 - -
0 1 62.5 kHz -
Fcrystal 1 0 F (ref) FBY2
Fout x Divider ratio
1 1 - -
or: N = -""'-'----c:-- (prescaler enabled)
Fcrystal x 8 Phase Comparator
R2 R6 T
A hexadecimal representation of N at FM and FL sets the Output State
tuning frequency (Fout). 0 0 a Normal Operation
Per Figure 5. the address is sent and followed by CO, BA 0 0 1 Off (High Impedance)
andlor FM. FL. Control and frequency byte pairs are distin- a 1 a High
guished in the first bit (1 for control, 0 for frequency). There- a 1 1 Low
fore, it is not necessary to always send 5 bytes. A data transfer 1 a 0 Normal Operation
could consist of CA-CO-BA, or CA-FM-FL. The following ex-
1 a 1 Off (High Impedance)
1 1 0 Normal Operation
ample describes the five hex control bytes required to instruct 1 1 1 Off (High Impedance)
the circuit to tune to VHF Channel 2 (101 MHz):
1) $C2(11000010) - This isthe MC44802A address. The Figure 6_ CO Bit Specifications
first byte of all MC44802A transmissions must be $C2.
2) $88(10001 000)-R2, R6andTare setto OOOto indicate
FM FL Fout{MHz) Display FM FL Fout{MHz) Dlsplal
normal operation. P=O enables the internal prescaler. R1,
RO=OO sets the divider ratio to 2048 which gives the $02 $80 10 None $IA $CO 107 (ch3) C03
greatest frequency resolution in the < 512 MHz region. $06 $40 25 None $IC $40 113 (ch4) C04
R3 is optionally set high to output a 62.5 kHz test signal $08 $CO 35 None $IE $CO 123 (ch5) C05
at Pin 10 (B4). SOC $80 50 None $20 $40 129 (chS) COS
3) $04 (0000 0100) - Sets band buller B2 (Pin 9) high $12 $CO 75 075 $25 $80 150 150
$19 $00 100 090 $2A $80 170 170
thereby disabling Cx.
$19 $40 101 (ch2) CO2 $32 $00 200 None
4) and 5) $1940 (0001 1001,01000000) - With the given
prescaler and divider values, the frequency is defined by P.O. RO.R1-0
N = Fout115,625 Hz. For 101 MHz:
Figure 7_ Sample Frequency Control Bytes
N 101 MHz = 6464
15,625 Hz
which is represented in hex by $19 40. sample MC44802A interface to this MCU. A full listing of the
code is included in the Appendix. An HC1'1 program is written
Note that this is not a unique solution to getting 101 MHzout without line numbers. The code shown is the 'program.lst' ver-
of the circuit since a dillerent combination of prescaler setting, . sion created by the assembler which inserts the line numbers
divider ratio and N could be used. Figure 7 shows a table offre- and machine code.
quency control bytes (FM, FL) used in this application note. In
all cases the internal prescaler is enabled, and the divider ratio Pin Descriptions
is 2048.
Note that only the HC 11 pins used in this exercise are shown
in Figure 8. Many olthe I/O pins can be configured fordillerent
MCU Implementation
functions throughout the. execution of a program. This is noted
The Motorola MC68HC11 E9 has the required characteris- by pins labeled name1/name2. The names in bold indicate the
tics for generating 12C transfers. It is equipped with parallel functions used. They will be referred to by their functional
and serial 110 ports, timers, a pulse accumulator, an AID con- name from here forward and are briefly explained below. Refer
verter system and expansion capability for multiple MPU sys- to the Appendix for code lines.
tems. Each of these functions must be set-up and activated in IC3 - (Input Capture 3) is an edge triggered interrupt pin
user-programmed software to be part of the system. This al- that can be configured for rising, falling, or both edges. It
lows the user to be concerned with only applicable functions. is configured to respond to rising edges (code lines 70 and
What follows are hardware and software descriptions for the 71). Ali controller output changes are initiated at this pin.

362
 +5.0 Vdc
~ I I I I
1 59 60 57 58
2.4 k +30 Vdc
SS

Pushbutton I PAO/IC3 34
25 I--
PD2/MISO
'(
I Switch
I----u- MCU
MC68HC11E9
22

PD3/MOSI
I--- SDA
23 MC44802A
STRB PLL
6
PD4/SCK
24 SCL

27 •••• 30 35·····42
+5.0V ~ut
PA71
OC1
......
...... PA41
OC4
PB71
A15
......
. ..... PBOI
AS
~ FO
2.4 k

- 3·Digit
Frequency
Display

Figure 8. MCU Implementation

SPI (Serial Peripheral Interface) Pins: Software Description

MOSI- (Master Out Slave In) is the serial output line used
The software is written in two functional blocks - a main
for 12C data communication with the PLL chip. The con·
program and an interrupt service routine (ISR). The main pro-
troller is configured as the master device in this exercise.
This line is referred to as PORT D, bit 3 when the SPI is gram sets up the MCU ports and control registers. It then goes
disabled (the SPI is enabled only during a serial transfer). into a low power stopped state until an interrupt is initiated. The
It is essential that this be configured as an open drain out· interrupt service routine creates the required serial and paral-
put (an external pullup is used) when programming the lel output signals, and then returns control to the main program
SPI Control Register (SPCR, code lines 122-123). This which waits for another interrupt.
allows the slave device (the PLL) to acknowledge by pull- The interrupt structure provides flexibility for expansion of
ing the data line low. this system. Other functions can be easily added to the main
MISO - (Master In Slave Out) is a serial input line to the program without affecting performance of the serial interface.
controller. Tied to MOSI, it forms a bi-directional data port But for this exercise, the main program is kept simple. It sets
permitting the MCU to read the acknowledge pulse.
up memory address references (lines 20-38), parallel Port A
SCK - is the clock line in the 12C protocol. It is referred to
(lines 46-48), parallel Port B (line 51) and the interrupt control
as PORT D, bit 4 when the SPI is disabled.
SS - is a slave select line that must be tied high (inactive) (lines 66-73). The main program then goes into its low power
to set the MCU as the master. wait state. It does nothing until control is transferred to the ISR.
An ISR flow diagram is included as Figure 10 for clarification.
Port A Pins: The following program was written under the assumption
PA7- is a general 1/0 pin. It must be configured as input that eventually the system will be run as a stand alone. Thus,
or output depending on the desired function. It is confi- the serial bytes pertaining to tuning requirements must be
gured here as an output (code lines 46-48) to drive a bit stored in the MCU EEPROM. To avoid program modification
in the seven segment display (in conjunction with each time such requirements change, data space has been al-
PA6-PA4). located for this function beginning at location B700. The pro-
PA6 to PA4 - are fixed direction output pins also used for gram requires a specific data format while maintaining appli-
the seven segment displays.
cation flexibility.
The first requested transfer will output bytes starting at loca-
Port B Pins:
PB7 to PBD - are fixed direction output pins used for the tion B700. Transmission continues until a null data byte ($00)
seven segment displays. is encountered (which is not outputted). The two bytes follow-
STRB - is an enable line that provides an active low pulse ing contain the display information. Transmissions of this for-
each time new data is written to Port B. This is used to mat should follow consecutively as desired with another null
latch data into the display decoders. after the last display value. 'The program will then reset the

363
data pointer to 8700. Figure 9 shows the frequency data space Note that this example contains two five-byte transmissions
for the sample system. It contains bytes for various frequen- and the remainder are three-byte transmissions. Three-byte
cies from 75 MHz to 170 MHz. 8and switching is done between transmissions are useful as unchanged control, and band in-
the 90 MHz and 101 MHz (VHF Channel 2) frequency values. formation need not be repeated. The displays will cycle
through '075', '090', 'C02', 'C03', 'C04', 'COS', 'C06', 'ISO', and
8700> c2 88 0412 cO 00 Of 75 c21610 00 Of 90 c2 88
8710> 0119 40 00 cf 02 c21a cO 00 cf 03 c21c 40 00 '170' which is a mix of frequency (in MHz) and VHF channel
8720> cf 04 c21e cO 00 cf 05 c2 20 40 00 cf 06 c2 25 displays. The lower four-bits of the first display value (set to f)
8730> 80 00 11 50 c2 2a 80 00 11 70 00 If If If If If are ignored since they are unconnected.

Figure 9. Sample System Control Data

No

Reset Pointer to
Top of Data Space

Pulse

Figure 10.ISR Flow Diagram

364
 Figure 11 is a picture of the first byte of a transmission (the high when the button is released. The cross-coupled NAND
PLL address). Note that the start condition is generated at the gates eliminate the effect of switch bounce.
scope trigger point and the bit stream 11000010 ($C2) is
clocked in on rising edges. After the eighth clock pulse, the r-----------------,I
I IC3
data line is released by the MCU and quickly acknowledged I
(pulled low) by the PLL chip. Refer back to Figure 2. I
I
I
I
t;,Vl = 4.96 V I
t;,V2 = 0.40 V I
I
I
~ ___ ~ _____________ J

Figure 13. Pushbutton Interrupt Circuit

This will provide a clean low-going pulse to trigger one of the

controller's edge-sensitive interrupts (IC3). IC3 is pro-
grammed to respond to the rising edge of the pulse to facilitate
further debouncing in software.

2V 5V PEAKDET 20 ~s Tek Frequency/Channel Display Implementation

The display is implemented using three seven-segment
Figure 11. PLL Address Transmission
(common cathode) LEDs. They are driven by parallel ports (A
and B) of the controller in the ISA. These ports send the display
If the PLL were not responding, the data line would have re- information to the hexadecimal-to-seven segment decoders
mained high ratherthan looking like aspike. This acknowledge (MCI4495-1). The STRB output from the controller is pulsed
is clocked in and the next byte is ready for transmission. Figure low each time data is written to Port B and is used to latch the
12 illustrates this by showing a full three-byte transmission that decoders.
updates the PLL tuning frequency. Display information is programmed in data space as shown
in Figure 9. Outputs are done in the ISR to Port A (lines
147-148) and then to Port B (lines 150-151), and are done in
t;,Vl = O.OB V this order because a write to Port B causes the STRB decoder
t;,V2 = 0.20 V enable pulse. Figure 14 shows the frequency display circuit.
The MC14495-1 is a hexadecimal-to-seven segment Latch/
Decoder Driver. It is an improved version of the MC14495 with
CMOS input levels and decreased propagation delays. This
permits them to be operated directly from the limited duration
pulse (STRB) generated by the MCU. The MC14495-1 has in-
ternal series output resistors (typically 290 il) allowing direct
co·nnection to a common cathode LED display.

SUMMARY

This application note should serve as a reference for using

2V 5V PEAKDET 0.1 ms Tek
an MC44802A for various tuning applications. It is not intended
Figure 12. Three Byte Data Transmission as a replacement for the MC44802A Data Sheet nor the
MC68HC11 Reference Manual. Its intention is to help bring
these tools together to build a working system.

Interrupt Circuitry Implementation

Bibliography
The interrupt circuit (Figure 13) is designed as a simple de- (1) MC44802A Data Sheet
bounced momentary pushbutton switch. The switch must (2) MC1648 Data Sheet
have a normally open (N/O) and a normally closed (N/C) con- (3) M68HCll E9 Data Sheet
tact. The output of the circuit is normally at VCC (+5.0 V). (4) M68HCll EVBU/ADI
When the button is pushed the output goes low. It comes back (5) MC14495-1 Data Sheet

365
 STRB PA7 PA6 PAS PM PB7 PB6 PBS PB4 PB3 PB2 PBl PBO
r --- I - - -- - ------ - - -r------- r-- -- -- -- ,
0 C B A 0 C B A 0 C B A

10 9 6 5 10 9 6 S 10 9 6 S

L.7
LE
MC14495-1 -7
LE
MC14495·1 L.. .,7
LE
MC14495·1

,-
7,f

c,_,
7{'
I-I -, 71'

~C

,-
_____________________________________ J
~

Figure 14. Three Digit Display Circuit

* c,=

APPENDIX 1 - Microprogramming Basics/

Program Listing

The M68HCll EVBU (Universal Evaluation Board) pro· sembler. This program will generate the necessary object
vides a friendly environment for developing an HCll system. code and, if desired, a listing file. The object file (xxxx.list) is
Programming is a three step process which includes writing then downloaded into the HC1l:
software, assembling it, and downloading it to the MCU. program. list - listing file,
program.s19 - file to be downloaded.
Writing/Modifying Software
Software should be created as a text file (e.g., pro·
gram.asm) following the format of HCll assembly com.· Downloading/Debugging
mands. Full description of each command can be found in the Performance of the software and hardware should be eva-
M68HC 11 Reference Manual. luated with the help of a personal computer (Macintosh or a PC
compatible) and a terminal emulation package such as Free-
Program Assembly term or Kermit. This program allows communication between
Once a program has been written, it is run through an as· the EVBU and computer.

366
 APPENDIX 2 - Program Listing

0001 • Motorola SPS - Bipolar Analog IC Division

0002 • Written by Paul Brownlee
0003
0004 • This M68HCll code provides control bytes to operate
0005 • an MC44802A (Motorola PLL Tuning Circuit) via 12C protocol
0006 • The bytes are to be determined by the user and placed in
0007 • memory starting with location B700 (see technical data sheet
0008 • for control byte information).
0009
0010 • Communication is achieved using the HC 11 's Synchronous Serial
0011 • Peripheral Interlace (SPI) to generate both the clock.and data
0012 • signals. The main program is a short monitor loop. Output is
0013 • implemented as an interrupt service routine for the edge
0014 • triggered interrupt IC3. Thus, the location to the routine,
0015 • B640, must be entered in user RAM as a jump destination for the IC3
0016 • service routine. The interrupt can then be implemented as a
0017 • simple debounced switch.
0018
0019 • REFERENCED TO X-OFFSET ($1000)
00200000 PORTA EQU $00 PORT A DATA REGISTER
00210004 PORTB EQU $04 PORT B DATA REGISTER
00220002 PIOC EQU $02 PARALLEL 1/0 CONTROL
00230026 PACTL EQU $26 PULSE ACC CNTRL REG (PORT A)
00240008 PORTO EQU $08 PORT D DATA REGISTER
00250028 SPCR EQU $28 SPI CONTROL REGISTER
0026002a SPDR EQU $2A SPI DATA REGISTER
00270029 SPSR EQU $29 SPI STATUS REGISTER
00280009 DDRD EQU $09 PORT D DATA DIRECTION REGISTER
00290022 TMSKI EQU $22 REGISTER FOR INPUT CAPTURE ENABLE
00300023 TFLGl EQU $23 REGISTER FOR INPUT CAPTURE STATUS
0031 0021 TCTL2 EQU $21 REGISTER FOR INPUT CAPTURE CONTROL
0032 • REFERENCED TO Y-OFFSET (STARTS AT $B700)
00330000 DATA EQU $00 DATA SPACE (REL DATA POINTER)
00340001 NEXTO EQU $01 NEXT DATA BYTE POINTER
0035 • REFERENCED TO 0000
00360000 YSTOR EQU $0000 RAM LOC FOR CONTROL DATA
003700e2 IC3JMP EQU $E2 THE LOCATION FOR IC3 JUMP INST
003800e3 IC3JMPl EQU $E3 LOC. TO PLACE THE JMP ADX
0039
0040
0041 ••••••••••••••••••••••••••• MAIN PROGRAM •••••••••••••••••••••••••••
0042 b600 ORG $B600
0043 b600 ce 10 00 LDX #$1000 • BASE FOR CONTROL REGISTERS
0044
0045 • PORT A SET-UP (FOR HIGH ORDER 7 SEG DISPLAY OUTPUT)
0046 b603 a6 26 LDAA PACTL,X • SET PORTA, BIT 7 TO
0047 b605 8a 80 ORAA #$80 • AN OUTPUT PORT
0048 b607 a7 26 STAA PACTL,X
0049
0050 • PORT B SET-UP (FOR 2 LOW ORDER 7 SEG DISPLAY OUTPUTS)
0051 b609 ld 02 ff BCLR PIOC,X $FF • SIMPLE HANDSHAKE MODE
0052
0053 • TEST OUTPUTS
0054 b60c 86 af LDAA #$AF • PUT AN 'A' IN THE HIGH
0055 b60e a7 00 STAA PORTA,X • HEX DIGIT
0056 b61 086 bc LDAA #$BC • AND A 'BC' IN THE LOW

367
 APPENDIX 2 - Program Listing (continued)

0057 b612a7 04 STAA PORTB,X • FOR LED DISPLAYS

0058
0059 b614 18 ce b7 00 LDY #$B700 • SET MEMORY POINTER
0060 b618 18 df 00 STY YSTOR
0061
0062 • INITIALIZE USER STACK POINTER
0063 b61b 8e 00 If LDS #$FF • STACK STARTS AT $FF WHICH
0064
0065 • INTERRUPT PREPARATIONS
0066 b61e 86 7e LDA #$7E • OPCODE FOR JMP INST
0067 b620 97 e2 STAA IC3JMP • LOADED INTO RAM
0068 b622 ce b6 40 LDD #$B640 • SET THE JUMP LOCATION FOR
0069 b625 dd e3 STD IC3JMPI • THE INT SERVICE ROUTINE
0070 b627 86 01 LDAA #$01 • INPUT CAPTURE (IC3) SET FOR
0071 b629 a7 21 STAA TCTL2,X • RISING EDGE
0072 b62b 1e 22 01 BSET TMSKI ,X $01 • ENABLE THE IC3
0073 b62e Oe CLI • ENABLE ALL NON-MASKED
INTERRUPTS
0074
0075 • MAIN PROGRAM DO NOTHING LOOP
0076 b621 MONITOR EOU
0077 b621 01 NOP SIT HERE AND DO NOTHING UNTIL
0078 b630 el STOP • SAVE POWER IN STANDBY MODE
0079 b631 20 Ie BRA MONITOR • INTERRUPT
0080
0081
0082
0083 ........................... INTERRUPT SERVICE ROUTINE ...........................
0084 b640 ORG $B640
0085
0086 b640 START EOU
0087 b640 86 64 LDAA #100
0088 b642 18 ee 03 e8 OUTERD LDY #1000 • DELAY FOR SOFTWARE
0089 b646 18 09 DELAY DEY • DEBOUNCING OF
0090 b648 26 Ie BNE DELAY • INTERRUPT CIRCUIT
0091 b64a 4a DECA
0092 b64b 26 15 BNE OUTERD
0093
0094 b64d 18 de 00 LDY YSTOR • LOAD POINTER
0095 b650 Ie 0810 BSET PORTD,X $10 • SET D BIT 4 HIGH (IDLE)
0096
0097 • THE REMAINING LOOP IS EXECUTED AS MANY TIMES AS THERE ARE
0098 • BYTES TO BE OUTPUTTED. IT STARTS AT B700 (OR WHEREVER IT LEFT
0099 • OFF ON PREVIOUS INTERRUPT HANDLED) AND OUTPUTS UNTIL A NULL
0100 • BYTE (00) IS FOUND (00 IS NOT OUTPUTTED). THE NEXT TWO BYTES
0101 • ARE DISPLAYED AND THE POINTER UPDATED.
0102
0103 b653 LOOP EOU
0104 b65318 e6 00 LDAB DATA,Y • LOAD THE PRESENT BYTE
0105 b6561d 28 40 BCLR SPCR,X$40 • DISABLE SPI
0106 b6591e 08 08 BSET PORTD,X$08 • SET D BIT 3 HIGH (IDLE)
0107 b65e 8638 LDAA #$38 • SS=I, SCK=MOSI=1
0108 b65e a7 09 STAA DDRD,X
0109 b660 el c2 CMPB #$C2 • CHECK DATA TO SEE IF A
0110 b662 26 03 BNE NOSTART • START CONDITION IS REO
0111 • (IF FIRST DATA BYTE)
0112

368
 APPENDIX 2 - Program Listing (continued)

0113 • This se~ment transfers a byte from the HCll's SPI

0114 • to the I C peripheral. Upon Entry, data is in Acc B,
0115 • w_start is the entry point for sending a start bit.
0116 • nostart is the entry point for transferring data
0117 • without a start condition,
0118
0119 b664 W_START EQU
0120 b664 ld 08 08 BCLR PORTD,X$08 • START CONDITION
0121 b667 NOSTART EQU
0122 b667 86 73 LDAA #$73 • ENABLE SPI (SPE=l); MASTER
0123 b669 a7 28 STAA SPCR,X • CPOL=CPHA=O; BITRATE=CLKl32
0124 b66b lc 08 08 BSET PORTD,X$08 • RETURN PD3 TO IDLE STATE
0125 b66e e7 2a STAB SPDR,X • WRITE DATA
0126 b670 a6 29 WAIT LDAA SPSR,X • WAIT FOR END OF XMISSION
0127 b672 2a fc BPL WAIT • IF NOT, WAIT
0128
0129 b674 ld 08 10 BCLR PORTD,X$10 • LEAVE SCLK (PD4) LOW
0130 b677 a6 28 LDAA SPCR,X • CREATE ACK PULSE
0131 b679 84 bf ANDA #$BF • CLEAR SPE, DISABLE SPI
0132 b67b a7 28 STAA SPCR,X • CAUSES PD4 (SDA) TO GO HIGH
0133
0134 b67d 18 6d 01 TST NEXTD,Y • TEST NEXT BYTE, IF<> 0
0135 b680 26 3a BNE HI_ACK • SLAVE GENRTS ACK (LOW)
0136
0137 b6821d 08 08 LO_ACK BCLR PORTD,X$08 • ELSE, CLEAR ACK BIT
0138 b6851c 0810 BSET PORTD,X $10 • GEN ACK CLOCK
0139 b688 21 f8 BRN LO_ACK • INSURE PULSE WIDTH
0140 b68a ld 08 10 BCLR PORTD,X$10 • CLOCK LOW
0141 b68d lc0810 BSET PORTD,X $10 • GEN STOP
0142 b690 lc 08 08 BSET PORTD,X$08 • CONDITION
0143
0144 b69318 08 INY
0145 b69518 08 INY • PNT TO FREQ VALU
0146 b697 ld 02 II BCLR PIOC,X $11 • SIMPLE HANDSHAKE MODE
0147 b69a 18 a6 00 LDAA DATA,Y • LOAD MSB OF FREQ VAL
0148 b69d a7 00 STAA PORTA,X • AND OUTPUT IT
0149 b69f 18 08 INY • MOVE POINTER
0150 b6al 18 a6 00 LDAA DATA,Y • LOAD 2LS DIGITS
0151 b6a4 a7 04 STAA PORTB,X • AND OUTPUT THOSE
0152
0153 b6a618 08 INY • POINT TO NEXT GROUP
0154 b6a818 df 00 STY YSTOR • SAVE NEW POINTER
0155 b6ab 18 6d 00 TST DATA,Y • CHECK FOR LAST GROUP
0156 b6ae 2607 BNE MODATA • IF NOT, KEEP YSTOR
0157 b6bO 18 ce b7 00 SETPTR LDY #$B700 • ELSE RESET POINTER
0158 b6b418 df 00 STY YSTOR • TO TOP OF DATA
0159
0160 b6b7 86 01 MODATA LDAA #$01
0161 b6b9 a7 23 STAA TFLG1,X • CLEAR INTERRUPT
0162 b6bb 3b RTI • STOP SERVICE OF OUTPUT
0163
0164
0165
0166 b6bc lc 0810 HI_ACK BSET PORTD,X $10 • GENERATE ACK CLOCK
0167 b6bf a6 08 LDAA PORTD,X • CHECK FOR SLAVE ACK
0168 b6cl 8404 ANDA #$04 • BEING A LOW BIT 3
0169 b6c3 26 09 BNE ERROR • IF NOT, BRANCH TO ERROR
0170 b6c5 21 f5 BRN HI_ACK • ENl:?URE CLK PULSE WIDTH

369
 APPENDIX 2 - Program Listing (continued)

0171 b6c7 1d 08 10 BClR PORTD,X $10 • BClR 4, PORTO

0172 b6ca 1808 INY • POINT TO NEXT DATA BYTE
0173 b6cc 20 85 BRA LOOP
0174
0175 b6ce 86 ee ERROR lDAA #$EE • PRINT OUT AN 'EEE'
0176 b6dO a7 00 STAA PORTA,X • TO INDICATE THAT THE
0177 b6d2 a7 04 STAA PORTB,C • SLAVE DIDN'T ACK
0178 b6d4 7e b6 bO JMP SETPTR • END XMISSION ATTEMPT
0179
0180

370
 AN1207
The MC145170 in Basic HF and VHF Oscillators
Prepared by: David Babin and Mark Clark

Phase-locked loop (PLL) frequency synthesizers are com- before being fed to other sections of the radio. The VCM output
monly found in communication gear today. The carrier oscillator can be directly used in computers and other digital equipment.
in a transmitter and local oscillator (LO) in a receiver are where The output.of a VCO or VCM is typically buffered, as shown.
PLL frequency synthesizers are utilized. In some cellular As shown in Figure 2, the MC145170 contains a reference
phones, a synthesizer can also be used to generate 90 MHz for oscillator, reference counter (R Counter), VCONCM counter (N
an offset loop. In addition, synthesizers can be used in com- Counter), and phase detector. A more detailed block diagram
puters and other digital systems to create different clocks which is shown in the data sheet.
are synchronized to a master clock.
The MC145170 is available to address some of these HF SYNTHESIZER
applications. The frequency capability of the MC145170 is very
broad - from a few hertz to 160 MHz. . The basic information required for designing a stable high-
.frequency PLL frequency synthesizer is the frequencies
ADVANTAGES required, tuning resolution, lock time, and overshoot. Forthe ex-
ample design of Figure 3, the frequencies needed are 9.20 MHz
Frequency synthesizers, such as the MC 145170, use digital
to 12.19 MHz. The resolution (usually the same as the fre-
dividers which can be placed under MCU control. Usually, all
quency steps or channel spacing) is 230 kHz. The lock time is
that is required to change frequencies is to change the divide
8 ms and a maximum overshoot of approximately 15% is tar-
ratio of the N Counter. Tuning in less than a millisecond is
geted. For purposes of this example, lock is considered to be
achievable.
when the frequency is within about 1% of the final value.
The MC145170 can generate many frequencies based on
the accuracy of a single reference source. For example, the
HF SYNTHESIZER LOW-PASS FILTER
reference can be a low-cost basic crystal oscillator or a temper-
ature-compensated crystal oscillator (TCXO). Therefore, high In this design, assume a square wave output is acceptable.
tuning accuracies can be achieved. Boosting of the reference To generate a square wave, a MC1658 VCM chip is chosen. Per
frequency by 100x or more is achievable. the transfer characteristic given in the data sheet, the MC 1658
transfer function, KVCM, is approximately 1 x 108 radians/
ELEMENTS IN THE LOOP second/volt. The loading presented by the MC1658 control in-
The components used in the PLL frequency synthesizer of put is large; the maximum input current is 350 ~A. Therefore, an
Figure 1 are the MC145170 PLL chip, low-pass filter, and volt- active low-pass filter is used so that loading does not affect the
age-controlled oscillator (VCO). Sometimes a voltage- filter's response. See Figure 3. In the filter, a 2N7002 FET is
controlled multivibrator (VCM) is used in place of the VCO. The chosen because it has very high transconductance (80 mmhos)
output of a VCM is a square wave and is usually integrated and low input leakage (100 nA).

DIVIDE VALUE

REFERENCE REFERENCE
OSCILLATOR OSCILLATOR
TO
LOW·PASS
FILTER
FROM
VCONCM

MULTIPLYING VALUE

Figure 1. PLL Frequency Synthesizer Figure 2. Detail of the MC145170

371
 +5V +5V +5V

1.5 kil
PLL
R2 BIAS
FREQUENCY
LOW-PASS 2.4kn
SYNTHESIZER VCM
FILTER
16 16
0.01 J.!F 47 pF
0.01 J.!F
PDout

.:.~
MC145170 MCI656

-= 0.01
J.!F

lMn lMn
-=
0.01 J.!F 0.01 J.!F
OUTPUT

510n PULLDOWN
LOW-PASS FILTER BUFFER/FILTER
-=
Figure 3. HF Synthesizer

In order to calculate the average divide value for the N I.B

~;0.1
Counter, follow this procedure. First, determine the average
1.7
/0.2
frequency; this is (12.19 + 9.2)/2 = 10.695 MHz or approxi-
1.6
/ 1\
mately 10.7 MHz. Next, divide this frequency by the resolution: /0.3
10.7 MHzl230 kHz = about 47. 1.5 Ir r\ 0.4
Next, reference application note AN535 (see book ,/"' K: 0.5
1.4
OL 130/0 Rev 1). The active filter chosen takes the form shown >-
u 1.3
r< r0 0.6 /"\
in Figure 9 of the application note. This filter is used with the z 0.7
single-ended phase detector output of the MC145170, POout.
W
::l 1.2
~~ /
The phase detector associated with POout has a gain
0
w
a: 1.1
r-£ / r----\
~ '/-: t--- ~
LL
K(J) = VOO/4". For a supply of 5 V, this is 5/4" = 0.398 V/rad. I-
::l 1.0
1 l
The system's step response is shown in Figure 4. To achieve
about 15% overshoot, a damping factor of 0.8 is used. This
I-
Q.

::l 0.9 -f o.B'1 \'--... VI

causes frequency to settle to within 1% at ront = 5.5.
The information up to this point is as follows.
0
cw
N
:::J
O.B
1.0
2.0 "'\\- V-//'1/ \ II
0.7 I----'
fref = 230 kHz "'a:0"
:;;
\
fVCM = 9.2 to 12.19 MHz; the average is 10.7 MHz, z 0.6
average N = 47
power supply = 5 V for the phase detector
Bo 0.5 \ /
KVCM = 1 x 108 rad/sN
'" 0.4
overshoot = approximately 15%, yields a damping 0.3
factor = 0.8
lock time t = 8 ms settling to within 1%, ront = 5.5 0.2
Ko or Kp = 0.398 V/rad. 0.1
From the application note, equation 61, ron = 5.5/t =
5.5/0.008 = 687.5 rad/s. o 1.0 2.0 3.04.0 5.0 6.0 7.0 B.O 9.0 10 11 12 13 14
"'nt
Equation 59 is Rl C= (Kp Kv)/ron 2 N
= (0.398 x 1 x 108 )/687.52 x 47 Figure 4. Type 2 Second Order Step Response
= 1.79
Equation 59 is used because of the high-gain FET.
Next, the capacitor C is picked to be 1 J.!F. Therefore,
R 1 = 1.79/C which is 1.79 Mil. The standard value of 1.8 Mil HF SYNTHESIZER PROGRAMMING
is used for Rl.
Programming the MC145170 is straightforward. The three
Equation 63 is R2 = (2~)/C ron
registers may be programmed in a byte-oriented fashion. The
= (2 x 0.8)/(1 x 10-6 x 687.5) registers retain their values as long as power is applied. Thus,
=2.33 kil. usually both the C and R Registers are programmed just once,
A standard value for R2 of 2.4 kil is utilized. right after power up.

372
 The C Register, which configures the device, is pro- VHF SYNTHESIZER
grammed with $CO (1 byte). This sets the phase detector to
The MC145170 may be used in VHF designs, also. The
the proper polarity and activates PDout. This also turns off the
range for this next example is 140 to 160 MHz in 100 kHz
unused outputs. The phase detector polarity is determined by
increments.
the filter and the VCM. For this example, the MC1658 data
sheet shows that a higher voltage level is needed if speed is VHF SYNTHESIZER LOW-PASS FILTER
to be increased. However, the low-pass filter inverts the signal
To illustrate design with the doubled-ended phase detector,
from the phase detector (due to the active element configura-
the <l>R and <l>v outputs are used. This requires an operational
tion). Therefore, the programming of the polarity for the phase
amplifier, as shown in Figure 5. From the design guidelines
detector means that the POL bit must be a "1."
shown in the MC145170 data sheet, the following equations
The R Register is programmed for a divide value that
are used:
results in the proper frequency althe phase detector reference
input. In this case, 230 kHz is needed. Therefore, with the
Ol =JKlpKVCO (1)
4.6 MHz source shown in Figure 3, the R Register needs a n NC Rl
value of $000014 (3 bytes, 20 in decimal).
The N Register determines the frequency tuned. Tuning damping factor (2)
9.2 MHz requires the proper value for N to multiply up the
reference of 230 kHz to 9.2 MHz. This is 40 decimal. For where, from the data sheet, the equation for the <IlR and <Ilv
12.19 MHz, the value is 53 decimal. To tune over the range, phase detector,
change the value in the N Register within the range of 40 to 53
with a 2-byte transfer. Table 1 shows the possible frequencies. K<Il = 'VDD
"2n"' = 5
21t = 0.796 V/rad (3)

1; = 0.707,

Table 1. The HF Oscillator Frequencies Oln = 21tfR = 21t x 100 kHz = 12566 rad/s (4)
50 50 '
NValue Frequency, MHz and
40 9.20 K _ 21td fVCO 21t x (160 -140 MHz)
41 9.43 VCO- d VVCO 10-2
42 9.66
43 9.89 = 1.57 x 107 rad/sN (5)
44 10.12 The control voltage range on the input to the VCO is picked to
45 10.35
be 2 to 10 V.
46 10.58
The average frequency = (140 + 160)/2 = 150 MHz. There-
47 10.81
fore, the average N = 1500.
48 11.04
The above choices for 1; and Oln are rules of thumb that are
49 11.27
a good design starting point. A larger Oln value results in faster
50 11.50
51 11.73
loop lock times and higher reference frequency VCO
52 11.96 sidebands for similar sideband filtering. (See Advanced
53 12.19 Considerations.)
Choosing Cl to be 4700 pF, Rl is calculated from the
rearranged expression for Oln as:
EXTRA FILTERING FOR THE HF LOOP Rl= KcpKVCO = (0.796 V/rad)(1.57 x 107 rad/sN)
Clo?nN (4700 pF)(12,566 rad/s)2 (1500)
When the HF oscillator was built, the proper frequencies
could not be tuned. The output of the MC1658 was examined = 11.23 kg (6)
with an oscilloscope and the switching edges were discovered Therefore, chose ari 11 kg standard value resistor.
to be "ragged." That is, the output did not appear to be a square R2 is determined from:
wave with clean transitions.
The fin input of the MC145170 is sensitive to 500 mV pop R2 = ~ = (2)(0.707)
signals, and the ragged edges were being amplified and OlnCl (12,566)(4700 pF)
counted down by the N Counter. Therefore, the edges needed
= 23.94 kg or (7)
cleaning up. One method would have been to add a low-pass
2.4 kg (standard value)
filter between the MC1658 and MC145170. However, be-
cause an additional buffer was needed elsewhere in the cir-
VHF SYNTHESIZER EXTRA FILTERING
cuit, an MC74HCU04 inverter was used in place of the filter.
This inverter's frequency response is low enough to clean up For more demanding applications, extra filtering is some-
the ragged edges. That is, filtering of the ragged edges times added. This reduces the VCO sidebands caused by a
occurred, and the output had smoother transitions. As men- small amount of the reference frequency feeding through the
tioned previously, one of the elements in the inverter package filter. One form of this filtering consists of spitting Rl into two
was used to buffer the output of the VCM before feeding it to resistors; each resistor is one-half the value of Rl, as indi-
the outside world. See Figure 3. cated by Rl/2 in Figure 5. Capacitors Cc are added from the

373
 2.4 k!l 4700 pF
4x5.6kQ
2x 1500pF
+5V
1 MHz Rl/2 Rl/2
+ 12V
VI
ICc
Rl/2 -= R1/2

MC145170
* Cc

I
2.4kQ

4700pF
-=

lk!l
TEST POINT
(LOCK DETECT]
' - - - - - - - - 0 DATA OUT
~-----------OC~

~--------o EN .
'----------<> DATA IN
+5V +5V
20 nH 2 x MV2115
R14
10k!}

MCl648

1000pF I I ~~OPF
Figure 5. VHF Synthesizer

midpoints to ground to further filter the reference sidebands. series with the rest of the circuit) is much smaller than C5 and
The value of Cc is chosen so that the corner frequency of this can therefore be neglected for this calculation.
added network does not significantly affect the original loop As above, let WRC = 257,600 rad/s be the cutoff of this filter.
bandwidth wB. Rl was previously chosen to be 10 kn. Therefore,
The rule of thumb for an initial value is Cc = 4/( Rl WRC),
where wRC is the filter cutoff frequency. A good value is to C5 = _ _1_= _ _ _1_ __ (11)
choose wRC to be lOx WB, so as to not significantly impact the wRCR14 (257,600)(10 kn)
original filter.
= 388 pF ~ 390 pF
(8)

= 12,566)1+(2)(0.707)2+ h+(4)(0.707)2+ (4)(0.707)4 THE VARACTOR

= 25,760 rad/s The MV2115 was selected for its tuning ratio of 2.6 to 1. The
capacitance can be changed from 49.1 pF to 127.7 pF over a
reverse bias swing of 2 to 30 volts. Contact your Motorola rep-
WRC = 10 wB = (10)(25,760) = 257,600 rad/s (9) resentative for information regarding the MV2115 varactor
diode.
For example, three parameters are considered.
CC=_4_= 4 (10) CT = Nominal capacitance
RlwRC (11.23 kn)(257,600 rad/s)
CR = Capacitance ratio
= 1383 pF ~ 1500 pF fR = Frequency ratio

There is also a filter formed at the input to the VCO. Again, CR= Cvmin = (Vmllx)P
this should be selected to ensure that it does not significantly (12)
Cvmax· Vmin
affect the loop bandwidth. For this example, the filter is domi-
nated by R14 with C5. The capacitance of the varactors (in where P = the capacitance exponent

374
Therefore,
f max 1 = 173 MHz (22)
GR =2.6(~)P (13)
21t[(19.9 nH)(42.2 pF)]0.5
The frequency ratio is 1.5 to 1 and is impacted by the tuning
range of the MV2115 varactor diode used in the tank circuit.
log(2.6) = plog(15) (14) Therefore, the required range of 140 to 160 MHz is not limited
by this VCO design.
P = log(2.6)/log(15) = 0.3528 (15) A pc board should be used to obtain favorable results with
this VHF circuit. The lead lengths in the tank Circuit should be
Using the nominal capacitance of 100 pF at 4 volts: kept short to minimize parasitic inductance. The length of the
trace from the VGO output to the PLL input should be kept as
100 pF = (~\0.3528 short as possible. In addition, use of surface-mount compo-
(16) nents is recommended to help minimize strays.
Gvmax 4 V)
VHF SYNTHESIZER PROGRAMMING
100 pF = 1.382 Again, programming the three registers of the MG145170
Gvmax is straightforward. Also, usually both the C and the R Registers
are programmed only once, after power up.
Solving for Gvmax:
The C Register configures the device and is programmed
with $00 (1 byte). This sets the phase detector to the correct
100 pF = 72.4 pF polarity and activates the <l>R and <l>V outputs while turning off
1.382 the other outputs. Like the HF oscillator, the phase detector
polarity is determined by how the filter is hooked up and the
Solving for Gvmin:
VCO.
2.6= Gvmin The R Register is programmed for a divide value that
(17)
49.1 pF delivers the proper frequency at the phase detector reference
input. In this case, 100 kHz is needed. Therefore, with the
Gvmin = (2.6)(49.1 pF) 1 MHz crystal shown, the R Register needs a value of
$OOOOOA (3 bytes, 10 in decimal).
Gvmin = 127.7 pF The N Register determines the frequency tuned. To tune
140 MHz, the value required for N to multiply up the reference
of 100 kHz to 140 MHz is 1400 decimal. For 160 MHz, the
THEVCO
value is 1600 decimal. To tune over the range, simply change
For convenience, the MG1648 VGO is selected. The tuning the value in the N Register with a 2-byte transfer.
range of the VGO may be calculated as
ADVANCED CONSIDERATIONS
fmax = (Gdmax + Gs )0.5
(18) The circuit of Figure 5 may not function at very-high tem-
fmin (Gdmin + Cs )0.5
perature. The reason is that the MG145170 is guaranteed to
a maximum frequency of 160 MHz at 85°G. Therefore, there
where
is no margin for overshoot (reference Figure 4) at high temper-
ature. There are two possible solutions: (1) maintain the ambi-
fmin= 1 (19)
21t[L(Cdmax + Cs )]0.5 enttemperature at less than 60 o e, or (2) limit the tuning to less
than 160 MHz.
As shown in Figure 8 of the data sheet, the VCO tank circuit Operational amplifiers are usually too noisy for critical ap-
is comprised of two varactors and an inductor. Typically, a plications. Therefore, if an active element is required in the in-
single varactor might be used in either a series or parallel tegrator, one or more discrete transistors are utilized. These
configuration. However, the second varactor has a two-fold may be FETs or bipolar devices. However, active filter ele-
purpose. First, if the 10 kQ isolating impedance is left in place, ments are not needed if the veo loading is not severe, such
the varactors add in series for a smaller capacitance. Second, as is encountered with most discrete veo designs. Because
the added varactor acts to eliminate distortion due to the tank active elements add noise, some performance parameters
voltage changing. are improved ifthey are not used. On the other hand, an active
Therefore, with the two varactors in series, Gdmax' = filter can be used to scale up the veo control voltage. For
Gdmaxl2. The shunt capacitance (input plus external capaci- example, to tune a wide range, the control voltage may have
tance) is symbolized by Cs . to range up to 10 V. For a 5 V PLL output, this would be scaled
Therefore, solving for the inductance: by 2x via use of active elements.
Some applications have requirements that must be met in
L= 1 19.9 nH = 20 nH (20) the areas of phase noise and reference suppression. These
(27tfmin)2(Cdmax' + Cs )
parameters are in conflict with fast lock times. That is, as lock
The Q of the inductor should be more than 100 for best per- times are reduced, reference suppression becomes more dif-
formance. ficult. Both reference suppression and phase noise are ad-
vanced areas that are covered in several publications. As an
fmin 1 = 135 MHz (21) example, consider that the VCO input voltage range for the
21t[(19.9 nH)(69.85 pF)]0.5
above VHF loop was merely picked to be 8 V. Advanced

375
techniques demand a trade off between this voltage range and prototype on a spectrum analyzer. Note that the reference
the spectral purity of the VCO output. This is because the sidebands appear at 100 kHz as expected, and are 50 dB
lower the control voltage range, the more sensitive the VCO down.
is to noise coming into its control input.
A VCO IC may not offer enough performance for some REFERENCES
applications. Therefore, the VCO may have to be designed CMOS Application-Specific Standard ICs, book OL130/0,
from discrete components. Motorola, 1990, MC145170 data sheet and AN535 application
Figure 6 shows the performance of the VHF Oscillator note.

I
1\
I \
J \
(\ / \ 1\
H .NJ!N' ~ ),\
I I
100 kHz CENTER =150 MHz, SPAN =250 kHz 100 kHz

Figure 6. VHF Oscillator Performance

376
 AN1306
Thermal Distortion In Video Amplifiers
Prepared by: Curtis Gong
Motorola RF Products Division
Torrance, CA

ABSTRACT signal, and can be explained using Figure 2. Notice after the
transition from black to white (from high voltage to low voltage),
Thermal distortion is a problem in many high resolution the video signal is below the specified white level. This signal
video amplifiers. Thermal distortion occurs when there are shows up on the display as a section "brighter" than white. The
instantaneous power changes in the transistor stages. If the signal does eventually settle to the white level; but until it does,
the display will appear brighter than it should be.
problem goes uncompensated, it leads to a visual el(ect
known as smearing. This Application Note will discuss what
WHAT CAUSES THERMAL DISTORTION?
smearing is, what causes thermal distortion, how to measure
it and how to compensate the problem.
The transistors of a video amplifier are often subject to large
instantaneous power changes because of the large voltage
WHAT IS SMEARING? swings, particularly on transitions from black to white. These
power changes cause changes in the transistor's junction tem-
Smearing is best explained by using an example. Smear- perature. Due to the transistor's thermal time constant, which
ing, or ghosting, is most noticeable when a black block is is the amount of time it takes something to heat up or cool
displayed on an all white background. Referring to Figure 1, down, the transistor can't change temperature fast enough. It
both Sections a. and b. should be the same brightness. When is this thermal time constant and the fact that VSE of a transis-
there is a smearing problem, Section b. will be brighter than tor changes with temperature, - 2 mV/oC, that causes thermal
Section a. This problem is related to the droop of the video distortion.

a.

BLACK
- - - " T - - - - - - - - - - - - - - - LEVEL

a.
_______ ______ ~-=--------
WHITE
LEVEL

Figure 1. Figure 2.

377
 Figure 3 shows a simple example that can be used to ex- temperature TE a change of ±1.6°C.) Notice on the plot of
plain the thermal distortion concept. In the ideal case. where TJ. that the junction temperature does not change instanta-
VBE does not change with temperature. there is a power neously. This is a result of the thermal time constant. Using
swing of 107 mW across the transistor. Using the 107 mW - 2 mV/oC. we can calculate VBE; from there we can
and a thermal resistance of 30°CIW. we can see how this calculate VE. IE. and YO. This example clearly shows the
power swing affects the output in the real case. (A change distortion of the square wave.
in power of 107 mW would create about the normal junction

Ideal Case
VIN (VOLTS)

40

+60 V

1K

VO(VOLTS) P(mW)
Vo 30 891

784
VSE 20

10
VE (VOLTS)

.4

.3

Real Case
TJ (OC) VSE(VOLTS)

1.1 .7032

VE (VOLTS) IE (mA) VO(VOLTS)

30.32
29.68
.4032 40.32
.3968

20.32
.3032 19.68
.2968'--_ _ _ _ _ _ __

Figure 3.

378
 MEASURING THE DISTORTION less than 100 mV is generally acceptable. Flatness of
50 mV - 100 mV for a 40 V swing is very difficult to measure.
Making an accurate measurement of the distortion can The effect of thermal distortion can be compensated. The
be difficult. The oscilloscope must have enough vertical offset Motorola CR2424 is used as an example to show some of
to enable the edge to be viewed with a reasonable scale. the compensation techniques that can be utilized. The output
Often, flatness measurements in the 100 mV to 200 mV waveform, when there is a distortion problem, appears as
range must be measured on a 1 VolVdiv scale. In this case, a signal with excessive mid and high frequency gain. The
the accuracy is not good. Another issue that must be consid- signal would be flat if this excessive gain were eliminated.
ered is scope performance at maximum offsets. When a One way of doing this is to use a series RC network as feed-
scope is operating at a maximum offset, it may introduce back from the output to the input. The CR2424 has an internal
some of its own distortion. Check with the manufacturer. compensation network which noticeably improves the flat-
ness. Unfortunately, this is only a first order compensation
network and doesn't eliminate all problems. The flatness can
HOW TO COMPENSATE THE PROBLEM be further improved by adding an external compensation net-
work consisting of a 150 pF capacitor and a 200 kQ resistor.
There is no real standard on how small the distortion must Figure 4 shows the flatness of the CR2424 without the inter-
be. Several years ago a 1% flatness was acceptable nal compensation network while Figure 5 shows the flatness
(400 mV for a 40 V swing). On today's high resolution dis- with the internal network. Note the considerable improvement
plays, this is clearly unacceptable. A flatness of 200 mV for in the flatness of the output waveform when the complete
a 40 V swing will cause noticeable smearing problems. Some CR2424, including its internal compensation network, is
designers believe a 50 mV flatness is required, but anything used.

Figure 4. CR2424 Without Compensation Figure 5. CR2424 With Internal Compensation

379
 Figure 6 shows the effect of an external compensation is not flat. This can be seen in Figures 5 and 6. On the display,
network. The improvement may seem small, but it can be this problem shows up as a gray area right after the transition
seen on the CRT. Additional external compensation networks from black to white. This is a frequency response issue and
may be added to further improve the flatness. In oscillo- can be corrected by adding an additional input peaking net-
scopes, where flatness is very important, as many as ten work. Figure 7 shows the circuit and a photo of the actual
networks are used. waveform.
There is another flatness issue. The first 0.511s of the pulse

'e DC v 008 V
-
I A2 11_
I~ -~~- -~ -I -

1-- - - - + - - - ---
1 1

--I - - - -
~' 1- -,- --,- I
--,
I

--: .:-:.-=- --= :-:..-=- -~-=-'--; :-;.-~--

- - I r -I ~ -I- - - --

- -- I
---
I
--- --- - - I
+ -I---L
1

1- I _ I
V 1u<:::.
----J -- - 1 1
I
~ - 1_
1V I 1 Ll~
1

150pF 200K
150 pF 200K

14 pF 20K

50 215

Figure 6. CR2424 With External Compensation Figure 7. CR2424 With Modified Input Network

380
 When using the external compensation network tech- may want to adjust the compensation network (by changing
niques as previously described, there are several precautions the capacitor) to optimize the flatness at a different contrast
that must be taken. The first precaution is that thermal level (voltage swing) on the display.
distortion is dependent on signal swing. The distortion Another area of precaution is the 215 Q input peaking
improves with smaller signal swings because the power resistor. Since the CR2424 is a feedback amplifier, the gain
changes are less. The 200 kQ and 150 pF RC compensation is determined by the input peaking resistor and the feedback
network was optimized for a 40 V signal swing. For smaller network. The previously mentioned compensation networks
signal swings, the compensation network tends to overcom- were optimized for a 215 Q input resistor. If the resistor was
pensate causing the flatness to slope in the opposite changed, the CR2424 would have a different gain and the
direction, i.e., the smearing would appear darker than white compensation networks would no longer be optimized.
instead of brighter than white. In this case, the CRT designer

381
382
 AN1401

I
Using SPICE to Analyze the
Effects of Board Layout on
System Skew When Designing
With the MC10/100H640
Family of Clock Drivers

Prepared by
Debbie Beckwith
Eel Applications Engineering

This application note illustrates the complexities of

board layout influences on the total skew of a system
when designing with the MC10Hl100H64x family of
clock drivers. Transmission line theory and the various
termination techniques are discussed. The note also
presents guidelines to assist designers in analyzing
their board layouts and loading schemes using SPICE
simulations to predict and minimize the total skew of a
system.

383
 Using SPICE to Analyze the Effects of Board Layout
on System Skew When Designing With the H640
Family of Clock Drivers
Objective will concentrate on illustrating the relationship of capacitive
The objective of this note is to illustrate the complexities loading versus propagation delay and the relationships
of board layout influences on the total skew of a system when dependence on board layout and termination technique.
designing with the H64x series of clock distribution chips. Capacitive loading refers to both "device output loading" and
The note will present some guidelines to assist designers '1ransmission line loading." When the interconnect line is
in using SPICE to analyze their board layouts and loading short (less than 4.5") the capacitive loading is seen by the
schemes to predict and minimize the total skew of a system. output of the driving device and the propagation delay can
The MC10H/100H64x series of devices are ECL/TIl be predicted by assuming a lumped load at the output of
translating clock drivers designed for systems requiring very the device. This is referred to as "device output loading."
low skew clock distribution. Skew is most often specified in However, when the line length exceeds 4.5", the capacitive
terms of "Output to Output" skew and "Part to Part" skew. loading is seen by the transmission line as opposed to the
"Output to Output" skew refers to the maximum variation in output device. This will be referred to as '1ransmission line
propagation delay between similar paths of a single device. loading." For the case of "transmission line loading,"
"Part to Part" skew refers to the maximum propagation delay propagation delay predictions must be based on the T pd
difference between similar paths on different devices being versus Cl relationship derived for a desired line length and
driven by the same inputs. The H64x series' skew termination technique. The propagation delay versus Cl
specifications are specified based on equal capacitive characteristics of an IC and a transmission line are different,
loading of all outputs. Since skew is a measurement of therefore it is not enough to simply ensure equal Cl'S on
propagation delay, and propagation delay is dependent on all clock paths to minimize skew.
capacitive loading, optimum skew performance can only be The results of this note are applicable to the entire H64x
achieved when all outputs are loaded equally. series of ECL/TIl translating devices, although only the
In many designs the clock will need to be routed to a output section of the H641 is modeled as the driving section
number of receiving gates at different locations in the system. of the analysis circuit. The ESD protection circuitry and
For the system deSigner, skew measured at these "package" model circuitry were inCluded on the output of the
destinations is a foremost concern. Skew between receiving driving device and the input of the receiving device to more
gates is a measurement of the maximum variation in accurately model real in-line circuits. The "package" model
propagation delay between the driving gate and each circuitry simulates the effects of the device packaging. In all
receiving gate. This implies that the designer must not only cases, the input clock to the analysis circuit is a 25 MHz
be concerned with "Output to Output" and "Part to Part" skew, ECl level input (+ 3. 15 V to +4.15 V) with 1 ns rise and fall
but also with the propagation delay along each path of the times. Propagation delay is measured from the 50% level
signal. Propagation delay is a function of supply voltage, of the input clock to the 1.5 V level of the TIL output at the
ambient temperature, and capacitive loading (CU. Since receiving gate.
propagation delay is dependent on supply voltage, which can
vary significantly from board to board, skew between ICs Transmission Line Concepts 1,2,3
on a single board will be much tighter than skew between For high speed systems, the interactions between wiring
ICs on different boards. This illustrates the advantage of and circuitry are most easily determined by treating the
placing ICs with tight skew requirements on the same power interconnections as transmission lines. A brief and simplified
plane. Assuming that a common power plane is used and review of transmission line theory and termination techniques
that the temperature gradient over the board is minimal, the will be presented before discussing the effects of termination
supply voltage and ambient temperature will affect the techniques on propagation delay. For a more detailed
propagation delay of all outputs in relatively the same ·discussion of Transmission Line Theory, refer to The
manner, and thus should have minimal effect on skew. Motorola MEClTM System Design Handbook.1
Propagation delay due to capacitive loading, however, may
vary from output to output; significantly affecting skew. This Characteristic Impedance: The conductors (interconnect
variation is due to the dependence of capacitive loading on trace and the AC ground plane) that interconnect a pair of
board layout, termination technique, and fanout. Circuits have distributed series inductance and distributed
To realize minimal skew at the receiving gates, the capacitance between them, and thus constitute a transmis-
deSigners goal is to design for equal propagation delays on sion line. When these distributed parameters are constant
all paths carrying the clock signal. The remainder of this note over a length of line, the line is said to have a characteristic

384
impedance, ZOo Zo is the ratio of transient voltage to of the receiving gate is large relative to the line characteristic
transient current passing by a point on the line when a signal impedance, therefore: PL is approximately equal to 1. A large
change occurs. The relationship between the distributed positive reflection occurs resulting in overshoot. The
parameters, characteristic impedance, and transient voltage reflected signal reaches point A at time 2TO, and a large
and current is expressed as: negative reflection results because the output impedance of
the driver gate is much less than the characteristic
VII =ZO =j (LO/CO) Eq2.1 impedance of the line. In this case the reflection coefficient
is negative. The signal is re-reflected back toward the load
= =
where Lo inductance per unit length and Co capacitance arriving at 3TO, resulting in undershoot at point B. The
per unit length. ZO is expressed in Ohms, Lo in Henries, impetus in restricting interconnect lengths is to minimize the
and Co in Farads. effects of overshoot and undershoot. A handy rule of thumb
is: to limit the undershoot to 15% of the voltage swing, the
Propagation Velocity: Propagation velocity can also be two way line delay should be less than the rise time of the
expressed in terms of Co and Lo: pulse. Thus the maximum length can be determined using
the following equation:
v = 11 j (Lo/CO) Eq2.2
Lmax < tRI (2*Tpd) Eq 2.4
Termination and Reflection: When a signal travels down where: =
L Line Length, tR Rise Time=
a transmission line, if the terminating resistance (RT) Tpd '" Propagation delay I unit length
matches the line impedance, the ratio of voltage to current
traveling along the line is matched by the ratio of voltage
Zo=500HMS TO=1.8ns
to current which must prevail at AT. From the viewpoint of
the driving device, no adjustment of output current is
required. If the line is not terminated in its characteristic
Vi-D-~VO
impedance the signal propagating down the line is partially
UNTERMINATEO TRANSMISSION UNE
reflected back to the source. The magnitude of the reflected
voltage signal is governed by the load reflection coefficient, Figure 2.1a. Block Diagram of Unterminated Line
PL:

Eq 2.3 Maximum open line lengths for the ECL/TTL translator

PL = (RT - ZO)/(RS - Zo)
were derived from SPICE simulations for 10 and 20 pF loads,
where: RS = Source Impedance a maximum overshoot of 40%, and a maximum undershoot
ZO = Characteristic Impedance of the line of 20%. Simulation results indicate for a 50 ohm line driving
a 10 pF load, a stub length of less than 5 inches (assuming
The reflected signal continues to be reflected between the
source and load impedances and is attenuated with each
=
T pd 0.18 ns/inch) will limit the overshoot to less than 40%,
and the undershoot to within 20% of the logic swing. When
passage over the transmission line. The output response
the load is increased to 20 pF the maximum line length is
appears as a damped oscillation asymptotically approaching
4.5 inches. The results are shown in Figures 2.1 band 2.1 C.
the steady state value. This phenomena is referred to as
To minimize undershoot the series termination or parallel AC
ringing. Ringing has an adverse affect on noise margin. To
termination technique should be used.
minimize ringing, three basic termination techniques are
available:

1. Minimizing Unterminated Line Length CLK ...... " -!" . . . CLKB

--- -- ~
n x.
- . II .
2. Series Termination ,
3. Parallel AC Termination '.. -11 •. _ _ _ _ _ _ .J

g: I I
Untermlnated Lines
Figure 2.1 a illustrates an unterminated transmission line.
1/ I I
Since the reflection coefficient at the load is of opposite
polarity to that at the source, the signal will be reflected back
'.J. 2'UNE --00 I
and forth over the transmission line with the polarity changing 5'UNE ~. ~'
·0.987V
after each reflection from the source impedance. Thus, steps 10" UNE
appear at the input to the receiving gate. When the driver ·2
gate delivers a full TTL swing, the signal propagates from o 20 40
TIME
point A arriving at point B a time TO later. At point B, the Figure 2.1 b. H64x Driving a 10 pF Load over
signal is reflected as a function of PL. The input impedance an Unterminated Line

385
 ---t-- - - - -- ,\ ,
... - - - ------
---1.-
,-
impedance of the driving device was obtained by extracting
the VOL versus IOL and the VOH versus IOH curves (refer
to Figures 2.2b and 2.2c). The output impedance of the
device is equal to the slope of the curves, which can be
I / calculated to be approximately 8 n. This value was verified
using SPICE simulations. Rser, in Figure 2.2a was varied
I Z
/ from to 0 to 50 0 in to 0 increments and the signal was
monitored at the input to the receiving gate (refer to Figure
o J 4.5" UNE: ~.98
...",
J 2.2d). Minimal undershoot and overshoot occurred when the

'b resistance of the output driving circuit was assumed to be

10 O. This value closely agrees with the B 0 value measured
4.8" UNE: -1.01 V ' - 5.0" UNE: -1.04 V in the lab. So, the value of Rser should be set to (Zo-tO)O
20 40 for a matched series termination.
nME Series termination is useful when the interconnect lengths
are long or impedance discontinuities exist on the line.
Figure 2.1c. H64x Driving a 20 pF load over
an Unterminated line Another advantage of using series termination is that the
signal travels down the line at half amplitude, minimizing
problems associated with crosstalk and EM Radiation. The
drawbacks of this technique are twofold. First, is the
Series Termination possibility of a two step signal appearing when the driven
inputs are far from the end of the transmission line. Second,
Series damping is a technique in which a termination series termination has limited use in TTL interconnect
resistance is placed between the driver and the transmission
schemes due to the voltage drop across Rser in the low state.
line with no termination resistance placed at the receiving Any voltage drop across Rser will reduce noise margin (NM)
end of the line. Series termination, illustrated in Figure 2.2a, at the receiver. This is illustrated below by calculating the
NML of a TTL driver/receiver pair, using data book values
ZO=500HMS TO= 1.8ns of IlL, VOL and VIL·

Vi~~VO
ser DB L-/ TTL: NML ~ VOL max - [VIL max + IlL (Rsed]
~ 0.8 V - [0.5 V + 0.4 mA (40 0)]
SERIES TERMINATED TRANSMISSION UNE
~ 0.284 V

Figure 2.2a. Block Diagram of Series Terminated line

However, when driving CMOS inputs, which pull very little
input current, very little NM is lost due to the series
is a special case of series damping in which the sum of the
termination resistor. Thus, series termination is a viable
termination resistor (Rser) and the output impedance of the
termination technique when driving CMOS gates.
gate (RO) is equal to the line characteristic impedance,
resulting in minimum undershoot and overshoot.

Rser+ RO ~ Zo Eq2.5
SWEEP VOLTAGE versus 10l
10
With series termination, when the output of the driver gate
0
switches, a change in voltage, delta V, occurs at the input
to the transmission line: -10
-20
l1V ~ Vin' (ZO)/(Rser + RO + ZO) Eq 2.6 ..-
§.
-30
-' -40
For a matched series termination: Rser + RO ~ ZO, thus 5;
-50
11 V ~ Vin/2. So an incident wave of half amplitude travels -60
down the transmission line. Since the transmission line is
-70
unterminated at the receiving end, the reflection coefficient
-80
of the load is approximately unity; therefore causing the
-90
voltage to double at tlW receiving end. When the reflected 0 0.5
wave arrives at the source it is completely absorbed by the SWEEP VOLTAGE (V)
series resistor since the impedance matches the characteris- Figure 2.2b. VOL versus IOl for H64x Series
tic impedance of the transmission line. The output

386
 · SWEEP VOLTAGE V8ISUS 10H DERIVATION OF T pel versus CL RELATIONSHIPS

Once the designer has chosen a termination technique,

4.5 the relationship of T pd versus CL for the specific application
:E should be derived. It is suggested that the derivation be
w 4 performed through simulations using the H64x Clock Driver
Cl
~
0
110 Spice Model Kit. A guideline for deriving the
> 3.5 relationships, T pd versus CL is presented through examples
"-
w for each termination technique discussed.
~ r-- --.. In deriving the relationships necessary to predict
t-. propagation delay a reference for T pd is established by
2.5 finding the propagation delay of the H641 's output driving
o 10 15 20 25 30 circuit. To measure T pd of the output driving gate using
OUTPUT HIGH (rnA)
SPICE, the analysis circuit shown in Figure 3.1 is used.
Figure 2.2c. YOH versus IOH for H64x Series

RW j30n CLK
r-- ECLtoTIL ESDand TIL Input
Package
I Translator
/
IJ ~ L I:}, / Vin
Output Circuitry Model
Circuitry
Gate
Circuitry
r-
ser=10n
~
- Asar= 400
4.15V -
3.15V -
ru
CLK

Rsar=400 I

-..J bI
R- I--
H641 DRIVING 1 GATE OVER VERY SHORT UNE

Figure 3.1. Simulation Block Diagram

\.. -3
_I\, I--
Rser= SOO

25 so 75
TIME In this circuit, the output driving gate is driving one gate
Figure 2.2d. Series Terminated Transmission Line over a very short line (<< 1"). When the interconnect line
=
Output for Rser 10, 30, 40, and 50 n length is this short the SPICE "transmission line" model is
Parallel AC Termination not needed to Simulate the interconnect line; and the
propagation delay due to the interconnect line length can
Parallel AC Termination, shown in Figure 2.3, should be
be assumed to be negligible. The propagation delay is
used when the ability to drive distributed loads or when
measured from the 50% voltage level of the input signal to
driving heavy DC TTL loads is required. Unlike series
the 1.5 V level of the TTL output; and can be expressed as
termination, the parallel AC termination scheme features an
follows:
undistorted waveform along the full length of the line. In
parallel AC termination, the receiving end is terminated to
a voltage through a resistor (RT) in series with a capacitance T pd(model) = Tpd(output gate) +,1 T pd(1 gate load) Eq 3.1
(CT). The value of RT is equal to the line characteristic
impedance. As a rule of thumb CT = 10'TD/ZO, where TO Through a SPICE simulation Tpd(model) was measured to
is the delay of the transmission line. When the termination be 2.76 ns. Rewriting the equation above to solve for
resistance matches the line impedance, no reflection occurs Tpd(output gate), the equation becomes:
because all the energy is absorbed by the termination. The
parallel AC termination scheme consumes no DC current Tpd(output gate) = 2.76 ns -,1 T pd(1 gate load)' Eq 3.2

'-D-rri:"'b-"
with outputs in either state.
To solve for T pd(output gate), the T pd due to the capacitive
loading of 1 gate is needed. This relationship will also be
very useful in finding propagation delay contributed by
fanout. By using the same circuit as above and incrementing
the number of receiving gate inputs, measurements of T pd
'6 CT are taken for each increment in the number of receiving gates
PARALLEL AC TERMINATEO TRANSMISSION UNE in order to develop a relationship between Fanout versus
Figure 2.3. Block Diagram: Parallel AC Termination Propagation Delay (,1 Tpd/,1# of Gates).

387
The following measurements were taken: determine this relationship, the circuit in Figure 3.1 was
modified by adding a load capacitor in parallel with the
Table 3.1 receiving gate, the value of the load capacitor was varied
, of Galea Tpd L-H(ns) Tpd H-L(ns) and measurements of the propagation delay taken for each
value of Cl. The data is summarized and shown in a plot
1 2.76 2.88
2 2.82 3.02 in Table 3.2 and Figure 3.3a, respectively.
4 2.93 3.2
6 3.02 3.46 Table 3.2
8 3.15 3.64 CL (pF) Tpd L-H (n8) Tpd H-L (ns)
15 3.99 4.01
0 2.76 2.88
10 2.98 3.34
and plotted below: 20 3.19 3.76
30 3.39 3.99
4.5 40 3.52 4.18
50 3.75 4.35
Tpd H·L 70 4.07 4.66
4
1 .......-Z T~H~L
. /V /
-
l-
.:?- ~ l-
3.5
,/
i I--
V ...-f4
/

-..... f-"'"" l- i-" -

3

2.5
o
~~ Tpd L·H

FANOUT
10

Figure 3.2. Fanout versus T pd for a "Short Line"

15
V-
~ f-"'""
i-'

--
;'"
~
If
Tpd L·H
~

2
o 10 20 30 40 50 60 70
Cload
The value of ~(Tpd)/ ~(# of gates) can be calculated by
finding the slope of the Fanout versus T pd curve. From Figure Figure 3.3a. CL versus Propagation Delay
3.2, ~(Tpd)/~(# of gates) can be measured to be, for Short Line
approximately:
From this data the change in propagation delay with
~ (Tpd) / gate =0.057 nsf gate. Eq3.3 respect to the change in Cl was calculated and the sensitivity
of the output driver to capacitive loading for an unterminated
T pd (output) can be calculated by substituting this data into Eq.
"short'" line was found to be 0.02 ns/pF. The capacitive load
3.2.
(Cl) per gate can be calculated by taking the ratio of
T pd(output gate) = 2.76 ns - 0.057 ns = 2.7 ns Eq 3.4 delay/gate to delay/Cl.

Note, T pd (output gate)isnotthepropagationdelayoftheH64x, Cl/gate = (0.057 nsigate)/(0.02 ns/pF) = 2.85 pF/gate

Eq 3.5
but, merely the propagation delay of the output circuitry
common to all of the H64x series. This value and the values When board layout constraints demand that line lengths
derived in the following T pd versus Cl curves should not be exceed 4.5", the effects of capacitive loading are no longer
used as actual values of propagation delay for the H64x seen at the output of the gate (output loading) but instead
series and are derived here only as a reference on which are seen by the line (transmission line loading). SPICE
to base the effects of line length, fanout, and termination simulations of Output gate Delay versus Line length are
technique on the propagation delay of the H64x devices. shown in Figure 3.3b. Notice that for line lengths less than
In real system designs, it will not always be realizable 4.5" the Output gate Delay increases linearly as the line
for the designer to have equal line lengths and fanout on length (or capacitive load) increases. For line lengths greater
each output. In attempting to achieve symmetrical loading than 4.5" the Delay curve sharply rolls off and approaches
on each output the designer will need to compensate for a constant value. The rolloff occurs when the output gate
unsymmetrical loading by either adding line length or no longer sees the capacitive load at the end of the
capacitive loads on appropriate lines. If the designer knows transmission line. The output gate sees only the '"load'" of
the skew between two paths, a relationship between the transmission line and thus, T pd approaches a constant
capacitive loading and propagation delay is needed to value. So, for accurate simulations of T pd versus Cl when
determine the capacitive load needed for compensation. To lines are greater than 4.5", the line should be modeled as

388
a transmission line and the effect of capacitive loading on in Table 3.3 along with the measurements taken for a
propagation delay re-evaluated. transmission line with Zo = 75 ohms:

Table 3.3
2.5
CL(pFI Tpd (nsl, Zo = 50 Tpd (nsl, Zo = 75
2.3
I---; i.!""50pFL AD'\ 0 4.3 4.27
2. 1 I \ 10 4.71 4.79
". 20 5.03 5.2
1.9 Y

-
30 5.31 5.55
1.7 I---; ~25pFLOA[
\
40 5.56 5.86
50 5.B 6.16
1.5
60 6.02 6.44
1.3 I-- 1T0pF OAl 70 6.22 6.71
100 6.B2 7.45
1.1
*Note: T pd includes the 1.8 ns delay of the transmission line.
0.9
o 4 6 8 10 t2
UNE LENGTH (In) Plotting Cl versus Tpd, the relationship is shown in Figure
Figure 3.3b. Tpd versus Line Length 3.5.

Using the SPICE model of a transmission line, three

termination techniques will be examined. The transmission
line model chosen for this exercise is available in the SPICE ., ,..V
Tpd L·H 75 ,V
simulator and assumes a propagation delay of 0.18 nslinch. ~
Relationships between line length and termination technique .Y ..-V
will be developed along with relationships between
propagation delay and capacitive loading for each ,.. V 1"
V
termination type. ...... ~ I
Tpd L·H 50
~~ ·1 I

CASE 1: UNTERMINATED TRANSMISSION LINE 4

o 20 40 60 80 100
CL (pF)
The analysis circuit, in Figure 3.1, was modified by Figure 3.5. CL versus T pd for Untermlnated Line
inserting a transmission line between the output driving
circuit and the receiving gate circuit. A capacitor, Cl, was
A comparison between Figure 3.3a and Figure 3.5 shows
hung in parallel with the receiving gate. (Refer to Figure 3.4).
that output loading versus transmission line loading produces
a nonlinear change in the T pd versus Cl curves. This implies
that, for line lengths> 4.5" the designer should use the Tpd
Zo= 50 OHMS, Td =1.8 ns versus Cl curve which corresponds to transmission line
,...----,
EClto TTL ESD and ESDand loading, for predicting propagation delay. Figure 3.5 shows
TTL Input
Translator Package Package Gate Tpd versus Cl curves for unterminated transmission lines
Output Model Model Circuitry with Zo of 50 0 and 75 o. Notice, the Ll Tpdf LlCl increases
Circuitry Circuttry Circuitry
as Zo increases. This is due to the fact C0500 > C0750·
This demonstrates an advantage of using lines with lower
4.15V -
3.15V -
ruCLK
ZO°

UNTERMINATED TRANSMISSION UNE CASE 2: SERIES TERMINATED

TRANSMISSION LINE
Figure 3.4. SPICE Model for Unterminated Line

The analysis circuit, in Figure 3.4, was modified by

To determine a relationship between Tpd versus Cl for inserting a series resistor between the output driving circuit
the Unterminated transmission line, the capacitive load was and the transmission line. A capacitor, Cl, was hung in
varied and measurements of propagation delay at the load parallel with the receiving gate. The resulting Circuit is shown
were taken for each value of Cl. The results are tabulated in Figure 3.6.

389
 Cload versus Tpd FOR MATCHED SERIES TERMINATED UNE
11
Zo =500HMS, Td = 1.8ns
ECLtoTIL ESDand ESDand TIL 10 _I ..1. TpdH-L?9 ~
Translator Package Package Input TpdL-H 7Z. I--"'"-J....-'"
Output
Circuitry
Model
Circuitry

4.15V - ru
CLK CL~
Model
Circuitry
Gate
Circuitry

~~
./. ~
.-
./
-"
--
.....
1/ l...oo'"
1/
K
f-'""'
.-
-"""'Tpd L-H 50

--
3.15V - I:iIII'" Tpd H-LSO
SERIES TERMINATED UNE
r I
~
Figure 3.6. Simulation Circuit: Series Terminated Line
4
o 20 40 60 60 100
First, Zo was set to a common value of 50 ohms and the Ctoad
line length was set to 10", which translates to a line delay,
Figure 3.7. CL versus T pd: Series Terminated Line
TO, of 1.8 ns. With CL set to 0 pF and measuring the
propagation delay at the output of the transmission line, the
accuracy of the transmission line model's TO can be Comparing these results to the results obtained for an
confirmed by comparing this measurement to the measured unterminated line, it can be observed that the Tpd versus
vlaue of Tpd at the input of the transmission line. The CL relationship is not only affected by line length, but also,
equation for the measured TO is: by the termination technique chosen by the designer. Using
Eq 3.6 series termination produces a significant decrease in
TO = Tpdout - Tpdin·
undershoot and overshoot. The tradeoff is an increase in
Plugging measured values into this equation for the above li Tpd/liCL. Notice, even when the gate is unloaded, the
circuit: series terminated line is slower than the unterminated line.
TO = 4.69 ns- 2.9 ns = 1.79 ns Eq3.7
CASE 3: PARALLEL AC TERMINATION
and we see it is very close to the predicted delay of (0.18 WITH LUMPED LOAD
nslinch)" to inches = 1.8 ns.
To determine a relationship between Tpd versus CL for The original circuit was modified by inserting a
matched series termination, the capacitive load was varied transmission line between the output driving circuit and the
and measurements of propagation delay at the load were receiving gate circuit. The circuit is shown in Figure 3.8. For
taken for each value of CL. The results are tabulated below Parallel AC Termination the matching network is a shunt
along with the measurements taken for a transmission line resistor (RT) in series with a capacitor (CT) to ground, placed
with Zo = 75 ohms: at the output of the transmission line. From transmission line
theory, the Parallel AC Termination technique requires that
Table 3.4 the resistance of RT match the characteristic impedance of
CL(pF) T pd (ns), Zo = 50 Tpd (ns), Zo = 75 the transmission line (ZO) for optimum performance
(minimum undershoot and overshoot and minimum propaga-
0 4.7 4.7
10 5.24 5.44 tion delay). Also as a rule of thumb the optimum CT can be
20 5.7 6.08 calculated as, CT = 10*TO/Zo, where TD = the delay of the
30 6.08 6.62 transmission line and Zo is the characteristic impedance of
40 6.45 7.11 the transmission line.
50 6.82 7.62
60 7.18 8.1
70 7.53 8.6 Zo = SO OHMS, Td = 1.8ns
100 8.57 9.97 ECLto TIL TIL
ESDand ESD and
-Note: T pd includes the 1.8 ns delay of the transmission line. Translator Package Package Input
Yin Output Gate
Model Model
Circuijry Circuitry Circuitry Circuijry
Plotting CL versus T pd, refer to Figure 3.7, the relationship
between CL and T pd is found to be a linear equation, when
the termination is matched, that can be expressed as follows: 4.1SV -
3.ISV -
ru
CLK

Tpd =ZO* CL + TO + delay of output circuit Eq 3.8

PARALLEL AC TERMINATION WITH WMPED LOAD
slope: Zo
y·intercept: TO + delay of output circuit Figure 3.8. Simulation Circuit: Parallel AC Termination

390
 With Zo set to 50 ohms and TO set to 1.8 ns, RT and overshoot, however, it causes a positive linear shift in the
Cr were calculated as 50 ohms and 360 pF, respectively. T pd versus CL curve. Series termination caused an increase
CL was varied and propagation delay measurements in aTpdf aCL of approximately 0.01 ns/pF for a transmission
recorded at each value of CL. Next, Zo was set to 75 ohms line with a Zo of 50 n.
As a result, propagation delays for
and TO to 1.8 ns. Values of AT and CT were recalculated series terminated lines quickly pass those of Paraliel AC
for these conditions and set to 75 ohms and 240 pF, terminated lines as capacitive load is increased. The tradeoff
respectively. Again CL was varied and propagation delay in choosing Paraliel AC termination over series termination
monitored. The results are tabulated in Table 3.5. is that Paraliel AC termination requires an extra capacitor,
CT, in each matching network. Comparing the Tpd versus
Table 3.5 CL curves for Zo = 50 0 and 75 0 in Figure 3.9 it is seen
that, as was the case in the other examples, the aTpdf aCL
CL (pF) T pel (ns), Zo = 50 Tpel (ns), Zo = 75
increases as Zo increases.
0 5.01 4.86
5 5.17
10 5.32 5.32 CASE 4: PARALLEL AC TERMINATION
15 5.47
20 5.63 5.73
WITH DISTRIBUTED LOAD
25 5.75
30 5.88 6.06
35 6.00 The original circuit was modified by inserting three
40 6.14 6.4 separate transmission lines between the output driving circuit
45 6.26 and the receiving gate circuit. The sum of the time delay of
50 6.38 6.71 the three transmission lines being 1.8 ns, to be consistent
55 6.50 with the data taken for the other termination techniques.
60 6.61 6.95
70 6.85 7.28 C\lpacitive loads are placed at the end of each transmission
100 7.54 8.03 line. The paraliel AC matching network is placed at the end
of the last transmission line. The circuit is shown in Figure
*Note: T pd includes the 1.8 ns delay of the transmission line.
3.10.

Plotting CL versus T pd results in the relationship shown in

Figure 3.9.
Zo = 50 OHMS, Td = 1.8 ns
ECLtoTIL ESDand ESDand TIL
Translator Package Package Input
Output Model Model Gate
I Circuilry Circuilry Circuilry Circu~ry

T~L'HJ5 .....
i.,...--'
I ..,. ........ i.,...--'-
..".;- .......
........:::: ~
~,

~ I PARALLEL AC TERMINATION WITH DISTRIBUTED LOAD

~'r" Tpd L·H 50
Figure 3.10. Simulation Circuit: Parallel
AC Termination
4 I I
o 20 40 80 80 100
<:toad
Figure 3.9. CL versus T pel: Parallel AC Termination Table 3.6
CL (pF) Tpel L·H(ns)

A comparison of the results of the Paraliel AC termination 0 5.01

15 5.35
scheme versus the unterminated scheme illustrates almost
25 5.54
no increase in aTpdfaCL. However, the propagation delay 30 5.68
for a Paraliel AC terminated line driving a 0 pF load is greater 45 5.98
than that for an unterminated line or a series terminated line 60 6.29
driving 0 pF. So, choosing Paraliel AC termination over an 90 6.84
unterminated line significantly decreases undershoot and -Note: Tpd includes the 1.8 ns delay of the transmission line.

391
 determining the relationship, Tpd versus T D for each

\,Ji ,., V termination technique when CL = 0, the designer could

--
",

,./" I-- determine the y-intercept of that termination techniques' ''Tpd

versus CL" curve for a desired line length.
~ V ,./"
",

~ /~H.L
Tpd versus UNE LENGTH FOR DIFFERENT TERMINATIONS
.,/
V I pd I
4
o 20 40 60 80
Cload
Figure 3.11. CL versus T pd: Oistributed Load:
Parallel AC Termination

Tpd L·H versus CLOAD FOR MATCHED SERIES TERMINATION 2L-____ ~ ______ ~ ______L __ _ _ ___O

--
10
o 1
Td (ns)
- TD= 1.8ns
TD=2.7ns
,., Figure 3.13. (Cld versus Tpd) versus

1-- .....
i-""
........
..... -
",
1,\
~

",

i-""" - - >-
K

\ .-
.....

TD=~.9nsl_
Termination Technique

By setting the capacitive load to 0 pF for each type of

termination, and varying the line length only; this type of
relationship is established. The results are shown in Figure
3.13. Once the designer knows the length of the transmission
line and the termination technique, a "T pd versus Line
3 Length" chart can be used to determine the y-intercept of
o 20 40 60 80 100 the appropriate termination schemes' "Tpd versus CL" curve.
Cload (pF) Note, these values have been derived using only the output
Figure 3.12. (T pd versus CLl versus TO for section of the H641 driving the input section of the H645.
Series Termination Therefore these propagation delay values are not
representative of actual delays of the H64x and are derived
With Zo set to 50 ohms and TD set to 1.B ns. Using the here only to show the relationship of T pd versus TD. It is
equations above RT and CT were calculated as 50 Q and suggested that the designer derive the T pd versus TD curve
360 pF, respectively. Total CL was varied and propagation with CL =0 pF for their specific application, using the "H64x
delay measurements recorded at each value of CL. The Clock Driver I/O Spice Model Kit."
results are tabulated in Table 3.6. Plotting CL versus T pd
gives the relationship shown in Figure 3.11. Summary
Data has now been derived for the relationship between The MC10H/100H64x series ECLITTL translating clock
capacitive loading versus propagation delay for the following drivers are ideal devices for systems requiring very low skew
termination techniques: unterminated transmission lines, clock distribution. Optimum skew performance from the H64x
series termination, and parallel AC termination. To generalize series requires equal capacitive loading on each output. To
these results for any interconnect line length, the relationship minimize skew in a system not only requires minimal "output
of (CL versus T pd) versus Line Length must be evaluated. to output" skew and "part to part" skew, but also requires
Using the series termination circuit configuration, the delay equal propagation delay along all paths carrying the clock
(line length) of the transmission line is varied from TD = 0.9 signal. Perhaps the most accurate technique of obtaining
ns to TD = 1.B ns to TD = 2.7 ns. At each line length setting equal propagation delay along all paths is to add trace to
a "CL versus T pd" curve was extracted. The results are the lines with shorter propagation delays. However, this is
summarized in the plot, Figure 3.12. a trial and error method and does not always provide a
Notice, changing the length of the transmission line feasible solution due to size constraints of the board. Another
merely causes a vertical shift of the Series Terminations' "T pd technique of obtaining equal propagation delays on each
versus CL" curve. This will be found true for the unterminated path is to add capacitive loading on paths with shorter
and the parallel AC termination schemes as well. So, by propagation delays. This method requires an understanding

392
of Tpd versus CL relationships. As shown in this note, T pd finally series termination. The tradeoff in choosing terminated
versus CL relationships are dependent on line length, lines versus unterminated lines is, of course, minimized
termination technique, and the characteristic impedance of undershoot for an increase in 6Tpdf6CL. The tradeoff in
the transmission line. If line lengths are less than 4.S", choosing parallel AC termination versus series termination
propagation delay can be predicted by assuming a lumped is an increase in the number of parts for a decrease in
capacitive load at the output of the driving device. When lines 6 T pdf 6CL. Since the values in this note have been derived
exceed 4.S" the capacitive load is no longer seen by the for the specific case of the output section of the H641 driving
output driving device, but is instead seen by the transmission the input section of an H64S, the values of propagation delay
line. A different Tpd versus CL relationship exists for the are not representative of actual delays of the H64x series
transmission line than the output device. The transmission of devices. Also, due to SPICE simulator limitations of
line Tpd versus CL relationship is dependent on termination accuracy, delays are not exact and should be used to predict
technique and line characteristic impedance. The depen- relative differences only. For these reasons, the designer is
dence on termination technique is important at line lengths encouraged to use the "H64x Clock Driver I/O Spice Model
greater than 4.S" because at these lengths undershoot Kit" to derive the relationships necessary to predict and
becomes significant enough (20% of logic swing for a 20 minimize skew for their particular system. To obtain the
pF load) to necessitate some sort of termination scheme to "H64x Clock Driver I/O Spice Model Kit" contact a Motorola
minimize its adverse effects. Relationships of Tpd versus CL representative.
were derived and compared for three termination schemes:
the unterminated line, the series terminated line, ana the References
parallel AC terminated line. All Tpd versus CL curves were 1Motorola MECL System Design Handbook, second edition,
derived for transmission lines with TD = 1.8 ns and Zo = Motorola Inc., 1983. Stock Code HB20SRlfD.
SO nand 7S n. For all three termination schemes, increasing
the characteristic impedance of the transmission line 2Motorola ECLinPSTM Data Book, Motorola Inc., 1991. Stock
produces an increase in the 6 Tpdf 6CL relationship. Of the Code DL140R1fD.
three termination techniques the unterminated line had the 3Fairchild FAST Applications Handbook. Fairchild Semicon-
smallest 6 Tpdf 6CL, followed by parallel AC termination, and ductor Corporation, 1987.

393
394
 AN1402

I
MC1 0/1 00H600 Translator Family
I/O SPICE Modelling Kit

Prepared by
Debbie Beckwith
Eel Applications Engineering

This application note provides the SPICE information

necessary to accurately model system interconnect
situations for designs which utilize the translator circuits
of the MC 1OH600 family. The note includes information
ontheH600, H601, H602, H603, H604, H605, H606and
H607 translators.

395
 MC1 0/1 00H600 Translator Family I/O SPICE Modelling Kit

Objective ESD protection circuitry and package models. The devices

shown in shaded boxes on the 1/0 buffer schematics are
With the difficulty in designing highspeed controlled modelled by the subcircuits illustrated on the appropriate
impedance PC boards and the expense of reworking those subcircuit schematic sheet. This hieracrchical method of
boards the ability to model circuit behavior prior to committing schematic representation is used to help simplify and clarify
to a board layout is essential for high speed logic designers. the buff8f schematics.
The purpose of this document is to provide the user with
enough information to perform basic SPICE model analysis on The H600 and H602 utilize the same output buffer. This
the interconnect traces being driven or driving the H600, buffer is represented by the H600 Output schematic of
H601, H602, H603, H604, H605, H606 or H607 translator Figure 6. These devices are dual supply devices which means
chips. The packet includes schematics of the input and output they require +5V, -5.2V and ground supplies. The A and AN
structures as well as ESD protection structures and package inputs should be driven differentially with the HIGH level at
models which may affect the waveshape of the input and VCC - O.85V and the lOW level equal to VCC -1.25V and the
output waveforms. Internal bias regulators and logic circuitry Band BN inputs should be driven differentially with a voltage
are not included as they have little impact on the 1/0 swing from -2.0V to -2.4V Notice the ESD protection circuitry
characteristics of the device and add a significant amount of on the output, this circuitry is represented by the FPS009E
time to the standard simulation analysis. In addition a SPICE schematic of Figure 15.
parameter set for the devices referenced in the schematics is
provided. The remainder of this document will introduce the The H601 is also a dual supply device, however, both the
various input and output stages for the H60x translators as input and output buffers are represented by one structure as
well as the other structures which affect the 1/0 characteristics shown in the H601 1/0 Schematic of Figure 7. The H601
of these devices. requires a single ended input, IN which should be driven from
VCC-O.9to VCC-1.75V Notice the "ECl in Pad Cell" on the
Schematic Overview input, this circuitry is represented by the "ECl Input Pad Cell"
schematic of Figure 15, and includes the 50KQ input pull down
There are ten basic schematics which can be used to resistor and the ESD protection circuity for the ECl input. The
represent all of the 1/0 for the H60x family of translator chips. A same ESD structure is used on the output buffer section of the
single TTL input structure can be used to represent all of the H601 1/0 Structure as is used on the H600 output buffer. The
TTL inputs, with the exception of the H606s "ClKT" input, H601 1/0 buffer also requires one bias supply, CBIAS, and
which should be modeled using the "H606 TTL Input" differential tritstate buffer inputs, TRI and TRIB. The CBIAS
structure. All of the ECl inputs can be represented by a single input should be set at 1.1V, while the TRI and TRIB inputs
ECl input structure, with the exception of the H601s "data" should be driven by the "H601 ECl Input" structure of Figure 3.
inputs, the H601 s ECl "TRI" and "TRIB" inputs and the H602s
"EClST" input, which should be modeled using the "H601 1/0 The H603 Output gate is represented by the schematic of
Gate" structure, the "H601 ECl Input" structure and the "H602 Figure 8. The IN and INB inputs should be driven differentially
ECl Input" structure, respectively. Six different output buffers with voltage swings of VCC to VCC - 0.85V The CBIAS input
represent all of the output buffers for the H60x series of should be forced to 1.1 V and the ENA input should be driven
translators. The rest of the schematics provided represent from VCC - 0.85 to VCC - 10.85V. The H603 again uses the
subcircuit schematics for the above mentioned 1/0 buffers, same ESD protection scheme as the H600.

Table 1. Device Type Input Cross Reference

Part Type Eel Inputs TTL Inputs H601 va H606 TTL Inputs H602 Eel Inputs H601 Eel Inputs
H600 EClST TTlST, 00-08 None None None None
H601 None TTLOE 00-08 None None EClOE
H602 lEN, RESET 00-08 None None None None
H603 All Inputs None None None None None
H604 RESET, ClK, ClKN ClKT, DO-OS None None None None
H605 All Inputs None None None None None
H606 ClK,ClKN,RESET None None ClKT, DO-OS None None
H607 All Inputs None None None None None

396
 The H604 and H606 utilize the same output buffer. This Table 2. Input and Bias Levels
buffer is represented by the "H604 Output Schematic" of Schematic Input Level
Figure 11. The IN and INB inputs should be driven differentially
with voltage swings from VCC - 0.B5 to VCC -10.B5V. Note, Eel Input VBB Vee-1.3V
the ESD protection circuitry is the same as the H600. Ves VEE + 1.3V
H600, H602 AlAN Vee - O.85V to Vee -1.25V
Figure 12 represents the schematic for the output buffer Output BlBN Vee - 2.0V to Vee - 2.4V
utilized by the H605. The IN and INB inputs should be driven Ves VEE + 1.3V
differentially from VCC - 0.B5 to VCC -1 0.B5V, while CBIAS is
H60l110 IN Vee - O.85V to Vee - 1.85V
forced to 1.lV. Again, the same ESD protection scheme is eBIAS 1.W
used as on the H600. TRlfTRIB -2.W to -2.5V
Ves VEE + 1.3V
The H607 output buffer is represented by the schematic of VBB Vee -1.3V
Figure 13. The IN and INB inputs should be driven differentially
H603 Output INIINB Vee to Vee - O.85V
from VCC to VCC - 1.BV. The ESD protection circuitry is ENA Vee - O.85V to Vee - 1.85V
the same. Ves VEE + 1.3V
VBBP Vee- 2.W
Two input structures can represent most of the inputs forthe eBIAS 1.lV
H60x family of translators, one for TIL inputs and one for ECl
inputs. The exceptions were discussed previously and the H605 Output INIINB Vee - O.85V to Vee - 1.29V
eBIAS 1.W
various inputs and appropriate input models are summarized VEE + 1.3V
Ves
in Table 1. For the dual supply devices with ECl inputs the
VCC and the VEE on the typical ECl input gates should be H604, H606 Ves VEE + 1.3V
Output
tied to ground and -5.2V respectively. All input pins should
have both a package model and ESD protection circuitry H6070utput IN/INB Vee to Vee - O.85V
connected to them. For TIL inputs the ESD protection circuitry
is represented by the FPS009E schematic of Figure 15. For
ECl inputs the ESD protection circuitry is represented along Handling Power Supplies
with a 50KQ input pull down resistor as part of the "ECl in Pad
It is important to properly apply the power supply voltages to
Cell" represented in Figure 15. The "Package Model" of Figure
accurately model these Circuits. This section will explain the
15 is self explanatory, the parasitic values provided are worst power supply terminology used on the I/O buffer schematics
case numbers. The package capacitance combines with the and how to properly apply these supplies with the appropriate
parasitic transistor capacitance of the input device and the package model.
ESD circuitry to comprise the load capacitance of the input.
The various input buffer ESD circuits are outlined in Figure 15,
notice that the ECl inputs utilize a different structure than the Table 3. Power Pin Descriptions
TIL inputs and outputs. The typical ECl input schematic Power Description
represents a single ended ECl input, the VBB reference
should be tied to VCC - 1.3V and the VCS bias should be tied EVee EVee is the most positive supply for the Eel
input gate (+5V for the H607 and ground
to VEE + 1.3V. To simulate a differential ECl input one simply for H60D-H606)
connects the complimentary input to the "VBB" side
of the input gate along with an associated ESD and VEE VEE is the most negative supply for an Eel gate.
For the H607 it is equal to ground, for the
package model. The differential input does not use the VBB
H600-H606 it is equal to -5.2V
switching reference.
TVeel Internal Vee for TTL Circuitry
For all of the input and output buffer schematics the
resistors should NOT be simulated as simple SPICE resistors. GNDI Internal ground for TTL Circuitry
Because these resistors are realized by a diffusion step in
wafer processing there are parasitic capacitances associated Table 3 lists the voltage supplies referenced on the I/O
with each. The subcircuit schematic is shown for the resistors schematics along with a description of each. The key to
in the "Resistor Model" schematic of Figure 15. The value of properly simulating these power supplies is in the application
each subcircuit resistor is one half the value given on the top of the package model. Because the output buffers, to a varying
level schematic and the parasitic capacitance is modelled by a degree, share VCC and ground pins, adjustments need to be
diode back biased to VCC. Also note that the resistor made to get a more accurate model if all of the outputs are not
temperature coefficient (TC) values for both the resistor simulated at the same time. If for example a single output is to
subcircuit and the resistors in the device subcircuits are be simulated the package model for the TVCCI and TGNDI
provided. For modelling at nominal temperatures only, these supplies should be scaled based on the number of outputs
TC's can be omitted. If however modelling will be performed which normally share the supplies. If the Simulated output
at the temperature extremes the TC information should normally shares its supplies with two other outputs the
be included. . package inductance would be tripled to simulate the same
inductive glitch seen on the power pin in an actual application.
Table 2 is provided to summarize the various internal The capacitive value for the package model is not as critical
voltage swings and bias levels required to run the appropriate and thus can be left alone. This method will allow users to
SPICE simulations. more accurately model an output behavior without resorting to

397
more accurately model an output behavior without resorting to be to manipulate the generic netlists. If, however the netlists
more complicated and lengthy simulations. The internal power are desired or questions arise about the contents of this
and ground pins are all powered through a single pin and are document the user can contact an ECl applications engineer
basically static, as a result no adjustments are needed for the for assistance.
package models on these supplies. Table 4 outlines the
internal power distribution for the H60x translators, this
information can be used to determine the scaling factors for Table 4. Power Pin versus Outputs
the package inductance for the output buffers. To use the table Number 01 Number Number
simply identify the output in question and divide the number of Part Type Outputs TVCC TGND
outputs in the group by the number of power pins for that
group, this will give the multiplication factor for the inductance. H600 9 3 N/A

H60l 9 2 3
Summary H602 9 3 N/A
The information included in this kit should provide the user H603 9 2 3
with all of the information necessary to do SPICE level system
H604 12 3 N/A
interconnect modelling. The schematic information provided
in this document is available in nellist form through EMAil or H605 6 2 2
an IBM or Macintosh disk. However with today's advanced H606 3 3 N/A
design tools it will probably be a simpler task to enter the
schematics in a good schematic capture package than it will H607 6 2 2

398
 PKG
~cc~-----------r---------------'r-----~

OUTI

VBB I------If---o CUTIB

V~-E~~----------------E-~~-C

R6
9000

VEE

Figure 1. Typical Eel Input Gate

Nl
FPSOO1

'P~ OSI
GRSOOI
AX
1- 2
TC = 4.45E-4, 2.78E-6
REP1
15.2

1----0 OUT REXT

13.7 .~ Dl
DSUBSOOI
~2

R4
225Cl

Figure 2. Typical TTL Input Gate

399
 PKG
EVCC D--..,.---.--------------.---....,

1 - - - - + - 0 OUll!
OUT

Figure 3. H691 ECl Input Gate

PKG
EVCCD------.-----------"""'T---....,

1----:..-+--0 OUll!
OUT

Figure 4. H602 ECl Input Gate

400
 Rl
2fcO Nl
FPSOO1

~r OSI
GRSOOI
r-------r--+----~DO~ RX
2
TC = 4.45E-4. 2.78E-8
REP!
15.2

REXT
13.7

N2

TGNDI

Figure 5. H606 TTL Input Gate

PKG
~CC e>-----------,---------------,----------,

RCl1
272.70

AD-------·C
~D-------------------~~------~

BD-------------------~

BN~--------------------------._+_------~

Figure 6. H600, H602 Output Gate

401
 '-----.J...--..::.:..::.::.:J=--..L-----<JTGNDI

Figure 7. H601110 Gate

Figure 8. H603 Output Gate

402
 N1
N1

RT OS1
5.3 QPS114

N2

01
OSUBS114

01 02
OSUB1N05 OSUB2N05 N2 -=
Te =4.45E·4, 2.78E-6
Te =4.45E-4, 2.78E-6
N3
-= N4 -=
QPNN05D QPS114

N1
N1
Te =4.45M, 2.78U OS1
GRSOO3

RX
R4 2
7.89
Te =4.45E-4, 2.78E-6
REPI
15.3

N2
01
OSUB139 REXT
22.9 01
OSUBSOO3

N3 Te =4.45M, 2.78U
-= N2 -=
QPN139 FPSOO3

N1 N1

R1 R1
23.4 OS1 19.1
FP025X

N2Q---'------L N20---'-----L
01 01
OSUB025 OSUB025X

Te = 4.45E-4, 2.78E-6 Te =4.45E-4, 2.78E-6 N3

N3

FPN025 FPN025X

Figure 9. H601 Output Subcircuits

403
 N5 N1

N1

RT
5.4
OSl
QPSl14

N2

01
02 OSUBS114
OSUB2N05
01
TC = 4.45E·4, 2.7BE-6
OSUB1N05 N2 -=
-= -= TC = 4.45E-4, 2.7BE-6
N3 N4

QPNN05M QPS114

Nl
Nl
OSl
GRSOO3

RX
R4 2
7.B9
TC = 4.45E-4, 2.7BE-6
REPI
15.3

N2 01
OSUB139 REXT
22.9 01
OSUBSOO3

N3
-= N2 -=
QPN139 FPS003

Nl Nl

Rl Rl
OSl 23.4 19.1
FP025

N20--.L------C N20--'------l:..
01 01
OSUB025 OSUB025X

TC = 4.45E-4, 2.7BE-6 TC = 4.45E-4, 2.7BE-6

N3 N3

FPN025 FPN025X

Figure 10, H603 Output Subcircuits

404
 ~~PCK~G__________________r_--------_.------~--~

R2
272.7n

IN D-----------------'h,

INB D--------------------t---~

Vcs

VEE

Figure 11. H604, H606 Output Gate

WCCID-~,----r_----r_-_,----_.--------~--------rF~~

CBIAS 0--+---+---'

IN

INB 0.---1------'

VEE

Figure 12. H605 Output Gate

405
W~I~-----r-----r----~----r----r-----r-----r------~~--'
IN 00---+---11-.......(,.
INBOo--;::::=t--f...

TGNDIIC>~--~--~--~--L--~--~---"""'~----L-~

Figure 13. H607 Output Gate

406
 N5 N1

N1
OSl
WNOS QPSl14
RT
5.4 OSl
OPSl14

N2

01
TC = 4.45E·4, 2.78E-S 02 OSUBSl14
OSUB2N05
01
QPNN05M OSUB1N05 N2 -=-
-=- TC = 4.45E-4, 2.78E-S
N3
-=- N4
N1
N1
OSl
GRSOO3

RX
R4 2
7.89
TC = 4.45E-4, 2.78E-S
REPI
15.3

N2 FPSOO3
01
OSUB139 REXT
22.9 01
OSUBSOO3
TC = 4.45M, 2.78U
N3
-=- N2 -=-
N1 N1

R1 R1
23.4 19.1

N2 N2
01 01
OSUB025 OSUB025X

N3
N3
-=- -=-
N1

Rl
19.5

N2Q---'-----f..
01
OSUB1OB

N3 -=-
Figure 14. H607 Output Subcircuits

407
 AS
7ID
RPKGl
INIO...-r:-:=-~Mri-'D OUT
RPKG3
0.20 RP
1-A.N\r---D INT 5OkO

Package Model ECl Input Pad Cell

(2S-lead PlCC)

Nl

VCCI POS
Rl 01 RIA
DSI 4.97 RES·DIOOE SPICEPAR/2
...
GROO9E
~

V 01 R1B
TC= 431.6U, 8.97U
N 2 Q - - + - - - - . [~
, PNOO9E ,II. 01 SPICEPAR/2
I -~DSUB009E
NEG
TC= 4.45E·4, 2.7BE·6 -=
FPS009EX Resistor Model

Figure 15. Miscellaneous Subcircults

SPICE Parameter List

TTL Subcircuit Models

.MODEL GRS001 D (IS=4.27E-14 RS=53 N=1.044 TI=10PS
+ CJO=54FF VJ=.4 M=.33
+ EG=.69 XTI=3 FC=.5 BV=30)
.MODEL DSUBS001 D (IS=1E-16 RS=O N=1TIt=500PS
+ CJO=87FF VJ=.51 M=.24
+ EG=1.115 XTI=3 FC=.5 BV=35)

.MODEL DSUB1 N05 D (CJO=203FF VJ=.51 M=.24)

.MODEL DSUB2N05 D (CJO=388FF VJ=.51 M=.24)
.MODEL PNN05A NPN (IS=1.662E-17 BF=70 NF=1.008 VAF=30 IKF=10A
+ ISE=O NE=1 BR=5 NR=1 XCJC=.1 VAR=100
+ IKR=. 7125MA ISC=1.803E-16 NC=1 RB=656.7 RBM=218
+ RE=O RC=91.62
+ CJE=86.47FF VJE=.9 MJE=.4
+ CJC=58.32FF VJC=.53 MJC=.37
+ TF=40P XTF=O VTF=100 ITF=3.89MA PTF=O
+ TR=200P XTB=1.51 EG=1.115 XTI=5 FC=O.5)
.MODEL PNN05B NPN (IS=1.583E-16 BF=70 NF=1.008 VAF=30 IKF=1 OA
+ ISE=O NE=1 BR=5 NR=1 XCJC=.1 VAR=100
+ IKR=6.78MA ISC=1.717E-15 NC=1 RB=77.29 RBM=31.25
+ RE=O RC=9.61
+ CJE=751.6FF VJE=.9 MJE=.4
+ CJC=445.2FF VJC=.53 MJC=.37
+ TF=40P XTF=O VTF=100 ITF=37.1MA PTF=O
+ TR=200P XTB=1.51 EG=1.115 XTI=5 FC=O.5)

408
.MODEL WN05 D (IS=1.0578E-12 RS=37.6 N=1.044 TT=10PS
+ CJO=141. 75FF VJ=.4 M=.33
+ EG=.69 XTI=3 FC=.5 BV=30)
.MODEL DSUBS114 D (IS=1E-16 RS=O N=1 TT=500PS
+ CJO=2.75PF VJ=.51 M=.24
+ EG=1.115 XTI=3 FC=.5 BV=35)
.MODEL QPS114 D (IS=2.52E-12 RS=1.35 N=1.044 TT=10PS
+ CJO=2.1PF VJ=.4 M=.33
+ EG=.69 XTI=3 FC=.5 BV=30)
.MODEL DSUB025X D (CJO=284FF VJ=.51 M=.24)
.MODEL PN025X NPN (IS=4.32E-17 BF=113 NF=1.008 VAF=30 IKF=10A
+ ISE=O NE=1 BR=5 NR=1 XCJC=.1 VAR=100
+ IKR=10.85MA ISC=4.68E-16 NC=1 RB=175 RBM=65
+ RE=O RC=35.2
+ CJE=193FF VJE=.9 MJE=.4
+ CJC=158FF VJC=.53 MJC=.37
+ TF=40P XTF=O VTF=100 ITF=5.7MA PTF=O
+ TR=200P XTB=1.51 EG=1.115 XTI=5 FC=0.5)
.MODEL FP025X D (IS=1.08E-13 RS=48.3 N=1.044 TT=10PS
+ CJO=90FF VJ=.4 M=.33
+ EG=.69 XTI=3 FC=.5 BV=30)
.MODEL DSUB025 D (CJO=284FF VJ=.51 M=.24)
.MODEL PN025 NPN (IS=2.45E-17 BF=113 NF=1.008 VAF=30 IKF=10A
+ ISE=O NE=1 BR=5 NR=1 XCJC=.1 VAR=100
+ IKR=1MA ISC=2.66E-16 NC=1 RB=193 RBM=89
+ RE=O RC=62
+ CJE=123FF VJE=.9 MJE=.4
+ CJC=108FF VJC=.53 MJC=.37
+ TF=40P XTF=O VTF=1 00 ITF=5.7MA PTF=O
+ TR=200P XTB=1.51 EG=1.115 XTI=5 FC=0.5)
.MODEL FP025 D (IS=1.4E-13 RS=52 N=1.044 TT=10PS
+ CJO=117FFVJ=.4 M=.33
+ EG=.69 XTI=3 FC=.5 BV=30)
.MODEL DSUB139 D (CJO=2.12PF VJ=.51 M=.24)
.MODEL PN139 NPN (IS=1.03E-16 BF=113 NF=1.008 VAF=30 IKF=10A
+ ISE=O NE=1 BR=5 NR=1 XCJC=.1 VAR=100
+ IKR=4.4MA ISC=1.22E-16 NC=1 RB=117 RBM=47
+ RE=O RC=8,41
+ CJE=493FF VJE=.9 MJE=,4
+ CJC=244FF VJC=.53 MJC=.37
+ TF=40P XTF=O VTF=100 ITF=96.7MA PTF=O
+ TR=200P XTB=1.51 EG=1.115 XTI=5 FC=0.5)
.MODEL GR139 D (IS=7E-14 RS=10 N=1.044 TT=10PS
CJO=88FF VJ=.4 M=.33
+ EG=.69 XTI=3 FC=.5 BV=30)
.MODEL GRS003 D (IS=4.27E-14 RS=53 N=1.044 TT=10PS
+ CJO=54FF VJ=.4 M=.33
+ EG=.69 XTI=3 FC=.5 BV=30)
.MODEL DSUBS003 D (IS=1E-16 RS=O N=1 TT=500PS
+ CJO=127FF VJ=.51 M=.24
+ EG=1.115 XTI=3 FC=.5 BV=35)
.MODEL DSUB009E D (CJO=106FF VJ=.51 M=.24)
.MODEL PN009E NPN (IS=3.92E-16 BF=113 NF=1.008 VAF=30 IKF=10A
+ ISE=O NE=1 BR=5 NR=1 XCJC=.1 VAR=100
+ IKR=.3MA ISC=4.25E-15 NC=1 RB=185 RBM=39
+ RE=O RC=3.9
+ CJE=1.37PF VJE=.9 MJE=.4
+ CJC=609FF VJC=.53 MJC=.37
+ TF=40P XTF=O VTF=100 ITF=1.64MA PTF=O
+ TR=200P XTB=1.51 EG=1.115 XTI=5 FC=O.5)
.MODEL GR009E D (IS=5.4E-13 RS=9.57 N=1.044 TT=10PS
+ CJO=683FF VJ=.4 M=.33
+ EG=.69 XTI=3 FC=.5 BV=30)

409
.MODEl DSUB108 D (CJ0=163FF VJ=.S1 M=.24)
.MODElPN108 NPN (IS=1.7SE-17 BF=113 NF=1.008 VAF=30 IKF=10A
+ ISE=O NE=1 BR=S NR=1 XCJC=.1 VAR=100
+ IKR=.7SMA ISC=1.9E-16 NC=1 RB=638.8 RBM=222
+ RE=O RC=87
+ CJE=90.6FF VJE=.9 MJE=.4
+ CJC=SO.3FF VJC=.53 MJC=.37
+ TF=40P XTF=O VTF=1 00 ITF=4.1 MA PTF=O
+ TR=200p XTB=1.51 EG=1.115 XTI=5 FC=0.5)
.MODEl W108 D (IS=5.1E-13 RS=58.8 N=1.044 TI=10PS
+ CJO=68.3FF VJ=.4 M=.33
+ EG=.69 XTI=3 FC=.5 BV=30)

Eel Transistor Models

.MODEl TOSI1 NPN
+ IS=21.18E-18 BF=112 BR=5.108 RE=1.S33 IKF=.0213 VAF=41.8
+ ISE=250E-18 RB=52.7 RBM=O IRB=O IKR=53E-S VAR=3.766
+ ISC=9S.62E-18EG=1.11 RC=26.33 NC=1.141 NR=.997
+ CJE=67.7E-15 VJE=1.037 MJE=.5718 NF=1.000 XTI=4.7
+ CJC=99.SE-15 VJC=.603 MJC=.266 NE=2.000 XTB=1.15
+ CJS=152E-15 VJS=.50S2 MJS=.346S TR=9.92E-9 PTF=20
+ TF=35E-12 XTF=2.25 VTF=1.67 ITF=.00808 XCJC=.069 FC=.8
.MODEl TPNP2 PNP
+ IS=7.69E-17 BF=5 BR=1 RB=164 RC=56 CJE=.086E-12
+ CJC=1.4E-12
.MODEl T0811 NPN
+ IS=33.33E-18 BF=114.5 BR=2.029 RE=1.333 IKF=.0336 VAF=42.7
+ ISE=1.0E-15 RB=56.6 RBM=O IRB=O IKR=.115 VAR=3.665
+ ISC=184.7E-18 EG=1.11 RC=22.86 NC=1.085 NR=.995
+ CJE=99.3E-15 VJE=1.037 MJE=.5718 NF=1.000 XTI=4.7
+ CJC=124.4E-15VJC=.603 MJC=.266 NE=2.000 XTB=1.15
+ CJS=170.4E-15 VJS=.5052 MJS=.3465 TR=9.92E-9 PTF=40
+ TF=3SE-12 XTF=2.25 VTF=1.67 ITF=.00808 XCJC=.089 FC=.8
.MODEl T12B1 NPN
+ IS=5.7E-17 BF=113 BR=1.116 RE=1.25 IKF=.0828 VAF=4
+ ISE=2.4E-15 RB=170 RBM=170 IRB=1.7E-3 IKR=.27 VAR=3.6
+ ISC=1.01E-16 EG=1.11 RC=13.3 NC=1.028 NR=1.019 XTI=3
+ CJE=15E-15 VJE=.658 MJE=.273 NF=1.000
+ CJC=27e-15 VJC=.603 MJC=.369 NE=2.000
+ CJS=101E-15 VJS=.429 MJS=.259 TR=5E-9
+ TF=39E-12 XTFf=3 VTF=1.4 ITF=.008 XCJC=.620 FC=.005
.MODEl T5406 NPN
+ IS=3.3E-16 BF=113 RB=86.6 BR=5
+ RC=23.6 RE=.833 CJE=.495E-12 CJC=.722E-12 CJS=.576E-12

Resistor Diode Model

.MODEl RES-DIODE D (IS=1E-16 TI=1NS VJ=.759V M=.333 CJO=50FF)

410
 AN1404

I
ECLinPSTM Circuit Performance
at Non-Standard VIH Levels

Prepared by
Todd Pearson
Eel Applications Engineering

This application note explains the consequences of

driving an ECUnPS device with an input voltage HIGH
level (VIH) which does not me9t the maximum voltage
specified in the ECUnPS Databook.

411
 ECLinPS Circuit Performance at Non-Standard VIH Levels

Introduction VIHmax and the ECLlnPS Family

When interfacing ECLinPS devices to various other As previously mentioned the MOSAIC III'" process allows
technologies times arise where the the input voltages do not for ECLinPS devices to operate at VIHmax levels somewhat
meet the specification limits outlined in the ECLinPS data higher than those specijied in the databook, however the
book. The purpose of this document is to explain the exact value of VIH for which saturation problems will occur
consequences of driving an ECLinPS device with an input varies from device to device and even among different inputs
voltage HIGH level (VIH) which does not meet the maximum for a given device. This variation is a result olthe different input
voltage specijied in the ECLinPS Oatabook. configurations used on the various inputs of ECLinPS
devices.
The results outlined in this document should not be viewed
as guarantees by Motorola but rather as representative The easiest way to define an acceptable VIHmax for each
information from which the reader can base design decisions. device in the family is to define at what point the input transistor
It is up to the reader to assess the risks of implementing the will saturate and specify for each input what the worst case
non-standard interface and deciding ij that level of risk is input transistor collector voltage will be. With this information
acceptable for the system design. Motorola's guarantee on designers will be able to determine on a part by part, input by
VIH will continue to be the specification standards established input basis what input voltage levels will be acceptable fortheir
for the 10HTM and 100K ECl technologies. application.

Simulation Results
Overview
The input saturation phenomenon was characterized
The upper end of the VIH spec of an ECLinPS, or any other through SPICE simulations and the results will be reported in
ECl, input is limited by saturation affects of the input the following text. For simplicity of simulation a buffer similar to
1ransistor. Figure 1 below illustrates a typical ECl input the E122 was used; Since the outputs of this buffer drive off
(excluding pulldown resistors and ESO structures); the chip, the VIHmax performance of this structure will be worse
structure is a basic differential amplijier configuration. With a than the typical input structure. Both a 100K and a 10H style
logic HIGH level asserted at the input the collector of that buffer were analyzed to note any discrepancies between the
transistor will be pulled down below 1he VCC rail by the gate two standards. As expected the simulation results showed no
current passing through the collector load resistor. The difference in the saturation susceptibility of a 100K versus a
voltage at the collector of the input transistor (VC) will be 1OH style buffer. Therefore the simulation results of only the
dependent on the gate current and the size of the collector 1OOK style buffer will be presented to minimize redundancy of
load resistor associated with the input gate. information.
The following text will referto Figures 4-8 in the appendix of
this document. Figures 4-8 are graphical plots of the input and
output waveforms of an E122 style buffer (structure similar to
that of Figure 1) for various VIH levels. V(in) represents the
input voltage while V(q) and V(qb) represent the output
voltages. The V(vbb) line was included for measurement
purposes only and will be ignored.
Vee Figure 4 represents the "standard" operation of the device
as a standard VIH input was used. Note that in this condition
the propagation delays measure in the 215-225ps range and
the IINH was 42.51JA. The IINH of this device is simply a
measure of the base current of the input transistor when that
transistor is conducting current. We will be monitoring both of
these conditions as well as any degradation in the output
Figure 1. Typical ECLlnPS Input Structure waveforms as a sign of the input transistor becoming
saturated. As can be seen in Figures 5 and 6 none of the
As the input VIH increases towards VCC the collector base
parameters change for VIH levels of up to -O.4V. With a
junction olthe input transistor becomes forward biased; as this
collector voltage, VC, of .... t.OV these VIH'S correspond to a
forward bias condition increases the transistor will move into
collector base forward bias of 600mV. As the VIH of the input
the saturation region. The value of VCB at which the transistor
moves closer to V CC, Figures 7 and 8, three phenomena start
begins to saturate is process dependent and will vary from
to occur: the IINH increases, the delays increase and
logic family to logic family. Fortunately the MOSAIC III process
signijicant changes occur to the output low level of the OB pin.
used to implement the ECLinPS family incorporates a deep n+
collector doping. This deep collector helps to mitigate the In Figure 7 the IINH of the input transistor has more than
effects of saturation of transistors by requiring a larger doubled from the "standard" level. This increase in base
collector-base forward bias to enter the saturation region. current leads to an increase in the VOL level as the collector

412
current must reduce to maintain the constant emitter current. belorethey are led into the differential ampl~ier input gate. The
As the collector current reduces, the IR drop across the switching relerence is also shifted down by one diode drop to
collector load resistor reduces, thus raising the VOL level on remain centered in the input swing. Obviously this input
the OB output. A~hough the VOL level has shifted the overall structure will represent the "best case" in the area 01 extended
propagation delay has remained essentially unchanged. VIHmax performance. In lact this type 01 input structure will
allow lor input vo~ages even several hundred millivo~s above
Finally, when the input is switched all the way up to Vec the
the VCC rail. This characteristic makes these type devices
VOL level no longer remains in spec as the input base current ideal lor interfacing with dillerential oscillators whose outputs
has jumped to almost 1ma and there has been sign~icant
lack any DC ollset. In the emitterlollower structure the limiting
degradation in the high-low propagation delay. ~ is apparent
lactor will be the saturation 01 the emitter lollower device
that lor this condition an E122 style buller will not perform
whose collector is at VCC. From the previous simulation
adequately lor most systems.
results this would suggest a maximum VIH 01 +O.6V.
From this inlormation it can be concluded that lor a
collector-base lorward bias 01 S600mV there will be no
adverse conditions on the performance 01 the device. The
performance starts to degrade with lurtherlorward bias until at
a lorward bias vo~age 01 =1.0V the device williail both its De
and AC specilications.
Vss
ECLlnPS Input Structure.
There are lour basic input structures which will allect the
VIHmax performance 01 ECLinPS devices. Thelourstructures
are as lollows: an internal buller, an external buller, an emitter
lollower input buller and a series gated emitter lollower input.
Figure 2. Emitter Follower Input Structure
The internal bullers are input structures whose outputs
drive other gates internal to the device, the vo~age swings 01 The series gate emitter lollower input will represent the
the input transistor collectors (Vel on these devices will be absolute worst case situation for a IOOE device. Figure 3
=800mV. An external buller is one in which the outputs are led represents a series gate emitter lollower input for a I OE and a
external to the chip. Because 01 the relatively large base drive 100E device. From this figure it is apparent that the lower
01 the output emitter lollower lor these structures the Vc switching level (B input levell is going to be much more
voltage will typically be a couple hundred milivo~s lower than susceptible to VIHmax lor the IOOE device than the 10E
lor the internal buller. Note that because 01 the larger output device. The two diode drops used for the 10E device is not
swings 01 alOE device, alOE style external buller will require possible lor a I OOE device due to the smaller VEE voltage 01 a
a VIHmax input level more near the spec~ied value. Both 01 IOOE device.
these structures are similar to that pictured in Figure 1.
To summarize the external gate will represent the worst
The third and lourth structures are somewhat dillerent in case VIHmax situation for a IOE device while the series gate
design than the lirst two. Figure 2 illustrates an emitter emitter follower case will represent worst case for a looE
lollower input structure. For the basicemitterlollower inputthe device. In either situation the standard emitter follower will
input voltages are dropped by an additional VBE (=800mVl allow the most leeway for non-standard VIHmax performance.

InpuIA Vss

Input S
Vss'
Vss"

Figure 3_ Emitter Follower Serle. Gate Input Structure

413
Other Considerations Conclusions
Simulations show that forward bias levels of :s600mVon the
When driving ECLinPS devices with other than standard input transistor will keep the input transistor in the active
input levels there is another phenomena that should be region and the performance of the device will not be
considered; namely effects of non-centered switching compromised. This forward bias voltage can be increased
references on the AC performance of a device. For with varying degrees of performance degradation to levels
non-standard input voltages the midpoint of the voltage swing somewhat higher than 600mV. Initial effects will be an
may not correspond to the internal Vee switching reference. If increase in the IINH current and a decrease in the output VOL
this is the case the resulting AC variation should be included in level on the oe output of the input gate. As the forward bias
the evaluation of a design. increases further the propagation delays through the device
will be adversely affected.
An input voltage swing not centered about the switching The following example will outline the use of the table in the
reference will exhibit a delay skew between the two input edge appendix to analyze the potential performance of a design
transitions. The size of this skew will be dependent on both the using non-standard VIH levels. If a design called for the
voltage offset of the reference voltage and the midpoint of the 10El12 and the 10E416to be driven by a-O.2V input signal a
input swing and the slew rate of the input as it passes through designer would want to know ~ these two devices would
the threshold region. As an example for the case in which the perform to specifications under these conditions. From the
VIH - -O.5V and the VIL remains at -1. 7V the midpoint of the table the worst case collector voltage Vc would be -1.05V and
swing will be at-1.1Vversus a-1.32V Vee reference. With a O.OV respectively. Subtracting these values from -O.2V yields
typical slew rate of 1ps/mV for ECLinPS type edge rates the forward bias voltages of 850mV and -200mV respectively.
rising input edge delay will be 220ps longer than normal and From this information the designer would conclude that the
the falling edge delay will be 220ps faster. This results in a 10E416 will function with no problems however the 10El12
440ps skew between the two input transitions that would not could suffer performance degradation under these same
be seen for an ideal switching reference. conditions.
The device information contained in the appendix of this
The only means of correcting this skew is to lower the VIL document will provide designers with all of the information
level to recenter the swing or provide a different switching necessary to evaluate the input transistor forward bias
reference for the device. The latter can be accomplished by conditions for all of the ECLinPS devices for different input
buffering the signal with a differential input device with one voltages. With these numbers and the information provided in
input tied to an externally generated switching reference. this document designers will be able to make informed
Raising the VIL level is not recommended due to the obvious decisions about their designs to meet the performance
loss of low end noise margin accompanied by any such shift. desired at an acceptable level of risk.

414
 Appendix
Vc (10E Typical) Vc (10E Wor.t c •••) Vc (l00E Typical) Vc (lODE Wor.t c...)
Device Input Input Structur. (V) (V) (V) (V)
E016 All INT -{l.BO -<l.90 -{l.BO -<l.90
El0l All EF -{l.15 -<l.25 -{l.10 -{l.20
El04/107 Dna EXT -{l.95 -1.05 -{l.90 -1.00
Onb SG -{l.SO -<l.60 -1.20 -1.30
El11 All INT -{l.BO -<l.90 -{l.BO -{l.90
E112 On EXT -{l.95 -1.05 -{l.90 -1.00
ENI INT -{l.BO -<l.90 -{l.BO -{l.90
E116 All EXT -<l.95 -1.05 -{l.90 -1.00
E122 All EXT -<l.95 -1.05 -{l.90 -1.00
E131 D INT -{l.90 -1.00 -{l.90 -1.00
Other SG -<l.SO -<l60 -1.20 -1.30
E141 All INT -<l.BO -<l.90 -{l.BO -<l.90
E142 All INT -<l.BO -<l.90 -{l.BO -{l.90
EI43 All INT -{l.BO -<l.90 -{lBO -{l.90
E1SO On EXT -{l.95 . -1.05 -<l.90 -1.00
Other INT -<l.BO -<l90 -<l.BO -<l.90
E151 All INT -<l.BO -<l.90 -{l.BO -<l.90
EI54 All INT -{l.BO -<l.90 -{lBO -<l.90
EI55 All INT -<l.BO -<l.90 -{l.BO -{l.90
EI56 All INT -{l.BO -<l.90 -{l.BO -<l.90
E157 On EXT -<l.95 -1.05 -{l.90 -1.00
SEl INT -<l.BO -<l.90 -{l.BO -{l.90
EI58 On EXT -<l.95 -1.05 -{l.90 -1.00
SEl INT -<l.BO -<l.90 -<l.BO -<l90
EI60 R,elK SG -<l.SO -<l.60 -1.20 -1.30
Other INT -<l.BO -<l.90 -{l.BO -{l.90
EI63 All INT -{l.BO -<l.90 -<l.BO -<l.90
EI64 All INT -<l.BO -<l.90 -{l.80 -{l.90
EI66 All INT -<l.BO -<l.90 -{l.BO -{l.90
E167 All INT -<l.BO -<l.90 -<l.BO -{l.90
E171 All INT -<l.BO -<l.90 -{l.BO -<l.90
E175 All INT -<l.BO -<l.90 -<l.BO -{l.90
EI95 All INT -<l.BO -<l.90 -{l.BO -<l90
EI96 All INT -<l.BO -<l.90 -{l.80 -{l.90
E212 All INT -{l.BO -<l.90 -{l.BO -{l90
E241 All INT -{l.BO -<l.90 -{l.BO -<l.90
E256 All INT -{l.BO -<l.90 -{l.BO -<l.90
E336 All INT -<l.BO -<l.90 -<l.BO -{l.90
E337 All INT -<l.BO -<l.90 -<l.BO -<l90
E404 All EF 0.00 0.00 0.00 0.00
E416 All EF 0.00 0.00 0.00 0.00
E431 All INT -<l.BO -<l.90 -{l.BO -{l.90
E451 All INT -<l.BO -<l90 -{l.BO -{l.90
E452 All INT -<l.BO -<l.90 -{l.BO -{l.90
E457 On EF 0.00 0.00 0.00 0.00
SEl INT -{l.SO -<l.90 -<l.BO -{l.90
INT = Internal Gate; EXT = External Gate; EF = Emitter Follower Input; SG = Senes Gated Input

415
 -0.25

---V(IN)
~
-0.5
- - - - V(O)
- -V(08)
-0.75
- - - - V(VB8)
-

..,
w
-1.0
V /',,-
/'
'"
\"\ /'
~ -1.25
~
-1.5
--;:1-------
l
I

----\X----- --- I

V--- / I \ " - - - - /I~,

-1.75

-2.0
---- --- .............. _--

-2.25
o 2000 4000

TIME

Figure 4. Input and Output Waveforms for VIH -4.9 =

(VOl- -1.8; TpD++ - 215ps; Tpo- - - 225ps; IINH - 42.51!A)

-0.0

---V(IN)
-0.25 -
- - - - V(O)
- -V(08)
-0.5 -

-0.75
[ \ - - - V(VB8)

w
~ / .~
~
>
-1.0
'I / /" \\ I
",

-1.25
-1-)( -------- -----'\'1------ 1----

-1.5

-1.75
LI- I
/'\.
...
- -
/'\\...
---- ----
-2.0
o 2000 4000

TIME
Figure 5. Input and Output Waveforms for VIH -4.5 =
(VOl- -1.8; TPD++ ~ 204ps; Tpo- - - 207ps; IINH - 43.41!A)

416
 -0.0

- - - V(tI)
-0.25 -
- - - - V(O)
--V(QB)
-0.5
/ "\. -
/ \
- - - - V(VBB)

-0.75

w
/ ~
'"
!:j
§2
-1.0
'i / /' \'\ ,/

-1.25

-1.5
-txt -------- I-----\~-----
I
:----

J / _--- \
I\\~
-1.75

-2.0
-- I '\.
...... t----
./
---- ----
o 2000 4000

TIME
Figure 6. Input and Output Waveforms for VIH -C.4 =
(VOL - -1.8; TPD++ - 201ps; TPo-- = 206ps; IINH - 46.7J.LA)

-0.0

- - - V(IN)
-0.25 I--
- - - - V(O)

-0.5
( \ - - V(QB)
t--

/ \
- - - - V(VBB)

-0.75
w
~
!j -1.0
/ - ------ ~---- \
§2
X '\\
/
/"
I
/"

-1.25

-t~t:--------1-----\\,----
I
1----

-1.5

-1.75
J/
\

\- X\ ---- ----
-2.0
-- "'
'\.
'V'
)
o 2000 4000

TIME

Figure 7. Input and Output Waveforms for VIH = -C.3

(VOL = -1.8; TPD++ - 196ps; TPo-- - 198ps; IINH - 114.8I1A)

417
 -0.0

--V(IN)
-0.25 I--------,f---------+----\--------t ____ V(Q)

- -V(OB)
-0.5 1------jf---------+---~r------__1 ____ V(VBB)

-0.75

w
CI ."".------
~ -1.0
~ /'
-1.25
~-------

-1.5
~
v------\
-1.75
\ J
-2.0
0 2000 4000

TIME
=
Figure 8. Input and Output Waveforms for VIH 0.0
(VOL - -1.8; TPD++ - 196ps; Tpo- - - 287ps; IINH - 912"A)

418
 AN1405

I
ECL Clock Distribution
Techniques

Pr9paredby
Todd Pearson
EeL Applications Engin99ring

This application not9 provid9s information on syst9m

d9sign using ECL logic tschnologi9s for reducing
syst9m clock Sk9W OV9r th9 alt9rnativ9 CMOS and TTL
tschno/ogi9s.

419
 ECl Clock Distribution Techniques

INTRODUCTION lor TIL and CMOS devices. Because 01 the near zero duty
cycle skew 01 a differential ECl device the output-to-output
The ever increasing performance requirements oltoday's
skew will generally be larger. The output-to-output skew is
systems has placed an even greater emphasis on the design
important in systems where either a single device can provide
01 low skew clock generation and distribution networks. Clock
all 01 the necessary clocks or lor the lirst level device 01 a
skew, the difference in time between ·simultaneous· clock
nested clock distribution tree. In these two situations the only
transitions within a system, is a major component 01 the
parameter 01 importance will be the relative position 01 each
constraints which lorm the upper bound lor the system clock
output with respect to the other outputs on that die. Since
Irequency. Reductions in system clock skew allow designers
these outputs will all seethe same environmental and process
to increase the performance 01 their designs without having to
conditions the skew will be signfficantly less than the
resort to more complicated architectures or more costly, laster
propagation delay windows specilied in the standard device
logic. ECliogic technologies offer a number 01 advantages lor
data sheet.
reducing system clock skew over the aiternative CMOS and
TIL technologies.
IN--""/
SKEW DEFINmONS
The skew introduced by logic devices can be divided into OUTa -----;::~-----
three parts: duty cycle skew, output-to-output skew and
OUTb----
part-to-part skew. Depending on the specilic application, each
01 the three components can be 01 equal or overriding
importance. OUTc ----+-+. . . . ,
OUTPUT·TO-OUTl'llT SKEW
Duty Cycle Skew
The duty cycle skew is a measure 01 the difference between Figure 2. Output-to-Output Skew
the TPLH and TPHl propagation delays (Rgure 1). Because
differences in TPlH and TPHL will resuit in pulse width
distortion the duty cycle skew is sometimes relerred to as Part-to-Part Skew
pulse skew. Duty cycle skew is important in applications
The part-to-part skew specilication is by lar the most difficuit
where timing operations occur on both edges or when the duty
performance aspect 01 a device to minimize. Because the
cycle 01 the clock signal is critical. The later is a common
part-to-part skew is dependent on both process variations and
requirement when driving the clock inputs 01 advanced
variations in the environment the resultant specffication is
microprocessors.
significantly larger than lor the other two components 01 skew.
Many times a vendor will provide subsets 01 part-to-part skew
specffications based on non-varying environmental
conditions. Care should be taken in reading data sheets to
lully understand the conditions under which the specified
limits are guaranteed. lithe part-to-part skew is specified and
is different than the specified propagation delay window lor the
device one can be assured there are constraints on the
part-to-part skew specification.
PWlo

Power supply and temperature variations are major

contributors to variations in propagation delays 01 silioon
Figure 1. Duty Cycle Skew devices. Constraints on these two parameters are commonly
seen in part-to-part skew specilications. Although there are
situations where the power supply variations could be ignored,
Output·\o-Output Skew
it is difficult lor this author to perceive 01 a realistic system
Output-to-output skew is defined as the difference between whose devices are all under identical thermal conditions. Hot
the propagation delays 01 all the outputs 01 a device. A key spots on boards or cabinets, interruption in air llow and
constraint on this measurement is the requirement that the variations in IC density 01 a board all lead to thermal gradients
output transitions are identical, therelore il the skew between within a system. These thermal gradients will guarantee that
all edges produced by a device is important the devices in various parts 01 the system are under different
output-to-output skew would need to be added to the duty junction temperature conditions. Aithough it is unlikely that a
cycle skew to get the total system skew. Typically the designer will need the entire commercial temperature range, a
output-to-output skew will be smaller than the duty cycle skew portion 01 this range will need to be considered. Therelore, a

420
part-to-part skew specified for a single temperature is of little inherent differences between the TpLH and TPHl delays in
use, especially n the temperature coefficient of the add~ion to the problems w~h non-centered sw~hing
propagation delay is relatively large. thresholds. In devices specnically designed to minimize this
parameter ~ generally cannot be guaranteed to anything less
For designs whose clock distribution networks lie on a than Ins.
single board which utilizes power and ground planes an The major contributors to output-to-output skew is IC layout
assumption of non-varying power supplies would be a valid and package choice. Differences in internal paths and paths
assumption and a specification lim~ for a single power supply through the package generally can be minimized regardless of
would be valuable. H, however, various pieces of the total the silicon technology utilized at the die level, therefore ECl
distribution tree will be on different boards w~hin a system devices offer less of an advantage in this area than for other
there is a very real possibil~that each device will see different skew parameters. CMOS and TTL output performance is tied
power supply levels. In this case a sp$Cification lim~ for a fixed closely to the power supply levels and the stabil~ of the power
VCC will be inadequateforthedesign of the system. Ideally the busses w~hin the chip. Clock distribution trees by definition
data sheets for clock distribution devices should include always sw~ch simu~aneously, thus creating signHicant
information which will allow designers to tailor the skew disturbances on the internal power busses. To alleviate this
specnications of the device to their application environment. problem mu~iple power and ground pins are utilized on TTL
and CMOS clock distribution devices. However even w~h this
strategy TTL and CMOS clock distribution devices are lim~ed
SYSTEM ADVANTAGES OF Eel to SOOps - 700ps output-to-output skew guarantees. With
differential ECloutputs very little Hany noise is generated and
coupled onto the internal power supplies. This coupled with
Skew Reductions the faster propagation delays of the output buffers produces
output-to-output skews on ECl clock chips as low as SOps.
ECl devices provide superior performance in all three
areas of skew over their TTL or CMOS competitors. A skew Two aspects of ECl clock devices will lead to signnicantly
reducing mechanism common to all skew parameters is the smaller part-to-part skews than their CMOS and TTL
compet~ors: faster propagation delays and delay insens~ivity
faster propagation delays of ECl devices. Since, to some
extent, all skew represent a percentage of the typical delays to environmental variations. Variations in propagation delays
faster delays will usually mean smaller skews. ECl devices, with process are typically going to be based on a percentage
especially clock distribution devices, can be operated in e~her of the typical delay of the device. Assuming this percentage is
single-ended or differential modes. To minimize the skew of going to be approximately equivalent between ECl, TTL and
these devices the differential mode of operation should be CMOS processes, the faster the device the smaller the delay
used, however even in the single-ended mode the skew variations. Because state-of-the-art ECl devices are at least S
performance will be signnicantly better than for CMOS or times faster than TTL and CMOS devices, the expected delay
TTL drivers. variation would be one fifth thosa of CMOS and TTL devices
without even considering environmental dependencies.
The propagation delays 01 an ECl device are insens~ive to
variations in power supply while CMOS and TTL device
propagation delays vary signnicantly with changes in this
parameter. Across temperature the percentage variation for
ooT_ _ _,,,; all technologies is comparable, however, again the faster
propagation delays 01 ECl will reduce the magn~ude of the
variation. Figure 4 on the following page represents
-----DELAYIo normalized propagation delay versus temperature and power
- - - - DELAYnom supply for the three technologies.

Figure 3. Vaa Induced Duty Cycle Skew

low Impedance line Driving
ECl output buffers inherently show very little difference
between TplH and TpHl delays. What differences one does The clock requirements 01 today's systems necessitate an
see are due mainly to switching reference levels which are not almost exclusive use 01 controlled impedance interconnect. In
ideally centered in the input swing (see Figure 3). For worst the past this requirement was unique to the performance
case sw~ching reference levels the pulse skew of an ECl levels associated with ECl technologies, and in fact
device will still be less than 300ps. H the ECl device is used precluded ~s use in all but the highest performance systems.
differentially the variation in the sw~ching reference will not However the high performance CMOS and TTL clock
impact the duty cycle skew as it is not used. In this case the distribution chips now require care in the design and layout 01
pulse skew will be less than SOps and can generally be ignored PC boards to optimize their performance, w~h this criteria
in all but the highest performance deSigns. The problem of established the migration from these technologies to ECl is
generating clocks which are capable of meeting the duty cycle simplnied. In fact, the difficu~ies involved in designing with
requirements of the most advanced microprocessors, would these ·slower" technologies in a controlled impedance
be a trivial task n differential ECl compatible clock inputs were environment may even enhance the potential of using ECl
used. TTL and CMOS clock drivers on the other hand have devices as they are ideally su~ed to the task.

421
 1.05 1.20
1.04
~
I1 1.03
1.02
1.01
1:01

( 1.15

~
~
Q
1.00 I!l 1.10
z z:
g 0.99 g
tc 0.98
tc
~
~
1.05

~
0.97
0.96
0.95
0.94 0.98 1.02 1.06 1.10 20 .w 60 80 100
POWER SUPPI.y (NORMAlIZED) lEMPERATURE (C~

Figure 4. TPD va environmental Condition Comparison

The low impedance outputs and high impedance inputs of It is true that dWferential interconnect requires more signals
an ECl device are ideal for driving son to 130n controlled to be routed on the PC board. Fortunately with the wide data
impedance transmission lines. The specWied driving and address buses of today's designs the clock lines
impedance of ECl is son, however this value is used only for represent a small fraction of the total interconnect. The final
convenience sake due to the son impedance of most choice as to whether or not to use differential interconnect lies
commonly used measurement equipment. Utilizing higher in the level of skew performance necessary for the design. It
impedance lines will reduce the power dissipated by the should be noted that although single-ended ECl provides less
termination resistors and thus should be considered in power attractive skew performance than differential ECl, it does
sensitive designs. The major drawback of higher impedance provide signWicantly better performance than equivalent
lines (delays more dependent on capacitive loading) may not CMOS and TTL functions.
be an issue in the point to point interconnect scheme generally
used in low skew clock distribution designs. o Q

Dlfferentlallntarconnec:t

The device skew minimization aspects of dWferential ECl

have already been discussed however there are other system
o Q
level advantages that should be mentioned. Whenever clock ClKb
lines are distributed over long distances the losses in the line
and the variations in power supply upset the ideal relationship
between input voltages and switching thresholds. Because
differential interconnect "carries· the switching threshold
information from the source to the load the relationship
between the two is less likely to be changed. In addition for CLKa
long lines the smaller swings of an ECl device produce much CLKb
lower levels of cross-talk between adjacent lines and
minimizes EMI radiation from the PC board.
There is a cost associated with fully dWferential ECl, more Figure 5.1800 Shifted Two Pha. . Clocka
pins for equivalent functions and more interconnect to be laid
on a typically already crowded PC board. The first issue is
USING ECl WITH POSlTlVE SUPPUES
really a non-issue for clock distribution devices. The
output-ta-output and duty cycle skew are very much It is hard to argue with the clock distribution advantages of
dependent on quiet internal power supplies. Therefore the ECl presented thus far, but it may be argued that except for all
pins sacrWiced for the complimentary outputs would otherwise ECl designs it is too costly to include ECl devices in the
have to be used as power supply pins, thus functionality is distribution tree. This claim is based on the assumption that at
actually gained for an equivalent pin count as the inversion leasttwo extra power supplies are required; the negative VEE
function is also available on a dWferential device. The supply and the negative Vrr termination voltage. Fortunately
presence of the inverted signal could be invaluable for a both these assumptions are false. PECl (Positive ECl) is an
design which clocks both off the positive and negative edges. acronym which describes using ECl devices with a positive
Figure 5 shows a method of obtaining very low skew (<SOps) rather than negative power supply. II is important to
1800 shWted two phase clocks. understand that all ECl devices are also PECl devices. By

422
using ECL devices as PECL devices on a +5 volt supply and problem of generating runt pulses when an asynchronous
inoorporating termination techniques which do not require a disable is used. The device also provides a muxed clock input
separate termination voltage (series termination, thevenin for incorporating a high speed system clock and a lower speed
equivalent) ECL can be incorporated in a CMOS or TIL test or scan clock within the same distribution tree. The
design whh no added cost. EClinPS E111 device is used to receive the signals from the
The reason for the choice of negative power supplies as backplane and distribute it on the card. The worst case skew
standard for ECL is due to the fact that all of the output levels between all 54 clocks in this shuation would be 275ps
and internal swhching bias levels are referenced to the VCC assuming that all the loads and signal traces are equalized.
rail. It is generaUy easier to keep the grounds quieter and equal
potential throughout a system than it is whh a power supply.
Becausethe DCparametersarereferencedtothe Vccrail any
disturbances or voltage drops seen on VCC willtranslate1:1to
the output and internal reference levels. For this reason when
communicating whh PECL between two bollrds it is
recommended that only differential interconnect be used. By
using dillerential interconnect VCC variations whhin the
specified range will not in any way affect the performance of
the device.
Finally mentioning ECL to a CMOS designer invariably
conjures up visions of space heaters as their perception of
ECL is high power. A~hough h is true that the static power of
ECL is higher than for CMOS the dynamic power dillerencel'
between the technologies narrows as the frequency
increases. As can be seen in Figure 6 at frequencies as low as
20MHz the per gate power of ECL is actually less than for
CMOS. Since clock distribution devices are never static it Figure 7. EeL Clock Distribution Tree
does not make sense to compare the power dissipation of the
two technologies in a static environment.
Mixed Technology Distribution Networks
20.-------------~
Building clock networks in TIL and CMOS systems can be
a little more complicated as there are more a~ernatives
15 available. For simple one level distribution trees fanout
devices like the MECL 10H645 1:9 TTL to TTL fanout tree can
be used. However as the number of levels offanout increases
the addition of EeL devices in an other wise TTL or CMOS
system becomes attractive. In Figure 8 on the next page an
E111 device is combined with a MECL H641 device to produce
81 TTL level clocks. Analyzing the skew between the 81
clocks yields a worst case skew, allowing for the full
temperature and VCC range variation, of 1.25ns. Under ideal
situations, no variation in temperature or VCC supply, the skew
would be only 750ps. When compared with distribution trees
utilizing only TTL or CMOS technologies these numbers
represent ..s0% improvement, more if the environmental
FREQUENCY (MHz)
conditions vary to any degree. For a 50MHz clock the total
Figure 6. ICC/Gate vs Frequency Comparison skew between the 81 TTL clocks is less than 6.5% olthe clock
period, thus providing the designer extra margin for layout
induced skew to meet the overall skew budget of the design.
MIXED SIGNAL CLOCK DISTRIBUTION Many designers have already realized the benefits of ECL
clock distribution trees and thus are implementing them in
their designs. Funhermore where they have the capability, I.e.
ECl Clock Distribution Networks ASICs, they are building their VLSI circuits with Eel
compatible clock inputs. Unfonunately other standard VLSI
Clock distribution in a ECL system is a relatively trivial circuits such as microprocessors, microprocessor suppon
matter. Figure 7 illustrates a two level clock distribution tree chips and memory still cling to TIL or CMOS clock inputs. As a
which produces nine dillerential ECL clocks on six different resun many systems need both EeL and TTL clocks within the
cards. The EClinPS E211 device gives the flexibility of same system. Unlike the situation outlined in Figure 8 the ECL
disabling each of the cards individually. In addition the levels are not merely intermediate signals but rather are
synchronous registered enables will disable the device only driving the clock inputs of the logic. As a resun the EeL edges
when the clock is already in the LOW state, thus avoiding the need to be matched with the TTL edges as pictured in Figure 9.

423
 used. The value of the delay element would be a best guess
estimate of the differences in the two propagation delays. It is
highly unlikely that the temperature coefficients of the
propagation delays of the ECL devices, TTL devices and
delay devices would be equal. Although these problems will
add skew to the system, the resultant total skew of the
distribution network will be less than H no ECL chips
were used.

Pll Based Clock Drivers

A potential solution for the problem outlined in Figure 9 is in
the use of phase locked loop based clock distribution chips.
Because these devices feedback an output and lock it to a
reference clock input the delay differences between the
various technology output buffers will be eliminated. One
might believe that with all of the euphoria surrounding the
performance of PLL based clock distribution devices that the
need for any ECL in the distribution tree will be eliminated.
However when analyzed further the opposite appears to be
Figure 8. ECl to TTL Clock Distribution
the case.
For a single board design with a one level distribution
system there obviously is no need for ECL. When, however, a
multiple board system is required where nested levels of
devices are needed ECL once again becomes useful. One
major aspect of part-to-part skew for PLL based clock chips
often overlooked is the dependence on the skew of the various
reference clocks being locked to. As can be seen in Figure 10
the specified part-to-part skew of the device would necessarily
need to be added to the reference clock skew to get the overall
skew of the clock tree. From the arguments presented earlier
this skew will be minimized Hthe reference clock is distributed
in ECL. It has not been shown as of yet where a PLL based
ECL clock distribution chip can provide the skew performance
of the simple fanout buffer. From a system standpoint the
buffer type circuits are much easier to design with and thus
given equivalent performance would represent the best
alternative. The extra features provided by PLL based chips
could all be realized Hthey were used in only the final stage of
the distribution tree.
Unfortunately none of the PLL based devices available
Figure 9. Mixed ECl and TTL Distribution today feature differential ECL compatible reference clock
inputs. Look for BiCMOS based PLL clock devices from
An ECL clock driver will be significantly faster than a TTL or Motorola in the near future. There will be a family of devices
CMOS equivalentfunction. Therefore to de-skew the ECL and featuring various technology compatible inputs and outputs to
TTL signals of Figure 9 a delay needs to be added to the input allow for the building of precisely aligned clock trees based on
of the ECL device. Because a dynamic delay adjust would not either ECL, TTL or CMOS (or a mixture of all three)
lend itseH to most production machines a static delay would be compatible levels.

424
 Conclusion
The best way to maximIZe the performance of any
synchronous system is to spend the entire clock period
REFb---.... performing value added operations. Obviously any portion of
the clock period spent idle due to clock skew lim~s the
potential performance of the system. Using EeL technology
devices in clock distribution networks will minimize all aspects
of skew and thus maximize the performance of a system.
Unfortunately the VlSI world is nof yet Eel clock based so
0UTa
that the benef~s of a totally Eel based distribution tree cannot
be realized for many systems. However there are methods of
incorporating Eel into the intermediate levels of the tree to
significantly reduce the overall skew. In addition the system
_ DEVICE SKEW rz.zzJ SYSTEM SKEW designers can utilize their new found knowledge to
incorporate Eel compatible clocks on those VlSI chips of
which they have control while at the same time pressuring
other VlSI vendors in doing the same so that future designs
Figure 10. System Skew For PLL Clock Distribution can enjoy fully the advantages of distributing clocks with EeL.

425
426
 EB27A
Get 300 watts PEP Linear
Across 2 to 30MHz from this
Push·Pull Amplifier

(The heat sink shown with amplifier is sufficient only for short test periods under forced air cooling.)

This bulletin supplies sufficient infonnation to build a Because of its excellent load and line voltage regulating
push-pull linear amplifier for 300 watts of PEP or CW capabilities, an integrated circuit bias regulator is used
output power across the 2- to 30-MHz band. One of in the amplifier. The MPCIOOO, originally described in
Motorola's new high-power transistors developed for this bulletin, consisted of a MCI723 chip and a built-in
single-sideband, MRF422, is used in this application. pass transistor. The manufacture of this device has been
discontinued however, and the' board lay-out was mod-
Like all transistors in its family of devices, MRF422 ified to incorporate the above two in separate packages.
combines single-chip construction that is advancing the The load regulation typically measures less than 2% at
state-of-the-art, and improved packaging to accommo- current levels up to 0.5 A, which assumes an hFE of 40
date the low collector efficiencies encountered in class for the RF power devices. The board surface provides
B operation. Rated maximum output power is 150 watts a sufficient heat sink for the 2N5990 pass transistor, but
CW or PEP with intennodulation distortion spec'd at a separate heat dissipator, such as Thennalloy 6107 can
- 30 dB maximum, - 33 dB typical. Although not rec- be added if necessary. With the component values
ommended, a saturated power level of 240- to 250-W shown, the bias is adjustable from 0.4 to 0.8 volts.
is achievable. Maximum allowable dissipation is 300 W
at 25°C.

427
 The effective base-to-base impedance, increased by the
RC networks is about 5 ohms at midband. As a result
of this and the 9: I impedance ratio in the input trans-
former Tl, the input VSWR is limited to 1.9:1 or less
across the band. Transformer T2, in addition to providing
a source for the feedback and carrying the dc collector
current, acts as the rf center tap of the output transformer.
To construct T2, wind 5 turns of 2 twisted pairs of AWG
No. 22 enameled wire on a Stackpole 57-9322 toroid
(Indiana General F627-8QI).

Vee ~ 28 v POUT a lOO W PEP

Transformer Construction
---
Gain flatness over the band is achieved using base input
networks R IC 2 and R2C 3 and negative feedback through
R3 and R4. The networks represent a series reactance of
20
0.69 ohms at 30 MHz rising to 1.48 ohms at 2 MHz. FREOUENCY (MHz)

A single-turn winding in the collector choke provides a Figure 1 - Collector Efficiency.

low-impedance negative feedback source, thus R3 and Power Gain and VSWR vs Frequency
R4 determine the amount. The reactance of C4 reduces A Stackpole dual balun ferrite core 57-1845-248 is used
feedback at high frequencies with the result that feedback for Tl. The secondary is made of W' copper braid,
increases an average of 4 dB per octave at decreasing through which three turns of the primary winding (No.
frequency. 22 Teflon@ insulated hook-up wire) are threaded. The
construction of T3 is similar to that of T I. It employs
For continuous operation at full power CW, It IS rec- two Stackpole 57-3238* ferrite sleeves which are ce-
ommended that heat sink compound, such as Dow Corn- mented together for easier construction. The primary is
ing #340, be applied between the board surface and R3 made' of 'I'" copper braid, through which three turns of
and R4, and if possible have air circulating over the top No. 16 Teflon@ insulated wire are threaded for the
of the circuit board as well. secondary.

" "
caD
C

E Q, )(

R3~ 14 e16

OPt::~.1
r'H~8' 1: 1 ~~ R~
Input
Atten

uator
l t.~'"
~:.. ~

fii-C::::l- g~.
Al1~j 0 OAB
T1 ..J \3'
Q3

0R5
.
<8>
@
Terminal Pins and
Feedthroughs
Feedthrough Eyelets.
Stand Off's

©
. "'0 MC'n,3C
A. B.

428
 C2

3OO-Watt Un..r Amplifier Schematic Diagram

'" ••, .on

j OJ'
-
Tl

:
TC:~[1-
c5U'L_
I: ---0 Output 50n

vcc+ R5
.rCl
-=-
C7 ~

R8

MC1723G

4
,2

3
I C15

R9
RIO
VCC -

Mounted To R11
Heatsink --....

Cl - 100 pF R 1, R2 - 2 X 3.3n, 1/2 W in parallel aI, 02 - MRF422, 03 - 2N5990

C2, C3 - 5600 pF R3. R4 - 2 X 3.9 fl, 1/2 W in parallel Tl. T2. T3 - See text
C4, C5 - 680 pF R5-47n,5W
C6, C7 - 0.101'F RS - 1.0n, 112 W All capacitors except electrolytlcs end C16
C11 - 470 pF R7, R8 - 1.0 k,1I2 W are chips -
C12, C13 - 0,331'F R9 - 18 k, 112 W
C14 - 10 J.l.F - 50 V electrolytic A 10 - 8.2 k, 1/2 W Union Carbide type 1813 and 1225,
C15 - 5QOJ.l.F - 3 V electrolytic R1l - 1,0 k Trimpot or Varadyne size 18 or 14, or equivalent
CIS - 1000 pF 01 - 2N5190
Ll. L2 - Ferroxcube
VK20020/48
Table I. Output harmonic contents,
L3, L4 - 6 ferrite beads measured at 300-W CW (all test data
each, Ferroxcube taken using a tuned output, narrow
5659065/38 band signal source).
For production quantities, the braid in T, may be made 2nd 3rd 4th 5th
of brass or copper tubes with their ends soldered to pieces f (Mhz) (dB below the carrier)
of PC board laminate. See cover picture and Motorola
AN-749 for details. 30,0 -38 -25 -34 -48

The bandwidth characteristics of these transformers do 20.0 -33 -13 -43 -45
not equal those of the transmission line type, but they're 15,0 -50 -10 -51 -47
much easier to duplicate.
7.50 -40 -30 -55 -47
The measured performance of the amplifier is shown
in figures I, 2, and 3 and harmonic rejection data in 4,0 -37 -22 -55 -37
table I. 2.0 -36 -18 -45 -37
*A similar product is available from Fair-Rite Products Corp., Wallkill, N.Y., 12589

®Registered trademark of DuPont

PCB, chips capacitors, transformers T T~, T" and ferrite beads are available from:
"
COMMUNICATIONS CONCEPTS, 2648 N. Aragon Ave., Kettering, Ohio 45420.
Telephone: (513) 294-8425.

429
 1 Figure
2 3 - 3 IMD v s Power Output
4
5

430
 EB29
The Common Emitter TO·39
and its Advantages

The common emitter T0-39 package is one of Motorola's

latest innovations in low-{;ost rf packages. It differs from Two important advantages can be derived from the
conventional TO-39's or TO-5's in that the emitter, not common emitter TO-39: By connecting the case to the
the collector, is connected to the metal casco To achieve rf circuit ground, emitter inductance is reduced and gain
this, a BeO insulating block metallized on top and bot- increased by 3 to 5 dB over that of comparable, conven-
tom is brazed to the can bottom and the transistor chip tionally wired transistors. And the case may be directly
brazed to the BeO insulator. Wires are then bonded from pressed, clipped, or soldered to the heat sink with no
the chip and insulator block to the terminals and the can effect on rf performance. This feature may eliminate the
bottom as shown in the photo. With NPN transistors, need for the heat radiating "coolers" because soldering
this configuration permits direct connection of the can the transistor bottom to the circuit, typically a PC
to rf and negative dc ground for many class Band C board, improves dissipation by removing heat through
circuits. the thick metal base rather than the thin can.

431
 Fixture for Functional Testing of the Common Emitter TO-39

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A B.B9 9.40 0.350 0.370
B B.OO B.51 0.315 0.335
C 6.10 6.60 0.240 0.260
D 0.406 0.533 0.016 0.021
E 0.229 3.1B 0.009 0.125
F 0.406 0.4B3 0.016 0.019
G 4.83 5.33 0.190 0.210
H 0.711 0.B64 0.028 0.034
J 0.737 1.02 0.029 0.040
K 12.70 0.500
L 6.35 0.250
M 45' NOM 45' NOM
P 1.27 0.050
Q 90' NOM 90' NOM
R 2.54 - 0.100 -
All JEDEC dimensions and notes apply. STYLE 5:
CASE 79-02 PIN 1. COLLECTOR
T0-39 2. BASE
3. EMITTER

For example, the MRF227 was mounted in this manner find the CE-T039 offers a real advantage from the elimi-
and a 8jc of I SOC/W was measured using a Barnes RM-2A nation of interstage RFI or coupling because the can is
Infrarea Microscope_ Compared to an MRF607 in a at rf ground. Stability is usually improved and the higher
conventional package operating under identical condi- available gain may reduce the number of transmitter
tions, this is greater than a 2: I reduction in thermal stages. Simplified and improved cooling may also be
resistance_ And as side benefits, the lower 8jc also re- obtained by connecting the can directly to the radio
duces power slump and improves reliability_ housing or chassis.

In many mobile radios CE-T039 devices can replace stud To sum it up: The emitter-to-can wired TO-39 known
or flange mounted stripline parts used for 1- to 4-watt as the CE-T039 offers the designer significant improve-
drivers. This conversion should normally offer a signifi- ments in both gain and thermal performance. Because of
cant savings in the cost of parts as well as the costs of its price, compared to SOE and T0-60 packages, the
mounting hardware and labor. designer can use the CE-T039 to reduce costs. And he
can make his design easier to assemble with no loss in
The designer of compact handheld radio equipment will rf performance.

432
 EB59
Predict Frequency Accuracy for
MC12060 and MC12061 Crystal
Oscillator Circuits

Crystal oscillators are used when it is necessary to gener- Crystals used with MC 12060/61 devices must meet the
ate a precise and highly stable signal. Such circuits typi- requirements specified in their data sheet. Since these
cally provide this stable signal at a frequency close to devices oscillate at the frequency that provides the low-
the resonant frequency (either parallel or series) of their est impedance (series resonance) between pins 5 and 6, a
crystal. However, circuit components and other factors crystal must not exhibit a spurious response resulting in
external to the crystal influence the crystal's natural impedance values near or less than the desired series
resonance to some degree, an effect often referred to as resonance impedance. In the evaluations discussed here,
"pulling" or "warping." A discussion of the variation in standard commercial crystals with ±0.0025% calibration
crystal frequency as a function of differing lCs·, temper- tolerance, fundamental mode, were used with the
ature, and dc supply voltage is presented in this bulletin MC 12060/61 devices. Measured series resonance fre-
to aid the designer in predicting the amount of fre- quencies for the crystals used, along with equivalent
quency pull in his particular design. series inductance (LS) and resistance (RS) values are
presented in Table 1.
Crystal Characteristics
·Specifically, the Motorola MC 12060/12560 and
As shown by the equivalent circuit of Figure I, crystals MC12061/12561 integrated circuits which are designed
behave as open circuits to dc. For ac signals below a for use with an external fundamental series resonant
crystal's series resonant frequency, the crystal exhibits crystal. Specified operating frequency range is 100 kHz
a capacitive reactance. As frequency increases, the series to 2 MHz for the 12060/12560 and 2 MHz to 20 MHz
resonance of Cs and LS is reached. The crystal then ap- for the 12061/12561. Complementary sine wave, com-
pears as a low value resistor, RS, shunted by a small
capacitance, CO. At frequencies above series resonance, TABLE I
the CS, LS combination appears as an inductive react- Crystal Parameters
ance. As frequency increases even higher, the inductive Series Equiv. Series Equiv. Series
reactance grows eventually equalling the capacitive re- Resonant Frequency Resistance RS Inductance LS
actance of CO. This is the high impedance, parallel reso- (MHz) (Ohms) (mH)
nant frequency for the crystal. Although the separation
in frequency between series and parallel resonance varies 2.500025 38.0 274.0
for different crystals, series resonance will typically 8.079977 8.4 17.6
occur several hundred Hertz to a few kilohertz below 13.411100 6.9 7.0
parallel resonance. 18.749563 12.5 2.9
19.999528 9.2 -
(kHz)
100.002 497 -
200.Q12 509 -
500.031 995 9857
999.985 380 2629
FIGURE 1 - Crvstal Equivalent Circuit
2000.032 96 526

433
plementary ECL, and single ended TTL outputs are MHz. Table III shows the variation in pull on the same
available. Complete technical specifications for these crystal resulting from the use of different MC 12060 and
ICs can be found on the device data sheet. Additional MC 12061 devices.
applications information is available in Motorola appli-
cation note AN-756 and engineering bulletin EB-60.

MC12060/61 Performance Figure 3 gives the frequency shift, ,/:aused by the

MC 12560/61 devices operating over their temperature
The circuit elements in an oscillator environment have range of -55°C to +125°C. Similar resultS can be ex-
an effect on the fundamental resonant frequency of a pected for the MC 12060/61 devices over their specified
crystal. To measure the influence of the MC12060/61 range of O°C to +75°C. Data was taken with the crystals
devices, tests were made using the circuit of Figure 2. at a constant temperature of approximately +25°C to
Frequency measurements were taken at the sine wave isolate the effect of temperature on the ICs. Since the
output (pin 2 or pin 3), the 680 ohm resistor making it curves are normalized, one must add the appropriate
possible to drive a 50 ohm load. Laboratory quantities room temperature value (see Table II) to obtain the net
of the ICs were tested, consequently some variation in frequency pull at a specific temperature. For example,
results could be expected if a production run cross sec- the MC12561 device operating with the nominal 8.08
tion were evaluated. MHz crystal would exhibit a net pull of approximately

VCC = 5.0 Vdc

UNLESS OTHERWISE NOTED

=f O,01I'F

UNUSED PINS
9THROUGH 16
D.U.T.
ARE CONNECTED
TO GROUND 680n

6 8

FIGURE 2 - MC12060/61 , MC12560/61

Evaluation Circuit

The measured pull of the MC12060/61 devices on a -40 - 11 = - 51 PPM at +125°C. The curves show a
crystal's series resonant frequency is shown in Table II small temperature dependence at lower frequencies that
for room temperature operation. Resonant frequency is increases significantly above midband. Although not
always reduced, the effect becoming more pronounced plotted, over the -55°C to +85°C range MC12560 at 2
with increasing operating frequency. Where minimum MHz and MC12561 at 18.75 MHz changed from +155 to
pull is required, the MC 12061 rather than the MC 12060 -275 and from +7 to -45 PPM respectively, referenced
should be considered for use at or slightly below 2.0 to +25°C.

TABLE II
Crystal Frequency Pullin Percent For MC12060/61 IC's
DEVICE MC12060 MC12061
NOMINAL CRYSTAL 0.100 0.200 0.500 1.00 2.00 2.50 8.08 13.41 18.75 20.0
FREQUENCY (MHz)
CRYSTAL PULL IN
PERCENT
. -0.0005 -0.0012 -0.0040 -0.03 -0.0002 -0.004 -0.01 -0.03 -0.05

'LESS THAN 1 Hz, MEASUREMENT LIMITED BY RESOLUTION OF TEST EQUIPMENT.

434
 TABLE III pacitor and its effect on increasing frequency. Therefore,
_ ... FrequencY Dwl8tlon From DlYloo to 0 ..100 if only a small increase in frequency is required, the trim
MC12060 capacitor value may become unreasonably large. To
assure a suitable value for the capacitor, it may be neces-
NOMINAL FREQUENCY
(MHz)
0.100
0.200
..
FREQUENCY DEVIATION
(Hz) (PPM)
.. sary to specify the crystal frequency lower than the
actual desired operating frequency. The pulling effect of
0.500 2 4.0 the ICs will normally be much less than that of the trim
1.000 10 10.0 capacitor and therefore the crystal can simply be speci-
2.000 165 82.5 fied such that the series combination of crystal and trim
MCI2061 capacitor is in series resonance at the desired operating
2.50 2 0.8 frequency. If it is also desired to account for the effects
B.08 110 13.6
13.41 485 36.2
of the ICs, this may be approximated by considering the
lB.75 1755 93.6 MCI2060 to add 266 pH and the MCI2061 1.6 pH in
-Less than 1 Hz, Measurement limited by resolution of test series with the crystal.
equipment. As a typical example, assume that the MC12061 is to be

10 .....
.......
............. ."C'
,,~
-9'0
~.f~
o
....
--
~
~

"' r"...
~
MCI2561 • 2 •0 MHz -

~C',..~
"- ~~~Oe.-
"\. ~~ ..
"
-10

"-"-,
NOTES:
1. NO MEASURABLE CHANGE -55·C TO +125·C FOR MC12560 OPERATING

-20
AT 100 kHz. TEST EQUIPMENT RESOLUTION <1 Hz.
2. FREQUENCY SHIFT BECOMES SIGNIF ICANTLY WORSE WHEN DEVICES
ARE OPERATED ABOVE MID-FREQUENCY RANGE. "'"-
-100 -50
I I

o
TEMPERATURE. ·C
50
I

100 "' 130

FIGURE 3 - Frequency Shift VS Temp. with Crystal

Located Outside Temp. Chamber

Figure 4 provides plots of frequency pull as a function used with a nominal 8 MHz crystal having an equivalent
of change in dc supply for the MC 12060/61 devices. series inductance LS = 17.6 mHo Figure 5 shows the
equivalent circuit. With no CTRIM added, the IC will
Design Example
lower the crystal's resonant frequency by approXimately
The ICs are designed to pull the crystal's natural series
resonant frequency lower . .If desired, this permits a trim
JC17.6 + 0.0016)/17.6 or 0.0045%. Use of a 10 pF trim
capacitor would place a net impedance in series with the
capacitor to be inserted in series with the crystal to set
crystal of jwLIC - j l/wCTRIM = -j 1.909 X 103 . This
the oscillator "on frequency". Since this trim capacitor
corresponds to an equivalent capacitance in series with
is approximately in series with Cs of the crystal, there is
I
an inverse relationship between the value of the trim ca- the crystal of CEQUIV = 21T X 8 X 106 x 1.909 x 103 -

435
 20

10 41 .. 0 FOR MC12061 OPERATING WITH 2.5 MHz CRYSTAL AND VDC

CHANGED '10%.

::;
l>-
I>-
0
~
<i

-10
MC12061 AT 18.7 MHz

-20

4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0

SUPPLY VOLTAGE IN VOLTS

FIGURE 4 - MC12060/61 Frequency Shilt Versus

DC Supply Voltage Value

Co is assumed negligible at the frequency of series resonance for the crystal.

FIGURE 5 - Crystal/Ie Oscillator Equivalent Circuit

10.42 pF. The crystal should be specified so that the requiring an undesirably large value of 247 pF. The
crystal reactance and that of CEQUIY are in series reso- CTRIM value can approach infinity if the crystal cali-
nance at the operating frequency (8.000 MHz). In effect, bration tolerance allows the crystal to be series resonant
this requires a crystal with a series resonance slightly on the high side of 8 MHz.
below 8.000 MHz so that at precisely 8.000 MHz it pre- A similar procedure can be followed for the MC 12060
sents a +j impedance which equals the -j impedance sup- device. In this case the approximation LIC = 266 /lH is
plied by CTRIM in series with LIC, i.e., CEQUIY. used. The calculated frequency pull for the nominal 500
kHz, 1 MHz and 2 MHz crystals described in Table I is
If the crystal is not resonant below 8 MHz as suggested, then -0.0013, -0.0051 and -0.0253 percent respec-
but rather at exactly 8 MHz, CTRIM must then be tively. This agrees closely with the measured values of
chosen to resonate with an LIC inductance of 1.6 /lH -0.0012, -0.0040, and -0.03 percent given in Table II.

436
 EB77
A 60 watt 225·400MHz Amplifier
- 2N6439

This bulletin describes a 60 watt, 28 volt broadband a dc blocking capacitor, and is followed by another 4: I
amplifier covering the 225 -400 MHz military com- impedance ratio coaxial transformer.
munications band. The amplifier may be used singly as a Collector decoupJing is accomplished through the use
60 watt output stage in a 225 -400 MHz transmitter, or by ofD, L4, C14 through CI6 and Rl.
using two of these amplifiers combined with quadrature
couplers, a 100 watt output amplifier stage may be con- Construction
structed. Typical performance curves of gain, efficiency, The circuit is constructed on a 3.375 X 2.5 inch (8.57
and input SWR are shown in Figures 5, 6, and 7. X 6.35 cm) double sided PC board. Board material is
3M Glass Teflon*, with a thickness of 0.031 inch (0_0787
Circuit Description cm). Glass Teflon was selected for its low loss and dielec-
This circuit is designed to be driven from a 50 ohm tric consistency. Figure 2 is a I: I photomaster print of
source and work into a nominal 50 ohm load. The input the top side of the board. Eyelets are placed at the points
network consists of two microstrip L-sections composed marked by a plus sign to carry the top ground to the
of ZI, Z2 and C2 through C6. CI serves as a dc blocking bottom side ground return. The edges of the transistor
capacitor. A 4:1 impedance ratio coaxial transformer Tl mounting hole beneath the emitter leads are also wrapped,
completes the input matching network. L1 and ferrite using copper foil soldered in place to insure a solid emitter
bead serve as a base decoupling choke. ground.(i,2) Construction details of the 4:1 transformers
The output circuit consists of shunt inductor L2 at are shown in Figure 4.
the collector, followed by two microstrip L-sections
composed of Z3, Z4 and C8 through C II. C12 serves as *Registered Trademark of Dupont

+ + + + + +
IJ

+ + + +
0 + "t-

O
2N6439 GAIN BLOCK DSH

FIGURE 1 - Component Layout of the Amplifier FIGURE 2 - Photo master (not full size)

437
 Rl
.---ic-:::-'>-.....J't:-':'''-+.......",ic=''---o +
L3 l14 .J:,.C16 1 28 Vdc

RF~-rrfl ZI
'" l"1J ~ "II"
All Chip Capacitors are 100 mil TOK-ACI Co,
Cl - 63 pF Chip Z1 - Microstrip Line
Stvle FC282 BAG
C2, CS - 27 pF Chip 800 mils L X 225 mils W
L 1 - 0.15,uH Molded Choke with Ferroxcube
C3' - 24 pF Chip 20.32 mm LX 5,715 mm W
Bead #56·590-65/48 on ground end of coil
C4 - 15 pF Chip Z2 - Microstrip Line
L2 - 1 Turn #22 AWG. l/S" 10
C5, C9 - 30 pF Chip 200 mils L X 225 mils W
L3 - 0.' 5 ",H Molded Choke
C6, C7 - 50 pF Chip 5.08 mm L X 5.715 mm W
L4 - Ferroxcube VK-200-19/48
Cl0-10pF Chip 23, 24 - M icrostrip Line
ell - 5,1 pF Chip Ql - 2N6439 550 mils L X 125 mils W
C12 - 150 pF Chip 13.97 mm LX 3.175 mm W
Rl - 10.0 2 Watt
el3 - 270 pF Chip
Board - 0.03'" (0.787 mm) Glass Teflon
C14, C16 - 680 pF Feedthru T1, T2 - 25 n Subminiature Coax (Type UT25) t'r = 2.56
C15 - 1.0 ",F 50 V Tantalum 2.25 inches (57.15 mm) long

FIGURE 3 - 2N6439 60 Watt Building Block 225-400 MHz

SCHEMATIC REPRESENTATION

"""ill""·'"
A B

ASSEMBLY AND PICTORIAL

1f--------0 ---j-----l®I
Ii' Transformer
\!..J (not to scale)
D;mens;~,+t=.------------"!'S
-----cL ! - -

0- 2,25 inches (5.715 cm)

o- 0.1875 inch (0.476 cm)

o Transformer Connections

-=s 50n

FIGURE 4 - Construction Details of the 4:1 Unbalanced to Unbalanced Transformers

438
 AMPLIFIER PERFORMANCE

FIGURE 5 - Power Gain versus Frequency

Efficiency versus Frequency FIGURE 6 - Output P_ _ venus Input Power
10 9 80
VCC=28V VCC"28V

,...
Pout=60W
80 60
'"
/'
" r-
GpE /'" 1
S
~
~

~
Ii?
40
. / ~4OOMH'
V
=225 11Hz
"' • .... f
/
~
6 20
./
50 J 10
V
o ./
250 300 350 400 o 10
I, FREQUENCY (MH.) ".,. INPUT POWER (WAITSJ

FIGURE 7 - Input VSWR ....... Freq_ncy

V
"- - " "-
I

250 300 350 400

f. FREQUENCY (MHz)

439
 FIGURE 8 - Amplifier Assombly

Bibliography
I. "Mounting Stripline - Opposed Emitter (SOE) Transis-
tors," Motorola Application Note AN·555, Motorola
Semiconductor Products Inc., Phoenix, Arizona.
2. Glenn Young, "Microstrip Design Techniques for UHF
Amplifiers," Motorola Application Note AN-548A,
Motorola Semiconductor Products Inc., Phoenix, Arizona.
3. Roy Hejhall, "Systemizing RF Power Amplifier Design,"
Motorola Application Note AN-282A, Motorola Semicon-
ductor Products Inc., Phoenix, Arizona.

NOTE: A 10 Watt 225 -400 MHz Amplifier-MRF331 is

described in Engineering Bulletin EB-74.

440
 E889

A 1 watt, 2.3GHz Amplifier

Introduction
Simplicity and repeatability are featured in this
l-watt S-band amplifier design_ The design uses aI)
MRF200I transistor as a common base, Class C ampli-
fier. The amplifier delivers I-watt output with 8 dB
minimum gain at24 V, and is tunable from 2.25 to 2.35
GRz. Applications include microwave communica-
tions equipment and other systems requiring medium
power, narrow band amplification. A photograph of
the amplifier is shown in Figure 1.

Circuit Description
The amplifier circuitry consists almost entirely of
distributed microstrip elements. A total of six addi-
tional components, including the MRF2001, are
required to build a working amplifier. Refer to Figure 2
for the schematic diagram of the amplifier.

FIGURE 1 - 1-W. 2.3 GHz Amplifier

r-----~---4~--__---------------_< ~~~VdC

Z9 Z10

RF RF
Input Output

Cl - 0.4-2.5 pf Johanson 7285· Board Material - 0.0625" 3M Glass Teflon .. ••

C2, C3 - 68 pF, 50 mil ATe'" f"r ::: 2.5 ± 0.05
C4 - 0.1 "F. 50 V • Johanson Manufacturing Corp., 400 Rockaway Valley Road, Boonton, NJ 07005
C5 - 4.7 ~F, 50 V Tantalum •• American Technical Ceramics, One Norden Lane, Huntington Station, NY 11746
... ·Registered Trademark of Du Pont
Z1-Z10 - Microstrip; see Photomaster, Figure 3

FIGURE 2 - Schematic Diagram

441
 The input and output impedances of the transistor Amplifier Assembly
are matched to 50 ohms by double section low pass The circuit boards are mounted on a 3.125" x 1.875"
networks. The networks are designed to provide about x 0.750" aluminum block. A 0.062" deep and 0.260"
3% 1 dB power bandwidth while maintaining a collec· wide slot is milled in the heat sink as shown in
tor efficiency of approximately 30%. There is one Figure 4.
tuning adjustment in the amplifier - C1 in the output The transistor mounts in the slot with two 4·40
network. Ceramic chip capacitors, C2 and C3, are used screws. An alternate approach that would eliminate
for DC blocking and power supply decoupling. Addi- the need for milling is the laminated structure shown
tionallow frequency decoupling is provided by capac· in Figure 5.
itors C4 and C5. Refer to Figure 3 for a 1: 1 photomaster
of the circuit boards. Using the laminated assembly, the transistor is
mounted on the surface of the block and 0.062" alumi·
num shim stock is sandwiched between the block and
the circuit boards. Connector mounting plates are
required if SMA type connectors are used for the RF
input and output. The SMA connectors can be fastened
directly to the block if the milled approach is used.
Either method results in the same performance for this
1·watt design. The laminated structure, however, may
not be suitable for higher power designs. With higher

r
power levels the transistor impedances are lower. The
RF ground impedance through the laminated metal
may be sufficiently high to impair gain and stability.
This point emphasizes the fact that the successful
design of RF amplifiers is dependent not only on atten·
tion to electrical considerations, but to the physical
_.,niUM,,',' 'MM construction as well. While construction related para-
sitics cannot be totally ignored at medium frequencies,
00" 0.5" 10" they can pose serious problems at microwave
Lu.ulLWJ frequencies. It is recommended that the following con·
struction techniques be followed when building this
amplifier. Refer to Figure 6 for the component
FIGURE 3 - Circuit Photomaster placement diagram.

--1.875

~A ~ ~ ~A --1.675 Material - Aluminum

A All dimenSIOns in inches
A B

-~- $ -[- _--1.218 A - Board Mounting Holes, Tap 2-56 8 Places

-J- -~-
$ ---0.658 B- DevIce Mounting Holes, Tap 4-40 2 Places
B
C- Mounting Holes for SMA Type Connectors. Tap 2-56 4 Places
~A '17A ~ ~A --0200
A
0.000

I I 22~ 11~31 I
2875 1.960 1.450 0250
I
3125 1.700 0.000
0.000 0.770 1.110 1 875

I I I- -
I.-m------rrro 0000
- - 0.083

FIGURE 4 - Amplifier Heat Sink

442
 Circuit Board

"."0." '"'""~ --1:;;"'

_I
AlumInum Block
' '1 rmamnOd:~+_ SMA Extended
Dielectric Connector
Connector
Mounting Plate

FIGURE 5 - Laminated Assembly

C4 C3 C5

1\1. Foil Wrap Asterisked Edges to Bottom Ground Plane

FIGURE 6 - Assembly Diagram

Construction Notes The boards can now be fastened to the heat sink and
1. The transistor is fastened to the heat sink with the remaining components mounted.
two 4-40 screws. The mounting surface should be flat 4. Use a minimum of heat when soldering C2 and
and clean. Thermal compound should not be used on C3. Excess heat could cause the end metal of the chip
the underside of this device; the flange provides the capacitor to separate from the ceramic.
transistor base connection and must make good elec· 5. C1 is a miniature variable capacitor whose
trical contact with the heat sink. The wide lead is the high self-resonant frequency makes it ideal for use at
emitter and the narrow lead is the collector. microwave frequencies. The package design makes it
2. The edges of the boards marked with an aster- very convenient to use wherever a shunt capacitive
isk (see Figure 6) must be foil wrapped to the bottom element is de&:red and is used here to vary the capaci-
ground plane to provide a low impedance RF ground tance of microstrip stub, Z5. The capacitor is mounted
connection for C3, C4, C5 and the emitter choke, Z9. by drilling a 0.120" diameter hole (#31 drill bit) at the
This is accomplished by soldering a l!4"·wide strip of point indicated in Figure 6. Using the circuit board as
1- to 5-mil thick copper foil to the top ground plane and a template, mark the point on the heat sink directly
then wrapping it around the edge of the board. The below the mounting hole. Since the capacitor is
other edge of the foil is soldered to the bottom ground slightly longer than the thickness of the board, a
plane. clearance hole is needed at this point. The bottom of
3. Use a #31 drill bit to drill the board mounting the capacitor is soldered to the ground plane on the
holes. With the transistor already mounted to the heat bottom of the board. The flange of the capacitor is
sink, slide the boards into position so they butt up soldered to Z5. Avoid getting solder into the area above
against the transistor. This will insure that the excess the flange as this will prevent the movement of the
lead inductance of the transistor is kept to a minimum. tuning piston.

443
 FIGURE 7 - Performance Curv..

Performance Data

- ~lGHZ
Amplifier tune-up is accomplished by adjusting Cl
Vee = 24Vdc
for maximum output power with minimum collector 1.4
current. The amplifier will tune from 2.25 to 2.35 GHz
~ 1.3

--- --
while maintaining an input VSWR of less than 2:1. ~
Typical performance curves appear in Figure 7. ~ V ~OGHZ
1.2
'"~

-- -
Figures 7a and 7b show performance with the
amplifier re-tuned for each frequency. Figure 7c ./
V V f- 2.35 GHz
...~ 1.1
shows performance without re·tuning. Note from
Figure 7c that the instantaneous 1 dB bandwidth is ...~=> 1.0
V ....... V V
approximately 70 MHz with the amplifier tuned to a
center frequency of 2.3 GHz.
0

0.9
V V
~Q
.......
0.8 /"

80 100 120 140 160

P;n.INPUT POWER (mW)

FIGURE 7a - Output Power versus Input Power

1.4
Vec = 24 Vdc ~
Pill '" 150mW 2.is GHz PDut
1.2 ~
P;n=IS~~,...

--
1.5 :;:;
-"""t-...
g 1.4 V ....-2.iOGHz ~
... 1.0 I'-..
U

ffi
......... V ~

--
35
I
--
0.8
~ V

--
n i'....
1.3 ....-2.3 SGHZ
'"~ '"
0
'"~
~
1.2
...--- V f-""
...~
0.6
0.4 V"" r- "
..........
30
25 ~
... ............ ....... ~ ........
--
~ 20
:3
~=> 1.1
........ V =>
0
0'
0
, 1.0 ,
~

........ .;' 3;1 ~

.;' .........
r-
0.9

20 24 28 2.25
- 2.30
VSWR

2.35
>
2;1 ~
1:1 !:

Vec. SUPPLY VOLTAGE (VOLTS) f. FREQUENCY (GHz)

FIGURE 7b - Output Power verlul Supply Voltaga FIGURE 7c - Output Power, Efficiency and
VSWR versus Frequency

NOTE: The MRF2001 is one of a family of 2 GHz power transistors with RF

output powers as indicated below:
MRF2001 1 W MRF2005 5 W
MRF2003 3 W MRF2010 10 W

444
 EB90

Low Cost VHF Amplifier Has

Broadband Performance

Introduction
This bulletin presents two VHF amplifier designs packages). The MRF260 and MRF262 are in a
intended for FM or CW service in the 136-174 MHz standard TO-220 silicone epoxy case with the emitter
band. Both amplifiers feature the Motorola MRF260 wired to the metal tab and center lead of the device.
and MRF262 plastic encased VHF transitors which This common emitter configuration results in good
are rated at 5.0 Wand 15 W power output respectively. RF performance, improved thermal conductivity,
This new series is derived from a line of highly and ease of mounting in an RF amplifier, by con-
successful device types of similar capability, but necting the transistor mounting flange to RF and
packaged in a standard configuration, (i.e., stripline DC ground.

FIGURE 1 - Engineering Models. A Common Board Layout is Used for Both Versions

445
Design Considerations
The lower frequencies (136-160 MHz) are serviced At frequencies beyond 100 MHz, dipped silver mica
by a design utilizing low-cost dipped silver mica capacitors generally become inductive, and do so
capacitors_ For a broadband response in the higher with a high degree of unpredictability. This
frequencies; (160-174 MHz), low inductance, ceramic phenomenon is also dependent upon component
chip capacitors are used_ value and becomes more pronounced with an
Ease of assembly, repeatability and fast economi- increase in frequency_ (Ref: 1, 2, 3). To maintain
cal construction received the utmost consideration predictable performance beyond 160 MHz, a second
in the design of this amplifier_ TO-220 devices layout featuring ceramic chip capacitors is offered
result in a low profile circuit which minimizes the (Figure 3, 6, 7)_ The design ofthese capacitors allows
volume occupied by the amplifier_ Additionally, the them to remain capacitive beyond the VHF frequen-
MRF262 transistor used in the output stage is a cies. Maintaining the bandwidth of 160-174 MHz
rugged device, able to tolerate high load SWR with this circuit board, the networks become lossy
conditions_ Maximum use of printed inductors and power output suffers slightly. Variable
assures good repeatability. capacitors may make this condition more tolerable
Both amplifiers utilize stagger tuned networks to and can be installed in the input and interstage
enhance bandwidth. Additionally, each design networks. In some cases the ease of adjustment and
retains excellent gain and stability characteristics added flexibility would justify the added cost of
when narrow banded. All of these merits are the variable capacitors.
attributed to optimum device gain and the Performance
reasonably high inter-stage impedance levels Normally, this amplifier will not require tuning
incurred at these power levels. provided that components are as described and are
positioned as shown on Figure 5 and 7. If an accurate
Circuit Description method of measuring power is available, a quick
The amplifier has two stages and uses 5.0 Wand check of amplifier performance can be accomplished
15 W rated transistors to accomplish the desired by comparing its parameters with the performance
gain and power output. Two stage transmission line data of Figures 8 through 11. Drive must be
Chebyshev networks accomplish coupling and maintained at 220 m W (±20 m W)and VCC held to 12.5
impedance transformation at the input and output. V dc to accurately reproduce the overall response
Nominal impedance levels are 50 ohms, while the noted here. Allow some degree of tolerance (10%) in
interstage network transforms device impedances output power to account for differences inherent in
directly. Values for the reactive elements of these component values and transistor performance. To
networks were almost entirely generated by assure broadband performance and tailored
computer aided design. Although the interstage frequency response, the amplifier should be checked
network is straight forward in design, it required using a swept frequency generator capable of
some modification and refinement of computer 200-300 m W output. Tuning for maximum power out
generated values to achieve the final results and and minimum reflected power at band centers will
accomodate available component values. not necessarily provide a broadband response.
Figures 8 through 11 graphically depict typicallevels
Construction of performance achieved with this amplifier. Either
The amplifier is assembled on double-sided G-10 version is stable into higher than 3:1 VSWR load
fiberglass board with 1 oz. copper cladding. The mismatch at all phase angles. The output device is
format is 2.0" x 3.5" and a photomask is provided tolerant of short term operation into an open or short
(Figure 13). Some method of electrically connecting circuit load at full drive.
the upper and lower ground plane is required. Eye- Harmonic content of a 150 MHz signal at the out-
lets or plated through holes are recommended, but put ofthe dipped silver mica version is illustrated in
alternative measures such as short pieces of wire Figure 12. The 2nd harmonic is approximately -50 dB
soldered to both planes can be used successfully. with respect to the fundamental. This level of
Failure to provide an adequate or consistent ground performance cannot be maintained across the entire
plane may result in poor RF performance, instability, band, therefore, some additional filtering of the
and unpredictable tuning. The reverse side of the output signal will be required to meet more stringent
board retains all copper and forms the ground plane. requirements.
Component placement and the recommended With the amplifier mounted on aluminum stock,
position of grounding eyelets is shown in Figures 13, 2.0" x 8.5" and 0.090" thick, a 25% duty cycle (1 min on,
5, and 7. All component leads are positioned and 4 min off) produced a temperature of 50 0 e (122°F)
soldered above the board. There are no through after two hours of operation. A 50% duty cycle (1 min
connections other than grounding points. This on, 1 min off) raised this temperature to 60 0 e (140°F)
facilitates component positioning, replacement, and full key down operation caused a stabilized
and access ability. The transistors are fitted into a temperature of80oe (176°F). All temperatures were
0.4" by 0.65" opening in the board and are installed measured on the heat sink at the final device with
directly against the heat sink. A coating of heat output power maintained at 15 watts. One can safely
sink compound such as Dow Corning 340 between assume that a panel on the outside edge (i.e., back-
each device and the heat sink improves thermal side) of a transceiver could be successfully used as a
contact and helps prevent power slump. heat sink for this amplifier.

446
References
1. Hatchett, John: 25 Watt and 10 Watt VHF Marine
Band Transmitters, AN-595, Motorola Semi-
conductor Products, Inc_
2_ Granberg, H: A Simplified Approach to VHF
Power Amplifier Design, AN-791, Motorola
Semiconductor Products, Inc_
3. Hollander, D: A 15 Watt AM Aircraft Transmitter
Power Amplifier Using Low Cost Plastic Tran-
sistors, AN-793, Motorola Semiconductor
Products, Inc.

FIGURE 2 - 136-160 MHz Amplifier

FIGURE 3 - 160-174 MHz Amplifier

447
 RFC6 RFC5
+
::;J;C12

C8~ L5 Cll
r-4-~~~~~~~~
L3

-=
C4
1I -= -=
C6
C71:
lRFc2

-=-=
II
rr
FIGURE 4 - Schematic Diagram of Dipped Silvered Mica Capacitor Version '136-160 MHz)

~ -1L....-----1
+12,5Vdc

RFC6

~
F
L4
:: Output .
u .
L1 CtO

Cl - 200 pF Cl0- 22 pF 02 - MRF262

C2 - 33 pF Cll-l00pF RFC1, RFC2 - 2 Turns #26 Enameled
C3 - 47 pF C12 - 1.0 /LF Tan1alum on Ferrite 8ead Ferroxcube 56-590-65/38
C4 - 18 pF C13, C14 - 0.05 I'F Erie Redcap RFC3 - 10 I'H Molded Choke
C5, C8 - 43 pF L1-L5 - Printed Inductor RFC4 - 0.15 I'H Molded Choke
C6 - 12 pF L3 - 1.25" #18 AWG, 1-1/2 Turns, 9/6410 RFC5, RFC6 - VK200-4B
C7, C9 - 50 pF 01 - MRF260 8 - Bead, Ferroxcube 56-590-65/38

FIGURE 5 - Component Placement, 136-160 MHz Amplifier

448
 RFC5 RFC6

L5 C8
,-~~~~~~~~r<

FIGURE 6 - Schematic Diagram of Chip Capacitor Version (160-174 MHz)

rr
12.5 Vdc

~
B

L1
RF~RFC4 L4
RF
Output

§]~ L3
L5
EL
~
~

T
L2
~
RF

~
Input
5/8'" Hairpin
loop, #18 AWG

Cl - 220 pF, TDK 100 mil Chip Capacitor L1-L5 - Printed Inductor
C2 - 43 pF, TDK 100 mil Chip Capacitor L3 - 5/8" .t18 AWG Wire formed into hairpin loop
C3 - 150 pF, TDK 100 mil Chip Capacitor Ql - MRF260
C4 - 15 pF, TDK 100 mil Chip Capacitor Q2 - MRF262
C5 - 63 pF, TDK 100 mil Chip Capacitor RFC1, RFC2 - 2 Turns #26 Enameled Wire
C6 - 27 pF, TDK 100 mil Chip Capacitor through Ferrite Bead Ferroxcube 56-590-65/38
C7 - 22 pF. TDK 100 mil Chip Capacitor RFC3 - 0.15 /'H Molded Choke
C8 - 100 pF, TDK 100 mil Chip Capacitor RFC4 - 10 /,H Molded Choke
C9 - 1.0 /,F Tantalum RFC5, RFC6 - VK200-48
Cl0 - 0.1 /,F Erie Redcap, 100 V General Purpose 8 - 8ead, Ferroxcube 56-590-65/38
Cll - 0.05 /'F Erie Redcap, 100 V General Purpose

FIGURE 7 - Component Placement, 160-174 MHz Amplifier

449
 FIGURE 8 - Power Output versus Frequency. FIGURE 9 - Power Output versus Frequency.
136-160 MHz Amplifier 160-174 MHz Amplifier

18 18

I:: 1
-
-
16
r--

- ...--
..... f.--
......... ~ 14
~
~ 12
~
...- 12
10 ~
~ 10
>- <>
~ 8.0 ~ 8.0
Pin = 220 mW
<> 6.0
'i;
~~C;}12~5m: - - ~ 6.0 VCC=12.5V - -
~4.0 } 4.0
2.0 2.0

136 140 144 148 152 156 160 160 162 164 166 168 170 172 174
f. FREQUENCY IMHz) f. FREQUENCY IMHz)
FIGURE 10 - Power Gain and Input VSWR FIGURE 11 - Power Gain and Input VSWR.
versus Frequency, 136-160 MHz Amplifier versus Frequency 160-174 MHz Amplifier

r-- P~u)15 ~ c- Pout; 13.5 W

Pin; 220 mW Pin; 220 mW
r-- VCC; 12.5 V c-

--
VCC; 12.5 V
19.0 18.5
~ 18.5
~
r-..... ~ 18.0
.- r--
;i V r-.... Z ~
C1 18.0 3.5 ;;: 17.5
.--- 3.5
i -
to
17.5 3.0 ~ ~ 17.0 k-' 3.0 ~
~ 17.0
~ 16.5
-- - - ..-
2.5 '"
2.0
~ ~ 16.5

~ ~'" 16.0 - --
2.5
'"
...
~

2.0 !!!
16.0
'-
136 140 144 148 152 156 160
1.5 15.5
160
- 162
-
164
-
166
-f-
168 170 172 174
1.5
f. FREQUENCY 1M Hz) f. FREQUENCY (MHz)

FIGURE 12 - Output Spectrum

136-160 MHz Model FIGURE 13 - PCB Photomasler (nol full size)

.[
Pout ;15W
J
-10
-20 VCC; 12.5 V

-30
ill
-40
-50
-60
-70

fo 2fo 3fo Note: Grounding eyelet locations Scale; 1:1

150 300 450 are indicated by dots.
f. FREQUENCY 1M Hz)

450
 EB93
60 watt VHF Amplifier Uses
Splitting/Combining Techniques

Using proven combining techniques to obtain are minimized. The exotic materials or expensive
higher output power or added reliability at VHF can be board layout required to produce a true push·pull
accomplished with excellent results. Simple matching design operating at VHF again makes combining
networks and power transistors featuring moderate techniques more appealing.
gain capability can produce a level of performance This 60 W amplifier operates from 150 to 175 MHz
comparable to that of a single-stage amplifier using and features two, low·cost Motorola MRF264 transis·
a larger, more expensive device. Though not the tors. These devices are designed for operation at VHF
ultimate answer in VHF amplifier design, the splitter! and individually produce 30 watts of rated output
combiner method does have distinct advantages over power and 6.0 dB of gain with a 12.5 volt supply. The
designs that brute force the transistors into a parallel amplifier design makes use of a modified Wilkinson
configuration. Current hogging and reduced imped. combiner technique to produce 60 watts output with a
ance level problems associated with that technique drive level of 15 watts.

FIGURE 1 - Engineering Model

451
Design Considerations turns (closewound) on a temporary 118 inch form and
Experimental work with 90° (quadrature) couplers then separating the individual turns by 0.020 inch. An
proved unsuitable for this application. Generally, they Xacto number 11 knife blade was used for this purpose
are sensitive to mismatch and tend to create instability and provides the correct turns spacing. The 10().ohm
and loss of power when used in an amplifier. In·phase isolation resistors, Rl and R2, must be noninductive
(Wilkinson) couplers provide an adequate solution to and carbon composition resistors proved to be entirely
this problem. (Ref: 1) They are relatively insensitive adequate. In a properly tuned and balanced amplifier
to phase changes and offer good bandwidth these resistors should remain fairly cool to the touch
characteristics. during normal operation. Each amplifier and coupler
Printed transmission lines for the frequency of input and output port is designed to be terminated into
interest can become somewhat cumbersome on 5().ohms to facilitate testing into a 5().ohm system.
standard circuit board material. Therefore, lumped A PCB bridge (Figures 3 and 9) is used to carry all
reactances (Ll, 2, 9, 10 and C1, 2, 3,14, 15, 16, Figure 5) of the dc feed circuitry. It acts as a continuation of the
are used to simulate 70.7 ohm 114 wave transmission ground plane and enhances circuit stability. Solid
lines, the main element in the couplers. This approach copper (0.027 inch) and double·sided circuit board
not only conserves board space, but provides a means were used as a construction medium and no difference
to compensate for small variations in associated in performance was noted with either material.
component values. Initial alignment is accomplished by driving the
Microstrip techniques are incorporated in the amplifier with a 5 watt CW source at approximately
amplifier networks to balance RF performance and 160 MHz. The applied voltage is set at 12.5 volts and
promote reproducibility. Because of the lower circu· the variable capacitors, C4 and C5, are adjusted in an
lating currents and reduced component heating in alternating manner to provide maximum output power.
the collector circuitry of low·powered stages, smaller Full drive (15 watts) is then applied and the capacitor
capacitors can be used in the networks at that point adjustments are repeated. At this point, the circuitry
than would be required for a single-ended 60 watt should be delivering 60 watts or more to the 5().ohm
design. Separating the major heat producing devices load with the 15 watts input. After the final adjust·
to two areas on the heatsink produces a more even ments are made, the isolation resistor temperature in
heat transfer to the ambient air. The combined ampli· either coupler should be relatively cool to the touch and
fier presented here has good harmonic suppression the input VSWR should be at a minimum. Best results
(Figure 8). A low·pass filtering effect is noticeable with will be obtained if the transistors are beta matched
the Wilkinson combiners. (±10%) prior to installing them in the circuit.

Construction and Alignment Additional Comments

A 1:1 photomask of the circuit is provided in Figure 9 This amplifier has been extensively tested for rug·
and double-sided G·10 fiberglass board with two·ounce gedness and reproducibility. The 15 watt input level
copper cladding is recommended for construction. The makes it compatible with the EB·90 two-stage VHF
ground points are indicated on the PCB photomask. amplifier as a driver. Together they form a chain
The inductors required for the splitter/combiner requiring 200 mW of input power for a 60 watt or
are constructed by winding the appropriate num ber of more output.

References
1. Lawrence R. Laveller; "Two Phased Transistors 2. Ernest J. Wilkinson; "An N·Way Hybrid Power
Shortchange Class C Amps," Microwaves, Pg. 48- Divider," PGM TT Transactions, pg. 116-118,
54, February, 1978. January, 1960.

452
 FIGURE 2 - Amplifier Layout - Top View

FIGURE 3 - Component Placement

LB +12.5 V Input L7

a. Output Side b. Base Side

FIGURE 4 - PCB Bridge Details

453
 Cl, C16 - 25 pF Unelco (Jl0l) Ll, L2 - 7 Turns #18, 0.125"10
C2, C3 -15 pF CM04 Mica L3, L4, L5, L6 - Printed Inductors
C4, C5 - 68 pF Standex L7, L8 - Printed Inductors
C6, C7 - Arco 404 Variable L9, Ll0 - 7 Turns #18 AWG, 0.12510
C8, C9 - 150 pF Standex Lll, L12 - 4 Turns #18 AWG, 0.250 lOw/Bead
Cl0, Cll - 56 pF Standex 01, 02 - MRF264
C12, C13 - 39 pF Standex RFC1, RFC2 - 0.15 /lH Molded Choke w/Bead,
C14, CIS - 15 pF Standex Ferroxcube 56-590 65/3B
C17 - 100 /IF @ 16 V Electrolytic RFC3, RFC4 - 4 Ferrite Beads each on #18 AWG
C18, C19, C20 - 680 pF Allen 8radley Feedthru Rl-l00nl/2WCarbon
R2 - lOOn 2.0 W Carbon

FIGURE 5 - Schematic· 60 W Amplifier

0 80
l .1
Pin = 15W t - -
VCC= 12.5V
~

-
",-
Pout ./

0 - i-- -r
I
~ I--
r- r-
I-
::>
:=::>
co
0
/
/"
,.- ico... f=160MHz t--

0
VSWR
2.0:1 20
1/ VCC = 12.5 V

1.5:1 ~ lL
VSWR
1.0:1 10 V
155 160 165 170 175 o 4.0 8.0 12 16 20
f. FREQUENCY (MHzl Pin INPUT POWER (WATTS)

FIGUR E 6 - Output Power, Efficiency, and FIGURE 7 - Output Power versus Input Power
Input VSWR versus Frequency

454
FIGURE 8 - PCB Photomaster (not full size)

455
456
 EB107

Mounting Considerations for

Motorola RF Power Modules

INTRODUCTION neering Laboratory. GEG was selected to do this work

The packaging used for standard Motorola RF Power because they have done extensive work in the area of
modules consists of a copper flange on which the sub- laminate stresses and have available several proven com-
strates are soldered and a non-conductive cover which puter programs which apply directly to this problem. The
is either of a "snap-on" or epoxy attached design. The assigned task was to provide an estimate of the maximum
ceramic substrates are either 96% alumina (AI,03)' amount of initial bow (curvature) in the mounting flange
99.5% alumina or 99% Beryllium oxide (BeO). These sub- which would not subsequently cause the ceramic sub-
strates are attached to the copper flange using either strate to fracture in the final assembled state. For the
lead-tin or indium based soft solders. Typical liquidus results of this analysis, see Table 1.
temperatures of these solders are in the 149°C to 163°C
range. MOUNTING CONSIDERATIONS
The purpose of this paper is to present the mechanical The theoretical analysis shows that some of the re-
factors which should be considered in mounting these sponsibility for proper mounting rests on the user. Proper
modules in equipment. consideration should be given to the following items:
1. Flatness of the mounting area must be such that
MAJOR MOUNTING FACTORS the final mounting of the module will not bend the flange
There are three major considerations in mounting an beyond the limits given in Table 1.
RF power module. First, the flange is used for the RF 2. Attention must be given to surface finish and clean-
electrical ground reference. Typical inductance of the liness of the mounting surface. For instance, if one
connection pins used on these modules is about 18 nano- mounts the module with thermal compound and uses a
henries per inch or 1.8 nanohenries per 100 mils. Since dirty work area which allows 3 to 5 mil particles to be
at 800 MHz a nanohenry has about 5.0 ohms reactance, present in the compound, a failure mode can be produced.
it is easy to see that it would be almost impossible to 3. Another consideration is the movement of material
achieve a low reactance ground through the use of pins around tapped or punched holes. A tapped or punched
alone. Second, the copper flange provides the thermal hole which leaves a burr on the mounting surface can
path for the removal of the heat produced in the active lead to fail ure modes.
devices present in the module. Thus, proper thermal han- 4. In addition, rigidity of the mounting surface and its
dling must be considered in mounting the module. Fi- material should be considered. For instance, the copper
nally, we must consider the mechanical stresses placed flange on an aluminum heatsink will result- in a bi-
on the module by the mounting techniques used. Here metallic system which can create a bending problem.
we consider stresses placed on the leads and bending or Consideration of the direction of ribs in a heatsink should
twisting of the mounting flange which would cause ce- be made to maximize stiffness in the direction of bending
ramic fractures. or adequate thickness of the heats ink must be provided
to control bending.
MODULE FLANGE FLATNESS It is not desirable to mechanically constrain the ends
During the processing ofthe module, consideration has of the module so that no "slip" is possible between the
to be given to the various stresses produced. Through module flange and its mounting surface. If the ends are
analysis of these stresses and the materials used we can constrained and the temperature differential between
arrive at the maximum allowable flange bending which the module and the heatsink is significant, there can be
can be tolerated from a mechanical standpoint. In de- enough bending of the module flange to break the ce-
termining the allowable flange flatness conditions, both ramic. An example calculation is shown below to dem-
analytical and empirical analyses were performed. onstrate this problem.
Agreement between both of these analyses was very Assume that the ends of the flange are constrained at
good. The theoretical analysis was performed by Moto- the centerline of the mounting holes. (2.4 inches for
rola Government Electronics Group, Mechanical Engi- MHW612A1MHW710/MHW720 series modules). Assume

457
that the module is mounted on a machined aluminum What should be derived from this discussion is that
heatsink. the design of the mounting for the module/heatsink sys-
Thermal expansion coefficients in /Linchlinchl'C tem is not a simple one and should not be done in a casual
Aluminum 25 x 10~6 manner.
Copper 17 x 1O~6 Our recommendation is that a mock version of the
L = 2.4 inches system be constructed early in the equipment design and
thermal cycling performed both with external heat input
For a reasonable approximation assume the thermally
to the system and with heat input to the system from the
induced bending creates an isosceles triangle as shown module. This is a very effective "analog computer" and
in Figure 1.
direct measurements of the flange/heatsink deflections
FIGURE 1 can be made. In this manner the actual expected flange
excursions can be compared to the recommended maxi-
mum flange bending to determine whether the design is
adequate. Incidentally, the recommended maximum de-
flection values given in Table 1 have a safety factor of
approximately 2. That is, the deflection required to crack
the ceramic is approximately twice the value given.
Table 1 includes data showing the empirical deflections
required to fracture a ceramic board in the module.
5. We strongly recommend the use of a good thermal
compound between the mounting surface. Sufficient ma-
terial must be used to fill all gaps which may be present.
Assume that the module flange changes temperature We have not been able to create any mechanical problem
from 25'C to 50'C and the heatsink changes temperature with excess compound as long as there is a path for the
from 25'C to 30'C in the same time (obviously the heat excess material to escape as the module is tightened down
input to the system comes from the copper flange - more with the mounting screws. At this point it should be
on this later). pointed out that unless both the module flange and the
Heatsink f::,. L (aluminum) = 2.4" x 5'C x 25 X 1O~6 heatsink were lapped to absolute gauge block flatness,
= 0.0003" there will always be a significant air gap between areas
Flange f::,. L (copper) = 2.4 x 25'C x 17 x 1O~6 of the flange and the heatsink. Since it is obviously not
= 0.00102" practical to achieve a lapped surface of this quality, this
portion of the mounting problem resolves to one of me-
So length ABC = 2.40102, AB = 1.20051" chanical rather than thermal considerations. As an
length AC = 2.4003", AD = 1.20015 aside, some of the Motorola modules also have machined
And AB" = AD" + BD" surfaces which may be oxidized to some degree. Infrared
BD = VAB" - AD" thermography of the active die was performed to see if
So BD = 0.029397 inches which far exceeds the there was any thermal degradation due to this oxide
allowable flange bend. layer and no degradation could be found. This has also
been found true on lapped discrete transistor flange
This analysis also points out the advantage of keeping mount parts.
the heatsink and the flange at lowest possible temper-
ature differential through the use of thermally conduct- Several manufacturers of thermally conductive heat-
ing compounds between the surfaces. sink compound exist. We have used products from Wake-
For instance, in the example given above with an alu- field and Dow Corning with success.
minum/copper system, the copper flange will remain in
tension at any temperature above the temperature at MOUNTING HARDWARE
which the system was constrained as long as the tem- Obviously an ideal mounting hardware scheme would
perature ratio between the heatsink and flange is kept be one in which the clamping pressure remained constant
less than the ratio of the thermal expansion coefficients with age. One way of achieving this is through the use
or 25/17. Incidentally, this assumes that the heat input of conical washers - one trade name is Belleville wash-
source to the system originates in the copper flange. This ers. Another possibility is "wavy" washers. Proper se-
situation points out the folly in some types of tempera- lection of mounting hardware and torque is also neces-
ture cycling testing. For instance, if the aluminum/cop- sary. We recommend the following mounting hardware
per system is constrained at 25'C and is uniformly heated sizes and torques:
to say 125'C. the copper remains in tension - if the 4-40 3 in/lb
system is cooled below 25'C, the copper will go into 6-32 5 inllb
compression. This is exactly the opposite situation ob- 8-32 5 inllb
tained when the heat input to the system comes from the
copper flange. TIGHTENING SEQUENCE
The above is a rather elementary analysis of the ther- A very important factor to be considered in mounting
mal effects on the module/heatsink system. Many other the module is the proper torquing sequence. The person-
factors are involved such as relative strengths of the nel involved in mounting the modules should be given
materials involved, bending of the mounting screws and careful instruction and their procedures monitored at
so forth. regular intervals. Since the flanges are punched from a

458
roll of material, there can sometimes be a small "roll-up" on the leads, even as the fixture wears. Motorola's spec-
at the end of the mounting flange. If one considers what ification for lead pull in shear and peel are 90B gm shear
can happen if the mounting hardware were tightened and 454 gm peel for BeO boards and 1500 gm shear and
completely at one end first, it is easy to see that the other 750 gm peel for alumina boards. Modules from PCB6, 90,
end could be "lifted" off the mounting surface well in and 91 product lines use BeO boards. Modules from the
excess of the allowable flange bending tolerance. PCB7, PC103 line use one alumina and one BeO board.
This should be avoided by first lightly alternately PC41, PC64, and PC104 use alumina boards.
snubbing down the mounting hardware "finger-tight."
Next, the hardware can be torqued to its final specifi- DE FLUXING
cation again in at least two sequential steps. These modules are designed to be manually soldered
into an assembly. The modules have a silicone die coat
THE IMPORTANCE OF THIS TORQUING over the active die, MOS capacitors, and nichrome re-
SEQUENCE CANNOT BE STRESSED sistors. The die coat used will not withstand the normal
TOO HIGHLY flux removal fluids and severe reliability problems could·
be incurred if the flux removal fluids or solder fluxes
LEADS penetrate the inside of the module. We recommend a flux
The leads used on the standard Motorola RF Power activity of no more than R or RMA be used.
Modules are of either tinned copper, gold or silver plated
KOVAR, or pure silver strap, typically 5 to 10 mils thick CONCLUSION
and 15 to 20 mils wide. The leads are intended for making In mounting RF power modules, the following major
electrical connections to the modules only and are not areas should be considered:
intended to support the module at any time in the as- 1. Heatsink flatness.
sembly process. Consideration should be given to the 2. Use thermal compound - eliminate dirt or grit in
stresses which may occur during mounting or testing. the compound or on mounting surfaces, use an ad-
Poorly designed test fixtures can create lead stresses far equate amount to fill gaps.
above those encountered in the end-use equipment. It is 3. Tighten modules down in an alternate manner
recommended that the fixture be designed so the leads "finger-tight" before final torquing.
are always clamped after the flange is clamped and the 4. Be careful with defluxing operations.
tolerances be such that an upward force is never placed 5. Consider lead stresses, both in mounting and testing.

TABLE 1 - Maximum Deflection

THEORETICAL """EMPIRICAL MAXIMUM RECOMMENDED

DEFLECTION DEFLECTION TO DEFLECTION COMBINED OUTGOING OA SPEC. (MAX)
TO BREAK BREAK HEATSINK & FLANGE
DEVICES LINE MIN AVG CONVEX CONCAVE CONVEX CONCAVE
MHW709,710 PC41 0.Q15 0.0190 0.0218 0.008 0.010 0.005 0.005
MHW720 * PC64 0.Q15 0.0190 0.0206 0.008 0.010 0.005 0.005
MHW720 ** PC64 0.Q11 0.0075 0.0079 0.007 0.0085 0.003 0.005
MHW720A PC104 0.0190 0.0206 0.008 0.010 0.005 0.005
MHW612, 613t PC86 0.0025 0.0019 0.0028 0.0015 0.002 0.001 0.002
MHW612A,613At PC87 0.011 0.0103 0.Q1 08 0.007 0.0085 0.003 0.005
MHW808 PC90 0.0025 0.0034 0.0015 0.002 0.001 0.002
MHW808A PC103 0.0065 0.0070 0.0035 0.004 0.0015 0.0025
MHW820 PC91 0.005 0.0073 0.0084 0.004 0.005 0.002 0.003
ALL UNITS IN INCHES

*' PC64 was changed to alumina board - BeO carrier transistor construction similar to PC41 in February, 1983. All product with date code .883 and
after has this construction.
H Old construction of PC64 with total 8eO output board.
*** Measured deflection to break a substrate within 3 to 5 seconds of application of force.
t These devices will be obsolete on September 30. 1983. Contact Motorola for the current availability and recommended discrete transistor replacement
lineup.

459
460
 EB411
A Digital Video Prototyping System
By Aldo Giardina B.Eng (Hons) AMIEE
Consumer Segment
Motorola Inc., Semiconductor Products Sector
Geneva

1, INTRODUCTION

This Engineering Bulletin describes a Digital Video The focus here is on the functionality of the
Prototyping System (DVPS) that has been developed combination of the above components and
using Motorola's latest multimedia devices, together development system. A Reference Section lists data-
with a PC-based Field Programmable GateArray (FPGA) sheets and user manuals containing detailed
development system. It is designed to provide a fast descriptions and information on their use.
and effective means of prototyping and demonstrating
digital video processing functions. A function developed The DVPS has been successfully used to implement
in this way may later be fully integrated as an ASIC two T.V. sub-systems, namely, a Picture-In-Picture
device for use in a consumer end-product. Processor and a 4:3-to-, 6:9 Picture Processor. Those
sub-systems are described briefly below.

2. MOTOROLA DEVICES USED

The DVPS takes advantage of several versatile b) MC44250(4). This triple B-bit Analogue-to-Digital
multimedia devices, that are listed below. They are Converter provides black-level clamping for either
used as a means of generating digital data from RGB orYUV signals. These are typically a.c. coupled
virtually any analogue video source, and providing a into the device from the MC440" which provides
means of displaying the resulting analogue video the appropriate clamping pulse, but may equally
signals on a consumer T.v. set, after the digital signal come from any other suitable video source.
processing function being prototyped. c) MC44200(5). This is the counterpart to the
a) MC440" (1). This is the multimedia derivative ofthe MC44250, a triple 8-bit Digital-to-Analogue
MC4400' (2). It performs the function of a Converter for RGB or YUV. It features differential
Multistandard (PAL/SECAM/NTSC) Chroma current source outputs designed to drive 75n
Decoder, with a selection between RGB or YUV loads with O.7Vpp.
output signals. The MC440' , also generates a T.v.
line-locked clock for digital sampling and subsequent Other devices used include the MC68HC05B6(6)
processing of the output signals. The latter function (8-bit MCU with onboard EEPROM), the MC, 4576(7)
is also available separately in the form of the (Dual Video OpAmp) and some standard CMOS
MC44'45(3). The output stages of the MC440" logic.
are designed to drive the inputs of the MC44250
directly.

461
 3. FPGA DEVELOPMENT SYSTEM

The digital processing element of the DVPS consists Development System(9) to produce a graphical file
of one or more FPGA devices. These comprise of user representing the configuration of the FPGA . This file
Configurable Logic Blocks (CLB's) and I/O Blocks may be manually edited for routing optimisation before
(lOB's) that, together with programmable interconnect, the final binary file is generated. Programming of the
allow most memory control and simple digital video FPGA devices may be carried out in one of two ways:
processing circuits to be implemented successfully. a) The binary file may be directly downloaded from the
The configuration data is stored in internal RAM. The host computer serial port to a powered device in a
reprogrammable nature of FPGA's makes debugging matter of seconds. This is the most appropriate for
and development a relatively straightforward process. the debugging and development stage, as it turns
circuit design changes into a quick and easy process
The logic capacity of the FPGA devices ranges from of device reconfiguration. It may be as simple as
1,200 up to 20,000 equivalent gates, with between 58 making an alteration to the schematic diagram and
and 240 user-programmable I/O's, which is ample for recompiling the design. As long as the device pin-
most applications. Their toggle frequency ranges out is unaltered, no rewiring is necessary.
between 50 and 125M Hz, and the devices come in a
b) When a design has matured and no further changes
range of package types.
are expected, the binary file may be programmed
into a serial or parallel PROM or EPROM. This is
The front-end to the development system is a
Schematic Capture Package(S), together with the FPGA addressed by the FPGA device itself to perform
automatic self-configuration of its RAM as part of
Library & Interface running on a Personal Computer.
Schematic files are processed by the FPGA the power-up sequence.

4. DVPS OVERVIEW

Figure 1 is a block diagram of the DVPS environment. output cards. The PC download cable connection is
The rack connects together the input card, the digital made directly to the digital card(s) for configuration of
card(s) and the output card through a backplane. The the FPGA(s). A Video source is connected to the front
external controller board also connects to the backplane of the input card; the outputs for connection to the final
to perform initialisation and control of the input and display are taken from the front of the output card.

Figure 1. Digital Video Prototyping System

462
The following three sections describe each card and made to the appropriate device data-sheet for more
its functions in more detail. Reference should be detail on application circuit diagrams.

5. INPUT CARD

IIC-BUS

a:
MC44011 """"8",,,,~~
VIDEO
PROCESSOR
MC44250
TRIPLE
VIDEOADC
~ ....~~
& CLKPLL
"""'....~w
8
~
a.
ClK·IN ~
~--~~----~------~ ~
III
~----------~~~~~--------------~
ClK·OUT

Figure 2. Input Card

The input card accepts various types of video signal determined by the division ratio set in the FPGA and
sources from which it generates three byte-wide data is always an integral multiple ofthe T. V. line frequency.
streams. A T.V. line-locked clock of up to 42MHz is Normally this would be chosen to be 27MHz. so that
also generated on this card for use in digital processing the video signals are sampled at 13.5MHz. as
of the data. Refer to figure 2 for a diagram of the card. recommended by CCIR Rec. 601(101.

Four BNC connectors atthe front ofthe card constitute The three signals from the MC44011 are a.c. coupled
the inputs. The first accepts composite video of any to the MC44250 inputs for black level clamping to the
standard. or a composite sync signal accompanied by appropriate levels before conversion. YUV or RGB
either RGB or YUV signals on the other three inputs. clamping modes are selectable through a jumper
The desired input configuration is selectable through setting. The RGB-mode clamps the back-porch of the
jumper settings on the card. These signals are signals to the bottom of the ADC input ranges. while
processed by the MC44011 to perform chroma the YUV-mode clamps the U and V signals to the
decoding and RGB matrixing where necessary. middle of the ranges. leaving the Y clamped to the
bottom of its ADC range. A burst-gate pulse is
The T.V. line-sync pulse from the signal source acts as generated by the MC440 11 to activate the d.c. clamps
a reference for the line-locked PLL that synthesises in the MC44250 at the correct time.
the clock on-board the MC44011. After suitable
buffering. the clock is output from this card for division The three 8-bit data streams resulting from the
down to line frequency by a counter in the FPGA on conversion are registered and buffered before being
the digital card. A T.v. line-rate Signal is returned from output to the digital card via the backplane.
that card to the phase/frequency comparator to
complete the loop in the MC44011. The exact Further details and circuit diagrams are given in an
frequency of the synthesised clock is. therefore. application note on video capture(111.

463
 6. OUTPUT CARD

IIe·BUS

2·P.U.&22·P.D.
RESIST.
a:
0 8 •
I- Wen
()
!;ca: ~ MC44011
W 8 ~
MC44200 VIDEO
z I-W
enU. TRIPLE
z ,u. PROCESSOR
0
() ~ffi s i VIDEODAC
8r.CLKPLL
W ~
Z
<C
..J MCl4576
a.
~ CLK·IN
~
II) 15KHz RETURN

CLK-OUT

Figure 3. Output Card

The output card. illustrated in figure 3. receives three The clock synthesis PLL on this card uses the same
8-bit data streams from the digital card. Its purpose is principle as on the input card. using a separate counter
to convert these into the analogue domain for display in the FPGA on the digital card. if the division ratio or
on a consumer T.v. or RGB monitor. A line-locked line frequency reference is different from that used by
clock is also available from this card for applications the former.
where the capture and display clock rates are potentially
different and/or unrelated. Data from the backplane is first registered by tri-state
buffers before being input into the MC44200 for
Access to the output signals is made via a PERITEL conversion. In the YUV-mode. the m.s.b.'s of the U
(SCART) Connection!'2) providing RGB signals. and V data lines are pulled-up by resistors while all
together with a fast-commutate or switching signal. other bits are pulled-downatthe inputs of the converter.
The MC44011 device on this card may also be used to This ensures that the video of any standard. or a
perform the matrixing of YUV signals to RGB. if composite sync signal accompanied by either RGB or
needed. Configuration of the card for the signal types YUV signals on the analogue outputs from the DAC·s.
being processed is set by jumpers. as on the input are correctly set for black-level when the input buffers
card. When connected to a T.V. set. the composite are set in tri-state mode. The MC44011 may then
video signal coming from the receiver via the PERITEL clamp these d.c. levels from the MC44200 and hence
connection may be used as a reference to which the provide the right levels for the receiver to display true
display clock synthesised by the local MC44011 may black.
be locked. This video signal is also output onto a BNC
connector for use as a source for the input card. if the The RGB signals from the MC44011 are buffered to
application requires it. drive the PERITEL socket with O.7Vpp at 750. using
MC14576 Dual Video OpAmps.

464
 7. DIGITAL CARD

I II " I I
PC CONN.

R-15KHz RETURN
-
CONFIG. MODE

I JUMPERS
R·ClK·IN

t Y·DATA·IN
a:
~
()

- ADDRESS B
III
U/V·DATA·IN Z
CONTROL
B
z
FIFO OR XILINX TIMING & CONTROL SIGNALS
0
()
DUAL PORT DATA-A FPGA III
VIDEO RAM . DEVICE B Y·DATA·OUT Z
DATA·B
U/V·DATA·OUT ~
«
fi ..J
a.
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t W·ClK·IN
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CD

W· 15KHz RETURN

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ADDRESS CON FIG. DATA

EPROM I

Figure 4. Digital Card

At the centre of the DVPS is the digital card. There may Invariably. the processing on the digital card involves
be one or several of these. between the input card and video data storage that requires memory external to
the output card. depending on the complexity of the the FPGA. Therefore. FIFO or Dual Port RAM devices
digital processing required by the application being would normally also be included on this card. close to
implemented. The FPGA currently employed in the the FPGAdevice. Figure 4 depicts a typical configuration
DVPS is the Xilinx XC3042PC84-1 00 device. This is a for this card.
4.200 equivalent-gate FPGA with a toggle rate of
100MHz. in an 84-pin PLCC package. As the function of the I/O pins is programmable and
application dependent. connections to and from the
In its simplest form the digital card consists of the FPGA pins are made using wire-wrap. once the pinout
FPGA device and the means to load its configuration has been defined.
RAM. This entails provision for a parallel or serial
PROM and/or a connection for the PC serial download
cable.

465
 8. RACK AND BACKPLANE

A 3U-high rack houses the DVPS, providing the Here, two external5V power supply units are used for
mechanical structure for, and the interconnections the digital and analogue sections respectively. All
between, the input card, the digital card(s) and the power and ground lines are kept separate on the
output card. All the cards described earlier are backplane and on the input and output cards. One star-
constructed in the form of extended-eurocards point connection is made between the grounds at the
(220mm x 1OOmm) and use 64-way edge connectors power supplies to avoid loops between the cards in
for plugging into the wire-wrapped DVPS backplane. the rack.

9. CONTROLLER BOARD

The two MC44011 devices on the input and output necessary because the two identical MC44011
cards must be initialised and controlled via software devices, by definition, have the same 12C-Busaddress,
using the two wire 12C-Bus Protocol(131. For this so that although they may share the same clock, two
purpose, an MCU Controller Board(141 built around separate data lines are needed to maintain separate
the MC68HC05B6 8-bit microcontroller, is used with control using the 12C-Bus protocol from a single
the DVPS. controller board.

This is a stand-alone board with a built-in keyboard and The controller board can also be used to manage the
an 8-digit 7-segment display. It operates in a pseudo vertical picture timing control, as the processing
12C-Bus mode of communication with the two devices, requirements at T.V. line rate lie within the limits ofthe
using three wires to the DVPS backplane. This is 4MHzMCU.

10. SYSTEM IMPLEMENTAnON EXAMPLES

As mentioned in the introduction, the DVPS has The second digital card contains dual port video-RAM
proved to be useful as a flexible prototyping platform which stores the data received from the first digital
for digital video processing functions. This section wi" card. The FPGA on this card generates all the control
briefly describe two projects in which the DVPS was signals necessary to access the memory, as well as
successfully employed to implement functions for performing the divider function for the PLL's on the
demonstration to equipment manufacturers. input and output cards. Its function is to write the data
into the memory at 4.5MsampleS/s using a clock that
8) Picture-In-Picture Processor is locked to the inserted (PIP) channel, and reading it
out again at 13.5MsampleS/s using a clock that is
Three digital cards were used together with the input locked to the background (MAIN) channel. These two
card and the output card to emulate a multistandard channels may, of course, be asynchronous to each
PI P function. The YUV samples coming from the input other, hence the requirement of the two separate PLL
card are standard independent by virtue of the clock sources.
MC440'1.
Data read out of the memory is output to the third
The first digital card contains an FPGA to perform data digital card. Here, the FPGA demultiplexes the colour-
reduction by multiplexing the U and V samples as a difference samples and interpolates them to
means of subsamplingthese channels and so reducing reconstitute three byte-wide data streams together
the data bandwidth by 33%. This takes advantage of with the luminance samples. The YUV data is then
the fact that the colour-difference signals each occupy converted to analogue signals and matrixed to RGB by
only half the bandwidth of the luminance signal. The the output card.
two resulting byte-wide data streams (y, UN) are then
decimated by a factor of nine, using a two-dimensional Here, the MCU controller board was successfully
median-filter. The output data represents the inserted used to perform control of the two MC44011 devices,
picture but at one third the original height and width. while also providing vertical timing control and row-
addressing for the video memory accesses.

466
b) 4:3-to-16:9 Picture Processor used are therefore derived from the PLL' s fundamental
clock frequency of 40.5MHz.
A single digital card between the input card and the
output card was sufficient to implement a processor Using the same principle as in the previous example,
to correctly display a 4:3 aspect-ratio picture on a 16:9 the two colour-difference data streams are multiplexed
aspect-ratio T.V. tube. Here too, the processor is into one by the FPGA before being written into the
multi standard by virtue of the MC44011 on the input memories along with the luminance samples. The
card. MC44140(15) PAL and SECAM delay-line functions
are also performed by this prototype using a further
The geometric correction is achieved by writing video FIFO memory, hence replacing the former device in a
data into FI FO memories at 10.125M Hz and reading system using the MC44001. To this end, the
outthe data at 13. 5MHz. As the read and write clocks multiplexed colour-difference samples are processed
are essentially related and both locked to the video across consecutive pairs of lines, before demultiplexing
derived from the T.V. receiver, only one PLL divider into separate data streams again and being output for
needs to be implemented in the FPGA. All the clocks conversion and matrixing by the output card.

11. REFERENCES

Copies of the Motorola data-sheets and application note listed below can be obtained from Motorola Product
Marketing, 31023 Toulouse Cedex, France.
(1) MC44011 Chroma Processor & Pixel Clock Generator - MC44011 Advance Information
(2) MC44001 Chroma And Deflection Processor - MC44000 Product Preview
(3) MC44145 Pixel Clock Generator - MC44145 Product Preview
(4) MC44250 Triple Video ADC - MC44250/D Data Sheet
(5) MC44200 Triple Video DAC - MC44200 Product Preview
(6) MC68HC05B6 B-bit Microcontroller - MC68HC05B6/D Data Sheet
(7) MC14576 Dual Video Ol>'amp - MC14576 Advance Information
(8) OrCAD/SDT Schematic Capture - User Manual
(9) XILINX FPGA Development System - User Manual
(10) CCIR Recommendation 601 - Specification of Standard
(11) Video Capture Applications of the MC4401 0 & MC44250 - Application Note
(12) Peri tel Connection - Specification of Standard
(13) Philips 12C-bus Protocol - Specification of Standard
(14) MCU Controller Board - MC44CTRBDOl 0
(15) MC44140 Digital Delay-line - MC44140 Advance Information

467
468
 Additional
Information

469
470
 Additional Information
Additional information relevant to Radio, RF and Video applications
may be found in the following Motorola documents, available through
your Franchised Distributor by quoting the appropriate reference.

AN10511D Transmission Line Effects in PCB Applications

BR3471D Bipolar logic Circuits - Quality & Reliability
BR470/D Motorola Discretes - The Complete Solution (Rev. 1)
BR475/D Advanced logic Functions
BR904/D Mll·Processed Devices: Technical Data
BR923/D Communications, Power & Signal Technologies Group, Reliability Audit Report,
September-December 1993
BR924/D Military Analog Lineup
BR1130/D Coming Through loud and Clear
BR1305/D Linear Integrated Circuits: New Product Calendar, January 1994
BR1330/D ECLinPS Lite Single Gate ECl Devices
BR1332/D logic Integrated Circuits Division: New Product Calendar - Second Quarter, 1994
BR1333/D low Skew Clock Drivers & Programmable Delay Circuits (Rev. 3)
BR1334/D High Performance Frequency Control Products (Rev. 1)
BR1409/D ECl300 logic Array
BR1415/D Military Telecom Special Functions
BR1418/D Military Analog, Telecom and Special Functions Fact Sheet, June 1992
BR1429/D Wideband Linear Amplifiers - CATV, CRT Drivers, General Purpose
BRE378/D UnitPAK Packaging
BRE504/D Electronic Tuning Address Systems
Dl110/D RF Device Data (Rev. 5, 1994)
DL111/D Bipolar Power Transistor Data (Rev. 6, 1992)
Dl122/D MECl Device Data (Rev. 5, 1993)
Dl126/D Small-Signal Transistors, FETs and Diodes Device Data (Rev. 4)
Dl128/D Linear and Interface Integrated Circuits (2 volume set, Rev. 4, 1993)
DL140/D High Performance ECl Data - ECLinPS and ECLinPS Lite (Rev. 2, 1993)
Dl145/D Military MECl Family Data
Dl148/D Discrete Military Operations Data
Dl151/D Rectifier Device Data (Rev. 1. Replaces DL125/D)
Dl41 OlD Power Applications Manual (Rev. 1)
Dl4111D Communications Applications Manual (Rev. 1)
Dl414/D FET Applications Manual
HB205/D MECl System Design Handbook (Rev. 1)
SG46/D RF Products Selector Guide & Cross Reference - 1994 (Rev. 11, 1994)
SG138/D Commercial Plus and Mil/Aero Application IC & Discrete Selector Guide
(Rev. 5, 1993)
SG140/D SCANSWITCH Selector Guide (Rev. 1, 1990)
SG169/D Mixed Signal Solutions from MOS Digital-Analog Integrated Circuits Division
- Quarter 1, 1994
SG270/D Discrete Semiconductor Cross Reference Guide -1992
SG365/D low Skew Clock Drivers and Programmable Delay Circuits (Rev. 2)
SG366/D TTL, ECl, CMOS and Special logic Circuits Selector Guide (Rev. 3, 1993)

471
 Additional Information (continued)

SG37010 Discrete Surface Mount Selector Guide (Rev. 1, 1994)

SGE112ID Cross Reference for NEC-to-Motorola RF Transistors
T8326/D Radio Frequency Transistors: Principles and Practical Applications
(Dye and Granberg, 1993)

472
Literature Distribution Centres:
EUROPE : Motorola Ltd., European Literature Centre, 88 Tanners Drive, Blakelands,
Milton Keynes, MK14 5BP, England.
ASIA PACIFIC : Motorola Semiconductors (HK) Ltd., Silicon Harbour Center, No. 2, Dai King Street,
Tai Po Industrial Estate, Tai Po, NT, Hong Kong.
JAPAN : Nippon Motorola Ltd., 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 , Japan.
USA: Motorola Literature Distribution, P.O. Box 20912, Phoenix, Arizona 85036 .

.® MOTOROLA