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    Exercise 4

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    computer organization and design solution 4th edition quiz

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    Exercise 4

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    aliverbe34
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    computer organization and design solution 4th edition quiz

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    Exercise4

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    computer organization and design solution 4th edition quiz

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    12 views3 pages

    Exercise 4

    Uploaded by

    aliverbe34
    computer organization and design solution 4th edition quiz

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    Computer Engineering |

    2019 Semester 1
    Ab. Hamraz
    Exercise Sheet 4
    Deadline:
    Write homework number and your name & ID & group on your file.
    For Example: Homework 04
    Ab. Razzaq Hamraz 20315
    Group A
    Exercise 1.3
    Consider three different processors P1, P2, and P3 executing the same instruction set with the clock rates and
    CPIs given in the following table.

    1.3.1 [5] <1.4> Which processor has the highest performance expressed in instructions
    per second?
    1.3.2 [10] <1.4> If the processors each execute a program in 10 seconds, find the
    number of cycles and the number of instructions.
    1.3.3 [10] <1.4> We are trying to reduce the time by 30% but this leads to an increase of
    20% in the CPI. What clock rate should we have to get this time reduction?

    For problems below, use the information in the following table.

    1.3.4 [10] <1.4> Find the IPC (instructions per cycle) for each processor.
    1.3.5 [5] <1.4> Find the clock rate for P2 that reduces its execution time to that of P1.
    1.3.6 [5] <1.4> Find the number of instructions for P2 that reduces its execution time to
    that of P3.
    Exercise 1.4
    Consider two different implementations of the same instruction set architecture. There
    are four classes of instructions, A, B, C, and D. The clock rate and CPI of each
    implementation are given in the following table.

    1.4.1 [10] <1.4> Given a program with 106 instructions divided into classes as follows:
    10% class A, 20% class B, 50% class C, and 20% class D, which implementation is
    faster?
    1.4.2 [5] <1.4> What is the global CPI for each implementation?
    1.4.3 [5] <1.4> Find the clock cycles required in both cases.

    The following table shows the number of instructions for a program.

    1.4.4 [5] <1.4> Assuming that arith instructions take 1 cycle, load and store 5 cycles,
    and branches 2 cycles, what is the execution time of the program in a 2 GHz
    processor?
    1.4.5 [5] <1.4> Find the CPI for the program.
    1.4.6 [10] <1.4> If the number of load instructions can be reduced by one half, what is
    the speedup and the CPI?

    Exercise 1.5
    Consider two different implementations, P1 and P2, of the same instruction set. There are five classes of
    instructions (A, B, C, D, and E) in the instruction set. The clock rate and CPI of each class is given below.

    1.5.1 [5] <1.4> Assume that peak performance is defined as the fastest rate that a
    computer can execute any instruction sequence. What are the peak performances of P1
    and P2 expressed in instructions per second?

    1.5.2 [10] <1.4> If the number of instructions executed in a certain program is divided
    equally among the classes of instructions except for class A, which occurs twice as
    often as each of the others, which computer is faster? How much faster is it?

    1.5.3 [10] <1.4> If the number of instructions executed in a certain program is divided
    equally among the classes of instructions except for class E, which occurs twice as
    often as each of the others, which computer is faster? How much faster is it?
    The table below shows instruction-type breakdown for different programs. Using this data, you will be
    exploring the performance trade-offs for different changes made to an MIPS processor.

    1.5.4 [5] <1.4> Assuming that computes take 1 cycle, loads and store instructions take
    10 cycles, and branches take 3 cycles, find the execution time on a 3 GHz MIPS
    processor.
    1.5.5 [5] <1.4> Assuming that computes take 1 cycle, loads and store instructions take 2
    cycles, and branches take 3 cycles, find the execution time on a 3 GHz MIPS
    processor.

    1.5.6 [5] <1.4> Assuming that computes take 1 cycle, loads and store instructions take 2
    cycles, and branches take 3 cycles, what is the speedup if the number of compute
    instruction can be reduced by one-half?

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