Recent Advances in Power Electronics and Drives

Lecture Notes in Electrical Engineering 1139
Krishna Murari
Bhim Singh
Vijay Kumar Sood Editors
Recent Advances
in Power
Electronics and
Drives
Select Proceedings of EPREC 2023,
Volume 2
Lecture Notes in Electrical Engineering
Volume 1139
Series Editors
Leopoldo Angrisani, Department of Electrical and Information Technologies Engineering, University of Napoli
Federico II, Napoli, Italy
Marco Arteaga, Departament de Control y Robótica, Universidad Nacional Autónoma de México, Coyoacán, Mexico
Samarjit Chakraborty, Fakultät für Elektrotechnik und Informationstechnik, TU München, München, Germany
Jiming Chen, Zhejiang University, Hangzhou, Zhejiang, China
Shanben Chen, School of Materials Science and Engineering, Shanghai Jiao Tong University, Shanghai, China
Tan Kay Chen, Department of Electrical and Computer Engineering, National University of Singapore, Singapore,
Singapore
Rüdiger Dillmann, University of Karlsruhe (TH) IAIM, Karlsruhe, Baden-Württemberg, Germany
Haibin Duan, Beijing University of Aeronautics and Astronautics, Beijing, China
Gianluigi Ferrari, Dipartimento di Ingegneria dell’Informazione, Sede Scientifica Università degli Studi di Parma,
Parma, Italy
Manuel Ferre, Centre for Automation and Robotics CAR (UPM-CSIC), Universidad Politécnica de Madrid, Madrid,
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Faryar Jabbari, Department of Mechanical and Aerospace Engineering, University of California, Irvine, CA, USA
Limin Jia, State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing, China
Janusz Kacprzyk, Intelligent Systems Laboratory, Systems Research Institute, Polish Academy of Sciences, Warsaw,
Poland
Alaa Khamis, Department of Mechatronics Engineering, German University in Egypt El Tagamoa El Khames,
New Cairo City, Egypt
Torsten Kroeger, Intrinsic Innovation, Mountain View, CA, USA
Yong Li, College of Electrical and Information Engineering, Hunan University, Changsha, Hunan, China
Qilian Liang, Department of Electrical Engineering, University of Texas at Arlington, Arlington, TX, USA
Ferran Martín, Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Bellaterra, Barcelona,
Spain
Tan Cher Ming, College of Engineering, Nanyang Technological University, Singapore, Singapore
Wolfgang Minker, Institute of Information Technology, University of Ulm, Ulm, Germany
Pradeep Misra, Department of Electrical Engineering, Wright State University, Dayton, OH, USA
Subhas Mukhopadhyay, School of Engineering, Macquarie University, Sydney, NSW, Australia
Cun-Zheng Ning, Department of Electrical Engineering, Arizona State University, Tempe, AZ, USA
Toyoaki Nishida, Department of Intelligence Science and Technology, Kyoto University, Kyoto, Japan
Luca Oneto, Department of Informatics, Bioengineering, Robotics and Systems Engineering, University of Genova,
Genova, Genova, Italy
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Federica Pascucci, Department di Ingegneria, Università degli Studi Roma Tre, Roma, Italy
Yong Qin, State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing, China
Gan Woon Seng, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore,
Singapore
Joachim Speidel, Institute of Telecommunications, University of Stuttgart, Stuttgart, Germany
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Haitao Wu, Academy of Opto-electronics, Chinese Academy of Sciences, Haidian District Beijing, China
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Krishna Murari · Bhim Singh · Vijay Kumar Sood
Editors
Recent Advances in Power

Electronics and Drives
Select Proceedings of EPREC 2023,
Volume 2
Editors
Krishna Murari Bhim Singh
Department of Electrical Engineering Department of Electrical Engineering
and Computer Science Indian Institute of Technology Delhi
The University of Toledo New Delhi, Delhi, India
Toledo, OH, USA
Vijay Kumar Sood

Department of Electrical, Computer
and Software Engineering
Ontario Tech University
Oshawa, ON, Canada
ISSN 1876-1100 ISSN 1876-1119 (electronic)

Lecture Notes in Electrical Engineering
ISBN 978-981-99-9438-0 ISBN 978-981-99-9439-7 (eBook)
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Preface
The Electric Power and Renewable Energy Conference (EPREC-2023) was orga-
nized by the Department of Electrical Engineering, National Institute of Technology
Jamshedpur, India, from May 25 to 27, 2023. We thank all the contributors for main-
taining the high standard and making EPREC-2023 a huge success. Out of total 234
valid submissions, only 95 were selected for publication in four different volumes,
i.e., an acceptance rate of nearly 40%. This volume, i.e., Recent Advances in Power
Electronics and Drives is one of four volumes to be published by Springer in the book
series Lecture Notes in Electrical Engineering (LNEE). It contains 25 high quality
papers.
This book entitled Recent Advances in Power Electronics and Drives—Select
Proceedings of EPREC 2023 provides rigorous discussions, case studies, and recent
developments in the emerging areas of power electronics, especially, power inverter
and converter, electrical drives, regulated power supplies, electric vehicle and its
charging infrastructure, etc. The readers would be benefitted in enhancing their
knowledge and skills in the domain areas. Also, this book may help the readers in
developing new and innovative ideas. The book can be a valuable reference for begin-
ners, researchers, and professionals interested in advancements in power electronics
and drives.
We thank all the authors, organizing committee members, technical program
committee members, reviewers, and student coordinators for their valuable contri-
butions and volunteer work. We also appreciate the role of session chairs/co-chairs
and thank the series editors of LNEE and Ms. Kamiya Katter, Associate Editors,
Springer for their help and quick responses during the preparation of the volume.
Toledo, USA Krishna Murari

New Delhi, India Bhim Singh
Oshawa, Canada Vijay Kumar Sood
v
Contents
Hardware-In-Loop Test for Electronic Control Unit . . . . . . . . . . . . . . . . . . 1

Bhupendra Teriya and Sushma Gupta
High Efficient Single Phase Active LED Driver with Reduced
Power Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ramesh Babu Pallapati, Ramulu Chinthamalla, Sindhu Vutturi,
D. V. K. Abhinay, and Chandra Kiran Kumba
Implementation of Model Predictive Current Control Technique
for Single Phase Four Level Grid Connected Asghar Inverter . . . . . . . . . . 27
Dipty Chandrakar, Bhagwan K. Murthy, and Aratipamula Bhanuchandar
A Low Voltage Stress Switched-Capacitor Based 7-Level Boost
Multilevel Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Gangadhar Dhal, Kasinath Jena, Lipika Nanda, Pradeep Ku. Sahu,
Kumaresh Pal, and Aditya Prasad Padhy
Design and Investigation of Solar PV-Fed PMSM Motor Drive . . . . . . . . . 51
Irfan Qureshi and Vikas Sharma
Scheming of Four-Phase IBC for Fast Charging of EV Battery . . . . . . . . . 65
Abhishek Singh, Pooja Kumari, and Niranjan Kumar
Speed Control of a Brushless DC Motor Using Hall Sensor . . . . . . . . . . . . 77
Manoj Kumar Kar, Shejal Sanjay Waghmare, Simeen Mujawar,
and Sreerekha Vadi
Implementation of Multifunctional Electric Vehicle Charger Based
on ANFIS with Solar PV Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Othuru Baba, S. Hussain Vali, Vempalle Rafi, and R. Kiranmayi
Axial Flux Motors for Suspension, Levitation and Propulsion
System of Hyperloop-A Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Richa Dewangan, Suresh Kumar Gawre, and Shailendra Kumar
vii
viii Contents
A Generalized Symmetrical and Asymmetrical Multilevel Inverter

Topology with Reduced Number of Components . . . . . . . . . . . . . . . . . . . . . . 123
Ragul Duraisamy and Thiyagarajan Venkatraman
Comprehensive Analyses of Control Techniques in Dual Active
Bridge DC–DC Converter for G2V Operations . . . . . . . . . . . . . . . . . . . . . . . 135
Sudipta Baidya and Akanksha Shukla
DBSCAN-Based Cascaded Inductively Coupled DSTATCOM
for PQ Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Praveen Kumar Yadav Kundala, Mrutyunjaya Mangaraj,
Suresh Kumar Sudabattula, Jogeswara Sabat, and Rohan Thakur
EV Charger Using Modified DAB Converter . . . . . . . . . . . . . . . . . . . . . . . . . 173
Payel Show, R. L. Josephine, and Sai Harsha Naidu
Overview of SOC Estimation Strategies for Battery Management
in Electric Vehicles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Anupam Singh and Arvind Yadav
Comprehensive Review of Switched-Capacitor Boost Single-Source
Nine-Level Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Haresh Nanda and Himanshu Sharma
Design, Simulation and Analysis of DC–DC Cuk LED Drivers . . . . . . . . . 221
B. Lakshmi Praba, V. Vidhu Priya, and R. Seyezhai
PV Partial Shading for Interleaved Quadratic High-Gain DC–DC
Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
M. Premchand and Swati Devabhaktuni
Investigation on Modified Bridgeless SEPIC PFC Converter
Topology for Battery Charging Application . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Sridhar Makkapati, N. Chitrapavai, and Seyezhai Ramalingam
The Improved vµ LMS-Based Grid Connected Solar PV System
Power Flow with Abnormal Grid and Non-linear Load Conditions . . . . . 261
Pavan Prakash Gupta, Ramesh Kumar Tripathi, and Shailendra Kumar
Predictive Torque Control of Five-Phase Open-Ended Winding
Induction Motor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Naresh Rayavarapu, Swati Devabhaktuni, and C. Venkata Subba Reddy
Grid-Integrated EV Charging Infrastructure . . . . . . . . . . . . . . . . . . . . . . . . 297
Sugunakar Mamidala and Arvind Kumar Prajapati
Modified Multi-inductor-Based Cell Balancing in Electric Vehicles . . . . . 325
Utsab Bhattacharya and Pradeep Kumar
Contents ix
Design and Hardware Implementation of Fuzzy Logic Controller

for Boost Converter for Battery Charging Using dSPACE . . . . . . . . . . . . . 343
K. S. V. Phani Kumar, Vishwanatha Siddhartha, Kalluri Deepika,
and Sonnati Venkateshwarlu
A Modified Direct Torque Control of a Five-Phase Induction Motor
for Harmonic Current Elimination and Reduction of Common
Mode Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
C. Venkata Subbareddy and Swati Devabhaktuni
A Novel Approach Towards Performance Analysis of Three Phase
Two Level Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Papia Ray, Shreya Mohanty, and Arvind R. Singh
About the Editors
Krishna Murari received a B.Tech. degree in electrical engineering from WBUT,

India, in 2010, an M.E. degree in power systems from Thapar University, India
in 2014, and a Ph.D. degree in electrical engineering from the Indian Institute of
Technology Roorkee, India in 2019. Currently, he is working as a Research Assis-
tant Professor at the Electrical Engineering and Computer Science Department, The
University of Toledo, Toledo, Ohio, USA. Prior to this, he worked as a Research
Associate at Clarkson University, Potsdam, New York. He has also worked as a
Postdoctoral Fellow with the Energy Production, and Infrastructure Center (EPIC),
University of North Carolina at Charlotte, North Carolina, USA. He is a member
of IEEE and has published 11 Journals, 10 conferences, 01 Book, and 02 book
chapters. He is serving as a reviewer in several international journals and confer-
ences. He is the recipient of the best-prized paper by The Industrial Automation and
Control Committee of the IEEE Industry Application Society among the research
articles presented in 2021. He is a reviewer in journals, such as IEEE, IET, MDPI,
and Taylor Francis journal. His research interests include power system analysis,
AC–DC power flow studies, demand-side management, optimization and control of
DERs, optimal power flow, distribution network pricing, and smart grid.
Dr. Bhim Singh (Fellow, IEEE) was born in Rahamapur, Bijnor (UP), India, in 1956.
He received a B.E. degree in electrical engineering from the University of Roorkee
(now IIT Roorkee), Roorkee, India, in 1977, the M.Tech. degree in power apparatus
and systems, and a Ph.D. degree in electrical engineering from the IIT Delhi, India,
in 1979 and 1983, respectively. In 1983, he joined the Department of Electrical
Engineering, University of Roorkee, as a Lecturer. He became a Reader there in
1988. In December 1990, he joined the Department of Electrical Engineering, IIT
Delhi, India, as an Assistant Professor, where he became an Associate Professor in
1994 and a Professor in 1997. He has been the Head of the Department of Electrical
Engineering at IIT Delhi from July 2014 to August 2016. He has been the Dean,
of Academics at IIT Delhi, from August 2016 to August 2019. He is a JC Bose
Fellow of DST, Government of India since December 2015. He has been CEA Chair
Professor since January 2019. Professor Singh has guided 84 Ph.D. dissertations and
xi
xii About the Editors
168 M.E./M.Tech./M.S.(R) theses. He has filed 58 patents. He has executed more

than 80 sponsored and consultancy projects. His areas of interest include solar PV
grid interface systems, microgrids, power quality monitoring and mitigation, solar
PV water pumping systems, and improved power quality AC–DC converters.
Dr. Vijay Kumar Sood was a Senior Researcher with the Research Institute of
Hydro-Québec (IREQ), Montreal, QC, Canada, for many years. Currently, he is
a Professor in the Electrical Engineering Department, at Ontario Tech University,
Oshawa, ON, Canada where he joined in 2007. He is also a registered Professional
Engineer in Ontario. Dr. Sood received his Ph.D. degree from the University of
Bradford, UK in 1977. He has authored over 160 articles and written two books on
HVDC and FACTS transmission systems. He was an Editor of the IEEE Transactions
on Power Delivery, Associate Editor of the IEEE Canadian Journal of Electrical and
Computer Engineering, and Editor of the IEEE Canadian Review quarterly magazine.
Currently, he is the Editor-in-Chief of the Distributed Generation and Alternative
Energy Journal. His current research interests include the monitoring, control, and
protection of power systems. Dr. Sood is a Life Fellow of the Institute of Electrical
and Electronics Engineers, a Fellow of the Engineering Institute of Canada, and an
Emeritus Fellow of the Canadian Academy of Engineers.
Hardware-In-Loop Test for Electronic
Control Unit
Bhupendra Teriya and Sushma Gupta
Abstract The vehicle’s electronic control unit (ECU) to be validated and verified in
accordance with client specifications. Adequate prototyping and testing are essential,
in order to speed up assembly cycle time, automation in testing replaces manual
testing by human operators on an ongoing basis. Before installing the ECU in the
vehicles, the hardware-in-loop (HiL) environment is used to test it. The HiL setup for
testing ECU to find the driving warning, which is a critical failure, is the main topic
of this study. The failure data is recorded in the memory together with the failure’s
date, time, and cause. The problem in the ECU is further diagnosed using the stored
data. The history data storage (HDS) feature in non-volatile memory (NVM) will
save various data for each major failure. The HiL makes it possible to test the ECU in
real-time conditions in the lab. Additionally, it offers a setting that is similar that of
a car. In HiL ECUs communicate with one another using the CAN communication
protocol.
Keywords Electronic control unit · Hardware in the loop system · Electric

vehicle · Real-time simulation · History data storage
1 Introduction
The implementation and testing processes used by the automotive industry today
have changed; industries are adopting a new method to test the system in a lab
setting, which offers real-world experience. The implementation of these similar
rapid prototyping ideas for car and other component testing or validation, known as
Hardware in the loop or HiL Simulation, may, however, represent the most significant
advance [1]. The HiL setup is a technique that substitutes a real-time environment
with all the components for the actual vehicle in order to test the operation of the
ECU and failure outcomes before assembling it into a vehicle. A real-time virtual
environment made up of a central controller known as the host computer with the
B. Teriya (B) · S. Gupta

Maulana Azad National Institute of Technology, Bhopal, India
e-mail: [email protected]
© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024 1
K. Murari et al. (eds.), Recent Advances in Power Electronics and Drives, Lecture Notes
in Electrical Engineering 1139, https://doi.org/10.1007/978-981-99-9439-7_1
2 B. Teriya and S. Gupta
install vector tools like vector CANOe and vTESTstudio is used to substitute the
engine and other components. The simplest method to test the ECU is to use these
tools and setup. Real-time simulation can be accelerated and improved with HiL
[2]. Software that uses simulation has a few drawbacks; Hardware in the loop is the
only solution to bridge the gap between simulation and real-time simulation because
software simulation cannot imitate natural behavior or operational conditions [3]. If
we can identify the ECU fault before applying it in the actual vehicle, the cost of
correcting error is greatly reduced. Instead of testing an ECU with the entire system,
the Hardware in Loop arrangement offers this capability to lower testing error. The
increasing demand from consumers for electric vehicles with more electric control
units or engine control units with enhanced functionality and operating range is
driving the need for significant advancements in the field [4]. The use of inexpensive
cars is not necessary because the hardware in a loop testing environment can imitate
the vehicles, provides the diagnostic capability, shortens the time needed for devel-
opment and testing, and can emulate several vehicles. The application of real-time
simulation to testing the vehicle’s engine control unit is expanded [5].
To integrate the real Hardware into the loop system while simulating mechanical
and electrical models of the system. The vehicle electronic control unit is interfaced
with the simulator during the HiL controller testing to test the control and protection
techniques. The configuration of hardware and software tools creates the HiL simu-
lation [6]. Since the operation of the electronic control unit (ECU) is a very high
frequency for transmitting the control area network (CAN) signal between the ECU
nodes, a real-time simulation is crucial for testing. CAN is a multi-master commu-
nication. The CAN protocol is used in vehicles for diagnostic services between the
ECU and the tester and wiring harness diagnosis, since it has a message transfer
rate of one megabit per second and a range of forty meters [7]. For highly auto-
mated vehicles, HiL testing is performed to ensure the accuracy and verification of
the automation project. Three crucial elements make up the strategy outlined for the
Validation and Verification (V&V) methodology. Validating an autonomous vehicle,
coming up with a safety concept, and making sure it complies with the standards
of the vehicle [8]. Laboratory testing methods sparked an interest in reducing the
developer and testers’ time while improving the product’s quality. The HiL set-up
offers a regulated, repeatable, and economical method of testing embedded systems.
Input–output diagnostics, regulated algorithm performance factoring input–output
functionality of the ECU processor, and RAM utilization are all provided by the HiL
simulation [9].
Hardware-In-Loop Test for Electronic Control Unit 3
1.1 Objective
Following are the objectives of the work:

• Understanding of hardware-in-loop set-up to test vehicle electronic control unit.
• Trigration of Warning for the driver after fault injection in the ECU and Identify
the stored data in NVM.
2 Hardware-In-Loop Set-Up
The hardware-in-loop arrangement consists of electrical sensors, actuators, electrical

and electronics loads (eLoad), and tools for automation. The interface between the
test unit and the plant simulation is provided by these electrical emulations [10]. The
value of each electrical component and load is controlled by the plant simulation and
is read by the simulation tools vector CANOe. It is also important to secure input–
output interferences with the test system in order to test an ECU; this is independent
of connecting the communication network to the test system. Figure 1 shows the
block diagram for hardware-in-loop set-up.
The information exchange between the ECU and the test system is handled by the
Vector Test system (VT System), which also has access to the input–output of the
hardware that is the subject of the test. All test system components are integrated into
the validation and verification (VV) system and connected in one module to check
for input–output interference. The VT system is completely linked with the vector
CANOe and vTESTstudio scripts, requiring little to no wire to set up the test, connect
the relay, add load for the actuation simulation, and add vehicle load [11–13]. The
Fig. 1 Hardware-in-loop set-up block diagram

comprehensive software package CANOe is used to test and analyze a single node or
a node network. Vector: vTESTstudio is used to automate test case scripts for ECU
to boost reliability and shorten simulation time. It offers test engineers a variety of
capabilities, including reusability. It can be used to validate and verify the ECU test
in the HiL configuration during all phases of product development. Direct access to
the HiL test environment is available. The CANOe is the sole tool that offers us a
wide range of possibilities for development and testing jobs. Simulation in the vector
CANOe tool also offers the capability for graphics and test-based result evaluation.
At a single HiL setup desk, it may analyze the multi-node network connectivity of
the ECU and the entire test system. All bus activity can be messaged through the
CANOe Trace window, and all frames and graphics windows display the message
sent and the graphics image of that message.
The EPS, iBooster, ESP, and other eLoads are utilized to examine the ECU’s
response for a failure in one of the loads. These loads are ASIL loads. All these
weights that were used in the vehicle are crucial in terms of safety. A failure in the
load occurs when the requirement of the load does not match the specification. A
calibrated XCP variable was employed to simulate these failures in the load. We can
modify the location of the internal switches of the loads using these XCP variables.
The test object for the test setup is the actual or real ECU. To analyze the failure
information, check whether the data and cause will be stored correctly or not in the
ECU memory, once internal controls fail. The ECU stores the information in ASCII
format. The Hardware in the Loop setup’s most important component is the ECU.
Based on the test’s requirements, the signal processor is chosen. The processor has
a sensor and actuators for efficiently processing signals supplied when the vehicle’s
ECU fails and for diagnostic services. Because of advances in power electronics,
various types of signal processors are used for signal processing. A signal processor’s
main goal is to offer a user interface, such as a set of data. For vTESTstudio to prepare
the test cases, the standard CANOe license is required, and an additional remote
permission is given for a remote computer with the HiL configuration. This central
PC is set up with the default license and is used to produce the anticipated test result.
The hardware used for the HiL setup’s work is quite similar to the hardware used for
the department’s routine testing. The department’s hardware is mostly unchanged
from the ECU under test; the software products offered by vector are connected to
various hardware items via licenses.
3 Driver Warning Data Storage
The data storage feature records details of numerous ECU resets, major errors, and
failures. Its main goal is to offer enough details so that the events can be replicated,
analyzed, or at the very least, the cause may be determined at the service garage,
during the study of the return warranty, or during the development test. Reason of
failure in the ECU are as follows:
• Resets that are generally not happening, like watchdog.

• Over current, over voltage and under voltage.
• Short circuit in the ECU.
• Software failures.
• Communication failure.
Driver warning test scenario is entirely dependent on the ECU issue. The red
warning lap illuminates whenever the electronic control unit experiences undesirable
changes or something dangerous, and alert the driver to the issue and reduce the
vehicle speed so that no new issues arise. Here, it is important to note that there are
some instances of degradation, the car has an issue if the degradation does not take
place. A separate DTC is received from the ECU if the primary switch, for example,
is not closing or opening properly.
The HiL test system is affordable, adaptable, and efficient. The brain of the HiL
is the host computer or desktop. Only the host computer is the center of all ongoing
activity. The host computer presents all the simulated results in the report in one
location for additional analysis.
3.1 Test Case Simulation in CANOe Under HiL Environment
Tools—hardware and software—are needed to prepare a test case for real-time simu-
lation of an automotive electronic control unit. Hardware in a loop system consists
of four main parts for the real time simulation:
• Host computer
• Loads
• Real ECU
• Signal processor.
A command-based editor application called vTESTstudio creates test case scripts
using Communication Access Programming Language (CAPL) code. Making an
independent test module that can be added to any generic testing environment is one
of the main assignments for the CANOe. The test suit for the test scripts implemented
in CANOe was created in the first step of the assignment in vTESTstudio. The
vTESTstudio integrated with CANOe by taking a script file in order to reproduce the
test case in Vector CANOe. The remote desktop is used to attach the file to CANOE.
The most recent hardware or electronic control unit is connected to the HiL config-
uration that can be shown as a node in CANOe; Fig. 2 shows the simulating node in
CANOe. The setting makes vTESTstudio and Vector CANOe HiL software test envi-
ronment possible. The supply board and all necessary components are connected in
a lab where the HiL simulator is located. The HiL used in test configuration receives
a remote-control power supply that it can control during the simulation. The HiL
system relates to the ignition system’s on/off functionality as well. If the ECU is
working fine, we will get positive response by adding 40 in the request service id.
Figure 3 shows the positive response from ECU.
An extra current is provided through the vector CANOe panel. When the current
limit reaches the upper limit of the expected range a warning lamp will trigger.
Figure 4 shows the warning lamp indication. If the current limit of the fault is
not decrease in the specified time duration the ECU itself open the main switch
to diagnose the fault and save the passenger live.
For a particularly complicated electrical powertrain control system, the HiL
system automates testing and collects the test results in one location. To test the ECU
under various conditions, external Hardware, such as a debugger, can be connected
Fig. 2 Node panel of ECU for simulation in CANOe
Fig. 3 Positive response received from ECU

Fig. 4 Warning lamp and control switch position
to a HiL system. HiL loads can controlled in accordance with the specifications of
the system test.
3.2 Simulation to Check the History of the Fault
The test setup should be connected to the most recent hardware sample running with
the proper software. The ECU testing standards are all up to date. After starting the
engine, the real-time simulation is activated. The car is now in running condition,
and all parameters have been established, including the date, time, speed, and supply
values (PS 0 and PS 1) (Fig. 5).
Fig. 5 Setting of parameters to start the simulation

Fig. 6 Opening of main switch after fault
PS 0 = 14 V, Load current = 3 A
PS 1 = 12.5 V,
Ignition = ON
Vehicle speed = 2 km per second
Distance travelled = 333,333 km
Date = 03-03-2022 (dd/mm/yy)
Time = 03-03-03 (h/min/s)
These numbers are utilized to satisfy the HiL simulation precondition stages in
order to use the diagnostics services to check the data that has been saved in the
ECU.
All the things that will be tested are simulated during the simulation process. Now
the current pulse is given in the ECU node to cause a failure in the circuit’s main
switch (open the switch) for a specific amount of time in order to generate the failure
in the ECU. If the main switch of the ECU opens the red warning lamp (kombi) status
went to 2. It suggests that an ECU must be diagnosed and that there is a problem
with the vehicle. Now we can check the history data for driver warnings using UDS
service id (UDS id—22).
Check the saved data using the unified diagnosis service id (UDS) after a failure;
Fig. 6 shows the kombi status 2 for warning, and the main switch status 6 which
indicate that the main switch is opened.
4 Result
The outcome of real-time simulation is compiled in a CANOe report that includes

information of all the simulated values and the cause of failures. The stored data
actual size is 2003 byte where first three byte indicate the positive response and
service id. The reason id 2 shows an overcurrent condition in the ECU. Figure 7
shows all the data related to the failures, and this data is stored in NVM for the
further analysis.
Fig. 7 CANOe report for driver warning with reason id

5 Discussion
HiL innovation and HiL simulation has quickly evolved into the most potent and
common method for desktop ECU testing. Today, sophisticated real-time models,
quick processors, and specialized HiL I/O are readily available on the open market.
Engine control, automated gearbox, vehicle dynamics control, and various other
vehicle modules are included in the HiL scope.
The HiL system described in this paper runs driver warning test case on ECU
node. Additionally, it offers the ability for diagnostics between the tester and the
ECU.
6 Conclusion
In this paper the Driver warning is checked by triggering the short circuit in the ECU
using vector CANOe and HiL Environment. In Vector CANOe, an input panel is
present, and the connected ECU can access the node attributes and properly transmit
CAN messages to nodes with node attributes, including all types of CAN signals
like vehicle speed, distance travelled, date, and time. The driver warning saved data
is 2000 bytes in size and contains all the simulate values with reason id of the event
to identify the cause for the main switch operation.
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1408
High Efficient Single Phase Active LED
Driver with Reduced Power Processing
Ramesh Babu Pallapati, Ramulu Chinthamalla, Sindhu Vutturi,

D. V. K. Abhinay, and Chandra Kiran Kumba
Abstract This paper presents a single-stage active LED driver circuit with power
factor correction, reduced power processing, and constant current output. This paper
tries to achieve the advantages of many two-stage driver solutions, which offer power
factor correction and constant output current regulation, with a single-stage approach.
Input power distribution can be done without extra switches. With a simple ripple
cancellation control logic, DC power and AC ripple power can be effectively matched,
allowing electrolytic capacitors to be replaced with long-life film capacitors for
increased LED driver lifespan. Reduced power processing design ensures that only
a part of the input power is processed twice rather than the entire amount as in the
case of two-stage driver circuits, thereby reducing the cost and size of the circuit.
A single input, two-output power factor correction converter configuration has been
discussed in this paper. On PSIM, a 30W simulation model is built and the results
are validated.
Keywords LED driver · Power factor · DC-DC converter · Reduced power

processing · Ripple power
R. B. Pallapati (B) · R. Chinthamalla · S. Vutturi · D. V. K. Abhinay · C. K. Kumba

Department of Electrical Engineering, National Institute of Technology Warangal, Warangal
506004, Telangana, India
R. Chinthamalla
S. Vutturi
D. V. K. Abhinay
C. K. Kumba
12 R. B. Pallapati et al.
1 Introduction
Light-emitting diodes (LEDs) have become very popular in the past few decades
because of their long life span, high efficacy, low cost, compact size, and ability to
deliver constant current output (COC). These light-emitting sources have replaced
conventional lightning devices in many applications, ranging from household to
industrial areas [1]. Their usage is also found in smart phones, LCD displays, street
lights, etc. Some research shows that LEDs can glow for 50,000–100,000 h while
maintaining 70% of their initial light output, which is almost 5 years. Since light
output is highly dependent on the input DC current fed to it, they need a current-
regulating circuit. And also, a rectification circuit is required to convert the sinusoidal
voltage to DC voltage when operated with the line supply. From this, it has been
concluded that LEDs must have a driver circuit providing constant current regulation.
These driver circuits can consist of active or passive components or a non-linear
regulator like a switched-mode power supply.
Further limitations imposed on the driver circuit by connecting to the line voltage
are power factor correction (PFC) with low input harmonics and rectification as
specified by IEC 61000-3-2 standards [2]. As LEDs are DC loads and are fed from
an AC supply, there is an imbalance between input AC power and output DC power [3,
4]. To compensate for the power imbalance, a storage element like a large inductor or
capacitor is incorporated [5]. The most common approach is to use bulk electrolytic
capacitors, which filter out the ripple in the voltage and are designed with respect
to the mains frequency and load supplied. But the use of electrolytic capacitors
can deteriorate LEDs life span because, through ageing, capacitors equivalent series
resistance increases and causes self-heating of the material [6]. Even a high-quality
electrolytic capacitor has an overall life time of 10 kh at operating temperatures [7].
Consequently, designing driver circuits without electrolytic capacitors has gained
much importance. At present, optimising circuit topologies and enhancing control
methods are the only other options available except electrolytic capacitors [8, 9].
Various single stage circuits are proposed to achieve unity power factor, constant
output current, and low input harmonics with greater efficiency.
For many decades, researchers have been trying to come up with different LED
driver solutions to meet the LED requirements. Various solutions, such as single-
stage, multiple-stage drivers have been proposed and implemented. It has been
observed that single-stage drivers are easy to work on as they are of low cost, have
a low component count, and are easy to install, especially where there is a space
constraint [10]. But single-stage converter topologies cannot be optimised to achieve
unity power factor, long life span, and low output ripple altogether. Later, multi-
stage drivers have been proposed that are designed to perform all the above tasks.
Multi stage drivers can be independent or integrated. The overall efficiency of these
drivers is dependent on the individual efficiencies of the converters employed. As it
involves multiple stages, each converter can be designed to perform multiple require-
ments together. Independent multistage drivers are able to reduce the bus capacitance
by allowing a high PFC bus voltage. Figure 1a shows a two-stage cascaded circuit,
High Efficient Single Phase Active LED Driver with Reduced Power Processing 13
Fig. 1 a Cascaded driver

configuration b bidirectional
power processing driver
configuration c
unidirectional power
processing driver
configuration d driver with
two output PFC
where stage 1 is designed to perform PFC and stage 2 is for current regulation [11].
A buffer capacitor buffers the ripple power. But this architecture has low efficiency
as power is reprocessed at each stage. Besides that, due to the increase in number of
components, the driver is expensive and requires a dedicated control circuit for each
converter, which could increase switching losses. Another architecture with a bidi-
rectional converter is proposed to increase the efficiency, as illustrated in Fig. 1b. This
circuit employs a PFC stage and a bidirectional DC-DC converter placed parallel to
the output. This bidirectional converter produces the compensating power to reduce
double line frequency ripple [12, 13]. This ripple power is almost 32% of total power,
Fig. 2 Proposed topology diagram with two output PFC and DC-DC regulation
therefore decreasing the power to be processed and increasing efficiency. Another

driver circuit having a unidirectional converter is proposed in [14–16], as shown in
Fig. 1c. Here, the ripple power is only processed once, making it more efficient than
a bidirectional scheme. However, the use of switches and diodes for power distri-
bution incurs additional losses. All the above power processing schemes use two
stages for power processing, leading to the use of an extra storage element. Another
power processing scheme using a unidirectional converter was proposed earlier, as
shown in Fig. 1d, which has two output ports at the PFC stage. Many schemes were
designed using inductances for power distribution. However, analogue controllers
are required to reprocess power. There are several reduced power processing-stage
driver configurations addressed in the literature [17, 18].
This paper proposes a single-stage topology with two converters integrated to
achieve a unity power factor, as shown in Fig. 2. The proposed topology consists of
two output PFC stage and a DC-DC stage. The distribution of output PFC power
is carried out using series capacitors, which will be explained in the following sec-
tions. This paper discusses a single-stage driver solution where a buffer capacitor is
connected in series with one of the converters.
This paper is organised as follows: The principles of operation and operating
modes are explained in Sect. 2. Section 3 discusses the design and control mechanisms
for the considered converter configuration. In Sect. 4, results from the simulation are
discussed, and Sect. 5 concludes the paper.
2 Principle of Operation
Considered topologies for PFC and power control using fly-back and buck-boost
converters are shown in Fig. 3. It has an input port, which is an AC supply, a diode
bridge rectifier, which connects the input to a fly-back converter, which acts as a PFC
circuit, which is connected in series to the source..Cdc and.Co are two output channels
Fig. 3 Proposed topology of flyback and buck-boost converters
of the PFC stage. Buck-boost converter acts as a power control converter, processing
energy from the DC bus capacitor to the load. As per this configuration, total input
power is processed by the fly-back converter, which in turn is split between the buffer
capacitor and the output capacitor.
Part of the power is directly connected to the load, whereas the other part is
further processed by a buck-boost converter for constant output current regulation
and then supplied to the load. In this design, the entire power is processed once by
the PFC stage, and only some part of the power is reprocessed by the PC converter.
Overall, a maximum of 50% power is processed twice, which improves efficiency
when compared to a cascaded configuration. In order to avoid the complexity of
the hardware system for the division of power to the load and DC-DC stage, two
capacitors are connected in series at the output of PFC converter, which distributes the
power to be processed. Capacitor .Cdc acts as the source for the buck-boost converter,
performing the DC-DC regulation, and at the same time, it is also part of the output
capacitor of the fly-back converter, whereas capacitor .Co acts as an output capacitor
for a buck-boost converter and another output of a PFC converter. The amount of
power to be shared by two capacitors is to be designed accordingly to meet the
efficiency requirements.
To improve efficiency, reduce the reprocessed power through the buck-boost con-
verter, as this power is processed twice. So, the power transfer through this converter
must be kept as low as possible. But at the same time, it must supply the losses
occurring during the DC-DC regulation, and the sum of the output power of both
converters must nullify the AC component, so a constant DC power is expected.
Keeping all the limitations in consideration, it is suggested to split the power in
half across capacitors. That is, half of the output power of the fly-back converter
is directly fed to the load through .Co , and the other 50% is fed to the buck-boost
converter. The important task of the LED driver is to have constant DC output power
to be given to the load. This is achieved using DC-DC regulation. Fly-back converter
develops current .i p f c (t) and the other converter develops current .i pc (t). These two
currents, when added across the load, produce a constant current without any ripple.
The fly-back output power has the same wave shape as its input power and varies
at double frequency as the power factor is nearly equal to unity. Out of which some
part is directly fed to load, let’s say . pd (t) , and other part . pdc (t) is fed to buck-boost
converter. The addition of the power output of the DC/DC converter. pc (t) (cancelling
power) and direct power gives the overall load power, which is nearly constant.
2.1 Operating Modes and Waveforms
Based on the operating principle and possible converter configurations, a topology

using a fly-back converter as a PFC and a bust-boost converter as a DC-DC converter
is chosen in DCM mode. There are four operating modes, as shown in Fig. 4, along
with their waveforms given in Fig. 5.
Mode I (.t0 - .t1 ): In this mode, both switches on both converters are turned on at .t0
as shown in the Fig. 4a. The primary winding inductance of a fly-back converter gets
charged by the input voltage. The . L p c is charged by DC bus voltage. .Co supplies to
the load. This mode ends when the switch . S2 is opened.
Mode II (.t1 - .t2 ): Current flows through the primary winding inductance of the
fly-back converter . L m1 p f c continues charging. Stored energy in . L pc is fed to .Co and
to the load through diode . Db as shown in the Fig. 4b. Switch . S1 is turned off at . D1 Ts
and the peak current through . L m1 p f c that is .i L m1 peak (t) in this mode can be estimated
as follows:
Vm | sin ωt|D1
.i inpk = (1)
L m1 p f c f sw
where . D1 is the duty cycle of . S1 and . f sw is the switching frequency when . S1 is

turned off, Input current and primary inductor current are equal to “0”. Therefore,
the average input current during a switching cycle is given as:
Vm | sin ωt|D12
i
. inavg = (2)
2L m1 p f c f sw
From this equation, Input current and input voltage are proportional to each other.
High power factor is easily achieved with constant duty cycle.
Mode III (.t2 - .t3 ): As shown in Fig. 4(c), in this mode both switches are in the
off state, and stored energy in the secondary of fly-back is discharged through diode
. Da . Both capacitors go through the charging phase. And the inductor . L pc continues
discharging energy to the load.

Mode IV (.t3 - .Ts ): In this mode as shown in the Fig. 4d, both inductors are com-
pletely discharged. .Cdc has no path to discharge, whereas .Co starts delivering energy
to the load.
Fig. 4 Operating modes of

considered topology
2.2 Analysis of Power Processing
The output power of the PFC fly-back converter is distributed between the load and
the Buck-Boost converter. The overall efficiency of the driver is dependent on the
amount of reprocessed power. Distribution has an effect on achieving constant output
power.
If . pop f c (t) is fly-back output power, .Co and .Cdc are two capacitor channels for
distribution. Let .Vo and .Vdc be the output voltage and DC bus voltage, respectively,
and power is shared in the ratio p and (1-p) across the DC-DC converter and load,
Fig. 5 Wave forms of driver

circuit
respectively. Then,
Vdc
. p= (3)
Vo + Vdc
Similarly, where . pdc (t) is power fed to the buck-boost and . pd (t) is power sent to the
load, it is required to lower the reprocessed power through the buck-boost converter
to enhance efficiency. As a result, the power split via buck-boost must be kept as
low as feasible. However, it must also supply the losses that occur during the DC-
DC conversion. The sum of the output power of both converters must cancel out the
ripple component, and a constant DC power is expected as shown in the Fig. 6. Based
on the above constraints, half of the output power of the fly-back converter is fed
directly to the load via .Co , while the other half is fed to the buck-boost converter.
Therefore, if “p” is the conversion ratio defined, where,
pdc (t)
. p= (4)
pdc (t) + pd
Now p must be close to 0.5. Reprocessing power should be greater than the power
directly fed to the load to balance the losses in regulation.
Fig. 6 Power flow diagram

in line period
. pdc (t) > pd (t) (5)
The PFC fly-back converter’s voltage gain is .V f b.
Vo + Vdc
. Vfb = (6)
Vm | sin ωt|
The PC buck boost converter’s voltage gain is .Vb /b.
Vo
. Vb/b = (7)
Vdc
The driver circuit’s voltage gain is .Vd .
V f b Vb/b
. Vd = (8)
1 + Vb/b
As a function of voltage gain, “p” is expressed as
1
. p= (9)
1 + Vb/b
Based on the value of p, PFC fly-back converter output can be divided into two parts.
The p times power is stored by DC bus capacitor, and the (1-p) times input power is
transmitted to the LED load. The driver’s total .η can be obtained as:
.η = pη f b ηb/b + (1 − p)η f b (10)

substituting (9) in (10),
1 1
.η= η f b ηb/b + (1 − )η f b1 (11)
1 + Vb/b 1 + Vb/b
ηb/b + V f b2
.η = ηfb (12)
1 + Vb/b
where .η f b is the PFC fly-back converter’s efficiency, and .ηb/b is the PC buck boost
converter’s efficiency. According to (12), the proposed method is more efficient than
the cascaded method, i.e. .η f b ηb/b . The output power of a DC-DC converter that
cancels the direct power is denoted as the cancelling power . pc (t), which is equal to
. pc (t) = Po − pd (t) (13)
where . Po is the LED load power.
3 Control Logic
3.1 Control Scheme
Switching of converters is done using PID controllers, as shown in Fig. 7. The aver-
age DC capacitor voltage must be constant. Fly-back converter switching operation
is controlled by comparing the voltage across the DC bus capacitor with a reference
value. The error signal generated is given to the PI controller, which, when compared
with the carrier frequency signal, produces the duty cycle . D1 of the PFC converter to
control switch. S1 . Similarly, buck-boost converter switching is controlled by compar-
ing load current with the required output current as a reference value, as this converter
Fig. 7 Design of control loop for a fly-back converter and b buck-boost converter
is designed for constant output current regulation. The PI controller receives an error
signal and then generates the buck-boost converter’s duty cycle,. D2 . PI control values
are chosen accordingly.
4 Simulation Results
The considered topology is tested for 30 W output power of LED operated at the
following specifications shown in Table 1.
Figure 8 shows the input voltage .vin (t) and current .i ac (t). It is noted that the
input power factor of 0.99 is achieved with input current harmonics of 9%, which
satisfy the IEC 6100-3-2 standards. The input voltage, DC bus capacitor voltage, and
Table 1 30 W prototype design parameters

Parameter Specification
Input voltage .vin (t) 110 V RMS AC
Supply frequency, f 50 Hz
PFC inductor, . L mp f c 300 .µH
PC inductor, . L pc 150 .µH
Output capacitor, .Co 20 .µF
Output capacitor, .Co 20 .µF
DC bus capacitor, .Cdc 20 .µF
Output current, . Io 0.33 A
Output voltage, .Vo 90 V
Switching frequency, . f sw 50 kHz
Fig. 8 Input AC voltage .vin (t) waveform, AC current .i in (t) waveform

Fig. 9 Input AC voltage .vin (t), Dc bus voltage .vdc (t), and output DC voltage .vo (t)
Fig. 10 Over view of PFC transformer current .i Lm1 p f c (t), and PC inductor current .i L pc (t)
output voltage are shown in Fig. 9. The overview of PFC inductor current and PC
inductor current is shown in Fig. 10. The primary current .i Lm1 p f c (t) and secondary
current .i Lm2 p f c (t) of PFC inductor are shown in Fig. 11. The current .i L pc (t) of the
PC inductor is shown in Fig. 12. The voltage across the switch . S1 , .vds1 (t) and current
Fig. 11 Primary winding current of PFC transformer .i Lm1 p f c (t), and secondary current of PFC
transformer .i Lm2 p f c (t)
Fig. 12 PC inductor current .i L pc (t)
flowing through the switch . S1 , .i ds1 (t) are shown in Fig. 13. It is observed from the
waveform that zero-voltage switching is achieved. The voltage across the switch . S2 ,
.vds2 (t) and current flowing through the switch . S2 , .i ds2 (t) are shown in Fig. 14. It is
observed from the waveform that the zero voltage switching is achieved. The output
voltage .vo (t), and current .i o (t) are shown in Fig. 15. The output current is constant
with a peak to peak ripple of 1.84%. The simulation results showed that, at full power,
the driver achieved a peak efficiency of 98%.
Fig. 13 Voltage across switch . S1 during turn off .vds1 (t), and current flowing through the switch
during turn on .i ds1 (t)
. S1
Fig. 14 Voltage across switch . S2 during turn off .vds2 (t), and current flowing through the switch
during turn on .i ds2 (t)
. S2
5 Conclusion
An active single-stage LED driver circuit is proposed in this paper. It has the advan-
tages of improved efficiency and low size over single-stage approaches. A reduced
power processing scheme improved the overall efficiency. Because only some part
of the power is processed twice by the regulation converter and the other part is
directly fed to the load, the complexity of designing a converter for power division
is eliminated by employing two series capacitors, thereby reducing the switching
Fig. 15 Output DC voltage .vdc (t), and output DC current .i o (t)
losses. The size of the entire converter is small, as the DC/DC converter processes
only 50% of power. A 30W PSIM simulation was built and tested. The driver had a
peak efficiency of 98% and a power factor of 0.99 at full power.
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Implementation of Model Predictive
Current Control Technique for Single
Phase Four Level Grid Connected
Asghar Inverter
Dipty Chandrakar , Bhagwan K. Murthy ,

and Aratipamula Bhanuchandar
Abstract This paper presents a Model Predictive Current Control (MPCC) tech-
nique for 1-phase 4-level Grid Connected Asghar Inverter (GC-AI) and basically it
consists of four unidirectional switches, two discrete diodes, four capacitors, and one
dc source. It offers self-balancing of capacitors, boosting ability, and well suitable
for photovoltaic applications. In grid connected operation, to inject the grid current
conventional dq-frame current control technique requires more number of trans-
formation blocks, complicated tuning proportional-integral parameters, modulation
stage and finally it produces sluggish transient response. To curtail the complexity
of control, a simple MPCC technique with needless modulator stage has been
implemented without consideration of weighting factors, and it also provides an
excellent dynamic performance. The objective of tracking reference current along
with balancing of capacitor voltages have been explained vividly using predictive
algorithm in both RL-load and grid-connected cases through PLECS platform.
Keywords Model predictive current control · Asghar inverter · Dq-frame current

control · Modulation stage · Grid connected inverter
1 Introduction
In the power electronics technology, the Reduced Device Count (RDC) Multilevel
Inverters (MLI) are commonly employed in solar, wind energy applications. Gener-
ally MLI creates staircase waveform that mimic the sinusoidal wave [1]. In literature,
D. Chandrakar (B) · B. K. Murthy · A. Bhanuchandar

Electrical Engineering Department, NIT Warangal, Hanamkonda, Telangana, India
B. K. Murthy
A. Bhanuchandar
28 D. Chandrakar et al.
there are three types of conventional MLIs that have been existed which are Neutral
point clamped (NPC), Flying Capacitor (FC), and Cascaded H-Bridge (CHB). In
order to determine the size of the inverter, it is typically important to consider the
number of switches, gate drivers, discrete diodes, capacitors, DC sources, and Total
Standing Voltage (TSV). Generally, switching device costs are usually set by TSV. For
producing 4-level output voltage, the NPC requires more number of discrete diodes
and the FC requires more number of floating capacitors. In FC-MLI, the capacitors
must be pre-charged to operate in traction applications [2]. In conventional MLIs,
CHB has more modular structure but it needs more isolated DC sources [3, 4]. The
topology [5] produces 4-level output voltage with one DC source but it requires more
number of power electronics switches and provides no voltage gain. The topology
[6] needs separate backend H-bridge in respective three phase operation thereby the
TSV become more.
The topology [7] is based on the switched capacitors (SC) and produces 4-evels in
output with single DC source. It provides voltage boosting and self-voltage balance
but TSV is high. Four levels are produced by the topology [8] using only one DC
source and three DC link capacitors. The capacitor voltages in this configuration are
balanced but provides unity voltage gain. In topology [9], the basic unit generates five
level output and by combining number of such units it is possible to generate more
number of levels but back-end full H-Bridge is required for negative level production
thereby TSV value is very high. The topology [10] produces 13-levels with single DC
source and 12 switches. It offers six times boosting potential and self-balancing of
SCs but TSV is 36V dc . The topology [11] produces nine levels with single DC source
and two SCs. It provides two time boosting ability and capacitors are self-balanced
but TSV is high which is 20V dc .
The AI topology [12, 13] consists of four unidirectional switches, two diodes,
one DC source, and four capacitors. They produce four levels in the output, provides
more than unity voltage gain and self-balancing of capacitors. In literature [10–
12], for grid connected system authors are utilized conventional dq-frame current
control technique along with PWM modulation. But this control technique requires
more number of transformation blocks, complicated tuning proportional-integral
parameters, modulation stage and finally it produces sluggish transient response.
To diminish the complexity of control, a simple MPCC technique with needless
modulator has been implemented without consideration of weighting factors. The
main objective of this paper is track the reference current along with balancing
of capacitor voltages have been explained clearly using MPCC technique in both
standalone and Grid-Connected Cases (GCC) for AI topology. The employment
of a MPCC technique improves transient response and grid current regulation in
accordance with reference current.
In this paper, Sect. 2 describes brief operation of Asghar Inverter, Sect. 3 describes
implementation of MPCC, Sect. 4 represents simulation results, Sect. 5 represents
comparative study between dq-frame and MPCC control technique then finally, and
Sect. 6 represents conclusions.
Implementation of Model Predictive Current Control Technique … 29
2 Brief Description and Operation of Asghar Inverter (AI)
The Asghar Inverter-AI [12] synthesis staircase four level waveform in the output
and provides boosting factor as 1.5. AI consist one DC source, four unidirectional
switches, two diodes, and four capacitors from which two are dc link capacitors
(C dc1 , C dc2 ) and other two are switched capacitors (C 1 , C 2 ). Schematic of AI is
shown in Fig. 1. Here, switches (S 1 , S 2 ) and (S 3 , S 4 ) are of complementary nature.
Switching operation of AI is divided into four modes which are listed in Table 1.
In this, ‘1’ represents ON state of Switch, ‘0’ represents OFF state of switch, ‘C’
represents charging of capacitor, and ‘D’ represents discharging of capacitor. Capac-
itors are self-balanced by series–parallel technique with the dc source and eliminates
sensors requirement. In this topology, boosting factor is 1.5 with single source, so this
topology can be used for low voltage application like PV application etc. Normally,
TSV is the sum of maximum standing voltage of all the switches. The standing
voltage of (S 1 , S 2 ) are 2 × V dc , (S 3 , S 4 ) are 2 × 2V dc , and standing voltage of (D1 ,
D2 ) are 2 × V dc . So TSV becomes 8V dc and finally per unit TSV is 5.33 pu. Due to
the continuous charging and discharging of SC, high inrush current is present in SC
based MLIs but in this topology, inrush current is low by applying MPCC technique
and that small inrush current further can be reduced by inserting very small value of
inductor (in terms of µH) in series with two diodes.
Fig. 1 Single-phase
4-level-grid connected D1
Asghar inverter
Cdc1 S1 C1 S3
Vdc
R
Cdc2 S2 C2 S4 L
Grid
D2
Table 1 Switching table

S. No [S 1 , S 2 , S 3 , S 4 ] C1, C2 Level output
1 [1 0 1 0] D, C 1.5V dc
2 [0 1 1 0] C, NE 0.5V dc
3 [1 0 0 1] NE, C −1.5V dc
4 [0 1 0 1] C, D −0.5V dc
3 Implementation of MPCC Technique-Standalone

(RL-Load) and Grid Connected Cases (GCC)
MPCC has number of benefits including multivariable control, applicability to a

variety of systems, simple constraint treatment, dead time compensation, and easy of
understanding and implementation even though the quality of the controller is directly
influenced by the system model [14]. Moreover, once proper system modelling is
done, MPCC is reliable and simple to implement. One of the best known uses of
these controllers is to command the current in accordance with the reference current
[15]. The MPCC predicts the behaviour of the system based on its current dynamics.
In order to control the load current, the inverter and the load are modelled, and
the next switching state is then anticipated based on the current output load current
[16]. According to the cost function, the switching states are anticipated so that the
difference between the reference value and the forecast value is as little as possible.
The cost function describing the future behavior of the system taking into account
references, upcoming actuations, and states [17, 18].
3.1 MPCC Technique: RL-Load Case
The flowchart for standalone (RL-load) is same as Fig. 2 but only grid term ‘V g (k)’
term as zero. Here, io (k) represents the inverter output current, T s represents the
sampling time, ‘R’ is the load resistance, ‘L’ is the inductor, and ‘g’ represents
the cost function. In MPCC technique, firstly load and inverter are modelled then
to control the load current, load model is should be discretized by “Forward Euler
approximation” method. After modelling is completed, the load current is sensed then
according to the load current, and next sampling interval current has been predicted.
Then predicted current is subtracted with the reference current and result is stored.
Now, the same process has been repeated for all the states and which state having low
value of cost function has been selected as optimized state and applied to the inverter.
By utilizing MPCC technique, it is possible to get an excellent transient response with
an excellent tracking capability. However, only the problem with MPCC technique
is that it is operating under variable switching frequency of operation inherently. But
this problem also can eliminate easily by utilizing continuous control set optimization
[19].
3.2 MPCC Technique: GCC
Whenever inverter is connected to the grid, some specifications should follow that is
called as “grid-code” requirements. Respective MPCC flowchart for grid connected
Fig. 2 Flowchart: MPCC technique
mode is shown in Fig. 2. Here, V g represents grid voltage which is completely sinu-
soidal with frequency of 50 Hz. By using flowchart, firstly grid current is sensed,
then according to sensed current next sampling interval current has been predicted
using discrete load model equation. Next, the reference current has been subtracted
to the predicted grid current and result is stored. This process is repeated for each
switching state and which switching state having low value of cost function is selected
as optimum switching state. Above process comes under inner loop, then after selec-
tion of optimum state actuation is applied to the inverter and this process shown
in outer loop. In the sampling interval, all of these loop process has been finished.
Generally, as number of switching states will increases then computation for selec-
tion of optimize state will also be increase. In AI, only four switching states are
present then computational burden becomes very low while using MPCC technique.
Table 2 Parameters for

S. No Specifications Value
simulation: RL-load case
1 V dc 266.66 V
2 Boosting Factor (BF) 1.5
3 R 100 Ω
4 L 80 mH
5 C 1 , C 2 , C dc1 , C dc2 2200 µF
6 Reference peak currents 3.5 A and 1.5 A
4 Simulation Results-MPCC Technique
4.1 RL-Load Case: Simulation Results
The respective simulation parameters with consideration of RL-load is listed in

Table 2. To get peak value of 400 V in the output of AI, the value of V dc has taken
266.66 V. MPCC control scheme has been used to the AI. Simulation results for RL
load with step change of reference peak value of current from 3.5 A to 1.5 A at t =
0.12 s has been shown in Fig. 3. In Fig. 3a red colour represents the actual output
current and yellow colour represents the reference current. Figure 3b shows self-
balancing characteristics of SCs, and it is balanced almost at 266.66 V. By changing
the reference current, inverter is producing four levels in the output with changed
width of levels which is shown in Fig. 3c.
In this control scheme, automatically output voltage level has been produced
according to the peak reference current. Figure 3d, e shows capacitor current, and
Fig. 3f shows input current of the inverter. Figure 4 shows the zoomed view of
reference and actual currents. From results conclusion can be drawn that actual
current is following the trajectory of reference current, inrush current is also low,
SCs are self-balanced, and transient response is also excellent.
4.2 Grid Connected Case- Simulation Results
Table 3 displays the simulation parameters taking the grid into account. MPCC
technique has been used with step change of Power Factor (PF). Simulation results
for step change of PF from unity to 0.9 lagging at t = 0.06 s is shown in Fig. 5.
In Fig. 5a and Fig. 6a green colour shows grid voltage, red colour shows actual
grid current, and yellow colour shows reference current. Peak value of the reference
current is considered as 10A and in this, outside gain block value 10 is used for
visibility purpose then peak value become 100A. Self-balancing features of SCs are
shown in Fig. 5b, and they are almost balanced at 266.66 V. Figure 5c shows output
voltage with four levels for unity and lagging PF. Figure 6 shows simulation results
for step change of PF from unity to 0.9 leading at t = 0.06 s. The self-balancing
(a) Reference(3.5A to 1.5A) and Actual Currents

4
2
0
-2
-4
(b) Vc1(Volts) and Vc2(Volts):Self-Balanced
267.0
266.8
266.6
266.4
266.2
(c) Inverter Output Voltage(V)
500
-500
(d) Idc(A)
20
(e)Ic1(A)
20
(f)Ic2(A)
20
0.06 0.08 0.10 0.12 0.14

Time(Seconds)
Fig. 3 Step change in reference current peak value: RL-load case
features of SCs are shown in Fig. 6b, here it is almost balanced at 266.66 V. Inverter
output voltage is displayed in Fig. 6c with four levels for unity and leading PF. The
harmonic spectrum of the grid current and inverter output voltage in GCC is displayed
in Fig. 7.
The maximum value of Inverter Output Voltage (IOV) at fundamental frequency
is 326.1 V and THD is 50.47%. Similarly, 9.92 A is the maximum grid current at
3.6
Inverter Output
Current(A)
3.4
Actual
Current (A)
3.2 Reference
Current (A)
400
Inverter Output
200
Voltage(V)
-200
-400
Time (seconds)
Fig. 4 Zoomed view of reference and actual currents-RL load case
Table 3 Parameters for

S. No Specifications Value
simulation-GCC
1 V dc 266.6 V
2 Grid voltage (peak) 325 V
3 Ts 10 µs
4 Grid frequency 50 Hz
5 Rgrid 0.01 Ω
6 L-filter 3 mH
7 Injected grid current (peak) 10 A
8 Capacitors 4700 µF
fundamental frequency has been obtained, and THD is 0.32% which meets IEEE-
1547 standards. From results, it is concluded that MPCC technique is working fine
for all power factor and having very good transient response. Here, UPF means,
injecting active power into the grid. Similarly, leading/lagging PF means reactive
power support also has been obtained. Finally, it satisfies the grid code requirements.
(a) Vgrid(V) and Igrid(A)-Ref. and Actual Currents

400
200
-200
-400
(b) Vc1(V) and Vc2(V):Self-Balanced
268
267
266

500
-500
0.00 0.02 0.04 0.06 0.08 0.10 0.12
Time(Seconds)
Fig. 5 Step change in PF from unity to 0.9 lagging-GCC results
5 Comparative Study Between Conventional dq-Frame

Current Control and MPCC Techniques
Table 4 shows comparison between conventional dq-frame current control and MPCC
technique. Generally, in dq frame technique more transformations, PI controllers
and modulation stage are needed while going to grid connection. While using PI
controllers, transient response is not generally good and tuning also inherently makes
complex to meet the desired value. However, only advantage of this dq-frame is it
provides fixed switching operation but computational burden is more. In literature,
many other linear control techniques are available but these are complex.
To alleviate this complexity, a simple and intuitive MPCC has been used in this
manuscript. It provides an excellent transient response without any weighting factors
and modulator. In both standalone and GCC, the AI given an excellent results in
dynamic operation. From the below table, it is concluded that MPCC is more advan-
tageous than conventional current control technique. But, MPCC technique’s key
issue is changeable switching frequency operation.
(a) Vgrid(V) and Igrid(A)-Ref. and Actual Currents

400
200
-200
-400
(b) Vc1(V) and Vc2(V):Self-Balanced
267.5
267.0
266.5

500
-500
0.00 0.02 0.04 0.06 0.08 0.10 0.12
Time(Seconds)
Fig. 6 Step change in PF from unity to 0.9 leading-GCC results
(a) IOV-Volts (b) Grid Current(A)

0.2
Mag(% of Fundamental)
Mag(% of Fundamental)
1
0.15
0.8
Fundamental (50Hz) = 326.1V , Fundamental (50Hz) = 9.92A ,
0.6 THD= 0.32% @MPCC
0.1 THD= 50.47% @MPCC
0.4
0.05 0.2
0 0
10 20 30 40 50 60 70 80 90 100
0 100
0 20 40 60 80 Harmonic order
Harmonic order
Fig. 7 Harmonic spectrum of IOV and injected grid current–GCC

Table 4 Comparative study between conventional dq-frame control and MPCC technique
S. No dq-frame current control MPCC technique
1 Nature of controller is linear Nature of controller is non linear
2 PI controller is used for error control Cost function is used for error control
3 Implementation platform can be analog or Implementation platform is digital only
digital
4 PWM modulation technique is required No modulation technique is required
5 ‘F sw ’ is fixed in linear control ‘F sw ’ is variable in MPCC
6 Constraints inclusion is not possible Constraints inclusion is possible
7 Linear control is complex due to presence of Simple and intuitive
PI controller, PLL block, transformation
block and gate pulse generating circuit
8 Transient performance is moderate Transient performance is excellent
6 Conclusion
In this paper, a MPCC technique has been applied to 1-phase 4-level AI and explained
thoroughly both RL-load and GCC. A comparative study is also done between
conventional current control technique and MPCC technique. Explanation of simu-
lation results in RL-load case and GCC is done with step change of peak reference
current and step change of power factors respectively. The SCs are self-balanced
without use of the additional circuits, sensors, complicated control schemes, and
capacitors having less ripple voltage. From results conclusion can be drawn that
dynamic response of the system is excellent. The GC-system with MPCC tech-
nique is supporting all power factor cases, and actual current is well followed the
trajectory of reference current. But, MPCC technique key issue is variable switching
frequency of operation. This difficulty can be avoided by adopting continuous control
set technique, which is the future scope of work.
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A Low Voltage Stress Switched-Capacitor
Based 7-Level Boost Multilevel Inverter
Gangadhar Dhal, Kasinath Jena, Lipika Nanda, Pradeep Ku. Sahu,

Kumaresh Pal, and Aditya Prasad Padhy
Abstract This study represents a 7-level DC-to-AC converter with an increase in

output voltage. The output voltage can be increased through the use of Switched
capacitor technologies, such as the series connection of charged capacitors and a DC
source. The significant features of the proposed design include the capacitors’ voltage
self-balancing and ability to boost the output voltage and reduced voltage stress on
the switching components. Without an H-bridge circuit at the back end, the proposed
inverter can provide bipolar voltage. A detailed comparison with existing switched
capacitor topologies is used to elucidate the benefits of the proposed design. The
proposed design’s loss analysis has been studied in detail. The effectiveness of this
design is 97.32%. The effectiveness of the proposed 7-level design in both steady state
and transient conditions is validated by extensive simulation testing using MATLAB/
Simulation software.
Keywords Bipolar inverter · Multilevel inverter · Switched-capacitor · Gain
G. Dhal · L. Nanda · P. Ku. Sahu

School of Electrical Engineering, KIIT University, Bhubaneswar, India
P. Ku. Sahu
K. Jena (B) · K. Pal · A. P. Padhy
Department of Electrical and Electronics Engineering, ARKA JAIN University, Jamshedpur,
Jharkhand, India
K. Pal
Department of Electrical Engineering, N.I.T., Jamshedpur, Jharkhand, India
40 G. Dhal et al.
1 Introduction
Multilevel inverters (MLIs) play an important role in the wind, solar, fuel cell, and
electric vehicle energy conversion systems [1]. The combination of direct current
(DC) sources, active switches, and power diodes in these converters allows for the
generation of a staircase voltage waveform with little Total Harmonic Distortion
(THD). In general, switches in MLIs can endure lower voltage stress than their 2-level
counterparts [2]. Additionally, MLIs benefit from a smaller output filter and lower
total losses [3]. However, when the number of layers rises, common MLIs like Flying
Capacitor (FC) and Neutral Point Clamped (NPC) face difficulties with capacitors’
voltage balance [4, 5]. Cascaded H-bridge (CHB) MLIs necessitate individual DC
supplies [6]. Many applications necessitate high AC voltage yet can only connect
to low-input DC sources. For many topologies, a transformer or inductor is used
when the input voltage is less than the output voltage. This is the case in applications
like grid-connected DG systems [7], electric vehicles [8], and renewable sources [9].
However, the aforementioned systems converters are cumbersome and heavy due to
the use of transformers and inductors [10].
In order to generate a greater AC voltage in a stair-like pattern, researchers look for
MLI structures that utilize a mix of DC sources and capacitors connected to a variety
of power semiconductors. Because of this need, inductor-less and transformerless
topologies have emerged. The total standing voltage (TSV ) and the number of DC
sources used in these inverters must be kept low to protect the semiconductors. In
order to enhance the voltage levels, new converters based on a switched-capacitors
structure have been developed [11–14], but they place a significant amount of stress
on the switching components due to the high voltage. Although [15] presents a
generalized MLI with self-balancing capabilities and the large number of components
required makes this solution impractical. Higher-frequency uses of this switched-
capacitor inverter are described in [16]. Due to the H-bridge, the inverter cannot be
used for applications requiring high voltage.
To get a voltage gain of two, the authors of [17] employ a nine-tier design
with eleven switches and two capacitors. Additionally, the topology in [18] may
improve the gain. However, more switching components are needed in generalized
SC architectures. According to [19], a five-level flying capacitor structure requires
ten switches and four capacitors. Since there are more switches, it’s less desirable in
practice. A topology that has been proposed in [20] has the capability of synthesizing
a 13-level voltage waveform with a boosting factor of six. The topology is distin-
guished by a number of distinctive characteristics, including its inherent capacity for
self-balancing, a high boosting factor.
A Low Voltage Stress Switched-Capacitor Based 7-Level Boost … 41
Significant characteristics of the suggested architecture include the ability to

generate bipolar multi-level voltages, the capacity to raise the voltage, and the
inherent self-balancing of capacitors’ voltage and reduced voltage stresses.
2 Proposed SC Design
Figure 1 depicts the proposed inverter circuit. Two capacitors (C1 , C2 ), and eleven
switches (S1a , S2a , S1b , S2b , S1c, ∼ S4c , S1d , S2d , S5e ,) comprise the proposed archi-
tecture. The proposed design consists of two kinds of switches IGBT with an antipar-
allel diode and IGBT without any series or antiparallel diode. The switch S5e , presents
a bidirectional switch. Based on Fig. 1, the suggested inverter can transition between
eight different modes. The γ x switching states are shown in Table 1 where x=
(0:1:2:3:4:5:6). Each switching state is associated with a different level of output
voltage Vo that has been generated by the inverter. Table 2 depicts the voltage stress
on switching components.
S1c
+
S1a S1b _ C1 S1d
S 3c
+
VDC _
S4 +
S2a S2b c
_ C2 S2d
V0 S2c
_ +
Load
Fig. 1 Proposed 7-level boost switched-capacitor MLI
Table 1 γ x switching states

γx S1a S2a S1b S2b S1c S2c S3c S4c S1d S2d S5e C1 C2 Vo
0 0 1 1 0 0 1 0 0 0 1 1 – C 0
0 1 0 0 1 1 0 0 0 1 0 1 C – 0
1 0 1 0 1 1 0 0 0 1 0 1 C – +V DC
2 0 1 1 0 0 1 0 0 1 0 1 D C +2V DC
3 0 1 1 0 0 0 0 1 1 0 0 D D +3V DC
4 1 0 1 0 0 1 0 0 0 1 1 – C −1V DC
5 1 0 0 1 1 0 0 0 0 1 1 C D −2V DC
6 1 0 0 1 0 0 1 0 0 1 0 D D −3V DC
42
Table 2 Voltage stresses on switching commoners

Switch S1a S2a S1b S2b S1c S2c S3c S4c S1d S2d S5e C1 C2 Vo
Str ess +V DC +V DC +V DC +V DC +2V DC +2V DC +V DC +V DC +2V DC +2V DC +2V DC – C 0
G. Dhal et al.
2.1 Description of Switching States
This section provides a detailed description of the different switchable states:

(a) γ 0 : (V0 = 0) The inverter generates V0 = 0 with the switches S2a , S2c , S2d on.
It is feasible to charge capacitors C2 with a magnitude of VDC by the way of
one separate path established by the switches S1b S5e shown in Fig. 2.
(b) γ 0 : (V0 = 0) Voltage at the output, V0 = 0, is produced when switches S1a ,
S1c and S1d are activated. Capacitor C1 have their voltages adjusted via the
connections S2b and S5e , yielding the results VC1 =VDC .
S1c S1c
+ +
S1a S1b _ C1 S1d S1a S1b _ C1 S1d
S 3c S 3c
S5e + S5e
+
VDC VDC _
_
S4 + S4 +
S2b c
_ C2 S2d S2a S2b c
_ C2 S2d
S2a
S2c V0 S2c
V0 _
_ + Load +
Load
(a) (b)
S1c S1c
+ +
S 3c S 3c
+ S5e + S5e
VDC _ VDC _
S4 + S4 +
S2a S2b c
_ C2 S2d S2a S2b c
_ C2 S2d
V0 S2c V0 S2c
_ + _ +
Load Load
(c) (d)
S1c S1c
+ +
S 3c S 3c
+ S5e S5e
+
VDC _ VDC _
S4 + S4 +
S2a S2b c
_ C2 S2d S2a S2b c
_ C2 S2d
V0 S2c S2c
_ V0
+ _ +
Load Load
(e) (f)
S1c S1c
+ +
S 3c S 3c
+ S5e S5e
+
VDC _ VDC _
S4 + S4 +
S2a S2b c
_ C2 S2d S2b c
_ C2 S2d
S2a
V0 S2c S2c
_ V0
Load + _ +
Load
(g) (h)
Fig. 2 a V0 = 0 b V0 = 0 c V0 = +1V dc d V0 = +2V dc e V0 = +3V dc f V0 = −1V dc e V0 =

−2V dc f V0 = −3V dc
44 G. Dhal et al.
(c) Aγ 1 : (V0 = +1V DC ) The output voltage is V0 =+1V DC , and the switches S2a ,
S1c , and S1d , are all activated. By switching power through S5e andS2b , the
voltages on capacitors C1 can be changed to VC1 = VDC .
(d) γ 3 : (V0 = +2V DC ) In this configuration, V0 =+2V DC , while switches S2a , S1b ,
and S1d are all turned on. The output voltage in this switching condition is
supplied by VDC and capacitor C1 i.e. V0 = (V DC + VC1 ) = +2V DC . By
switching power through S2c the voltages on capacitors C2 can be changed
to VC2 =VDC .
(e) γ 4 : (V0 = +3V DC ) In this configuration, V0 = +3V DC , while switches
S1b ,S4c ,S1d , and S2a are all turned on. The output voltage in this switching condi-
tion is supplied by VDC and capacitor C1 and C2 i.e. V0 = (V dc + VC1 + VC2 )
= +3V DC .
(f) γ 2 : (V0 = −1V DC ) The output voltage is V0 = −1V DC , and the switchesS1a ,
S2c and S2d , are all activated. By switching power throughS1b ,S5e the voltages
on capacitors C2 can be changed to VC2 =VDC .
(g) γ 3 : (V0 = −2V DC ) In this configuration, V0 =−2V DC , while switches S1a , S2d ,
S2b , and S5e are all turned on. The output voltage in this switching condition
is supplied by VDC and capacitor C2 i.e. V0 = −(V dc + VC2 ) = −2V dc . By
switching power through S1c the voltages on capacitors C1 can be changed to
VC1 = VDC .
(h) γ 4 : (V0 = −3V DC ) In this configuration, V0 = −3V DC , while switchesS1a ,S2b ,
S3c and S2d are all turned on. The output voltage in this switching condition is
supplied by VDC and capacitor C2 C1 i.e. V0 = −(V dc + VC1 + VC2 ) = −3V dc .
3 Results and Discussions
3.1 Simulation Outcomes
In the following part, the Simulation analysis of proposed 7-level SCMLI architec-
tures is shown in Fig. 3. Table 3 details the simulation inputs. Figure 3a displays the
waveforms for the inverter’s output voltage V0 and load current I0 when the inverter
is fed an R-L load (R = 30 Ω and L = 40 mH). Output (V0 ) waveform consists
of seven distinct voltage levels. Each step of the output voltage has same magni-
tude. Rapid load increases or decreases have no effect on the operating voltages.
The voltages across capacitor are self-balanced under transient load. The effect of
varying the modulation index is illustrated in Fig. 3b. The MLI generate seven levels
at 0.95 MI and when the MI changes from 0.95 to 0.75 and 0.75 to 0.25 the proposed
design generates 5 and 3 levels respectively. The output voltage waveform shifts as
the modulation index are adjusted. There is evidence that once a change is made,
the inverter design stabilizes rapidly. Figure 3c, d depicts the voltage stresses experi-
enced by the switching components. These voltage wave form of different switches
proof the stresses are less than the load voltage.
150
V0
0
-150
3 I0
0
-3
50
VC1
48
50
VC2
48 Time(s)
0 0.1 0.2
(a)
150 M=0.75
M=0.95 V0 M=0.25
0
-150
3
I0
0
-3
50
VC1
48
50 VC2
Time(s)
48
0 0.1 0.2
(b)
50
S1a
0
50
S2a
0
50
S1b
0
50
S2b
0
100 S1c
0
0 0.1 Time(s) 0.2
(c)
Fig. 3 Simulation outputs: a RL-load shift b switching frequency c, d switch stresses e, f THD
analysis voltage and current at 0.95 and 0.5 modulation index
46 G. Dhal et al.
100
S3c
0
100
S5e
0
100 S4c
0
100
S1d
0
100
S2d
0
0 0.1 Time(s) 0.2
(d)
Fundamental(50Hz)=139.6,THD=20.87%
Mag(% of Fundamental
1.5
0 100
1.2
0 100
(e) THD at a Modulation index of 0.95
0 100
0 100
(f) THD at a Modulation index of 0.5
Fig. 3 (continued)
Table 3 Details of simulation inputs

Parameters Range
Supply source 50 V
MI 0.95, 0.75, 0.25
Load R = 30 Ω and L = 40 mH
Table 4 Comparative analysis

References ns nl nc nd n dri T SV pu Gain Fc/l Efficiency
[13] 14 7 2 2 12 4.6 3 4.28 97.12
[15] 16 7 2 – 14 5.3 3 4.57 96.45
[16] 12 7 4 4 12 5.3 3 4.57 96.81
[P] 12 7 2 – 11 5.3 3 3.57 97.32
nl = no. of level, n s = no. of switch, n c = no. of capacitor, n d = no. of diode, TSV pu = Per unit
total standing voltage, P = Proposed topology
4 Comparative Analysis
The advantages of the proposed circuit are made clearer by contrasting it with other
MLIs on a variety of metrics, including: n s ,n d , n c , and the voltage gain (see Table 4).
The overall component per level can be evaluated as [14]:
n s + n c + n d + n dri
Fc/l = (1)
nl
The proposed architecture is able to achieve the five-level and booster output.
Compared to [13, 15, 16], the proposed design has fewer switches on each level, as
shown in Table 4.
5 Loss Analysis
The section follows discusses the proposed topology’s losses, including switching
losses, conduction losses, and capacitor ripple losses.
(a) Switching losses (Ps )
These kinds of losses occur when a switch is turned on and off. Mathematically, the
switching power losses can be written as [20].
1
Ps = f V [Ion ton + Ioff toff ], (2)
6
48 G. Dhal et al.
where V : blocking voltage.

Ion , Ioff : The amount of current passing through the switches immediately
following and immediately preceding their activation.
ton , toff : times at which the switch is turned on and off.
f : indicates fundamental frequency.
(b) Conduction losses (P c )
When the power switches and the diode are operating in the conduction mode, the
internal resistance of the device causes power to be lost, which is referred to as
conduction losses. The losses that are caused by the power switches and diodes can
be stated as [21] in this way.
Pc,sw = V s,on Is,avg + Is,rms

2
Rs,on (3)
Pc,d = V d,on Id,avg + Id,rms

2
Rd,on (4)
where Vs,on ,Vd.on ; on-state voltage of switch and diode respectively.

Is,avg , Id,avg Is,rms , Id,rms : average and rms current of switch and diode, respec-
tively.
(c) Ripple losses (Pr )
The ripple loss in a switched-capacitor inverter is caused by the potential difference
that exists between the input power source and the capacitor during the charging and
discharging intervals. Each of these can be stated using the following format: [5].
f ∑( )
2
Ripplelosses (PR .) = Cn ΔV Cn
2
(5)
2 n=1
ΔVc : Capacitor’s voltage ripple.
6 Conclusion
In this study, a new 7-Level boost inverter with the capacity to perform self-voltage
equalization is presented. The proposed SC inverter architecture may amplify a single
dc input source by three times, allowing for the generation of a multistep waveform.
The advantages of the proposed design are explained by making comparisons to other
switched capacitor topologies. The results of the simulations verify the theoretical
analysis and show that the proposed topology can handle dynamic variations in
loading conditions without altering the voltage of the capacitors.
References
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Design and Investigation of Solar PV-Fed
PMSM Motor Drive
Irfan Qureshi and Vikas Sharma
Abstract This paper presents a constant-speed Permanent Magnet Synchronous

motor (PMSM) drive system fed by solar PV. The Speed is almost constant throughout
the period. The presented scheme contains a solar panel, boost converter, three-phase
inverter, and three-phase PMSM Motor. The control scheme includes Perturb and
Observe algorithm for maximum power point tracking (MPPT) and an improved
modified space vector modulation (IMSVM) controller for the three-phase inverter.
Perturb and observe algorithm is implemented to extract the most amount of power
from PV panels and IMSVM is used to control voltage for the three-phase inverter.
The IMSVM has simple usage, has fewer harmonic contents, requires fewer compu-
tational calculations, has low switching losses, and most efficient technique. The
MPPT algorithm is easy to practice, proficient, and adopted widely in commercial
industries. PMSM motor is widely used in EVs water pumping, and other industrial
applications. The proposed scheme has been simulated and results have been verified
in MATLAB/Simulink environment and analyzed its performance characteristics.
Keywords PV array · Perturb and observe algorithm · Boost converter · PMSM ·

IMSVM inverter
1 Introduction
Solar energy is a non-convention source and plentiful and has been verified to be a
demanding resource of energy. This is due to its nature to constantly provide energy
[1]. By making utilization of renewable energy sources, we can reduce environmental
pollution or we can say minimize ecological harms such as the greenhouse effect. The
non-convention energy resources such as solar, wind, ocean thermal, hydro, biogas,
I. Qureshi (B) · V. Sharma

Government Engineering College Bikaner, Bikaner, Rajasthan, India
e-mail: [email protected]; [email protected]
V. Sharma
52 I. Qureshi and V. Sharma
tidal, etc. are used to produce electrical energy. Out of these, solar energy is the most
well-known, cheaper, efficient, and economically beneficial, easily distinguishable,
and gives a consistent performance. Kumar and Singh have presented a single-ended
primary inductor SEPIC converter in the PV fed water pumping system [2].
Kumar and Singh have designed an easy, cost-effective, and efficient PV-fed
PMBLDC drive water pumping system [3]. Kalla et al. [4] presented a capable
controller for a PV array-controlled BLDC drive electric vehicle scheme in MATLAB
software. The system model and Simulink of the PV system and PMBLDC drive have
been presented and MATLAB results are also depicted. PV fed trapezoidal back Emf
PMSM drives have been proposed in [5–16]. Murshid and Singh [17] have presented
the sensorless PMSM Drive fed by a solar PV panel for a water pumping system.
PV-fed PMSM drive is also presented in [17–20].
Parbhakaran et al. [21] have investigated PV-fed standalone single-stage PMSM
drives. PV fed PMSM driven systems have been also depicted in [22–28]. Murshid
and Singh et al. [29] developed an improved double-step PV array-fed PMSM motor
water pump system with protection capabilities. Kalla et al. [30] have presented a
PV array fed IMD driven water pumping scheme.
Kashif and Singh [31] have designed a water pumping system PV-fed PMSM drive
with a hybrid ANF scheme and self-sensing scheme and also compared both schemes
in MATLAB/Simulink. Mishra et al. [32] have presented a synchronous motor drive
fed by a solar battery system. The scheme has been simulated in MATLAB and results
have been verified by testing in the lab also. Kashif and Singh [33] have investigated
a PV-fed PMSM-based water pumping system with reduced sensor control. The
scheme is simulated as well as results have been verified by the lab. Kumar et al.
[34] have described Solar battery-fed PMSM motors for electrical vehicle applica-
tions. The scheme has been simulated and results have been verified by MATLAB/
Simulink.
This paper proposed a PMSM Drive system integrated with solar PV panels as
depicted in Fig. 1.
The control technique used for the control of the inverter is IMSVM and P&O
algorithm is used to get the utmost amount of power from PV IMSVM that provides
gate pulses to the inverter to achieve the constant speed at the desired torque. The
described scheme is simple to apply, proficient, and adopted widely in industries and
causes reduction in the sensors. PMSM motor driven system has been widely used
PV Boost
Inverter PMSM
Array Converter
P&O IMSVM PUMP

Algo
Fig. 1 Proposed scheme representation

Design and Investigation of Solar PV-Fed PMSM Motor Drive 53
Boost
Converter VSI
Ipv IL
VL
Solar
L
insolation G PV panel D
S1 S3 S5 PMSM
Vpv
C S Cd
Vdc ia
ib
ic
Cell temperature Tc S4 Speed
S6 S2
Sensor
MPPT PWM S1 to S6
P&O generator
IMSVM
Vdc*
generator
PI controller
Fig. 2 Proposed scheme of solar PV fed PMSM drive system
and PMSM motor is highly implemented and efficient to fan, EV, water pumping,
and other industrial applications.
2 Scheme and Working Principle
Figure 2 shows the proposed scheme of the PV-fed PMSM drive. The presented
system contains a solar panel and a boost converter IMSVM PMSM motor. The
solar PV panel is coupled with the boost converter. The P&O algo is working to
extract the maximum quantity of energy from the PV array. The boost converter is
then fed to the 3-φ IMSVM inverter. The inverter is connected to a PMSM drive.
3 Control Schemes
The SVM technique has been used to generate gate signals for the inverter. The
technique is as follows.
3.1 Space Vector Modulation Scheme
A vector space representation is shown in Fig. 3.

Fig. 3 Representation of β'-âxis

primary space vectors
V’1 (0,1,0) V’2 (1,1,0)
V6(0,1,1) V7(0,0,0) V3(1,0,0)
V8(1,1,1) α-axis
V5(0,0,1) V4(1,0,1)
The process of SVM is somewhat different from other PWM techniques. It’s a
way to change the type of digital. The main motive of this scheme is to make the
loads of the load line equal to the dimensions of the reference line. This can be done
by properly selecting the MOSFET inverter switch at the right time. This can be
achieved by modifying the vector space.
The SVM method has a low current ripple, the scheme uses 15% less DC input
voltage than other techniques, is consistent and simple to execute, and has noise
reduction in Motor Drives.
Space rotation: In a double space, three time-related functions are satisfactory,
xa (t) + xb (t) + xc (t) = 0 (1)
Links are provided as to vector [xa 00]t corresponds x-axis, vector [0xb 0]t is along
the y-axis and vector [0xc 0]t is beside the ż-axis. In a more composite way, it’s
presented as
2
xa + xb ej( 3 )π + xc e−j( 3 )π
2 2
x(t) = (2)
3
i.e., 2/3 is the multiplier. The number is described as a real and imaginary way
u(t) = ux + juy (3)
In the standard form, the 3-φ voltages in the way of xa , xb and xc are specified by
xa = Vm sin(ωt) (4)
xb = Vm sin(ωt − 120◦ ) (5)

xc = Vm sin(ωt − 240◦ ) (6)
The 3-φ inverter output voltage vector is unchanged during operation, so the
current of the 3-φ inverter and as a result, PMSM drive currents can be stable by
selecting the suitable voltage vector.
4 System Design and Modeling
We know that solar power is transformed into electricity with the use of PV panels
that provide high emissions during the day and low emissions in the dawn and the
dark. Energy output relies on sunlight and heat. Therefore, we have designed the
system control system to make it more efficient.
4.1 PV Panel Design
A PV array equivalent circuit is displayed in Fig. 4. Several PV panels are termed

PV cells or arrays. In the system, we use the special arrangement of solar PV arrays
in series and parallel arrangement. Rating of the PV panel has been given in Table 1.
ip = ide + isn + is (7)
is = ip − ide − isn (8)
Vot + is Rsn
∵ ide = Io ( − 1) (9)
aVT

Vot + is Rsn Vot + is Rsn
is = ip − IO exp −1 − (10)
aVT Rsn
The above equations are standard mathematical forms to explain the I-V
performance features of the solar array. Where Io = reverse-saturation current.
Vot = Voltage corresponding to temp.
Fig. 4 Equivalent circuit of is

the ideal PV array ide isn
Rse
ip Di Rsn Vot
Table 1 PV panel rating

Symbol Name Values
Ppv Power rating 4.4 KW
Ns No. of series string 27
Np No. of parallel string 1
V ocn Open circuit voltage 32.9 V
I scn Short circuit current 8.21 A
Fig. 5 I-V and P-V curve of

an idyllic solar array MPP
(Voc, 0)
(Vmp, Imp)
P[W]
I[A]
(0, Isc)
V[Ʋ]
The idyllic I-V and P-V curve of the PV array is presented in Fig. 5. Its variations
depend on the temperature and irradiance values.
Selection of inductor and capacitor of Boost Converter. A small amount of
inductor makes a quick temporary response; and causes a large current explosion,
resulting in a high loss of conductors in the switch, inductor, and parasitic resistance.
A small inductor also requires a large capacitor filter to reduce power outages.
For the Boost converter it is given as follows.
dki (1 − dki )2 R
lcr = (11)
2fswt
vot − vinp
dki = dutyratio = (12)
vinp
where, vinp isinputvoltage, vot isoutputvoltage, RisResistance, fswt is switching

frequency.
For the Boost converter, the peak-to-peak ripple voltage is,
vin dk
∂v cr = (13)
8lcr Cf 2sw
where Ciscapacitance and lcr is Critical inductance.

Perturb and Observe Technique. The control algorithm to attain maximum power
point is given below. It is mainly implied due to its simplicity and reliable nature and
non-difficult implementation.
‘P = 0 and V = 0, at MPP
‘P > 0andV > 0,
leftofMPPonP − V curve
‘P < 0andV < 0,
rightofMPPonP − V curve
The duty ratio D is attuned as described,
Dnew = Dold ,
if‘P = 0andV = 0,
Dnew = Dold − D,
if
‘P > 0andV > 0,
else
‘P < 0andV < 0
Dnew = Dold + D,
if
‘P > 0andV < 0,

DC to ABC
Gate timings
dq And clarke
Vdc + PI Compare Demux
- Transformation To 3-phase
Generate inverter
θ signals
Vref
Repeating
sequance
Fig. 6 Proposed scheme of generating pulse
else
‘P > 0andV > 0.
where D denotes the perturbing duty ratio and Dnew andDold are the latest and
previous quantity of the duty cycle.
Control Technique Explained for PMSM Drive. Figure 6 depicted the schematic
Visio diagram of the proposed system for generating gate signals.
Here Vdc and Vref are the coupling capacitor voltage and reference voltage corre-
spondingly. Proportional-Integral reduces the error values. Then these signals are
compared with repeating sequence signals and are given to the demultiplexer which
generates the six voltage signals. The depicted scheme has been molded and simu-
lated in MATLAB. The PV system is coupled to a boost converter. The boost converter
is then connected to the 3-φ inverter via a dc link capacitor. Gate pulses to the inverter
are given by the IMSVM technique and the inverter is connected to the PMSM motor
drive which starts the drive. These gate signals are given to the 3-φ inverter. This dc
voltage is then converted into Vα and Vβ which is then converted into ABC by using
a 2-phase to 3-phase transformation.
5 Simulation Results and Discussions
The results have been obtained at time-varying isolation levels of 1000, 800, and
600 W/m2 and a temperature of 25 °C. The value of G is 800 W/m2 at step time
0–5 s. At the step time of 5 s the value of irradiance is 1000 W/m2 until the step time
of 8 s. At step time between 8 and 10 s, the value of irradiance is 600 W/m2 as shown
in Fig. 7.
Values of PV current Ipv and power Ppv varies with variation in G as shown in
Fig. 7. PV Array Power i.e. Ppv is 1400 W at G 800 W/m2 , 1800 W at G 1000 W/m2
and 1000 W at G 600 W/m2 . Dc link voltage i.e. Vdc is around 400 V and slightly
changes with change in isolation level G is shown in Fig. 7. PV Array Current Ipv
are values 6, 7.5, and 4.4 A respectively. The rotor speed ωm is constant by nearly
Fig. 7 Dynamic performance of the system when isolation level changes from 800, 1000, to 600
W/m2
200 rps but changes with change in irradiance as shown in Fig. 7. The steady-state
performance of the drive has been depicted in Fig. 8. All the quantities are constant
at steady-state conditions as shown in Fig. 8. Results have been taken at G 600 W/
m2 , PV Array Power Ppv is 1000 W DC link voltage i.e. Vdc is 400 V, Output VSC
Current i.e. Iabc 25A, Rotor Speed ωm is 200rps and Electromagnetic Torque Te is 5
N*m.
Figure 9 demonstrates the load change dynamic performance of the system at
isolation level G 800 W/m2 . PV Array Power is 1400 W. When there is a variation
load at a step time of 3 s, torque changes from 10 to 5 N * m. speed is slightly
changed at that point and then again back to constant i.e. 200 rps so the system gains
its stability very fast as depicted in Fig. 9. The Speed of the PMSM drive is constant.
So the speed of the PMSM drive has not been affected by the load change. We can
say that the PMSM has a constant speed drive at any load.
Fig. 8 Steady-state performance of the system at 600 W/m2 isolation level
6 Conclusions
A PV-driven PMSM scheme has been analyzed in this paper using the space vector
modulation control technique and P&O algorithm. The results are obtained at 25 °C.
The speed of the drive is constant irrespective of load torque. We can say that the
PMSM has a constant speed drive at any load. SVM has lesser harmonics than
any other technique of modulation so the noise reduction is motor, also it has the
advantage to use 15% less DC voltage than the other techniques. The maximum
power point has been attained without any oscillations. The proposed scheme is cost-
effective and eliminates the current sensor savings on the drive side, providing high
performance and consistent performance. The performance of the entire scheme is
found to be adequate in most operating systems as well as water pumping in irrigation
and industrial areas in dynamic and steady-state conditions.
Fig. 9 Dynamic performance of the system when load change at a step time of 3 s
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motor drive based on multi-input DC boost converter supplemented by hybrid PV/FC/battery
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BLDC motor drive. In: 2012 IEEE international conference on Power Electronics, Drives and
Energy Systems (PEDES), Bengaluru, pp 1–6
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drive. In: 2013 annual IEEE India Conference (INDICON), Mumbai, pp 1–6
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2553–2558
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bridgeless-Luo converter fed BLDC motor drive. In: 2013 IEEE industry applications society
annual meeting, Lake Buena Vista, FL, pp 1–8
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zeta converter. IEEE Trans Ind Inform 10(4):2064–2072
10. Bist V, Singh B (2014) A PFC-based BLDC motor drive using a canonical switching cell
converter. IEEE Trans Ind Inform 10(2):1207–1215
11. Bist V, Singh B (2014) A PFC based bridgeless Sheppard-Taylor converter fed brushless DC
motor drive. In: 2014 innovative applications of Computational Intelligence on Power, Energy
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DC motor drive. In: 2014 9th International Conference on Industrial and Information Systems
(ICIIS), Gwalior, pp 1–6
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drive. In: 2014 eighteenth National Power Systems Conference (NPSC), Guwahati, pp 1–6
14. Bist V, Singh B (2014) An adjustable-speed PFC bridgeless buck–boost converter-fed BLDC
motor drive. IEEE Trans Ind Electron 61(6):2665–2677
15. Hou H, Yao W, Zhang W (2016) Vector control of single phase brushless DC motor. In: 2016
19th International Conference on Electrical Machines and Systems (ICEMS), Chiba, pp 1–5
16. Gujjar MN, Kumar P (2017) Comparative analysis of field oriented control of BLDC motor
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(ITEC), Long Beach, CA, USA, pp 63–68
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ECS57921.2023.10063001
Scheming of Four-Phase IBC for Fast
Charging of EV Battery
Abhishek Singh, Pooja Kumari, and Niranjan Kumar
Abstract In today’s world, the Automobile industry is shifting rapidly from conven-
tional ICE Vehicles to EVs. As the name suggests, EVs use electric motors instead
of gasoline engines. Increase in demand of EV leads to increase in demand of power
electronic converters to make electrical circuitry more and more efficient. Efficiency
during battery charging can be enhanced by shrinking the losses and ripples in the
output voltage of converters. The interleaving concept comes into the picture to
reduce the losses along with ripples in output voltage, the reduction in the size of
components, and faster response. This paper focuses on working of a four-phase
interleaved boost converter for the rapid charging of EV batteries. The simulation of
the proposed circuit is executed in MATLAB/SIMULINK and the results are vali-
dated. The result compares a conventional boost converter with an interleaved boost
converter. The simulation outcomes highlight how the interleaved boost converter
(IBC) boosts the input voltage.
Keywords Simulation · Interleaving · Ripples · Electric vehicle · Output

voltage · Four-phase IBC
1 Introduction
We all know that EVs [1] are the future of means of transport in the world. It is
not only clean and eco-friendly but also highly efficient relative to our conventional
internal combustion engine (ICE) vehicles. An EV has countless advantages [2] over
an ICE but the only drawback it has is its charging time. Generally, a conventional
vehicle takes around 2 min in refuelling the tank whereas an EV takes 30 min to 12 h
to get fully charged depending on its level of charging rate.
A. Singh (B) · P. Kumari · N. Kumar

Department of Electrical Engineering, NIT Jamshedpur, Jamshedpur, India
N. Kumar
66 A. Singh et al.
Level 1 charging [3] takes around 10–12 h to fully charge a discharged battery
once whereas, Level 2 charging [3] takes around 4–6 h. These time durations are very
high and push us to move on Level 3 chargers or DC fast chargers which take less
than an hour to charge the battery. In Level 3 chargers [3], various power electronic
converters are used to get high voltage and current. Since these batteries charge
on DC but our supply is AC so, in almost all of them, different types of DC–DC
converters [4] are being used with a rectifier. DC–DC converters [5], also called
choppers, are having DC parameters at both the source and load end. The four-ϕ
IBC [6] is also a boost-type DC–DC converter. This type of converter is generally
used to step up the input voltage. It generally uses a diode, inductor, filter capacitors,
and other semiconductor switches like MOSFET or BJT, depending on the type of
application in its circuit.
Battery technology has improved over the years, and with the increased use of
portable devices, the demand for fast charging has increased. Fast charging allows
devices to be charged quickly, reducing downtime, and increasing productivity. The
traditional charging methods are slow, and this has resulted in the emergence of new
technologies such as the IBC. A boost converter (BC) operates in a manner that
during the turn-on of the switch, the inductor stores energy, and during the turn-
off of the switch, the combined energy of the source and the inductor eventually
boosts the input voltage. There is a filter capacitor connected in parallel with the
load resistor to maintain the constant output voltage. Generally, a conventional BC
is not preferred for battery charging purposes because of its high content of ripples.
By using the concept of interleaving, the ripples of both output voltage along with
input current get reduced. Also, to serve the increase in energy demand, interleaving
allows us to handle larger loads. With proper switching in IBC, we can get all the
above-mentioned advantages. A further advantage of IBC [7] is that at any time at
least one of the converters is supplying the load.
Some of the works of the authors are addressed in the literature review. The
literature survey has demonstrated that the use of multiple phases in a converter can
improve efficiency, reduce component stress, and increase power density.
In [8] the author presents a promising solution for efficient and reliable solar power
conversion. The proposed converter topology has several advantages over conven-
tional boost converters, including reduced ripple current and voltage, improved
efficiency, and increased power density. The simulation outcomes verify that the
suggested converter is capable of efficiently converting low-voltage, high-current
solar panel output to a higher voltage suitable for grid-connected applications.
The interleaving algorithm in a parallel power converter is proposed in [9]. These
converters consist of two to four analogous BC connected in parallel and are regu-
lated by interleaved switching signals having the same frequency and some phase
shift. By sharing the input current among the cell phases, this design achieves large
consistency and efficiency in power electronic systems, as well as improved mainte-
nance and low heat dissipation. The authors designed and experimentally verified a
1.2 kilo-watt converter model with a switching frequency of 25 kHz, which is related
to a PEM fuel cell system (1.2 kW, 46-A) in a laboratory. The results validate higher
system performance by reducing the ripple current to nearly zero. In the context of
Scheming of Four-Phase IBC for Fast Charging of EV Battery 67
applications involving renewable energy sources, a similar study on interleaved BC

and conventional BC has been presented in [10]. In this study, a comparative perfor-
mance analysis of 3-ϕ uncoupled and directly coupled IBC for renewable energy
sources was conducted. When evaluated with a traditional BC, it has been discov-
ered that the proposed IBC results in a lower level of current ripple. As a result of the
comparative study, it has been determined that three-phase IBC is an advantageous
topology for use in applications involving renewable energy. In [11] the performance
of the PEM fuel cell current is proposed in a well-written and well-organized study
that provides valuable insights into the use of a 4-ϕ IBC and a novel control strategy
to improve the performance of the PEM fuel cell current. The results demonstrate
the effectiveness of the proposed approach by highlighting its potential for future
applications in fuel cell systems.
Similarly, the efficacy of 2-ϕ and 3-ϕ IBC for applications involving renewable
energy sources is investigated in [12]. By utilizing an IBC with three stages, it is
possible to effectively reduce the overall ripple of the current, which in turn lengthens
the lifetime of renewable sources. The traditional 2-ϕ IBC that is stated in the liter-
ature is contrasted with a 3-ϕ IBC that is discussed in this particular piece of work.
Input current ripple is significantly reduced, thanks to the use of three Phase IBCs
as opposed to two-phase models. Comparisons are made between the ripples of the
two different types of converters, output voltage, input current, and inductor current
for a variety of duty cycles. MATLAB/SIMULINK is the software that is utilized for
simulation. The outcomes are analyzed and compared to the theoretical parameters
to ensure their accuracy. The analysis of four phase IBC has not been considered in
the proposed scheme. The ripples present in the output voltage can be reduced with
the help of the interleaved boost DC–DC converter that is suggested in [13]. The
converter has a high voltage ratio and a low ripple. The low DC voltage produced
by the fuel cell is converted by this converter to the high DC voltage produced by
the DC link. The developed model is applied for fuel cell applications. In [14], an
analysis of the performance of IBC with multiple phases is presented. MATLAB/
SIMULINK is used for the simulation analysis of an IBC with multiple phases (two/
three/four). However, in the aforementioned scheme, none has considered the usage
of IBC in the fast charging of EV batteries. Therefore, the designed model explains
the application of IBC in the charging of EV batteries [15].
The rest of the manuscript is presented as follows. Section 2 describes the
scheming of the original BC. The working of IBC is explained in Sect. 3. Section 4
summarizes the designing and implementation part of the proposed IBC simulation
model and the conclusion has been drawn in Sect. 5.
2 Scheming of Conventional Boost Converter
Let us first see the conventional BC which is shown in Fig. 1.

The Duty Cycle (D) of the above converter can be calculated by the following
equations:
68 A. Singh et al.
Fig. 1 Conventional BC
Vi
Vo = (1)
1− D
Vi
D =1− (2)
V0
Vo and Vi are output and input voltage.

Now, from the above equations, we can see that the output voltage depends on the
duty cycle. It means that if the duty cycle has a high value, then it gets reflected as a
higher value of output voltage. For the designing of an inductor, we have an equation
as follows,
Vi ∗ D
L= (3)
I L ∗ f s
where L is the Inductance, I L is the Inductor ripple current, and f s is the Switching
frequency. The size of the inductor depends f s on and the inductor ripple current. As
the f s increases, the size of the inductor will reduce, and vice-versa.
For designing the value of the capacitor, we have an equation as follows,
Vi ∗ D
C= (4)
R ∗ f s ∗ Vo
where C is the Capacitance, R is the Load resistor, and V o is the Output voltage
ripple. The size of the capacitor depends on the ripple of the output voltage and f s .
As f s increases, the size of the capacitor will reduce and vice-versa.
3 Working of Interleaved Boost Converter (IBC)
The IBC is a type of DC–DC [16] converter that uses multiple converters in parallel
to provide a higher current output. This results in faster charging times, making it an
ideal method for charging batteries. This paper presents an overview of IBC and its
application in battery charging.
The converters are interleaved, meaning that the switching signals of the converters
are staggered, resulting in a smoother output. The interleaved boost converter operates
in two phases; the first phase involves the charging of the inductor, and the second
phase involves the discharge of the inductor.
During the initial phase, the switches are turned on, and the current flows through
the inductor. In the next phase, the switches are turned off, and the inductor discharges,
resulting in higher voltage output. The interleaved boost converter is an efficient
method of charging batteries, and it is used in various applications, including
renewable energy, electric vehicles, and portable devices.
4 Design and Implementation of the Proposed IBC Model
The simulation is executed to evaluate the robustness of IBC. The simulation results
show that the converter is efficient and can charge the battery within a short period.
The circuit diagram of the 4-ϕ IBC is depicted in Fig. 2. It is the parallel connection
of four boost converters with each phase having a 90-degree shift from the other.
Since these inductor currents are out of phase, they help to reduce the ripples [17] by
scrapping their effect. At any instant in time, at least one of the phases is supplied to
the load. The division of current into four parts helps in the reduction of power loss.
Fig. 2 Four-phase IBC circuit diagram

70 A. Singh et al.
The gate pulses for this converter have some phase shift which is calculated based
on the following equation,
360◦
θ= (5)
n
where n is the number of the phases of IBC.
The value of inductors L 1 , L 2 , L 3 , and L 4 are calculated based on the following
equation,
Vi ∗ (Vo − Vi )
L1 = L2 = L3 = L4 = (6)
I L ∗ f s ∗ Vo
The inductor current and current through the diode is illustrated in Figs. 3 and 4
respectively. iLA, iLB, iLC, and iLD represent the inductor current across all four
phases. The currents iA, iB, iC, and iD represent current through the diode across all
the phases. Since there are four phases in the proposed circuit, therefore the switching
pulses are shifted 90° from each other which is shown in Fig. 5. These switching
signals are provided with the help of pulse generators which is having a frequency
of 25 kHz.
When the diode becomes a forward bias then, it allows the inductor current to
flow and the magnitude of the inductor current that is flowing in the proposed circuit
per phase is around 331.2 A as shown in Figs. 3 and 4, which is the same as the
magnitude of the diode current.
Fig. 3 Inductor current across all the four phases

Fig. 4 Current through diode across all the four phases
Fig. 5 Switching pattern for four-phase IBC

72 A. Singh et al.
The value of the capacitor is computed by implementing the below equation,
D ∗ Vo
C= (7)
f s ∗ R ∗ V o
where Vo is the Ripple in the output voltage.

MATLAB simulation of battery charging with four-phase IBC is shown in Fig. 6.
The Output voltage of the IBC is calculated by using the equation (8).
Vi
Vo = (8)
1−D
There are mainly four blocks in the proposed IBC model as illustrated in Fig. 7.
The AC voltage source provides the required supply voltage. The rectifier converts
AC–DC voltage. Further, a filter circuit is designed consisting of an inductor and
capacitor. The inductor mainly smoothens out the current waveform and the capacitor
filter smoothens the output DC voltage. Then the purely rectified DC voltage is fed
to the battery which acts as a load in our case. The proposed IBC model is applied
for fast charging of the battery.
The simulation was run and the charging curve of the battery and output current
is illustrated in Fig. 8. It can be observed that the SOC [18] of the battery increases
during the charging mode of operation. The output current of the battery is main-
tained at around 8A. The battery specifications and the circuit parameters have been
provided in Table 1.
The waveforms of input and output voltage are depicted in Fig. 9. The IBC boosts
the input voltage from 204.8 to 389.40 V as there is a duty cycle of 50%. The value
of inductances and capacitance is calculated around 0.01 mH & 800 μF respectively.
5 Conclusion
The IBC is an efficient and effective method of fast-charging batteries. The converter
uses multiple converters in parallel to provide a higher current output, resulting in
faster charging times. This paper presents an overview of IBCs and their application
in battery charging. The design and implementation of an IBC for fast charging of a
lithium-ion battery are presented, and the results show that the converter is efficient
and can charge the battery within a short period. The proposed model designed in
MATLAB/SIMULINK environment can charge the battery rapidly. This circuit takes
around 30 min to charge a battery of 400 V and 50 Amperes per hour capacity from
0 to 90% and charges to 100% in less than 40 min. So, we can say that the charging
rate of this circuit is slightly around 2C.
For future scope, we can add a power factor improvement circuit at the input side
and, we can add a control circuit based on the state of charge level so that we can
make it more compatible with all types of EVs.
Scheming of Four-Phase IBC for Fast Charging of EV Battery
Fig. 6 MATLAB simulation of battery charging with four-phase IBC

73
74 A. Singh et al.
Fig. 7 Block diagram of proposed IBC
Fig. 8 SOC and output current
Table 1 Simulation
Parameters Values
parameters
Vi 204.8 V
Vo 389.40 V
fs 25 kHz
L1 = L2 = L3 = L4 0.01 mH
C 800 μF
θ 90°
D 50%
Fig. 9 Plot illustrating input voltage (V i ) and output voltage (V o ) of IBC
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Speed Control of a Brushless DC Motor
Using Hall Sensor
Manoj Kumar Kar, Shejal Sanjay Waghmare, Simeen Mujawar,

and Sreerekha Vadi
Abstract Speed control using a Brushless DC (BLDC) motor typically involves

adjusting the amplitude and frequency of the power supplied to the motor. A BLDC
motor outperforms a brushed DC motor because it replaces the mechanical commu-
tation unit with an electronic one, which improves dynamic characteristics, increases
efficiency, and reduces noise levels slightly. Hall sensors are used to provide feedback
to the motor controller. BLDC motors can operate more efficiently and accurately by
using Hall sensors to detect the position of the rotor. There are typically three Hall
sensors positioned around the stator. The sensors detect the position of the rotor’s
magnetic poles as they pass by, and send a signal to the motor controller indicating
which coil to energize next. The motor controller then switches the current to the
appropriate coil, causing the rotor to continue turning. MATLAB/SIMULINK is used
to examine the dynamic properties of BLDC motors, including speed, current, and
back EMF.
Keywords BLDC motor · Hall sensor · PI controller · Speed control · MATLAB/

Simulink
1 Introduction
Speed control of an Induction motor is required for many reasons such as improved
efficiency, process control, safety, reduce mechanical stress and noise, and to extend
the life of the motor and connected equipment. Speed control using Brushless DC
(BLDC) motors has several benefits such as high efficiency, high power density, low
M. K. Kar (B)
Tolani Maritime Institute, Pune 410507, India
S. S. Waghmare · S. Mujawar · S. Vadi
AISSMS College of Engineering, Pune 411001, India
S. Vadi
78 M. K. Kar et al.
maintenance, smooth and precise control, wide speed range etc. over other types of
motors. For these reasons, BLDC motors are becoming increasingly popular in many
applications, including automotive, aerospace, industrial automation, and consumer
electronics. There are several ways to control the speed of a BLDC motor: pulse width
modulation, current control, voltage control, sensor less control etc. The method
used for speed control of a BLDC motor depends on the specific application and the
requirements for speed control accuracy, efficiency, and cost.
Both BLDC and permanent magnet synchronous motors (PMSM) are commonly
used in various applications such as electric vehicles, industrial automation, and
robotics. However, there are some advantages of BLDC motors over PMSM that
make them a preferred choice in certain scenarios.
(i) One of the main advantages of BLDC motor is their simple control structure.
BLDC motors are driven by a simple trapezoidal or sinusoidal current wave-
form, which can be generated using a relatively simple and inexpensive motor
controller. In contrast, PMSM requires a more complex control algorithm to
regulate the current in the motor’s winding to maintain a constant magnetic
field, which can increase the cost and complexity of the system.
(ii) Another advantage of BLDC motors is their ability to operate over a wide speed
range, including low speeds. PMSM motors typically require a high-speed
operation to maintain the magnetic field, which can limit their performance in
applications where low speeds are required.
(iii) BLDC motors are also generally more robust and reliable than PMSM motors.
BLDC motors have a simpler rotor structure and do not require the use of rare-
earth magnets, which can be expensive and prone to demagnetization. This can
make BLDC motors more cost-effective and reliable in certain applications.
The author proposed a fuzzy logic-based speed control method for a BLDC motor
[1]. The method is tested using MATLAB/Simulink and the results demonstrate
that the proposed method provides excellent speed control performance. In paper
[2], the authors investigate the use of pulse width modulation technique for speed
control of a BLDC motor. The method is implemented using a microcontroller and
the results show that the method is effective in controlling the speed of the motor.
The authors proposed an artificial neural network (ANN) and PSO based speed
control method in [3] for a BLDC motor. The method is tested using MATLAB/
Simulink and the results show that the proposed method provides good speed control
performance. In [4], the authors investigate the use of extended Kalman filter (EKF)
for sensor less speed control of a BLDC motor. The method is implemented using a
microcontroller and the results show that the method provides accurate speed control
performance. The authors proposed a Model Predictive Control (MPC) based speed
control method for BLDC motor in [5]. PMSM motors have a higher power density
and efficiency than BLDC motors, which can make them more suitable for high-
performance applications such as electric vehicles or aerospace applications. By
simulating the speed control of a BLDC motor under various load situations, a PID
and fuzzy based controller is used [6] to validate the control. Here, regulated voltage
from an inverter is used to control the motor’s speed. For BLDC motor speed control,
Speed Control of a Brushless DC Motor Using Hall Sensor 79
a modified DE algorithm-based proportional integral (PI) controller is suggested [7].

The approach for BLDC motor speed control using DSP and Hall effect sensors is
provided [8]. Artificial Neural Network (ANN) controller and PID controller are
used in [9] to control the speed of brushless DC motor. By reducing the high values
of overshoot and steady-state error and raising the value of rise-time, the stability
indicator has been improved [10]. For the BLDC motor system, a speed control
system based on ANFIS and low-resolution Hall-effect sensors is used [11]. The
results of tuning a PID controller using the GWO and PSO techniques are compared,
and it is clear from the findings that the proposed GWO strategy produces better
dynamic performance for BLDC motors [12]. In [13, 14], the authors suggested
speed control of PMSM which has a sinusoidal back-EMF waveform and requires a
more complex control scheme to maintain constant torque and speed. BLDC motors,
with their trapezoidal waveform, can be controlled more easily.
Overall, the literatures demonstrate that there are several effective methods for
speed control of BLDC motors, including fuzzy logic, PWM, ANN, Kalman filters,
and model predictive control. These methods can be implemented using microcon-
trollers and provide excellent speed control performance, making BLDC motors an
ideal choice for many applications.
In this work, the speed control of BLDC motor has been accomplished using PI
controller.
2 Mathematical Modeling of BLDC Motor
A BLDC motor can be modeled mathematically for control and simulation purposes.
The BLDC motor consists of a rotor with permanent magnets, and a stator with
windings that produce a magnetic field when energized. The stator windings are
typically arranged in three phases.
The following equations can be used to model the motor:
1. Electromotive force (EMF) equation:
e = kω (1)
where e is the EMF generated in each phase, k is a constant that depends on the
motor construction, and ω is the rotor angular velocity.
2. Torque equation:
T = kτ I (2)
T is the torque produced by the motor, kτ is a constant that depends on the

motor’s construction, and I is the current flowing through the stator windings.
3. Voltage equation:
80 M. K. Kar et al.
V = RI + e (3)
where, V is the voltage applied to the stator windings, R is the winding resistance,
and e is the EMF generated in each phase.
4. The dynamics of the motor can also be included by adding a first-order differential
equation for the rotor angular velocity.
Rotor dynamics equation:
dω
J = T − Bω − TL (4)
dt
where, J is the rotor’s moment of inertia, B is a damping coefficient, TL is the
external load torque, and dω
dt
is the angular acceleration of the rotor.
By combining these equations and simulating them, the behaviour of the BLDC
motor can be modelled and its response to different control inputs and load conditions
can be predicted.
This model can also be used to design and optimize control algorithms for the
motor, such as PID controllers or model predictive controllers. The Simulink model
of the BLDC motor with Hall sensor is shown in Fig. 1.
3 Hall Sensor
A Hall sensor is a device that measures magnetic fields. The Hall effect is a
phenomenon where a magnetic field applied perpendicular to a current-carrying
conductor generates a voltage across the conductor.
A Hall sensor consists of a thin strip of semiconducting material with current
passing through it. When a magnetic field is applied perpendicular to the strip, the
Hall effect causes the voltage to develop across the strip. This voltage is proportional
to the strength of the magnetic field. Hall sensors are used for speed sensing.
Hall sensors are often used in BLDC motors to provide feedback to the motor
controller about the position of the rotor. BLDC motors require a way to determine
the position of the rotor in order to switch the current to the coils at the appropriate
time.
Hall sensors are typically installed in the motor in a way that allows them to detect
the position of the rotor’s magnetic poles. There are usually three sensors spaced
evenly around the stator. As the rotor rotates, the Hall sensors detect the position of
the magnetic poles and send signals to the motor controller. The motor controller
uses these signals to determine when to switch the power to the motor. Based on the
signals from the Hall sensors, the motor controller adjusts the power supplied to the
motor to maintain the desired speed. The motor controller switches the power to the
motor at the correct timing to keep the rotor rotating at the desired speed. To further
control the speed of the motor, a speed controller can be used. The speed controller
adjusts the power supplied to the motor based on the desired speed set by the user.
Fig. 1 Simulink diagram of BLDC motor with Hall sensor

82 M. K. Kar et al.
Generally, SPWM method is used to generate PWM signal [15, 16]. But, gener-
ating a PWM signal using a Hall sensor can offer several advantages over SPWM,
including higher accuracy, simplicity, reduced harmonic distortion [17, 18], and
better efficiency. The Hall sensor signals are shown in Fig. 2. Figure 3 shows the
Hall sensor signals for 3-phases.
4 Simulation Result and Discussion
The speed response of a BLDC motor with the Hall sensor is shown in Fig. 4. The
response depends on various factors, including the motor design, the quality of the
Hall sensors, the motor controller’s capabilities, and the load on the motor. Generally,
the response should be fast and stable, with minimal overshoot or delay in reaching
the desired speed. After using Hall sensors, the speed response of a BLDC motor
should be precise and consistent which is 3000 rpm.
Figure 5 shows the electromagnetic torque response of a BLDC motor. The elec-
tromagnetic torque of a BLDC motor with the Hall sensor is the torque generated by
the interaction between the magnetic fields of the stator and rotor. When current flows
through the stator windings, it creates a magnetic field that interacts with the perma-
nent magnets on the rotor, producing a torque that rotates the rotor. The Hall sensors
provide feedback to the motor controller about the position of the rotor, allowing the
controller to adjust the current and voltage to the motor’s coil in a timely and accurate
manner to maintain the desired speed and torque output. The electromagnetic torque
generated by a BLDC motor with Hall sensors depends on various factors, including
the motor design, the number and arrangement of the stator windings and magnets,
and the current and voltage applied to the motor’s coil.
The torque output can be optimized through control algorithms that adjust the
current and voltage to the motor’s coils to maximize the electromagnetic torque output
while minimizing losses due to flux leakage and eddy currents. The electromagnetic
torque of a BLDC motor with Hall sensors is an essential factor in determining the
motor’s performance, efficiency, and suitability for a particular application.
Figure 6 shows the response of the stator current. The current control techniques
that adjust the current to the motor’s coils based on the Hall sensor feedback, such
as pulse-width modulation (PWM) or current regulation. The quality of Hall sensors
and the motor controller’s capabilities also play a crucial role in determining the
stator current response of a BLDC motor with Hall sensors.
Figure 7 shows the response of stator back EMF of a BLDC motor with the Hall
sensor. The stator back EMF is generated by the interaction between the magnetic
fields of the stator and rotor, which changes as the rotor rotates and the magnetic
fields vary. The response of the stator back EMF of a BLDC motor with Hall sensors
is important for determining the motor’s speed and position. As the rotor rotates,
the Hall sensors provide feedback to the motor controller about the position of the
rotor, which allows the controller to adjust the current and voltage to the motor’s
coil in a timely and accurate manner. This adjustment allows the motor to maintain
a consistent speed and position, with minimal variation in the stator back EMF.
Speed Control of a Brushless DC Motor Using Hall Sensor
Fig. 2 Hall sensor signals ((i ) h a (ii ) h b , (iii ) h a ∗ h b , (i v) h a , ∗ h b )

83
84
Fig. 3 Hall sensor signal for 3-phases ((i ) Ha − Ha , (ii ) Hb − Hb , (iii ) Hc − Hc ,)

M. K. Kar et al.
Fig. 4 Rotor speed response
Fig. 5 Electromagnetic torque (N-m) response

86 M. K. Kar et al.
Fig. 6 Response of stator current
Fig. 7 Response of stator back EMF

5 Conclusion
The speed control of the BLDC motor using Hall sensor is achieved using MATLAB/
SIMULINK environment. This allows them to be used in a wide range of appli-
cations, from small hobby motors to large industrial equipment. Different motor
parameters such as rotor speed, electromagnetic torque, stator current, and stator
back EMF waveform are observed. It is clear from the obtained result that the use
of the Hall sensor enhances the performance of the BLDC motor. The advantages
of using a BLDC motor with Hall sensors include high efficiency, low maintenance,
high torque-to-weight ratio, smooth and quiet operation, precise speed and position
control, wide speed range application etc. Overall, the use of Hall sensors in BLDC
motors provides many advantages over brushed DC motors, making them a popular
choice for a wide range of applications.
References
1. Sriram J, Sureshkumar K (2014) Speed control of BLDC motor using fuzzy logic controller
based on sensorless technique. In: 2014 International Conference on Green Computing
Communication and Electrical Engineering (ICGCCEE), March 2014. IEEE, pp 1–6
2. Lin YK, Lai YS (2011) Pulsewidth modulation technique for BLDCM drives to reduce
commutation torque ripple without calculation of commutation time. IEEE Trans Ind Appl
47(4):1786–1793
3. Ramya A, Balaji M, Kamaraj V (2019) Adaptive MF tuned fuzzy logic speed controller for
BLDC motor drive using ANN and PSO technique. J Eng 2019(17):3947–3950
4. Terzic B, Jadric M (2001) Design and implementation of the extended Kalman filter for
the speed and rotor position estimation of brushless DC motor. IEEE Trans Ind Electron
48(6):1065–1073
5. Xia K, Ye Y, Ni J, Wang Y, Xu P (2019) Model predictive control method of torque ripple
reduction for BLDC motor. IEEE Trans Magn 56(1):1–6
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speed control for BLDC motor. In: 2017 Conference on Emerging Devices and Smart Systems
(ICEDSS), March 2017. IEEE, pp 229–233
7. Jigang H, Hui F, Jie W (2019.) A PI controller optimized with modified differential evolution
algorithm for speed control of BLDC motor. Automatika: časopis za automatiku, mjerenje,
elektroniku, računarstvo i komunikacije 60(2):135–148
8. Wu HC, Wen MY, Wong CC (2016) Speed control of BLDC motors using hall effect sensors
based on DSP. In: 2016 International Conference on System Science and Engineering (ICSSE),
July 2016. IEEE, pp 1–4
9. Mamadapur A, Mahadev GU (2019) Speed control of BLDC motor using neural network
controller and PID controller. In: 2019 2nd International Conference on Power and Embedded
Drive Control (ICPEDC), August 2019. IEEE, pp 146–151
10. Anshory I, Hadidjaja D, Sulistiyowati I (2021) Measurement, modeling, and optimization speed
control of BLDC motor using fuzzy-PSO based algorithm. J Electr Technol UMY 5(1):17–25
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based fuzzy inference. Microsyst Technol 24:33–39
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motor. J Electr Eng & Technol 16:955–961
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13. Yadav R, Kar MK, Singh AK (2022) Speed control of a three-phase IM with closed-loop control
scheme. In: Recent advances in power electronics and drives: select proceedings of EPREC
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14. Yadav R, Kar MK, Singh AK (2021) Controlling speed of a permanent magnet synchronous
machine using closed loop control scheme. In: 2021 emerging trends in industry 4.0 (ETI 4.0),
May 2021. IEEE, pp 1–6
15. Tripathi SS, Kar MK, Singh AK (2022) Comparative THD analysis of multilevel inverter using
different multicarrier PWM schemes. In: Recent advances in power electronics and drives:
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system using PWM technique of D-STATCOM. In: Recent advances in power electronics and
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Implementation of Multifunctional
Electric Vehicle Charger Based
on ANFIS with Solar PV Array
Othuru Baba, S. Hussain Vali, Vempalle Rafi, and R. Kiranmayi
Abstract This article describes the development of a grid-connected, home-based

electric vehicle (EV) charger that meets the demands of an EV, household loads, and
the grid. The charger is powered by solar photovoltaic (PV) arrays. The charger is
built inside a solar panel array so it may operate independently while providing unin-
terruptible power and charging home loads. Nonetheless, the grid linked mode of
operation is possible if there is no or inadequate PV array generation. Synchroniza-
tion and smooth mode switching management assist the charger, enabling automatic
grid connection and disengagement without interfering with household supplies or
EV charging. In order to maintain local loads, the charger also offers active/reactive
power assistance from V2G and power transfer from V2H. Moreover, the charger
is set to operate as an active power filter, keeping the grid current’s total harmonic
distortion (THD) to less than 5% and maintaining a unity power factor (UPF). An
adaptive neuro-fuzzy inference system (ANFIS) is utilised to regulate the dc-link
voltage as part of an energy management method that is based on dc-link voltage
regulation. The sinusoidal reference grid current is supplied by a second-order gener-
alised integrator frequency locked loop with dc offset rejection (SOGI-FLL-DR) for
efficient operation under distorted voltage settings.
Keywords ANFIS · Electric vehicle · Solar PV generation · Power quality ·

Active power · Reactive power
O. Baba · S. H. Vali · V. Rafi (B)

Department of Electrical Engineering, JNTUA College of Engineering, Pulivendula, Andhra
Pradesh 516390, India
R. Kiranmayi
Department of Electrical Engineering, JNTUA College of Engineering, Anantapuramu, Andhra
Pradesh, India
90 O. Baba et al.
1 Introduction
Electric vehicle (EV) is gaining traction as viable alternative for nonrenewable

fuel-powered autos. However, charging infrastructure for EVs is critical. Electricity
required to charge electric vehicles is particularly energy-intensive and is frequently
generated by coal- and gas-fired power plants. As a result, EVs may be the pollu-
tion free alternative to today’s transportation provided the required energy to charge
them comes from flow resources such as solar, wind and other comparable sources.
The fact that this sort of charging station uses solar power that is generating and
using locally is advantageous. As a consequence, no upgrades to transmission lines
are required to accommodate the enormous power. When energy prices are high,
the charging station is not required to utilize the grid. It has been recommended
that solar PV panels be installed on office buildings and parking lots. Removing the
dc–dc converter step decreases the number of power stages by one, simplifies the
circuit, and lowers the price of converter reduces without decreasing the solar PV
performance.
The converter must be utilised for other reasons in order to boost the charger’s
working efficiency while the EV battery is not placed for charge. However, the
available literature employs a number of converters and controllers for a range of
operating modes. Furthermore, the charger’s operational capacity is limited by the
grid’s accessibility, how modes are switched between them, and other aspects that
affect the charger’s operational efficacy [1–4].
The promptness and precision of the dc-link voltage controller, on the other hand,
affect how effectively the energy management strategy works. Using an ANFIS
controller, unified control maintains the dc-link voltage in a three-phase power
converter. In many other publications, PI controller used to manage the dc bus
voltage in a manner similar to this. As a result, tuning the ANFIS controller to
accommodate unforeseen disturbances while it is operational is difficult. The dc-link
voltage control in this research employs an adaptive neuro-fuzzy inference method
to improve the system’s dynamic and steady-state performances (ANFIS). ANFIS
is well-known for its exceptional resistance to disruptions and unpredictability, such
as unexplained dissimilarity in control variables and system characteristic [5–10].
Figure 1 depicts the circuit architecture of the given charging mechanism. This
gadget integrates a solar PV array into the VSC’s de-link, transforming it into a 1-
phase two directional EV charger. The system feeds solar PV and EV battery power
onto the grid while also charging the EV battery with grid and solar PV power. In
this charger’s two-stage design, a two way ac-dc conversion step is follows by a
two way dc–dc conversion stage. When sending PV power and EV electricity to the
grid, the ac-dc conversion stage acts as the inverter, converting the dc voltage to the
ac voltage. While charging the EV battery, it also converts the input ac voltage to
dc voltage. The output of the two directional dc–dc converter is linked to the EV
battery (BDDC). The charger’s dc–dc converter does all of the necessary operations
[11–17]. When the EV battery is being drained, the dc converter functions in boost
mode, and when it is being recharged, it operates in buck mode.
Implementation of Multifunctional Electric Vehicle Charger Based … 91
Vpv
igg L ih S1 S3 S5
vs is Iev
Rf RfLc
vg Cdc
Cf E Cf Vd Lb
230V,50Hz PCC cb
S2 S4 S6
Single
Phase Supply Bidirectional AC-DC Bidirectional DC-DC
Converter Converter
Fig. 1 Charger circuit topology
PV array ipv
Additionally, it controls the dc bus voltage and maximizes the power provided by
the solar PV array. The coupling inductor connects the charger to the grid (Lc).
Harmonics be required to remove in order to smooth the grid current. To stop
switching harmonics produced by the VSC from being injected to the grid, a ripple
filter is additionally attached at Point of Common Coupling.
2 Problem Formation
Figure 2 depicts an energy management flowchart under various working states

expressed. In the grid-connected mode, steady-state energy management is as
follows:
PP V ± PB ± Pg − Ph = 0 (1)
Power from the PV array, EV, household load and the grid are represented as PPV ,
PEV , Ph , and Pg , respectively. The positive power in this phrase indicates generation
of power, whereas the negative power indicates power utilization. That the grid and
the EV may both create and consume energy. As a result of fluctuations in the solar
irradiance, home load and the current for EV charging the charger suffers a transient
in the grid mode operation. The change in PV array power should have no effect on
EV battery charging/discharging or residential supply because it only impacts grid
power.
As a result, a number of things happen in order to reach the system’s energy
equilibrium during an irradiance shift.
Irradiance ↑↓→ PP V ↑↓→ dc - link power ↑↓

92 O. Baba et al.
Fig. 2 Flowchart of energy management and operation strategy
→ Vdc ↑↓→ Vdc regulation → I P ↑↓→ i g∗ ↑↓→ i g ↑↓ (2)
In standalone mode, the energy management is provided as,
PP V ± PE V − Ph = 0 (3)
The change in home demand and solar irradiation both affect the energy balance
in standalone mode, just like they do in grid-connected operation. However, because
dc-link voltage is modified by EV battery, it adjusts for any power interruptions.
Energy management is achieved under household load changes is given as,
i h ↑↓→ dc - link power PP V ↑↓→ Vdc ↑↓

→ Vdc regulation → I E V ↑↓→ I E V ↑↓ (4)
3 Methodology
To maintain uninterrupted electricity to the house while the electric car is being
charged. Control is therefore designed in a way that permits multifunctional oper-
ation. The control is primarily bifurcated as islanded and grid linked modes, as in
Fig. 3 (GCM). The active and reactive powers, along with the V2H and V2G modes,
Fig. 3 VSC in combined control
are all covered by two main controllers. Methods for integrated bi-directional control
of islanded and grid connected dc–dc converters are investigated.
A. Grid connected mode
To regulate the flow of active and reactive power and produce pulsating pulses for
the VSC the GCM mode controls the dc link voltage and grid current. ANFIS is used
in this project to balance the MPPT and dc-link voltage of a PV array.
The expression for voltage error is,
∗
e = Vdc − Vdc (5)
The expected current is given as using the sliding surface as,
P + ,S>0
Id = { Pdc− ,S<0 (6)
dc
The imitative of the first order dc-link voltage is now obtained as follows.
Id 1
Vdc = − Vdc + μ (7)
Cdv Vdc R L Cdv
On basis of the Lyapunov stability requirements.

{ ( ∗ ∗
) } ( ∗)
S γ Vdv − Vdc + e = S{γ Vdc + e} (8)
{ ( ) }
Id 1
S γ − Vdc + μ + e (9)
Cdv Vdc R L Cdv
{( ) }
γ Id γ
S − Vdc + γ μ + e (10)
Cdv Vdc R L Cdv
94 O. Baba et al.
Now I d is selected such as S. S < 0

( )
1 1 1 ∗
Id = Cdv Vdc [ − Vdc + Vdc − (σ + δ)sign(S)] (11)
R L Cdv γ γ
The chattering phenomena may emerge with the current ANFIS control because
of the (σ + δ) sign (S) in (16). With the current ANFIS control, the chattering cannot
be completely eradicated. But by determining the small permitted steady-state error
and setting the amount of so that the (+) does not get too tiny, the chattering has
been kept to a specific frequency. Since is a positive constant, the definition of is as
follows:
||e||,v
e >0.1V
δ = {.1,ve <0.1V (12)
(1) VSC control in GCM
Figure 3 depicts VSC control. EVs and non-linear residential loads are respon-
sible for harmonics in the power factor and grid current also deteriorates. In the
interest of increasing power factor and guarantee the THD of grid current under
5%, a second-order generalized, integrator-frequency, locked loop with dc rejection
capacity (SOGI-FLL-DR) is employed to forecast the basic load urrent and makes
baseline current harmonic-free. Utilizing sampling hold and ZCD, Fig. 3 shows how
to extract the fundamental active load current component (Zero Crossing Detector).
The current active approximate expression is given as
i hp kωs 2
= 3 (13)
ih s + (k0 + kω)s 2 + ω2 (s + k0 )
where the load currents ih , ihp are the basic load currents. The frequency prediction
coefficient, k o is the dc rejection coefficient, k is the gain that controls speed of
prediction, and is the frequency.
The calculated total active current is as follows using (11) and I hp :
I p = Id − Ihp (14)
The reference grid current’s reactive current’s amplitude (I q ) is calculated using

(Qref ), and it is stated as,
2 × Q ref
Iq = (15)
Vtm
where the amplitude of PCC is V tm .

Immediate reference when the components of actual (I p ) and reactive (I q ) are
multiplied by the in-phase (ut ) and quadrature-phase unit template (qt ), the resulting
active grid current (ip ) and instantaneous reference.
Reactive grid current (iq ) are supplied as,
i p = I p × u t , i q = I q × qt (16)
Using the following formulas, ut and qt are produced.

vgp vgp
ut = , qt = (17)
Vtm Vtm
where V tm is the PCC voltage’s amplitude and V gp and V gq are its in-phase and
quadrature-phase voltages, respectively. The predicted unit templates also become
sinusoidal since these two voltages (V g and V s ) computed by the SOGI-FLL-DR
method become harmonic-free with the aid of V pg and V gq , the V tm is produced as,
/
Vtm = vgp
2 + v2
gp (18)
The total reference grid current is computed by multiplying the reference active
grid current (ip ) by the reference reactive grid current (ir ).
i g∗ = i p + i q (19)
A. Islanded mode control of VSC
The integrated system’s goal when operating in islanded mode is to use the PV
array’s electricity to run the household appliances and recharge the EV on its own.
Additionally, the V2H power transfer is used to power the home when the PV array
is not generating any power. VSC is regulated to act as just an inverter to supply the
load while it is in the islanded mode, as illustrated in Fig. 3. The controller creates
the voltage to do this shown in Fig. 3 by making use of the reference frequency and
voltage.
The reference voltage and the observed voltage are combined to produce VSC
pulses. The charger needs a grid connection in order to operate in “islanded mode” and
exchange two-way electricity. As PCC voltage, frequency and phase must match the
grid voltage, frequency and phase must also match. The grid connection is therefore
automatic and smooth. The controller forecasts the phase angles of the grid voltage
and PCC voltage in order to determine the phase error between both the two voltages.
Phase error across two voltages is lessened using the PI controller. The controller
uses the wrong frequency to generate the reference voltage for the rectified frequency
when the phases of two voltages are in phase with one another.
96 O. Baba et al.
4 Results and Discussion
The OC voltage and SC current are 460 V and 10 A, respectively of the PV array.
However, 396 V and 9.5 A, correspondingly, the peak power point voltage and
current. The experimental model’s electric vehicle (EV), battery is a 240 V, 35Ah
lead-acid battery. The charger runs by digital controller (dSPACE-1006). The digital
controller needs a number of signals (voltage and current) from the charger to execute
the control algorithm. The Hall Effect based voltage (LEM LV-25P) and current
(LEM LA-55P) sensors may be used to collect a variety of voltage and current
signals (analogue). A analogue to digital converter is used to transform these signals
from analogue to digital converter (ADC). The VSC and dc–dc converter’s switching
pulses are produced by the digital controller, which also analyses the digital input
and applies the control algorithm.
A. Charger performance in steady state
See Fig. 4.
B Dynamic performance of charger
The charger’s independence in running an EV charging station and providing elec-

tricity to a home’s load using power from a PV array is highlighted by a demonstration
of the charger in its isolated mode. When the solar irradiation is operating in islanded
mode, the residential load varies. As a consequence, Fig. 7 illustrates how the charger
functions when there are disruptions (Figs. 5, 6 and 8).
5 Conclusion
The implementation of multifunctional EV integrated charger with a solar PV array,

residential load, and grid. The results obtained that it is possible to simultaneously
power homes in both grid-connected and islanded modes. These tests indicate that the
charger is functioning as intended when charging EVs. Serving loads while retaining
the grid’s quality of electricity.
(a)
(b)
(c)
(d)
(e) (f)
Fig. 4 a Voltage of grid (V). b Current of grid (A). c Charging voltage (V). d Charging current
(A). e THD of V gv . f THD of I gv
98 O. Baba et al.
Fig. 5 a Under change in household load. b Generator power. c derating of MPPT. d Performance of
solar irradiance power in varying conditions. e Voltage and current under charging and discharging
of EV battery. f Household current
Fig. 5 (continued)
100 O. Baba et al.
Fig. 6 Reactive power performance of vehicle to grid
Fig. 7 Active power filter and distorted voltage condition operation performance
Fig. 8 Difference between using PI, SMC and ANFIS dc link voltage regulation
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Axial Flux Motors for Suspension,
Levitation and Propulsion System
of Hyperloop-A Review
Richa Dewangan, Suresh Kumar Gawre, and Shailendra Kumar
Abstract Begun in 1904, the vactrain concept was first introduced by Robert H.
Goddard. This concept has a potential to bring about a revolutionary change in the
way we contemplate transportation in our daily lives. In today’s fast paced life style,
the time taken to travel on an average by any human being is roughly 228 h in a year
and we spend roughly 10% of our total income for the purpose of commuting. The
concept of vactrain has been modernized as hyperloop transportation which has made
substantial progress in the recent years. This system can be used for both passenger
and freight operations which are 5 times faster in speed, relatively economical and
environment friendly mode of traversing. With research and development taking
place globally, one of the technical demanding issues involves effective suspension,
levitation and propulsion. The suspension and levitation system has been evolved
by utilizing Electromagnetic suspension, Electro dynamic suspension and Electro
dynamic wheel. Likewise, the propulsion system utilizes the use of different config-
urations of linear induction motors. Motivated by several studies on Hyperloop, we
have researched on ‘lightweight Capsule solutions’ (LCS) which employs a hybrid
excited EDS along with EDW based on axial flux motors. Axial Flux permanent
magnet machines (AFPM) is a capable contender for electric propulsion applications
owing to its high-power density, high efficiency and effective volume utilization. It
has the highest possible torque to weight ratio in comparison to radial flux perma-
nent machines (RFPM). The most promising AFPM structure (TORUS) that can be
employed has been presented in this review.
Keywords Electromagnetic suspension (EMS) · Electrodynamic suspension

(EDS) · Electrodynamic wheels (EDW) · Wheel on rail suspension (WRS) · Linear
induction machines (LIM) · Axial flux permanent magnets (AFPM) · Rotating flux
permanent magnets (RFPM) · Maglev (magnetic levitation) · TORUS machine
(doughnut shaped/tire shaped) · Yokeless and segmented armature (YASA)
R. Dewangan (B) · S. K. Gawre · S. Kumar

Department of Electrical Engineering, Maulana Azad National Institute of Technology,
Bhopal 462003, India
104 R. Dewangan et al.
1 Introduction
The concept of hyperloop has evolved majorly from vactrains, air cushioned suspen-
sion and tube trains. When compared to existing systems of transportations it is
probably the fastest mode of traversing both theoretically and practically [1]. Since
capsules inside the tube levitates and propels in near vacuum conditions it overcomes
the two main drawbacks of existing systems—friction and air drag [2]. Today in the
21st century, it has become a reality quickly progressing from its developmental stage.
The speed that has yet been successfully attained in the capsule in Nevada desert
carrying two passengers by a ‘virgin hyperloop’ is about 172.2 km per hour within
6 s for a distance of 0.39624 kms and the entire experiment lasted for about 16 s.
This speed is comparatively less to the existing speed achieved by 2G high temper-
ature superconducting magnets for subsonic speed [3]. Such high-speed application
requires high power input which is provided by using the DC-to-AC power electronic
converter and the microcontroller [4, 5]. To make it energy efficient a battery storage
comes under consideration [6]. The aim is to achieve a system independent of grid
and keep it stable [7, 8].
A systematic study of the hyperloop and policy making decisions for future scope
has been drafted by Gkoumas [9] using an optimal design of the propulsion system
[10] with communication limitations [11]. The potential of two Hyperloop networks
within Europe was studied. The results indicate that the Hyperloop could be used as
an alternative to rail or air travel, but a different Hyperloop network might be needed
as explained in [12]. Existing technologies use linear induction machines at either
primary or secondary levels; double sided or single sided for the purpose of guidance
in tracks [13–15].
The newest technology involving the use of axial flux motors which is potentially
the most significant change in upcoming industries and has been grabbing the atten-
tion of the entire automotive world is discussed in detail in the papers [16–23]. A
slotted Torus type axial flux machine as described in paper [24] is the most practical
approach proved so far. A detailed study of noise reduction, energy density simula-
tion and ripple reduction are done for Torus machines. The conceptual application
of axial flux machines in the aircraft system to reduce the weight of the aircraft with
higher torque to weight ratio as compared to the existing system is one of the most
feasible solutions that can be employed and researched on for the hyperloop system.
As an ongoing development to the employees, Axial Flux motors have been used as
motors for rotating the propeller blades to provide linear thrust proving to be extraor-
dinarily efficient. Multi-stack axial flux permanent magnet generator (AFPM) for a
hybrid electric vehicle which can be controlled with sensors despite the compound
structure is designed and modified using Motor-CAD using Multiphysics simula-
tion tools. Comparison of Halbach arrays, axial and radial flux provides a detailed
explanation of ease with which we can implement in thehyperloop. Also, coreless
AFPM motor and is feasibility is checked for the drive system for constant power
application.
Axial Flux Motors for Suspension, Levitation and Propulsion System … 105
The structure of this article is as follows. Figures 1, 2, 3, 4 and 5 depict the different
suspension systems under Sect. 2. It consists of a brief description which can be
employed for hyperloop systems. The advantages and disadvantages are tabulated
in Table 1. The paper progresses forward by mentioning the propulsion variants
employing Linear induction machines under Sect. 3. Equations (1)–(4) describe
the elementary governing formulae of induction machines. Section 4 progresses
with different types of Axial Flux machines and their promising topology. These
topologies are currently employed in Hybrid Electric vehicles in many companies.
Rolls Royce and Magnex are currently involved in extensive research on these types
of motors and have simulated proofs of its efficiency. YASA is the topology with an
efficiency of over 97%. Section 5 explains the light weight capsules solutions (LCS).
Fig. 1 Electrodynamic suspension [2]
Fig. 2 Electromagnetic suspension [2]

Finally key challenges and research opportunity in accordance with the companies
involved currently is highlighted in Sects. 6 and 7. Followed by conclusion in Sect. 8.
Fig. 3 Electrodynamic wheels suspension [2]
Fig. 4 Wheel on rail suspension [2]

Fig. 5 Air cushioned suspension [2]
Table 1 Comparison of various suspensions

Comparative analysis of various suspension systems
Suspension Advantages Disadvantages References
variant
EDS • Highest levitation speed • Capsule needs simple [1, 2]
• Inherently stable (active control auxiliary wheeled system
needed is not needed) • Creates high drag energy
consumption
EMS • Levitation at low speed and • Inherently undamped and [3, 4]
standstill is technically easy unstable
• Uncomplicated guidance • Precise monitoring to
maintain levitation height
EDM • Thrust force is created rather drag • High mass of wheels [5, 6]
due to rotating magnets
WRS • Simple design • Cannot reach beyond [7, 8]
580 km/h
ACS • Low friction and drag is possible • High energy consumption [9, 10]
at supersonic speed of compressor
2 Suspension Types
The type of suspension decides the degree of friction forces the pod will suffer along
its path. For example, WRS will cause more friction as compared to EDW type. A
collective analysis of these suspensions is done in Table 1.
2.1 Electrodynamic Suspension—EDS
Contrast to the EMS presented in the next sub-section, here repulsive forces are
instead used for levitating when the electro-dynamic suspension (EDS) system comes
into the picture. Due to the interaction between a conductive material and a closely
traveling magnetic field these forces appear. Magnetic liftable sky moves over this
potential track which induces eddy currents following Faraday’s and Lenz’s law.
This levitator can be composed furthermore with superconducting magnets (SCMs)
or iron-less Halbach arrays with permanent magnets [1, 2]. The Halbach arrays which
are flux-concentrated enhance the usefulness of PM materials.
The most crucial disadvantage of the EDS is that the forward motion (‘lift-off
speed’) is mandated for the levitation action to be delivered. This suggests the neces-
sity of additional ‘landing and take-off wheels’ to levitate the capsule at shallow
speeds and at stalling conditions. Nevertheless, this is comprehended as a rather
insignificant issue assuming that the EDS is uncomplicated, durable, fail-proof, and
negligibly costly to function at high service velocities. It doesn’t need unnecessary
dynamic modification of the magnetic field to attain steady suspension, although
the levitation stature isn’t forthright controllable. The magnetic drag becomes low
at high speed; opposite to the near eroding ‘frictional’ drag of gyration (wheeling
motion) or aerodynamic drag of airplanes.
2.2 Electromagnetic Suspension—EMS
The electromagnetic suspension (EMS) levitation is established by attractive forces

between ferromagnetic materials and field-wound electromagnets. Usually, the
guideway is assembled from ferromagnetic iron, whereas the cabinet of the vehicle
has functional coils that regulate the attractive force to the iron beam [3, 4]. This
is realized with a control loop in the feedback that balances the levitation of the
EMS. There is no need for separate ‘landing’ wheels since the force of suspension
is independent of the motion.
2.3 Electrodynamic Wheels—EDW
A standard design of a cylindrical PM Halbach Array rotates to induce its field on

an inactive surface which is inherently conductive. This happens in EDS (electro-
dynamic wheel similar to EDS). This induced field is opposed by the eddy currents
developed inside the surface. EDW is different from other suspension systems
because it can generate coexisting levitation and thrust forces. It makes use of
the radial magnetic array’s rotation by generating a forward thrust force instead
of decreasing its motion due to backward drag force. Nevertheless, this entire setup
demands a rotational movement which introduces the need for a rotating motor that
causes loss in terms of mechanical energy. Yet, a high levitation-to-weight ratio is
achieved with an increased rotary speed [5, 6]. The concept of EDW is only theoret-
ical as only a few industrial players are designing or even accepting it as a potential
solution. Therefore, this comes under a soft Technology readiness level (TRL) and
is not yet motivated up to conveyance purposes.
2.4 Wheel-On-Rail Suspension—WRS
The wheel-on-rail system (WRS) is a traditional technique for both suspension and
propulsion. Yet, wheels don’t form a suitable model that can be used for subsonic
or near-sonic speeds proposed in the HTS [7, 8]. Due to frictional losses, excessive
heating, centrifugal forces, and dynamic instability its feasibility quotient reduces.
The wheels experience all the forces especially rolling friction drag.
2.5 Air-Cushioned Suspension—ACS
Proposed in 2013 ‘Air Bearings’ was the original concept before the Vac Train was
renamed Hyperloop. However, no solid backdrop computations were conclusively
presented for this solution [9, 10]. The air from surroundings is compressed into
a cushion due to which the so-called air-cushioned suspension (ACS) levitates the
capsule. Its principle is the same as that of the hockey table’s aerodynamic lift.
3 Propulsion Variants
3.1 SP-Type LIM (Sort Primary Linear Induction Motor)
Eddy current is induced on a conducting sheet due to the traveling magnetic wave
in the linear induction motor (LIM), which generates a Lorentz Thrust force (that
is the same as the rotating induction motor). The infrastructure wherein the stator
coils are present on the vehicle and the guide-way is composed of the conducting
reaction material which is devoid of electrification along its length, is called a short
primary linear induction motor (SP-LIM) thus making it much more suitable and
affordable (Especially, when aluminum material is added to the guideway). The
overall construction cost is lowered because of this. The EM waves from primary
windings have faster synchronous speed (vs), whereas the mechanical speed is lower
(v) with a slip ‘s’ and is explained by the relation as shown below.
v = vs (1 − s) (1)
The slip varies precisely in the range of 10–20% in linear machines (a lot higher in
comparison with the rotary machines). This lowers the maximum feasible velocity
thus making it inconvenient for achieving ‘near-sonic speed’. Since the air gap is
large; larger induction is required in the same proportion [11, 12]. This impacts
efficiency in an undesired way, as it is constricted by ‘s’ as shown from the formula
in (2)
ηL I M = 1 − s (2)
This topology has been considered for low-to-medium speed maglev trains, such
as Korean UTM (110 km/h) and Japanese HSST (100 km/h) because of its low drag,
low edge coefficient, and low energy efficiency. This topology is favourable because
of the low cost of electrification and is considered for super-high-speed HTS as well.
The main reason for such an application is that at ultra-high HTS speed, its capsule
can store a sufficient amount of kinetic energy. Apparently, during deceleration SP-
LIMs can regenerate a substantial amount of this energy and can be operated as an
‘energy harvester’. Despite that, this harvested energy must be consistent with the
maximum rate of charging of the onboard storage system. A single-sided LIM can
be configured from this solution of SP-LIM.
3.2 SP-Type LRM (Short Primary—Linear Reluctance

Motor)
The core principle is that when the primary armature coils interact with a ferromag-
netic rail due to reluctance it produces motion. In this way, the linear reluctance motor
operates [2]. The track has salient poles, segments, or notches. The primary coil in
the vehicle generates a magnetic traveling wave that synchronizes with the capsule’s
motion based on the continuous attractive force it experiences due to salient poles
along the track (creating a forward motion).
3.3 LP-Type LIM (Long Primary—Linear Induction Motor)
In classical machine terminology where the linear induction motor (LIM) has a long
stator and a short stator is considered a long primary (LP). Hence, the guideway
consists of active stator coils along its length while the vehicle is integrated with
conduction plates onboard. Since there will be electrification throughout the track,
the cost of construction is higher when compared to SP-LIM. LP-LIM was the
initial concept of hyperloop without putting coils along the whole track but instead
putting them in distributed spots for soft pushing [13, 14]. However, the intricacy and
expenses will still touch clouds. Additionally, a lot of unusual leakage of main flux
happens due to its path being the air gap between these two bodies. This efficiently
reduces the energy efficiency of LP-TYPE LIM.
3.4 LP-Type LSM (Long Primary—Linear Synchronous

Motor)
With the guideway being long primary (LP) in a Linear Synchronous motor (LSM),
a magnetic synchronism is maintained between both the stationary and magnetic
parts. This ensures that the mechanical speed (v) is equivalent to the synchronous
speed (vs) of the magnetic wave. Thus, the pole pitch needed will be as shown in the
formula:
τ p = v/2 f (3)
With known values of the ‘service speed’ (v) and frequency of supply (f), the
possibility of constructing a short primary linear synchronous motor (SP-LSM) with
‘back-to-back’ poles becomes easier. Yet, the machine becomes bulky and is the
prime reason why this mode of transportation isn’t preferred for practical appli-
cations. Whereas, the LP-LSM requires most of the components on the stationary
guideway thus saving the space and weight of the vehicle (LCS). Even the onboard
vehicle doesn’t consist of immediate propulsion power it is provided externally.
Hence, along the total track length (L), the minimum number of phase coils (Nc) is
given by,
N c = 3L/τ p = 6L f /v (4)
Assuming (_p) as the pole pitch of a three-phase system is supposed.

To make the coils stronger along various sections of the track despite the tremen-
dous amount of ‘active material’, the coils must be designed accordingly. Precise
infrastructure is a must in areas (section along the track) where heightened de-
acceleration and acceleration functionality is needed [15, 16]. Thus, material can
be saved through various segments of the track. This entire construction turns the
guideway into a principally functional ‘Linear Motor’. Generally, the pod (capsule) is
composed of permanent magnets, thereby making it low on energy. But, that’s how
many kinds of active (magnetic) material is underutilized throughout the system.
Except, in cases where superconducting magnets are used e.g. ‘JR-maglev MLX’,
only the EMS is compatible with a low air gap height.
The interplay between the ESM/LSM consists of propulsion and levitation mecha-
nisms coupled together. This coupling has an impedance that needs to be minimized
and this calls for constant control. Regular sensing of position and height is also
required.
4 Axial Flux Machines
Axial flux permanent magnet machine (AFPM) is an apt contender for applications in
electric propulsion because of its high efficiency, high power density, and maximum
utilization of the entire machine volume. Recent progress in AFPM technology,
particularly for electric vehicle propulsions (EV), concerning design, various poten-
tial topologies, modelling, mechanical and thermal analysis involving the usage of
advanced materials, and aspects of construction have been mentioned in this section
[17–22].
4.1 Different Types of TORUS Topologies
The concept of TORUS machines comes from their constructional shape (resembling
a toroid). It consists of the rotor as an external structure and the stator as an internal
structure. The stator is made up of strip wound steel and is slotted evenly. These
slots are used to hold the polyphase windings. The two disc-shaped rotors are axially
magnetized with the help of arch-shaped permanent magnets made of “Neodymium
Iron Boron (NdFeB).” These permanent magnets are placed on the rotor disc’s inner
surface. There are two basic types of TORUS machines and are differentiated based
on the flux’s path through its structure. They are TORUS NN and TORUS NS [23].
In the TORUS NN construction, the magnetic flux passes through the stator and
moves along the stator core along its circumference. In the TORUS NS construction,
the magnet-driven flux pass through the stator and axially moves along the axis of
the machine axis. This results formation of a ‘stator-less yoke’ theoretically.
Withal, a winding that is wrapped in a ‘Back-to-back’ configuration is employed
for a TORUS NN type machine. Whereas, in a TORUS NS type construction, lap
winding is short-pitched to produce the desired torque.
In construction where one stator is sandwiched between two disc-shaped rotors is
considered a basic TORUS structure. Figures 6 and 7 represent the axial flux TORUS
machine which is surface mounted slotted PMs—NN and NS type respectively. Both
these machines differ from each other in terms of the arrangement of the polarity of
magnets, armature winding placement, and stator yoke’s thickness.
Torus NN type. In each of the back-to-back stator slots, the direction of flow of
current is reversed. In this topology, a back-to-back winding structure is employed.
The windings are wrapped in the same way around the stator periphery to justify
the back-to-back winding [24]. The magnet-driven flux enters the stator from N-
pole and travels through it in such a way that it covers the path through the stator
circumferentially and exits when it finds the south pole of the rotor. Thus, completing
Fig. 6 Representation of axial flux machines a expanded view b actual view [17]
Fig. 7 Slotted TORUS machine NN-type [24]
a flux path that travels is equal through the stator as well as the rotor (permanent
magnets).
Torus NS type. As it is similar to the winding of the toroid, the current in the
stator flows in the direction same as that in each of the back-to-back slots. The flux
from N-pole in the rotor (Permanent Magnets) enters the stator and passes through
it to the adjacent S pole of the rotor. This flux moves to the N-pole of the rotor and
closes its path in the same way as before to enter the N-pole of the Adjacent rotor
through the stator [25]. Thus, the magnetic flux travels majorly through the rotor and
a small path through the stator.
The stator and rotor of the axial machines have the same physical structures but
differ from each other concerning the arrangement of the winding and the thickness
of the stator yoke. The TORUS NN type requires the stator to be of Iron because the
main flux travels axially through it. This is not necessary for the TORUS NS type.
This makes the TORUS NS type to have decreased axial length and iron losses. This
also implies a stronger power density and increased efficiency. Regardless, using
Lap winding in this structure results in lengthier winding and winding at the end.
Due to this, the outer diameter is bigger implying higher copper loss and slightly
reduced power density and efficiency. On top of this, for obtaining a proper flux path
in TORUS NS type the poles facing each other in rotors must be of N and S type or S
and N-type. For NS structure, this combination must be of N and N or S and S type.
Thus, the direction of the current must be manipulated to ensure a complete closed
flux path and to create torque [26–30].
5 Light Weight Caplsues Solution (LCS)
The Long Primary—synchronous motor’s (Linear) “electric propulsion can be

combined with the H-EMS (hybrid excited EMS) levitation system.” It can be
constructed without Permanent magnets, but then the field windings will have to
collectively supply the entire excitation for LSM and the ‘levitation force’ of the
EMS. Primary suspension can be tolerated with the schematically designed H-EMS.
The height in the air gap can be governed and handled by the current in the field
winding. Making the track inherently laminated is helpful in reducing energy required
since drag due to magnetism is comparatively less. Since we are looking for securing
the reliability of suspension theoretically at ‘subsonic speed’ and ‘near-sonic speed’
we must enhance the functionalities of H-EMS to focus on these aspects. Avoiding
contact between the track and the vehicle at any speed is the most important thing.
Earnshaw’s theorem clearly explains how a system is by default unstable against
perpendicular movements [31–35]. Maintaining such a small air gap (height) requires
an extremely precise feedback control that also includes monotonous behavior.
Furthermore, the irregularities of the track and deviations which are dynamic in
nature must be dealt with ease using this control scheme. Even minute failure during
sensing or minor collapse in control systems can lead to grave outcomes. The EMS is
the most suitable suspension (in comparison with hydraulic machine-based suspen-
sion) with more satisfactory shock absorption even at the corner points present in the
track but is solely dependent on the power supply making it predisposed to malfunc-
tioning and causing huge losses. Nevertheless, a solution consisting of both EMS and
EDS is suggested as a hybrid solution to bargain with this multidimensional situation.
Still, ‘bottom-configured EMS’ is the only suspension that can dodge mechanical
contact. In this commission, ski pads for raising are positioned beneath the carriage,
So that in case the central levitation fails the entire process continues. On the other
hand, the ‘top-configured EMS’ would undoubtedly result in colliding as a result of
a breakdown. This is not permissible if a power outage ensues.
Another intrinsic drawback of the LCS is the fact that the LP-LSM needs expensive
infrastructure and power supplies along the route that must be maintained constantly.
Fig. 8 Employing axial flux machines as wheels or as compressor [Aircraft systems] can reduce
the requirement of complete vacuum tubes and help in achieving high speed by providing required
thrust
Regardless, one could plan to incorporate renewable resources or solar panels to mini-
mize the environmental consequence of the large-scale infrastructure, i.e., exercise
land that is occupied to its full potential. Yet, the electrification infrastructure will be
uncompellingly pricy, and the cost when compared to the tube infrastructure already
required to enable Hyperloop as a fully functional applied science will reach sky
high (Fig. 8).
6 Key Challenges
To date, very few demonstrators have reached the speed of 650 km/h whereas the
expected speed by Hyperloop on a real-life scale is approximately 1000 km/h. To
achieve a speed equivalent to this theoretical value Hyperloop lines require curves
with an incredibly large radius. The the traveling speed of this mode of transport
will become a ‘turbulent roller coaster of senses.’ if there aren’t any changes in
the physical traveling lines. In actuality, regardless, it has to be made available to
all public when analogized to the conventional mode of transportation. The various
speeds achieved by the other fast modes of transportation are given in Table 2.
Table 2 Speed achieved by competitors of Hyperloop

Criteria/type of transport Current status of different transportation systems
Energy required (W h/km) Speed (km/h) Passengers (per capsule)
Monorail 2120 60 180
High-speed rail 28 250 1300
Maglev 24–27 605 574
Airplanes Varies 876 130
Hyperloop 400–500 10780.26 28
Since Hyperloops can function on green energy with almost zero carbon footprint
it still doesn’t hide the fact that the energy required for its usual running condition is
extremely ‘high’. This “high” energy [36–38] requirement is because of the constant
maintenance of a partial vacuum within the tubes.
Implementation of the capsule which runs at a very high speed inside a vacuum
tube is not an impossible task, but ensuring passenger safety throughout the passage
results in increasing the cost of maintenance and still poses one of the major chal-
lenges. Also, there has to be a regulatory framework that directs all the organizations
to submit their norms limited to precise legislation. But doing this can restrict the
development of Hyperloops.
As for problems of interoperability, it can be solved if all the organizations
collectively join hands to progress and research different approaches. Or the leading
company acquires the entire market and neutralizes competition to work together.
Although as mentioned above this can lead to restricted outcomes as everyone is
working on strikingly different technologies.
Thus, all the Hyperloop players must project their superiority to move further
than the Swiss Metro. It was launched in 1992 and came to an end when the
authorities discarded the project as incapable due to being unfinished within the
time range.Today, Elon Musk is being appreciated for reintroducing the concept of
the hyperloop and popularizing it by conducting competitions around the world to
build prototypes. The ‘Hyperloop’ brand acquired by Richard Branson under Virgin
companies with the engineering extravagant mind of Josh Geigle has demonstrated an
extraordinary feat of successfully running a passenger capsule. With this successful
run, there are more chances to observe over the next few years when the hyperloop
will become feasible for an everyday audience. Untill then some barriers remain as
described below.
6.1 Business Case
A feasibility study that is done preliminary to the start of a project is called a ‘Business
case’. The prices are cogitated against the advantages and in this way, a conclusion
can be drawn about whether or not to resume the project. Unpretentiously, the scheme
is initiated once the benefits overpower the capital investment [39]. For the hyperloop,
such an inquisition into expediency should also be done. Fascinating factors here are
which groups or individuals can sponsor the hyperloop and who will profit; what
will be the cost of the hyperloop once this starts operating for the public.
6.2 Emergency Exits
Trouble in some form always exists for the hyperloop. Unwanted emergencies could
occur in tubes and create an emergency to evacuate the people on board. To design
such an emergency system that can include both security and within the budget range
is a complicated task. To classify the type of emergency as critical or non-critical is
a challenging task and probably undefined.
Since the hyperloop is a fairly new concept and is still in its developmental stage,
there is an unavailability of practical data with bare minimum experience [40]. It is
formidable to resolve what is adequate in terms of safety.
6.3 High Speed Switches
A network that contains a central hub linking various lines in a way similar to
existing metros can form a great hyperloop grid. Nevertheless, other options need
to be researched on for reducing complexity. To directly connect and form such
a transportation system all links must collect pods at a single point and those pods
must be provided with a stand to stop. Links passing through these stations must have
elevated floors and vice versa at the station comparable to the roadways system. This
system will provide the pods to cruise smoothly. In case there aren’t any stoppages
at the stations, the links can be switched directly to the ramps which will isolate the
path from the station and allow a direct link to the main line of transport.
High-speed switches [41–43] come into the picture when we want to ensure that
the system has higher efficiency and reduces the average travel times. High-speed
switches are being researched with the development of semiconductor materials thus
making the system faster, advanced, and more reliable.
6.4 Road to Implementation
Hyperloop is undergoing a dynamic trend of ups and downs in the current transporta-
tion sector. More and more organizations are coming forward with their innovative
technology but still lagging due to a lack of capital investment or free will. Certain
companies like Elon Musk’s hyperloop had open-sourced the technology for devel-
opment. Whereas most companies like Zeleros have been working independently
although these are contributing to collective development. To streamline this vision,
it is important to ensure that all companies come under one umbrella to accelerate
growth efficiently. In other words, the presence of a standard design and a central
organ for regularizing. This will guarantee that the hyperloop system is not scattered
across various issues.
However, limiting individual organizations to compromise with their ongoing
projects and bringing them under single-handed control cannot be considered a solu-
tion. Hence, the only way to achieve speedy development is when one or two of these
competing companies can establish a practical model. This will attract nations to be
a customer of the new technology thus producing a standard design.
6.5 Standardization
Standardization is difficult to achieve since the hyperloop concept has various original
concepts. Thus, to converge this entire plethora of versatility is challenging to acquire.
Hence individual designs must be made to follow a certain set of common rules but
must be allowed to vary the concept at different levels based on the requirements.
Thus, this brings standardization of the hyperloop without losing essential elements
gained on the road to discovery.
6.6 Levitation
Due to variation in guideways, the levitation systems may differ for application
purposes. Several levitation systems are defined in [44]. Levitation mechanisms play a
rather important part in defining how efficiently a tube could propel without impacting
the guideway. To ensure an obstacle-free and smooth ride the design of the guideway
must be standardized. But this isn’t possible because a single levitation mechanism
hasn’t been established. Thus, a standard levitation mechanism must be developed
which is proven superior to all other mechanisms thereby providing a set of rules for
faster development of the hyperloop. Firstly, these obstacles need to be overcome:
• Well-developed EMS system that can be relied upon (because in case of a power
outage the safety of the system must be ensured and EMS forms the basis of active
systems)
• A guideway for the EDS system must be developed with a higher Drag/Lift which
doesn’t suffer from air friction.
6.7 Financing the Hyperloop
Hyperloop without a doubt is an expensive affair until its technology is well estab-
lished. To date, the maglev concept has been employed in China and Japan. Even
though the hyperloop and maglev both are expensive, maglev didn’t gain momentum
in the market. Despite the hyperloop being much more advantageous, it must be
protected from facing an analogous situation [45] and being shut down entirely.
To avoid such a shutdown, financing parties and companies must come together to
survive and support this innovation.
7 Research Opportunities
To reduce the cost of infrastructure: To make a system that is potentially affordable

and maintainable, one must focus on incorporating propulsion equipment on the
pods/capsules rather than just the tube. The concept in totality must be to utilize the
magnetic levitation to give a frictionless hyperloop ride and use axial flux motors
for propulsion either at the back as ‘pushing force’ or beneath the pod as auxiliary
wheels during the start and stop of the vehicle. The advantages of axial flux motors
have shown to be overpowering the existing motors. A company named Zeleros has
been able to incorporate a turbofan at the front of the tube and minimize the air drag
build-up by creating a suction of the air at the front of the capsules. They also aim at
keeping the pressure of the air inside the tube equivalent to the pressure outside. This
is entirely different from other standard approaches that aim at eliminating the air
drag by putting the inside of the tube at lower pressures. Since we know how safety
can be practiced by keeping the tubes under standard pressure as in the airplanes, The
security precautions can be easily guessed and implemented. The biggest drawback
of keeping the propulsion equipment on the tube is that it increases the maintenance
cost of the entire setup and creates hurdles as repeated replacement is not possible.
7.1 Magnetic Levitation Simulation and Turbofan Airflow
Simulation of magnetic levitation is necessary for a vehicle that is wingless and floats
inside a tube. It must have sufficient lift and thrust without having any contact with
tube walls. It may be analogous to a piston inside an engine and is a tight fit. Such
a configuration requires a combination of permanent magnets and electromagnets
located on the top and bottom of the vehicle. A gap sensor is used to precisely measure
the distance so that tube floats without any hindrances [46–50].
The electromagnetic field created by the axial flux motors placed on the pod must
not interact with the tube’s magnetic field in a way that may disrupt passengers’
journey. The effect of turbofan on the tube and the kind of motor used needs to be
explored. This can be achieved while simulating the design. The consequences of
electromagnetic radiation on humans must be studied and carefully designed. The
pods must be made of an impermeable material that protects the inside of the pod
from any kind of turbulence related to magnetic interference or the pressure difference
from surroundings. These effects need to be studied while simulating the tubes. Using
simulation software is necessary to eliminate the possibility of an unstable system.
For small-scale testing, these simulations must include variables like the mass of the
pod, fluid dynamics, and boundary conditions.
8 Conclusions
The axial flux concept was the concept that was used by Michael Faraday some
200 years back to make the first electric generator. However, this motor didn’t see
the light of the day back then. Today it is the most powerful lightweight motor that can
revolutionize electric vehicle and more importantly in the electric aviation sector. It
is lightweight making it suitable for soaring freely in the sky or within the tube. This
paper clearly presents multidimensional applications of the use of axial flux motor
in the hyperloop so that the tubes can achieve subsonic speed with less weight and
higher efficiency inside vacuum. Already companies like Rolls Royce and Magnex
have been doing intense research and development on this type of motor. Ion-Bird
craft developed by Rolls Royce uses three such motors by ‘Yasa’ having an efficiency
of more than 96%. Axial flux machines have recently seen concentrated application
in electric vehicles as well, thus making a suitable candidate for hyperloop systems.
Axial flux machine as mentioned in the sections above can be implied in capsules/
pods for levitation. The entire system runs on electricity harnessed by solar power
and doesn’t release air pollutants. Thus, the availability of a hyperloop for regular
means of transport will help in reducing the traffic and travel time.
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Aerodyn 212:104591
A Generalized Symmetrical
and Asymmetrical Multilevel Inverter
Topology with Reduced Number
of Components
Ragul Duraisamy and Thiyagarajan Venkatraman
Abstract In the modern technological world, Multilevel Inverters (MLI) are

preferred over square wave inverters for medium and higher voltage applica-
tions. They offer beneficial merits such as low Total Harmonic Distortion (THD),
reduced voltage stress, power quality improvement, and high reliability during faults
compared to traditional inverters. However, large components, circuit complexity,
and high cost make the concept unattractive. So, this paper focuses on simple gener-
alized symmetrical and asymmetrical MLI with less components suitable for renew-
able energy and electrical drive applications. The switching signals are generated
by an efficient nearest voltage level algorithm technique. In our paper, two-module
9-level symmetrical and 21-level asymmetrical MLI are taken to validate the circuit.
The novelty has been proved by comparing their performance parameters with other
configurations. Further, by cascading the proposed topology in series, the gener-
alized equation for parameters has been developed. The topology has been simu-
lated by MATLAB/Simulink. Then its results are tested under R and RL loads. In
the asymmetrical case, THD satisfies the IEEE standard and eliminates the filter
requirements.
Keywords Multilevel inverter · Total harmonic distortion · MATLAB/Simulink
1 Introduction
Multilevel Inverter (MLI) occupies a major portion in the field of power electronics
DC-AC converters due to recent technologies such as solar energy sources, micro-
grids, and distributed generation concepts [1]. It is a combination of DC sources
and low power rated power semiconductor devices to generate stepped voltage
signal similar to sinusoidal waveform and is used for applications such as grid
R. Duraisamy (B) · T. Venkatraman

Department of Electrical and Electronics Engineering, Sri Sivasubramaniya Nadar College of
Engineering, Kalavakkam, Tamil Nadu 603110, India
124 R. Duraisamy and T. Venkatraman
synchronization of non-conventional DC renewable sources, electrical vehicles,

solid-state transformers, and static VAR compensators. As a standalone system, MLIs
are normally preferred for integrating solar energy sources with the electric drive
domestic pumping system [2]. The advantages of MLI are low harmonic distortion,
lower electromagnetic interference (EMI), no filter requirement, fault-tolerant capa-
bility, and compactness compared to square wave inverter, but it has some limitations
such as higher cost and circuit complexity [3]. The basic classifications of multilevel
inverters are flying capacitor MLI, diode clamped MLI, and cascaded H-bridge MLI.
Among these, cascaded H-bridge is popular because of no voltage balancing issues,
less harmonics, modular structure, and being suitable for solar-based distributed
energy generation. Based on DC source value, it is again categorized as symmetrical
and asymmetrical MLI. The symmetrical MLI has equal sources while the latter has
unequal DC sources. The former topology is preferred for modularity and simple
switching algorithm, while the latter for higher levels with less components [4].
In [5], the different topologies for symmetrical and asymmetrical sources are
analyzed and their effectiveness is discussed by comparing their performance param-
eter values such as THD, number of devices, compound count per level, total standing
voltage, and efficiency. The author [6] suggested the circuit of a 9-level symmetrical
inverter constructed by using 16 power semiconductor switches and 4 sources, but
it has demerits like large number of devices, high THD, and other power quality
issues. The MLI such as 5-level, 17-level symmetrical and 17-level asymmetrical
has been proposed [7], while 17 level asymmetrical is designed by 10 switches,
2 diodes, 2 capacitors, and 2 sources. In [8], the 9-level symmetrical and 17-level
asymmetrical inverters are incorporated by 6 unidirectional switches, 01 bidirec-
tional switch, 02 capacitors, and 02 sources. But the inclusion of a capacitor creates
voltage-balancing issues during switching operations at higher levels. To overcome
these demerits, the researcher [9] introduced the 15-level topology consisting of 8
switches and 3 sources. In addition to that, the DC source is replaced by solar photo
voltaic cells and a DC-DC converter. The paper [10] presented the 15-level inverter
by 10 switches and 3 sources, and also analyzed the harmonic distortion values for
different pulse width modulation techniques. In [11], the 11-level inverter is formed
by 10 switches, 2 capacitor, and one DC source. In [12], the step-up 13-level switched
capacitor is formed by 13 switches, one diode, 3 capacitor, and one source. Another
paper [13] introduced generalized inverter, in which 13-level modules were generated
by 8 unidirectional switches, 2 bidirectional switches, 2 capacitors, and 2 sources.
Based on the literature survey, this paper proposes a novel topology which is
capable of extending as a generalized circuit to produce the waveform for higher
levels. It has also become a fault-tolerant circuit for failure of specific switches and
sources. The current flow path for 9-level symmetrical and 21-level asymmetrical
topology is discussed, and its switching states are tabulated in Section II. Section III
derives the mathematical equation for extended generalized topology; furthermore,
Section IV displays the simulation results and Section V discusses the conclusion.
A Generalized Symmetrical and Asymmetrical Multilevel Inverter … 125
Fig. 1 Basic unit of proposed circuit diagram
2 Proposed MLI Topology
2.1 Generalized Topology Configuration
The circuit diagram of the proposed topology is shown in Fig. 1. It consists of 6

switches in the outer part and 2 switches, 2 DC sources, and 2 diodes in the inner
part of the topology.
The inner part of the topology is called module, which can be extended in series to
modify the circuit as a generalized category that is suitable for higher levels. Figure 2
presents the topology with two modules connected in series. The two module H-
shaped topology consists of 10 switches, two diodes, and four sources. In the same
way, the number of modules in the middle part of configuration can be increased in
series to increase the levels; then it produces higher quality of waveform similar to
a sinusoidal signal.
The generalized equation is derived for symmetrical and asymmetrical cases. In
symmetrical topology, all the voltage sources are equal (V 1 = V 2 = V 3 …V n ). For
M number of levels (M = 5,9,13…),
M + 11
The number of switches = (1)
2
M −1
The number of DC sources = (2)
2
(a) (b)
Fig. 2 Generalized topology: a two-module circuit, b n-module topology
M −1
The number of diodes = (3)
2
M + 11
The number of gate driving circuits = (4)
2
In asymmetrical cases, the voltage sources are selected in the ratio as 1:2:3:4.
Then the generalized equation is derived on the basis of the number of modules (1,
2, 3 … n)
The number of switches = 2n + 6 (5)
The number of DC sources = = 2n (6)
The number of Diodes = = 2n (7)
The number of gate driving circuits = 2n + 6 (8)
The number of voltage levels is derived based on mathematical conditions

= 7, if n = 1 (9)
= (Number of levels)n=n−1 + (8n − 2)if n > 1
9-level Symmetrical and 21-Level Asymmetrical MLI

The two-module generalized MLI is considered for analysis purposes. It consists
of 10 switches, 2 sources, and 2 diodes. Based on the generalized equation, it is
Fig. 3 Current flow path: a 2 V mode; b V mode; c 4 V mode; d 3 V mode
able to generate 9 level and 21 level under symmetrical and asymmetrical sources
respectively. The current flow path through the proposed topology for symmetrical
source is shown in Figs. 3 and 4.
For V voltage level, the one source is connected to the load through the current
path V-S 1 -L-S 6 -S 4 -S 2 -D3 -S 1 -V. Similarly, for 2 V voltage level, two voltage sources
are connected through the switches to the load (V-S 1 -L-S 6 -S 4 -S 2 -S 3 -V-S 1 -V ). Then
the current flow path for other voltage levels is shown in Fig. 4. Based on the analysis,
the switching signals are provided for both symmetrical and asymmetrical topologies
in Tables 1 and 2, respectively.
Figure 5 shows the current flow path for different levels under the asymmetrical
mode. The 4 V voltage level is achieved by connecting the V 3 source across the
load through the current path V 1 -S 1 -L-S 6 -S 4 -V 3 -V 1 . Similarly, 6 V voltage level is
connected through the load by the path (V 1 -S 1 -L-S 5 -V 2 -D4 -S 4 -V 3 -V 1 ).
Comparison Analysis.
The comparative analysis of the proposed MLI topology with recently introduced
circuit to prove its novelty configuration. The component count per level is the
Fig. 4 Current flow path: a −V mode; b −2 V mode; c −3 V mode; d −4 V mode
Table 1 Switching states for 9-level symmetrical topology

Levels Switches
S1 S2 S3 S4 S5 S6 S7 S8 S9 S 10
+4 V 1 0 0 1 1 0 1 1 1 1
+3 V 1 0 0 1 1 0 1 1 1 0
+2 V 1 0 0 1 0 1 1 0 0 0
+V 1 0 0 1 0 1 1 0 0 0
0 1 0 1 0 1 0 0 0 0 0
−V 0 1 1 0 1 0 1 0 0 0
−2 V 0 1 1 0 1 0 1 0 1 0
−3 V 0 1 1 0 0 1 1 1 1 0
−4 V 0 1 1 0 0 1 1 1 1 0
Table 2 Switching states for 21-level asymmetrical topology

Levels Switches
S1 S2 S3 S4 S5 S6 S7 S8 S9 S 10
+10 V 1 0 0 1 1 0 1 1 1 1
+9 V 1 0 0 1 1 0 0 1 1 1
+8 V 1 0 0 1 1 0 1 0 1 1
+7 V 1 0 0 1 1 0 0 0 1 1
+6 V 1 0 0 1 1 0 0 1 0 1
+5 V 1 0 0 1 1 0 1 0 0 1
+4 V 0 1 0 1 1 0 0 0 0 1
+3 V 1 0 0 1 0 1 0 0 1 0
+2 V 0 1 0 1 1 0 0 1 0 0
+V 1 0 0 1 0 1 1 0 0 0
0 0 1 0 1 0 1 0 0 0 0
−V 0 1 1 0 1 0 1 0 0 0
−2 V 1 0 1 0 0 1 0 1 0 0
−3 V 0 1 1 0 1 0 0 0 1 0
−4 V 1 0 1 0 0 1 0 0 0 1
−5 V 0 1 1 0 0 1 1 0 0 1
−6 V 0 1 1 0 0 1 0 1 0 1
−7 V 0 1 1 0 0 1 0 0 1 1
−8 V 0 1 1 0 0 1 1 0 1 1
−9 V 0 1 1 0 0 1 0 1 1 1
−10 V 0 1 1 0 0 1 1 1 1 1
generalized critical parameter used to compare its effectiveness. So, the mathematical
equation is
N SW + N S + N D + NC
ComponentCountperLevel(CCpL) = (10)
L
N sw —number of switches
N s —number of sources
N D —number of diodes
N c —number of capacitors.
Table 3 shows the proposed topology has the least components compared to other
research papers; therefore, its size, cost, and complexity are reduced.
Fig. 5 Current flow path: a V mode; b 4 V mode; c 6 V mode; d 10 V mode; e −6 V mode; f −

4 V mode
Table 3 Comparison of proposed topology with other configurations

Parameters [13] [12] [11] [10] [9] [8] [7] [6] Proposed
Level 13 11 13 11 15 15 17 17 21
No. of 11 9 14 10 9 10 14 10 10
switches
No. of 0 0 0 0 0 0 0 2 2
diodes
No. of 2 1 1 1 3 3 4 3 4
sources
No. of 2 2 3 2 0 0 4 0 0
capacitors
Total no. of 15 12 18 13 12 13 22 15 16
component
CCpL 1.153 1.09 1.385 1.18 0.792 0.866 1.294 0.882 0.761
The two-module generalized topology is considered for simulation purpose. It

consists of 10 unidirectional switches, four sources, and two diodes. The performance
of topology is verified by MATLAB/Simulink in both symmetrical and asymmetrical
cases. In symmetrical MLI, the voltage sources are equal (V1 , V2 , V3 and V4 are
10 V). The nine-level staircase sinusoidal waveform is generated with the help of
symmetrical sources. The circuit is tested under resistive and inductive loads (R =
20 Ω and L = 10 mH) to prove its topology suitable for electric drive applications.
The 9-level voltage and current waveforms are shown in Figs. 6 and 7.
In asymmetrical MLI, the voltage sources are selected in the ratio of 1:2:3:4 (V1
= 10 V, V2 = 20 V, V3 = 30 V, V4 = 40 V). The 21-level staircase output is produced
with the help of asymmetrical sources. The corresponding waveform is depicted in
Figs. 8 and 9. The control signals for the switches are generated by the Nearest
Level Control (NLC) algorithm technique as per the switching table. As per the FFT
Fig. 6 9-level MLI: a voltage waveform for R = 20 Ω; b current waveform for R = 20 Ω

Fig. 7 a Current waveform of 9-level MLI for R = 20 Ω and L = 10mH; b FFT analysis for 9-level
MLI
analysis, the Total Harmonic Distortion (THD) for 9-level voltage output has 9.35%
while 21-level output has 3.90%.
In the above discussion, the THD is reduced drastically due to increase in levels
under the asymmetrical case and satisfy IEEE 519 standards, therefore the quality
of waveform is improved. Then the filter is not needed which leads to reduction in
size and decrease in cost.
Fig. 8 21-level MLI: a voltage waveform for R = 20 Ω; b current waveform for R = 20 Ω
Fig. 9 a Current waveform of 21-level MLI for R = 20 Ω and L = 10mH; b FFT analysis for
21-level MLI
4 Conclusion
A compact generalized multilevel inverter topology has been proposed in this paper.
The effectiveness has been proved by simulating two-module 9-level symmetrical
and 21-level asymmetrical MLI in the MATLAB/Simulink environment. The gener-
alized equations are derived to calculate the number of switches, sources, diodes,
and levels for extended module MLI. The THD analysis of voltage waveform for
9-level MLI and 21-level MLI are simulated. By comparing the number of switching
devices, sources, capacitors, and CCpL with recently introduced topologies to prove
its superiority. Based on the analysis, it perfectly fits renewable energy and electrical
drive applications.
References
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In: 4th International Conference on Energy, Power and Environment (ICEPE). IEEE
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motor drive. In: 4th international conference on Recent Development in Control, Automation
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with reduced components. IEEE Access 9:746–760
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inverter with reduced components for solar PV applications. IEEE Access 9:581–595
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reduced switch count using different PWM techniques. In: 2017 international conference on
frontiers of information technology. IEEE, pp 333–339
10. Ali M, Chakrabortty RK (2021) 11-level operation with voltage-balance control of WE-type
inverter using conventional and DE-SHE techniques. IEEE Access 9:317–428
11. Kim K-M, Han J-K, Moon G-W (2021) A high step-up switched-capacitor 13-level inverter
with reduced number of switches. IEEE Trans Power Electron 36:2505–2510
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asymmetrical inverter with hybrid PWM scheme. IEEE Trans. Ind. Electron 69:817–830
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for multilevel inverters. IEEE Trans. Ind. Electron 66:5186–5200
Comprehensive Analyses of Control
Techniques in Dual Active Bridge
DC–DC Converter for G2V Operations
Sudipta Baidya and Akanksha Shukla
Abstract Power conversion via high-frequency link (HFL) using DC–DC

converters is gaining gradual popularity in Electric Vehicles (EVs) and the power
sector due to their high power density, lightweight, cost-effectiveness, and relia-
bility without conciliatory efficiency. One such promising DC–DC converter that
combines bidirectional ability with energy storage and isolation is the dual active
bridge (DAB). This paper presents the outcome of various control methodologies on
the peak inductor current, primary and secondary side voltage of the HF transformer,
and output power of a DAB converter. This converter regulates power flow in both
directions by employing phase shift techniques. The traditional control techniques
can be categorized as single-phase shift (SPS), dual-phase shift (DPS), and triple-
phase shift (TPS). Closed-loop controlling and simulation results for all three control
techniques are presented here along with a comparative analysis. It is observed that
with an increase in the degree of freedom of control, both peak inductor current
and switching stress reduce. As the degree of control increases, so does the overall
performance of the DAB converter.
Keywords DC–DC converters · Bidirectional · Dual active bridge · Control

techniques · Efficiency · Power conversion · Single-phase shift · Dual-phase shift ·
Triple-phase shift
1 Introduction
Transportation is essential in today’s world for connecting people from one location
to another. As a result, vehicles are needed to assist with daily transportation. On the
other hand, internal combustion engine (ICE) vehicles are the main sources of air
S. Baidya (B) · A. Shukla

Department of Electrical Engineering, SVNIT, Surat 395007, India
A. Shukla
136 S. Baidya and A. Shukla
pollution. Electric vehicles are becoming more and more popular with customers,
researchers, and engineers as a solution to the growing environmental problems and
over-dependence on crude oil as a replacement for a transportation system based on
petroleum, automobile firms are now concentrating on creating electric automotive
infrastructure [1]. Further, with the increased penetration of renewables like solar
and wind of which solar is the prominent one, the requirement of DC–DC power
electronic converters is also increasing. Isolated and non-isolated converters with a
wide range of uses in renewable energy generation systems are currently available.
However, when it comes to performance and efficiency, isolated DC–DC converters
outperform non-isolated converters. Other advantages include galvanic isolation, a
high conversion ratio, energy storage ability, and circuit protection. The bidirectional
nature of such converters validates their use in DC microgrids [2], electric vehicles
[3], battery charging and discharging, aircraft [4], UPS, photovoltaic systems [5],
and other applications. The DAB converter is the most used isolated bidirectional
DC topology to interface EV and fuel-cell applications [6].
DAB is a bidirectional DC–DC converter that was first described by De. Doncker
in 1988 [7]. A typical dual active bridge consists of an HF transformer and H-
bridges on both the high-voltage (primary) and low-voltage (secondary) sides of the
transformer. All power switch generally considers a duty ratio of 0.5 and has the
capability to produce two square voltages, both on the primary and secondary sides.
The transformer keeps the two H-bridges separate and makes sure that their voltages
remain the same. The instantaneous energy storage element is the transformer’s
leakage inductance. Power flow can be possible in both directions. and the side can
be considered as the primary or secondary one [8]. The HF transformer used in a
dual active bridge contributes to the converter’s small size in applications such as
those proposed in [9].
A dual active bridge is suitable for energy storage systems, EVs, and renewable
integration to the grid due to the advantages of energy storage capability, isolation,
bidirectional power transfer, high power density, and the easy soft-switching execu-
tion without the use of extra passive components [10]. The control mechanisms used
here range from basic to complicated. Three different control types are available, i.e.
single-phase shift, dual-phase shift, and triple-phase shift. SPS provides the simplest
control mechanism of the three methods, having just one degree of freedom [11].
SPS control has become quite popular as a result of its advantages, such as high
dynamic response, low inertia, and simplicity of implementation of soft-switching
control [12]. When the primary and secondary voltages are the same, the converter is
capable of achieving high efficiency [13]. DPS modulation with D1 and D2 has two
degrees of freedom. It has various advantages in terms of Zero Voltage Switching
(ZVS) range, circulating reactive power drop, and increased efficiency, particularly
at light loads [14, 15]. Additionally, it is observed that reducing reactive power can
increase the DAB converter’s efficiency even more, which inspired the development
of the TPS control method. With this strategy, each of the three degrees of freedom
D1 , D2 , and D3 can individually regulate the three degrees of freedom. It is the most
complex method of controlling a dual active bridge converter. The primary goal is
to minimize reactive power as well as transformer current since we must develop
Comprehensive Analyses of Control Techniques in Dual Active Bridge … 137
the power equations. The performance seen here is superior to both SPS and DPS
control; however, TPS control implementation is exceedingly difficult [16, 17].
The literature presents different techniques to select the optimum phase shift for all
the aforementioned control methodologies. The Lagrange Multiplier Method (LMM)
is used to find the best value for the phase shifts in the DPS technique. The phase shift
optimal values of D1 , D2, and D3 are obtained using the Karush–Kuhn–Tucker (KKT)
method [18]. Transformer voltage and its harmonic components are analyzed by
Generalized Average Modeling (GAM) for a DAB converter [19]. Many researchers
have also established the inductor current and phase shift equations for the reduction
of reactive power. However, the researchers have attempted to determine the optimal
phase shift values for different objectives like minimization of reactive power and
the leakage inductor current. However, there is still the requirement to establish a
general method for determining the phase shifts as per the desired objective. The
objectives of the study carried out are detailed below
• Description of single-phase shift, dual-phase, and triple-phase shift techniques
with efficient closed-loop control to find the optimum phase shifts.
• Development of closed-loop control methodology with an objective to achieve
constant-voltage charging.
• Comparative analysis of the three techniques to better comprehend their benefits
and drawbacks.
The closed-loop control employs a proportional–integral (PI) controller to achieve
optimum phase shifts for all three techniques. The controller also ensures to obtain
reduced switching stress, peak inductor current, and ripples in the output voltage
of the converter. Dynamic simulations are carried out to demonstrate the efficacy
of the developed control mechanism. The paper is structured as follows: In Sect. 2,
the basic principle of the DAB converter is described followed by the description of
the control methodology in Sect. 3. In Sect. 4, closed-loop operation is discussed.
Results and discussions for three control techniques are presented in Sects. 5 and 6
concludes the work.
2 DAB Converter
DAB converter is shown in Fig. 1a. It consists of two H-bridge circuits (H bridge-1
and H bridge-2), a filter inductor, and an HF transformer. Both H-bridges comprise
four self-commutating power semiconductor switches (IGBTs/MOSFETs). The filter
inductor reflects the input side transformer equivalent leakage inductance. This
element L is important for power transfer through the converter. Other advantages
of this converter include a high-voltage transfer ratio, galvanic isolation, high power
density, and high efficiency.
The first DC input (V in ) is applied to H-Bridge-1 of the DAB converter, which
converts it into square-waveform with high conversion voltage ratio V ab by switching
the switches (S 1 , S 4 ) for half of the switching cycle (T s ) and the other switches (S 2 ,
Fig. 1 DAB converter a topology and b equivalent power system analogy
S 3 ) for the other half. Through HFT and the filter inductor, this voltage V ab is shifted
to the secondary side of the H-bridge. Galvanic isolation is a feature a of single-phase
high-frequency transformers. The voltage is scaled at a turn ratio of N:1 and voltage
gain (d) is defined as NV 2 /V 1 . The required DC supply is provided by H-bridge-2
on the secondary side [20]. The active power is controlled by varying the D3 value
of two H-bridges. Reactive power is controlled by changing the values of D1 and D2
between the H 1 Bridge and the H2 Bridge. So, the DAB converter can be controlled in
three different ways. Equation (1) provides the inductor voltage at various switching
instants. Table 1 presents a generalized equation for the inductor voltage for these
different switching instants. This table helps understand how the inductor voltage
changes at specific points in time, aiding in the analysis and design of the circuit.
Vlm = Vpri − Vsec , = Vab − Vcd , (1)
where Vsec , denotes the secondary voltage on the primary side.

The relationship between input and output voltage at boundary condition (V 1 =
NV 2 ) is given by
Table 1 DAB switching sequence

Mode Interval Active switches Inductor current waveform Governing equation
V1 +N V2
Mode I [t 0 , t 1 ] S 1 , S 4 and S 6 , S 7 Both positive and negative di
dt = L lk
V1 −N V2
Mode II [t 1 , t 2 ] S 1 , S 4 and S 5 , S 8 Positive di
dt = L lk
Mode III [t 2 , t 3 ] S 2 , S 3 and S 5 , S 8 Both positive and negative di

dt = − V1 +N
L lk
V2
Mode IV [t 3 , t 4 ] S 2 , S 3 and S 6 , S 7 Negative di

dt = − V1 −N
L lk
V2
V1 (1 − 2D)
V2 = (2)
N
The most important parameter choice of leakage inductor is given by Eq. 3
N V1 V2 φ(π − φ)
L lk = (3)
2π 2 f s P0
The required phase shift to transfer power is given by

( / )
π 8 × f s × L lk × P0
φ = × 1− 1− (4)
2 N × V1 × V2
The value of capacitance to maintain the voltage ripple within the desired range
by Eq. 5.
( )
dV2 V1 φ V2
C = φ 1− − (5)
dt XL π R
3 Control Strategies
3.1 SPS Control
The most popular DAB control mechanism is SPS control. The associated switches
S 1 –S 4 and S 5 –S 8 produce square-wave gate signals with a duty ratio of 50%. Full-
bridges H1 and H2 have a corresponding alternating voltage of V ab and V cd , corre-
spondingly, while the current through inductor L is iL . Only one phase-shift ratio
(ϕ or D3 ) is controlled here. The inductor voltage can be changed by modifying the
ϕ value between V ab and V cd . The phase shift ratio ϕ can easily control the power
flow’s direction and its amplitude, where the +ve value of ϕ indicates the charging
of the battery and −ve value of ϕ is for discharging of the battery [21]. The complete
voltage and current waveforms are shown in Fig. 2. When the voltage magnitude of
Fig. 2 Inductor current (iL ),

primary voltage (V pri ),
secondary voltage (V sec ),
and waveform in SPS control
the primary side and secondary sides is mismatched, both the peak and RMS inductor
current rise [17]. Furthermore, in this case, the converter cannot work within ZVS
range. Therefore, the power loss rises intensely, and efficiency decreases [22].
The output power is expressed as
N V1 V2 D(1 − D)
P0(SPS) = (6)
2 f s L lk
3.2 DPS Control
This control algorithm has two phase shifts, i.e. an identical phase shift between half-
bridge (D1 or D2 ) and phase shift between the primary and secondary sides of the
HF transformer (D3 ). This provides the flexibility of using two control parameters to
control the state variables, which was not possible in SPS. To minimize the circulating
current in addition to D3 , another degree of freedom is present. There are two possible
approaches: one is to control D1 or D2 based on the voltage gain, and another option
is to control both D1 and D2 but with an imposed condition that is D1 = D2 . This
phase shift value is defined by D1 and D2 ranges varying from 0 to 1. The dual-phase
shift control can be converted to single-phase shift control by simply changing the
value of D1 = D2 = 1and output power can be obtained.

primary voltage (V pri ),
secondary voltage (V sec ),
waveform in DPS control
As shown in Fig. 3, the switching loss is reduced when the zero voltage is matched
or three levels of voltage (+V 1 , 0 and −V 1 ) reach the high-voltage side compared to
the SPS mode. The only source of the output fluctuations in the DAB converter may
be reactive power. DC-link capacitor is necessary to withstand these fluctuations.
The losses in a transformer directly change with the square of the inductor current
RMS value [15].
The output power is expressed as (0 < D1 < D2 < 1)
N V1 V2 D2 (1 − D2 − 0.5D12 )
P0(DPS) = (7)
2 f s L lk
3.3 TPS Control
Circulating current (or reactive power) is a major concern for dual active bridge
converters. In DPS control, D1 = D2 = 1 and D3 is controlled to achieve the desired
output voltage. Over a period of time, iL approaches a negative value. Inductor current
contributes to reactive power or reverse power in a dual active bridge converter, and
iL must maintain its position in the positive cycle. In the case of triple-phase shift,
each variable D1 , D2 , and D3 is controlled independently. TPS control is capable
of eliminating reactive power to a degree. It is extremely challenging to control all
three variables in this situation. These variables must be selected so that the power
factor is maximized and the inductor current is minimized. As shown in Fig. 4, both
the primary and secondary side voltage has three levels of voltage (+V 1 , 0 and −V 1 )
along with some phase shifts in terms of D1 , D2 , and D3 . The optimal values of D1 ,
D2 , and D3 are obtained by minimizing the amplitude of the fundamental component
of current through the inductor iL [23], or minimizing fundamental reactive power.
TPS control allows for full soft switching across the entire load range while reducing
peak current through an inductor. At low loads, this modulation scheme also results
in the minimum amount of copper and conduction losses, thus the converter achieves
high efficiency.
The output power is given as
N V1 V2 2
P0(TPS) = (D − D1 D2 + 2D1 − 2D1 D3 ) (8)
4 f s L lk 1

primary voltage (V pri ), and
secondary voltage (V sec )
waveform in TPS control
Fig. 5 Closed-loop control strategy of DAB
4 Closed-Loop Control
The dual active bridge converter working in charging mode is shown in Fig. 5. In
closed-loop operation, the output voltage V 2 is controlled in constant voltage (CV)
mode by generating the switching pulse. The load voltage V 2 is maintained at a fixed
value using a proportional–integral (PI) controller. Df is regarded as the main control
parameter, which is the phase difference between the fundamental components of
Vab and Vcd. The fundamental phase shift Df = D3 + D2 /2 – D1 /2 and phase-
shifted delay is generated for the SPS, DPS, and TPS techniques. Df is also used
to determine which switching mode is used [24]. The optimized modulation outline
is used to calculate the inner degree of freedom D1 and D2 . The inner duty ratio
calculation is accomplished in the simplest form by regulating D1 and D2 to achieve
optimal values by slow control loops.
Each switch has a duty ratio of 0.5. In the case of the SPS technique, the phase shift
D1 = D2 = 1 is considered, and only D3 is varied to generate pulses for secondary
side switches. In the DPS technique, two phase shifts (D1 or D2 and D3 ) are generated
to give the switching pulses to switch S 5 and S 8 .
The simulation of a dual active bridge is performed on a resistive load and is simu-
lated by using MATLAB/Simulink R2016a on a computer with 4 GB RAM and
Intel i3 processor. The proper calculation of output resistance, output capacitance,
input voltage, output voltage, and inductor values are taken into consideration. The
MATLAB Simulink program provides the output voltage, inductor current, inductor
voltage, and transformer’s primary and secondary voltage waveforms. DAB key
system parameters are provided in Table 2.
Table 2 DAB key system

Parameter Index Ratings
parameters
Input voltage V1 96 V
Output voltage V2 48 V
Total leakage inductance L lk 50 μH
Output power rating Po 500 W
Switching frequency fs 20 kHz
Turns ratio N 1:1
Output current I0 10 A
Load resistance R 4.8 Ω
Output voltage ripple Δ V <5%
Fig. 6 Primary and secondary voltage of transformer in SPS control
5.1 SPS Control
Figure 6 represents the primary voltage and secondary voltage across the transformer,
where the primary leads the secondary by a phase shift of ϕ = 53o . The voltage rapidly
changes from V 1 to −V 1 on the primary side and vice versa on the secondary side.
The current through inductor, voltage across inductor, and the output voltage are
shown in Figs. 7, 8, and 9 respectively in SPS control.
5.2 DPS Control
In the DPS control of a DAB converter, there are two degrees of freedom when either
D1 or D2 is present, along with D3 . A closed-loop control scheme is applied for both
D1 and D2 as shown in Fig. 5. The high-frequency transformer’s primary side has
three voltage levels with a voltage range of +V 1 to 0 to −V 1 as shown in Fig. 10.
Fig. 7 Current through inductor in SPS control
Fig. 8 Voltage across inductor in SPS control
The current through the inductor, voltage across the inductor, and the output voltage
are shown in Figs. 11, 12, and 13 respectively in the DPS control charging mode.
Fig. 9 Output voltage in SPS control

Fig. 10 Primary and secondary voltage of transformer in DPS control
Fig. 11 Inductor current in DPS control
Fig. 12 Inductor voltage in DPS control

Fig. 13 Output voltage in DPS control
5.3 TPS Control
In triple-phase shift control of the DAB converter, there are three phase shift param-
eters: D1 , D2 , and D3 . A closed-loop control scheme is applied to D1 , D2 , and D3
shown in Fig. 5. Both the primary and secondary sides of the high-frequency trans-
former have three voltage levels with a voltage range of +V 1 to 0 to −V 1 as shown
in Fig. 14. The current through the inductor, voltage across inductor, and the output
voltage are shown in Figs. 15, 16, and 17 respectively in the TPS control charging
mode.
In case of SPS control from Fig. 6, it is observed that the voltage rapidly changes
from V 1 to −V 1 on the high-voltage side and vice versa on the low voltage side of the
transformer; in DPS only the primary voltage archives zero voltage level, i.e. a voltage
range of +V 1 to 0 to −V 1 as shown in Fig. 10, while in TPS control both sides have
a voltage range of +V 1 to 0 to −V 1 as shown in Fig. 14. From this transformer’s
waveform, it is clear that SPS control has not occurred at zero voltage level. The
switching losses caused by this will reduce efficiency. In DPS, only the primary side
Fig. 14 Primary and secondary voltage of transformer in TPS control

Fig. 15 Inductor current in TPS control
Fig. 16 Inductor voltage in TPS control
Fig. 17 Output voltage in TPS control

Table 3 Comparison of SPS, DPS, and TPS techniques

S. No. Technique Stress across switch S 1 Transformer’s square Peak inductor current
(VA) voltage level
1. SPS 185.4 V 1 to −V 1 on the primary 25.10 A
and secondary sides
2. DPS 176.9 +V 1 to 0 to −V 1 on only 20.93 A
Primary side
3. TPS 170.6 +V 1 to 0 to −V 1 on both
the primary and
secondary sides
voltage has zero level so only the secondary side switches suffer additional switching
loss. In TPS, both the primary and secondary side voltage have zero level; this reduces
the overall switching loss. Also at zero voltage level of the transformer, in switches
zero voltage switching (ZVS) has occurred.
Also, from Figs. 8, 12 to 16, it is observed that in SPS inductor voltage has two
voltage levels. In DPS, inductor voltage waveform has six different voltage levels,
and in TPS inductor voltage has four different voltage levels. It indicates that in DPS
control voltage level changes frequently with the inductor current slope.
From Figs. 7, 11 to Fig. 15 it has been discovered that the peak inductor current
reduces from 25.10 A in SPS control to 20.93 A in DPS control and reduces to
18.92 A in TPS control. By increasing the complexity of controlling and handling
more duty ratio, the inductor current waveform is getting smoother and the peak
value is reduced. Because this is going to the input of the transformer, lowering
the current will result in lower transformer losses. Furthermore, the TPS technique
reduces switching stress and peak inductor current as shown in Table 3. DPS and TPS
techniques have 4.58 and 7.98% less switch stress as compared to the SPS technique.
It is clear that the TPS and DPS controls outperform the SPS control. From Figs. 9,
13 to 17 it is observed in output voltage that SPS has more settling time and its value
gradually decreases toward DPS and TPS. Hence, it concludes that TPS has faster
control in output voltage.
6 Conclusion
This paper presents a comparison in terms of transformer voltage, peak inductor

current, and switching losses between three control techniques for a DAB converter.
The proposed analysis’s results can be summarized as follows:
• When D1 = D2 = 0, the DPS and TPS control behave similar to SPS control.
• In the SPS technique, due to only one control parameter the switching losses
caused by this reduce efficiency. In DPS control, it produces less reactive power
because it only has two degrees of freedom. The TPS control has the least reactive
power of the three control strategies with three control parameters, which reduces
switch stress and inductor current.
• In TPS due to zero voltage level at the primary and secondary levels, this reduces
the overall switching loss.
• In DPS and TPS, the inductor current waveform is getting smoother and the peak
value is reduced, so the decrease in current will also result in decreased transformer
losses.
• The TPS is a control strategy that enables minimum reactive power and increased
efficiency across the entire operating range of output power. Alternatively, it is a
more complicated technique.
Hence, DPS and TPS control enhance DAB converter performance. In the future,
the elimination of PI controller will be attempted to increase the response time of the
converter. Further, DAB converter with both grid to vehicle (G2V) and vehicle to grid
(V2G) capability for fast charging and discharging applications will be developed.
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DBSCAN-Based Cascaded Inductively
Coupled DSTATCOM for PQ
Improvement
Praveen Kumar Yadav Kundala, Mrutyunjaya Mangaraj,

Suresh Kumar Sudabattula, Jogeswara Sabat, and Rohan Thakur
Abstract This study clarifies the feasibility of implementing a machine learning

(ML)-oriented cascaded inductively coupled distributed static compensator for power
quality (PQ) enhancement. The issues involved in declining the power quality (PQ)
using a cascaded direct coupled static compensator (CDC-DSTATCOM) were iden-
tified as a hazardous disappointment. Hence, to improve the quality, the coupling
transformer is served in unification with CDC-DSTATCOM. Also, the recent growth
of machine learning (ML) systems and the progression of computational resources,
with unpredicted data obtainability, have inspired the researchers. In this study,
density-based spatial clustering of application with noise (DBSCAN) is employed by
using its own learning mechanism (LM) using MATLAB/Simulink. This controller
is composed of six subnets, with six being used for active tuned weight extraction,
while only three are allocated to the reactive part. Among them, six subnets are
employed for active tuned weight extraction whereas other three subnets are used
for reactive part. Moreover, the above-said devices are triggered with the help of
generated reference supply current. To illustrate how CDC-DSTATCOM and CIC-
DSTATCOM work, we take a close look at a real-world case study. In conclusion,
the CIC-DSTATCOM is enhanced in a more healthful way than others in terms of
reducing harmonics, improving power factor, balancing loads, regulating potential,
etc.
Keyword CDC-DSTATCOM · CIC-DSTATCOM · DBSCAN algorithm · PQ
P. K. Y. Kundala (B) · S. K. Sudabattula

School of Electrical Engineering, LPU, Jalandhar 144001, India
S. K. Sudabattula
M. Mangaraj
Department of EEE, LIET, Vizianagaram 535005, India
J. Sabat
Department of EEE, VITAM, Berhampur 761008, India
R. Thakur
Department of EEE, GH Raisoni University, Amravati, India
154 P. K. Y. Kundala et al.
1 Introduction
The major objective of the Electrical Power Distribution System (EPDS) based on the
present situation is to offer secure, consistent, qualitative, effective, and inexpensive
source to the consumers. As a result, the EPDS must be appropriately planned,
designed, and operated in a safe manner. EPDS is generally prone to a greater quantity
of disturbances during the process [1–3]. Increased electrical power needs, absence of
long-term scheduling, open access to customers, the least level of safety, nonlinear
loads, and unexpected load switching are all contributing factors to deteriorating
supply quality. As a result, power system operators require innovative strategies for
increasing PQ performance [4–6].
The DSTATCOM is a significant choice for current PQ concerns because of
this incentive to improve PQ performance in the EPDS [7–9]. Despite the fact that
DSTATCOM plays an important part in EPDS, as a result, the difficult issue is to
offer suppleness and long-term viability for all of the overhead possibilities. Impor-
tant voltage source inverter (VSI) selection, VSI extension, control process design,
IFCT structure, and impedance match are primary study areas for PQ improvement.
For the past three decades, most academics and R&D firms have worked on
various custom power devices (CPD) to alleviate PQ-related issues [15–18]. All
CPDs vaccinate reactive power at the system’s point of common coupling (PCC) in
a flexible, reliable, and rapid manner. Because the PCC is in close contact with the
source, load, and DSTATCOM in CDC-DSTATCOM, it is subjected to additional
stress. As a result, there are increased opportunities for short-circuit currents to flow,
insufficient protection, and thermal losses, among other things [12].
The cascaded H-bridge inverter is one of the most popular converter topologies
used in high power medium potential range loads. The H-bridges are connected
in cascade to achieve low harmonic distortion. The cascaded H-bridge multi-level
inverter utilizes multiple inverter units connected in a series chain to generate high
AC potentials. Each phase leg comprises two H-bridge units powered by two isolated
DC supplies, typically obtained from a multi-pulse diode rectifier. The number of H-
bridge units in a cascaded inductively coupled DSTATCOM is primarily determined
by the inverter’s operating potential and harmonic requirements.
To solve the shortcomings of CDC-DSTATCOM, a new step must be taken.
As a result, the research direction is encouraged to move forward with a correc-
tive approach based on IFCT. First and foremost, the design of CDC-DSTATCOM
for EPDS is the subject of this paper. Later, with CDC-DSTATCOM, the IFCT is
announced to act as an inductive intermediate among the supply and the load. It has a
variety of advantages, including reduced switching stress, improved PCC balancing
voltage, increased compensation capabilities, and other conceivable combinations.
For three-phase three-wire (3P3W) EPDS, two-level potential source converters are
considered due to the design element of the DSTATCOM [19–21]. Due of its popu-
larity in the literature study, this three-leg VSI topology is widely advocated. The
proposed architecture allows for future flexibility in terms of adding more converters
and loads.
DBSCAN-Based Cascaded Inductively Coupled DSTATCOM for PQ … 155
Traditional high-voltage transmission line monitoring systems focus entirely on

AC measurements via potential transformers (PTs) and CTs, ignoring the DC compo-
nents flowing on transmission lines, and may also cause harmonics to flow in the grid.
Most of data are constantly collected from many sections of the power system. ML is
a powerful mathematical method for analyzing this data and offering useful insights
to system operatives so they may make quick and efficient judgments [22–24].
Power and energy systems are one of the most promising segments, with a massive
quantity of underutilized data. The available datasets can be used to analyze a variety
of power system planning, operation, monitoring, and economics problems. Power
grids are complex nonlinear arrangements, and cutting-edge machine learning tools
can aid in the analysis and modeling of their behavior [10, 11].
Due to a lack of data and computational power in previous decades, machine
learning (ML) did not gain widespread use in the business. Many practical uses
of machine learning in power systems are now possible, thanks to recent advances
in computing technology and the distribution of improved meter infrastructures,
phasor measurement units, and micro-PMU. Load prediction, skillful islanding,
power system irregularity detection, security assessment, optimal power flow (OPF),
fault detection, demand response, customer modeling, improving grid resiliency, and
detecting frequency events are just a few of the ongoing and promising applications
of machine learning [13, 14].
The filtering mechanism of DSTATCOM is carried out utilizing a broader mathe-
matical approach and the DBSCAN algorithm in MATLAB/Simulink for a healthier
functioning [22].
• It is possible to achieve good convergence results.
• This technique’s main attributes are compensatory, enhanced tracking, and
adaptive capabilities.
• The suggested approach enables many PQ problems, such as harmonic drop,
improved potential control, healthy power factor, output load balancing, and lower
DC link voltage, among others.
• It also has flexible harmonics over current protection feature.
• It has the ability to reorganize more parameters for a better algorithm version.
The preceding section covers the case studies literature review. Section 2 delves
into the specifics of circuit configuration and modeling for both CDC-DSTATCOM
and CIC-DSTATCOM. Modeling and design of IFCT are covered in Sect. 3. Section 4
contains the system structure, as well as the DBSCAN method and the MATLAB/
Simulink platform. Section 5 contains the findings of the comparative simulations.
Finally, Sect. 6 summarizes the system’s effectiveness.
Fig. 1 CDC-DSTATCOM
in EPDS
2 Design of the CIC-DSTATCOM
Both the CDC-DSTATCOM and CIC-DSTATCOM structures of the 3P3W EPDS

are shown in Figs. 1 and 2, respectively. The VSI-based DSTATCOM linked at the
point of common coupling (PCC) of EPDS is structured in Fig. 3. DBSCAN is used
to generate the switching signals for the IGBTs in both compensators.
3 Innovations of the Anticipated Topology
There are numerous novelties which are enlightened as follows:

• Response and reaction time: The proposed DSTATCOM possesses better response
and reaction time.
• Component extraction: the proposed method has the capability to extract
demanded time domain component for both harmonics and inter harmonics.
• Reduced computation time: This technique is designed to fit a parallel processing
structure for each time domain component to reduce the computation time.
• Dynamic operation of inverter: AS VSC is operated by the DBSCAN algorithm,
the hysteresis current controller (HCC) processes the analog signal to convert
into digital signals for the generation of the firing pulses for different loading
scenarios.
• Improvement in system effectiveness: The system effectiveness is improved by
reason of less iteration process involved in the DBSCAN algorithm.
• Discount in THD of the source current: The THD of the supply and output load
current are 2.94%, 26.69% correspondingly obtained with CIC-DSTATCOM,
whereas 4.00 and 26.32% correspondingly gained from CDC-DSTATCOM.
Fig. 2 CIC-DSTATCOM in EPDS
Fig. 3 VSI-based
DSTATCOM
4 Designing of Inductive Transformer
In Fig. 2, the intricate winding construction of the proposed CIC-DSTATCOM is

shown. The proposed CIC-STATCOM includes an inductively filtered converting
transformer (IFCT), a DSTATCOM comprising a VSI, and a nonlinear load. The
IFCT structure covers 3 windings over which CDC-DSTATCOM and nonlinear load
are joined. Those are primary winding (PW), secondary side winding (SW), and
filtering winding (FW). The switching signal generation process is structured in
Fig. 4, whereas the internal signal of DBSCAN is shown in Fig. 5. The IFCT is
wound in a unique way so that the grid, the load, and the DSTATCOM all have
balanced potential. So the harmonics are inaccessible from the PW:
⎧
⎨ N1 i ap + N2 i as + N3 i a f = 0
N i + N2 i bs + N3 i b f = 0 (1)
⎩ 1 bp
N1 i cp + N2 i cs + N3 i c f = 0
⎧
⎪
⎪ i ap = (u sa − u apo )/Z line
⎪
⎪
⎪
⎪ i bp = (u sb − u bpo )/Z line
⎪
⎪
⎪
⎪ i cp = (u sc − u cpo )/Z line
⎪
⎪
⎪
⎪ i as = i al + i zal
⎪
⎪
⎪
⎪ i bs = i bl + i zbl
⎪
⎪
⎨
i cs = i cl + i zcl
(2)
⎪
⎪ i ap + i bp + i cp = 0
⎪
⎪
⎪
⎪ i as + i bs + i cs = 0
⎪
⎪
⎪
⎪ ia f + ib f + ic f = 0
⎪
⎪
⎪
⎪ i a f = i c f + i cat = i c f + ira + i za
⎪
⎪
⎪
⎪ i b f = i a f + i cbt = i a f + ir b + i zb
⎪
⎪
⎩
i c f = i b f + i cct = i b f + ir c + i zc
⎧
⎨ u ab f = (i zb − i za )/Z o
u = (i zc − i zb )/Z o (3)
⎩ bc f
u ca f = (i za − i zc )/Z o
⎧
⎪
⎨ u apo −
N1
u
N3 ab f
= i ap z p − N1
i z
N3 a f f
u bpo − N1
u
N3 bc f
= i bp z p − N1
i z
N3 b f f (4)
⎪
⎩u −
cpo
N1
u
N3 ca f
= i cp z p − N1
i z
N3 c f f
4.1 Formulating Demonstration of the DBSCAN by PI

Controller
The whole strategy progression is articulated as follows:
∑
n ∑
n
w pa (n + 1) = w pa (n) + μk ek i La u pa − w pa (n)ξk / w pa (n) (5)
1 1
∑
n ∑
n
w pb (n + 1) = w pb (n) + μk ek i Lb u pb − w pb (n)ξk / w pb (n) (6)
1 1
∑
n ∑
n
w pc (n + 1) = w pc (n) + μk ek i Lc u pc − w pc (n)ξk / w pc (n) (7)
1 1
Fig. 4 Switching signal generation using DBSCAN control algorithm for CIC-DSTATCOM
Fig. 5 Internal signal of the CDC-DSTATCOM

DBSCAN 60 CIC-DSTATCOM
40
i (A)
*
s
20
0
0.55 0.6 0.65 0.7 0.75
Time (Sec)
∑
n ∑
n
wqa (n + 1) = wqa (n) + μk ek i La u qa − wqa (n)ξk / wqa (n) (8)
1 1
∑
n ∑
n
wqb (n + 1) = wqb (n) + μk ek i Lb u qb − wqb (n)ξk / wqb (n) (9)
1 1
∑
n ∑
n
wqc (n + 1) = wqc (n) + μk ek i Lc u qc − wqc (n)ξk / wqc (n) (10)
1 1
4.2 The Median of the Active and Reactive Components’

Weights
The average quantity (w p ) of active weighting measures of a-, b-, and c-phase is
computed as
w pa + w pb + w pc
wp = (11)
3
The average quantity (wq ) of reactive weighting measures of a-, b-, and c-phase
is computed as
wqa + wqb + wqc

wq = (12)
3
4.3 Computation of In-Phase and Quadrature Unit Potential

Template
Following is an approximation of the in-phase unit potential templates

(u pa , u pb , u pc ):
vsa vsb vsc

u pa = , u pb = , u pc = (13)
vt vt vt
Likewise, the quadrature unit potential patterns (u qa , u qb , u qc ) are the relations of

phase potentials shown below
u pb +u pc ⎫
u qa = √
3 ⎪
⎬
3u pa +u pb −u pc
u qb = √ (14)
2 3
−3u pa +u pb −u pc ⎪
⎭
u qc = √
2 3
vt can be expressed as
/
2 +v 2 + v 2 )
2(vsa
vt = sb sc
(15)
3
4.4 Assessment of Active Module of Base Supply Currents
By subtracting the measured DC potential from the known DC potential, we can

calculate the DC potential variance
vde = vdc(ref) − vdc (16)
PI controller’s output
{
wcp = k pa vde + kia vde dt (17)
The total active modules of the reference supply current is
wsp = wap + wcp (18)
4.5 Assessment of Reactive Module of Base Supply Currents
By subtracting the measured AC bus potential from the standard AC potential, we

can obtain the AC potential variation
vte = vt (ref) − vt (19)
PI controller’s output
{
wcq = k pr vte + kir vte dt (20)
The total reactive modules of the reference supply current is
wsq = wrq − wcq (21)
4.6 Assessment of Triggering Arrangement
The instantaneous reference active module of each phase is estimated by
i aa = wsp u pa , i ab = wsp u pb , i ac = wsp u pc (22)

Likewise, the instantaneous reference reactive module of each phase is projected

by
ira = wsq u qa , ir b = wsq u qb , ir c = wsq u qc (23)
Then the reference source currents are

∗ ∗ ∗
i sa = i aa + ira , i sb = i ab + ir b , i sc = i ac + ir c (24)
HCC receives current error signals after comparing real source currents to refer-
ence source currents for each phase. These are fed to T1 − T6 used in the voltage
source converter (VSC).
5 Simulation Results with Discussion
In Table 1 are listed the system parameters.
5.1 Simulation Results of CDC-DSTATCOM
The simulation time in between 0.55S and 0.75S for this Power Distribution System
(PDS) is chosen. For this particular event, time in varying load is maintained all over
the mentioned simulation time, as depicted in Fig. 6a. By considering a-phase supply
voltage and corresponding current, the power factor of the supply side is observed
and shown in Fig. 6b. From Fig. 6c, the source side power factor is to improve and
Table 1 System parameters

Symbol Value
vs 230 V/phase
fs 50 Hz
Rs 0.51 Ω
Ls 2.1 mH
K pr 0.2
K ir 1.1
vdc 605 V
Cdc 2 mF
K pa 0.01
K ia 0.05
Rc 0.25 Ω
Lc 1.5 mH
maintained at p.f 0.97. In Fig. 6e. the THD of the load current is greatly distorted
whose THD is 26.32%, whereas in Fig. 6d source current is significantly improved
with reduced THD value (THD 4%). In addition, this control scheme maintains load
balancing and voltage regulation as shown in Fig. 6a.
Fig. 6 a Simulated (a)

electrical parameters (top to 500
v s(V)
bottom). b Power factor at 0
-500
input side. c Power factor at
100
is(A)
output side. d Source % 0
THD. e Load % THD -100
il(A) 100
0
-100
50
icb(A) i (A)
0
ca
-50
50
0
-50
50
icc(A)
0
-50
v dc(V)
500
0
0.55 0.6 0.65 0.7 0.75
Time (sec)
(b) 400
vsa(V)
Source side power factor
isa(A)
200
-200
-400
0.55 0.6 0.65 0.7 0.75
Time(sec)
(c) 400
vla(V)
ila(A)
Load side power factor
200
-200
-400
0.55 0.6 0.65 0.7 0.75
Time(sec)
Fig. 6 (continued) (d) Fundamental (50Hz) = 53.05 , THD= 4.00%

1.5
Mag (% of Fundamental)
1
0.5
0
0 2 4 6 8 10
Harmonic order
(e) Fundamental (50Hz) = 51.28 , THD= 26.32%
15
10
0
0 2 4 6 8 10
Harmonic order
5.2 Simulation Results of CIC-DSTATCOM
The simulation time in between 0.55S and 0.75S for this Power Distribution System
(PDS) is chosen. For this particular event, time varying load is maintained all over
the mentioned simulation time. By considering a-phase supply voltage and corre-
sponding current, the power factor of the supply side is observed and shown in Fig. 7b.
In this figure, the source side power factor is improved and maintained at p.f 0.99.
Figure 7c shows the power factor at the output side. In Fig. 7e, the THD of the load
current is greatly distorted whose THD is 26.69%, whereas in Fig. 7d source current
is significantly improved with reduced THD value (THD 2.94%). In addition, this
control scheme maintains load balancing and voltage regulation as shown in Fig. 7a.
Because of the 535 V desired and consistent DC link potential, the potential regula-
tion is maintained. Lastly, 319 V is maintained at PCC to meet the potential balancing
requirements.
The comparative effectiveness study of the CDC-DSTATCOM and the CIC-
DSTATCOM is shown in Table 2.
6 Analysis of Different Factors
6.1 KVA Rating

√ vdc If
The VA rating = 3∗ √ ∗ √
2 2
Fig. 7 a Simulated (a)

electrical parameters (top to
500
v s (V)
bottom). b Power factor at 0
input side. c Power factor at -500
is (A) 100
output side. d Source % 0
THD. e Load %THD -100
50
il(A)
0
-50
100
ica(A)
0
-100
50
icb(A)
0
-50
50
v dC(V) i (A)
0
cc
-50
500
0
0.55 0.6 0.65 0.7 0.75
Time (sec)
(b) 400
vsa (V)
Source side power factor
isa (A)
200
-200
-400
0.55 0.6 0.65 0.7 0.75
Time(sec)
(c) 400
vla(V)
300
ila(A)
Load side power factor
200
100
-100
-200
-300
-400
0.55 0.6 0.65 0.7 0.75
Time(sec)
Fig. 7 (continued) (d) Fundamental (50Hz) = 52.27 , THD= 2.94%

1.2
1
0.8
0.6
0.4
0.2
0
0 2 4 6 8 10
Harmonic order
(e) Fundamental (50Hz) = 51.39 , THD= 26.69%

20
15
10
0
0 2 4
Harmonic6order 8 10
Table 2 Performance of DC-DSTATCOM and IC-DSTATCOM

Performance parameter DSTATCOM at PCC
CDC-DSTATCOM CIC-DSTATCOM
i s (A), THD 53.05, 4.00 52.27, 2.94
vs (V), THD 320.4, 2.22 320, 1.41
il (A), THD 51.28, 26.32 51.39, 26.69
Power factor 0.95 0.99
√ 541 12.6
CDC-DSTATCOM’s kVA rating = 3 ∗ √ ∗ √ = 5.856 kVA
2 2
√ 541 10.5
CIC-DSTATCOM’s kVA rating = 3 ∗ √ ∗ √ = 4.919kVA
2 2
6.2 De-rating Factor (DF)

D F = 1 − efficiency
CDC-DSTATCOM’s kVA rating = 5.85 kVA, p f = 0.97

kW rating = 5.85 ∗ 0.97 = 5.67 kW
Losses = 3I 2f ∗ Rc
I f = 12.6 A, Rc = 0.26 Ω
3I 2f ∗ Rc = 3 ∗ 12.62 ∗ 0.26 = 117.20 W
Input = output + losses
= 5670 + 117.20 = 5787.20 W = 5.787 kW
5.67
Efficiency = ∗ 100
5.787
= 97.97%
DF of CDC-DSTATCOM = 1 − 0.97 = 0.03
CDC-DSTATCOM’s kVA rating = 4.919 kVA, p f = 0.99
kW rating = 4.919 ∗ 0.99 = 4.869 kW
I f = 10.6 A, Rc = 0.26 Ω
3I 2f ∗ Rc = 3 ∗ 10.62 ∗ 0.26 = 82.70 W
Input = output + losses
= 4869 + 82.70 = 4951.70 W = 4.95 kW
4.86
Efficiency = ∗ 100 = 98.18%
4.95
DF of CDC-DSTATCOM = 1 − 0.981 = 0.019.

6.3 Harmonic Compensation Ratio (HCR)

THD% after compensation 4.00
For CDC-DSTATCOM = = = 0.151
THD% before compensation 26.32
For CDC-DSTATCOM
THD% after compensation 2.94

HCR = = = 0.1101.
THD% before compensation 26.69
6.4 Distortion Index (DIN)

DIN = THD% (1 − 0.5(THD%))
CDC-DSTATCOM = 4.00 (1 − 0.5(4.00)) = −4
CDC-DSTATCOM = 2.94 (1 − 0.5(2.94)) = −1.38
6.5 Form Factor (FF)

Irms
FF =
Iavg
FF for CDC-DSTATCOM =
π
Irms = 39.14 A Irms = √ Iavg
2 2
39.14
Iavg = 35.23 A qquadFF = = 1.11
35.23
FF for CDC-DSTATCOM =
Irms = 37.65 A Iavg = 33.89 A
37.65
FF = = 1.11.
33.89
6.6 Ripple Factor (RF)

I AC
RF =
I DC
√ /(
(Ir ms )2 − (I DC )2 )
RF = = F F2 − 1
I DC
/( ) /( )
RF for CDC-DSTATCOM = F F2 − 1 = 1.112 − 1 = 0.481
/( ) /( )
RF for CIC-DSTATCOM = F F2 − 1 = 1.112 − 1 = 0.481.
6.7 Harmonic Factor (HF)

Ir(h)
The HF of the h th harmonic, H F h = ms
Ir(1)
ms
39.14
For CDC-DSTATCOM = = 0.737
53.05
37.65
For CIC-DSTATCOM = = 0.721.
52.27
6.8 C-Message Weights

/∑ /∑
∞ (i ) 2 ∞ (i) 2
i=1 (C i I ) i=1 (C i I )
C = /∑ C=
∞ (i ) )2 Irms
i=1 (I
39.142
For CDC-DSTATCOM = = 0.54
53.052
37.652
For CIC-DSTATCOM = = 0.51.
52.272
Refer to Table 3 for a comparative assessment of CDC and CIC DSTATCOM.
Figure 8 represents the bar graph for indexed parameters.
Table 3 Comparative analysis

Sl. Configurations KVA DF HCR DIN FF RF HF C-message
No. rating weight
1 CDC-DSTATCOM 5.856 0.03 0.151 -4 1.11 0.481 0.737 0.54
2 CIC-DSTATCOM 4.919 0.019 0.1101 -1.38 1.11 0.481 0.72 0.51
Fig. 8 Bar graph
5
4
3 C-Message
2 HFweight
RF
FF
1 DIN
HCR
0 DF
kVA rarting
7 Conclusion
This research work focuses on the analysis of 2 different types of techniques, CIC-
DSTATCOM and CDC-DSTATCOM. Firstly, this paper analyzed the motivation
of DSTATCOM with direct coupling; secondly, it analyzed the efficiency of CIC-
DSTATCOM. Finally, the proposed DBSCAN topology could realize more effective
usage in terms of power quality. The crucial features of the proposed topology are
as follows:
• Introducing of IFCT is the reason to improve the output AC potential at the inverter
as compared to other case studies.
• The merits like low potential stress, a lesser amount of switching loss, and greater
efficiency are observed.
• Also load balancing, source current harmonics elimination, voltage regulation,
and pf improvement are obtained as per target value of IEEE and IEC grid code.
References
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DC-link voltage rating for load compensation with non-stiff source. IEEE Trans Power Electron
27(3):1201–1211
2. Raveendra N, Madhusudhan V, Jaya Laxmi A (2020) RFLSA, “control scheme for power
quality disturbances mitigation in DSTATCOM with n-level inverter connected power
systems”. Energy Syst 11:753–778
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shunt active power filter. Energy Syst 8:297–308
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four-leg DSTATCOM based on instantaneous symmetrical components theory. Energy Syst
9:79–111
5. Singh B, Jayaprakash P, Kothari DP, Chandra A, Haddad KA (2014) Comprehensive study of
DSTATCOM configurations. IEEE Trans Ind Inf 10(2):854–870
6. Manoj Kumar MV, Mishra MK, Kumar C (2015) A grid-connected dual voltage source inverter
with power quality improvement features. IEEE Trans Sustain Energy 6(2):482–490
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conditioning. In: 2015 International Conference on Industrial Instrumentation and Control
(ICIC), Pune, pp 1069–1073
8. Xu C, Dai K, Chen X, Kang Y (2016) Unbalanced PCC voltage regulation with positive-
and negative-sequence compensation tactics for MMC-DSTATCOM. IET Power Electron
9(15):2846–2858
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control algorithms. IET Gener Transm Distrib 11(10):2643–2653
10. Ouyang T, Pedrycz W, Pizzi NJ (2021) Rule-based modeling with DBSCAN-based information
granules. IEEE Trans Cybern 51(7):3653–3663
11. lai W, Zhou M, Hu F, Bian K, Song Q (2019) A new DBSCAN parameters determination
method based on improved MVO. IEEE Access 7:104085–104095
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technique for power quality improvement. IET Power Electron 10(4):480–489
13. He X, Jiang Y, Wang B, Ji H, Huang Z (2021) An image reconstruction method of Capacitively
Coupled Electrical Impedance Tomography (CCEIT) based on DBSCAN and image fusion.
IEEE Trans Instrum Meas 70:1–11
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gas insulated switchgear based on genetic algorithm and density-based spatial clustering of
applications with noise. IEEE Sens J 21(2):965–973
15. Mangaraj M, Panda AK (2017) NBP-based icosφ control strategy for DSTATCOM. IET Power
Electron 10(12):1617–1625
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DSTATCOM topology for medium-voltage reactive power compensation. IEEE Trans Power
Electron 33(3):2113–2126
17. Mangaraj M, Panda AK (2018) DSTATCOM deploying CGBP based icos φ neural network
technique for power conditioning. Ain Shams Eng J 9(4):1535–1546
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DSTATCOM for power quality improvement. IET Gener Transm & Distrib 13(3):423–434
19. Mangaraj M, Panda AK (2019) Modelling and simulation of KHLMS algorithm-based
DSTATCOM. IET Power Electron 12(9):2304–2311
20. Mangaraj M, Panda AK, Penthia T, Dash AR (2020) An adaptive LMBP training based control
technique for DSTATCOM. IET Gener Transm Distrib 14(3):516–524
21. Mangaraj M, Sabat J (2021) MVSI and AVSI-supported DSTATCOM for PQ analysis. IETE
J Res. https://doi.org/10.1080/03772063.2021.1920850
22. Li Y, Saha TK, Krause O, Cao Y, Rehtanz C (2013) An inductively active filtering method for
power-quality improvement of distribution networks with nonlinear loads. IEEE Trans Power
Deliv 28(4):2465–2473
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power filter in distribution networks. Int J Electr Power Energy Syst 99:638–649
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series active power filter. IEEE Trans Power Electron 32(5):3490–3498
EV Charger Using Modified DAB
Converter
Payel Show, R. L. Josephine, and Sai Harsha Naidu
Abstract There has been an increase in demand for electric vehicles in recent times,
and this demand is expected to continue. However, the most serious flaw with EVs
will be the time it takes for a battery to be charged by a charger. Therefore, to
mitigate this problem, a DC fast charger (also known as an off-board charger) has
been introduced to the automotive industry to remedy this issue. There is going to
be a great deal of novelty in this project when a 35 KW DC off-board charger is
presented with great functionality. In the following material, one can comprehend
what components must be included to guarantee that the charger is relatively less
expensive with excellent efficiency. The charger consists of three stages: (a) AC/
DC converter (b) DC/DC converter (c) Battery controller. Later in the article, these
stages are explained in more detail. A lithium-ion battery with a predetermined SOC
and nominal voltage is taken into consideration. One can examine how the SOC
and voltage of the battery are raised by looking at a simulink block of the entire
closed-loop charger.
Keywords Vienna rectifier · DAB multiplier · DC off-board charger
1 Introduction
EVs have advantages over conventional vehicles, such as reduced emissions, no

exhaust emissions, and reduced consumption of gasoline, but are challenged by
limited travel range and lack of quick charging facilities. To overcome these difficul-
ties, a 35 Kw level 3 DC charger is suggested in this paper. Below is a block diagram
of the system (Fig. 1 and Table 1).
P. Show · R. L. Josephine (B) · S. H. Naidu

National Institute of Technology, Tiruchirappalli, Tamil Nadu, India
174 P. Show et al.
Fig. 1 Block diagram of EV charger
Table 1 Level specification in dc charging

EV charging Connector Typical Estimated Estimated range User case
level type output charging time per hour for
power (kw) charging
Level 1 J1772 1–1.8 22–40 h 4–11 km Home/backup
Level 2 J1772, 3–22 2 – 13 h 16–120 km Workplace,
Mennekes hotels,
overnight
charging
Level 3 CCS1 30–360 15 min–1.5 h 193–2250+ km Highway
CCS2 depending on services,
charge logistics hubs,
acceptance rate distribution
centers
1.1 Objective
This charger’s primary specialization is its ability to produce 35 Kw as output that

meets the specifications of a 15 Kw charger with higher efficiency. The secondary
voltage of the transformer utilized in the DAB converter also falls as the charger rating
does; as a result, insulation thickness is reduced. However, the DAB Multiplier, a
redesigned DAB converter, has been introduced in this charger. The output voltage
of the transformer’s secondary side will automatically grow due to the multiplier
present at the output side, so the output power. Additionally, if we later examine the
inductor’s expression present in DAB converter, we will discover that it is directly
proportional to the secondary side output voltage. Inductor size, turns, and cost all
reduce when the secondary side voltage drops. The following is the list of additional
charging issues and their fixes (Table 2).
2 Vienna Rectifier
Front-end converters are used for a variety of applications, such as electric vehicle
chargers, telecommunication systems, welding, and motor drives. The Vienna recti-
fier is a bidirectional boost rectifier with advantages such as higher efficiency, higher
EV Charger Using Modified DAB Converter 175
Table 2 Problems with recent charger and solution of those problems

Problems Solution
(a) Because there are a total of 8 switches To decrease the number of MOSFET
when using a typical DAB converter, the switches in DAB converter. In a
price will be higher conventional DAB converter the number of
MOSFET switches is 8 but in a DAB
multiplier the total no. of MOSFET
switches is 6 with more than expected
voltage
(b) One must increase the switching frequency MOSFETs can achieve zero voltage
in order to reduce the size of the switching (ZVS)
transformer, although doing so could result
in an increase in switching losses as well
(c) The harmonic injection by other appliances To make the power-factor unity at grid side
connected to the grid may cause the grid with the help of Vienna rectifier
side power factor to be distorted
(d) Harmonic injection may result in a rise in To make the THD of input current always
the input current’s THD less than 5% with the help of front end
converter
ratio of power to weight, low THD, almost the power factor as unity, and tiny filter
requirement. It is the best choice for high power applications.
2.1 Vienna Rectifier Basic Configuration
This proposes a revolutionary Vienna rectifier (with voltage-oriented controller)EV

charging system architecture that combines voltage-oriented and PI controllers to
improve efficiency and power density (Fig. 2).
Circuit Operation. Six MOSFETs or IGBTs (active semiconductor switches), as
well as six diodes, make up the Vienna rectifier scheme. The three-level Vienna
Fig. 2 Block diagram of Vienna rectifier

176 P. Show et al.
Fig. 3 Mode I: when input current is positive and also MOSFET is OFF
rectifier’s functioning because of current route at one leg in every mode is shown in
the picture below indicated by the red line.
Mode-I. The diode D1 conducts at mode-I while the reference voltage is generally
+ve during one half cycle and also the switches, e.g., IGBTs or MOSFETs, are
generally OFF, and current moves via V a , then L s , Rs , and then D1 , C 1 , as depicted
in Fig. 3.
Mode-II. In mode 2 operation, switches S 1 S 2 conduct and the current is flowing
via V a , then L s , Rs and then S 1 , S 2 as indicated in Fig. 4 while the reference voltage
is +ve during half cycle.
Mode-III. Switches S 1 –S 2 conduct at mode-3 during the negative half cycle of the
reference voltage and they are turned on, causing current to flow through switch S 1
then S 2 , then Rs and L s and then V a as depicted in Fig. 5.
Mode-IV. The current flows via C 2 , D2 then Rs , L s and V a in mode-IV during the
negative half cycle of reference voltage and while MOSFETs are in OFF condition
(Fig. 6).
Fig. 4 Mode II: when input current is positive and also MOSFET is ON
Fig. 5 Mode III: when input current is negative and also MOSFET is ON
Fig. 6 Mode-4: when i/p current is negative and also MOSFET in OFF
2.2 Controlling Method
During high power applications like power required for welding and various charging
stations for electric vehicle, control techniques have been employed in AC/DC
converters in literature.
Hysteresis Current Control Method [1]. The HCC, depicted in the image below,
is implemented separately for each phase in 3-phase, 3-level PWM rectifier systems.
The switching-signal, (si ’), where i denotes the phase, is directly generated by each
current controller. If the difference between phase current, ii , and reference sinusoidal
current, ii *, exceeds the upper hysteresis limit (+h) in case of positive input current,
the power transistor for the associated phase is turned off, resulting in a drop in ii ,
also the transistor turned back on, the phase current rises, and this cycle repeats once
ii hits the lower hysteresis limit −h (Fig. 7).
Voltage-Oriented Control Method [2]. The established control structure has a
significant impact on how AC to DC power converters function. Dual vector current
178 P. Show et al.
Fig. 7 Control block of hysteresis current control
controllers (DVCC) are the foundation of voltage-oriented controller functioning.

The following issue is reduced by voltage-oriented control:
• Ripples in output DC voltage
• Input current total harmonic distortion
• Grid side input power factor.
As depicted in Fig. 8, the suggested technique regulates the charging mechanism
using VOC technology along with the lower order harmonics of current at the grid
side. According to Eqs. (1) and (2), in αβ 0 and dq0 domains,the matrices of Park
and Clark transformation are implemented,
⎡ ⎤ / ⎡ ⎤⎡ ⎤
vsα 1 −√
1
2
−√21 vsa
⎣ vsβ ⎦ = 2 ⎢ ⎥
⎣ 0 23 − 23 ⎦⎣ vsb ⎦ (1)
3 √1 √1 √1
v0 2 2 2
vsc
[ ] [ ][ ]
vd sinθ cosθ vsα
= (2)
vq −cosθ sinθ vsβ
where the source voltages at the domain of ABC are vsa , vsb , and vsc . Source voltages
at the domain of αβ 0 and dq0 are vsα , vsβ , v0 , vd , and vq , and θ is power system’s
operational phase. The three-phase source current, iSabc , is transformed using a similar
strategy, as shown in Fig. 8.
The control variables on the AC side are transformed into the DC signals by
changing the transformation technique. Proportional-integral controllers may readily
eliminate steady-state errors using the methods shown below,
Fig. 8 The voltage-oriented controller’s control architecture using PWM
( ) ( )
vd,ref = K p i Sd,ref − i Sd + K i i Sd,ref − i Sd dt (13)
( ) ( )
vq,ref = K p i Sq,ref − i Sq + K i i Sq,ref − i Sq dt (14)
where
K p , K i : PI controller gains.
i sd , i sq : Input current in the domain of dq0.
i sd,ref , i sq,ref : Reference signals for i sd , i sq
[ ] [ ][ ]
vα,ref sinθ cosθ vd,ref
= (15)
vβ,ref −cosθ sinθ vq,ref
The operation of VR is in a controlled manner, as depicted in Eq. (15), by using

an inverse park-transformation after gathering the reference voltages vd,ref and vq,ref ,
which are being utilized to establish the switching-pulses Sabc . Figure 8 provides a
summary of VOC-operation engaging the total domain-transformation procedure.
Park’s changes and Clarke’s metamorphosis make up the transformation. 3-
phase quantities are transformed into the 2-phase stationary-quantities (α and β)
using Clarke’s conversion. The revolving reference frame is created by transforming
stationary two-phase (α and β) through Park transformation into reference frame of
d and q. Also the spinning reference frame of dq is being transformed into a reference
frame of α and β using inverse Park’s conversion method. Additionally, stationary
reference frame is transformed using inverse Clarke’s transformation method into
3-phase AC system.
180 P. Show et al.
3 DAB Multiplier
3.1 Introduction
DAB converter and voltage multiplier combination provide soft switching charac-
teristics for high efficiency photovoltaic applications.
To confirm the efficiency and benefits of the suggested converter, experimental
results with a 30 KW, 200–350 V simulink diagram are supplied after a thorough
analysis of the operation principle.
3.2 Why DAB Multiplier
The problems related to different converters other than DAB multiplier are given
below:
• Boost converter not suitable for step-up applications due to conduction losses.
• For Coupled inductor-based boost converter, Coupled inductor leakage-
inductance can lead to a voltage spike when power switches are made.
• Switching capacitor-based converters cause significant transient current and
conduction losses.
By modifying the transformer’s turns ratio, isolated converters can more easily
achieve high voltage conversion, similar to DAB converters, where soft switching is
also accomplished to reach high efficiency. (Table 3).
3.3 Operating Principle [3, 4]
The converter’s topology is depicted in Fig. 4.3a, which combines a voltage multiplier
[5] with a DAB converter. Here, (C a1 /C a2 ) and (S 5 /S 6 ) serve as the internal doublers,
and (D7 /D8 ) and (C o1 /C o2 ) are built as the output voltage-doublers.
Mode 1 (t0 tot1 ). S 2 , S 3 , S 6 , and D7 are in the on state prior to time zero. S 2 switches
off at t 0 , and body diode of S 1 conducts (Fig. 9).
Mode-2 (t1 tot2 ). At t 1 , S 1 turn on with ZVS (Fig. 10).
Mode-3 (t2 tot3 ). S 3 switches off at time t 2 , and S 4 ’s body diode conducts (Fig. 11).
Mode-4 (t 3 t ot 4 ). Att 3 , S 4 turns on with ZVS (Fig. 12).
Mode-5 (t 4 t ot 5 ). D7 shuts down without reverse recovery at time t 4 when the
current flowing through it approaches zero (Fig. 13).
Mode-6 (t5 tot6 ). S 6 shuts off at the time of t 5 , while D8 as well as S 5 ’s body diodes
conduct (Fig. 14).
Mode-7 (t 6 t ot 7 ). S 5 activates with ZVS at time t 6 . S 1 goes off at time t 7 , and the
subsequent half switching cycle involves a similar action (Fig. 15).
Table 3 Comparison between conventional DAB converter and DAB multiplier

Conventional DAB converter DAB multiplier
One can achieve the voltage equal to the One can achieve higher voltage than the
standard one standard
The value of inductor will be higher in this Since the inductor’s value is directly correlated
case for the same amount of voltage whatever with the transformer’s secondary voltage, it’s
one obtain in case of DAB multiplier value will be reduced as one can apply lesser
amount of voltage. Assume one need 400 V at
output side, but one can apply simply 250 V to
the transformer’s secondary side because the
output voltage will ultimately increase due to
the multiplier’s existence
The total no of switches will be higher (8 The total no of active switches (Mosfet)
switches) lower(6 switches)
The price will be higher The price will be lower
ZVS (Zero Voltage Switching) remain intact ZVS (Zero Voltage Switching) remain intact
The size of the transformer will be more as The size of the transformer will be reduced as
voltage and as well as turns ratio will be higher voltage and as well as turns ratio will be
than DAB multiplier for the same amount of reduced
required voltage
Fig. 9 Mode 1
Fig. 10 Mode-2
182 P. Show et al.
Fig. 11 Mode 3
Fig. 12 Mode 4
Fig. 13 Mode 5
Fig. 14 Mode 6
Fig. 15 Mode 7
3.4 Phase Shift Control Technique
Here, the phase shifting angle is regulated to preserve the necessary level of power
transfer. By delaying or advancing the PWM signals for “Conv2(secondary side)”
relative to “Conv1(primary side)”, the phase shifting angle can be produced.
Closed loop operation is used to implement the phase shift control logic. It is
developed to use a proportional-integral (PI) controller. The image above depicts the
control block diagram needed to enable bidirectional current flow. In this case, the
reference voltage (V*) is being used by the PI controller to govern the phase shift.
The PWM signals for “Conv1” are fixed in this case, whereas the PWM signals for
“Conv2” are controlled by the control logic. As a result, there is a phase shift in
“Conv2’s” output voltage relative to “Conv1’s” output voltage (Fig. 16).
184 P. Show et al.
Fig. 16 Control block diagram
4 Battery Controller
Lithium-ion batteries are used in consumer gadgets due to their high open circuit
voltages and energy-to-weight ratios, low self-discharge rate, lack of memory effect,
and gradual loss of charge when not in use. Battery controller controls the output DC
power for charging and as well as discharging modes, also the battery current during
the charging and discharging process. The discharge process must be terminated
when a battery’s terminal voltage falls just below the threshold voltage or when the
Charging level of the battery descends below to the specified bound, indicating that
it’s the time to charge the battery. The battery’s degrading process accelerates quickly
if improper activities like overdischarging, overcharging, or improper charging take
place. There are two categories of charging techniques: basic and advanced. The
conventional methods can be divided into four categories: constant voltage method
(CV), constant current method (CC), constant current plus constant voltage (CC-
CV), and multistage constant current (MCC) methodology for charging. To further
increase charging efficiency, techniques like Constant Current are being explored.
These techniques include increasing usage and achieving quick charging (Fig. 17).
5.1 Simulink Diagram of Charger
See Fig. 18.
5.2 Vienna Rectifier
See Fig. 19.

Fig. 17 Operation of each mode
Fig. 18 Simulink diagram of charger
5.3 Waveforms Obtained from Vienna Rectifier
See Figs. 20 and 21.

Discussion On Waveforms Obtained From VR. The following points can be noted
from the above waveforms:
• According to Fig. 20., one can able to generate 400 V DC from 230 V, 50 Hz AC.
• One can infer from Fig. 22. that the unity power factor can be achieved easily.
• According to Fig. 23., the source current THD is always less than 5%.
186 P. Show et al.
Fig. 19 Vienna rectifier simulink diagram
Fig. 20 Output voltage from Vienna rectifier
5.4 DAB Multiplier
Parameter Calculation. The following parameters can be calculated as shown

below:
Power (P) = 15KW.
AC input voltage = 230 V.
Mosfet switching frequency( f s ) = 50 kHz.
Fig. 21 Gate pulses for switches of VR
Fig. 22 Source current and source voltage at grid side
DAB converter input (V 1) = 400 V.

DAB converter Output voltage (V 2) = 180 V.
Output voltage ripple = 5% of V out .
Phase shift = 0.1 rad.
Turns ratio (n) = 2 (Table 4 and Fig. 24).
5.5 Waveforms Obtained from DAB Multiplier
See Figs. 25, 26, 27 and 28.

188 P. Show et al.
Fig. 23 THD of source current
Table 4 Calculation of parameters for DAB converter

Inductor: Capacitor: Resistor:
−∅)
L = nV 1∗V2π2∗∅∗(π
2f P = 3.084 uH C= n∗i s −i 0
= 17.78 uF R=
V02
= 9ohm
s f s ∗Δ Vc P
Fig. 24 Simulink diagram of DAB multiplier

Fig. 25 Output voltage from DAB multiplier
Fig. 26 Output power from DAB multiplier
Discussion On Waveforms From DAB Multiplier. The following points can be

noted from the above waveforms:
• The DAB converter calculation reveals that one can be able to create a 35 KW
(level 3) charger with the requirements of a DC level 1 charger (15 KW), resulting
in a reduction in the size of the inductor as from the calculation it is very clear that
the size of inductor is directly proportional to the voltage across the secondary
winding.
190 P. Show et al.
Fig. 27 Soft switching property of DAB multiplier
Fig. 28 Gate pulses
• It is clear from Fig. 24. that the number of MOSFET switches in the DAB converter
can be reduced. A DAB multiplier has 6 total MOSFET switches with a higher
voltage than predicted, compared to the 8 MOSFET switches in a typical DAB
converter.
• One can deduce from Fig. 27. that transistors (MOSFETs) can achieve zero voltage
switching (ZVS).
Fig. 29 Battery charging waveform
5.6 Waveform from Battery Controller
Discussion On Battery Charging Waveform. The following point can be noted

down from the above waveform.
It is abundantly evident from Fig. 29. that the battery’s SOC and voltage are
increasing while the current is decreasing.
6 Summary and Conclusion [6]
The demand for electric vehicles has grown, but the length of time it takes to charge
is a major drawback. A DC fast charger has been proposed to address this problem.
Three components are needed: AC/DC converter, DC/DC converter, and battery
controller. A lithium-ion battery with a fixed SOC and nominal voltage is taken into
consideration. A novel First Charger topology with a DAB multiplier and Vienna
rectifier is proposed to improve power factor and output voltage control.
References
1. Dalessandro L, Round SD, Kolar JW (2008) Center-point voltage balancing of hysteresis current
controlled three-level PWM rectifiers. IEEE Trans Power Electron 23(5):2477–2488. https://doi.
org/10.1109/TPEL.2008.2002060
2. Rajendran G, Vaithilingam CA, Misron N, Naidu K, Ahmed MR (2021) Voltage oriented
controller based Vienna rectifier for electric vehicle charging stations. IEEE Access 9:50798–
50809. https://doi.org/10.1109/ACCESS.2021.3068653
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3. Rodríguez Alonso AR, Sebastian J, Lamar DG, Hernando MM, Vazquez A (2010) An overall
study of a dual active bridge for bidirectional DC/DC conversion. In: 2010 IEEE energy conver-
sion congress and exposition, Atlanta, GA, USA, pp 1129–1135. https://doi.org/10.1109/ECCE.
2010.5617847
4. Qin H, Kimball JW (2014) Closed-loop control of DC–DC dual-active-bridge converters driving
single-phase inverters. IEEE Trans Power Electron 29(2):1006–1017. https://doi.org/10.1109/
TPEL.2013.2257859
5. Lin P, Chua L (1977) Topological generation and analysis of voltage multiplier circuits. IEEE
Trans Circuits Syst 24(10):517–530. https://doi.org/10.1109/TCS.1977.1084273
6. Salavati M, Driss S, Farhangi S (2019) High efficiency electric vehicle fast charging. In: 2019
10th international Power Electronics, Drive Systems and Technologies Conference (PEDSTC),
pp 689–694. https://doi.org/10.1109/PEDSTC.2019.8697531
Overview of SOC Estimation Strategies
for Battery Management in Electric
Vehicles
Anupam Singh and Arvind Yadav
Abstract Electric and hybrid electric vehicles are becoming more popular today.
Typically, batteries serve as the major energy source. Battery management is used
to optimize battery use and protection. This battery management system provides
cell balancing and guards against overcharging and over-discharging of batteries.
For these purposes, a precise state of charge assessment is required. The many
techniques used to determine state of charge (SOC) can be categorized as direct
measurement techniques, accounting techniques, adaptive techniques, and hybrid
techniques. This article discusses the benefits and drawbacks of the most prominent
state-of-charge estimation methodologies. The review also outlines the critical reac-
tion factors required for calculating the battery SOC precisely. This will help make
sure that the SOC assessment is precise. It will help a lot when deciding on the best
method for making an EV’s energy storage and control strategy secure and reliable.
Keywords Electric vehicle · State of charge · Battery management · Sustainable

development
1 Introduction
Many people think of cars when they think of things that hurt the environment. In
fact, cars that use traditional fuels have caused problems like the greenhouse effect
and haze. Because of this, people are once again looking at different energy vehicles,
particularly electric vehicles, which will be the new trend in the coming years [1]. At
the moment, every country in the world is doing research on electric vehicles. Many
of these countries have said that the way batteries are managed is slowing down
the growth of electric vehicles. Efficient battery management is an important part of
A. Singh · A. Yadav (B)

Department of Electrical Engineering, GLA University, Mathura 281406, India
A. Singh
194 A. Singh and A. Yadav
making sure electric vehicles are safe, extending the life of the batteries, lowering
costs, and increasing the driving range [2–9].
A good BMS is required for a battery to work securely and effectively, avoid major
harm, and deal with degradation rate and cells that aren’t balanced [10, 11]. Also, a
good battery management system can check the battery’s state of charge (SOC). This
system can set security warnings to avoid over-discharging or overcharging, evaluate
current and voltage, and sense temperature. Also, a BMS is needed to control and
update data, find faults, and make sure the voltage of each battery is the same. These
are all important parts of getting a good estimate of SOC.
In a battery control system, the state of charge is like the fuel gauge in a normal
car. The SOC job is to tell the driver how the battery is doing and keep problems
like overcharging and over-discharging from happening [12, 13]. In fact, figuring out
how to estimate the SOC is a problem that has been studied. We know that the battery
is a highly complicated and nonlinear electrochemical attribute, and that its success
depends on how it is made and how it is used. At the same time, the performance of
the battery should take into account not only how well a single battery works, but
also how well different batteries in the pack work.
In fact, SOC was first studied by scholars and researchers in the 1960s. Over the
past 50 years, scientists have done a lot of work on figuring out the SOC of batteries,
but this problem still needs a better solution [14, 15]. So, this paper looks at the
different ways SOC can be estimated so that it can help scholars, researchers, and
car companies.
The remainder of the paper is established as follows: Sect. 2 goes with the battery
and its management and State of Charge (SOC). SOC Estimation Methods will be
addressed in detail in Sect. 3. Section 4 will cover the summary, and Sect. 5 will
conclude.
2 Battery and Its Management
2.1 Different Types of Batteries
Batteries are made up of one or more cells. Each cell has chemical reactions that
cause electrons to flow through a circuit. Figure 1 shows that a battery has three
main parts: an anode (the “−” side), a cathode (the “+” side), and an electrolyte. An
electrolyte, which is a material, reacts chemically with an anode and a cathode. A
battery is a machine that changes chemical energy into electrical energy right away.
Figure 1 shows the battery is made up of five parts: the composite positive electrode
(cathode), a separator, the composite negative electrode (anode), and two copper and
aluminum electrode current collectors. Electrolytes separate the positive (cathode)
electrode from the negative (anode) electrode. Negative electrodes are composed of
graphene or coal tar, while positive electrodes are composed of lithium metal oxides.
Overview of SOC Estimation Strategies for Battery Management … 195
ELECTROLYTE POROUS
GRAPHITE
SEPARATOR
CATHODE(+) ANODE(-)
Cu Current Collector AI Current Collector
LITHIUM ION
Fig. 1 Lithium-ion battery
Ni-mh batteries have problems because they are expensive, lose power quickly,
and generate a lot of heat. Lead-acid batteries have problems because they have low
specific energy, don’t work well in cold temperatures, and don’t last long. Li-ion
batteries are used in most portable devices right now because they store more energy
per unit of weight than other types of batteries. In addition, they work well at high
temperatures, save energy, and self-discharge [16].
Table 1 shows vital parameters of different energy storage systems. It is established
that lithium-ion batteries outperform conventional energy storage systems in terms of
power and energy density. Furthermore, they have several appealing characteristics
such as highly efficient, extended cycle life, low self-discharge rate, and high voltage
[16].
Table 1 Performance comparison among various energy storage devices

ITEMS Lead-ACID Ni-MH Li-ION
Voltage (V) 2.0 1.2 3.3–3.7
Energy density (Wh/Kg) 35–40 60–80 100–200+
Power (W/Kg) 300 500–1300 800–3000
Self-discharge rate (%Month) 4–8 20 1–5
Eco-friendly Toxic Yes Yes
Cost Low Medium High
Efficiency (%) 85 80 93
Lifetime (cycle) 300–500 500–1000+ 800–1500+
Charging / Discharging
& Cell Equalizer
Onboard or
Cloud Based
Data Logger
Pack Voltage SOC
Sensors
Li –Ion & Current SOP Main
Data State Wireless
Battery Wireles Cell Voltage Controller
Aggregator Estimator Modules SOH
Pack s
Modules Temperature RUL
Display
Thermal Management
Fig. 2 Battery management system
2.2 Battery Management System
At the moment, BMS is used by a lot of car industries and universities. A highly
formed BMS is used in portable electronic components like cell phones. But the use
of BMS in EVs is still in its early stages. The reason is that there are a hundred times
more batteries inside an EV than in a portable electronic component.
EVs are characterized with high current, power, and voltage which makes BMS
more complicated than portable electronic components.
BMS tasks are monitoring (voltage, current, power, temperature) and evaluating
the SOC, protecting against fault condition (overcurrent, overcharge, undercharge,
and short circuit), and conducting battery health diagnostics. Figure 2 shows that
BMS is made of signal/communication lines, actuators, sensors, and controllers.
2.3 State of Charge (SOC)
The SOC of a battery is the ratio of how much power is still left in the battery to how
much power is available in certain scenarios (discharge and charge ratio, temperature)
[17]. In electric cars, an important parameter is the State of Charge (SOC), which
shows the current storage capacity as a percentage of the total potential.
Figure 3 shows that it gives a measurement of how much electrical energy is kept
in a battery. It is comparable to the gasoline gauge on a typical IC engine car [18,
19].
Equation (1) depicts the mathematical expression:
SOC - 1 100%
SOC -0.5 50%
SOC - 0 0%
Fig. 3 Charge Gauge indicator
Qc
SOC = ∗ 100% (1)
Q
In the above equation, Qc is the battery charge and Q is the battery capacity. SOC
may be written as [0, 50 and 100%] or [0, 0.5 and 1]. A cell with a SOC of 100%
or 1 is completely charged. A cell with a SOC of 50% or 0.5 is half charged or half
discharged. A cell with a SOC of 0% or 0 is empty [20].
Figure 4 depicts the SOC (in %) value during charging and discharging.
In Fig. 4 OCV is the open-circuit voltage of the cell. In reality, the battery fluctuates
with both internal and external elements, requiring a modification to Eq. (2):
Fig. 4 SOC during charging and discharging

t ηI
SOC(t) = SOC(t0 ) − ∫ dτ (2)
t0 Cn
In Eq. (2), SOC (t) is the battery’s nominal capacity. Cn is the capacity of battery,
I is the current, and η is the coulomb efficiency, also known as discharged efficiency
(η = Q/Qn ).
3 SOC Estimation Methods
As stated at the beginning, the SOC of the battery is also a crucial part of BMS.
When the SOC of a battery is precisely and safely estimated, it can be used as a
measurement factor for automotive energy management and the best design of the
control system. So, more ways have been suggested for evaluating the SOC of a
battery in actual time. In order to compare these methods more closely, we have put
them into four categories, which are shown in Fig. 5.
Model-Based Methods
To be able to estimate SOC online, a model of Li-ion batteries must be made. Equiv-
alent Circuit Model (ECM) and Electro-Chemical Model (EChM) are two ways to
model how a Li-ion battery behaviour changes over time, and simulating models can
be used for both the models so as to predict the battery behaviour over time. When
EVs are in use, OCV methods can’t be used because they need a certain amount of
time to rest before they can estimate SOC.
SOC ESTIMATION METHODS
Equivalent Circuit Model (ECM) Method

Model Based
Electrochemical Model (EChM) Method
Coulomb Counting (CC) Method

Book Keeping
Modified Coulomb Counting (MCC) Method
Open Circuit Voltage (OCV) Method

Direct Internal Resistance (IR) Method
Output Voltage (OV) Method
Particle Filter (PF) Method

Adaptive Filter Fuzzy Neural Network (FNN) Method
Kalman Filter (KF) Method
Fig. 5 Battery SOC Estimation Methods for BMS

Fig. 6 First order equivalent

circuit model of battery R1
Rs
+
Voc C1
Vt
V1
-
Equivalent Circuit Model

ECM methods are best because they are easy to use and take less time to work out.
ECM methods can only calculate the exact SOC for fresh batteries, and they can’t
analyze all of the battery’s electrochemical reactions, which can lead to the final SOC
value wrong [21]. Still, ECM methods and Extended Kalman-Filter (EKF) are often
used together to accurately determine SOC.
The terminology used in Fig. 6 is described as follows:
V t = Terminal voltage, Rs = Internal resistance,
R1 = Battery ohmic resistance, C1 = Battery nominal capacity,
V oc = Open-circuit voltage.
Book-Keeping Methods
The data about how much current flows out of a battery are used in the book-keeping
method. This method makes it possible to include rechargeable battery pack effects
such as self-discharge, energy losses, and how well the battery discharges. Estima-
tions have been made using the coulomb counting method and the modified coulomb
counting method.
Coulomb Counting Method
The coulomb counting method is the easiest way to figure out the SOC of a battery.
This method is employed to calculate the SOC(t). The SOC(t − 1) values that were
estimated before are used to figure out the SOC(t). To figure out SOC, use the
following equation:
SOC (t) = SOC (t − 1) + I (t)nt (3)
Here
I(t) is the Discharging Current.
But the accuracy of this method is affected by things like temperature, the past of
the battery, the discharge current, and the number of cycles [22].
Modified Coulomb Counting Method
To improve the cc method, a new method has been suggested. This method requires
the rectified current to increase the precision of the estimation method. The purpose
of allowing flow of current is to change the flow of current. There is a nonlinear

connection between the current that is being fixed and the current of a battery that is
being used up. With the customized method, SOC is calculated with the following
equation:
SOC (t) = Ic (t) Qn t + SOC (t − 1) (4)
Here,
Ic (t) = K2 I (t) + K1 I (t) + K0
where K 0 , K 1 , K 2 and are constant values.

The outcomes of the tests show that the modified technique is more precise than
the conventional method [23].
Direct Methods
Direct measurement techniques use things like a battery’s inductance or voltage
level. Methods like internal resistance, open-circuit voltage, and output voltage are
the most common.
Internal Resistance (IR) Method
Using the battery’s voltage and current, the method measures the battery’s internal
resistance. Voltage is monitored using variations in current change over brief periods
of time (below 10 ms). The DC capacity of the battery is shown by the DC resistance,
which is based on how the voltage and current change. To get the ohmic impact and
reduce the effects of exchange response and chemical transmission, a brief time
of below 10 ms is required [24]. If the period is longer, a mistake is present in the
calculated resistance value. The approach also has good flexibility and only estimates
SOC accurately during the last stages of discharge. Also, its low value makes it hard
to obtain a precise result of the internal resistance.
Output Voltage Method
The output voltage method is formed on the fact that when battery is discharging, the
output voltage drops because of the internal inductances. Since the EMF of the battery
is related to the voltage at the terminal, this method is the most accurate. Different
discharge currents and temperatures have been used with the terminal voltage method
[25]. But at the last of a battery’s charge, the output voltage drops quickly, so the
estimated error of the output voltage method is big [23].
Open-Circuit Voltage (OCV) Method
This method is based on the principle that a battery’s state of charge is equal to
its open-circuit voltage when it hasn’t been connected to a load for more than two
hours. But a disconnect time that long might not be good for a battery. The open-
circuit voltage and state of charge of the Li-ion battery would not follow a straight
line like the lead-acid battery. By putting a pressure load on a Li-ion battery and
Fig. 7 Second order

equivalent circuit model of
battery
waiting for it to reach equilibrium, the relationship between OCV and SOC was
found. Because the conventional open-circuit voltage varies from battery to battery,
all batteries can’t have the same relationship between the open-circuit voltage and
SOC. The connection in between open-circuit voltage and state of charge needs to
be measured to get a precise estimation of the SOC. It is a simple process that works
very well. The main problem with the OCV method is that it takes a long time to
reach balance [26]. The plan can only be used when the cars are parked and not being
driven.
The open-circuit voltage (OCV) of a lead-acid battery is approximately propor-
tional to its state of charge (SOC):
VOC (t) = b1 × SOC(t) + b0 (5)
where
SOC(t) = Battery SOC.
b1 = Obtained from knowing the value of b0 and V OC (t) at SOC = 100%.
b0 = Battery terminal voltage when SOC = 0%.
The terminology used in Fig. 7 is described as follows:
V oc = Open-circuit voltage; R0 = Internal resistance (In series with voltage
source);
C 1 = Double layer capacitance; R1 = Charge transfer resistance;
R2 = Resistance due to polarization; C 2 = Capacitance due to polarization.
When compared to activation polarization, concentration polarization has slower
dynamics.
Adaptive Filter Methods
Recently, as AI has grown, many new adaptive systems for estimating SOC have
been made. Particle filter, fuzzy neural network, and Kalman filter are some of the
new methods. The adaptive systems are ones that can change on their own as the
environment changes. Since there are many chemical factors that affect batteries and
their SOC is not linear, adaptive systems are a good way to estimate SOC [23].
Kalman Filter (KF) Method

The KF method, which models the battery while taking into account unknown char-
acteristics, is the most effective way for predicting the SOC value. High precision
and a reliable way to figure out SOC when there are outside interruptions are the main
advantages of the KF method [27, 28]. It is frequently utilized in a wide range of appli-
cations, including those involving cars, radar tracking, aeronautical engineering, and
navigation tracking. Despite having a high processing cost, KF has recently found
great success in battery status estimation. One of the best things about KF is that it
can fix itself, which makes it able to handle large differences in current.
Fuzzy Neural Network
It’s used in a lot of different ways, especially to figure out which system is unknown.
In multivariable system identification, FNN can find the best values for the instruc-
tion system accessories. Lee et al. looked into a way to evaluate the SOC of each
battery in a series of batteries using computational intelligence. A FNN, B-splint
membership functions, and a reduced-form genetic algorithm are all used together
in computational intelligence [23].
The SOC estimation techniques are listed in Table 2 along with their merits and
demerits. Even though there are numerous SOC estimation techniques, only a small
number of them have been applied in actual EV applications. One of the SOC estima-
tion methods used in actual cars is the CC approach. Although complicated calcula-
tion makes data-driven-based SOC estimation a problem for real-world applications,
it is thought to be a more accurate method of estimating SOC.
Table 2 Comparison of SOC methods

Sequence number SOC methods Merits Demerits References
1 ECM Online, highly Efficiency is [21, 22]
precise model-dependent
2 EChM Online, highly Efficiency is [21, 22]
precise model-dependent
3 CC Easy, less estimation Challenge to find [22, 23]
power initial SOC
4 OCV Easy, highly precise Offline and [26, 24]
laborious
5 IR Easy Less precise [24, 25]
6 EMF Easy, cost-effective Lengthy [25]
computation
7 PF Highly precise, less Use sophisticated [23, 27]
estimation time mathematics
8 KF Highly precise, less Complicated [27, 28]
estimation time calculation
9 GA Highly precise Intricate [28]
calculation
4 Summary
The principal goal of this research is to provide comprehensive information to look

at the different ways SOC can be estimated for EV batteries. Table 2 lists the merits
and demerits of various types of SOC estimation methodologies.
People think that estimating SOC with data-driven methods is more accurate, but
the complicated calculations slow down practical applications. This problem can be
solved by reducing complexity in accordance with the capabilities of the computation
unit. The following suggestions are made for research on potential improvements to
SOC estimation techniques:
a. When estimating SOC, take into account external disturbances that batteries may
encounter.
b. For AI-based techniques, enhance the training algorithms and make use of a
sizable data set.
c. As each SOC estimation method has advantages of its own, linking the top
approaches to work in concert with one another can increase estimation accuracy.
d. To keep costs down, the SOC computation construction process should be cut
down as much as possible.
5 Conclusion
This article describes common techniques for estimating the level of charge of
batteries. The direct measurement method works well for simple tasks, but their preci-
sion isn’t very good in some SOC estimation algorithms. The open-circuit voltage
approach is simple to apply, but propulsion batteries can’t be used while SOC is being
supervised, so they can only be used when the vehicle is stable. Almost all the time,
lead-acid batteries are used for these methods. Even though book-keeping methods
that use current data as input don’t require much computing work, they aren’t always
accurate over time. This method works pretty well on lithium batteries. To get rid of
all of this wrong information, the book-keeping technique uses a number of different
methods. The main problem with adaptive methods of estimating is that they require a
lot of computing power for complex calculations, even though they are very accurate
across the whole SOC varying and at various flow currents. A regularization mistake
can also happen with nonlinear systems. The accuracy of the designed approach is
influenced by the complexity and precision of the battery design.
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Comprehensive Review
of Switched-Capacitor Boost
Single-Source Nine-Level Inverters
Haresh Nanda and Himanshu Sharma
Abstract Penetration of renewable sources into the grid demands new inverter
configurations to improve the quality of voltage and current. In such applica-
tion, multilevel inverters (MLIs) are booming due to their advantages of reduced
harmonics and staircase output voltage pattern. Reduced switch and reduced source
based topologies have been developed for different applications. However, switched-
capacitor (SC) topologies are beneficial in reducing switch count as well as the source
count while providing boosted output from a dc source. From 5-level, 7-level too
much higher level SC type MLI topologies have been researched in recent years. In
this work, 9-level topologies are extensively reviewed as it reduced the harmonics
efficiently and on the other hand fewer components can be utilized to produce a
required multilevel boosted output. A 9-level SC type MLI can produce two-time
gain and four-times gain output efficiently. The 9-level MLIs with two-time gain,
i.e., dual-boost SC MLI (SC-DMLI) and the other with four times gain capability,
i.e., quadruple-boost SC MLI (SC-QMLI) are reviewed critically in this work. A
comparison among these topologies is also illustrated. Simulation results of selected
SC-DMLI and SC-QMLI are presented at the end for verification.
Keywords Multilevel inverter · Nine-level · Reduced components · Self-voltage

balance · Single-source · Switched-capacitor · Voltage gain
1 Introduction
Renewable energy based power generation is the most wanted requirement across the
globe in recent days. This requirement is to reduce the fossil fuel power generation
and pollutions [1, 2]. A key step towards achieving carbon neutral energy generation
is the design of new power converters such as dc-dc converters and dc-ac inverters. In
solar and wind energy systems towards designing compact systems, high-gain dc-dc
H. Nanda · H. Sharma (B)

School of Electronics and Electrical Engineering, Lovely Professional University, Phagwara,
Punjab, India
208 H. Nanda and H. Sharma
and dc-ac converters are more popular. Literature manifest more compact inverters,
which devoid of the dc-dc stage and synthesizes required high-gain ac output through
single-stage inverters which are gaining popularity [3–6]. Conventional three-level
inverters must be combined with dc-dc stage to achieve required high-gain output,
whereas multilevel inverters (MLIs) have been introduced later as a potential solution
to many problems [3–6]. The key problem that is surmounted using MLI is the size
of the filter is reduced, voltage stress is reduced and electromagnetic interference
can be kept minimum. Back in 1980s to 1990s, three different MLIs such diode-
clamped, flying capacitor and cascaded H-bridge structures have been reported for
applications such as high-voltage dc system, active power filters, photovoltaic (PV)
applications, traction application, high-frequency power generation, etc. The diode-
clamped and flying capacitor structures were developed with the use of single-dc
source but employing number of diodes and capacitors, respectively [3, 7–9]. Due
to the more number of diodes and capacitors, controlling the capacitor voltage and
balancing as desired becomes more complex. Also, failure of one component leads
to complete system failure as the diodes and capacitors are connected in series gener-
ally. To avoid this problem, cascaded H-bridge circuits proved efficient in different
applications [10, 11]. Such circuit is formed by cascaded connection of H-bridge
modules and this facilitates reliability in operation even under failure of one compo-
nent. A major issue that holds back in further research is the requirement of multiple
dc sources and integration of number of switches. This has motivated research on
topologies to make it more compact in terms of switches, dc sources and capacitors
and diodes.
In the recent past, initially researchers have developed structures employing
reduced number of switches. For instance, a conventional cascaded H-bridge circuit
requires twelve switches and three symmetrical dc sources to synthesize a 7-level
output. However, asymmetrical structure were also developed which can produce the
7-level output using two asymmetrical dc source with reduced number of switches.
Many such reduced switch MLIs presented in [12–18] can operate in symmetrical
and asymmetrical modes. Different modes of MLI operation is explored in [12]
where three sources are still required to generate 7-level output, i.e., three PV panels
may be utilized as the sources. These MLIs also should be operated under different
loading conditions. Whereas, switched-diode type reduced switch structure as in
[13] addresses this issue at the cost of an additional switch. Symmetrical operation
under any loading condition can be achieved using the structure presented in [19],
which requires more number of switches compared to further improved topologies
developed later. Along with the effort to reduce the switch and source count reduc-
tion is taken as a key initiative by developing asymmetrical structures which may
be beneficial for PV applications [14, 15, 20]. These circuits still require different
rating panels to be integrated to produce the required output. Figure 1a shows the
generalized structure of the reduced switch MLI that requires multiple sources, high
voltage rating switches, and multiple dc-dc or ac-dc converters. This therefore cannot
be considered as a potential candidate towards achieving high-gain output using
compact structure. Considering this, MLIs with minimum or single input source by
Comprehensive Review of Switched-Capacitor Boost Single-Source … 209
integrating switched-capacitors (SCs) as potential voltage boosters are developed

more recently.
In PV application, numbers of PV panels are connected in series and parallel to
match the required grid voltage and current. SC integration with MLI can produce the
required boost output while reducing the number of panels connected to a common
dc bus as shown in Fig. 1b. The dc-dc converters can be avoided as SC assist in
voltage boosting. For instance, MLI in [21, 22] can produce high voltage gain output
and can also be extendable to create more voltage levels. Interestingly, each capacitor
are self-charged without using voltage balancing circuit as required in conventional
flying capacitor circuits. While maintaining the desired voltage across the capacitors,
different circuit combinations are also possible to create 13-level, 17-level, and more
voltage steps using one or minimum dc sources [6, 23]. Without much effort to
Local linear & Local linear &

non-linear load non-linear load
DC-DC Reduced
Converter Reduced Switch
switch Switched-
And multilevel Capacitor
inverter Multilevel
AC-DC Inverter
Converter
dc bus
Multiple Single input

input source source
(a) (b)
Vout
2Vin
1.5Vin
Vin
0.5Vin
-0.5Vin ωt
-Vin
-1.5Vin
-2Vin
Dual boost 9-level SC MLI
(SC-DMLI)
Vout
4Vin
3Vin
2Vin
Vin
-Vin ωt
-2Vin
-3Vin
-4Vin
Quadruple boost 9-level SC MLI
(SC-QMLI)
(c)
Fig. 1 a Generalized reduced switch MLI topology, b emerging single-input SC-MLI topology,
c nine-level SC-MLI output pattern
redesign a compact module, CHB circuit can be modified as in [5, 24] to create
high-gain boosted output from one source. The voltage balancing issue persists in
these topologies and that needs special attention. Apart from this, as these circuits
are derived from the conventional structure, thus number of switch requirement is
very high. So, it is clear that topologies are designed to produce 5-level, 7-level,
9-level to 25-level, and more using reduced number of switches and minimum dc
sources. However, in terms of the application industries or in real-time PV system as
the number of level is more, few more number of components and the stress cannot
be avoided. Therefore, compact structure with optimum voltage levels can be a good
choice. Therefore 9-level circuits are extensively studied as it reduced the harmonics
efficiently and on the other hand fewer components can be utilized to produce a
multilevel output.
In [7, 25, 26], 9-level circuits utilize the concept of more voltage level step genera-
tion by extending the modules. Therefore, more components are used while only one
dc source is employed. For producing the ac output voltage, H-bridge is used. The
switches in the H-bridge bear the maximum voltage that increases the total voltage
stress that needs attention. MLIs proposed in [27, 28] also are efficient in synthesizing
more levels at the output. These are one of the early developed structures which utilize
two switches; one to discharge and one to charge the capacitor. Diode is additionally
used in the voltage level generation path. However, series diodes may also block the
current flow under inductive loading condition, which needs careful design. Number
of switches is comparatively more than earlier discussed circuits. The 9-level MLI in
[29] creates the required output with two-times gain. Two capacitors are maintained
the voltage at half of the dc voltage magnitude and these are discharged in series
with the dc source to crate twice voltage gain. Four switches are used for ac voltage
generation, which has maximum voltage stress. To address the issue with voltage
stress, new structures have been analyzed in [30, 31]. Internally, the ac output is
obtained without using high voltage rating components. On the other hand, more
sources can be integrated to increase the voltage levels. New circuit in [32] reduces
the capacitor stress and rating. More compact modules proposed in [33–35] to create
9-level output with gain limited to two-time only. Alongside, circuits with 9-level
output and four-time gain introduced more recently in [36, 37]. These circuits have
the advantage of modularity to create more voltage levels, whereas more number
of components can sacrifice the compactness. Without much complexity, simpler
circuits are developed in [38, 39] which produces 9-level output with four-times
voltage boosting. Other MLIs developed in [40, 41] also comes under the similar
category but number of capacitors and voltage stress are different than the earlier
ones. It is clear from Fig. 1c that 9-level boost type circuits can synthesize two types
of output pattern. One with two-time gain, i.e., dual-boost SC MLI (SC-DMLI) and
the other with four-time gain capability, i.e., quadruple-boost SC MLI (SC-QMLI).
In this work, 9-level topologies of both these categories are reviewed critically in
Sects. 2 and 3.
Section 4 puts forward comparison between these circuits for more understanding.
Section 5 presents the simulation of selected 9-level circuits to show the working.
Finally, it is clear from the conclusions that new 9-level circuit design requires clear
understanding of the existing circuits. Therefore, researchers can refer this work to
generate new ideas.
2 Review of Dual-Boost SC MLI (SC-DMLI)
This section details recently developed 9-level MLIs with two-time voltage gain. The
circuits shown in Fig. 2a–e produce the output with voltage steps 0, ±0.5V in , ±V in ,
±1.5V in , and ± 2V in . Figure 2a shows that the SC-DMLI circuit employs single dc
source, 11 switches, and two capacitors. Both capacitors are charged to half of the
dc source magnitude by connecting with the source in parallel. In the positive cycle,
the first step is produced as V in − V c1 , next step is produced due to source only, third
step is produced as V in + V c1 , and the peak level is produced as V in + V c1 + V c2 . In a
similar way, negative voltage levels are produced. Figure 2b shows that the SC-DMLI
circuit employs single dc source, 11 switches similar to the circuit in Fig. 2a, two
dc-link capacitors, and one flying capacitor. Both the dc-link capacitors are charged
to half of the dc source magnitude by connecting with the source in parallel. The
flying capacitor (C 3 ) is charged to input voltage magnitude. In the positive cycle, the
first step is produced due to V c2 , next step is produced due to source only, third step
is produced as V c2 + V c3 , and the peak level is produced as V in + V c3 . In a similar
way, negative voltage levels are produced. Figure 2c shows that the circuit employs
single dc source, 10 switches, and two capacitors. Both capacitors are charged to half
of the dc source magnitude by connecting with the source in parallel. In the positive
cycle, the first step is produced due to V c2 , next step is produced due to source only
(where both the capacitors can be charged), third step is produced as V in + V c2 ,
and the maximum voltage level is produced as V in + V c1 + V c2 . In a similar way,
negative voltage levels are produced. Figure 2d shows that the circuit employs single
dc source, 10 switches, and two capacitors. Both capacitors are charged to half of the
dc source magnitude by connecting with the source in parallel. In the positive cycle,
the first step is produced due to V c1 or V c2 , next step is produced due to source only
(where both the capacitors can be charged), third step is produced as V in + V c1 or V in
+ V c2 , and the maximum voltage level is produced as V in + V c1 + V c2 . In a similar
way, negative voltage levels are produced. Figure 2e shows that the circuit employs
single dc source, only 9 switches, and two capacitors. Both capacitors are charged
to half of the dc source magnitude by connecting with the source in parallel. In the
positive cycle, the first step is produced due to V c1 or V c2 , next step is produced due
to source only (where both the capacitors can be charged), third step is produced as
V in + V c1 or V in + V c2 , and the last voltage level is produced as V in + V c1 + V c2 .
S1 S4
S8
S11 C1
S10 S3 S6 S8
Vin S2 S6 S7 C1
Vin C3
S10 C2 S1 S2 S5
S9 C2
S3 S5 S11 S4 S7 S9
Io Io
+ Vo - - Vo +
(a) (b)
+ Vo -
Io
S9 S10
D1 S3 D1
C2 S6
S10 C2 S7
S3 S4 S5 S6
S1
Vin S5
C1 S9 S2 D3 S8
C1
S1 D2 S4
Vin S2
S7 Io
S8 - Vo +
(c) (d)
C2 S6 S8
D1 S5
Io
S3 D2 S4
+ Vo -
S1
C1 S9 S7
Vin S2
(e)
Fig. 2 Dual-boost 9-level SC-DMLI topologies. a [33], b [35], c [31], d [29], e [34]
3 Review of Quadruple-Boost SC MLI (SC-QMLI)
This section details recently developed 9-level MLIs with four-time voltage gain.
The circuits shown in Fig. 3a–e produce the output with voltage steps 0, ±V in ,
±2V in , ±3V in , and ±4V in . This is the maximum achievable voltage gain for a 9-
level topology. Figure 3a shows that the SC-QMLI circuit employs single dc source,
12 switches, and two capacitors. One capacitor (C 1 ) is charged to input voltage
magnitude due to parallel connection with the source, and the other (C 2 ) is charged
to twice the dc source magnitude. In the positive cycle, the first step is produced due
to the source only (where the capacitor C 1 is charged), the next step is produced as
V in + V c1 (where the capacitor C 2 is charged), third step is produced as V in +V c2 ,
and the peak level is produced as V in + V c1 + V c2 . In a similar way, negative voltage

levels are produced. Figure 3b shows that the circuit employs single dc source, 12
switches, and three capacitors. One of the switches is bidirectional and therefore the
driver requirement is low. One capacitor (C 1 ) is charged to input voltage magnitude
due to parallel connection with the source, and the other capacitors (C 2 & C 3 ) is
charged to twice the dc source magnitude. In the positive cycle, the first step is
produced as V c3 − V c1 , the next step is produced as V in + V c1 (where the capacitor
C 3 is charged), third step is produced as V in + V c3 , and the peak level is produced
as V in +V c1 +V c3 . In a similar way, negative voltage levels are produced. Figure 3c
shows that the circuit employs single dc source, only 9 switches, and two capacitors.
One capacitor (C 1 ) is charged to input voltage magnitude due to parallel connection
with the source, and the other (C 2 ) is charged to twice the dc source magnitude. The
operation is very similar to the SC-QMLI shown in Fig. 3a. Figure 3d shows that
the SC-QMLI circuit employs single dc source, 10 switches, and three capacitors.
One capacitor (C 1 ) is charged to input voltage magnitude due to parallel connection
with the source, and the other capacitors (C 2 & C 3 ) is charged to twice the dc source
magnitude. The operation is very similar to the SC-QMLI shown in Fig. 3a. However,
in the positive cycle C 1 and C 2 contributes to produce the required four steps and in
the negative half-cycle cycle C 1 and C 3 contributes to produce the required four steps.
Figure 3e shows that the SC-QMLI circuit employs single dc source, 8 (minimum)
switches, and three capacitors. The operation is very similar to the operation of SC-
QMLI shown in Fig. 3d. In the positive cycle C 1 and C 3 are contributing whereas
C 1 and C 2 contributes to produce the required four steps in negative half-cycle.
4 Comparative Assessment of SC-DMLI and SC-QMLI
To show the different features of the SC-DMLI and SC-QMLI, 9-level circuits studied
in Sects. 2 and 3 are compared in Table 1. The number of switches (N s ), number
of driver circuits (N dv ), number of diodes (N d ), and number of capacitors (N c ) are
summarized for different circuit configurations. Approximately 8–12 switches are
required for designing the circuit. The driver circuit requirement for some circuit is
low due to employing bidirectional switch. More use of capacitors or the rating of the
capacitors also should be selected appropriately to maintain the system reliability.
The gain is two for some of the topologies, and maximum four gains is achieved
in the recent circuit topologies. The full H-bridge is used in few circuits, which has
high voltage stress.
S4 S7 S7
S9 S12 S5
S12 S3 C1 C2 S4 C1 S9
S6 C2
S1 S1 S2
S11 Vin S2 C3 Vin S3 S10
S10
S5 S8 S11 S8 S6
Io Io
- Vo + - Vo +
(a) (b)
D2 D3
S4 C2 C3
S8 S5 S6
D1 C1 S S6 S8 S3
3 C2 Io S4
D1 C1 S6
S2
S1 + Vo - S9 Vin S7
S1
S2 S5 S9 S7
Vin
Io
- Vo +
(c)
(d)
D2 C2
S3
S7 D1 C1
S5
Io
S1
- Vo +
Vin
S8 S6 S2
S4
D3 C3
(e)
Fig. 3 Quadruple-boost 9-level SC-QMLI topologies. a [39], b [38], c [41], d [1], e [40]
5 Simulation Verification
To understand the working of both the types of 9-level MLIs, i.e., SC-DMLI with
twice gain and SC-QMLI with quadruple gain are simulated in MATLAB using
fundamental frequency control logic. A SC-DMLI proposed in [29] and SC-QMLI
proposed in [41] are simulated considering input voltage source of 100 V. Both
these circuits use two capacitors each. In the SC-DMLI equal rating capacitors of
1500 µF are selected and for the SC-QMLI two capacitors with rating 1500 µF and
3000 µF are selected. IGBT with anti-parallel diodes as switches are used for the
circuit design. Different loads are connected to verify the operation. One is the purely
resistive type 50 Ω load, and the other load is 60 Ω–120 mH load.
Figure 4a shows the output of SC-DMLI where the output voltage is boosted to
two-times, i.e., 200 V due to sum of single input source voltage and two capacitor
voltages. Both capacitors (C 1 and C 2 ) are equally charged to half of the dc source
Table 1 Comparison of SC-DMLI and SC-QMLI topologies

SC-MLIs Ns N dv Nd Nc Gain H-bridge
9-level SC-DMLI (two-times gain)
[33] 11 11 0 2 2 NO
[35] 11 10 0 3 2 NO
[31] 10 8 1 2 2 NO
[34] 10 10 3 2 2 NO
[29] 9 9 2 2 2 YES
9-level SC-QMLI (four-times gain)
[39] 12 12 0 2 4 NO
[38] 12 11 0 3 4 NO
[1] 10 10 3 3 4 NO
[41] 9 9 1 2 4 YES
[40] 8 8 3 3 4 NO
magnitude by connecting with the source in parallel. The load current pattern is
changed due to the change in load suddenly at 0.2 s. Figure 4b shows the output
of SC-QMLI where the output voltage is boosted to four-times, i.e., 400 V due to
sum of single input source voltage and two capacitor voltages. One capacitor (C 1 )
is charged to input voltage magnitude, and the other (C 2 ) is charged to twice the
dc source magnitude. The load current pattern is changed due to the change in load
suddenly at 0.2 s. Capacitor voltage ripple also changes with change in load from
resistive to inductive type. The harmonic profile of load voltage and load current of
the SC-QMLI is shown in Fig. 4c. The total harmonic distortion of load voltage and
load current are 9.53% and 1.73%, respectively under inductive load condition.
To validate the stable operation with different transient operations, SC-QMLI is
further simulated with change in dc input from 80 to 100 V. As can be verified from
Fig. 5a, the capacitor voltage balancing is inherent and 9-level output is accessible
persistently. Figure 5b further shows the operation with change in control input,
i.e., the change in modulation index (M). Both capacitor voltages are balanced, and
9-level voltage pattern changes with change in control input.
(a)
(b)
(c)
Fig. 4 Simulation results a SC-DMLI [29] operation under different load, b SC-QMLI [41]
operation under different load, c hHarmonic analysis load voltage and load current under RL load
Vo (V), 25*Io (A), Vc1 (V), Vc2 (V) Vo (V), 25*Io (A), Vc1 (V), Vc2 (V)
M change from 0.2 to 0.6 M change from 0.6 to 0.9

Supply input change
Time (s) Time (s)
(a) (b)
Fig. 5 Simulation results SC-QMLI [41] operation under a variation in input voltage and b change
in modulation index
6 Conclusion
In terms of renewable energy or specifically for PV and electric vehicle applications,

SC type boost MLIs are gaining much reputation. Some SC MLIs were developed
with multiple sources with low step-up ability. Several SC type MLIs with 5-level,
7-level, 9-level, and more voltage levels were also proposed employing single input
source and significant voltage boosting ability. Researchers may find difficulty in
accessing several SC type topologies and their evolution. Therefore, recently devel-
oped SC MLIs with 9-level and single input source have been collected in this work,
which can be referred as a unique solution for designing new configurations.
Utilizing self-voltage balancing SCs, a 9-level MLI can synthesize twice gain or
maximum four-times gain output. Not considering the topologies with unity gain, 9-
level SC type MLIs under SC-DMLI and SC-QMLI categories have been reviewed
critically in this work. Comparisons have been conducted for different SC-DMLI
and SC-QMLI in terms of number of components and voltage gain. Also, simulation
results of each variety of 9-level circuits justify the voltage boosting feature. Some
of the topologies that utilize H-bridge require more number of high voltage rating
switches and topologies developed without H-bridge have more benefit of low voltage
stress. Inrush current in general SC MLIs are unavoidable, which is very high due
to continuous charging discharging of the SCs. Although different methods were
addressed recently to limit the inrush current, still extensive research is ongoing
to address this issue. Therefore, future structural innovation requires understanding
on number of components, voltage stress, inrush current, and voltage gain. The
reviewed topologies also can attain more applicability in future renewable energy
based standalone and grid-tied systems utilizing the SiC and GaN devices.
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Design, Simulation and Analysis
of DC–DC Cuk LED Drivers
B. Lakshmi Praba, V. Vidhu Priya, and R. Seyezhai
Abstract Light Emitting Diodes (LED) have achieved great success in the lighting
industry due to their superior qualities when compared to conventional lighting solu-
tions. These qualities include a long lifespan, minimal maintenance needs, environ-
mental friendliness, high luminous efficiency, controllability of both light and color,
reliability, and high-power density. In the lighting business, LED driver design is
crucial. They protect the LED from changes in power and voltage. In this study,
various LED drivers are compared using a DC/DC Cuk converter that can operate
in both continuous conduction mode (CCM) and discontinuous conduction mode
(DCM). A new novel flicker free PV based interleaved non-inverting DC–DC cuk
LED driver is proposed in this research work. There is a brief evaluation and compar-
ison of the performance parameters of integrated cuk-sepic converter, non-inverting
cuk converter (NICC), conventional cuk converter, and interleaved non-inverting cuk
converter. For the proposed LED driver, an Artificial Neural Network (ANN) method
is implemented to reduce the ripple value by optimizing the specific values of capac-
itor, inductance, and switching frequency. The MATLAB/SIMULINK software is
utilized to simulate the circuit configuration for the recommended topology, and the
outcomes are validated.
Keywords CUK · LED driver · Non-inverting · CCM · DCM · Ripple · ANN ·

PV
1 Introduction
In many lighting uses, the light-emitting diode (LED) has replaced conventional
general lighting systems (GLS) and fluorescent lighting sources as a viable alterna-
tive. In comparison to other light sources, LEDs have many advantages including a
long lifespan, high effectiveness, the ability to produce directional light, the absence
B. Lakshmi Praba (B) · V. Vidhu Priya · R. Seyezhai

Department of EEE, Sri Sivasubramaniya Nadar College of Engineering, Kalavakkam, Chennai,
India
222 B. Lakshmi Praba et al.
of mercury, and the ability to dim. Since LEDs are typically thought of as being
current-controlled, a dc–dc converter is necessary to power the LED load [1–3].
A good LED driver is essential for a high-quality LED lamp; it must not only be
designed to meet requirements but also have a lifespan that is similar to that of the
LED. In order to maximize the LED’s effectiveness and dependability, the controller
system must be created. Poor efficiency and increased flicker are the two biggest
problems the lighting industry has ever had to deal with when developing converters
for such low-power lighting loads. However, there is a trade-off between efficiency
and cost when choosing converter topologies [4, 5].
The usage of renewable energy sources like solar photovoltaic (PV), wind, solar,
thermal, etc. has been encouraged due to growing concerns about climatic change and
global warming caused by carbon emissions [6]. To make solar energy more useful, it
is essential to lower the cost and enhance efficiency [7]. The growth of solar energy
systems in recent years with better performance is thus the subject of numerous
research works. The solar-powered device achieves high conversion efficiency due
to power electronic converters, which transforms electrical energy from one form to
another [8, 9]. Therefore, the DC/DC cuk LED drivers are examined in this research
work [10, 11].
The Cuk converter topology [12–14] was chosen because it can offer non-pulsating
input and output current, a minimal number of storage components and switches,
and a high energy storage density by using a capacitor instead of an inductor. Similar
to the Cuk converter, the Non-Inverting Cuk converter produces positive [15–17]
output as related to the negative voltage of the Cuk converter.
The converters are made to operate in both CCM and DCM, to achieve high
efficiency. But the main difficulty of conventional cuk converter is higher current
and voltage stresses [18] on the semi-conductor devices. Therefore, the integrated
cuk converter is presented. That is a cuk-SEPIC integrated converter for reduced
stress and improved efficiency compared to conventional cuk converter [19–21]. But
this cuk-integrated SEPIC converter has more current ripple and this ripple causes
flickering effect.
Therefore, a novel Interleaved [22, 23] DC/DC cuk non-inverting LED driver is
proposed, and it has reduced filter size and reduced LED current and voltage ripple.
The suggested novel interleaved [24, 25] cuk converter has the following benefits: it
can step up and step down the load voltage, it has continuous source and load current,
it is symmetrical in structure, it distributes current equally among the phases, and it
offers ripple cancellation, which further reduces ripple.
The Artificial Neural Network (ANN) method is used to find the exact values
of filter capacitor and inductor values with respect to the duty ratio and operating
frequency to propose the flicker free interleaved non-inverting cuk LED driver. Then
the conventional inverting cuk LED driver, non-inverting cuk LED driver, cuk SEPIC
integrated LED driver, and the proposed LED driver performance parameters are
analyzed and compared. Circuit design simulations for the discussed topologies have
been performed using MATLAB/SIMULINK.
Design, Simulation and Analysis of DC–DC Cuk LED Drivers 223
2 Proposed Interleaved Non-inverting DC/DC CUK LED

Driver
The interleaving topology has been utilized for electronics, mainly in high power
applications. Since stress across the device can exceed its limit in high power appli-
cations, the power device cannot manage the strain. Interconnecting the devices can
offer a solution in this situation, but the current and voltage sharing are a significant
concern. Paralleling the converters rather than the power devices is an alternative
option. Better energy utilization and ripple cancellation are provided by the inter-
leaving concept. With a rise in phase count, the ripple content of the LED voltage
and input current decreases. The need for passive elements grows as the number of
phases rises, which raises the cost of implementation. Thus, the number of phases has
been decided upon in accordance with the complexity of the plan, cost, and number
of phases. These considerations led to the decision to use two stages in this situation.
Figure 1 displays the circuit diagram of interleaved cuk converter.
Mode 1: In this mode the inductor current I L1a and I L2a grow and decrease expo-
nentially as a result of the switch Q1 being closed and Q2 being open, as well as the
D1 diode and D2 becoming open and closed, respectively.
Mode 2: In this mode the inductor current I L1a and I L2a is rapidly decreasing
and increasing, respectively, as a result of the switch Q1 being open and Q2 being
closed, as well as the diode D1 and D2 becoming reverse biased and forward biased,
respectively.
Fig. 1 Interleaved non-inverting cuk-converter

2.1 CCM
The design equations of interleaved non-inverting cuk converter in CCM mode are
as follows.
Duty cycle
VL E D
D= (1)
VL E D − Vs
Average inductor currents
P0
IL1 = (2)
−VL E D
Vs
IL2 = (3)
R
Change in inductor currents.
20
ΔI L 1 = ∗ IL1 (4)
100
20
ΔI L 2 = ∗ IL2 (5)
100
Inductor values
Vs ∗ D
L1 = (6)
ΔI L 1 ∗ f s
Vs ∗ D
L2 = (7)
ΔI L 2 ∗ f s
Capacitor values
Vs ∗ D
C1 = (8)
R ∗ f s ∗ ΔVC1
VLED (1 − D)
C2 = (9)
8 ∗ L 2 ∗ ΔVo ∗ f s2
where
Vs —Supply voltage
D—Duty cycle
f s —Switching frequency
Table 1 Simulation
Parameters Values
parameters of interleaved
non-inverting cuk converter Power output, P 10 W
(CCM) Input Voltage, Vs 12 V
Duty ratio, D 0.67
Switching frequency, f s 30 kHz
Inductance, L 1 and L 2 1.59 and 2.15 mH
Capacitance, C1 9 µF
Capacitance, C2 1.7 µF
Output Load, R 57.6 Ω
VLED —LED voltage

L 1 and L 2 —Inductors
C1 and C2 —Capacitors.
Matlab/Simulink, the recommended interleaved non-inverting converter in CCM
is simulated based on these design equations for the simulation parameters that are
displayed in Eqs. 1–9 (Table 1).
The following Figs. 2, 3 and 4 demonstrates the waveform of LED voltage and
current, and stress of switch CCM interleaved non-inverting cuk converter.
The LED voltage is 25.3 V with voltage ripple of 0.004 V.
The LED current is 0.46A with current ripple of 0.0015A.
The voltage stress is 39 V, and the current stress is 3.9A.
2.2 DCM
The design equation of cuk converter DCM is as follows.

Inductor values
Vs 2 ∗ D
L 1c = (10)
P ∗ fs
(1 − D) ∗ R
L 2c (11)
2 ∗ fs
The inductor and capacitor values are derived from the critical value equations of
inductor and capacitor. The simulation parameters of Cuk converter DCM from the
design Eqs. (10)–(11) are as follows.
Matlab/Simulink, the recommended interleaved non-inverting converter in DCM
is simulated based on these design equations for the simulation parameters that are
displayed in Eqs. 10 and 11. The following Figs. 5, 6, and 8 display the waveform of
LED voltage and current, and stress of switch CCM interleaved non-inverting cuk
converter.
Fig. 2 LED voltage waveform of NICC (CCM)
The LED voltage is 24.3 V with voltage ripple of 0.0019 V.

The LED current is 0.4 A with current ripple of 0.0019A.
The continuous and discontinuous waveforms for the inductor currents in an
interleaved non-inverting cuk converter is demonstrated in Fig. 7a, b. Therefore, the
proposed converter is working in DCM mode (Fig. 8).
The voltage stress is 38 V, and current stress is 2.39 A.
3 Comparative Analysis
Performance parameters like voltage and current ripple, efficiency and voltage and
current stress for conventional cuk, non-inverting cuk, and integrated cuk-sepic are
compared and inferred. These parameters are calculated by waveforms that are
simulated in matlab. The examined LED driver topologies for comparative analysis
are
Fig. 3 LED current waveform of NICC (CCM)
Fig. 4 V & I stress of interleaved non-inverting cuk converter (CCM)

Fig. 5 LED Voltage waveform of interleaved non-inverting cuk converter (DCM)
1. Conventional Inverting DC/DC CUK LED driver

2. Non-inverting DC/DC CUK LED driver
3. Integrated DC/DC CUK-SEPIC LED driver
4. Interleaved Non-inverting DC/DC CUK LED driver.
It can be inferred from the voltage and current ripple comparative analysis in
Table 2 that the Cuk-Sepic Integrated converter has less ripple which satisfies the LED
driver application. From the analyses, it can be concluded that the proposed inter-
leaved topology has improved performance than the other examined LED drivers and
hence is highly preferred for LED applications. Therefore, Interleaved cuk converter
topology is chosen for further analysis and implementation.
From Fig. 9 it can be inferred that for Interleaved cuk converter the efficiency is
greater than other topologies.
From Figs. 10 to 11 it can be observed that the current stress is least for the
proposed interleaved topology.
Fig. 6 LED current waveform of interleaved non-inverting cuk converter (DCM)
From the analyses, it can concluded that the proposed interleaved non-inverting
cuk LED driver has better performance than the other topologies and hence is highly
preferred for LED applications. Therefore, Interleaved cuk converter topology is
chosen for further analysis and implementation.
4 Optimization of Ripple Using ANN
The Neural Network controller, which essentially uses nonlinear control principles,
significantly improves system efficacy. Additionally, it improves system functionality
and reduces system problems. Neural networks’ self-adjusting abilities allow them to
modify system parameters like variations, uncertainties, and non-linearities. Several
applications are required for the artificial neural network controller topology design.
The number of inputs and outputs for each layer’s neurons is roughly equivalent
(a)
(b)
Fig. 7 Inductor currents of interleaved non-inverting cuk converter (CCM and DCM)
Fig. 8 V & I stress of interleaved non-inverting cuk converter (DCM)

Table 2 Cuk converter

Parameters Values
simulation parameters (DCM)
Power output, P 10 W
Source Voltage, Vs 12 V
Duty cycle, D 0.67
Operating frequency, fs 30 kHz
Inductor, L 1 1 mH
Inductor, L 2 100 µH
Capacitor, C1 9 µF
Capacitor, C2 20 µF
Output Load, R 57Ω
Fig. 9 Efficiency Efficiency

95% 92%
88% 88%
90% 85%
85%
80%
Conventional Non-Inverting Interleaved Cuk-Sepic
Cuk Cuk Cuk Integrated
Fig. 10 Voltage stress Voltage stress (V)

across the switch in DCM
mode Cuk-Sepic Integrated 26.57
Interleaved Cuk 37.1
Non-Inverting Cuk 38.87
Conventional Cuk 38.398
0 10 20 30 40 50
Fig. 11 Current stress in Current stress(A)

switch DCM mode
Cuk-Sepic Integrated 1.5

Interleaved Cuk 2.8
Non-Inverting Cuk 3
Conventional Cuk 3.311
0 1 2 3 4
to the number of inputs and outputs for connection control signals used to create
the structure. The recommended network has a (3–2–1) number of neurons as its
structural design, depending on how many (neurons) are present in each layer of the
suggested artificial neural network controller structure.
The LED voltage ripple depends on passive components like inductor L 2 , filter
capacitance C2 , and switching frequency f s as shown in Eq. 12. Therefore, any
variation in these parameters affect the LED voltage ripple considerably. As multiple
parameters affect the LED voltage ripple, it is better to use a neural network to
optimize it.
V0 (1 − D)
ΔV O = (12)
8 ∗ L 2 ∗ ΔC2 ∗ f s2
Figures 12, 13, and 14 show the variation of the LED voltage ripple versus the
switching frequency, inductor, and capacitance for same duty cycle and LED voltage.
Fig. 12 LED voltage ripple

versus operating frequency

versus inductance

versus capacitance
Fig. 15 Architecture of ANN prediction model
The above figures show that the ripple value is reduced when the frequency, capac-
itor, and inductance values are increases. The data extracted from these Figs. 12, 13,
and 14 is used to formulate the data required to build the ANN. Then the architecture
of ANN predicted model with 3 inputs and the single output is depicted in Fig. 15.
The inputs for this model are operating frequency f s , inductor, and capacitors.
The relationship between the network output and the associated targets was exam-
ined using regression. The correlation between experimental and ANN predicted
values for ripple is shown in Fig. 16. It demonstrates an excellent fit between ANN
predicted values and the observed data.
The ripple obtained from ANN was lower for a specific inductor and capacitor
value as listed in Table 3 with the operating frequency of 30 kHz, and when these
values were used in the simulation circuit, it was observed that the ripple had been
further reduced and the inductance value is also reduced from the value prior to
optimization. Table 4 depicts the values before and after comparison that have been
recorded and tabulated. These optimized results are useful to implement the hardware
setup.
Fig. 16 Regression plots of ANN using MATLAB
Table 3 Performance parameters computation

Topology/Parameters Output voltage Output current Switch voltage Switch current
ripple (V) ripple (A) stress (V) stress (A)
Conventional Cuk CCM 0.004 0.004 36.8 3.31
DCM 0.021 0.021 38.39 3.14
Non-inverting Cuk CCM 0.04 0.04 36.311 1.5
DCM 0.022 0.022 38.87 3
Cuk-Sepic CCM 0.04 0.04 26.57 1.75
integrated DCM 0.015 0.015 24.5 4.15
Interleaved CCM 0.004 0.0015 39 3.9
non-inverting Cuk DCM 0.0019 0.0019 38 2.39
Table 4 Comparison before and after optimization (ANN)

Before optimisation After optimisation
L 2 = 200 µH L 2 = 100 µH
C2 = 20 µF C2 = 20 µF
f s = 30,000 Hz f s = 30,000 Hz
LED voltage ripple = 0.019 V LED voltage ripple = 0.008 V
LED current ripple = 0.019 A LED current ripple = 0.004 A
5 Conclusion
A novel interleaved non-inverting DC/DC CUK LED driver is proposed in this paper.
The performance parameters of the LED driver is compared with the existing ones
like conventional inverting DC/DC CUK, non-inverting DC/DC CUK, and positive
output DC/DC CUK-SEPIC integrated topologies in both CCM and DCM. From
the results, it is concluded that the interleaved non-inverting LED driver in DCM
mode has reduced LED voltage ripple, enhanced efficiency, and reduced device
current stress. To reduce the ripple further, the ANN method is used to find the opti-
mized values of inductor and filter capacitance by varying duty cycle and operating
frequency. Therefore, the LED current and voltage ripple after applying ANN method
are reduced due to the prediction of exact inductance and capacitance values. More-
over, the projected comparative study will be useful to design a ripple free, reduced
stress, and highly efficient converter for LED applications.
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5305
PV Partial Shading for Interleaved
Quadratic High-Gain DC–DC Converter
M. Premchand and Swati Devabhaktuni
Abstract High-gain DC–DC converters are the most trending power converters for
Photovoltaic (PV) applications. The output voltage of the photovoltaic panel is very
low. The conventional boost converter is limited to gain 4. The high-gain DC–DC
converter will provide a large range of gain so that we can easily step the voltage to
higher voltage. The newly proposed quadratic interleaved quadratic converter will
provide a gain of nearly 42 gain. This high-gain converter is suitable for high-voltage
and less current applications. The efficiency of this converter is 90%.
Keywords PV panels · High-gain DC–DC converters
1 Introduction
Renewable energy sources are increasing day by day. Renewable energy will
contribute 30% of the total production of power in India. The solar PV panel will
produce nearly 100 GW in the year 2022 (India). The solar PV panel will contribute
60% of power in total renewable power. The output voltage of PV panel is nearly
10 V. The output voltage panel of PV module depends on the module. There are
different types of modules and these are (1) monocrystalline silicon, (2) polycrys-
talline silicon, (3) amorphous silicon, and (4) concentrated PV cell. The concentrated
PV cell have higher efficiency and higher performance rate. The conventional boost
converter is limited to gain 4. After gain 4, the efficiency will come down drastically.
M. Premchand (B) · S. Devabhaktuni

Electrical Department, NIT Warangal, Warangal, Telangana, India
S. Devabhaktuni
238 M. Premchand and S. Devabhaktuni
This topology will boost the voltage to a higher value with good efficiency. This
paper describes the new topology of interleaved high-gain DC–DC converter. In this
paper, we will be discussing the different modes of operation, voltage gain, voltage
and current stress, design of components, and open-loop and closed-loop results.
2 High-Gain DC–DC Converter
The high-gain DC–DC converter will advance the version of boost converter. This
converter is of two types. They are isolated and non-isolated. The isolated converter
consists of transformer. The transformer-based converter is used for stepping up the
high voltage. In this converter, a coupled inductor is used and reset is done in every
cycle. The resetting of core is important because of transformer may get into deep
saturation mode. Due to this complexity in the isolated converter, the non-isolated
converter is more preferred. The new proposed converter will have a maximum
gain of 42. The 10 V DC voltage will have a maximum output voltage of 420. As
the converter is giving 42, it is called a quadratic converter. The interleaved means
paralleling of two converters. So, this is called interleaved quadratic non-isolated
converter [1] (Fig. 1).
3 Interleaved Quadratic Non-isolated Converter
The newly proposed interleaved quadratic converter is used for mainly solar PV
Applications. The converter consists of two inductors, L 1 , L 2 ; two MOSFET switches,
S 1 , S 2 ; three capacitors, C 1 , C 2 , C 3 ; three diodes, D1 , D2 , D3; and load resistance, R.
The converter is shown in Fig. 2.
Fig. 1 Efficiency versus duty ratio—boost converter

PV Partial Shading for Interleaved Quadratic High-Gain DC–DC Converter 239
Fig. 2 Interleaved quadratic non-isolated converter
4 Operating Analysis of Converter
There are four modes of operation present. The time interval is divided into four
parts (t0–t4).
4.1 Mode 1—[T0 –T1 ]
During this mode, both switches, S 1 , S 2, are on. Both inductors, L 1 , L 2, are charging.
The initial charge present across the capacitor is supplied to the load and the diode
current present across the load will be decreasing [2].
4.2 Mode 2—[T1 –T2 ]
During this mode, both switches, S 1 , S 2, are on. Both inductors, L 1 , L 2, are charging.
The diode across the load is reverse-biased. The output capacitor will supply the load
[3].
4.3 Mode 3—[T2 –T3 ]
During this mode, switches, S 2 , S 1, are off. The input current will split into two ways.
One way is through inductors L 1 and L 2 . One current will flow from inductor L 1 ,
capacitor C 1, and diode D3 . The inductor current L 2 will discharge and supply the
current to the load. It will flow into output diode and load [4].
4.4 Mode 4—[T3 –T4 ]
During this mode, switches, S 2 , S 1, are off. Both inductors, L 1 , L 2, are discharging.
The diode across the load is reverse-biased. The output capacitor will supply the load
[5].
5 Analysis of the Converter
The proposed converter has inductors, capacitors, diodes, and switches. We are
neglecting resistance from both inductors and capacitors. We are considering Rds
= 0.03 and voltage drop across the switches is negligible.
5.1 Voltage Gain of Proposed Converter
This converter has a wide range of gains. The gain will vary according to the duty
ratio [6].
Vm |sin wt|D
I pk = (1)
L m fs
The voltage gain plays a very vital role in the converter.
VDC
VC1 = (2)
(1 − D)
[2 − D]VDC
VC2 = (3)
(1 − D)

3 − 3D + D 2 VDC
VC3 = (4)
(1 − D 2 )
The output voltage Vo

5 − 4D + D 2 VDC
Vo = (5)
(1 − D 2 )

Vo 5 − 4D + D 2 VDC
M= = (6)
VDC (1 − D 2 )
The voltage gain of discontinuous current mode is like the continuous mode. The
voltage across the capacitors C 1 and C 2 are similar in CCM and DCM. The switch
will conduct from 0 to D duty cycle. The switch will take some time from coming
D to Do .
The output voltage across capacitor C 1 .
[3Do + D(2 − D − D0 )]VDC

VC1 = (7)
(1 − D)D0
The output voltage across capacitor C 3 (Fig. 3).
[Do (5 − 3D) + D(4 − 2D)]VDC

VC3 = (8)
(1 − D)Do
The change in duty ratio Do
[D(4 − 2D)]VDC
Do = (9)
[(1 − D)Vo (5 − 3D)]VDC
The peak current of inductor L 2
D(2 − D)VDC
i L2 = (10)
(1 − D)L 2 f s
The output current will depend on the inductor peak value.
Do i L2
Io = (11)
2(D − Do )
The voltage gain in the discontinuous mode will be
Fig. 3 Gain versus duty ratio—proposed converter

Vo [5 + 1 + (2D R/2(1 + D)/L 2 f s ]

M= = (12)
VDC (1 − D 2 )
5.2 Voltage and Current Stress Analysis
The voltage and current stress should be minimal so that it can bear the high voltage
and current [7].
The voltage across switch S 1
Vo
VS1 = (13)
(5 − 4D + D 2 )
The voltage across switch S 2
(1 − D)Vo
VS2 = (14)
(5 − 4D + D 2 )
The voltage across switch D1
(1 − D)Vo
VD1 = (15)
(5 − 4D + D 2 )
The voltage across switch D2
(2 − D)Vo
VD2 = (16)
(5 − 4D + D 2 )
The voltage across switch D3 (Fig. 4)
(2 − D)Vo
VD3 = (17)
(5 − 4D + D 2 )
5.3 Design of the Components
The design of the components in converter is important. The inductance will vary
with the duty cycle so that we need to design the converter. The min inductance and
capacitance need to be changed properly. The inductance value will vary according
to duty ratio [8].
Fig. 4 Voltage stress—proposed converter
The min inductance of L 1

D (1 − D)4 R
L 1 min = (18)
2 f s ([4 − D(3 − D)][5 − D(4 − D)])
The min inductance of L 2

D(2 − D) (1 − D)2 R
L 2 min = (19)
2 f s [5 − D(4 − D)]
The capacitor needs to change design properly for charge and discharge. The
design for Capacitor 1
[4 − D(3 − D)]i o
C1 = (20)
(1 − D)δV C1 f s
The design for Capacitor 2
io
C2 = (21)
δV C2 f s
The design for Capacitor 3
Di o
C3 = (22)
δV C3 f s
For the capacitor design, voltage ripple value will be present in every formula because
we have to decide how much ripple voltage is allowed. Usually, we allow a maximum
voltage ripple of 5%.
Table 1 Parameter values

S. No Parameters value Of proposed topology
Number Parameter Values
1 Input DC voltage V 25 V
2 Inductor value L 1 100 µH
3 Inductor value L 2 200 µH
4 Capacitor value C 1 180 µF
7 Frequency 50 kHz
8 Duty ratio 70%
9 Output voltage 440 V
The input voltage V DC is usually 10–30V. The gain of the converter is shown in
Fig 3. The output voltage is decided on the duty ratio. The inductor design mostly
can take 5 times the min inductor value.
The capacitor design mostly can take 10 times the min capacitor value. Inductor
L 1 = 100 µH, L 2 = 200 µH, and L 3 = 100µH will suit for most of the duty ratio.
Capacitor value C 1 = 180 µF, C 2 = 180 µF, and C 3 = 22 µF will work for most of
the duty ratio (Table 1).
6 Open-Loop Results of the Proposed Converter
The converter will consist of switches, diodes, inductors, and capacitors. The non-
linearity of inductors and capacitors will cause losses. Both switches have Rds =
0.02. The diode also has on-state voltage drop. All these components will contribute
losses to the converter [9].
The efficiency of the converter is 90%. From Fig 6, the contribution of losses
will be from switching losses mostly (MOSFET) and some minute losses from R,
L, C components. The switching losses are directly proportional to the frequency.
The input power is 400 W, There will be more switching due to higher frequency
(50 KHz). Inductor L1 has a peak current of 50 A with a time interval of 0.01 s. The
inductor current waveform will be triangular. The current moves from 10 to 14 A in
steady state. The inductor current will vary according to input voltage and duty ratio.
With the increase in the duty ratio, the output voltage also increases. More inductor
current will occur for higher duty ratio. Inductor L 2 has a peak current of 25 A with a
time interval of 0.01 s. The inductor current waveform will be triangular. The current
moves from 2 to 7 A in steady state [10] (Figs. 5 and 7).
Capacitor C 1 has a peak voltage of 110V with a time interval of 0.01 s. The
inductor current waveform will be constant. The capacitor voltage in steady state
Fig. 5 Output voltage and input voltage—proposed converter
Fig. 6 Output and input power—proposed converter
Fig. 7 Current across inductor and voltage across capacitor—proposed converter

Fig. 8 Diode current and switching sequences—proposed converter
is 100 V. The capacitor voltage will vary according to input voltage and duty ratio.
Capacitor C 2 has a peak voltage of 90 V with a time interval of 0.01 s. The inductor
current waveform will be constant. The capacitor voltage in steady state is 80 V.
Capacitor C 3 has a peak voltage of 450 V with a time interval of the 0.01 s. The
inductor current waveform will be constant. The capacitor voltage in steady state is
445 V[11].
Input power Pi is 400 W and output power Po is 360 W. The efficiency is Po /Pi
= 360/400 = 90%.
Diode D1 has a peak current of 20 A with a time interval of 0.01 s. The diode
current waveform will be triangular from 0 to on time, in off time the diode current
will be zero. The diode current moves from 0 to 4 A in steady state. Diode D2 has a
peak current of 20 A with a time interval of 0.01 s. The diode current waveform will
be triangular from 0 to on time, in off time the diode current will be zero. The diode
current moves from 0 to 4 A in steady state.
Diode D3 has a peak current of 50 A with a time interval of 0.01 s. The diode
current waveform will be triangular from 0 to on time, in off time the diode current
will be zero. The diode current moves from 0 to 15 A in steady state. The switching
sequence will be supplied from the pulse generator. The pulse generator has a duty
ratio of 70% with f s 50 KHz [12] (Fig. 8).
7 PV Partial Shading for the Proposed Converter
The solar PV panel will have variable voltage because it is connected to different
sets of panels which consists of various combinations of series and parallel. The
solar PV panel will depend on the irradiance and temperature. The PV panel mainly
depends on the open-circuit voltage (V oc ) and short-circuit current (I sc ). The open-

circuit voltage is directly proportional to the irradiance. The open-circuit voltage will
increase with decrease in temperature [13].
The PV panel output voltage will have variable voltage due to variable irradiance
and temperature. This phenomenon is called PV partial shading. The shading of
PV panel will cause the flow of reverse current across the panels. To avoid the
reverse flow of current, diodes are placed. The output voltage of PV partial shading
is non-regulated DC; to make it regulated, closed-loop operation is performed [14].
The output voltage of PV panel will vary according to irradiance and temperature.
Three PV panels are taken with different irradiances and temperatures. The first PV
panel has an irradiance of 1 KW/m2 and a temperature of 25 °C.
The second PV Panel has an irradiance of 0.6 KW/m2 and a temperature of 25 °C.
The third PV panel has an irradiance of 0.4 KW/m2 and a temperature of 25 °C. The
total voltage across array is a combined voltage across each panel. The maximum
power is obtained from the total voltage and current across array. The change in
voltage and power is considered so that, based on the error in voltage and power,
duty cycle is considered. If error in power is positive, the duty cycle will increase
for positive error voltage and duty cycle will decrease for negative error voltage. If
error in power is negative, the duty cycle will decrease for positive error voltage and
duty cycle will increase for negative error voltage.
The duty ratio is generated from the MPPT algorithm. This method is called
incremental MPPT algorithm. Duty cycle is given to the PWM controller. The primary
goal of the PWM controller is to generate pulses for switches. There are two types
of PWM. They are (1) Square PWM and (2) Triangular PWM. The square PWM has
higher fundamental value but the ripple content will be more. The triangular PWM
will have less ripple content, so it is preferred more. The output of the triangular
PWM is given to switches S 1 , S 2 .
7.1 Partial Shading Operation for the Proposed Converter
The PV partial shading is integrated into the converter. The output voltage from the
PV partial shading is 40 V. The 40 V voltage is given to the DC–DC converter. The
MPPT converter will generate duty cycle. The MPPT will generate according to the
error in voltage and power. The maximum duty ratio is D = 0.7 and the minimum
duty ratio is D = 0.6. Then it is given to the PWM DC generator. The frequency of
the PWM generator is 50 KHz. It will generate a duty cycle of 0.6–0.7. According
to the gain versus duty ratio, the gain will be around 15 and the output voltage will
be around 600 V [15].
The peak current across L1 in open loop is 14 A but, in partial shading, the peak
current is increased to 80 A. The peak current across L2 in open loop is 10 A but, in
partial shading, the peak current is increased to 40 A. The voltage across C1 in open
loop is 100 V but, in closed loop, the voltage is also 100 V. The voltage across C2 in
open loop is 60V but, in closed loop, the voltage is increased to 90 V.
The peak current across D1 in open loop is 4 A but, in partial shading, the peak
current is increased to 80 A. The peak current across D2 in open loop is 4 A but, in
partial shading, the peak current is increased to 50 A. The peak current across D3 in
open loop is 12 A but, in partial shading, the peak current is increased to 100 A [16].
The peak current across L1, L2, D1 , D2 , D3 is increased in the closed loop when
compared to the open loop. The voltage across capacitor will change according to
the output voltage (Figs. 9 and 10).
The input voltage to the converter is 40 V. The gain of the converter is 42. The
maximum voltage allowed is 1050 V. The output voltage will vary from 50 to 1050 V.
The large range of voltage will be reflected on the output side. The main aim of this
partial shading is to obtain the desired voltage by varying duty cycles. The desired
voltage can be integrated into DC grid. The DC grid has various applications in
electric vehicles (vehicle to grid, Grid to vehicle, battery charging, high efficiency
household applications, and renewable energy source) [17].
Fig. 9 Output voltage in the closed-loop operation
Fig. 10 Current across inductors and voltage across capacitors

Table 2 Output voltage

S. No Converter parameters
Number Output voltage (V) Response time (s) Output ripple %
1 400 0.4 0.8
2 500 0.28 0.83
3 600 0.22 0.9
4 700 0.19 1.4
5 800 0.12 1.75
6 900 0.11 2.05
7 1000 0.1 2.1
The output voltage 600V has a gain of 15. The closed-loop response time is 0.22
s and has a ripple of 0.9%. The output voltage is inversely proportional to response
time; with increase in the output voltage, the response time decreases. The output
voltage is directly proportional output ripple percentage; with increase in the output
voltage, the output ripple percentage decreases. The optimal voltage is 400–600 V
so that output voltage ripple will be less but the response time can be reduced with
advanced controller. The MPPT can integrated with PI (Table 2).
Controller, but PI Controller will have sluggish performance towards response
time due to the presence of integral controller it will collect the past data and try to
remove that data, so due to this PI controller have sluggish performance.
The Advanced Controller like Fuzzy Controller, Artificial Intelligence Tech-
niques. The fuzzy controller can decrease the response time because this controller
will have a set of rules defined like negative big, negative small, zero big, positive big,
positive small. The artificial intelligence and neural network will track the reference
very keenly so that error can be removed. The trend of machine learning and artificial
intelligent techniques is increasing.
8 Conclusion
In this paper, The proposed converter will boost the voltage with a gain of 42. The
efficiency of the converter is 90%. The output power of the converter is 360 W. The
converter is mainly suitable for the PV panel applications. The converter can support
the PV partial shading and closed-loop operation. The partial shading of the converter
also supports with a gain of 42. The response time in this operation for this converter is
inversely proportional to output voltage. The output voltage ripple percentage in this
operation for this converter is directly proportional to output voltage. The converter
can operate in closed loop.
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Investigation on Modified Bridgeless
SEPIC PFC Converter Topology
for Battery Charging Application
Sridhar Makkapati, N. Chitrapavai, and Seyezhai Ramalingam
Abstract An amazing alternative to traditional internal combustion engine-based

automobiles is electric mobility. The main barrier to the growth of electric mobility is
the lack of grid-friendly charging stations and the restricted availability of charging
infrastructure. The essential component for recharging the onboard batteries and
powering the vehicle is the charging infrastructure. The majority of traditional Elec-
tric Vehicle (EV) chargers consume distorted line current and have poor power
factors, which strains the environment at the end of the power distribution chain.
The nonlinear loads call for an improvement in the grid’s power quality. A survey on
different SEPIC-based PFC converter topologies both with continuous and discon-
tinuous modes are carried out and based on their demerits a modified SEPIC AC-DC
PFC converter with reduced output current ripple and enhanced efficiency is proposed
for electric vehicle charging application. In this paper, a detailed explanation of its
design and simulation framework is presented. Various functional parameters such
as supply current THD, supply PF, supply DF, semiconductor stress, efficiency, and
output ripple of the suggested converter are computed and compared based on their
simulation study.
Keywords PFC converter · Electric Vehicle (EV) · SEPIC converter · Total

Harmonic Distortion (THD)
1 Introduction
The global market for electric vehicles (EVs) is expanding primarily due to rising
pollution levels and the demand for environmentally friendly transportation methods.
However, the lack of adequate infrastructure for charging a battery and its technology
mostly prevents its progress. A power conversion interface that is essential to charge
makes up most of the Charging Technology (CT). They must adhere to international
standards for power quality and safety. Typically, a CT has a power modulator of
S. Makkapati (B) · N. Chitrapavai · S. Ramalingam

Sri Sivasubramaniya Nadar College of Engineering, Kalavakkam, Chennai 603110, India
252 S. Makkapati et al.
different configurations at the battery end and a rectifier section on the front end.
The front-end rectification is utilized to transform the AC supply into an unregulated
DC, and the power modulator is used to regulate the voltage and/or current at the
load side to control battery charging. Unfortunately, such solutions in the literature
run at a very low power factor and pull a distorted current with significant current
Total Harmonic Distortion (THD) from the supply.
The power modulator, i.e., the power converter from the utility grid should
exhibit a unity power factor. Several topological solutions are presented in [1–3]
as PFC solutions to enhance efficiency in bridgeless configurations. In [4] system-
atic configurations are presented with bridgeless (BL) boost; however, it has several
issues like isolation and high inrush current during startup. Though the discontinuous
conduction provides inherent PFC it also produces higher current stress.
Several SEPIC bridgeless solutions are suggested [5–10], though the presented
solutions have continuous input current, they have inherent merits and demerits. In
[5] the converter is identified with a drawback of conduction of too many components
during each switching period. In [6] the components are reduced to a greater extent,
but the inductors employed are not coupled. Therefore, the current stress is more
compared to the conventional SEPIC solution. In [7] bridgeless solution is presented
with increased efficiency; however, the suggested topology exhibits higher circu-
lating currents and higher input noise. Another solution in [8] many benefits of this
setup include the lowest component count and straightforward isolation. Its principal
drawbacks include strong EMI noise and a lack of coupling inductor function.
A solution of Step-Down Bridgeless SEPIC configuration for charging applica-
tions is proposed in [11]. Switched inductor SEPIC converter with a single-stage
configuration had been utilized, to attain desired DC gain, which is used to provide
a single-stage charger configuration without any isolation.
In [12] a two-stage battery charging solution is suggested. The first stage of
the charger has characteristics of high voltage conversion ratio and unity power
factor operation, and both were achieved by a bridgeless high gain SEPIC converter.
Another bridgeless solution for charging applications with better power quality
parameters is focused in [13]. Elimination of the diode bridge rectifier and the conduc-
tion losses are greatly reduced. From various literature surveyed, most standard EV
chargers show distorted line current at low power factor which pollutes the power
distribution end. Therefore, this paper presents a modified bridgeless SEPIC topology
for the Electric vehicle charging infrastructure. The proposed one operates with the
discontinuous operation to exhibit the inherent power factor correction. Section 2
presents the operation with its modes and design equations. Section 3 elaborates the
simulation framework and comparison of functional parameters with the existing
solutions.
Investigation on Modified Bridgeless SEPIC PFC Converter Topology … 253
2 Modified Bridgeless SEPIC (MBL-SEPIC) Topology
In this study, a Modified BL-PFC rectifier is proposed and is presented in Fig. 1,

adding the additional inductors L01, and L02, and an additional diode is embedded
for the suggested topology. Under steady-state operation, the circuit operates in two
modes of operation during the positive half cycle. Its corresponding circuit operation
is shown in Figs. 2 and 3, respectively.
2.1 Operating Modes
Mode 1. The MOSFET S1 switches on at this moment. The inductor currents iL1
and iL01 thereby cause the diode Dp to be forward biased. By the voltages (V in +
V 0 ) and V in , the diodes D1 and Dn are reverse biased, respectively. The charging
power source for the inductors L 1 and L 01 is provided by the voltages V in and V C1 . In
D1
C1
L1
C2 D2
V in
Co L
O
L2 L 01 A
S1 S2 L 02
Dp Dn D
Fig. 1 Circuit diagram of modified bridgeless SEPIC topology
D1
iL01
C1
i0
L1
C2 D2
Vin
Co L
O
L2 L01 A
S1 S2 L02
Dn Dp D
iL1
Fig. 2 Operation mode-1

D1
C1
L1 iL01
iL1 C2 D2
Vin
Co L
iL01
O
L2 L01 A
S1 S2 L02
Dn Dp D
iL01
iL1
iL1
Fig. 3 Operation mode-2
accordance with the input voltage V in , inductor currents iL1 and iL01 linearly increase.
The corresponding current path in this mode is shown in Fig. 2.
Mode 2, MOSFET S 1 is in OFF state in this stage of operation and the output
diode D01 is in conduction due to the inductor current iL1 , iL01 . The sum of currents
iL1 , and iL01 pass through the output diode (D1 ) and diode (Dp ). The voltage across
inductors L 1 and L 01 is same as the output voltage. The corresponding circuit diagram
and its current paths are shown in Fig. 3.
2.2 Design Equations
The following are the design equations of the MBL-SEPIC PFC converter in
discontinuous conduction mode. The duty cycle is obtained from
Vo
D= (1)
Vo + Vin
The primary inductors L 1 and L 2 are obtained as
Vin ∗ D
L1 = (2)
f sw ∗ i L1
Vin ∗ D
L2 = (3)
f sw ∗ i L2
The output inductors of L 01 and L 02 can be estimated as
L 1 ∗ L eq
L 01 = L 02 = (4)
L 1 − L eq
Table 1 Specifications of the

Parameters Suggested converter
converter
Supply voltage V m = 220
Line frequency f l = 50
Duty cycle D = 0.3
Inductors L 1 = 20 mH, L 2 = 20 mH
L 01 = 1.8 mH, L 02 = 1.8 mH
Switching frequency 25 kHz
Capacitors C 1 = 10 μF, C 2 = 100 μF
Output voltage 65 V
Output power 6.5 A
Output power 450 W
Fig. 4 Simulation circuit of MBL-SEPIC circuit
The output capacitor is obtained from the equation below. Table 1 represents the
designed values for the suggested solution. Figure 4 represent the simulation circuit
of the solution.
Prated
Co = (5)
Vo ∗ ω1 ∗ Vo
3 Simulation Framework
A 450 W model charging circuit is simulated using MATLAB/Simulink. The utility

voltage and current waveform are presented in Figs. 5 and 6, respectively. Input
voltage of 325 V peak input voltage is applied, and the input source current is nearly
sinusoidal. The circuit operates in a discontinuous conduction mode that inherently
exhibits PFC. The DCM is evident from Fig. 7.
Fig. 5 Source voltage waveform
Fig. 6 Source current waveform
Fig. 7 Discontinuous L 01 current waveform

Fig. 8 Switch voltage and current pattern
The Switch parameters are represented in Fig. 8. In most of the SEPIC circuits
the switch currents are like inductor currents. The same is also applicable in this
topology.
To meet the desired voltage and current such as 65 V and 6.5 A, respectively.
The converter presents the lesser ripple at the load side. The voltage and current
ripple at the load side are within the permissible limits. Figures 9 and 10 show the
output voltage and current waveform, respectively. Input current harmonic spec-
trum is shown in Fig. 11. The harmonic content in this topology is of 8.52% lesser
compared to the existing solution in the literature.
Ripple comparison is carried out based on the existing solution with the proposed
converter. However, the suggested modified bridgeless SEPIC converter presents a
lesser output ripple to charge the battery system (Fig. 12).
Fig. 9 Output voltage

Fig. 10 Output charging current
Fig. 11 Input current harmonic spectrum
From Table 2 it is evident that the source side functional parameters are calcu-
lated and compared with the existing solutions. The suggested Modified SEPIC
presents the better input power factor with lesser harmonic distortion at the source.
The efficiency is much improved compared with conventional SEPIC solutions. The
suggested converter meets the desired source and load requirement for the battery
charging system.
Fig. 12 Ripple comparison of conventional and proposed topology
Table 2 Comparison of functional parameters

Parameter SEPIC-CCM SEPIC-DCM SEPIC BRIDGE Suggested converter
LESS-CCM
Supply THD 15% 12% 10.42% 3.61%
Supply power factor 0.89 0.90 0.93 0.95
Distortion factor 0.06 0.08 0.09 0.08
Efficiency 78% 85% 87% 87%
4 Conclusion
This study suggests MBL-SEPIC solution with reduced power device conduction
counts throughout the switching interval. A second current path could assist in mini-
mizing circulating power loss and getting rid of unwanted circulating current. The
converter operates with a 450 W power rating driven from a single-phase 230 V AC
supply. Input side functional parameters such as harmonic distortion, and input power
factor are within the limits. A comparative study is carried out between conventional
and the suggested topologies. The modified bridgeless solution presents better results
for the charging circuit when fed from the single-phase AC source.
References
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ating at the boundary of continuous conduction mode and discontinuous conduction mode. In:
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and conduction losses. IEEE Trans Ind Electron 58(9):4153–4160
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rectifiers for PFC applications. IEEE Trans Power Electron 27(7):3292–3301
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improved power quality. IEEE Trans Ind Appl 58(5):6357–6367
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SEPIC converter. IEEE Trans Ind Appl 56(1):477–487
The Improved vµ LMS-Based Grid
Connected Solar PV System Power Flow
with Abnormal Grid and Non-linear
Load Conditions
Pavan Prakash Gupta, Ramesh Kumar Tripathi, and Shailendra Kumar
Abstract In the reported work, the two-stage grid-tied solar PV with non-linear
load is presented, with various conditions at the point of common coupling (PCC)
voltage. The non-linear load at PCC absorbs the active power and injects the reactive
power which may lead to higher THD in grid current. The various PCC voltage
profiles like normal voltage and distorted voltage due to harmonics are analyzed
and the system is simulated for, 20% SAG and 20% SWELL at PCC to test the
robustness and effectiveness of the control for presented VSC control. The improved
vμ least mean square (IvμLMS) method is presented for grid-tied VSC control
to provide good convergence, less burden, and improved dynamic responses under
various conditions at PCC. According to the IEEE-519 standard, the PV power is
fed at unity power factor (UPF) with lower total harmonic distortion (THD) for the
grid and load. On the DC-side a recent DC–DC boost converter topology with higher
voltage gain is used, this makes the smaller PV arrays and able to convert grid-tied
system. The perturb and observe (P&O) algorithm is applied to obtain the maximum
power point (MPP) operation for solar PV arrays. The grid-tied PV system and its
controls are modeled in MATLAB/Simulink environment and analyzed. The grid
current is maintained at lower THDs as per IEEE519 and at unity power factor with
different working conditions, which verifies the efficacy of the presented method.
Keywords Adaptive based control · Solar PV system · Grid-tied PV · Voltage

source converter (VSC) · Power quality · High gain DC–DC boost converter ·
Non-linear load · Least mean square algorithm
P. P. Gupta (B) · R. K. Tripathi

EED, MNNIT Allahabad, Prayagraj, Uttar Pradesh 211004, India
S. Kumar
EED, MANIT Bhopal, Bhopal, Madhya Pradesh 462003, India
262 P. P. Gupta et al.
1 Introduction
The rapid consumption of fossil fuels and day by day increasing demand of the power
generation is creating a lot of burden on the environment and pollution. Therefore, in
the last few decades, the researchers have reported renewable energy sources (RES) as
a prominent and effective alternative to power generation in an environment friendly
way for increasing power demand. These clean and contamination free RES like
solar PV (SPVs), Wind, Tidal, Hydro, etc. have lower carbon footprints and are freely
available in abundance to match the required energy demand. Among them, solar PV
(SPVs) is static, requiring less maintenance and potentially available RES around us
and thus it makes it more suitable for grid connected system [1]. In general, either
single stage (i.e., DC-AC) or double stage (i.e., DC–DC and then DC-AC) topologies
are primarily used for the grid connected SPV system. Such topologies involve the
power electronics interface for DC–DC and/or DC-AC conversions and hence play
a vital role in power control from RES to grid and load [2].
The intermittency of the SPV based power generation required maximum power
extraction during different solar irradiance conditions. The various literature reported
the corresponding maximum power point algorithms for the same, the P&O algorithm
is one of the simplest and most effective technique used in the work [3]. For two-
stage grid connected SPV system, the typical DC–DC boost converter is widely used,
however, there is a constraint of operation of boost converter at high duty ratio. The
step-up high gain DC–DC converters, both isolated and non-isolated, are one of the
remedies for these issues [4]. This limitation comes due to the parasitic present in the
passive and active elements of the converter circuit. The SPV system typically oper-
ates at low voltage levels that must be increased to the appropriate DC-link voltage for
proper inversion, i.e., DC-AC for grid connection, by using inverters. Therefore, it is
required to use a high gain step-up DC–DC converter either isolated or non-isolated
configuration for proper conversion [5]. The non-isolated configuration has its advan-
tage over the isolated configuration and hence it can be used for DC–DC stage. In
[6], a non-isolated topology of a step-up DC–DC converter with higher voltage gain
is reported and compared to use in renewable applications. The topologies have key
benefits, which include improved voltage gain at lower duty ratios, less voltage stress
across active switches, and suitability for smaller PV array deployments on residen-
tial rooftops, which enables grid connectivity. A three phase voltage source converter
(VSC) is used and synchronized for grid connection after the DC–DC conversion
stage which maintains the MPP operation. Numerous time and frequency domain-
based control techniques have been published by researchers. For grid connected
VSC control, usually heavy computation burden occurs for digital controllers with
frequency domain techniques, also it involves larger sampling time for decomposition
of harmonics [7]. Since time domain methods are suitable for grid connected systems,
real-time digital controllers are frequently incorporated into hardware implementa-
tion. The traditional time domain techniques such as synchronous reference frame
theory (SRF), instantaneous active-reactive power (p-q theory) theory, instantaneous
symmetrical component theory, etc. involve transformations [8–10]. Although, both
The Improved vμ LMS-Based Grid Connected Solar PV System Power … 263
methods have efficient PQ solutions for a balanced grid, a pricey digital controller is
necessary for hardware implementation. For distorted grid p-q theory-based controls
generate both real and imaginary power components due to harmonics in grid refer-
ence currents. During the harmonic compensation process, these real and imaginary
components get processed and result in unwanted harmonics of higher order. With
unbalanced load condition, the SRF method not perform well. A low pass filter
(LPF) is required to introduce to mitigate second harmonics in d-axis component,
which also results in poor dynamics. Such drawbacks can be resolved by using
an adaptive control-based notch filter [11], with noise cancellation [12], frequency
observer etc. [13]. These controls provide good harmonic compensation but have
slow adaption process, which may delay the system response. To mitigate such
drawbacks, some researchers have presented other learning behavior-based adaptive
control algorithms with constant and/or variable step sizes. Such controls involve
linear statistical estimation techniques to obtain optimal solution but during real-
time application, it creates high computational burden. This issue can be handled
by adaptive filters, which are based on approximate iterative algorithms such as
least mean square (LMS), least mean fourth (LMF), leaky least logarithmic abso-
lute difference, gradient search-based methods, etc. [14–17]. These methods provide
fast convergence and smaller computational burden per iteration. Though, to design
accurate models these techniques need a good analytic model, the convergence speed
may slow down due to computational burden on controller, which may further affect
the speed of generation of VSC reference currents. Performance verification of the
suggested controls in both sinusoidal and non-sinusoidal grid situations is required.
Along with this, the linear and non-linear loads can be used, which may also
pollute the system operation. Generally, electric ballast, drives, printers, fax machines
computers, etc. are few examples of non-linear loads. These loads degrade the steady
state and dynamic behaviors of the system, poor power factor, uneven neutral-ground
voltage, and mal-operation of protective devices. To improve on these issues custom
power devices are required to be installed, which can source or sink the reactive
power and can mitigate power quality issues [18]. The control techniques of custom
power devices provide extraction of fundamental components, which further gener-
ates the reference grid currents [19, 20]. As a result, the dynamic and steady state
behaviors of the grid connected system can be improved by selecting an intelligent
control strategy. Some of the reported control techniques are adaptive linear neuron
(ADALINE), variable leaky least mean square (VLLMS), and adaptive notch filter
[21–24]. These adaptive filters improve the convergence speed, dynamic response,
and power quality. Although, being employed over the previous four decades, the
adaptive inverse control (AIC) provides poor convergence because of the conven-
tional LMS method [25]. The forgetting factor and symbolic function based less
computational LMS is proposed, but still it is easy to diverge [26]. The invention of a
fractional LMS algorithm is coincided with the development of fractional calculus,
but zero value instead of initial iteration-based makes it less rigorous [27]. Another
enhanced fractional LMS algorithm has also been reported [28, 29] but it has not
addressed the stability issues. Based on the previous studies and developments [30–
32], the suggested approach is an improved vμLMS (IvμLMS) with variable step
size. With this technique, the calculated LMS error modifies the variable adaptive
step size, hence providing good convergence and less computation which is explained
in Sect. 4.
The main contribution of this reported work for double stage grid-tied Solar PV
system are as follows:
(1) A recent step-up dc–dc converter topology with higher voltage gain is used to
achieve suitable DC-link voltage at DC-bus with P&O based MPP operation of
solar PV array of smaller in size.
(2) The smaller size PV arrays are often installed on small house rooftops which
can also be converted into on-grid mode.
(3) An uninterruptable active and reactive power can be supplied to the connected
load and three phase-grid during the normal, distorted, sag, and swell PCC
voltage profile.
(4) With standard irradiance and temperature at solar PV, the P&O algorithm main-
tains the MPP operation at DC–DC stage for proper feed of active power demand
even during the different PCC voltage conditions.
(5) The DC-link voltage is controlled and quickly settles its actual value to the
desired reference during the various PCC voltage profiles, hence providing
smooth operation of the VSC with presented IvμLMS control.
(6) The grid current THD is also achieved as per the standard IEEE519 with non-
linear load operation; during sag-swell and distorted PCC voltage conditions.
(7) Using IvμLMS technique of grid-tied VSC, the need for separate PLL is not
required and abc-αβ-dq-abc transformations are no more required. As this
presented adaptive based technique, can extract corresponding fundamental
components from PCC to generate corresponding weights and current references
for VSC control during almost all possible conditions of operation.
Section 1 of the reported article has an introduction, while Sect. 2 contains the work
related to the schematic diagram. Sections 3 and 4, respectively, explain the HGC
DC–DC topology and the presented VSC control. Section 5 presents the simulink
results in detail. The paper is concluded in Sect. 6, followed by a list of references.
2 Schematic Diagram
Figure 1 represents the two-stage solar PV three phase three-wire grid-tied schematic.
It consists of three separate PV arrays connected with three separate step-up DC–
DC converters with higher voltage gain and three phase DC-AC VSC, interfacing
inductances, non-linear load, and three phase-grid. Three phase VSC is controlled
to distribute the RES-generated power to the grid and loads.
The presented control of VSC is able to mitigate harmonics at PCC. The IvμLMS
method provides three phase VSC control for desired power sharing and to maintain
the power quality at PCC.
Solar
Irradiance &
Temperature Ipv + -
DC-Bus
Vpv
S2
L1
Vdc iLabc
Control
S1
Algorithm
L2 Vsab VsbcVsca
P&O MPPT
Solar High Gain DC-DC Boost Converter
Irradiance &
Temperature Ipv
Vpv
S2 DC SW1 SW3 SW5 Lf PCC
L1 Link Vsa
Vdc isa
A Vsb
S1 Vdc B
Vsc isb
L2 C
P&O MPPT Interfacing iLabc isc
Solar High Gain DC-DC Boost Converter Inductor Distribution
Irradiance &
Temperature Ipv Grid
SW4 SW6 SW2 Non-Linear
Vpv Loads
S2 Voltage Source
L1
Vdc Converter
S1
L2
P&O MPPT
High Gain DC-DC Boost Converter
Fig. 1 Schematic diagram of the grid-tied PV system
3 DC–DC High Gain Boost Converter Topology
The DC–DC stage is required to do the MPPT even at the lower voltage input obtained
from solar PV array. The traditional simple boost converter has limited voltage gain
at higher duty ratio due to its parasitic, therefore, to maintain the desirable DC-link
voltage of VSC, it is required to install larger size of solar PV array.
For smaller installation of solar PV array, its lower voltage is required to boost by
higher voltage gain DC–DC converter at comparatively lower duty ratios. In [6], Fig. 2
shows step-up high gain DC–DC boost converter consisting of switched inductor and
switched capacitor topology with continuous conduction mode (CCM) voltage gain
and corresponding switch stress in (1) & (2) respectively. The [6], presented, the
CCM, DCM, and BCM analysis of this converter. The High gain converter (HGC)
and conventional boost converter voltage gain versus duty ratio graph are shown in
Fig. 3. The major advantage of using HGC is higher voltage gain which can be used
with smaller PV installations, lower power rating devices due to lesser switch stress,
lower duty ratio operation. From Fig. 2, during the switch S 1 , S 2 ON; L 1 , L 2 and DC
source will become in parallel and store the energy. The diode D1 and D2 will remain
in reverse bias and D0 conducts to feed the load from the stored energy of capacitor
C1,
C 2 and C 0 . When switches are OFF; L 1 , L 2 and DC source all three become in
series to feed the energy towards the load side, hence providing higher gain. As a
result, during this period diodes D1 and D2 are forward biased and capacitors C 1 and
C 2 store the energy. Also, diode D0 will remain reversed biased and C 0 will keep on
feeding the load from its stored energy. Hence, a continuous current mode (CCM)
of operation is achievable. The corresponding detailed mathematical modeling and
key waveforms of CCM and DCM mode are reported in [6]. The corresponding
CCM mode [6] and volt-second balance equations, result in the voltage gain of the
D0 D0
L1 S2 L1 S2 L1 S2
D1 C2 C2 D0 D1 C2
+ + +
D1
C0 R Vo C0 R Vo C0 R Vo
VDC VDC VDC
- - -
S1 S1 S1 L2
L2 L2 D2
C1 D2 C1 C1 D2
Fig. 2 Step-up high gain DC–DC boost converter topology, Switch ON and OFF mode
Fig. 3 Voltage gain versus duty ratio plots for step-up high gain DC–DC converter topologies
converter in (1),
( )
Vo 3+ D
MCCM = = (1)
VDC 1− D
( )
VDC
VS1 = VS2 = (2)
1− D
Thus, V o denotes the output voltage, V DC denotes the input DC voltage, and D is
the CCM duty cycle, V S1 and V S2 are the voltage stress across switches S 1 and S 2 .
4 Control Technique of VSC
The technique-based on improved vμ least mean square is developed in the study

that is currently being presented to extract the corresponding active power signals
from the load current. To produce good results than the least mean square (LMS)
method, the suggested control includes a variable step size parameter. The presented
method consists of the variable step size modeled with simple mathematics equations.
An improved variable step size algorithm can provide good adaptive filtering. The
presented IvμLMS technique, as shown in Fig. 4, generates the reference current to
Fig. 4 Block diagram of presented IvμLMS VSC control
regulate the switching pattern of VSC, which regulates the voltage and current at
PCC. This section explains the associated mathematical equations. The expressions
for the voltage amplitude at the grid terminal are given as,
2v Lsab + v Lsbc −v Lsab + v Lsbc −v Lsab − 2v Lsbc

v psa = , v psb = , v psc = (3)
3 3 3
/
2 2
Vt = (v + v2psb + v2psc ) (4)
3 psa
where, Vt is the peak value of voltage at the point of common coupling (PCC),
v psa , v psb are the phase voltages, and v Lsab , v Lsbc , v Lsca are the line voltages at grid
side. The calculation of corresponding unit templates of the PCC voltage can be
obtained as follows
v psa v psb v psc
u pa = , u pb = , u pc = (5)
Vt Vt Vt
The fundamental adaptive component of the non-linear load current can be

extracted using the IvμLMS technique. For phase-A, the corresponding mean square
error by the presented IvμLMS technique can be obtained as follows,
e pa (n) = i La (n) − [u pa (n) × w pa (n)] (6)
where, w pa is the fundamental weight obtained from IvμLMS and i La represents

load current for connected non-linear load. The expression for fundamental weight
can be derived as follows for phase A,
w pa (n + 1) = w pa (n) + [μ(n)e pa (n)u pa (n)] (7)
where, μ(n) is the step coefficient, the adaptive variable step size gets modulated by
the assessment of least mean square error. The updated equation is as follows:
μ(n + 1) = αμ(n) + γ p 2 (n) (8)
p(n) = βp(n − 1) + (1 − β)e2 (n) (9)
The following conditions have to be satisfied as,

⎧
⎨ μmax , μ(n + 1) > μmax
μ(n + 1) = μmin , μ(n + 1) > μmin (10)
⎩
μ(n + 1), else
In the above-mentioned equations, 0 < α < 1, γ > 0, 0 < β < 1. The

parameter γ may adjust the time of convergence and maladjustment of the algorithm.
To regulate the convergence time, the β which is exponential weight coefficient
parameter can also be used.
In order to offer the fastest convergence speed, μmax is typically chosen in such
a manner so that it is close to the non-stationary step point of the standard LMS
algorithm. In the steady state, a decision is made in accordance with the expected
maladjustment and algorithm convergence rate. The μmax range can be derived as,
2
0 < μmax < (11)
3tr (R)
As per the above-mentioned mathematical modeling, the corresponding all three

phase weights can be obtained. The average weight of the three phase load currents
is given as,
w pa + w pb + w pc
Wavg = (12)
3
Additional to it, the solar PV is intermittent in nature due to changing atmospheric
conditions, which also makes fluctuation in grid parameters. The equivalent PV feed
forward weight is used in order to sustain the power flow to inject power into the
utility grid during erratic atmospheric conditions, the PV feed forward is given as,
2Ppv
W pv f = (13)
3Vt
The corresponding total weight is derived from average weight of the load, DC-
link voltage control, and solar PV feed forward which is given as,
W P Lt = Wavg + Wdc − W pv f (14)
Now to obtain the three phase reference grid currents the total weight is multiplied
with the unit templates of each phase and these are obtained as,
∗ ∗ ∗
i sa = [W pLt × u pa (n)], i sb = [W pLt × u pb (n)], i sc = [W pLt × u pc (n)] (15)
The obtained reference currents are utilized to generate hysteresis controller based
VSC switching for PV grid-tied system. The DC-link voltage control is performed
using a PI controller, and corresponding K p and K i are tuned to obtain the smooth
control of DC-link voltage. The voltage at the DC-link capacitor has to be greater
than twice the peak grid voltage and can be derived as follows,
√
2 2VL L
Vdc - link = √ (16)
3m
5 Simulated Results
The presented system and its controls are developed and analyzed in the MATLAB/
Simulink environment. The three separate PV arrays, each of 6 kW capacity
connected to their corresponding HGCs to maintain the DC-bus voltage and also
delivered its power at MPP by P&O algorithm.
Figures 5 and 9 consist of three phase source voltage at PCC, three phase source,
load and inverter currents, DC-link voltage, PV voltage, current and power, active
power extracted from or injected to the grid, and solar irradiance. On DC–DC-side,
three separate solar PV arrays each of 6 kW maximum power are connected to three
separate high gain DC–DC boost converters, all together providing around 18 kW
PV power at DC-bus. In a simulation study of the presented grid-tied PV system,
the 20% voltage SAG occurs at PCC at instant T = 0.2–0.4 s, as shown in Fig. 5a.
From Fig.5b the instant, T = 0.6–0.8 s a 20% voltage SWELL occurs at PCC with
the same load conditions. The PCC voltage profile, non-linear load, PV irradiance,
and the grid current THDs are given in Table 1. The load current has a high THD of
17.30%, However, the presented IvμLMS based VSC control ensures the lower grid
current THD value of 3.41, 1.65, and 12.44% as per the IEEE 519 standards shown
in Fig. 5 and in Table 1.
Also, the DC-link voltage is controlled to its reference value during the sudden
occurrence of sag and swell. During the operation, with 1000 W/m2 irradiance around
18 kW maximum power generated by PV is injected into the load and grid as shown
in Fig. 6. The VSC operated in grid injection mode, and the presented IvμLMS VSC
control generates corresponding per phase and average weights shown in Fig. 7 during
normal, sag and swell PCC voltage. The weights of BLMS and presented IvμLMS
400
vs(V) 0
-400
20
is(A)
0
-20
20
iL(A)
0
-20
50
Ipv(A) Vpv(V) Vdc(V) ivsc(A)
-50
860
840
180
170
160
110
100
90
20
Ppv(kW)
18
16
0
Pg(kW)
-5
-10
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time (sec)
(a)
400
vs(V)
-400
10
is(A)
0
-10
20
iL(A)
0
-20
40
Ipv(A) Vpv(V) Vdc(V) ivsc(A)
0
-40
860
840
180
170
160
110
100
90
20
Ppv(kW)
18
16
0
Pg(kW)
-5
-10
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
Time (sec)
(b)
Fig. 5 Grid-tied PV system response during a 20% Sag and b 20% swell at PCC voltage
Fig. 6 Active and reactive powers during normal, sag and swell in PCC voltage
are compared to show the efficacy of IvμLMS. The suitable fixed step-parameter ‘μ’
in BLMS is difficult to find and it may result in higher weight oscillations with faster
dynamics which may generate improper current reference thereby deteriorating the
grid current power quality. While present IvμLMS has a variable step-parameter and
can provide a trade of between weight oscillation and dynamic response and thus
can provide much better grid current power quality. The Fig. 8 shows the grid current
THDs during normal, sag, and swell in PCC voltage.
In another case study, the 5th and 7th harmonics and other disturbances are
included in the PCC voltage to distort the PCC voltage, as shown in Fig. 9 during
instant T = 0.15–0.35 s. The presented IvμLMS control technique-based VSC
control injects the PV power to connected non-linear load and the grid. Also, the
corresponding DC-link voltage profile is controlled to its reference value shown in
Fig. 9. With the 17.30% THD load, the VSC feeds the load and also injects the rest
of the power into grid at a lesser THD of 3.29% as per the IEEE519 standard during
distorted PCC voltage. The active and reactive power is shown in Fig. 10 and it shows
that the power injected into the grid at unity power factor. The corresponding per
phase and average weight generated by the IvμLMS is shown in Fig. 11. The dynamic
response and oscillations in generated weights have been compared in Fig. 11a, b,
which reflects the robustness and efficacy of the presented IvμLMS control of VSC.
As discussed above, the presented IvμLMS provides moderate dynamics and lesser
oscillations in weights for suitable current reference generation for VSC switching
using hysteresis control. Also, the PCC voltage, grid currents, and load currents THDs
are shown in Fig. 12 which reflects that at 11.18% THD distorted PCC voltage and
17.30% THD non-linear load current, the injected grid current by VSC has a THD of
3.29%. Table 2 summarized the simulation instants, load values, solar PV irradiance,
PCC voltage profile, and corresponding grid current THD values.
Fig. 7 Comparison of a phase-A weights and b average weights generated by BLMS and IvμLMS
control during normal, sag and swell in PCC voltage
Fig. 8 THDs of grid current during normal, sag and swell in PCC voltage
400
vs(V)
0
-400
20
is(A)
0
-20
20
iL(A)
0
-20
40
Vdc(V) ivsc(A)
0
-40
850
845
840
105
G(kW/m2) Pg(kW) Ppv(kW) Vpv(V) Ipv(A)
100
180
160
20
18
16
-5
-10
2
1
0
0 0.15 0.2 0.25 0.3 0.35 0.4
Time(sec)
Fig. 9 Grid-tied PV system response during distorted PCC voltage
Fig. 10 Active and Reactive powers during distorted PCC voltage

Fig. 11 Comparison of a phase-A weights and b average weights generated by BLMS and IvμLMS
control during distorted PCC voltage
Fig. 12 PCC voltage, grid current, and load current THD during distortion
6 Conclusion
The presented work consists of the DC–DC boost converter with higher gain for grid
connected solar PV system with non-linear load. The different PCC voltage profiles
of sag, swell, and distorted voltages have been simulated and analyzed. The presented
Table 1 Load, irradiance, PCC voltage, and grid current THD at normal, sag and swell at PCC
Simulation Load active Load reactive Irradiance PCC voltage Grid current
instant power (kW) power (kVAr) (W/m2 ) profile %age THD
0.0–0.2 9.83 4.445 1000 Normal 03.41
0.2–0.4 9.83 4.445 1000 20% sag 01.65
0.4–0.6 9.83 4.445 1000 Normal 03.32
0.6–0.8 9.83 4.445 1000 20% swell 12.44
0.8–1.0 9.83 4.445 1000 Normal 03.33
Table 2 Grid current THD with distorted PCC voltage

Simulation Load active Load reactive Irradiance PCC voltage Grid current
instant power (kW) power (kVAr) (W/m2 ) profile %age THD
0.00–0.15 9.83 4.445 1000 Normal 03.76
0.15–0.35 9.83 4.445 1000 Distorted 03.29
0.35–0.40 9.83 4.445 1000 Normal 03.34
IvμLMS technique for grid-tied VSC control provides the smooth operation with
variable PCC voltage profile conditions and with non-linear load which offers higher
THD current drawl. Also, the presented grid-tied PV system with IvμLMS VSC
control has provided the reactive power support to ensure the unity power factor
operation of the grid during non-linear load and various PCC voltage profiles. The
sag, swell, and distorted PCC voltage conditions have been simulated to obtain good
DC-link voltage profile, unity power factor of grid, and lower THD of grid current as
per IEEE519 standards. The presented IvμLMS VSC control provides reactive power
support and also has fast convergence due to variable step size function. Such control
scheme can reduce the burden of complex calculation and steps on controller, also
eliminates the dependency on the use of PLL block and abc-dq-abc transformations
for grid-tied VSC. All the conditions have been simulated, compared, analyzed,
and summarized to evidence the robustness and improved performance of variable
step-parameter based presented IvμLMS control of grid-tied PV system.
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Predictive Torque Control of Five-Phase
Open-Ended Winding Induction Motor
Naresh Rayavarapu, Swati Devabhaktuni, and C. Venkata Subba Reddy
Abstract The main intention of this paper is to compare conventional predictive

torque control with the predictive torque control of stator open-ended winding five-
phase induction motor drives (PTC-C and PTC-OEWFPIM) to be distinct in terms
of the switching frequency reduction, torque and flux ripple, voltage stress, and
common mode voltage minimization. In the proposed control technique, the dual
two-level voltage source inverters enhance the output voltage levels from two to
three. Both the inverters are connected on a common DC bus link, which allows
undesired circulating common mode currents through the DC bus link, resulting in
the rise of common mode voltage (CMV) would be mitigated with the proposed
control technique. PTC-C and PTC-OEWFPIM controlled schemes are compared
at a five-phase voltage space vector structure utilizing large voltage vectors only of
individual inverters. The proposed PTC-OEWFPIM scheme was verified through
MATLAB/Simulink simulations and compared with conventional PTC-C.
Keywords Open-end winding five-phase induction machine · Conventional

Predictive Torque Control (PTC-C) · Dual 2-level inverter · Common Mode
Voltage (CMV) · Torque and flux ripple · Device switching frequency
1 Introduction
One of the popular variable speed multiphase motor drives which are extensively
researched for its minimum DC link voltage requirement of the inverter, the minimum
current drawn per phase, applied in high-power low voltage requirements like aero-
space propulsion, submarine, and traction drives are the five-phase induction motor
(FPIM) [1]. The FPIMs are reliable because of their fault tolerance and low power per
phase. A voltage source inverter (VSI) with a two-level five-leg inverter having thirty-
two subspace voltage vectors allows having a high degree of control. The subspace
vectors are further divided into two zero, ten small vectors, ten medium vectors, and
N. Rayavarapu (B) · S. Devabhaktuni · C. Venkata Subba Reddy

Department of Electrical Engineering, National Institute of Technology, Warangal, India
280 N. Rayavarapu et al.
ten large vectors [2]. Field Oriented Control (FOC), Direct Torque Control (DTC),
high-power or predictive Torque Control (PTC), and Sliding Mode Control (SMC)
are various control techniques that help to improve the performance of high-power
industrial drives. a common drive control technique based on linear controllers is
field-oriented control was implemented for drives in the 1960s as its control resem-
bles like separately excited DC motor drive. The complex structure of FOC is caused
by the inclusion of reference frame transformations, proportional-integral (PI) regu-
lators, and rotor flux observers. Although DTC has its own limitations, such as
low sampling time in practical implementation due to torque and flux hysteresis
controllers, inadequate flux and torque regulation, and switching frequency depen-
dent on motor speed and hysteresis band, FOC limitations can be overcome by DTC.
A comparison between the FOC and the DTC implemented in an FPIM is given in
[3].
Even though the model predictive control (MPC) was developed in the 1970s, due
to the fast sampling time requirement in power electrical drive systems it has been
implemented more recently [4]. There are two separate divisions in MPC, which
are the CCS-MPC and the FCS-MPC. The proposed PTC technique is part of the
(FCS-MPC) finite control set model predictive control technique [5]. PTC becoming
vital for high-performance electric drives because of its advantages over FOC and
DTC, like better torque and flux regulation, easy control because of regulation of
parameters into cost function, simple structure, and intuitive nature [6]. Dynamic
torque control of an induction motor with PTC can naturally handle multiple control
variables, nonlinear systems, and system constraints [7].
In [8, 9] PTC PTC was implemented for the Five-Phase Induction Motor drive to
enhance the torque and flux ripple. For motor drive applications, Cortes et al. [10]
developed various cost function and weighting factor architectures. To get a better
response, however, an empirical technique takes into account the weighting factor
value. The empirical method of choosing weighting factors requires a lot of time.
Cortes et al. [11] uses a genetic algorithm-based approach to weight determination,
which necessitates a lengthy lookup phase before control. In [12], a more complicated
approach is used to establish the ideal set of weighting factors by doing numerous
searches with a wide variety of parameter values. In [13], the implementation of PTC
on the OEWIM drive, and the self-tuning function are used to optimize the weighting
factor for each sample interval.
This study used a dual voltage source inverter to supply. Utilizing only big voltage
vectors from separate inverters, predictive torque control of a five-phase open-ended
winding in a five-phase voltage space vector structure. This paper is organized as
follows. Section 2 discusses the mathematical modeling of the dual-inverter fed
OEWFPIM. Section 3 discusses in great detail how the conventional PTC for the
OEWFPIM drive works. The suggested PTC and its control ideas are discussed in
Sect. 4. In Sect. 5, simulation and experimentation are used to validate the new PTC
method and show how it outperforms traditional PTC. Finally, Sect. 6 provides a list
of findings.
Predictive Torque Control of Five-Phase Open-Ended Winding … 281
2 Modelling Equations for a Dual Two-Level Voltage

Source Inverter Supplied with FP-OEW Induction Motor
A mathematical model of the three-level configured dual inverter of a five-phase

open-end winding induction motor (FP-OEWIM) utilizing voltage DC link ratio
with 1:1 and individual pole voltages is provided below.
Dual inverter fed FP-OEWIM inverter pole voltages of each inverter are stated by
(1) and (2) as shown below.
⎛ ⎞ ⎛ ⎞
Va0 Sa+
⎜ V ⎟ ⎜ S+ ⎟
⎜ b0 ⎟ ⎜ b ⎟ V
⎜ ⎟ ⎜ ⎟ dc
⎜ Vc0 ⎟ = ⎜ Sc+ ⎟ ∗ (1)
⎜ ⎟ ⎜ +⎟ 2
⎝ Vd0 ⎠ ⎝ Sd ⎠
Ve0 Se+
⎛ ⎞ ⎛ ⎞
Va , 0 Sa+,
⎜ V , ⎟ ⎜ S+ ⎟
⎜ b 0 ⎟ ⎜ b, ⎟ V
⎜ ⎟ ⎜ ⎟
⎜ Vc, 0 ⎟ = ⎜ Sc+, ⎟ ∗
dc
(2)
⎜ ⎟ ⎜ +⎟ 2
⎝ Vd , 0 ⎠ ⎝ Sd , ⎠
Ve, 0 Se+,
+
where S a + , S b + , S c + , S d + , S e + and Sa, , Sb,+ , Sc,+ , Sd,
+
, Se,+ are switching on the upper
side of inverter 1 and 2 legs of the dual VSI inverter respectively.
The consequent leg voltage in the two identical inverter arrangements exhibits 3
levels and is denoted by Eq. (3) and illustrated below as.
⎛ ⎞ ⎛ ⎞
ΔV aa , Va0 − Va , 0
⎜ ΔV , ⎟ ⎜ V − V , ⎟
⎜ bb ⎟ ⎜ b0 b0⎟
⎜ ⎟ ⎜ ⎟
⎜ ΔV cc, ⎟ = ⎜ Vc0 − Vc, 0 ⎟ (3)
⎜ ⎟ ⎜ ⎟
⎝ ΔVdd , ⎠ ⎝ Vd0 − Vd , 0 ⎠
ΔV ee, Ve0 − Ve, 0
The phase voltage and common mode voltage (CMV) can be obtained from (1)
to (3) and shown by (4) and (5) as below of dual inverter configuration.
1 ( )
Vcm = ∗ Δvaa , + Δv bb, Δv cc, + Δv dd , + Δv ee, (4)
5
⎛ ⎞ ⎛ ⎞
vaa , Δvaa ,
⎜ v , ⎟ ⎜ Δv , ⎟
⎜ bb ⎟ ⎜ bb ⎟
⎜ ⎟ ⎜ ⎟
⎜ vcc, ⎟ = ⎜ Δv cc, ⎟ − (Vcm ) (5)
⎜ ⎟ ⎜ ⎟
⎝ vdd , ⎠ ⎝ Δvdd , ⎠
vee, Δv ee,
Analysis of the dynamic behavior of induction motors is complicated because

the voltage and torque equations are rigidly coupled as they are time-varying in
nature. In order to model an induction motor of 5-phase as a 2-phase machine
for straightforward analysis, five-phase quantities are converted into two-phase
quantities [10].
One can observe the dynamic behavior of an induction motor by dynamically
simulating a five-phase induction machine using the below equations in a fixed
reference frame and employing space vector representations of electrical values.
Stator voltage equation in vector form:
d
Vs = Rs Is + ψs (6)
dt
Rotor voltage equation in vector form:
d
0 = Rs Ir + ψr − ωr ψr (7)
dt
The stator flux linkages using the above voltage equations are arrived as
{
ψs = (V s − I s R s )d t (8)
The stator, rotor conductors flux linkages can obtain as
ψs = L s i s + L m ir (9)
ψr = L r ir + L m i s (10)
The magnetic torque produced with reference frame as stationary of a two-axis

machine can be expressed as
5P
Te = imag(ψs ∗ Is ) (11)
22
The torque balancing equation for mechanical systems can be written as
dωr
Te = Tl + j
dt
{
Te − Tl
and ωr = dt (12)
J
where
P—Stator poles
T e —Developed electromagnetic torque
T l —Load torque
ωr —Rotor mechanical speed
J—Moment of inertia
the equations from (6) to (12) can be used to simulate the five-phase induction in a
stationary reference frame.
3 Classical PTC of FP Induction Motor Fed by Two-Level

Inverter Configuration
Predictive torque control is shown in the block diagram of Fig. 1 and involves a two-
level inverter with a two-level five-phase inverter that has 32 switching states and
the potential for two switching combinations. The switching states are represented
as [S a S b S c S d S e ] where S i ∈ [0, 1] {i = a, b, c, d, e}.
In the inverter of one leg, when the switch on bottom is “ON” S i = 0 and S i = 1
indicates the Upper Switch is “ON”. Based on the switching state resulting voltage
of the inverter could be expressed as follows with V dc as the DC bus voltage (Fig. 2).
Ref Flux ᴪs Sa
Ref Speed ω Sb
PI Cost Function Sc
Controller Sd
Se
Measured Speed
ωr Te(k+1) ᴪs(k+1) 2-Level Inverter FPIM
ωr Torque and Flux

Prediction
Te ᴪs
Vdc
Large voltage Torque & Flux
vectors Estimation
Fig. 1 PTC-controlled dual inverter fed FP Induction motor

Fig. 2 Shows two-level five

leg inverter topology Sa Sb Sc Sd Se
Vdc/2
Vdc/2
Sa’ Sb’ Sc’ Se’
FPIM
⎡ ⎤ ⎡ ⎤
va 4−1−1−1−1
⎢v ⎥ ⎢ ⎥
⎢ b ⎥ V dc ⎢ −14 − 1 − 1 − 1 ⎥
⎢ ⎥ ⎢ ⎥
⎢ vc ⎥ = ⎢ −1 − 14 − 1 − 1 ⎥ (13)
⎢ ⎥ 5 ⎢ ⎥
⎣ vd ⎦ ⎣ −1 − 1 − 14 − 1 ⎦
ve −1 − 1 − 1 − 14
va , vb , vc , vd andve are phase voltages of the inverter.

In a distributed stator winded five-phase induction machine d-q subspace compo-
nents are responsible for torque production and mapped with the harmonic order
of 10n ± 1 (n = 1, 2, 3, …) that is 9th,11th,19th, and 21st-order harmonics. The
x–y subspace components do not generate useful torque and are mapped 10n ± 3 (n
= 0, 1, 2, 3… ) order harmonics. Thus, there is no effect on torque production by
the order harmonics say 3rd, 7th, 13th, and 17th. Among these, the 3rd harmonics
are the strongest because the motor leakage inductance is not capable of sufficiently
filtering them. Reduced x-y stator flux components are required because distortion
in phase current results from non-torque generating harmonics that are not leached
out.
The IM’s dynamic model is depicted by taking stator current and rotor flux as the
state variables using the machine modeling equations from (6) to (12).
( )
di s kr 1
i s + τs = − j ω ψr + vs Rσ (14)
dt Rσ τr
di s
ψr + τr = ( j ω)τr ψr + L m i s (15)
dt
where i s = i ds + ji qs ,ψr = ψdr + j ψqr , vs = vds + j vqs, τr = L r Rr , τσ =
L2
σ L s Rσ , σ = 1 − L s mL r , kr = LLmr , Rσ = Rs + Rr kr2 , andω = Pωr
By expanding and discretizing stator flux from Eq. (3) the prediction model is
formed as given by (16), and stator current (14) as given by (17), at time instant
(k + 1)
ψsp (k + 1) = ψs (k) + Ts vs (k) − Rs Ts i s (k) (16)

( ) { [( ) ]}
Ts Ts 1 kr
i sp (k + 1) = 1 + i s (k) + − jωk r ψr (k) + vs (k)
τσ τσ + Ts Rσ τr
(17)
p p p
where ψs = ψds + j ψqs ; ψs (k + 1) = ψds (k + 1) + j ψqs (k + 1).
vs (k) is the Vector that is selected for the minimum cost function and Ts is sampling
time. From the predicted stator current and stator flux, the electromagnetic torque is
given by
5 ( }
Tep (k + 1) = P Im { ψsp (k + 1) ∗ i sp (k + 1) (18)
2
The predicted values are compared in the cost function using the reference values
Tnom or Tref and ψnom or ψref . The voltage vector with the lowest cost function is
chosen throughout the control cycle, and it activates the inverter.
The cost function is evaluated as follows
| |
gh = |Tref − Tep (k + 1)h | + λψ |ψref − ψsp (k + 1)h | (19)
The sole parameter that can be changed in predictive torque control is the
weighting factor λψ , which can increase or reduce the relative weight of torque
versus flux control. The weighting factor will be the ratio of the magnitudes of Tnom
and |ψnom | if the weights assigned to the two control variables are equal.
Tnom
λψ = (20)
|ψnom |
A dynamic result can be seen in Fig. 11 for conventional PTC and Fig. 12 PTC
OEW-FPIM. It is possible to achieve an excellent dynamic performance with low
distortion in the proposed controlled technique than the existing control scheme.
4 Proposed Predictive Torque Control of an Open-Ended

Winding Five-Phase Induction Motor Fed by Dual VSI
Configuration
The block diagram is shown in Fig. 3 for a Three-level dual VSI Fed FPOEWIM.
The speed error is generated by comparing the measured speed with the reference
speed and is processed by passing through the speed PI controller, which gives the
ref. torque command (Tr e f ) through the saturation block. The amplitude of refer-
ence torque would be within the limits of reference torque during simulation. Refer
the Sect. 2 for understanding the mathematical model of dual two-level inverter
voltage source inverter configuration. The sensed five-phase currents from the stator
Sa2
Sb2
Sc2
Sd2
Se2
Vdc/2
Ref Speed Ref Flux ᴪs Sa1
W Sb1
PI Cost Function Sc1
Controller Sd1
Se1
Measured Speed
ωr 2-Level FPIM
Te (k+1) ᴪs (k+1)
Inverter
ωr Torque and Flux

Prediction
Te ᴪs
Large voltage Vdc

Torque & Flux
Vectors
Estimation
v25, v24….v17
Fig. 3 PTC based dual inverter fed Five-phase open-ended winding induction motor
of FPIM are transformed using transformation matrices. Torque and flux estimation
block estimate the actual toque kth instant using the Eqs. (16) and (18), the torque
approximated compared with reference torque and the approximated flux compared
with reference flux in the cost function. The cost function will select the optimal
voltage vector, which will actuate the inverter switching.
Equation (21) shows how the voltage space vectors V s1 , and V s2 of the individual
VSIs can be used to express the resultant voltage space vector V s of the dual inverter
system depicted in αβ plane in the stationary reference frame.
When inv1 and inv2 are in the similar switching state or when all lower or upper
switches of any of the inverters are turned on simultaneously, null voltage vectors
are formed.
( )
2 Vdc ( + )
Sa + Sb+ e− 5 + Sc+ e− 5 + Sd+ e− 5 + Se+ e− 5
i2π i4π i6π i8π
Vs1 =
5 2
( )
2 Vdc ( + )
Sa , + Sb+, e− 5 + Sc+, e− 5 + Sd+, e− 5 + Se+, e− 5
i2π i4π i6π i8π
Vs2 =
5 2
Vs = Vs1 − Vs2 (21)

A two-level VSI has 32 switching vectors, of which thirty are active subspace
voltage vectors, two are zero voltage vectors, and the active vectors are divided into
large, medium, and small vectors. Large voltage vectors in the x-y harmonic plane
appear as small voltage vectors or vice versa with opposite axes. The x-y harmonic
plane maps medium voltage vectors in the plane to medium vectors.
The suggested dual inverter configuration’s fundamental space vector plane is
divided into ten sectors, each with a 36° angle span. From inv1 and inv2 large vector
switching states, which result in minor components, ten active space vectors, and
two null voltage vectors are generated. The 32 subspace voltage vectors total are
grouped down into four as follows ten large subspace voltage vectors, similarly
Medium subspace voltage vectors, Small subspace voltage vectors, and two null
voltage vectors. In order to replicate the PTC-C and PTC-OEW five-phase induction
motor drives, only large voltage vectors are used. If the inverter1 (inv1) operated with
vector v25 and the inverter2 (inv2) operated with vector v7 in the suggested control
technique, the difference (v25 − v7) yields the consequent large voltage vector.
VL1 = V25inv1 − V7inv2 = 0.647V dc ∠0 − 0.647Vdc∠(6π/5)
VL1 = 1.23Vdc∠(π/10) (22)
All other resultant voltage vectors from V L2 to V L10 are generated in the controlled
techniques as similar to V L1 (Fig. 4 and Table 1).
The common mode voltage in conventional predictive torque control would exit
in between the DC link neutral and inverter phase leg which allows zero sequence
currents to cause damage to the insulation of motor windings and bearings. The
common mode voltage in the proposed control technique is eliminated by selecting
vectors with a phase difference of 72° between two consecutive vectors. Both the
Conventional PTC and PTC-OEWFPIM are implemented in this paper using only
ten large vectors with two null voltage vectors as in Figs. 5, 6, 7 and 8. The machine
is simulated for three cases say free running (without load), loading at 2s with load
torque of 10 N-m, and free run at high (1400 rpm) and medium (800 rpm) speeds
respectively.
With the aid of the MATLAB/Simulink software, the PTC-FP-OEWIM drive opera-
tion with huge voltage vectors is implemented and confirmed. The PTC-OEWFPIM
method being suggested yields findings that are notably different from those
β axis
Sector 4
Sector 5 VL3
Sector 3
VL4
VL2
VL5 Sector 2
Sector 6
VL1
α axis
VL6
Sector 1
Sector 7 VL10
VL7
VL9
Sector 8
Sector 10
VL8
Sector 9
αβ Plane
Fig. 4 Voltage vector diagram for switching the dual inverter in αβ plane
Table 1 Voltage vector combinations for switching the dual inverter

S. No Vectors of inverter-I Vectors of inverter-II Resultant vectors
1 V 25 = V dc * 0.6472 ∠0 V 7 = V dc * 0.6472 ∠ − 144 V L1 = 1.2310 ∠18
2 V 24 = V dc * 0.6472 ∠36 V 3 = V dc * 0.6472 ∠ − 108 V L2 = 1.2310 ∠54
3 V 28 = V dc * 0.6472 ∠72 V 19 = V dc * 0.6472 ∠ − 72 V L3 = 1.2310 ∠90
4 V 12 = V dc * 0.6472 ∠108 V 17 = V dc * 0.6472 ∠ − 36 V L4 = 1.2310 ∠126
5 V 14 = V dc * 0.6472 ∠144 V 25 = V dc * 0.6472 ∠0 V L5 = 1.2310 ∠162
6 V 6 = V dc * 0.6472 ∠180 V 24 = V dc * 0.6472 ∠36 V L6 = 1.2310 ∠−162
7 V 7 = V dc * 0.6472 ∠216 V 28 = V dc * 0.6472 ∠72 V L7 = 1.2310 ∠−126
8 V 3 = V dc * 0.6472 ∠252 V 12 = V dc * 0.6472 ∠108 V L8 = 1.2310 ∠−90
9 V 19 = V dc * 0.6472 ∠288 V 14 = V dc * 0.6472 ∠144 V L9 = 1.2310 ∠−54
10 V 17 = V dc * 0.6472 ∠324 V 6 = V dc * 0.6472 ∠180 V L10 = 1.2310 ∠−18
Table 2 Parameters of
Parameter Numerical value
five-phase induction motor
Resistance of stator (Rs ) 1.05 ohms
Resistance of rotor (Rr ) 1.42 ohms
Inductance of stator (L s ) 90 mH
Inductance of rotor (L r ) 90 mH
Mutual inductance (L m ) 84.73 mH
No. of poles (P) 4
Rated speed 1440 rpm
Inertia constant (J) 0.148
Inverter DC voltage (V dc ) 100 V
of traditional PTC procedures. With the same reference torque or nominal torque
Tnom =7.74 Nm and reference stator flux or nominal stator flux ψnom =1 Wb, all
predictive torque control methods are applied at the same sampling frequency of
100 s and switching frequency of 5 kHz. 800 rpm is considered medium speed for
the five-phase induction motor while 1400 rpm is considered high speed. In the figures
below, the simulated results for the proposed method and the traditional method [1]
are displayed and compared (Table 2).
5.1 Simulation Results for Conventional PTC
See Figs. 5, 6, and 7.
5.2 Simulation Results for Conventional PTC-OEW
The set speeds of 1400 rpm and 800 rpm for five-phase induction motor, the Flux,
Torque, and Speed steady state speed responses for classical PTC method [1] are
given in Fig. 7 under high and medium speed conditions. In Fig. 10 the flux, torque,
and speeds, under steady state responses for PTC based OEW Five-phase induction
motor are shown. It can be observed from the results depicted in Figs. 7 and 10 that
the proposed PTC-OEW FPIM scheme produces significant torque ripple reduction
under medium speed . Compared Fig. 5 with Fig. 8 depicts the decrement flux ripples
Fig. 5 Stator flux, torque, speed, d-q x-y currents, inverter voltage response at rated speed 1500 rpm
of PTC-C
of PTC-C with 10 N-m load torque
Fig. 7 Stator flux and torque ripple at 1400 rpm and 800 rpm for PTC-C
with PTC based OEW FPIM by selecting vectors when compared with Classical
Predictive Torque Control under free running simulation for the motor. In Figs. 6
and 9 steady state operation at a constant load torque of 10 N-m is observed that the
medium speed ripple is improved in the proposed controlled technique (Figs. 11, 12
and Table 3).
6 Conclusions
The Proposed PTC-OEW FPIM controlled technique utilizes the 10 large active
vectors generated from two two-level inverters to enhance the drive performance in
terms of torque and speed ripples under medium speed operations. During dynamic
operations where the speed changes from high to medium, the torque and flux ripples
are improved, and also during a constant load of 10 N-m. Here in the proposed
controlled technique, only large voltage vectors are used. The same controlled tech-
nique can be implemented further for different voltage vectors like by the combina-
tion of large, medium, small, and zero voltage vectors. The x-y subspace harmonics
are not eliminated this could be the scope for improvement. Hence it is suggested
that the proposed PTC-OEW scheme exhibits improved dynamic and steady state
performance results for dual inverter fed OEW Five-phase IM under medium speed.
MATLAB/Simulink software is used for implementing the proposed controlled
scheme.
Fig. 8 Stator Flux, Torque, Speed, d-q x-y currents, Inverter voltage response at rated speed
1500 rpm of PTC-OEW
of PTC-C with 10 N-m load Torque
Fig. 10 Stator flux and torque ripple at 1400 rpm and 800 rpm for PTC-OEW
Fig. 11 Flux and torque ripple, speed dynamics of at 500 rpm of PTC-C
Fig. 12 Flux and torque ripple, speed dynamics of at 500 rpm of PTC-OEW
Table 3 Comparison of results

PTC-C PTC-OEW PTC-C PTC-OEW
Torque ripple (p-p) (%) Flux ripple (%)
High speed (1400 rpm) 10.2 6.07 8.02 5.06
Medium speed (800 rpm) 12.5 8.9 9.95 6.08
Dynamics at +500 to −500 rpm 12.2 10.05 10.1 8.08
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Grid-Integrated EV Charging
Infrastructure
Sugunakar Mamidala and Arvind Kumar Prajapati
Abstract Grid-integrated electric vehicle (EV) charging infrastructure is becoming

increasingly important as EV adoption continues to grow. The integration of EV
charging infrastructure with the electric power grid presents several challenges,
including interoperability, safety, grid stability, and efficiency. This paper provides
the current state of the art in grid-integrated EV charging infrastructure. The paper
begins by discussing the benefits of grid-integrated EV charging, including reduced
greenhouse gas emissions and improved grid flexibility and provides an overview
of the various types of EV charging infrastructure, including Level 1, Level 2, and
DC fast charging. The paper also discusses the various communication protocols
used in EV charging infrastructure, such as OCPP, CCS, and CHAdeMO. The
paper discusses the existing standards and regulations for EV charging infrastructure,
including IEEE 1547, IEC 61851, and ISO/IEC 15118. The paper work concludes
by discussing the future of grid-integrated EV charging infrastructure, including the
integration of renewable energy sources. Overall, this paper provides the current state
of grid-integrated EV charging infrastructure/EV charging stations.
Keywords Grid integration · Electric vehicles (EVs) · Charging infrastructure ·

Greenhouse gas emissions · Renewable energy sources · Standards
1 Introduction
Internal combustion engine (ICE) vehicles contribute to air pollution and are depen-
dent on foreign oil, making electric vehicles (EVs) a promising alternative. However,
early EVs faced challenges such as limited range, insufficient charging infrastructure,
and long charging times, which made them less competitive than traditional vehicles
S. Mamidala
VIT-AP University, Amaravati, India
A. K. Prajapati (B)
NIT Jamshedpur, Jamshedpur, Jharkhand, India
298 S. Mamidala and A. K. Prajapati
(TVs). Range anxiety, the fear of running out of battery power while driving, was also
a common concern among EV owners. To overcome these challenges, battery tech-
nology has been improved to increase energy capacity and extend driving range [1,
2]. Additionally, three technologies have been developed to address the issue of long
charging times: dynamic on-road charging, direct current fast charging, and battery
swapping. Dynamic on-road charging involves wirelessly charging EVs while they
are in motion. Direct current fast charging allows for faster charging times compared
to traditional AC charging [3, 4]. Battery swapping stations, where used EV batteries
are replaced with fully charged ones, provide a quick way to recharge EVs.
In recent studies, local charging systems and battery swapping stations have been
used to develop electric bus charging infrastructure [5, 6]. The adoption and success
of electric vehicle technology has faced challenges related to the various types of
batteries used and battery ownership issues. However, dynamic on-road charging
has been seen as a promising solution, especially for fixed-route trips like freight
transportation and buses. The dynamic on-road charging allows EVs to be charged
wirelessly while in motion, eliminating the need for lengthy charging times and
range anxiety. This technology is particularly suitable for fixed-route trips where EVs
follow a predetermined path and can be charged at specific locations. For example,
electric buses can be charged at bus stops or along a specific route, allowing for
uninterrupted service. In the case of freight transportation, dynamic on-road charging
can be used to charge electric trucks while they are on the highway, reducing the need
for frequent stops to recharge. This can increase efficiency and reduce transportation
costs.
A recent study suggests that providing a network of charging infrastructure can
help increase the acceptance and adoption of electric vehicles. The study examines
how technological advancements impact the optimal charging infrastructure required
to meet the growing charging demand for EVs [7, 8]. This analyses the placement and
number of charging stations in intercity networks, taking into account the proximity
of other structures. As EV technology offers lower fuel emissions, it is gaining
popularity and is expected to become even more popular in the near future. The
study predicts that the popularity of EVs will rapidly increase, highlighting the need
for efficient and accessible charging infrastructure. By strategically placing charging
stations and ensuring sufficient numbers of chargers at each station, the study suggests
that the charging infrastructure can be optimized to meet the growing demand for
EVs. This can help to increase the convenience and attractiveness of EVs as a viable
transportation option, further driving their popularity and adoption. The fast charging
infrastructure is a key factor in supporting the widespread adoption of electric vehicles
and overcoming the challenges associated with EV ownership, such as charging time
and range anxiety [9, 10].
The tethering electric vehicles to the power grid presents challenges in terms
of infrastructure planning and power quality considerations, it also offers opportu-
nities for load balancing, reactive power support, and ancillary services [11–14].
The integrating the grid with the EV charging infrastructure presents technical chal-
lenges related to power quality, voltage deviations, and distribution system losses.
However, solutions such as smart charging and energy storage systems are being
Grid-Integrated EV Charging Infrastructure 299
developed to optimize EV charging and minimize its impact on the grid [15]. Other
problems include the instability issue and the shortening of transformer life due to
overloading. To reduce these effects, a variety of demand-side management tactics
are used, such as the use of energy storage systems (ESS) and the incorporation
of renewable energy sources (RES) into charging systems [16, 17]. The benefits of
using energy storage systems are discussed in relation to minimizing the negative
grid effects of EV charging. Renewable energy is being considered as an alternative
source for EV charging, with a focus on solar PV. The idea of vehicle-to-grid power
flow is becoming more popular in order to support the grid.
In spite of this, range anxiety and the availability of adequate charging stations
are two major barriers to EV adoption. Consumers are delaying the adoption of elec-
tric vehicles because they are concerned about the lack of public charging stations,
according to numerous studies [18, 19]. Two main categories, conductive charging,
and wireless charging can be used to classify EV charging techniques. So far, the most
developed charging technique is conductive charging. Offboard chargers and slow
chargers/AC chargers are additional categories under which the conductive charging
system can be further subdivided into fast chargers/DC chargers. Since the charging
socket is accessible easily, AC chargers are more prevalent. The battery cannot be
quickly recharged by AC chargers because of their power limitations. Range anxiety
issues can be addressed by using DC chargers, which have high power levels. DC
fast chargers are being installed along highways in numerous countries, but they still
aren’t enough to allay EV users’ fears about range anxiety.
Additionally, using DC chargers frequently may cause a battery’s lifespan to
be shortened. Another approach to charging EVs is wireless power transfer. Three
different techniques, static charging, quasi-dynamic charging, and dynamic charging,
can be used to automate the charging of electric vehicles (EVs) by wireless power
transfer [20–22]. Static charging has a number of advantages, including easy instal-
lation in parking lots or garages and the removal of the electric shock risk caused
by large conductive wires. The quasi-dynamic charging system charges EVs when
they stop for brief periods of time, like at stop signs, extending their range on the
road and lowering their need for energy storage. While the vehicle is moving, the
dynamic system continuously charges the EV battery. The advantages of this system
include a decrease in EVs’ need for energy storage and a reduction in range anxiety.
According to numerous technical studies that have been thoroughly conducted on
this subject, the major difficulties associated with the integration of EVs into elec-
trical grids include transformer overloading, high load demand during peak hours,
harmonic injection into the system, voltage stability, and sag, all of which put the
quality and stability of the electric grid at risk [23, 24].
There are six sections in this paper. A summary of charging technologies for
charging systems is provided in Section II. The grid integration standards are covered
in Section III. The charging infrastructure described in Section IV consists of both
hardware and software components. Sections V discusses recommendations and
future scope for complete adoption of EVs. Section VI presents a final conclusion.
2 EV Charging Technology
In general, conductive and inductive charging systems can be used for EV charging.
Inductive charging systems are still being researched and are not yet widely adopted
in the electrified transportation sector, the more popular and well-established system
is conductive charging.
2.1 Conductive Charging Systems
Power is transferred to the vehicle directly during conductive charging [25]. Conduc-
tive charging is divided into two main categories: on-board and off-board charging.
In order to provide quick charging, an off-board method is used, whereas onboard
methods are primarily used for slow charging where the charging activity is contained
inside the vehicle. Chargers that use offboard charging are moved outside of the
vehicle. The society of automotive engineers (SAE) and the electric power research
institute (EPRI) have classified EV charging levels as level1, level2, and level3 [26].
As shown in Fig. 1, Levels 1 and 2 are AC chargers, while Level 3 is a DC fast
charger.
Level-1 AC Charger: Level-1 charging, which uses a typical AC 120 V, 15 A or 20
A domestic outlet, is the slowest charging. This method of charging utilizes a typical
SAE J1772 connector on one end and a NEMA 5-15 R/20 R electrical outlet on the
other. Level-1 charging requires between 8 and 16 h to fully charge and uses between
1.4 and 1.9 kW of power, based on the current rating. Approximately $500–$880 is
the estimated cost of the residential applications Level-1 charging infrastructure.
Level-2 AC Charger: The charging mode of Level-2 is typically regarded as the
highly popular one for both public and private facilities. For private charging, this
charging mode of Level-2 is typically regarded as the highly popular one for both
public and private facilities, and for public charging, it uses a 400 V AC three-phase
connection with 80 A current. This charging technique makes use of a standard SAE
J1772 connector. Level-2 charging takes 4–8 h to fully charge and offers power
Fig. 1 Conducting charging

system Conductive
Charging
System
Level-3 DC
Level-1 AC Level-2 AC
Fast
Charger Charger
Charger
outputs between 7.7 kW and 25.6 kW. Installing Level-2 charging infrastructure is
expected to cost between $2150 and $2300.
Level-3 DC Fast Charger: For public or commercial charging stations, Level-3
or DC fast charging is the most effective charging technique [24]. Depending on the
size and type of the battery, fast charging can complete an 80% charge in 10–15 min.
Due to the long charging time for the final 20% of the charge, DC fast charging is
essentially only considered up to an 80% state of charge level. Level-3 charging uses
an offboard charger to convert AC to DC, and the vehicle receives DC power through
Japanese CHAdeMO and SAE J1772 Combo connectors. A three-phase circuit with
a range of AC 208–600 V that carry up to 200 A of current for fast charging. A
vehicle’s overall weight can be decreased by using an offboard charger, which lessens
the amount of onboard circuitry. According to the updated SAE standards, there are
two levels of DC fast charging, Level-1 and Level-2 charging. The Output power of
Levels 1 and 2 is 0–40 kW and 40–100 kW respectively. It will cost between $50,000
and $160,000 to build level-3 charging infrastructure.
2.2 Inductive Charging Systems
Without making direct contact between the vehicle and power source, inductive
or wireless charging transfers power using an electromagnetic field [27]. Electrical
safety is one area where inductive charging beats conductive charging. The drawbacks
of this charging technique include less efficiency and more power losses. Induction
charging, as depicted in Fig. 2, allows for automated charging.
Level-2 charging at a power rating of 7.2 kW with 230 V AC was accomplished
by an inductive charging method with an efficiency of 88.5% [28].
Static wireless charging: Static charging may be put in place where it is needed,
such as private and parking garages, with the advantage of eliminating the shock
hazard caused by wires.
Dynamic wireless charging: The dynamic wireless charging system can reduce
the size of the batteries in EVs and increase driving range by travelling along
designated charging tracks, the vehicle is continuously charged.
Fig. 2 Inductive charging

systems Inductive
Charging
System
Quasi-
Static Dynamic
Dynamic
Charging Charging
Charging
Quasi-Dynamic wireless charging: In addition to extending the driving range

and enabling EVs to use less energy storage, when a vehicle briefly stops, as, at a
traffic signal, the quasi-dynamic induction charging system charges the battery.
3 Charging Standards for Grid-EV Integration
The charging standards for grid-EV integration help to promote the adoption of EVs
by ensuring that the charging infrastructure is safe, reliable, and interoperable with
the grid. The standards provide a common framework for the design, installation,
and operation of the charging infrastructure, which can help to reduce costs and
simplify the process for EV drivers and charging infrastructure providers. There are
several global standards for EV charging infrastructure [29, 30]. While IEC is widely
used in Europe, SAE and IEEE are used by manufacturers based in the United States.
Japan’s CHAdeMO EV charging standards are used there. Guobiao (GB/T) standards
are used in China for both DC and AC charging.
3.1 EV Charging Standards
There are several reasons why EV charging standards, such as IEC (Interna-
tional Electrotechnical Commission) and SAE (Society of Automotive Engineers)
standards, are important such as
Interoperability: EV charging standards ensure that EVs from different manufac-
turers can be charged using the same charging infrastructure. This interoperability
is crucial for EV adoption, as it allows drivers to charge their EVs at any charging
station, regardless of the make or model of their vehicle.
Safety: EV charging standards ensure that charging equipment is safe for both the
EV and the user. These standards specify safety requirements for charging cables,
connectors, and charging stations, to minimize the risk of electrical shock, fire, or
other hazards.
Efficiency: EV charging standards specify charging protocols and communication
protocols between the EV and the charging station, to ensure that charging is efficient
and fast. These protocols help optimize the charging process and reduce the time
required to charge an EV.
Future-proofing: EV charging standards are designed to be future-proof, meaning
that they can accommodate new technologies and advances in EV charging. For
example, the latest version of the IEC standard includes provisions for wireless
charging, which may become more widespread in the future.
The EV charging standards are essential for ensuring that EVs can be charged
safely, efficiently, and conveniently, and for promoting the widespread adoption of
electric vehicles (Fig. 3).
Fig. 3 Standards for charging electric vehicles
3.2 Standards for Grid Integration
IEEE1547, UL1741, and NFPA70 are three standards and codes that are available.
The following list of standards and codes highlights their key features.
IEEE1547: Standard protocols for integrating distributed resources with electrical
power systems are IEEE1547. The key points of IEEE1547 are described in the below
Table 1.
UL standards: Several standards were released by Underwriters’ Laboratories
(UL) to address various DER grid integration issues. UL 1741, which addresses the
specifications for power conversion equipment and their protective devices that apply
to the grid integration of DERs, is the most significant of these standards. The key
components of UL 1741 SA, UL 62109, UL 62109-1, and UL 62109-2 are listed in
Table 2.
3.3 National Electric Code (NEC) Standards
For safety precautions in the EV industry, NEC standards for EV charging equipment
are required [30].
NEC 625: Off-board charging requirements are provided by NEC 625, “Electric
Vehicle Charging and Supply Equipment Systems.” It provides installation guidelines
for the EV charging station equipment and covers the infrastructure connected to
Table 1 Description of IEEE1547 standards

Standards Description
IEEEP1547.1 For interconnection specifications and equipment
For equipment interconnecting distributed resources
IEEEP1547.2 Describes the characteristics of distributed energy resources (DERs) and related
interconnection problems
IEEE 1547 is a power system connectivity standard
In order to make IEEE 1547 user-friendly, it includes application details and
technical background
IEEEP1547.3 Promotes interoperability by providing standards for controlling, exchanging,
and monitoring distributed generators linked to an electric power system
Serves as a reference for controlling, exchanging, and monitoring distributed
resources linked to electric power systems
IEEEP1547.4 Discusses the engineering aspects of how neighborhood’s buildings can function
as “electrical islands” to supply power when utility power is unavailable
Referred to as a draught guide for creating, managing, and connecting distributed
resource island systems to the electrical grid
Table 2 UL standards [30]

Standards Description
UL 62109 After being renamed to comply with IEC standards, UL 1741 is now known as UL
62109
“Power Converters for Use in PV Systems,” as the name suggests, and UL 62109-1
and UL 62109-2 are its two subsections
Specifically covers the testing and construction requirements for photovoltaic
inverters and converters
UL Covers the essential specifications for creating power conversion equipment that is
62109-1 protected from risks like an energy, mechanical failure, fire, electric shock, and
others
“Standard for the safety of power converters used in photovoltaic power
systems—part 1: General requirements” is the name of the standard
UL Takes care of the requirements for inverter-specific safety features, such as DC
62109-2 injection, labeling and documentation, total harmonic distortion, system isolation
protection, and voltage, and frequency control
Entitled “PV Inverter Specific Requirements”
UL 1741 It is a UL 1741 supplement draught standard
SA Describes contemporary smart inverter topographies and testing procedures
Essential for integrating DERs into the smart grid
Determines the essential inverter functions for the best grid stability
UL 1741 It includes output controllers, converters, charging controllers, and inverters made
for grid-connected or stand-alone power systems that abide by utility-specific
interconnection requirements and are certified in accordance with the National
Electric Code (NEC)
either feeder or branch circuits for EV charging, such as conductors, connecting

plugs, and inductive charging devices.
NEC 625: The area of truck parking spaces is covered by this standard, which
is titled “Electrified Truck Parking Spaces.” It specifies the requirements for the
electrical apparatus and conductors used to charge trucks that are located outside of
the vehicle.
3.4 Standards for EV Safety
To integrate the grid and charge EVs, safety measure is a requirement. NFPA and
NEC place a strong emphasis on security and safety. These two organizations codes
for EV charging and grid integration are described in more detail below. Standards
of NFPA: The public can get information about the fire, electrical, and life safety
from NFPA, a leader in the field worldwide. NFPA 70, which includes guidelines on
the PCC customer side regarding safety and electrical wiring, is the standard that the
organization has released in the area of the integration of electric vehicles into the
grid.
The requirements for grid interconnection are specified in 690, a solar photo-
voltaic system. 700: Emergency systems- Provisions that apply to emergency power
systems are included, as well as information about interconnection, such as transfer
switches. Section 701 of the code provides details on connecting backup power
sources. Section 702 on optional standby systems contains details about intercon-
nection, circuit wiring, grounding, and transfer switches. 705: This article has a lot
of implications for EV integration. Broadly speaking, this term refers to the intercon-
nection of alternative energy systems, with the exception of fuel cell and photovoltaic
(PV) systems.
4 Charging Infrastructure Integration with the Electrical

Grid
There are several advantages of charging infrastructure for electric vehicles (EVs)
as illustrated below.
Convenience: EV charging infrastructure provides a convenient means of charging
for EV owners. With charging stations located in public places, workplaces, and
residential areas, EV owners can easily charge their vehicles while going about their
daily activities. Reduced Emissions: EVs produce zero tailpipe emissions, which
can help to reduce air pollution and improve public health. By providing charging
infrastructure, the adoption of EVs can be increased, resulting in a reduction in
greenhouse gas emissions from the transportation sector.
Lower Operating Costs: EVs have lower operating costs than gasoline-powered
vehicles because electricity is generally cheaper than gasoline on a per-mile basis.
Charging infrastructure can make it more convenient and cost-effective for EV
owners to charge their vehicles, which can further reduce their operating costs.
Energy Security: Charging infrastructure can increase energy security by reducing
dependence on imported oil for transportation. By increasing the use of domestically
produced electricity for transportation, countries can enhance their energy security
and reduce their dependence on foreign oil.
Economic Benefits: The development and installation of charging infrastructure
can create jobs and stimulate economic growth. The growth of the EV industry can
also create new opportunities for businesses involved in the production, distribu-
tion, and maintenance of EV charging infrastructure. The charging infrastructure for
electric vehicles provides convenience, reduces emissions, lowers operating costs,
increases energy security, and provides economic benefits. The continued expansion
of charging infrastructure is essential to support the growth of the EV industry and
to reduce greenhouse gas emissions from the transportation sector. As illustrated
in Fig. 4, power, communication, and control infrastructure make up the overall
infrastructure for charging [30].
4.1 Power Infrastructure
Fuel-wise installed generation capacity is depicted in Fig. 5 and AC or DC power

supplies are used for EV charging [31, 32]. Depending on the country’s power system,
the voltage and frequency levels for AC charging can vary. Three levels of AC
charging are distinguished: level 1, level 2, and level 3, with level 3 having the
highest charging voltage, and DC charging is more rapid and typically has a higher
charging power capacity [33].
4.2 Communication and Control Infrastructure
The communication network for EV charging: Effective grid-wide and EVSE

communication is necessary for smart charging management [34]. There are two
types of communication protocols available: wired communication protocols and
wireless communication protocols as shown in Fig. 7. These technologies are used to
integrate EVs into various private networks; they are comprising field area networks
(FAN), home area networks (HAN), neighborhood area networks (NAN), and indus-
trial area networks (IAN). These networks are utilized to keep an eye on and manage
home electricity usage for other purposes and for charging and discharging (Figs. 6).
The wireline communication: Wireline technologies are suitable for long-distance
data transfer, such as the distribution of charging stations throughout big cities, that
communicates and receives data using the same power line, is the most widely used
Fig. 4 EV charging infrastructure [30]
Fig. 5 Installed generation capacity up to March 2022. Source Ministry of Power government of
India
Control
Infrastructure in
EV Charging
System
Mobility Coordinati Control

Control on Control Structure
Un-
Static Dynamic Coordinated Centralized Decentralized
coordinated
Control Control Control Control Control
Control
Real time
Consolidated Optimization
Hierarchical
Predictive
Structure
Control
Fig. 6 Control infrastructure in EV charging
Fig. 7 Buck-EV charging station (BC EVCS)
protocol in wireline communication technology. Home Plug 1.0, home plug turbo,
home plug AV, HD-PLC, and UPA are a few PLC-based protocols.
The wireless communication: Wireless communication is also necessary for a
complete communication structure, for example, to allow vehicles and charging
stations to communicate using data [35, 36]. In order to connect electrical devices,
wireless LAN devices are used to construct the wireless communication network in
a hierarchical mesh configuration. Popular wireless communication technologies for
EV grid connections include Wi-Fi, cellular, Zigbee, satellite networks, and WiMAX.
It serves as the primary medium for informing EV users of their charging status.
The EV charging control infrastructure: The charging control structure, which
includes the distribution grid, EVs, and charging stations, can be divided into three
groups based on coordination, mobility, and control structure, as shown in Fig. 8
Fig. 8 Output voltage and current of Buck-EV charging station
[37, 38]. In this discussion of vehicle mobility, there are two types of EV charging
infrastructure: static and dynamic. Static charging is considered to be the same as
the vehicle being parked in a charging station and dynamic charging system takes
into account various temporal movements, such as the time the vehicle arrives and
departs, the route is taken, and any unforeseen reasons for an EV to arrive or depart.
Uncoordinated and coordinated charging control are the two approaches used in
this charging coordination for EVs. Due to their uncoordinated charging, electric
vehicle batteries either begin charging right away when they are plugged in or begin
charging after a fixed delay that can be adjusted by the user. This charging process
continues until the battery is fully charged or disconnected. Off-peak charging, which
involves recharging EVs when demand on the grid is at its lowest point, is a planned
charging method.
The EV integration with the electrical grid refers to the process of connecting electric
vehicles (EVs) to the power grid. This is important because as more EVs are on the
road, they will require more electricity to charge their batteries. The power grid must
be able to handle this increased demand and manage the flow of electricity to and from
EVs. This integration included features of smart charging, where EVs communicate
with the grid to optimize charging times and reduce strain on the system during peak
hours. This can also involve vehicle-to-grid (V2G) technology, which allows EVs to
send excess power back to the grid during times of high demand or when renewable
energy sources are producing more electricity than needed. The integration of electric
vehicles with the grid is a crucial step towards a cleaner and more sustainable energy
future. This work has explored various types of EV charging stations connected to
the grid and identified several power quality parameters from the simulation models.
This has been shown that these power quality issues can be mitigated through the use
of active and passive filters [39, 40]. By addressing these issues, we can promote the
growth and adoption of EVs, contributing to a more environmentally friendly future.
The output voltage, current, real power, and reactive power characteristics are
essential in real-time scenarios because they provide critical information about the
state of the power system, including stability, power demand, and power quality.
Monitoring these characteristics helps operators to detect issues in advance and take
corrective measures before they lead to equipment malfunctions or power outages.
This proactive approach can prevent potential problems from escalating and ensure
the efficient operation of the power system.
5.1 BC EVCS Characteristics
Figure 7 illustrates a buck converter charging station with grid integration used for
charging electric vehicle batteries. However, the voltage and current characteristics
of the charging station show power quality issues, as shown in the simulation results
represented in Fig. 8, without any compensation. The voltage output exhibits more
disturbances from 0 to 0.025 s, voltage spikes and notches from 0.05 to 0.5 s. On
the other hand, the output current shows more disturbances from 0 to 0.05 s and less
from 0.05 to 0.1 s. However, the current is stable from 0.15 s onwards.
Figure 9 shows the simulation waveforms of real and reactive power, with real
power being 4.5 × 104 watts and reactive power being 0.2 × 104 kVAR. The power
used by a device or system provides information about the actual power demand of
the system. Monitoring real power enables operators to manage power supply and
demand more effectively, reducing costs, and improving system efficiency. Reactive
power is used to maintain the magnetic field in electrical devices such as motors and
transformers. It is essential in real-time scenarios as it provides information about the
system’s stability. Reactive power helps to maintain voltage levels, and monitoring
it allows operators to detect issues with power factor and take corrective action to
prevent equipment damage or power outages.
Fig. 9 Real and reactive power of Buck-EV charging station
Fig. 10 Boost-EV charging station (B-EVCS)
5.2 B-EVCS Characteristics
Figure 10 illustrates a boost converter charging station with grid integration used for
charging electric vehicle batteries. However, the voltage and current characteristics
of the charging station show power quality issues, as shown in the simulation results
represented in Fig. 11, without any compensation. The voltage output exhibits more
disturbances from 0 to 0.016 s, voltage spikes and notches from 0.05 to 0.5 s. On the
other hand, the output current shows more disturbances from 0 to 0.05 s. However,
the current is stable from 0.15 s onwards.
power being 10.2 kW and reactive power being 100 kVAR. The power used by a
device or system provides information about the actual power demand of the system.
Monitoring real power enables operators to manage power supply and demand more
effectively, reducing costs, and improving system efficiency. Reactive power is used
Fig. 11 Output voltage and current of Boost-EV charging station
to maintain the magnetic field in electrical devices such as motors and transformers.
It is essential in real-time scenarios as it provides information about the system’s
stability. Reactive power helps to maintain voltage levels, and monitoring it allows
operators to detect issues with power factor and take corrective action to prevent
equipment damage or power outages.
Fig. 12 Real and reactive

power of Boost-EV charging
station
5.3 BBCEVCS Characteristics
Figure 13 illustrates a buck-boost converter charging station with grid integration

used for charging electric vehicle batteries. However, the voltage and current charac-
teristics of the charging station show power quality issues, as shown in the simulation
results represented in Fig. 14, without any compensation.
power being 27 kW and reactive power being 1 kVAR. The power used by a device
Fig. 13 Buck-Boost EV charging station (BBCEVCS)
Fig. 14 Output voltage and current of Buck-Boost EV charging station

Fig. 15 Real and reactive power of Buck-Boost EV charging station
or system provides information about the actual power demand of the system. Moni-
toring real power enables operators to manage power supply and demand more effec-
tively, reducing costs, and improving system efficiency. Reactive power is used to
maintain the magnetic field in electrical devices such as motors and transformers.
It is essential in real-time scenarios as it provides information about the system’s
stability. Reactive power helps to maintain voltage levels, and monitoring it allows
operators to detect issues with power factor and take corrective action to prevent
equipment damage or power outages.
5.4 SEPIC EVCS Characteristics
Figure 16 depicts a SEPIC converter charging station with grid integration utilized
for charging electric vehicle batteries. Nevertheless, Fig. 17 illustrates the voltage
and current characteristics, while Fig. 18 shows the power characteristics.
5.5 ZETA EVCS Characteristics
Figure 19 depicts a ZETA converter charging station with grid integration utilized
for charging electric vehicle batteries. Nevertheless, Fig. 20 illustrates the voltage
and current characteristics, while Fig. 21 shows the power characteristics.
Fig. 16 SEPIC-EV charging station (SEPIC EVCS)
Fig. 17 Output voltage and current of SEPIC-EV charging station
5.6 SOLAR EVCS Characteristics
To reduce the burden on the utility grid, renewable energy sources are favored, and
in this paper, a solar charging station was built as depicted in Fig. 22 to provide
uninterrupted power to both electric vehicles and the utility grid. The PV character-
istics such as voltage, current, and power at an insolation of 1000 kWh/m2 and a
temperature of 45 °C are illustrated in Fig. 23. Moreover, Figs. 24 and 25 display the
voltage, current, and power characteristics of solar PV integrated utility grid.
Fig. 18 Real and reactive power of SEPIC-EV charging station
Fig. 19 Zeta-EV charging station (ZETA EVCS)
5.7 Correlation Between ICEV and BEV Cars Co2 Emission
Guobiao The average distance covered by an Indian car is around 12,000–15,000 km

per year. Let us consider a value of 14,000 km for comparison purposes between the
two vehicles as represented in Table 3.
The BEV battery life 200,000 km, average car runs per year 14,000 km means
average life of the battery is 14 years (200,000/14000), No CO2 emission of battery
production up to 14 years means we are in green vehicle (GV) mode and we reduced
74,340 kg CO2 by adopting one BEV car as shown in Fig. 26. How least adoption
of EVs in India compared with other countries in Asian-Pacific region Fig. 27.
Fig. 20 Output voltage and current of Zeta-EV charging station
Fig. 21 Real and reactive power of Zeta-EV charging station

Fig. 22 Solar-EV charging station
Fig. 23 Solar panel output

Fig. 24 Output voltage and current of Solar-EV charging station
Fig. 25 Real and reactive

power of Solar-EV charging
station
Table 3 Comparisons of real-time scenarios of both the cars co2 emission per year
IC Engine Vehicle (ICEV) Battery Electric Vehicle (BEV)
The car must burn 777.78 lit of diesel to For a total distance of 14,000 km, the car must be
cover its 14,000 km of driving charged 64 times (given the car’s 220 km range
(average mileage 18 km) on a single charge; 14,000/220 = 64)
For 777.78 lit diesel purification, we need To recharge a 30-kWh battery 64 times, 1920
777.78 kW of power, which produces kWh of power is required (30 kwh*64 times)
469.94 kg CO2 (777.78*0.57*1.06)
For burning 777.78 lit fuel during running, a Around 1423 kg of CO2 is emitted overall during
total of 2084.5 kg CO2 are emitted annually charging (1920*0.57*1.3)
(777.78*2.68)
Total CO2 Emissions are equal to total CO2 Production of a 30 kWh battery results in
emissions for fuel production plus fuel burn emissions of 5310 kg CO2 (30*177, once only).
during vehicle operation Total CO2 Emission equals the sum of CO2
emissions during battery production and CO2
emissions during charging
=469.94*y + 2084.45*y (y represent the =1423*y + 5310*y kg CO2
number of years) =5733*y (y represent the number of years)
=2554.39*y kg of CO2 is released annually
when the car is in use
Fig. 26 CO2 emission of both the cars

Fig. 27 Market share % of

electric cars in the
Asia–Pacific region
6 Conclusion
The Grid-Integrated EV Charging Infrastructure plays a crucial role in the modern

electric vehicle industry by providing uninterrupted and sustainable power to electric
vehicles, reducing the burden on the utility grid, and promoting renewable energy
sources. This paper has provided valuable insights into various aspects of charging
infrastructure, including different topologies, power quality issues, real and reactive
power monitoring, and solar charging stations with grid integration. The research
and development of advanced technologies and innovative solutions in this field,
as demonstrated in the MATLAB simulations, will further boost the growth and
adoption of electric vehicles, contributing to a cleaner and greener future.
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ehs-2022-0146
Modified Multi-inductor-Based Cell
Balancing in Electric Vehicles
Utsab Bhattacharya and Pradeep Kumar
Abstract Cell balancing is an essential feature of battery management systems as

the battery packs are affected by various factors, and imbalance is one of the major
ones. Without balance, the cell’s performance will drift apart, and much energy
will be wasted in the battery pack when they are frequently operated in recycling
conditions. Different methodologies for cell balancing have been proposed so far,
which must be adequately applied considering the application of the battery pack.
This paper presents a modified simple inductor-based active cell balancing technique
in Electric Vehicles. The cell equalization topology has been simulated in MATLAB/
Simulink. The performance is evaluated using the quantification of energy exchange.
The results show that the proposed approach transfers energy in less time, with lower
losses. Also, the design complexity is less.
Keywords Cell balancing · Battery management systems · Imbalance · Active

cell balancing
1 Introduction
Energy storage is critical for operating microgrids to transport systems. Several

energy storage systems (ESS) options are available depending on the application
and the duration for which the energy is supplied. A broad classification of different
ESSs available is shown in Fig. 1 [22]. Among these various sources, the battery
energy storage system (BESS) provides high specific power (W/Kg) as well as high
specific energy (Wh/kg) in comparison to other ESSs. Though ESSs with better
specific energy (Wh/kg) or specific power (W/kg) are available, BESS are considered
mature and safe for application. As a result, BESSs are the preferred choice for
microgrids, especially electric transport, due to ease of portability. Li-ion batteries
U. Bhattacharya (B) · P. Kumar

National Institute of Technology, Kurukshetra, India
P. Kumar
326 U. Bhattacharya and P. Kumar
Fig. 1 Classification of
different energy storages
according to the duration of
energy usage
are preferred in electric vehicles due to their long cycle lives, large capacity, high-
energy densities, compact volume, low self-discharge rates, no memory effect, lower
weight, and increased safety [2–4]. The individual cell voltages of these batteries are
low; therefore, to provide the required voltage and current, the cells are connected
in series and parallel to form a stack. The charging or discharging process of the
stack stops as soon as one of the cells is either completely charged or discharged,
respectively [1]. Thus, the imbalanced cells limit the whole pack’s capacity. The
imbalance arises due to intrinsic factors, like manufacturing and fabrication [5], and
extrinsic factors, like temperature and external circuitry [6]. Imbalanced cells lead
to heating [9], an increase in losses [10], low efficiency, and accelerated degradation
[11]. Thus, a reduction is observed regarding the battery pack’s usable capacity,
decreased usage efficiency, and reduced battery pack lifetime [12]. Therefore, cell
balancing using a battery management system (BMS) becomes essential [6–9].
The BMSs use either state-of-charge (SOC) or voltage-based balancing. The
balancing technique based on voltage is simple to operate, and it is affected by
the internal state of the battery, and environment d balancing is simple and easy to
operate [10–12]. On the other hand, SOC reflects the battery pack’s capacity [13,
14]. It is affected by temperature, self-discharge, battery model, and other factors.
State-of-Charge (SOC) based factors are preferred over voltage-based ones.
A body of literature shows different topologies for cell balancing [7]. The different
approaches can be broadly classified as passive balancing, the release of redundant
energy from the cell, and active balancing, transferring energy from one cell (full) to
the other (empty). Though passive balancing is simple, the approach is inefficient.
On the other hand, active balancing is more reliable and efficient. It uses inductors,
capacitors, transformers, or converters as intermediate bridges to absorb the energy
from full cells and deliver it to the emptier cells. Figure 2 shows the different cell
balancing topologies proposed in the literature.
Among the different topologies, active topologies are preferred. The inductor-
based topologies have found more attention from researchers than passive topologies.
Along with the charge balancing, the time it takes is also critical. The multi-inductor
topologies are designed to share charge. But, the time taken to balance is high. There-
fore, this paper proposes a modified single inductor-based charge-sharing strategy to
• Balance the charge between cells.
• Speed up the charge-sharing process.
Modified Multi-inductor-Based Cell Balancing in Electric Vehicles 327
Fig. 2 Different proposed cell balancing topologies
The proposed approach uses a simple algorithm of a single inductor. The advantage
of the proposed method are
• Makes charge transfer fast,
• Design remains simple,
• Overall losses across the switches, diodes, inductors, and load are less for the
proposed topology,
• The charge transferred to the weak cells from the higher cells is also more,
• The amount of energy transferred from the higher SOC cells and delivered to
lower SOC cells is also more than the single inductor.
This paper proposes a modified multi-inductor-based active cell balancing
topology. The methodology uses an inductor across each cell after the array of
switches and diodes. Both the proposed and conventional methods are implemented
with the same control algorithm. The system is simulated on Simulink.
This article delves into various cell balancing techniques and utilizes MATLAB/
Simulink to simulate some of these methods. The paper begins by providing a
succinct overview of these topologies. Next, it proposes a novel modified topology
and simulates this new approach and the traditional single inductor-based method
using MATLAB/Simulink. The energy delivered, consumed, and losses are then
examined. Lastly, the balancing topologies are compared based on various factors
such as application, circuit design, balancing speed, complexity, cost, energy deliv-
ered, balancing system efficiency, energy loss, and more. The simulation results are
thoroughly analyzed, and conclusions are drawn accordingly.
2 Existing Work: Literature Review
The Battery Management System (BMS) is critical in ensuring the balance of all
cells in a Battery Energy Storage System (BESS). A uniform State-of-Charge (SOC)
for the pack and individual cells is essential, as significant imbalances could result in
safety hazards [13]. Cell balancing must occur during these processes to maximize
energy delivery or release during charging or discharging [14].
The BMS employs the cell equalization technique to achieve consistent charge
levels, which involves dissipating the excess charge as heat or transferring it to the
less charged cells [15]. Reference [16] recommends incorporating control measures
within each battery module to enhance the overall performance of the whole pack
by influencing individual cell conditions. Passive [17] and active balancing [18] are
the two methods of cell equalization, with the former dissipating surplus charge as
heat and the latter transferring excess charge from highly charged cells to those with
a lower charge.
2.1 Passive Balancing
The energy dissipation from high-energy cells is a reliable and straightforward

approach to cell balancing. Passive balancing achieves this by dissipating the excess
energy of high SOC cells through shunt resistors. The extra energy from the higher
SOC cells bypasses as current through the resistors until their level becomes equal to
that of lower SOC cells. It has advantages like easy implementation, low complexity,
low costs, and easy control algorithms. While passive balancing is a straightforward
and reliable approach to cell balancing, it has limitations. Since the excess energy in
the high SOC cells is dissipated as heat, cell cycle efficiency is reduced. Additionally,
thermal problems may arise if the balancing currents are very high [19].
The passive balancing method can be categorized as fixed and switched resistor
balancing. These methods differ in connection or disconnection of shunt resistors by
controlling switches. These methods may be implemented with dissipating current
smaller than 10 mA/Ah, that is, for low-power applications [24].
Each cell has a shunt resistor to dissipate the extra charge in fixed resistor
balancing. The shunt resistors are adjusted to limit the cell voltage and SOC [20]. This
method can also be implemented in lead-acid and nickel-based batteries [21]. The
balancing speed is slow. In switched resistor balancing, a control switch is connected
to the shunt resistors, allowing control of the current flowing through the resistor [22].
In imbalance, the control algorithm controls the resistance. This method is highly
efficient compared to fixed resistors and is simple and reliable [23]. It is suitable for
use with Li-ion batteries.
2.2 Active Balancing
In active balancing, higher SOC cells’ energy is transferred to lower SOC cells
with loss [25, 26]. It uses energy storage components, like transformers, converters,
capacitors, and inductors, which act as an intermediate bridge for storing charges from
higher SOC cells and then transferring them to lower SOC cells. The main advantages
of active balancing involve using the energy available in the battery more efficiently.
However, the implementation of this method involves complex configurations and
control algorithms.
Inductor Based Topologies
In this topology, energy is transferred using inductors [27]. Inductors store and
balance energy among cells, taking less balancing time. Filter capacitors may be
used across the cells to filter out the high frequency due to the high switching
frequency [28]. Two main topologies of the equalization circuits exist based on
the number of switches and inductors used. These are the single inductor topology
and the multi-inductor topology [29].
A single inductor balancing circuit uses a single inductor for energy transfer
within the pack, as shown in Fig. 3 [30]. The control architecture captures the cell
with the highest and lowest SOC; hence, they transfer energy. Diodes are connected
in series with the switches to avoid any possible short circuits. Control algorithms
are complex, and balancing speed is suitable [31].
Figure 4 shows a multi-inductor balancing circuit, where n cells are balanced
using n-1 inductors and 2n − 2 switches. The controller senses imbalance, and
hence higher cells are switched on first. In this method, the adjacent cells can be
balanced directly. Hence, it takes a high-energy loss and balancing time due to many
energy conversions [32].
Fig. 3 Single inductor-based cell balancing topology

Fig. 4 Multiple inductor-based cell balancing topology
Capacitor Based Topologies

This topology uses capacitors for shuttling energy within the cells [33]. Generally,
these capacitors are typically connected in parallel across the cells.
As shown in Fig. 5, switched capacitor balancing typically employs n − 1 capaci-
tors to balance n cells. While the control strategy is simple, the balancing time is typi-
cally higher, particularly when more cells are connected in a series configuration [34].
Double-tiered switching capacitor balancing method is shown in Fig. 6 [35].
The double-tiered method uses two capacitor tiers for energy shuttling. Hence,
the balancing time reduces comparatively as more switched capacitors are used.
However, more capacitors increase the balancing circuit battery size and cost [36].
Transformer Based Topologies
Transformers are a reliable component that is the intermediate bridge for transferring
energy from one cell to another [37].
A single-winding transformer, also known as a “switched transformer,” as shown
in Fig. 7, is a selectable energy converter [38]. The energy is transferred from one
cell to the transformer and then to the weak cells.
Fig. 5 Switched capacitor cell balancing topology

Fig. 6 Double-tiered capacitor cell balancing topology
Fig. 7 Single winding transformer cell balancing topology
The multi-winding transformer-based method, shown in Fig. 8, has one core and
one primary winding connected to the battery pack and several secondary windings
connected to each cell along with diodes [39]. This method has a complex magnetic
design as the number of windings increases, and the size, cost, saturation problem,
and complexity of algorithms also increase with the number of cells and secondary
windings.
Figure 9 shows the multiple transformer method with multiple transformers [40].
The typical configuration for transformer-based balancing involves connecting the
transformer’s primary windings in parallel, whereas the secondary windings of the
transformer to the cells via series diodes. The number of cells can be increased
easily, and this method is often preferred for implementing modular design, but
bulkiness, costs, and saturation problem rises as the number of transformers required
also increases.
Fig. 8 Multiple winding transformer cell balancing topology
Fig. 9 Multiple transformer cell balancing topology
Converter Based Topologies

These topologies use energy converters like Buck, Boost, Cûk, Buck-Boost, Flyback,
Full-Bridge, Ramp, Quasi-Resonant converters, and so on [41]. An essential advan-
tage of this topology is its ability to manage individual cells effectively. They are
fully controlled, flexible, and have quite complex control algorithms. Sometimes
intelligent control is also required.
A switch matrix and a converter can selectively balance any battery cells [42].
This method’s advantages are the simplicity of modularization and good balancing
speed. Implementing effective logic control is crucial for preventing short circuits
and safe operation of the cell balancing system. Although converter-based topologies
give optimum solutions, these systems are costly and complex [43, 44] (Fig. 10).
Fig. 10 Converter cell balancing topology

Table 1 Advantages and disadvantages of different cell balancing topologies

Fig No Advantages Disadvantages
3 Good equalization speed; Good efficiency Complex control is required
4 Moderate equalization speed Filtering capacitors required for high switching
current; complex control
5 Simple control; requires one capacitor with The acceleration of the equalization process
minimal switches necessitates intelligent control
6 Satisfactory balancing speed than single Complex control is required; high number of
switched switches
7 Low magnetic loss Highly complex control; core changes to add new
cells in the configuration
8 Good balancing time Complex magnetic design; high cost; satisfactory
efficiency
9 New cells can be easily added to the Expensive; complex control; bulky
configuration, fast equalization speed
10 Fully controlled, fast speed, flexible Costly, highly complex control, size increases,
process complex and intelligent implementation
Table 2 Comparison of different topologies for cell balancing

Fig No Balancing Complexity of Cost Size Charging/ Applications Efficiency
speed control Discharging
type
3 Good Complex Low Moderate Both Medium/High Good
4 Moderate Complex Medium Moderate Both Medium/High Medium
5 Low Complex High Bulk Both Medium/High Good
6 Very Low Moderate Medium Moderate Both Medium/High Good
7 Good Complex Medium Moderate Charge Medium/High Medium
8 Good Complex High Bulk Charge Medium/High Medium
9 Good Complex High Bulk Charge Medium/High Medium
10 Good Complex High Bulk Both Medium/High Good
Tables 1 and 2 provide a comprehensive comparison of various cell balancing

topologies. Table 1 highlights the pros and cons of each topology, while Table 2
focuses on balancing speed, efficiency, control strategy, and other related factors.
When selecting a cell balancing topology, the critical criteria are the control actions
and plan perspectives. The control techniques employed are identified by depend-
ability and activity methods, which include charge–discharge control [45]. Effective
control strategies result in greater reliability for the desired applications.
3 Proposed Topology
Figure 11 depicts the proposed system designed for balancing the battery cells. It uses
inductors as the intermediate bridge for removing imbalance. Each cell is connected
with an inductor in parallel after the array of switches and diodes. One more inductor
Fig. 11 Proposed modified inductor-based cell balancing method
is connected across the whole battery pack. The diodes and switches help control
the current direction and flow; the energy could move from higher cells to weaker
cells. To balance a battery pack consisting of n cells, the proposed system requires
n + 1 inductors and 2n switches. The inductors connecting batteries transfer power
to the nearby batteries. The inductor connecting the inductor helps to speed up the
energy transfer process between the inductors. The proposed approach uses two more
inductors and switches than the multi-inductor topology.
However the balancing speed of multi-inductor topology is slow. Moreover, the
multi-inductor-based topology uses a more complex algorithm [32], with more
incurred losses [46] than the single inductor-based method. Hence, the single inductor
method is superior to a multi-inductor-based method in terms of losses incurring
within the circuit, complexity, and so on [47]. As a result, the proposed methodology
is also compared to the single inductor method.
The control algorithm is shown in Fig. 12. It estimates the SOC for each cell and
checks for any differences. When the algorithm senses differences, the higher cells
energize the weak ones. The inductors act as the medium of transfer and the intensity
of the transfer depends upon the existing SOC differences.
Energy meters are connected across each component to measure energy exchange
between the cells and losses incurred in the various parts of the balancing circuit. The
energy meters consist of a voltmeter connected across the component and an ammeter
connected in series. The product of the measured values is taken and integrated
throughout the time till equalization. The energy can be calculated as (1).
The system used for the study has the following details:
Number of Batteries: 4
Battery Rating: Li-Ion, 3.7 V, 5.4Ah
Inner Inductor Rating: 200, 300, 400, 500 mH
Outer Inductor Rating: 200, 300, 400, 500 mH.
Fig. 12 Control algorithm

of inductor-based cell
balancing flowchart
{tbal
E= V I dt (1)
0
Here, E is the measured energy, voltage across the component is V, current through
the component is I, and t bal is the required balancing time.
The effectiveness of the modified multi-inductor approach is assessed through

a simulation-based evaluation. The system, as detailed above, is simulated on
SIMULINK on a CORE i5 8th Gen with 8 GB RAM Laptop. Three cases have been
taken, which consist of different SOC levels of four Li-On Cells. The performance
is analyzed considering three cases:
– Case-I: The cells’ initial SOC are 87, 93, 94, and 88%.
– Case-II: The cells’ initial SOC are 90, 92, 89, and 87%.
– Case-III: The cells’ initial SOC are 90, 89, 88, and 87%.
The cases considered generate different scenarios for different batteries. In each
case, different values of inductors are also checked. The value of the inductor remains
the same for all the inductors. The results for the proposed approach are compared
to that of the single inductor approach.
Figure 13 shows the results for Case-I. It shows a significant reduction in the
time required to balance the cells. With the single inductor method, the time taken is
Fig. 13 Results for case 1, a time taken for cell balancing, b percentage charge transfer, c energy
transfer factor, and d energy exchange within the cells and losses incurred within the balancing
circuit
Fig. 14 Current flowing through the outer inductor for case-I (500 mH)
Fig. 15 Results of
simulation for case 2, a time
taken for cell balancing,
b percentage charge transfer,
c energy transfer factor, and
d energy Exchange within
the cells and losses incurred
within the balancing circuit
Fig. 15 (continued)
about 70–80 s, whereas it remains less than 67 s with the proposed method. The time
also increases with an increase in the inductor size for the single inductor method,
whereas it remains the same with the proposed method. The energy transfer factor
also remains high with the proposed method, showing that the proposed method
transfers more power as compared to the single inductor approach. The percentage
charge transfer also remains high. The energy loss also remains slightly lower. The
current flowing through the inductor is shown in Fig. 14. Similar pattern is observed
with the current of the other inductors. Due to limitations of page, only one case with
500 mH is shown.
Figures 15 and 16 illustrate the simulation results for Cases II and III, respectively.
Both figures show a similar trend to that of Fig. 13.
The proposed topology uses the same switching algorithm applied for single
inductor-based topology. The results show that the balance of the battery system using
the proposed topology is faster than the single inductor-based topology. Moreover,
the overall losses occurring across the switches, diodes, inductors, and load are found
to be less for the proposed topology. The charge transferred to weak cells from higher
cells is also more. The energy transferred from higher SOC cells and delivered to
lower SOC cells is also more than the single inductor.
Fig. 16 Results of simulation for case 3, a time taken for cell balancing, b percentage charge
transfer, c energy transfer factor, and d energy exchange within the cells and losses incurred within
the balancing circuit
5 Conclusion
Balancing has been one of the most critical factors in developing and implementing
a safe, smooth, and efficient battery management system, as imbalances can cause
serious issues. According to the usage, balancing methods must be chosen by
considering the factors like complexity, size, cost, speed, efficiency, and design.
This paper proposes a simple modified multi-inductor-based active cell equaliza-
tion technique. The methodology uses an inductor across each cell after the array of
switches and diodes. Both the proposed and conventional methods are implemented
with the same control algorithm. The system is simulated on Simulink. The results
show that the balance of the battery system using the proposed topology is faster than
the single inductor-based topology. Moreover, the overall losses occurring across the
switches, diodes, inductors, and load are found to be less for the proposed topology.
The amount of charge transferred to the weak cells from the higher cells is also more.
The amount of available energy transferred from the higher SOC cells and delivered
to lower SOC cells is also more than the single inductor.
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0405
Design and Hardware Implementation
of Fuzzy Logic Controller for Boost
Converter for Battery Charging Using
dSPACE
K. S. V. Phani Kumar, Vishwanatha Siddhartha, Kalluri Deepika,

and Sonnati Venkateshwarlu
Abstract Maintaining desired output voltage level is a critical feature required for
a boost converter. The controller’s response is critical to analyze a converter’s per-
formance and ability. This paper analyzes closed-loop control of the boost converter
with PI and Fuzzy Logic Controllers using MATLAB Simulink and dSPACE 1104
platforms in a Hardware in-loop environment. To make it a test bench, hardware
is developed using Proteus software, where the inductor, capacitor, and load (bat-
tery) terminals are available. The switching frequency used is 20 kHz. Tuning of
the controller parameters is carefully carried out to achieve the best performance
possible. The response obtained for a step change in the input is studied with an
individual controller in action. The error between actual and desired output voltages
is observed during the transient and steady-state conditions. It is found that the Fuzzy
logic controller delivers the fastest response among them.
Keywords Boost converter · dSPACE · PI controller · Fuzzy logic controller ·

Hardware-in-Loop (HIL)
1 Introduction
Battery charging is essential in almost every industry these days. Proper battery
charging is essential for battery health and thereby reducing maintenance costs.
K. S. V. Phani Kumar (B) · V. Siddhartha · S. Venkateshwarlu

Electrical and Electronics Engineering, CVR College of Engineering, Ibrahimpatnam 501510,
Hyderabad, India
V. Siddhartha
S. Venkateshwarlu
K. Deepika
Supply Chain Management, University of Manitoba, Winnipeg, Canada
344 K. S. V. Phani Kumar et al.
Therefore, the converters in such charging applications play a critical role in efficient
and reliable operation. DC-DC Converters, especially boost converters, are mostly
used in many battery charging applications where the desired output voltage must
be more than the input voltage [1]. With the advancement in the availability of
components that work for higher switching frequencies, the converter’s performance
has significantly improved.
The boost converter can be controlled in two ways (i) Open Loop and (ii) Closed
Loop. The best performance can be achieved when the closed-loop operation is
performed. Researchers in the literature have widely used a PI control method to
achieve the desired outputs [2, 3]. But in recent times, many topologies and advanced
algorithms have been applied to achieve superior boost conversion performance. One
such kind is the Fuzzy Logic Controller (FLC). FLCs are developed based on the set
theory and use the programmer’s experience to tune the outputs to the inputs given
by the user. It has been demonstrated in the literature that fuzzy systems can develop
reliable outputs with a faster response time. Its robust operation makes it applicable
to most applications [4–8].
In this paper, a boost converter test bench is developed for a switching frequency
of 20 kHz. The conventional boost converter topology is selected here. The PCB is
designed by using the Proteus software. The converter is analyzed in closed-loop
control with PI and Fuzzy Logic Controllers using MATLAB Simulink and dSPACE
1104 platforms in a Hardware in-loop environment. The response obtained for a step
change in the input is studied with and without the controller. The converters are tuned
in such a way as to achieve the best performance. The errors in the output voltage
are examined in both transient and steady-state conditions. A detailed investigation
is presented. Overall, a practical approach to designing and implementing a DC-DC
boost converter for battery charging applications is presented in this paper, which
can be helpful for researchers and practitioners in power electronics.
2 Methodology
The Boost converter circuit topology considered in the paper is shown in Fig. 1. The
operation of this boost converter involves switching on and off the MOSFET so that
the inductor is charged and discharged. Since the discharge time is less, the energy
stored in the inductor must be released quickly. So, the voltage is boosted and given
to the capacitor connected at the end. The voltage accumulated at the capacitor forms
the source of the load (battery). The graphical representation of the effect of duty
cycle change on the output voltage is given in [9].
Design and Hardware Implementation of Fuzzy Logic Controller … 345
Fig. 1 Boost converter circuit
2.1 PI Controller
The traditionally known and most widely applied controller is a Proportional Inte-
gral Controller. It is known for its robust and diverse applications. This closed-loop
application works on the error e(t) between the desired value (DV) and actual values
(AV) of the feedback signal as shown in Eq. 1. This error is applied as an input to the
PI controller. Then the output u(t) is calculated based on the Eq. 2.
. e(t) = AV (t) − DV (t) (1)
This error is applied as an input to the PI controller. Then the output u(t) is
calculated based on the Eq. 2.
. u(t) = K p e(t) + Ki
s
e(t) (2)
Where, . K p = proportional gain, . K i = integral gain.

The controller used here is discrete since the signals generated are sample-based.
The integral of the error is calculated by storing the previous value and summing it
up with the change proposed by the controller. This can be represented by the Eq. 3.
. u(t) = u(t − 1) + Δ u(t) (3)
where, u(t) = PI control variable, .Δu(t) = PI controller output.
2.2 Fuzzy Logic Controller (FLC)
The fuzzy logic controller was developed for obtaining closed-loop control of the
output DC Voltage is presented in this section. The PWM control technique is a non-
linear approach to obtain the desired value of output voltage magnitude. It is a small
signal model-based approach. The main aim here is to maintain the error between
the set value and the actual value of load (battery) voltage to be zero. Deriving a
mathematical model may not be appropriate for the same to have quick and desired
outputs.
A fuzzy logic controller is designed to accept real-world variables and convert
them to crisp values for further processing. In the present scenario, the inputs con-
sidered are the error and the error rate. Here error corresponds to the difference
between the actual output voltage value at the load (battery) terminals and the set
voltage value the user decides. The output would be the amount of updation needed
in the modulation index value to determine the pulse width and hence the charg-
ing and discharging times of the inductor placed in the circuit. The Block diagram
representation of the Fuzzy simulation environment employed in the work done is
shown in Fig. 2. Here, the approach used to generate the the modulation index of the
PWM pulse is described. The actual value of output, i.e., the load (battery) voltage,
is given by the voltage sensor placed in the hardware to ADC, while the set value
is given using the DAC through dSPACE Control Desk. This error is calculated at
the summation point, and the same is given to the fuzzy logic controller (FLC) as
one of the inputs. This error value is subtracted from the previous error value using
a unit-delay function to obtain a change in the error signal as shown in Eq. 4.
. Δ e(t) = e(t) − e(t − 1) (4)
where, e(t) = error value, .Δ e(t) = change in the error value, dt = change in
time.
This is given as the second input signal to FLC. The output of FLC is the change
in the Modulation index (Mi) value. This must be added to the previous Mi value
to obtain the new value. The previous value is obtained using a Delay function. The
obtained new Mi value is now fed to the PWM generation block available in the
Simulink library.
Once the input values are converted to crisp values based on the membership
functions of the inputs, they are sent to the Rule Base, where they are analyzed
further. A mapping is done between the inputs and outputs based on the rules so that
the crisp value of the output value is obtained. Figure 3 gives the rule base used in
the designed FLC. The weightage given for each rule is also specified.
These rules can be visualized using the surface view option available in the MAT-
LAB toolbox environment, as shown in Fig. 4. For realizing the hardware, Proteus
software is used to design the PCB. The layout designed for the circuit considered
in Fig. 1 is given in Fig. 5.
The developed boost converter hardware is shown in Fig. 6 with the labels specify-
ing the components placed on the PCB. A Yokogawa scope coder is used to obtain the
results as shown in Fig. 7. A Testbench environment is developed with the dSPACE
so that more experiments can be conducted.
Fig. 2 Block diagram representation of the simulation performed
Fig. 3 Rules considered for FLC
3 Results Obtained
To start with, a PI controller is employed to get the closed-loop response of the

system. Initially, the boost converter input terminals are given a voltage of 3V from a
Regulated Power Supply present in the workbench. The controller is not switched on,
so the output is equal to the input voltage. When the controller is switched on, with a
set value of 5V, the boost converter has responded to the same and is developing the
required 5V output. This can be seen in Fig. 8 There is no peak overshoot observed
Fig. 4 Fuzzy logic controller design—surface view (3D)
Fig. 5 PCB layout generated using Proteus software for boost converter circuit
in the response. The firing pulse supplied, with the input and output voltage during
steady values are shown in Fig. 9.
Boost converter response when Fuzzy logic controller is applied is shown in
Fig. 10. It can be seen clearly that the response is much faster and there is no overshoot
detected. The Step changes are rapidly given, as shown in Fig. 11, and the Current
drawn by the load (Pink line) is also shown. The green line shows the error with a
standard deviation of only 0.012 V.
Fig. 6 DC-DC converter hardware developed
Fig. 7 Overall hardware system developed for conducting HIL operation

Fig. 8 Response of PI controller to the step input applied
Fig. 9 Input, output, and pulses captured during steady state

Fig. 10 Response of Fuzzy controller to the step input applied
Fig. 11 The error response for changing set value and the current drawn by the load
4 Conclusions
The aim is to maintain the desired output at the terminals of the boost the converter
has been achieved. The controllers considered (PI and Fuzzy) are tested in the hard-
ware system developed under a closed-loop system. MATLAB Simulink the model
developed with the extension to dSPACE 1104 platform is implemented with both
controllers. Hence a test bench is now set up to perform various operations and exper-
imentations regarding the parameters of the boost converter and the controllers. The
step changes applied to the system are analyzed and the results obtained show the
dominance of the Fuzzy Logic Controller compared to the PI the controller in terms
of the transient time.
References
1. Tofoli FL, Pereira DD, de Paula JW, Oliveira Junior DD (2015) Survey on non-isolated high-
voltage step-up dc-dc topologies based on the boost converter. IET Power Electron 8(10):2044–
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phase characteristics. In: IEEE power and energy conference at Illinois. IEEE, pp 1–7. https://
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https://doi.org/10.1016/0165-0114(89)90118-8
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cation, Upper Saddle River
A Modified Direct Torque Control
of a Five-Phase Induction Motor
for Harmonic Current Elimination
and Reduction of Common Mode Voltage
C. Venkata Subbareddy and Swati Devabhaktuni
Abstract The classical hysteresis-based direct torque control (DTC) in five-phase

electrical drives is a simple and effective control scheme that exhibits superior
dynamics and less parameter dependency. It is necessary to eliminate harmonic (xy)
plane components while implementing any control scheme of five-phase induction
motors. In literature, most of the proposed lookup table-based DTC techniques of
five-phase induction motor focus on the reduction of torque ripple and flux ripple
and elimination/reduction harmonic plane currents and not focus on common mode
voltage (CMV) reduction. The proposed lookup table-based DTC uses only small and
large voltage vectors of the 2-level 5-leg inverter, which provides the lowest CMV
along with torque and flux ripple reduction. A modified lookup table-based DTC is
implemented to control the five-phase induction motor which eliminates harmonic
plane currents and minimizes the CMV along with the torque and flux ripple reduc-
tion. The effectiveness of the proposed DTC technique is verified by simulating the
model in the MATLAB/Simulink software.
Keywords Five-phase Induction motor · Lookup table-based DTC · Common

mode voltage
1 Introduction
Multi-phase electrical machines [1, 2] are best suitable for high-performance elec-
trical drive applications due to their overwhelming advantages such as high fault-
tolerant capability, high torque density, reduced per-phase power, and smooth oper-
ation [3–5]. Recently, several researchers started to focus on the control of five-
phase induction motors with superior control schemes such as direct torque control
C. Venkata Subbareddy (B) · S. Devabhaktuni

National Institute of Technology Warangal, Warangal 506004, India
S. Devabhaktuni
354 C. Venkata Subbareddy and S. Devabhaktuni
schemes, predictive torque/current control schemes, and field-oriented control

schemes due to advancements in power converter switches and fast digital controllers
[6, 7]. Multi-phase induction motors are used in electrical vehicular applications, ship
propulsion, and electric aircraft applications [8, 9]. The lookup table-based DTC tech-
nique is a simple and effective method in classical 3-phase drives which provides fast
dynamics and less parameter dependency when compared with other methods such as
FOC, and PTC schemes [10]. Several research works are implemented to overcome
the shortcomings of the classical DTC method such as high torque and flux ripple and
variable switching frequencies. A detailed analysis has been done about the effect of
switching vectors on stator flux and the developed torque of induction motors [11,
12]. The 2-level five-leg inverter switching vectors are placed in two independent
fundamental (αβ), and harmonic (x-y) planes [13]. The fundamental plane compo-
nents are only responsible for the production of useful torque and harmonic plane
components create only ohmic losses. There forth it necessitates the elimination
of harmonic plane components while implementing any control scheme for 2-level
inverter-fed 5-phase induction motors [14]. So, the advanced control schemes cannot
be directly implemented for five-phase induction motors because of the existence
of harmonic plane components which create unnecessary power loss. In literature,
several research works have been done to control the five-phase induction motors to
get better steady-state performance with the elimination of harmonic plane compo-
nents [15–21] [22–25]. In [15], a space vector modulation technique is implemented
to generate sinusoidal voltages in a five-phase VSI. An SVM-DTC technique is
implemented in a five-phase induction motor [16], which eliminates harmonic plane
components with proper switching patterns and suffers from slow dynamics and
more PI controllers. Parsa et al. implemented a lookup table-based DTC with a large
vector on five-phase induction motors [17] which suffer from drawbacks associated
with classical DTC [10] and harmonic plane components are not eliminated. In [18],
Gao et al. implemented a DTC with a modified lookup table such that it minimizes
the harmonic plane components and still suffers from the complex algorithm and
won’t eliminate harmonic plane components. Reference [19], discusses the modified
DTC with multiple lookup tables to reduce torque and flux ripple and it produces
all levels of common mode voltages. Reference [20] implements a modified lookup-
based DTC to mitigate CMV to the lowest level with the usage of only large vectors.
Reference [21] uses three neighbor large vectors over one control period such that
the resultant voltage in harmonic plane components becomes zero and it produces
high flux ripple and current %THD.
The CMV is a severe issue in electrical machines as it is a source of electromag-
netic interference (EMI) and causes the mal-operation of protective overcurrent relays
in industrial drives. Common mode current also causes the ball bearings failure and
reduces the life span of machines [21]. Hence, it is important to reduce the common
mode CMV while implementing any control scheme in five-phase induction motors.
The proposed work reduces 80% of CMV with the use of one large and small voltage
vector over a control period in a 5-phase inverter for virtual voltage vector generation
in the lookup table-based DTC method and also reduces the torque ripple.
A Modified Direct Torque Control of a Five-Phase Induction Motor … 355
The five-phase VSI shown in Fig. 1 offers 32 switching states and is placed in
both the fundamental (αβ) plane and harmonic (xy) plane as indicated in Fig. 2. The
32 voltage vectors are divided into large (0.647V dc ), medium (0.4V dc ), and small
(0.247V dc ) and null vectors based on their magnitudes in both αβ-plane xy-planes
as in Fig. 2. The small vectors in αβ-plane will be seen as large vectors in xy-plane
or vice versa and medium vectors in αβ plane will appear as medium vectors in xy-
plane. Hence, the elimination or minimization of xy-plane components is necessary
while implementing any control scheme in a five-phase induction motor. A volt-
sec balance technique is implemented in [18] to eliminate xy-plane components by
Vdc/2 Sa Sb Sc Sd Se
o a b c d e
Vdc/2 S d' S e'
S a' Sb' S c'
a b c d e
Fig. 1 Two-level five-leg inverter with five-phase induction motor
β axis Y axis
Sector 4 Sector 3 Sector 4 Sector 3
V12 V28
V10 V26
Sector 5 V24 Sector 2 Sector 5 V2

V30 V8 V27 V18 Sector 2
V14 V11
V29 V14 V24 V30
V4 V13 V20 V8 V19
V26
V10 V3
Sector 1
V15 V22 V9 V16 V25 Sector 1 V9 V15 V25 V16 V22
Sector 6 V6 V6
α axis Sector 6 x-axis
V21 V12 V28
V5 V27
V11 V18 V1 V7 V17 V23
V2 V13
V17 V20
V7 V23 V1 V29 V4
Sector 7 Sector 10 Sector 7
Sector 10
V3 V19 V5 V21
Sector 9 Sector 8 Sector 9
Sector 8
αβ Plane xy plane
Fig. 2 Space vector location in fundamental (αβ) plane and harmonic (xy) plane
applying large and medium vectors with 0.632 and 0.368 times of control period T s
which produces the highest CMV.
2 Concept of Common Mode Voltage in a Five-Phase

Inverter
The common mode voltage (CMV) is the voltage between the mid-point of the DC
link voltage of the inverter and the neutral point of the machine. The CMV in a
five-phase inverter-fed drive is expressed as follows:
Vdc Vdc
Vcm = (Sa + Sb + Sc + Sd + Se ) − (1)
5 2
where
V dc = DC link voltage of five-leg inverter.
S a , S b , S c , S d , S e = inverter upper switches statuses (0 = off or 1 = on).
With the substitution of 32 inverter switching statues (0 or 1) in (1), six levels
of common mode voltages of (±V dc /2), (±3V dc /10), and (±V dc /10) appear. It is
observed that the large switching vectors (e.g.: 11001) and small switching vectors
(e.g.: 01001) will exhibit a common mode voltage level of (±V dc /10); the medium
switching vector (e.g.: 10000) exhibits a common mode voltage of (±V dc /10); and
null voltage switching vector produces common mode voltage levels of (±V dc /2).
And it is concluded that the large and small voltage vectors show lowest CMV of
(±V dc /10) and medium voltage vectors exhibit medium common mode voltage levels
of (±3 V dc /10) whereas null voltage vectors produce highest common mode voltage
levels of (±V dc /2). Hence, the switching states which produce the lowest CMV will
be used to minimize the torque and flux ripple while implementing the lookup table
DTC scheme of the five-phase induction motor.
The modified lookup table-based DTC uses the small and large vectors to generate
virtual voltage vectors to get lowest common mode voltage while eliminating xy-
plane currents and it will reduce the torque and flux ripple due to reduced resultant
vector magnitude.
3 Implementation of a Proposed Lookup Table-Based DTC

with Virtual Voltage Vectors and Lowest Common Mode
Voltage
The theory of virtual voltage vectors V 3 is introduced in [18] with the volt-sec balance
method to eliminate harmonic plane components. The proposed method uses the volt-
sec balance method to generate virtual voltage vectors such that it will produce zero
harmonic plane currents and the lowest CMV levels. As the magnitude ratio of the
large (e.g. state 22) voltage vector and small (e.g. state 25) voltage vector in the
harmonic plane is 1/0.382, the dwell time ratio of large and small vectors will be set
at 0.382 to construct zero mean vector in the harmonic plane as depicted in Fig. 3.
The resultant vector in the fundamental plane and the harmonic plane will be shown
in (2) and (3) respectively. The active virtual voltage vector generation is shown in
Fig. 3 and the resultant magnitude will be 0.4V dc . The virtual zero voltage vectors
V 0 will be generated from two opposite small vectors (i.e., 9 and 22) to eliminate
the highest level CMV with the original zero vector as shown in Fig. 4. The 10
V 3 are created from 10 large to 10 small vectors and zero V 3 are placed in space
as shown in Fig. 5. The zero voltage vectors synthesized from two opposite large
voltage vectors for equal dwell times over the control period such that it will produce
zero magnitudes to avoid large common mode voltage. If the switching vector lies
in sector 1 and a zero vector needs to select then vectors 25 and 6 will be selected to
form zero magnitude vectors. Thus the virtual vectors are generated such that they
will generate the lowest CMV.
The virtual voltage vector V 1 in fundamental (αβ) and harmonic (xy)-plane can
be obtained below
V1_αβ = t1 VL_αβ + t2 V L_αβ = 0.4Vdc (2)
V1_x y = t1 VS_x y + t2 V SL_x y = 0 (3)
β- axis y- axis
t2 t1 t1 t2
22 25 25 22
V1 α- axis V1 x- axis
(a) (b)
Fig. 3 Virtual voltage vector V 1 generation in both a αβ-plane and b xy-plane with the inverter
switching states 25 and 22
β-axis
y- axis
t2 t1 t1 t2
22 9 α-axis 9 22
V0 V0 x- axis
(a) (b)
Fig. 4 Virtual zero voltage vector V 0 generation in both a αβ-plane and b xy-plane with the inverter
switching states 9 and 22
β axis
Sector 4 Sector 3
V4 (12,18) V3 (28,11)
Sector 2
V5 (14,21) V2 (24,5)
Sector 5
Sector 1
V6 (6,9) V1 (25,22)
V0 α axis
Sector 6
Sector 10
V7(7,26) V10 (17,10)
Sector 7
V8 (3,20) V9 (19,13)
Sector 9
Sector 8
αβ Plane
Fig. 5 Virtual voltage vector with opposite small and large vector states
where V S = Magnitude of small vector = 0.2472V dc .

V L = Magnitude of large vector = 0.6472V dc .
t 1 = Dwell time of large vector = 0.723T s
t 2 = Dwell time medium vector = 0.276T s .
T s = t 1 + t 2 = control period.
The virtual zero voltage vector V 0 can be generated from two opposite small
voltage vectors i.e., vectors 9 and 22 as shown in Fig. 4.
V1_αβ = t1 VS_αβ + t2 V S_αβ = 0 (4)
V1_x y = t1 VL_x y + t2 V L_x y = 0 (5)
where V S = Magnitude of small vector = 0.2472V dc .

V L = Magnitude of large vector = 0.6472V dc .
t 1 = t 2 = Dwell time of large vector = 0.5T s .
T s = t1 + t2 = control period.
The lookup table for the proposed DTC method is shown in Table 1 where virtual
voltage vectors V 1 to V 10 are used. The voltage vector V 0 is a virtual zero voltage
vector that is generated from two opposite small vectors’ fundamental plane.
Figure 6 shows the schematic diagram for implementing the modified DTC control
scheme where the speed error is treated with the Proportional Integral controller and
Table 1 A lookup table of modified DTC method

Ψ stat T stat Ssectors
1 2 3 4 5 6 7 8 9 10
1 1 V2 V3 V4 V5 V6 V7 V8 V9 V 10 V1
0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0
−1 V 10 V1 V2 V3 V4 V5 V6 V7 V8 V9
−1 1 V5 V6 V7 V8 V9 V 10 V1 V2 V3 V4
0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0
−1 V7 V8 V9 V 10 V1 V2 V3 V4 V5 V6
Vdc
T* Te
Hysteresis Tstat +
ω*r + PI + Torque
controller
ωr T Controller Voltage
vector Switching 5 -PH
Ψse Hysteresis Ψstat
Ψs* selection table IM
+ Flux
Controller Table
Ψs
Inverter
Speed
Sector VaVb ..Ve Sensor
Stator iαs
Flux Clarke
& Torque Transformation
estimation i βs ia ib ..ie
Vαs
Vβs
Fig. 6 Implementation diagram of modified lookup table-based DTC
gets the demanded torque. The reference torque and flux are compared with the
measured values in hysteresis torque and flux controllers. Depending on the flux
status, torque status, and sector information switching voltage vector is selected
from the lookup Table 1.
4 Simulation Results Analysis
The superiority of the modified lookup table-based DTC control scheme is tested
and compared with the existing DTC method [18] through Simulink/Matlab soft-
ware with the same hysteresis bands and sampling time/control period. The
proposed method is tested under both low and high speeds for no load and
loaded cases. Figure 7 represents the torque flux responses for a speed of
120 rad/s under no load for existing DTC [18] and exhibits torque and flux ripple of
3.1 Nm and 0.06 Wb respectively. Figure 7 shows the response of flux and torque for
a speed of 120 rad/s for the proposed method under no load and shows reduced torque
and flux ripple of 2.4 Nm, and 0.045 Wb. From Figs. 7 to 8, it is concluded that the
modified DTC reduces both flux ripple and torque ripple under no load. Similarly,
Figs. 9, 10 shows the torque and flux pattern for high speed 120 rad/s under a load of
5Nm for both existing DTC [18] and modified DTC. The conventional DTC method
produces the torque ripple and flux ripples of 2.4 Nm and 0.066 Wb whereas the
proposed method shows reduced flux and torque ripple of 0.054 Wb and 1.8 Nm.
Figure 11 shows flux and torque pattern for a low speed of 20 rad/s under load of
5 Nm for the classical DTC and exhibits torque and flux ripple of 2.34 Nm and
0.066 Wb respectively. Figure 12 shows the flux and torque pattern for the low speed
of 20 rad/s under a load of 5Nm for the proposed control schemes and it is seen that
the modified DTC scheme exhibits lower flux ripple and torque ripple of 0054 Wb
and 1.56 Nm respectively under low speed and load cases.
Figure 13 indicates the CMV levels for a classical DTC scheme with the DC link
voltage of 300 V and it exhibits all levels of CMVs such as±(300/2), ±(3*300/10)
Fig. 7 Flux, and torque waveforms for a speed of 120 rad/s for classical DTC [18] under no load
Fig. 8 Flux, and torque waveforms for a speed of 120 rad/sec for proposed DTC under no load
Fig. 9 Flux, and torque waveforms for a speed of 120 rad/s for classical DTC [18] under the load
of 5 Nm
Fig. 10 Flux, and torque waveforms for a speed of 120 rad/s for proposed DTC under load of 5
Nm
and ±(300/10) as it used the zero vectors and medium vectors and large vectors
respectively. Similarly, Fig. 14 shows the CMV pattern of the modified lookup table-
based DTC and it gives the smallest common mode voltage (300/10) as it uses only
large and small voltage vectors for a dc link voltage of 300 V. Hence, the proposed
method exhibits lowest common mode voltage which improves the life span of the
machine. The machine parameters are given in Tables 2 and 3.
Fig. 11 Flux, and torque waveforms for a speed of 20 rad/s for classical DTC [18] under the load
of 5 Nm
Fig. 12 Flux, and torque waveforms for a speed of 20 rad/s for proposed DTC under load of 5 Nm
Fig. 13 Common mode voltage (CMV) for classical DTC method [18]
Fig. 14 Common mode voltage (CMV) for the proposed DTC method
Table 2 Results comparison

T_ripple F_ripple T_ripple F_ripple Max CMV
Speed (rad/s) 120 rad/s 20 rad/s
Load (Nm) 0 5 0 5 5 5 5
CDTC 3.1 2.4 0.06 0.066 2.34 0.066 ±150 V
Proposed DTC 2.4 1.8 0.045 0.054 1.56 0.054 ±25 V
Table 3 Machine parameters

Five-phase induction motor parameters
No. of poles (P) 4
Mutual inductance (L m ) 0.45 H
Stator inductance (L s ) 0.4893 H
Rotor inductance (L r ) 0.4893 H
Stator resistance (Rs ) 6.03 Ω
Rotor resistance (Rr ) 6.085 Ω
Inertia constant (J) 0.0048
Rated speed 1440 rpm
Inverter DC voltage (V dc ) 300 V
5 Conclusion
The proposed control scheme uses large and small voltage vectors for the proposed
lookup table-based DTC of an FPIM which gives the lowest CMV. The proposed
control scheme also reduces the torque ripple and flux ripple for different speeds
and different loading conditions when compared with the classical DTC method.
The proposed method is useful for increasing the machine life span as it gives the
lowest common mode voltage with reduced torque and flux ripple along with nullified
harmonic plane components.
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A Novel Approach Towards Performance
Analysis of Three Phase Two Level
Inverter
Papia Ray, Shreya Mohanty, and Arvind R. Singh
Abstract For three phase two level inverters, a comparison between Space Vector
Pulse Width Modulation (SVPWM) and Sinusoidal Pulse Width Modulation
(SPWM) is done. Sine Pulse Width Modulation (SPWM) and Space Vector Pulse
Width Modulation (SVPWM) are the most often used PWM techniques for three
phase voltage source inverters. To run the motor at its rated speed, we are specifi-
cally using the SPWM and SVPWM techniques to enhance motor speed and improve
performance. The excellent efficiency and minimal torque ripple of this vector control
approach, together with improved system performance, make it suited for use in high
performance motors. It has been found that switching occurs only once in SVPWM
when moving from one state to another in a switching sequence, which results in lower
switching loss. In contrast, multiple switching occurs in SPWM when moving from
one state to another, which increases switching loss and lowers efficiency. SVPWM
produces reduced Total Harmonic Distortion (THD), offers improved output quality,
and more effectively utilizes DC bus voltage. The MATLAB/SIMULINK program is
utilized to carry out the system analysis. In light of all the information we had gath-
ered, we consequently came to the conclusion that the Space Vector PWM technique
provides better comprehensive performance and efficiency when compared with the
Sine PWM technique. However, due to the advantages of the SVPWM technique,
it can be applied to solar-powered water pumping systems to increase their water
pumping effectiveness.
Keywords Voltage source inverter · Pulse width modulation · Sine pulse width
modulation · Space vector pulse width modulation · Total harmonic distortion
P. Ray (B) · S. Mohanty

Department of Electrical Engineering, VSSUT, Burla, Odisha, India
A. R. Singh
Department of EECE, University of Pretoria, Pretoria, South Africa
368 P. Ray et al.
Nomenclature
VSI Voltage Source Inverter

PWM Pulse Width Modulation
SPWM Sine Pulse Width Modulation
SVPWM Space Vector Pulse Width Modulation
THD Total Harmonic Distortion
PMSM Permanent Magnet Synchronous Machine
PF Power Factor
1 Introduction
Due to its efficiency, PWM is currently frequently employed in industrial areas. There
are various PWM techniques utilized for inverter switching. To boost motor perfor-
mance, we are specifically using the SPWM and SVPWM techniques to improve
motor speed. In the context of the suggested technique i.e., implementing an effi-
cient PWM technique to improve motor performance, a comparison between SPWM
and SVPWM is made [1].
1.1 Pulse Width Modulation
PWM is especially well suited for operating inertial loads like motors since they are
less susceptible to this discrete manner of switching. The aim of the Pulse Width
Modulation is to regulate the load, but for smooth control, the PWM switching
frequency must be properly chosen. PWM, also known as pulse-duration modulation
(PDM), is a technique for regulating the average power of the electrical signal. The
supply is switched between the value of 0 and 100% at a rate quicker than it takes
the load to alter appreciably in order to regulate the average value of voltage and
current provided to the load. The total power provided to the load increases with the
length of time as the switch is on. Depending on the application and load, the PWM
switching frequency can change significantly. The load is smoothly controlled when
a too high switching frequency is chosen for the application, but it may hasten the
premature breakdown of the mechanical control parts. Load oscillations result from
choosing a too low switching frequency for the application. The key benefit of PWM
is having an extremely low loss in power in the switching devices. Almost there is
zero current flowing through a switch when it is in off condition, and there is almost
zero voltage drop across the switch while power is transmitted to the load. Therefore,
loss in power is almost zero in both of the situations because it is the product of the
voltage and the current. PWM also performs well with digital controls, which helps
in quick determination of the required duty cycle due to their on/off nature.
A Novel Approach Towards Performance Analysis of Three Phase Two … 369
1.2 Sine Pulse Width Modulation
A typical PWM method is sinusoidal PWM. In this PWM approach, the switching
states for each pole in the inverter are determined by comparing the AC voltage
reference which is in sinusoidal nature with the triangular carrier wave which has a
high frequency in real time. The switching states for each pole can be identified after
comparison. The desired reference voltage waveform is referred to as the modulating
wave in carrier-based PWM systems. Additionally, a wave that has been modulated
by another wave is known as a carrier wave or carrier. Typically, the modulating
wave is significantly lower in frequency than the carrier wave. The most popular
carrier waveform in the PWM technique for modulating AC voltage is the triangle
waveform. On the other hand, the PWM approach allows for the use of various modu-
lating waveforms. The modulating waveform used in typical SPWM uses sinusoidal
waveforms.
1.3 Space Vector Pulse Width Modulation
The field-oriented control for the induction motor and the permanent magnet
synchronous motor (PMSM) frequently use the space vector modulation technique
(SVM). The pulse width modulated signals produced by space vector modulation are
used for controlling the switches of the inverter, which in turn generates the neces-
sary voltage in modulated form to drive the motor at the required speed or torque
[2]. Another name for the space vector modulation is called space vector pulse width
modulation (SVPWM). The reference signal is sampled on a regular basis in space
vector modulation, a PWM control algorithm for multi-phase AC generation. After
each sample, non-zero active switching vectors next to the reference vector and one
or more zero switching vectors are chosen for the proper portion of the sampling
period in order to synthesize the reference signal as the average of the used vectors.
An estimated voltage vector for any type of magnitude, at any type of position, within
the space vector hexagon is created by combining the switching states that tune with
the fundamental space vectors for direction and the null vectors for magnitude. Any
vector of voltage with varied magnitude and varied direction is possible for every
PWM period by manipulating the switching sequences, and consequently the ON
time durations of the pulses. In order to create a constantly rotating space vector, the
space vector modulation technique aims in producing switching sequences which
match the reference vector of voltage for every period of PWM. Fixed switching
frequency, less harmonic content, and greater DC bus utilization are the key benefits
of the SVPWM technique. When compared to the traditional PWM approach, the
utilization of the DC bus voltage is 15.15% more efficient. According to the SVPWM
operating theory, the lower transistor is turned off when the higher transistor is turned
on.
370 P. Ray et al.
1.4 Voltage Source Inverter
The Voltage Source Inverter (VSI) has proved to be more effective and affordable,
takes up less area, has a quicker dynamical reaction for the sudden alterations in
torque or speed, and also can operate a motor without any de-rating. A typical VSI
of three phase consists of a single diode rectifier (or SCR bridge rectifier in the case
of DC output voltages of variable nature) that converts AC lines to DC, it also has a
parallel capacitor DC link that helps in storing system energy and controls the DC
bus voltages, also an inverter made up of insulated gate bipolar transistors (IGBTs)
that produces output frequency of variable nature based on the switching technique
and the applied reference voltage. The three phase inverter’s operating principle is
that it has three single-phase inverter switches, each of which can be linked to a load
terminal. The proposed VSI model as shown in Fig. 1 depicts the circuit diagram
representation of 3-phase voltage source inverter.
Figure 1 concludes the circuital representation of 3-phase voltage source inverter.
S1 to S6 are six switches in three phase VSI which when activated through gate pulse
give some output which again acts as input to PMSM drive.
The rest of the paper is arranged as: Sects. 2 and 3 give an idea of SPWM &
SVPWM schemes respectively. In Sect. 4, a brief explanation about the proposed
method and result analysis is given. Section 5 depicts application of the proposed
method and Section 6 draws the conclusion.
2 SPWM Technique
This method generates a digital signal and modulates the duty cycle so that the
waveform’s average voltage resembles a pure sine wave. According to the common
carrier triangular wave shape, each modulating voltage behaves as an independent
Fig. 1 Voltage source inverter model with permanent magnet synchronous motor drive
signal. The switching states of each pole in the inverter are determined by comparing
the reference wave to the carrier signal and using the following rules,
• If Vref ≻ Vc then upper switches i.e. (S 1 , S 3 , S 5 ) are turned ON (with pole voltage
of = V2dc ) where, Vref = The Reference Voltage; Vc = The Carrier Voltage.
• If Vref ≺ V then lower switches i.e. (S 4 , S 6 , S 2 ) are turned on (with pole voltage
of = − V2dc )
The condition required for SPWM technique is that the amplitude of the reference
voltage Vref must remain lower than the peak value of the carrier triangular wave Vc ,
i.e. Vref ≤ V2dc .
Vdc
V01 = M I sin ωt (1)
2
where, V01 = Fundamental component of output voltage.M I = Modulation Index.
V01 = Vref sin ωt (2)
Since Vref ≤ V2dc , from Eqs. (1) to (2) range of M I is found to be, 0 ≤ M I ≤ 1,
which is called as linear modulating range because, in this type of range the output
of the inverter is linearly proportionate to reference voltage Vref .
3 SVPWM Technique
According to this method, the chance of switches in VSI being on or off is used to
calculate the phase voltage.0 indicates that the bottom switch is on while the upper
switch is off, while 1 indicates the opposite. The Clark Transformation is used to
divide the three phase voltage into two phases, which is subsequently transformed
into polar form.
[ ] [ ]⎡ V ⎤
a
Vα 1√− 21 −√21 ⎣ Vb ⎦
= (3)
Vβ 0 23 − 23
Vc
/
( )2
Vr = (Vα )2 + Vβ (4)
( )
−1 Vβ
α = tan (5)
Vα
From Eq. (3) the two-phase voltage is obtained and from Eqs. (4) to (5) the
resultant voltage Vr and angle α are obtained respectively.Vr is a rotating vector in
the 360° space and it has magnitude and angle at any instant.
372 P. Ray et al.
Based on the probability of switches, the voltage Space Vector is estimated with
the three phase voltage, reference voltage, and angle as concluded from Table 1.
As shown in the above Fig. 2 the voltage space vector V0 and V7 are in inactive
states means, no output is obtained from the inverter at these states. There are 6 active
states which lead to voltage output in the VSI. For any angle α and sector k,
( )
2Tperiod K ×π
Ta = √ Vr sin −α (6)
3Vdc 3
( )
2Tperiod (K − 1) × π
Tb = √ Vr sin α − (7)
3Vdc 3
T0 = Tperiod − Ta − Tb (8)
From Eqs. (6) to (8) the time period for switching sequence is calculated.
Table 1 Phase voltage, resultant voltage, and angle according to probabilities

Space vector S1 S2 S3 Van Vbn Vcn Vr α
V0 0 0 0 0 0 0 0 0
V1 1 0 0 2
3 Vdc − 31 Vdc − 13 Vdc Vdc 0
V2 1 1 0 1
3 Vdc
1
3 Vdc − 23 Vdc Vdc 60
V3 0 1 0 − 13 Vdc 2
3 Vdc − 13 Vdc Vdc 120
V4 0 1 1 − 23 Vdc 1
3 Vdc
1
3 Vdc Vdc 180
V5 0 0 1 − 13 Vdc − 31 Vdc 2
3 Vdc Vdc 240
V6 1 0 1 1
3 Vdc − 23 Vdc 1
3 Vdc Vdc 360
V7 1 1 1 0 0 0 0 0
Fig. 2 Visualization of
space vectors
Table 2 Symmetrical
Section Ts1 Ts2 Ts3
SPVWM time table
T0 T0 T0
1 Tperiod − 2 2 + T2 2
T0 T0 T0
2 2 + T1 Tperiod − 2 2
T0 T0 T0
3 2 Tperiod − 2 2 + T2
T0 T0 T0
4 2 2 + T1 Tperiod − 2
T0 T0 T0
5 2 + T2 2 Tperiod − 2
T0 T0 T0
6 Tperiod − 2 2 2 + T1
3.1 SVPWM DC Bus Utilization
When the peak value of the line voltage equals the DC bus voltage, the limit of the
linear modulation region, also known as maximum DC bus utilization, is reached.
√
3 1
Vr,linerms = √ Vr,phase max = √ Vdc = 0.707Vdc (9)
2 2
where, Vr,linerms = Line to Line RMS Voltage; Vr,phase max = Phase output maximum
peak voltage; While for SPWM,
Vr,linerms = 0.612Vdc (10)
From Eq. (9) to (10) it is found that the DC bus utilization in case of SVPWM is
15.5% more than that of SPWM [3–5].
3.2 Generation of Appropriate Switching PWM Signals
Switching is kept to a minimum while moving from one state of the voltage space
vector to another in order to reduce switching losses [6, 7].
The switching sequence is generated using Table 2.
4 Description of Proposed Method and Result Analysis
4.1 Sine PWM
The most often used method for creating pure sinusoidal signals is SPWM. In Sine
PWM, there is a digital waveform that is created, and the modulation of duty cycle
occurs in order to resemble the waveform’s average voltage as a pure sine wave. The
374 P. Ray et al.
Fig. 3 Simulink model of the sine PWM
harmonic components of the voltage are moved to the higher frequencies using this
Sine PWM. The SPWM approach compares each modulating voltage to the common
carrier triangle waveform as a distinct signal. Figure 3 shows the MATLAB Simulink
model of the SPWM.
Figure 3 concludes the Simulink model which generates sinusoidal modulating
signal.
4.2 Space Vector PWM
SVPWM offers less THD and improved PF, making it the ideal computational method
of PWM for a voltage source inverter of three phase. According to the SVPWM
operating theory, the lower transistor is turned off when the higher transistor is
turned on. The output voltages are evaluated by turning the upper switches (S 1 , S 3 ,
S 5 ) ON and OFF. SVPWM offers an increase in maximum voltage of about 10–20%.
Figure 4 shows the MATLAB Simulink model of the SVPWM.
The modulating signal with third harmonic is generated as concluded from Fig. 4.
Figure 5 shows the working principle of SPWM and Fig. 6 shows the working
principle of SVPWM.
Figures 5 and 6 conclude the comparative analysis of the working principles of
SPWM and SVPWM. Now graphically we have compared the voltages, current,
torque, modulated wave, and carrier and reference wave of SPWM and SVPWM
which is shown below.
Fig. 4 Simulink model of the space vector PWM
Fig. 5 SPWM flow chart

376 P. Ray et al.
Fig. 6 SVPWM flow chart
4.3 Carrier and Reference Wave Comparison
Unlike pure sinusoidal reference wave in SPWM, the SVPWM technique contains
a third harmonic component leading to higher DC bus utilization as shown in the
Figs. 7 and 8.
The reference wave is compared with the carrier wave to generate the modulated
wave as concluded from Figs. 7 and 8.
Fig. 7 Carrier and reference

signal of SPWM
Fig. 8 Carrier and reference

signal of SVPWM
4.4 Measurement of Speed
The performance of PMSM drive is analyzed using the SPWM and SVPWM tech-
niques. The output speed obtained in case of SPWM and SVPWM is shown in the
Figs. 9 and 10 respectively.
The output speed is obtained from display in the SIMULINK model in case of
SPWM and SVPWM as 155.2 rpm and 176.7 rpm as concluded from Figs. 9 and 10
respectively.
Fig. 9 Rippled output speed

waveform of SPWM
378 P. Ray et al.
Fig. 10 Cleaned output

speed waveform of SPWM
4.5 Total Harmonic Distortion in Voltage
High harmonic content can produce heating effect in the motor increasing losses and
reducing efficiency. The Total Harmonic Distortion in voltage in case of SPWM and
SVPWM is shown in Figs. 11 and 12 respectively.
Fig. 11 % THD in voltage in SPWM
Fig. 12 % THD in voltage in SVPWM

The THD in voltage is compared and found to be lower in SVPWM as concluded

from the Figs. 11 and 12.
4.6 Total Harmonic Distortion in Current
High harmonic content can lower the power factor and harmonics in current can
increase the frictional loss. The THD estimation in current is done in case of SPWM
and SVPWM as shown in Figs. 13 and 14.
Therefore, this demonstrates that SVPWM is a more effective way than SPWM
since it has lower THD as concluded from Figs. 12 and 14, switching losses are
reduced, and it helps with effective DC bus utilization. All of them are clear from
the graphs comparing the two PWM techniques that are given above.
Fig. 13 %THD in current in SPWM
Fig. 14 % THD in current in SVPWM

380 P. Ray et al.
5 Application of SVPWM
As mentioned earlier the SVPWM has various advantages over SPWM. Advantages
of space vector PWM:
• With the space vector modulation method, each cell’s repeat switching only affects
one device, resulting in minimal switch consumption.
• To make calculations simpler, the three phase PWM wave is immediately
generated from the voltage space vector.
• The basic maximum value of the inverter output line voltage is the DC side voltage,
which is 15% higher than the output voltage of a typical SPWM inverter [8].
• Fixed switching frequency, low harmonic content, and higher DC bus utilization
are the primary benefits of the SVPWM method. When compared to the traditional
PWM technique, the use of the DC bus voltage is 15.15% more efficient [9–12].
SVPWM can be used to achieve effective outcomes in a range of models that
incorporate a three phase, two level inverter since it has advantages over SPWM.
As a result, we advise employing a 3-phase 2 level inverter to apply the SVPWM
strategy in the case of solar-powered water pumping systems. This would make the
entire model efficient and lossless.
6 Conclusion
The proposed method compares SPWM with SVPWM for three phase two level
inverters. Different control and PWM technologies are being used by an increasing
variety of inventive industrial applications that call for greater performance. The
most popular PWM methods for three phase voltage source inverters are SPWM
and SVPWM. High performance variable frequency drives can benefit from this
vector control approach’s outstanding efficiency and little torque ripple, as well as
better system performance. MATLAB/SIMULINK is used to conduct the system
analysis. The simulation findings show that the SVPWM-based system works better
than the SPWM system. We noted switching losses and general harmonic distortion
in both techniques. SVPWM has shown higher results since there is less THD and
switching loss because it uses sophisticated computational switching algorithms to
eliminate THD than SPWM.
References
1. Lin H, Chen R, Li R, Zhu L, Yan H, Shu Z (2019) A flexible and fast space vector pulse width
modulation technique for multilevel converters. In: 2019 22nd International Conference on
Electrical Machines and Systems (ICEMS), Harbin, China, pp 1–4. https://doi.org/10.1109/
ICEMS.2019.8921982
2. Singh S, Tiwari N (2018) Simulation and comparison of SPWM and SVPWM control for two
level inverter. Int J Comput Appl 13(2):267–273
3. Gujjar MN, Kumar P (2017) Comparative analysis of field-oriented control of BLDC motor
using SPWM and SVPWM techniques. In: 2nd IEEE international conference on Recent Trends
in Electronics, Information & Communication Technology (RTEICT), Bangalore, India, pp
924–929. https://doi.org/10.1109/RTEICT.2017.8256733
4. Waheed A, Usman ASM (2013) Comparative study of SVPWM (space vector pulse width
modulation) & SPWM (sinusoidal pulse width modulation) based three phase voltage source
inverters for variable speed drive. IOP Conf Ser: Mater Sci Eng 51:012027. https://doi.org/10.
1088/1757-899X/51/1/012027
5. Kumar KV, Michael PA, John JP, Kumar SS (2010) Simulation and comparison of SPWM and
SVPWM control for three phase inverters. ARPN J Eng Appl Sci 5(7):61–74
6. Asim M, Khan MS, Yadav RK, Mewara HS, Sethy N (2022) Multilevel inverters operating with
improved harmonic performance using SVPWM. In: Advanced energy and control systems:
select proceedings of 3rd international conference, ESDA 2022. Springer Singapore, pp 149–
156
7. Zeng Q, Chang L (2008) An advanced SVPWM-based predictive current controller for three-
phase inverters in distributed generation systems. IEEE Trans Ind Electron 55(3):1235–1246
8. Shaobang X, Ke-You Z (2007) Research on a novel SVPWM algorithm. In: 2007 2nd IEEE
conference on industrial electronics and applications, May 2007, pp1869–1872
9. Xue S, Wen X (2005) Simulation analysis of two novel multiphase SVPWM strategies. In 2005
IEEE international conference on industrial technology, December 2005, pp 1337–1342
10. Liang W, Wang J, Luk PCK, Fang W, Fei W (2014) Analytical modeling of current harmonic
components in PMSM drive with voltage-source inverter by SVPWM technique. IEEE Trans
Energy Convers 29(3):673–680
11. Le PNH, Van Nguyen N (2022) Common-mode voltage reduction in two-level voltage source
inverter with carrier-based PWM strategies. In: 2022 IEEE ninth International Conference on
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Lecture Notes in Electrical Engineering 1139

Recent Advances in Power

Vijay Kumar Sood

ISSN 1876-1100 ISSN 1876-1119 (electronic)

Paper in this product is recyclable.

Toledo, USA Krishna Murari

Hardware-In-Loop Test for Electronic Control Unit . . . . . . . . . . . . . . . . . . 1

A Generalized Symmetrical and Asymmetrical Multilevel Inverter

Design and Hardware Implementation of Fuzzy Logic Controller

Krishna Murari received a B.Tech. degree in electrical engineering from WBUT,

168 M.E./M.Tech./M.S.(R) theses. He has filed 58 patents. He has executed more

Bhupendra Teriya and Sushma Gupta

Keywords Electronic control unit · Hardware in the loop system · Electric

B. Teriya (B) · S. Gupta

Following are the objectives of the work:

The hardware-in-loop arrangement consists of electrical sensors, actuators, electrical

Fig. 1 Hardware-in-loop set-up block diagram

3 Driver Warning Data Storage

• Resets that are generally not happening, like watchdog.

3.1 Test Case Simulation in CANOe Under HiL Environment

Fig. 2 Node panel of ECU for simulation in CANOe

Fig. 3 Positive response received from ECU

Fig. 4 Warning lamp and control switch position

3.2 Simulation to Check the History of the Fault

Fig. 5 Setting of parameters to start the simulation

Fig. 6 Opening of main switch after fault

The outcome of real-time simulation is compiled in a CANOe report that includes

Fig. 7 CANOe report for driver warning with reason id

1. Lu B, Wu X, Figueroa H, Monti A (2007) A low-cost real-time hardware-in-the-loop testing

Ramesh Babu Pallapati, Ramulu Chinthamalla, Sindhu Vutturi,

Keywords LED driver · Power factor · DC-DC converter · Reduced power

R. B. Pallapati (B) · R. Chinthamalla · S. Vutturi · D. V. K. Abhinay · C. K. Kumba

Fig. 1 a Cascaded driver

therefore decreasing the power to be processed and increasing efficiency. Another

Fig. 3 Proposed topology of flyback and buck-boost converters

2.1 Operating Modes and Waveforms

Based on the operating principle and possible converter configurations, a topology

where . D1 is the duty cycle of . S1 and . f sw is the switching frequency when . S1 is

discharging energy to the load.

Fig. 4 Operating modes of

2.2 Analysis of Power Processing

Fig. 5 Wave forms of driver

Fig. 6 Power flow diagram

. pdc (t) > pd (t) (5)

The PFC fly-back converter’s voltage gain is .V f b.

The PC buck boost converter’s voltage gain is .Vb /b.

The driver circuit’s voltage gain is .Vd .

As a function of voltage gain, “p” is expressed as

.η = pη f b ηb/b + (1 − p)η f b (10)

substituting (9) in (10),

. pc (t) = Po − pd (t) (13)

where . Po is the LED load power.

3.1 Control Scheme

Table 1 30 W prototype design parameters

Fig. 8 Input AC voltage .vin (t) waveform, AC current .i in (t) waveform

Fig. 12 PC inductor current .i L pc (t)

Fig. 15 Output DC voltage .vdc (t), and output DC current .i o (t)

Dipty Chandrakar , Bhagwan K. Murthy ,

Keywords Model predictive current control · Asghar inverter · Dq-frame current

D. Chandrakar (B) · B. K. Murthy · A. Bhanuchandar