NCP3420

MOSFET Driver with Dual

Outputs for Synchronous
Buck Converters
The NCP3420 is a single Phase 12 V MOSFET gate driver
optimized to drive the gates of both high−side and low−side power http://onsemi.com
MOSFETs in a synchronous buck converter. The high−side and
low−side driver is capable of driving a 3000 pF load with a 30 ns MARKING
propagation delay and a 20 ns transition time. DIAGRAMS
8
With a wide operating voltage range, high or low side MOSFET
SO−8 3420
gate drive voltage can be optimized for the best efficiency. Internal
8 D SUFFIX ALYW
adaptive nonoverlap circuitry further reduces switching losses by CASE 751 G
1
preventing simultaneous conduction of both MOSFETs. 1
The floating top driver design can accommodate VBST voltages as
high as 35 V, with transient voltages as high as 40 V. Both gate outputs DFN8 1 8
3420
can be driven low by applying a low logic level to the Output Disable MN SUFFIX
ALYWG
(OD) pin. An Undervoltage Lockout function ensures that both driver 1 CASE 506BJ
G
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection. A = Assembly Location
L = Wafer Lot
Features Y = Year
W = Work Week
• Thermal Shutdown for System Protection G = Pb−Free Package
• Internal Pulldown Resistor Suppresses Transient Turn On of Either
MOSFET PIN CONNECTIONS
• Anti Cross−Conduction Protection Circuitry 1 8
BST DRVH
• One Input Signal Controls Both the Upper and Lower Gate Outputs
IN SWN
• Output Disable Control Turns Off Both MOSFETs OD PGND
• Complies with VRM10.x and VRM11.x Specifications VCC DRVL
• Undervoltage Lockout 1 8
• Thermally Enhanced Package Available
BST DRVH
• These are Pb−Free Devices
IN SWN
OD PGND
VCC DRVL

(Top View)

ORDERING INFORMATION
Device Package Shipping†

NCP3420DR2G SO−8 2500 Tape & Reel

(Pb−Free)

NCP3420MNR2G DFN8 3000 Tape & Reel

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

© Semiconductor Components Industries, LLC, 2009 1 Publication Order Number:

December, 2009 − Rev. 3 NCP3420/D
 NCP3420

OD 3

VCC TSD 1 BST

UVLO
IN 2 8 DRVH

FALLING
EDGE MONITOR
DELAY
7 SWN

FALLING
EDGE MONITOR
DELAY

START STOP NON−OVERLAP

MIN DRVL 4 VCC
TIMERS
OFF TIMER
5 DRVL

6 PGND

Figure 1. Block Diagram

PIN DESCRIPTION
SO−8 DFN8 Symbol Description

1 1 BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds
this bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value
is between 100 nF and 1.0 mF. An external diode is required with the NCP3420.

2 2 IN Logic−Level Input. This pin has primary control of the drive outputs.

3 3 OD Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.

4 4 VCC Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.

5 5 DRVL Output drive for the lower MOSFET.

6 6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.

7 7 SWN Switch Node. Connect to the source of the upper MOSFET.

8 8 DRVH Output drive for the upper MOSFET.

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 NCP3420

MAXIMUM RATINGS
Rating Value Unit

Operating Ambient Temperature, TA 0 to 85 °C

Operating Junction Temperature, TJ (Note 1) 0 to 150 °C

Package Thermal Resistance: SO−8

Junction−to−Case, RqJC 45 °C/W
Junction−to−Ambient, RqJA (2−Layer Board) 123 °C/W
Package Thermal Resistance: DFN8 (Note 2)
Junction−to−Case, RqJC (From die to exposed pad) 7.5 °C/W
Junction−to−Ambient, RqJA 55 °C/W

Storage Temperature Range, TS −65 to 150 °C

Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free (Note 3) 260 peak °C

JEDEC Moisture Sensitivity Level SO−8 (260 peak profile) 1 −

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Internally limited by thermal shutdown, 150°C min.
2. 2 layer board, 1 in2 Cu, 1 oz thickness.
3. 60−180 seconds minimum above 237°C.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.

MAXIMUM RATINGS
Pin Symbol Pin Name VMAX VMIN

VCC Main Supply Voltage Input 15 V −0.3 V

PGND Ground 0V 0V

BST Bootstrap Supply Voltage Input 35 V wrt/PGND −0.3 V wrt/SW

40 V v 50 ns wrt/PGND
15 V wrt/SW

SW Switching Node 35 V DC −5.0 V DC

(Bootstrap Supply Return) 40 V < 50 ns −10 V < 200 ns

DRVH High−Side Driver Output BST + 0.3 V −0.3 V wrt/SW

35 V v 50 ns wrt/PGND −2.0 V < 200 ns wrt/SW
15 V wrt/SW

DRVL Low−Side Driver Output VCC + 0.3 V −0.3 V DC

−5.0 V < 200 ns

IN DRVH and DRVL Control Input 6.5 V −0.3 V

OD Output Disable 6.5 V −0.3 V

NOTE: All voltages are with respect to PGND except where noted.

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 NCP3420

ELECTRICAL CHARACTERISTICS (Note 4) (VCC = 12 V, TA = 0°C to +85°C, TJ = 0°C to +125°C unless otherwise noted.)
Characteristic Symbol Condition Min Typ Max Unit
Supply
Supply Voltage Range VCC − 4.6 − 13.2 V
Supply Current ISYS BST = 12 V, IN = 0 V − 0.7 6.0 mA
OD Input
Input Voltage High VOD_HI − 2.0 − − V
Input Voltage Low VOD_LO − − − 0.8 V
Hysteresis − − − 400 − mV
Input Current − No internal pull−up or pull−down resistors −1.0 − +1.0 mA
Propagation Delay Time tpdlOD − 1.0 25 45 ns
tpdhOD 1.0 25 45 ns
PWM Input
Input Voltage High VPWM_HI − 2.0 − − V
Input Voltage Low VPWM_LO − − − 0.8 V
Hysteresis − − − 500 − mV
Input Current − No internal pull−up or pull−down resistors −1.0 − +1.0 mA
High−Side Driver
Output Resistance, Sourcing Current − VBST − VSW = 12 V (Note 6) − 1.8 3.0 W
Output Resistance, Sinking Current − VBST − VSW = 12 V (Note 6) − 1.0 2.5 W
SW Pulldown Resitance − SW to PGND 10 − 55 kW
Output Resistance, Unbiased − BST−SW = 0 V 10 − 55 kW
Transition Times trDRVH VBST − VSW = 12 V, CLOAD = 3.0 nF − 16 30 ns
tfDRVH (See Figure 3) − 11 25 ns
Propagation Delay (Note 5) tpdhDRVH VBST − VSW = 12 V, CLOAD = 3.0 nF 20 30 45 ns
tpdlDRVH (See Figure 3) 10 30 45 ns
Low−Side Driver
Output Resistance, Sourcing Current − VCC = 12 V (Note 6) − 1.8 3.0 W
Output Resistance, Sinking Current − VCC − PGND = 12 V (Note 6) − 1.0 2.5 W
Output Resistance, Unbiased − VCC = PGND 10 − 55 kW
Timeout Delay − DRVH−SW = 0 − 85 − ns
Transition Times trDRVL VBST − VSW = 12 V, CLOAD = 3.0 nF − 16 30 ns
tfDRVL (See Figure 3) − 11 25 ns
Propagation Delay (Note 5) tpdhDRVL VBST − VSW = 12 V, CLOAD = 3.0 nF 15 30 45 ns
tpdlDRVL (Note 6, tpdhDRVL Only) (See Figure 3) 10 30 45 ns
Undervoltage Lockout
UVLO Startup − − 3.9 4.3 4.5 V
UVLO Shutdown − − 3.7 4.1 4.3 V
Hysteresis − − 0.1 0.2 0.4 V
Thermal Shutdown
Over Temperature Protection − (Note 6) 150 170 − °C
Hysteresis (Note 6) − 20 − °C
4. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
5. For propagation delays, “tpdh’’ refers to the specified signal going high; “tpdl’’ refers to it going low.
6. GBD: Guaranteed by design; not tested in production.
Specifications subject to change without notice.

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 NCP3420

OD
VOD_HI

VOD_LO

tpdlOD tpdhOD

90%
DRVH
or
DRVL 10%

Figure 2. Output Disable Timing Diagram

VPWM_HI

VPWM_LO
IN
tpdlDRVL tfDRVL

90% 90%
DRVL 2V
10% 10%

trDRVL
tpdhDRVH trDRVH tpdlDRVH tfDRVH

90% 90%
DRVH−SW
10% 2V 10%

tpdhDRVL

SW

Figure 3. Nonoverlap Timing Diagram

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 NCP3420

APPLICATIONS INFORMATION

Theory of Operation Likewise, when the PWM input pin goes low, DRVH will
The NCP3420 are single phase MOSFET drivers designed go low after the propagation delay (tpdDRVH). The time to
for driving two N−channel MOSFETs in a synchronous buck turn off the high−side MOSFET (tfDRVH) is dependent on
converter topology. The NCP3420 will operate from 5 V or the total gate charge of the high−side MOSFET. A timer will
12 V, but have been optimized for high current multi−phase be triggered once the high−side mosfet has stopped
buck regulators that convert 12 V rail directly to the core conducting, to delay (tpdhDRVL) the turn on of the
voltage required by complex logic chips. A single PWM input low−side MOSFET
signal is all that is required to properly drive the high−side and
the low−side MOSFETs. Each driver is capable of driving a Power Supply Decoupling
3.3 nF load at frequencies up to 1 MHz. The NCP3420 can source and sink relatively large
currents to the gate pins of the external MOSFETs. In order
Low−Side Driver to maintain a constant and stable supply voltage (VCC) a low
The low−side driver is designed to drive a ESR capacitor should be placed near the power and ground
ground−referenced low RDS(on) N−Channel MOSFET. The pins. A 1 mF to 4.7 mF multi layer ceramic capacitor (MLCC)
voltage rail for the low−side driver is internally connected to is usually sufficient.
the VCC supply and PGND.
Input Pins
High−Side Driver The PWM input and the Output Disable pins of the
The high−side driver is designed to drive a floating low NCP3420 have internal protection for Electro Static
RDS(on) N−channel MOSFET. The gate voltage for the high Discharge (ESD), but in normal operation they present a
side driver is developed by a bootstrap circuit referenced to relatively high input impedance. If the PWM controller does
Switch Node (SW) pin. not have internal pull−down resistors, they should be added
The bootstrap circuit is comprised of an external diode, externally to ensure that the driver outputs do not go high
and an external bootstrap capacitor. When the NCP3420 are before the controller has reached its under voltage lockout
starting up, the SW pin is at ground, so the bootstrap threshold. The NCP5381 controller does include a passive
capacitor will charge up to VCC through the bootstrap diode internal pull−down resistor on the drive−on output pin.
See Figure 4. When the PWM input goes high, the high−side
driver will begin to turn on the high−side MOSFET using the Bootstrap Circuit
stored charge of the bootstrap capacitor. As the high−side The bootstrap circuit uses a charge storage capacitor
MOSFET turns on, the SW pin will rise. When the high−side (CBST) and the internal (or an external) diode. Selection of
MOSFET is fully on, the switch node will be at 12 V, and the these components can be done after the high−side MOSFET
BST pin will be at 12 V plus the charge of the bootstrap has been chosen. The bootstrap capacitor must have a
capacitor (approaching 24 V). voltage rating that is able to withstand twice the maximum
The bootstrap capacitor is recharged when the switch supply voltage. A minimum 50 V rating is recommended.
node goes low during the next cycle. The capacitance is determined using the following equation:
Q
Safety Timer and Overlap Protection Circuit CBST + GATE
DVBST
It is very important that MOSFETs in a synchronous buck
regulator do not both conduct at the same time. Excessive where QGATE is the total gate charge of the high−side
shoot−through or cross conduction can damage the MOSFET, and DVBST is the voltage droop allowed on the
MOSFETs, and even a small amount of cross conduction high−side MOSFET drive. For example, a NTD60N03 has
will cause a decrease in the power conversion efficiency. a total gate charge of about 30 nC. For an allowed droop of
The NCP3420 prevent cross conduction by monitoring 300 mV, the required bootstrap capacitance is 100 nF. A
the status of the external mosfets and applying the good quality ceramic capacitor should be used.
appropriate amount of “dead−time” or the time between the The bootstrap diode must be rated to withstand the
turn off of one MOSFET and the turn on of the other maximum supply voltage plus any peak ringing voltages
MOSFET. that may be present on SW. The average forward current can
When the PWM input pin goes high, DRVL will go low be estimated by:
after a propagation delay (tpdlDRVL). The time it takes for IF(AVG) + QGATE fMAX
the low−side MOSFET to turn off (tfDRVL) is dependent on
where fMAX is the maximum switching frequency of the
the total charge on the low−side MOSFET gate. The
NCP3420 monitor the gate voltage of both MOSFETs and controller. The peak surge current rating should be checked
the switchnode voltage to determine the conduction status of in−circuit, since this is dependent on the source impedance
of the 12 V supply and the ESR of CBST.
the MOSFETs. Once the low−side MOSFET is turned off an
internal timer will delay (tpdhDRVH) the turn on of the
high−side MOSFET

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 NCP3420

12 V 12 V

NCP3420
4 1
BST
Vcc
DRVH 8
3 7
Output Enable OD SW Vout
DRVL 5
2 6
PWM in IN PGND

Figure 4. NCP3420 Example Circuit

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 NCP3420

PACKAGE DIMENSIONS

DFN8 3x3, 0.5P

CASE 506BJ−01
ISSUE O

A EDGE OF PACKAGE NOTES:

D 1. DIMENSIONS AND TOLERANCING PER ASME
B L Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30
L1 MM FROM TERMINAL.

ÇÇÇ
PIN 1 4. COPLANARITY APPLIES TO THE EXPOSED
REFERENCE PAD AS WELL AS THE TERMINALS.

ÇÇÇ
E DETAIL A
OPTIONAL MILLIMETERS

ÇÇÇ
CONSTRUCTION DIM MIN MAX
2X A 0.80 1.00
0.10 C L A1 0.00 0.05
A3 0.20 REF
2X b 0.18 0.30
D 3.00 BSC
0.10 C D2 1.64 1.84
TOP VIEW
E 3.00 BSC
DETAIL A E2 1.35 1.55
DETAIL B OPTIONAL e 0.50 BSC
0.05 C CONSTRUCTION K 0.20 −−−
L 0.30 0.50
A L1 0.00 0.03
8X
0.05 C
(A3) SEATING SOLDERMASK DEFINED
NOTE 4 SIDE VIEW C PLANE
A1 MOUNTING FOOTPRINT
D2 1.85

ÉÉ
DETAIL A EXPOSED Cu MOLD CMPD 8X
8X L 0.35
1 4

E2
ÉÉ
DETAIL B
8X K OPTIONAL
CONSTRUCTION 3.30 1.55

8 5
8X b
e 0.10 C A B
BOTTOM VIEW 0.05 C NOTE 3
0.50
8X 0.63 PITCH
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 NCP3420

PACKAGE DIMENSIONS

SOIC−8
D SUFFIX
CASE 751−07
ISSUE AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
C N X 45 _ A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
SEATING
PLANE C 1.35 1.75 0.053 0.069
−Z− D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
0.10 (0.004) H 0.10 0.25 0.004 0.010
H M J J 0.19 0.25 0.007 0.010
D K 0.40 1.27 0.016 0.050
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S
S 5.80 6.20 0.228 0.244

SOLDERING FOOTPRINT*

1.52
0.060

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050

SCALE 6:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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9