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Electrical

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GATE Previous Year Questions

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 Contents

ANALOG ELECTRONICS
GATE Solved Questions

Sr. No. Topic Pages

1. Diode Circuit ................................................................................................ 1 - 12

2. BJT and FET Biasing ................................................................................... 13 - 27

3. Small Signal Analysis ................................................................................. 28 - 31

4. Frequency Response ................................................................................. 32 - 33

5. Operational Amplifier .................................................................................. 34 - 69

6. Feedback Amplifiers & Oscillators ............................................................ 70 - 75

7. Function Generator & 555 Timer ................................................................ 76 - 78

ANALOG Soil Mechanics & Foundation
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1
DIODE CIRCUIT
1. The cut-in voltage of both zener diode Dz and D shown in Figure is 0.7 V, while breakdown voltage of
the zener is 3.3 V and reverse break down of D is 5 V. The other parameters can be assumed to be
the same as those of an ideal diode. The values of the peak output voltage (V0) are
1k
I

1k
~ 10sint V0
=314 rad/sec

(a) 3.3 V in the positive half cycle and 1.4 V in the negative half cycle.
(b) 4 V in the positive half cycle and 5 V in the negative half cycle.
(c) 3.3 V in the both positive and negative half cycle.
(d) 4 V in the both positive and negative half cycle.
[1 Mark : GATE-2002]
2. The forward resistance of the diode shown in figure is 5 and the remaining parameters are same as
those of ideal diode. The DC component of the source current is
D

Vi ~ 45
Vi = Vm sin t
 = 314 rad/sec

Vm Vm Vm 2Vm
(a) (b) (c) (d)
50 50 2 100 2 50 2
[1 Mark : GATE-2002]
3. In the single phase diode bridge rectifier shown in figure, the load resistor is R = 50. The source
voltage is V = 200 sin t, where  = 2 × 50 rad/sec. The power dissipated in the load resistor R is

R
V ~ A
B

3200 400
(a) W (b) 400 W (c) W (d) 800 W
 
[2 Marks : GATE-2002]
 2 GATE Previous Solved Questions
4. A voltage signal 10 sin t is applied to the circuit with ideal diodes as shown in figure. The maximum
and minimum values of the output waveform of the circuit are respectively
10K
+
D1 D2
~ Vi 4V
4V
V0

10K
–
(a) +10V and –10V (b) +4V and –4V
(c) +7V and –4V (d) +4V and –7V
[2 Marks : GATE-2003]
5. The current through the zener diode in the given circuit is

2.2K
+
Iz
10V RL 3.5V
VZ = 3.3V
RZ = 100 –

(a) 33 mA (b) 3.3 mA (c) 2 mA (d) 0 mA

[1 Mark : GATE-2004]
6. Assuming that the diodes are ideal in figure the current in the diode D1 is

1K 1K

D2
5V D1
8V

(a) 8 mA (b) 5 mA (c) 0 mA (d) –3 mA

[2 Marks : GATE-2004]
7. Assume that D1 and D2 in figure are ideal diodes, the value of current I is

D1
2k
1mA
(DC) I
D2 2k

(a) 0 mA (b) 0.5 mA (c) 1 mA (d) 2 mA

[1 Mark : GATE-2005]
 ANALOG Soil Mechanics & Foundation
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8. What are the states of the three ideal diodes of the circuit shown in figure?
1
1

D2

1 5A
D1 D3
10V

(a) D1-ON, D2-OFF, D3-OFF (b) D1-OFF, D2-ON, D3-OFF

(c) D1-ON, D2-OFF, D3-ON (d) D1-OFF, D2-ON, D3-ON
[1 Mark : GATE-2006]
9. Assuming the diodes D1 and D2 of the circuit shown in the figure to be ideal ones, the transfer characteristics
of the circuit will be
D1 V0

2 D2
RL=
Vi

10V 5V

Vo Vo
10

10
(a) (b) 5

Vi Vi
10 5 10

Vo Vo

10

(c) (d)
5
Vi 10 Vi
5

[2 Marks : GATE-2006]
10. The equivalent circuits of a diode, during forward and reverse bias, is shown in figure.
0.7V
+ –  + –

– +  – +
10k

10sint ~ V0 10k
5V
 4 GATE Previous Solved Questions
If such diodes are used in the clipper circuit of figure given above, the output voltage (V0) of the circuit
will be

+5V +5.7V

(a)    t (b)    t
–5V –10V

10V +5.7V
(c)    t (d)    t
–5.7V –5V

[1 Mark : GATE-2008]
11. In the voltage doubler circuit shown in figure, the switch ‘S’ is closed at t = 0. Assuming diodes D1 &
D2 to be ideal, load resistance to be infinite and initial capacitor voltages to be zero, the steady state
voltage across capacitors C1 & C2 will be

t=0 Vc1 D2
+ –
S C1 +
5sint ~ D1 C2
–
Vc2 Rload

(a) VC1 = 10V, VC2 = 5V (b) VC1 = 10V, VC2 = –5V

(c) VC1 = 5V, VC2 = 10V (d) VC1 = 5V, VC2 = –10V
[2 Marks : GATE-2008]
12. The following circuit has a voltage source Vs as shown in the graph. The current through the circuit is
also shown

a b

VS +
– R 10k

15 1.5
10 1.0
Current (mA)
VS(volts)

5 0.5
0 0
-5 -0.5
-10 -1.0
-15 -1.5
0 100 200 300 400 0 100 200 300 400
Time (ms) Time (ms)
ANALOG Soil Mechanics & Foundation
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The element connected between ‘a’ and ‘b’ could be
(a) a b (b) a b

(c) a b (d)
a b
[1 Mark : GATE-2009]
13. Assuming that the diodes are ideal in the given circuit, the voltage V0 is
10k

D1 D2
10k
10V V0 15V
10k

(a) 4V (b) 5V (c) 7.5V (d) 12.12V

[1 Mark : GATE-2010]
14. A clipper circuit is shown below

1K

+
D
Vi ~ Vz =10V – Vo

5V

Assuming forward voltage drops of the diodes to be 0.7V, the input-output transfer characteristics of the
circuit is

V0 V0

10V
4.3V
(a) 4.3V (b)

Vi Vi
4.3V 4.3V

V0
V0
10V

5.7V -5.7V
(c) (d)
Vi
-0.7V 10V
Vi
0.7V 5.7V -5.7V

[2 Marks : GATE-2011]
 6 GATE Previous Solved Questions
15. The i-v characteristics of the diode in the circuit given below are

 v  0.7
 A, v  0.7V
i   500
0A, v  0.7V

The current in the circuit is

1k
i
+ +
10V V
– –

(a) 10 mA (b) 9.3 mA (c) 6.67 mA (d) 6.2 mA

[1 Mark : GATE-2012]
16. In the circuit shown below, the knee current of the ideal zener diode is 10 mA. To maintain 5 V across
RL, the minimum value of RL in  and the minimum power rating of the Zener diode in mW respectively
are

100

IL
10V

Vz = 5V RL

(a) 125 and 125 (b) 125 and 250 (c) 250 and 125 (d) 250 and 250
[2 Marks: GATE-2013]
17. A voltage 1000 sin t Volts is applied across YZ. Assuming ideal diodes, the voltage measured across
WX in Volts is

1k
W X
Y
Z

1k

(a) sin t (b) (sin t + |sin t|) / 2

(c) (sin t – |sin t|) / 2 (d) 0 for all t
[2 Marks : GATE-2013]
ANALOG Soil Mechanics & Foundation
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20
18. The sinusoidal ac source in the figure has an rms value of V. Considering all possible values of R ,
L
2
the minimum value of RS in  to avoid burnout of the Zener diode is

RS

20 V 5V RL
1/4W
2

[1 Mark : GATE-2014]
19. Assuming the diodes to be ideal in the figure, for the output to be clipped, the input voltage vi must be
outside the range

10k

vi 10k v
o

1V 2V

(a) –1 V to –2 V (b) –2 V to –4 V
(c) +1 V to –2 V (d) +2 V to –4 V
[2 Marks : GATE-2014]
20. A non-ideal diode is biased with a voltage of -00.03 V, and a diode current of I1 is measured. The thermal
voltage is 26m V and the ideality factor for the diode is 15/13. The voltage, in V, at which the measured
current increases to 1.5I1 is closest to
(A) -4.50 (B) -0.09
(C) -0.02 (D) -1.50
[2020 : 2 Marks]
21. Consider the diode circuit shown below. The diode, D, obeys the current-voltage characteristic

  V  
ID  IS  exp  D   1 , +
  nVT  
where n > 1, VT > 0, VD is the voltage across the diode and ID is the current through it. The circuit is
biasedso that voltage, V > 0 and current, l < 0. If you had to design this circuit to transfer maximum
power fromthe current source (I1) to a resistive load (not shown) at the output, what values R1 and R2
would you choose?
 8 GATE Previous Solved Questions

(A) Small R1 and small R2 (B) Large R1 and large R2

(C) Small R1 and large R2 (D) Large R1 and small R2
[2020 : 2 Marks]
22. In the circuit shown, a 5 V Zener diode is used to regulate the voltage across load R0. The input is an
unregulated DC voltage with a minimum value of 6 V and a maximum value of 8 V. The value of Rs
is 6W. The Zener diode has a maximum rated power dissipation of 2.5 W, Assuming the Zener diode
to beideal, the minimum value of R0 is__________W

[2021 : 1 Marks]
23. For the circuit shown below with ideal diodes, the output will be

(A) Vout = Vin for Vin > 0 (B) Vout = Vin for Vin < 0
(C) Vout = -Vin for Vin > 0 (D) Vout = -Vin for Vin < 0
[2022 : 1 Marks]
24. All the elements in the circuit shown in the following figure are ideal. Which of the following statements
is/are true?
ANALOG Soil Mechanics & Foundation
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(A) When switch S is ON, both D1 and D2 conducts and D3 is reverse biased.
(B) When switch S is ON, D1 conducts and both D2 and D3 are reverse biased.
(C) When switch S is OFF, D1 is reverse biased and both D2 and D3 conduct.
(D) When switch S is OFF, D1 conducts, D2 is reverse biased and D3 conducts
[2023 : 2 Marks]


 10 GATE Previous Solved Questions

SOLUTIONS
SOLUTIONS
1. Ans. (b) DC component is
During the positive half cycle, when Vi > 4 V
 Vm 
zener diode is replaced by V2 (ON) & D is   V 
replaced by 0.7 V IdC =  50    m 
    50 
1k
+ During negative half cycle,
3.3V Diode is reverse biased & is replaced by open
Vi ~ 0.7
1k Vo=4V circuit.

–
 I= 0

During the negative half cycle, 3. Ans. (b)

Zener diode becomes forward biased and PN The given circuit can be redrawn as
junction diode becomes reverse biased, then
1k
D1 D4
+
R
Vi ~ Vo ~ C D
1k
– D2 D3

Vi B
Vo =
2
= 5sin t R
Vomax = –5V V(t) ~ i(t)
2. Ans. (a)
During positive half cycle,
During the positive half cycle of the input then
Diode is forward biased & is replaced by 5
D1 & D3 – ON,  short circuit
5
D2 & D4 – Off  open circuit
V  t  200sin t
Vi ~ 45 i(t) = 
R 50
= 4 sin t Amp.
Vi During the negative half cycle of the input,
D1 & D3 – Off  open circuit
D2 & D4 – ON  short circuit

I
V(t) ~ R

Vi V t
i(t) = i(t) =  4sin t
50 R
Vm In full wave rectifier, power dissipated in the
i(t) = sin t
50 load resistor R is
ANALOG Soil Mechanics & Foundation
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V(t) 5. Ans. (c)
Given that Vo= 3.5V
t
0
VZ = 3.3V

i(t) Then zener diode offers Rz = 0.1 k of dynamic

resistance.
t
0 So, Vz + IzRz = 3.5
 3.5  3.3 
V t  i t  200 4 Iz =  R   2mA
P=  =   z 
2 2 2 2
6. Ans. (c)
P = 400W
In the circuit, D2 must be forward bias where
4. Ans. (d) D1 is first replaced by open circuit
For positive half cycle Apply Nodal analysis at node 1
(i) When Vi>4V, D2  ON, D1  OFF then
V1  5 V1  8
Vo = 4V  0
3
10 10
(ii) When Vi<4V, D1 & D2  OFF
1K V1 1K
 Vo = Vi
10k 1
+ 5V 8V

~ Vi 4V 4V Vo=4V
10k
– V1  5  V1  8 = 0
For negative half cycle, D1  ON, & D2OFF
2V1 = –3
10 k
V1 = –1.5V
+
 D1 is Reverse biased
I
Vi ~ 4V Vo
ID1 = 0
10 k
– 7. Ans. (a)
Vi – 10I + 4 – 10I = 0 The current always search the low resistance
path. D1-ON and D2-OFF.
 Vi  4  The I directed from N type to P–type of D2
I=   mA
 20  (D2–R.B) As D2 is reverse biased & is replaced
When Vi = –10V (maximum negative value) by open circuit.
 I =0
6
I= mA
20
Vo + 4 – 10I = 0
Vo = 10I – 4

 6 
= 10    4
 20 
= 3  4  Vo  7V
 12 GATE Previous Solved Questions
in parallel and voltage across them must be same.
D1 2k So that the value of output voltage from potential
1mA divider network is
(DC) I
D2 2k
 10  Vi
Vo = Vi    Vo  5sin t
 10  10  2
8. Ans. (a)
Therefore, voltage across diode is always less
In the given circuit, we can analyse that the
than 0 V, VD < 0 i.e., diode is reverse biased for
diodes
the given input.  V0 = 5 sint
1K
11. Ans. (d)
1K At t = 0, switch is closed and During the positive
D2 half cycle of input,
10V 1K 5A
D1 D1 is forward biased & D2 is reverse biased
‘C’, will charge upto +5V
D1 – ON VC1 = 5V

D2 – ON & + –
D3 – OFF then +
But no current flows through D2 because current –
~ Vi

always search the low resistance path (through

short circuit path D1) Therefore D2 also OFF During the negative half cycle of input voltage
9. Ans. (a) D1 – Off

When Vi =0, Dl-OFF and D2 also OFF D2 – ON

VC1
+ –
+ +
2 D2 +
Vi RL= Vo
Vi ~ –
C2
10V 5V
– –
Vo = 10V Apply KCL
Vi + VC2 + VC1 = 0
When Vi > 10V, D1–ON and D2–OFF VC2 =  Vi  VC1
+ + = –5 – 5
2 = –10V
Vi V0
10V  C2 will charge upto –10V
– –
12. Ans. (a)
Vo
During the positive half cycle, diode gets forward
10V biased then Vo = Vi.
During negative half cycle, diode gets reverse
Vi biased then Vo = 0
0 10V
13. Ans. (b)

10. Ans. (a)

Diode branch and 10k resistor are connected
ANALOG Soil Mechanics & Foundation
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1k
10K i
I V0 +
+
10V 10V v
10K – –

D1 is forward biased (ON),

D2 is reverse biased (Off). From (1) and (2)
10
I =  0.5mA 10  1000i  0.7 9.3
20  103 i= =  2i
500 500
V0 = 10  103 I
V0 = 5V 9.3
 3i =
500
14. Ans. (c)
During positive half cycle of the input. 3.1
i= A  6.2mA
500
When Vi < 5.7V, diode will be off and Zener
diode will not operate in breakdown region 16. Ans. (b)
Therefore, Vo = Vi
When Vi > 5.7V, diode will be ON, as it is on, Is
Vo = 5.7V
Rs =100
Zener diode will never operate in break down
region (i.e., it will always be in off state)
During negative half cycle of input, IL
Vs =10V Iz
Diode is reverse baised and Zener diode gets
+
forward biased when Vi  – 0.7V Vz = 5V RL
–
Vo

5.7V

–0.7V
Vi Given, knee current of zener diode,
0.7V 5.7V
Iz knee = 10 mA
Then, Vo = –0.7V Current supplied by source,
When Vi > –0.7V, diode will be off and zener
diode get reverse biased. Vs  Vz 10  5
Is =   50mA
Rs 100
Then, V0 = Vi
15. Ans. (d) Maximum load current
i – v characteristic of the diode : IL max = Is – Iz knee

 IL max = 50 – 10 = 40 mA
v  0.7
i= A, v  0.7V ...(1) Minimum load resistance,
500
From the given circuit, Loop equation : Vz 5
RL = I   125
min
L max 40  103
v = 10 – 1000 i, v  0.7V ...(2)
Maximum current in zener diode = Iz max
 14 GATE Previous Solved Questions
Maximum power dissipation of Zener diode 19. Ans. (b)
determines the minimum power rating of zener Case-I: Vi  – 4V
diode. Maximum current in Zener diode gives
maximum power dissipation in diode which occurs D2  ON
when load current is zero. Maximum current in D1  OFF
diode flows when load is open circuited.
So, Vo = –2V
Maximum current in Zener diode,
Case-II: –4 V  Vi  –2 V
Iz max = Is = 50 mA
Both the diodes will be OFF.
Maximum power dissipation in zener diode,
PD = Vz Iz Vo = V1'
max max

= 5 × 50 × 10–3 W Case–III: Vi  –2V

 PD max = 250 mW D1  ON
Minimum power rating of diode, D2  OFF
Pz = PD max = 250 mW Vo = –1 V
17. Ans. (d) 20. Ans. (B)
For positive half cycle
0.03
1k  
I1  I0 e15/1326 mV  1
W Y X  
Z As, VD = -ve‘1’ cannot be neglected in diode
current equation
1k

VWX = 0 I1  I0  e 30 mV/30 mV  1

For negative half cycle

1k  I0 [e 1  1]  0.64 I0 ...........(i)

W Y X
Z 1.5I1  I0 e VD /30 mV  1

1k - 1.5 ´ 0.64I0 = I0  e VD /30 mV  1

 
Short circuit condition
0.96  e VD 2 /30 mV  1
VWX = 0
1  0.96  eVD /30 mV  0.04  eVD /30 mC
18. Ans. 299 to 301
30 mV in(0.04)  VD  VD  0.96 V
IS  IZ + IL
21. Ans. (C)
1 20 – 5
 (Putting IL = 0 ) R2
20 Rs R1 , low, R 2 high : VD  V 
R1  R 2
 RS   300 
If R2 is large Vd (high). R1 is less VD = V
Hence, R Smin = 300 So for maximum power to deliver to load R1 is
small and R2 is large.
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22. Ans. (30)
To calculate R0 min, we must find IL max
Is min = Iz min + IL max

Vi min  Vz
 I z min  I L max
Rs
For ideal zener diode, Iz min = 0

Vi min  Vz 65
 I L max   I L max
Rs 6

1
IL max  A
6

Vz 5
R 0min    30 
I L max 1/ 6

23. Ans. (A)

Positive half cycle

D1 and D2 will be ON.

For Negative half cycle

D1 and D2 will be OFF.
 16 GATE Previous Solved Questions

The output waveform

So, V0 = Vin for Vin > 0

24. Ans. (B, C)

When switch on,

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D3 off by observation

Assume D1 and D2 off

KCL is being violated. Assume D1 on, D2 off

18 GATE Previous Solved Questions
\ D2 is reverse biased, \ our assumption is correct, i.e., D1 = ON and D2 = OFF and D3 = OFF.
When switch is off,

\ D1 is reverse biased, \ D1 is OFF

Switch off : D1 off, D2 and D3 on.

