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    Khadija Kennou 229J85 Ex1-4

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    Khadija Kennou 229J85 Ex1-4

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    Khadija Kennou 229J85 Ex1-4

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    khadijakennou04

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    Khadija Kennou 229J85

    Experiment 1
    1. Logic function test of "NAND gate"

    2. "And-OR-NOT gate" logic function test


    3. XOR gate logical function test

    4. Use and not gate to form other logic gate circuits


    (1) AND gate circuit
    (2) OR gate circuit

    (3) XOR gate circuit

    2. Unused Input Terminals of NAND Gates


    Connect to VCC (Logic High): For unused inputs of NAND gates,
    connect them to VCC (logic high) to ensure they do not float and
    cause unpredictable behavior.
    3. Unused Input Terminals of NOR Gates
    Connect to GND (Logic Low): For unused inputs of NOR gates,
    connect them to GND (logic low) to prevent floating inputs and
    ensure stable operation.
    4. Main Disadvantages of TTL Logic Gates
    Power Consumption: TTL logic gates consume more power
    compared to CMOS gates, especially in large circuits.
    Noise Margin: Lower noise margin compared to CMOS, making
    them less suitable for high-noise environments.
    Speed: Generally slower than some advanced CMOS
    technologies, limiting their use in high-speed applications.
    Heat Dissipation: Higher power consumption leads to more heat
    generation, requiring effective heat management.
    Experiment 4 (confirmatory): Half adder and full adder
    1. Half adder composed of NAND gate

    2, Half adder composed of XOR gate


    3. Full adder composed of XOR gate and NAND gate

    4. Function test of full adder


    2. Use XOR Gate to Form a Half Subtracter
    Logical Relation:

    Difference (D):
    D=A⊕B (XOR gate)
    Borrow (B):
    B= A⋅B (AND gate and NOT gate)
    Logic Circuit: Draw the logic circuit for the half subtracter
    using XOR and AND gates.
    3. Design a Full Subtracter (Optional Device)
    Logical Relations:

    Difference (D):
    D=A⊕B⊕B in(using XOR gates)
    Borrow Out (B_{out}):
    𝐵𝑜𝑢𝑡=(𝐴‾⋅𝐵)+(𝐴⊕𝐵‾⋅𝐵𝑖𝑛)(using AND, OR, and NOT gates)

    A B B_in D B_out
    0 0 0 0 0
    0 0 1 1 1
    0 1 0 1 1
    0 1 1 0 1
    1 0 0 1 0
    1 0 1 0 0
    1 1 0 0 0
    1 1 1 1 1
    Experiment 3 (design): Design of combinatorial logic circuit
    1. Write the design process according to the design content (list,
    write, draw the logic diagram).
    1.1 Determine Input and Output Variables
    Inputs: A, B, C_in (Carry-in)
    Outputs: S (Sum), C_out (Carry-out)
    1.2 Establish the Truth Table
    A B C_in S (Sum) C_out (Carry Out)
    0 0 0 0 0
    0 0 1 1 0
    0 1 0 1 0
    0 1 1 0 1
    1 0 0 1 0
    1 0 1 0 1
    1 1 0 0 1
    1 1 1 1 1
    1.3 and 1.4
    2.

    3..the results are the same as the truth table


    4.. Understanding Logic Gates:
    Reinforce the principles of how NAND gates can be used to build any
    logic circuit.
    Complexity Management:
    Realize the importance of simplifying expressions for practical circuit
    design.
    Simulation and Validation:
    Learn the importance of testing each step in a simulator before
    building the physical circuit.

    Experiment 2 (design): Design of combinatorial logic circuit

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