DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

SCHOOL OF TECHNOLOGY
PANDIT DEENDAYAL ENERGY UNIVERSITY
SESSION 2024-25

SUBMITTED BY
NAME : Kouadio Akotto Daniel
ROLL NO. : 23BCP471
DIVISION : 7
COURSE NAME : Digital Electronics and
Computer Organization
COURSE CODE : 20CP203P

Department of Computer Science and Engineering

Pandit Deendayal Energy University

 INDEX
S. No. Aim of the Experiment Date

1 Simulation of logic gates

2 Simulation of half adder
3 Simulation of full adder
4 To simulate half-subtractor and full-subtractor using normal
gates and NAND gate
5 To simulate 2:1 MUX, 4:1 MUX and 8:1 MUX using normal
gates and NAND gate

6 To simulate 4-bit Parallel Adder and Parallel Subtractor

7 To design a 1:4 DEMUX and 1:8 DEMUX using NAND

Gate

8 To implement and verify Decoder

9 To design an ALU circuit

10 ( OPEN ENDED EXPERIMENT)

To design a 4-Bit BCD adder

EXPERIMENT 1: LOGICAL GATES
AIM: Using logic Gates
SOFTWARE USED: Logisim

AND Gate :

• Definition: The AND gate outputs a high signal (1) only if all of its inputs are high
(1).
• Output Operation: For inputs A and B, the output X= A*B

• Truth table
OR Gate

• Definition: The OR gate outputs a high signal (1) if at least one of its inputs is high
(1).
• Output Operation: For inputs A and B, the output X= A+B

• Truth table

NOT Gate

• Definition: The NOT gate, also known as an inverter, outputs the opposite of its input.
• Output Operation: For input AAA, the output X= ¬A

• Truth table
NAND Gate

• Definition: The NAND gate outputs a low signal (0) only if all of its inputs are high
(1); it’s the inverse of the AND gate.
• Output Operation: For inputs A and B, the output X= ¬(A*B)

• Truth table

NOR Gate

• Definition: The NOR gate outputs a high signal (1) only if all of its inputs are low (0);
it’s the inverse of the OR gate.
• Output Operation: For inputs AAA and BBB, the output X=¬(A+B)

• Truth table

XOR Gate (Exclusive OR)

• Definition: The XOR gate outputs a high signal (1) only if exactly one of its inputs is
high (1). It’s often used for binary addition.
• Output Operation: For inputs AAA and BBB, the output X=A⊕B

• Truth table
XNOR Gate (Exclusive NOR)

• Definition: The XNOR gate outputs a high signal (1) if both inputs are the same,
either both 0 or both 1. It is the inverse of the XOR gate.
• Output Operation: For inputs AAA and BBB, the output X=¬(A⊕B)

• Truth table
EXPERIMENT 2: HALF ADDER
AIM: To design half adder using gates and verify their truth tables.
SOFTWARE USED: Logisim
THEORY What
is an Adder?
An adder is a digital logic circuit in electronics that is extensively used for the addition of
numbers. In many computers and other types of processors, adders are even used to calculate
addresses and related activities and calculate table indices in the ALU and even utilized in other
parts of the processors. These can be built for many numerical representations like excess-3 or
binary coded decimal. Adders are basically classified into two types: Half Adder and Full
Adder.

HALF ADDER
A half adder is a type of adder, an electronic circuit that performs the addition of numbers.
The half adder is able to add two single binary digits and provide the output plus a carry
value. It has two inputs, called A and B, and two outputs S (sum) and C (carry). The common
representation uses a XOR logic gate and an AND logic gate.

1. EQUATIONS

SUM (X) = A XOR B = A B

CARRY (Y) = A AND B = A.B

CIRCUIT DIAGRAMS: HALF-ADDER

• Making Half-Adder using AND-OR gates

• Making a Half-Adder using XOR gate

TRUTH TABLE
EXPERIMENT 3: FULL ADDER

AIM: To design Full Adder using gates and verify their truth tables.

SOFTWARE USED: Logisim

THEORY

1. FULL ADDER:
Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs
are A and B, and the third input is an input carry as C-IN. The output carry is designated as C-
OUT and the normal output is designated as S which is SUM.
A full adder logic is designed in such a manner that can take eight inputs together to create a
byte-wide adder and cascade the carry bit from one adder to the another.

1. EQUATIONS:

Logical Expression for SUM

= A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN

= C-IN (A’ B’ + A B) + C-IN’ (A’ B + A B’)
= C-IN XOR (A XOR B)
= (1,2,4,7)

Logical Expression for C-OUT

= A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN
= A B + B C-IN + A C-IN
= (3,5,6,7)

CIRCUIT DIAGRAM: HALF-ADDER

• Making Full Adder using NAND gate

• Making Full Adder using XOR gate

 1. TRUTH TABLE:

EXPERIMENT 4

Aim: To simulate half-subtractor and full-subtractor using normal gates and

NAND gate
Software : logisim
Theory:
In electronics, a subtractor is a digital circuit that performs subtraction of
numbers and can be designed using the same approach as that of an adder.
There are two types of subtractors: (1) Half Subtractor
(2) Full Subtractor
(1) Half Subtractor: The half-subtractor is a combinational circuit which is
used to perform subtraction of two bits. It has two inputs, A (minuend) and B
(subtrahend) and two outputs Difference and Borrow.

Block Diagram:

Truth Table:

SOP Expressions:
Difference (D) = A’B+AB’
Borrow (B) = A’B

(2) Full Subtractor: A full subtractor is a combinational circuit that performs

subtraction involving three bits, namely A (minuend), B (subtrahend), and Bin
(borrow-in). It accepts three inputs: A (minuend), B (subtrahend) and a Bin
(borrow bit) and it produces two outputs: D (difference) and Bout (borrow out).
Block Diagram:

Truth Table:
SOP Expressions:
Difference (D) = (A B) 'Borrowin'
Borrow (B) = A'.B + (A B)'

Observations:
(1) Half Subtractor
(a) Normal Gates:

(b) XOR Gate:

(c) NAND Gate:

(2) Full Subtractor

(a) Normal Gates:

(b) NAND Gate:

Result:
The half-subtractor and full-subtractor circuit has been simulated and verified.

EXPERIMENT 5
Aim: To simulate 2:1 MUX, 4:1 MUX and 8:1 MUX using normal gates and
NAND gate.
Software: logisim
Theory:
Multiplexer is a data selector which takes several inputs and gives a single
output. In multiplexer we have 2n input lines and 1 output lines where n is the
number of selection lines. They are also termed as “Data n selector, parallel to
serial convertor, many to one circuit, universal logic circuit”. There are 4 types
of multiplexers:
(1) 2:1 MUX
(2) 4:1 MUX
(3) 8:1 MUX
(4)16:1 MUX

(1) 2:1 MUX

Block Diagram:
Truth Table:

Logical Expression:

Z=A’0+A1

(2) 4:1 MUX

Block Diagram:

Truth Table:

0 0

0 1

1 0

1 1

Logical Expression:
Y= 0′1′0 + 1′10 + 21′0 + 310

(3) 8:1 MUX

Block Diagram:

Truth Table:

Logical Expression:

Y= 0′1′0 + 1′10 + 21′0 + 310

Observations:
(1) 2:1 MUX
(2) 4:1 MUX
(a) Normal Gates:

(b) NAND Gate:

(3) 8:1 MUX

(a) Normal Gates:
(b) NAND Gate:
Result:

The 2:1 MUX, 4:1 MUX and 8:1 MUX circuits have been simulated using
normal gates and NAND gate.

EXPERIMENT 6
Aim: To simulate 4-bit Parallel Adder and Parallel Subtractor
Software: Logisim
Theory:
(1) Parallel Adder:
A binary adder that is capable of forming sum and carry outputs for addend and
augend words of greater than one bit in length by operating on corresponding
pairs of addend and augend bits in parallel, i.e. at the same time is known as a
parallel adder.
It consists of full adders connected in a chain where the output carry from each
full adder is connected to the carry input of the next higher order full adder in
the chain.
An n-bit parallel adder requires n full adders to perform the operation.

(2) Parallel Subtractor:

A digital circuit that is used to calculate the arithmetic difference between two
binary pairs of bits is known as a parallel subtractor. Here in binary bits, the
length of one bit is higher than other bits.
The parallel binary subtractor is formed by combination of all full adders with
subtrahend complement input.
An n-bit parallel subtractor requires n full adders to perform the operation.

Observations:
(1) Parallel Adder

(2) Parallel Subtractor

Result:
The 4-bit parallel adder and parallel subtractor circuits have been simulated.

EXPERIMENT 7
Aim: To design a 1:4 DEMUX and 1:8 DEMUX using NAND Gate.
Software: logisim
Theory:
A De-multiplexer (DEMUX) performs the reverse operation of a multiplexer i.e.
it receives one input and distributes it over several outputs. De-multiplex means
one into many.
De-multiplexing is the process of taking information from one input and
transmitting the same over one of several outputs.
They are classified into four types:
(1) 1:2 DEMUX
(2) 1:4 DEMUX
(3) 1:6 DEMUX
(4) 1:8 DEMUX

(1) 1:4 DEMUX

A 1-to-4 demultiplexer has a single input, Data, four outputs (I0 to I3) and two
select inputs (S1 and S0). The input variable Din has a path to all four outputs,
but the input information is directed to only one of the output lines.

Block Diagram:

Truth Table:

SELECT OUTPUT

0 0 Data 0 0 0

0 1 0 Data 0 0

1 0 0 0 Data 0

1 1 0 0 0 Data

Logical Expressions:

Y0= S′1S′0
Y1= S′1S0

Y2= S1S′0

Y3= S1S0

(2) 1:8 DEMUX

This DEMUX can direct one data line onto 8 separate output channels and these
8 channels are controlled by 3 control signals.

Block Diagram:

Truth Table:
 A

Logical Expressions:

Y0= S′2S′1S′0

Y1= S′2S′1S0 Y2=S

′2 S1S′0

Y3=S′2 S1S0

Y4= S2S′1S′0

Y5= S2S′1S0 Y6=S2 S1S′0

Y7=S2 S1S0
Observations:
(1) 1:4 DEMUX
(a)

(b)

(c)

(d)
(e)

(2) 1:8 DEMUX

(a)

(b)
(c)

(d)

(e)
(f)

(g)

(h)
Result:
The circuit for 1:4 DEMUX has been simulated.

EXPERIMENT 8

Aim: To implement and verify Decoder

Software: Logisim
Theory:
A decoder has ‘n’ input lines to handle n bits and from one to 2n output lines to
indicate the presence of one or more n-bit combinations. Apart from this, there
is also a single line connected to the decoder called enable line. It is only
responsible for making the decoder ACTIVE or INACTIVE. If the enable “E” is
zero, then all outputs are zero regardless of the input values. If it is one, then the
decoder performs its normal operation. A decoder is a device which does the
reverse of an encoder, undoing the encoding so that the original information can
be retrieved.

(1) 2:4 Decoder: A 2:4 Decoder has 2 input lines 0 and 1, an enable line ‘E’
and 4 output lines Y0, Y1, Y2 and Y3.

Logical Expressions:

= E.A1. A0

= E.A1. A′0
= E.A′1. A0

= E.A′1. A′0

(2) 3:8 Decoder: A 3:8 Decoder has 3 input lines S0, S1 and S2 , an enable line
‘E’ and 8 output lines D0, D1, D2, D3, D4, D5, D6, D7.

Block Diagram:
= E.S′2. S′1. S′0

= E. S2. S′1. S′0

= E. S′2. S1. S′0

= E. S2. S1. S′0

= E. S′2. S′1. S0

= E. S2. S′1. S0 = E.

S′2. S1. S0

= E. S2. S1. S0
Observations:
(1) 2:4 Decoder
(a)

(b)
(c)

(d)

(2) 3:8 Decoder

(a)
(b)

(c)
(d)

(e)
(f)

(g)
(h)

Result: The Decoders circuits are implemented and verified.

EXPERIMENT 9

Aim: To design an ALU circuit

Software: Logisim
Theory:
In computing, an arithmetic logic unit (ALU) is a digital circuit that performs
arithmetic and logical operations. The ALU is a fundamental building block of
the central processing unit (CPU) of a computer, and even the simplest
microprocessors contain one for purposes such as maintaining timers. The
processors found inside modern CPUs and graphics processing units (GPUs)
accommodate very powerful and very complex ALUs; a single component may
contain several ALUs. Mathematician John von Neumann proposed the ALU
concept in 1945.

Block Diagram:
Truth Table:

Observations:
(a) Sum
(b) AND

(c) OR
(d) XOR

Result:
ALU logic circuit has been designed.
OPEN-ENDED EXPERIMENT
Aim: To design a 4-bit combinational shifter using logic gates
Software: Logisim
Theory:
Shift micro-operations are used for serial transfer of data.
Information transferred through the serial input determines the type of shift.
There are three types of shift.
(1) Logical shift
(2) Circular shift
(3) Arithmetic shift

Block Diagram:

4-BIT COMBINATIONAL CIRCUIT SHIFTER

Function Table:
When the selection input S = 0, the input data are shifted right (down in the
diagram).
When S = 1, the input data are shifted left (up in the diagram).

Observations:

Result:
4-bit combinational shifter using logic gates has been designed successfully.