FPGA Product Selection Guide

Product Selection Guides
1
Important: Verify all data in this document with the device data sheets found at www.xilinx.com
TABLE OF CONTENTS JUNE 2011
Printed in U.S.A. PN 2436-5
Zynq-7000 Extensible Processing Platform ............................................................................ 2
7 series FPGAs ................................................................................................................................................ 3
Virtex
-6 FPGAs .............................................................................................................................................. 6
Spartan
-6 FPGAs ........................................................................................................................................ 7
Virtex-5 FPGAs ............................................................................................................................................... 8
Virtex-4 FPGAs ............................................................................................................................................ 10
Extended Spartan-3A FPGAs .............................................................................................................. 11
Spartan-3 and -3E FPGAs .....................................................................................................................12
Xilinx CPLD Products ...............................................................................................................................13
Configuration Storage Solutions ........................................................................................................15
Xilinx ISE
Design Suite ......................................................................................................................... 17

Aerospace & Defense ...............................................................................................................................18
Automotive ...................................................................................................................................................... 24
Xilinx Boards & Kits .................................................................................................................................. 28
Xilinx IP Cores, Reference Designs, and Instructor Led Training Courses ............ 31
Xilinx Productivity Advantage ............................................................................................................. 32
ZYNQ-7000 EXTENSI BLE PROCESSI NG PLATFORM
2
Zynq-7000 ExtensibIe Processing PIatform
Device Name
Part Number
Processor Core
Processor Extensions
Maximum Frequency
L1 Cache
L2 Cache
On-Chip Memory
External Memory Support
External Static Memory Support
DMA Channels
Peripherals
Security
(1)
Peripherals and Static Memory Multiplexed I/O
(2)
Processing System to Programmable Logic Interface Ports
(Primary Interfaces & Interrupts Only)
Xilinx 7 Series Programmable Logic Equivalent
Programmable Logic Cells (Approximate ASIC Gates
(3)
)
Look-Up Tables (LUTs)
Flip-Flops
Extensible Block RAM (# 36 Kb Blocks)
Programmable DSP Slices (18x25 MACCs)
Programmable Logic
Kintex-7 FPGAs Artix-7 FPGAs
35,200
80 220
28K Logic Cells (~430K) 85K Logic Cells (~1.3M)
760
1,060 KB (265) 1,860 KB (465)
294,800
400
Artix-7 FPGAs
53,200 78,600
125K Logic Cells (~1.9M)
560 KB (140)
106,400
17,600
240 KB (60)
157,200
Processing System
DDR3, DDR2, LPDDR2
2x Quad-SPI, NAND, NOR
8 (4 dedicated to Programmable Logic)
2x USB 2.0 (OTG) w/DMA, 2x Tri-mode Gigabit Ethernet w/DMA,
2x SD/SDIO w/DMA, 2x UART,
2x CAN 2.0B, 2x I2C,
2x SPI, 4x 32b GPIO
54
AES and SHA 256b for secure boot
256 KB
800 MHz
32 KB Instruction, 32 KB Data per processor
512 KB
2x AXI 32b Master, 2x AXI 32b Slave,
4x AXI 64b/32b Memory
AXI 64b ACP
16 Interrupts
147,400
Z-7010 Z-7020 Z-7030 Z-7040
Zynq"-7000 ExtensibIe Processing PIatform
XC7Z010 XC7Z020 XC7Z030 XC7Z040
NEON & Single / Double Precision Floating Point
Dual ARM Cortex-A9 MPCore with CoreSight
Kintex-7 FPGAs
235K Logic Cells (~3.5M)
XMP084 (v1.1) Important: Verify all data in this document with the device data sheets found at www.xilinx.com/7 2
Peak DSP Performance (Symmetric FIR)
PCI Express (Root Complex or Endpoint)
Agile Mixed Signal (AMS) / XADC
Security
(1)
Type CSG400 CSG484 CSG400 CSG484 FBG484 FBG676 FFG676 FBG676 FFG676 FFG900
Size (mm) 17x17 19x19 17x17 19x19 23x23 27x27 27x27 27x27 27x27 31x31
Pitch (mm) 0.8 0.8 0.8 0.8 1.0 1.0 1.0 1.0 1.0 1.0
Processing System Total I/Os (includes Multiplexed I/Os) 130 130 130 130 130 130 130 130 130 130
Multi-Standards and Multi-Voltage SelectIO
TM
Interfaces
(1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V)
100 100 120 200 100 100 100 100 100 200
Multi-Standards and Multi-Voltage High Performance SelectIO Interfaces
(1.2V, 1.35V, 1.5V, 1.8V)
- - - - 63 150 150 150 150 150
Serial Transceivers - - - - 4 4 4 8 8 12
Maximum Transceiver Speed (Speed Grade Dependent) N/A N/A N/A N/A 6.6 Gb/s 6.6 Gb/s 12.5 Gb/s 6.6 Gb/s 12.5 Gb/s 12.5 Gb/s
XMP087 (v1.2)
Notes: 1. Security is shared by the Processing System and the Programmable Logic.
2. Static memory interface combined with the usage of many peripherals could require more than 54 I/Os. In that case the designer can use the Programmable Logic SelectIO interface.
3. Eqivalent ASIC gate count is dependent of the function implemented. The assumption is 1 Logic Cell = ~15 ASIC Gates.
4. Preliminary product information. Subject to change. Please contact your Xilinx representative for the latest information
AES and SHA 256b for secure configuration
Packages
Gen2 x4 Gen2 x8
2x 12 bit, 1 MSPS ADCs with up to 17 Differential Inputs
- -
912 GMACS 58 GMACS 158 GMACS 480 GMACS
7 SERI ES FPGAS
3
Important: Verify all data in this document with the device data sheets found at www.xilinx.com/7
(1.0V)
XC7V585T XC7V1500T XC7V2000T XC7VX330T XC7VX415T XC7VX485T XC7VX550T XC7VX690T XC7VX980T XC7VX1140T XC7VH290T XC7VH580T XC7VH870T
XCEZv585T XCEZv1500T XCEZv2000T XCEZvX330T XCEZvX115T XCEZvX185T XCEZvX550T XCEZvX90T XCEZvX980T XCEZvX1110T
91,050 229,050 305,400 51,000 64,400 75,900 86,600 108,300 153,000 178,000 44,375 90,700 136,900
582,720 1,465,920 1,954,560 326,400 412,160 485,760 554,240 693,120 979,200 1,139,200 284,000 580,480 876,160
728,400 1,832,400 2,443,200 408,000 515,200 607,200 692,800 866,400 1,224,000 1,424,000 355,000 725,600 1,095,200
6,938 16,163 21,550 4,388 6,525 8,175 8,725 10,888 13,838 17,700 4,425 8,850 13,275
795 969 1,292 750 880 1,030 1,180 1,470 1,500 1,880 470 940 1,410
28,620 34,884 46,512 27,000 31,680 37,080 42,480 52,920 54,000 67,680 16,920 33,840 50,760
Clocking 18 18 24 14 12 14 16 20 18 24 6 12 18
850 850 1,200 700 600 700 600 1,000 900 1100 300 600 650
408 408 576 336 288 336 288 480 432 528 144 288 312
1,260 1,620 2,160 1,120 2,160 2,800 2,880 3,600 3,600 3,360 840 1,680 2,520
3 3 4 - - 4 - - - - - - -
- - - 2 2 - 2 3 3 4 1 2 3
1 1 1 1 1 1 1 1 1 1 1 1 1
Configuration AES / HMAC Blocks 1 1 1 1 1 1 1 1 1 1 1 1 1
36 36 36 - - 56 - - - - - - -
- - - 28 48 - 64 80 72 96 24 48 72
GTZ 28.05Gb/s Transceivers - - - - - - - - - - 8 8 16
-1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2
-2L, -3 -2L, -2G -2L, -2G -2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L -2L, -2G -2L, -2G -2L, -2G -2L, -2G
-1, -2 -1 -1 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1 -1 - - -
Configuration 153.9 319.9 426.6 106.1 131.5 154.7 175.4 219.2 269.4 367.2 91.8 183.6 275.4
Package
(8)
Area
FFG1157 35 x 35 mm 0, 600 (20, 0) 0, 600 (0, 20) 0, 600 (0, 20) 0, 600 (20, 0) 0, 600 (0, 20)
(9)
EasyPath Cost Reduction Solutions
(1)
XILINX VIRTEX
-7 FPGAS
Virtex-7 FPGAs
Optimized for Highest System Performance and Capacity
(1.0V, 0.9V) (1.0V, 0.9V)
Part Number
Logic
Resources
Slices
(2)
Logic Cells
(3)
CLB Flip-Flops
Memory
Resources
Maximum Distributed RAM (Kbits)
Block RAM/FIFO w/ ECC (36Kbits each)
Total Block RAM (Kbits)
CMTs (1 MMCM + 1 PLL)
I/O Resources
Maximum Single-Ended I/O
(4)
Maximum Differential I/O Pairs
(4)
Embedded
Hard IP
Resources
DSP48E1 Slices
Gen2 PCI Express Interface Blocks
Gen3 PCI Express Interface Blocks
GTX 12.5Gb/s Transceivers
(5)
Speed Grades
Commercial
Extended
(7, 12)
Industrial
Configuration Memory (Mbits)
Available User I/O: 3.3V SelectIO
TM
Pins, 1.8V SelectIO Pins (GTX, GTH Transceivers) 1.8V SelectIO Pins (GTH, GTZ)
Flip chip, fine pitch BGA (1.0 mm ball spacing)
GTH 13.1Gb/s Transceivers
(6)
FFG1761
(9)
42.5 x 42.5 mm 100, 750 (36, 0) 50, 650 (0, 28) 0, 700 (28, 0) 0, 850 (0, 36)
FLG1761
(9)
42.5 x 42.5 mm 0, 850 (36, 0)
FHG1761
(9)
45 x 45 mm 0, 850 (36, 0)
FLG1925 45 x 45 mm 0, 1200 (16, 0)
FFG1158 35 x 35 mm 0, 350 (0, 48) 0, 350 (48, 0) 0, 350 (0, 48) 0, 350 (0, 48)
FFG1926 45 x 45 mm 0, 720 (0, 64) 0, 720 (0, 64)
FFG1927 45 x 45 mm 0, 600 (0, 48) 0, 600 (56, 0) 0, 600 (0, 64) 0, 600 (0, 80)
FFG1928
(10)
45 x 45 mm 0, 480 (0, 72)
FLG1928
(10)
45 x 45 mm 0, 480 (0, 96)
FFG1930
(11)
45 x 45 mm 0, 700 (24, 0) 0, 1000 (0, 24) 0, 900 (0, 24)
FLG1930
(11)
45 x 45 mm 0, 1100 (0, 24)
HCG1155 35 x 35 mm 300 (24, 8) 400 (24, 8)
HCG1931 45 x 45 mm 600 (48, 8) 650 (48, 8)
HCG1932 45 x 45 mm 200 (48, 8) 200 (72, 16)
Notes: 1. EasyPath solutions provide a fast and conversion-free path for cost reduction. XMP084 (v4.1)
2. A single Virtex-7 FPGA CLB comprises two slices, with each containing four 6-input LUTs and eight Flip-Flops, for a total of eight 6-LUTs and 16 Flip-Flops per CLB.
3. Virtex-7 FPGA logic cell ratings reflect the increased logic capacity offered by the 6-input LUT architecture. 11. Virtex-7 FPGAs in FFG1930 and FLG1930 packages are footprint compatible. See package guide for differences.
4. Refer to data sheet for details on I/O standards support. 12. -2G supports 12.5G GTX, 13.1G GTH, 28.05G GTZ with -2 fabric.
5. 12.5 Gb/s support in "-3E", "-2GE" speed/temperature grade; 10.3125 Gb/s support in "2C", "-2LE", and "-2I" speed grade.
6. 13.1 Gb/s support in "-3E". "-2GE" speed grade; 11.3 Gb/s support in "2C" and "-2LE" speed/temperature grades; 10.3125 Gb/s in "-2I" speed/temperature grades.
7. See data sheet for information on low-power operating modes.
8. Leaded package options ("FFxxxx"/"FLxxxx"/"FHxxxx"/"HCxxxx") available for all packages. 13. Please contact your Xilinx representative for the latest information.
9. Virtex-7 FPGAs in FFG1761, FLG1761, and FHG1761 packages are footprint compatible. See package guide for differences.
10. Virtex-7 FPGAs in FFG1928 and FLG1928 packages are footprint compatible. See package guide for differences.
Ceramic flip chip, fine pitch BGA (1.0 mm ball spacing)
7 SERI ES FPGAS
4
XILINX KINTEX-7 FPGAS
XC7K70T XC7K160T XC7K325T XC7K355T XC7K410T XC7K420T XC7K480T
10,250 25,350 50,950 55,650 63,550 65,150 74,650
65,600 162,240 326,080 356,160 406,720 416,960 477,760
82,000 202,800 407,600 445,200 508,400 521,200 597,200
838 1,938 4,000 4,938 5,663 5,763 6,588
135 325 445 715 795 835 955
4,860 11,700 16,020 25,740 28,620 30,060 34,380
Clock Resources 6 8 10 6 10 7 8
300 400 500 300 500 350 400
144 192 240 144 240 168 192
240 600 840 1,440 1,540 1,680 1,920
1 1 1 1 1 1 1
1 1 1 1 1 1 1
Configuration AES / HMAC Blocks 1 1 1 1 1 1 1
8 8 16 24 16 28 32
-1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2
-2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3
-1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2
Configuration 23.2 45.1 88.2 105.1 122.0 122.6 140.1
Package Area
Kintex-7 FPGAs
Optimized for Best Price-Performance
(1.0V, 0.9V)
Part Number
Available User I/O: 3.3V SelectIO
TM
Pins, 1.8V SelectIO Pins (GTX Transceivers)
Lidless flip chip BGA supporting 6.6 Gb/s serial line rates (1.0mm ball spacing)
Speed Grades
Commercial
Industrial
I/O Resources
(2)
(2)
Embedded
Hard IP
Resources
DSP48E1 Slices
PCI Express Interface Blocks
(3)
GTX 12.5 Gb/s Transceivers
Extended
Logic Resources
Slices
(1)
Logic Cells
CLB Flip-Flops
Memory
Resources
FBG484
(4)
23 x 23 mm 185, 100 (4) 185, 100 (4)
FBG676
(4)
27 x 27 mm 200, 100 (8) 250, 150 (8) 250, 150 (8) 250, 150 (8)
FBG900
(4)
31 x 31 mm 350, 150 (16) 350, 150 (16)
FFG676
(4)
27 x 27 mm 250, 150 (8) 250, 150 (8) 250, 150 (8)
FFG900
(4)
31 x 31 mm 350, 150 (16) 350, 150 (16)
FFG901
(4)
31 x 31 mm 300, 0 (24) 350, 0 (28) 380, 0 (28)
FFG1156
(4)
35 x 35 mm 350, 0 (28) 400, 0 (32)
XMP085 (v3.1)
Notes: 1. A single Kintex-7 FPGA CLB comprises two slices, with each containing four 6-input LUTs and eight Flip-Flops, for a total of eight 6-LUTs and 16 Flip-Flops per CLB.
5. Preliminary product information, subject to change. Please contact your Xilinx representative for the latest information.
2. Refer to data sheet for details on I/O standards support.
4. Leaded package options ("FBxxx" or "FFxxx") available for the following Kintex-7 devices: XC7K160T, XC7K325T, XC7K355T, XC7K410T, XC7K420T, XC7K480T
Flip chip BGA supporting 12.5 Gb/s serial line rates (1.0mm ball spacing)
Lidless flip chip BGA supporting 6.6 Gb/s serial line rates (1.0mm ball spacing)
3. Hard block supports PCI Express Base 2.1 specification at Gen1 and Gen2 data rates. Gen3 supported with soft IP.
7 SERI ES FPGAS
5
XILINX ARTIX-7 FPGAS
XC7A8 XC7A15 XC7A30T XC7A50T XC7A100T XC7A200T XC7A350T
1,250 2,400 5,250 8,150 15,850 32,250 54,450
8,000 15,360 33,600 52,160 101,440 206,400 348,480
10,000 19,200 42,000 65,200 126,800 258,000 435,600
100 200 400 600 1,188 3,013 4,738
20 40 52 75 135 365 515
720 1,440 1,872 2,700 4,860 13,140 18,540
Clock Resources 2 2 5 5 6 10 12
200 200 250 250 300 500 600
96 96 120 120 144 240 288
20 40 80 120 240 740 1,040
- - 1 1 1 1 1
1 1 1 1 1 1 1
Configuration AES / HMAC Blocks 1 1 1 1 1 1 1
GTP 5.0 / 6.6 Gb/s Transceivers - - 4 4 8 16 16
-1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2
-2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3
-1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2
Configuration 5.0 5.0 10.0 10.0 27.0 45.0 85.0
Package Area
Extended
Available User I/O: 3.3V SelectIO Pins (GTP Transceivers)
Wire bond, chip scale BGA (0.5 mm ball spacing)
Part Number
Slices
(1)
Logic Cells
(2)
CLB Flip-Flops
Artix-7 FPGAs
Optimized for Lowest Cost and Power with Small Form-Factor Packaging for Highest Volume Applications
(1.0V, 0.9V)
Logic Resources
Memory
Resources
Speed Grades
Commercial
Industrial
I/O Resources
(4)
(4)
Embedded
Hard IP
Resources
DSP48E1 Slices
(3)
CPG236 10 x 10 mm 140 (0) 140 (0)
CSG225 12 x 12 mm 100 (4) 100 (4)
CSG324 15 x 15 mm 200 (0) 200 (0) 210 (0) 210 (0) 210 (0)
FTG256 17 x 17 mm 170 (0) 170 (0) 170 (0) 170 (0) 170 (0)
FGG484
(5)
23 x 23 mm 250 (4) 250 (4) 285 (4)
FGG676
(6,7)
27 x 27 mm 300 (8)
FBG484
(5,7)
23 x 23 mm 285 (4) 285 (4)
FBG676
(6,7)
27 x 27 mm 400 (8) 400 (8)
FFG1156
(7)
35 x 35 mm 500 (16) 600 (16)
XMP086 (v2.1)
Notes: 1. A single Artix-7 FPGA CLB comprises two slices, with each containing four 6-input LUTs and eight Flip-Flops, for a total of eight 6-LUTs and 16 Flip-Flops per CLB.
2. Artix-7 FPGA logic cell ratings reflect the increased logic capacity offered by the 6-input LUT architecture.
5. Artix-7 FPGAs in FGG484 and FBG484 packages are footprint compatible.
6. Artix-7 FPGAs in FGG676 and FBG676 packages are footprint compatible.
7. Leaded package options available.
8. Preliminary product information, subject to change. Please contact your Xilinx representative for the latest information.
4. Refer to data sheet for details on I/O standards support.
Wire bond, fine pitch BGA (1.0 mm ball spacing)
3. Supports PCI Express Base 2.1 specification at Gen1 and Gen2 data rates.
Lidless flip chip BGA (1.0 mm ball spacing)
Flip chip BGA (1.0 mm ball spacing)
6
VI RTEX
-6 FPGAS
VI RTEX
-6 FPGAS
XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T
XCE6VLX75T XCE6VLX130T XCE6VLX195T XCE6VLX240T XCE6VLX365T XCE6VLX550T XCE6VLX760 XCE6VSX315T XCE6VSX475T XCE6VHX250T XCE6VHX255T XCE6VHX380T XCE6VHX565T
11,640 20,000 31,200 37,680 56,880 85,920 118,560 49,200 74,400 39,360 39,600 59,760 88,560
74,496 128,000 199,680 241,152 364,032 549,888 758,784 314,880 476,160 251,904 253,440 382,464 566,784
93,120 160,000 249,600 301,440 455,040 687,360 948,480 393,600 595,200 314,880 316,800 478,080 708,480
1,045 1,740 3,040 3,650 4,130 6,200 8,280 5,090 7,640 3,040 3,050 4,570 6,370
156 264 344 416 416 632 720 704 1,064 504 516 768 912
5,616 9,504 12,384 14,976 14,976 22,752 25,920 25,344 38,304 18,144 18,567 27,648 32,832
Clock Resources 6 10 10 12 12 18 18 12 18 12 12 18 18
360 600 600 720 720 1,200 1,200 720 840 320 480 720 720
180 300 300 360 360 600 600 360 420 160 240 360 360
288 480 640 768 576 864 864 1,344 2,016 576 576 864 864
1 2 2 2 2 2 - 2 2 4 2 4 4
4 4 4 4 4 4 - 4 4 4 2 4 4
12 20 20 24 24 36 - 24 36 48 24 48 48
- - - - - - - - - - 24 24 24
-L1, -1, -2, -3 -L1, -1, -2, -3 -L1, -1, -2, -3 -L1, -1, -2, -3 -L1, -1, -2, -3 -L1, -1, -2 -L1, -1, -2 -L1, -1, -2, -3 -L1, -1, -2 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2
- - - - - -2 -2 - -2 - - -2 -
-L1, -1, -2 -L1, -1, -2 -L1, -1, -2 -L1, -1, -2 -L1, -1, -2 -L1, -1 -L1, -1 -L1, -1, -2 -L1, -1 -1, -2 -1, -2 -1, -2 -1
Configuration 26 3 43 8 61 6 73 9 96 1 144 1 184 9 104 5 156 7 79 9 79 9 119 8 160 7
XILINX VIRTEX
-6 FPGAS
EasyPath FPGA Cost Reduction
Solutions
(1)
Slices
(2)
Logic Cells
(3)
CLB Flip-Flops
Virtex-6 LXT FPGAs
Optimized for High-Performance Logic and DSP
with Low-Power Serial Connectivity
(1.0V, 0.9V)
Virtex-6 SXT FPGAs
Optimized for Ultra High-
Performance DSP with Low-
Power Serial Connectivity
(1.0V, 0.9V)
Virtex-6 HXT FPGAs
Optimized for Communications Systems that Require
Highest-Bandwidth Serial Connectivity
(1.0V)
Part Number
Maximum Distributed RAM (Kb)
Logic Resources
Memory
Resources
I/O Resources
(4,5)
Embedded Hard
IP Resources
(6)
Block RAM/FIFO w/ECC (36 Kb each)
Total Block RAM (Kb)
Mixed-Mode Clock Managers (MMCM)
Speed Grades
DSP48E1 Slices
Extended
Configuration Memory (Mb)
10/100/1000 Ethernet MAC Blocks
GTX Low-Power Transceivers
GTH High-Speed Transceivers
Commercial
Industrial
XMP068 (v1.0) Important: Verify all data in this document with the device data sheets found at www.xilinx.com 6
Configuration 26.3 43.8 61.6 73.9 96.1 144.1 184.9 104.5 156.7 79.9 79.9 119.8 160.7
Package
(7)
Area
FF484 23 x 23 mm 240 (8, 0) 240 (8, 0)
FF784 29 x 29 mm 360 (12, 0) 400 (12, 0) 400 (12, 0) 400 (12, 0)
FF1156 35 x 35 mm 600 (20, 0) 600 (20, 0) 600 (20, 0) 600 (20, 0) 600 (20, 0) 600 (20, 0)
FF1759 42.5 x 42.5 mm 720 (24, 0) 720 (24, 0) 840 (36, 0) 720 (24, 0) 840 (36, 0)
FF1760 42.5 x 42.5 mm 1,200 (0, 0) 1,200 (0, 0)
FF1154 35 x 35 mm 320 (48, 0) 320 (48, 0)
FF1155 35 x 35 mm 440 (24, 12) 440 (24, 12)
FF1923 45 x 45 mm 480 (24, 24) 720 (40, 24) 720 (40, 24)
FF1924 45 x 45 mm 640 (48, 24) 640 (48, 24)
XMP068 (v1.1)
Notes:
2. A single Virtex-6 FPGA CLB comprises two slices, each containing four 6-input LUTs and eight flip-flops (twice the number found in a Virtex-4 FPGA slice), for a total of eight 6-input LUTs and 16 flip-flops per CLB.
3. Virtex-6 FPGA logic cell ratings reflect the increased logic capacity offered by the 6-input LUT architecture.
4. Digitally Controlled Impedance (DCI) is available on I/Os of all devices.
6. One System Monitor block is included in all devices.
7. All products are available Pb-free and RoHS-Compliant (FFG).
5. Supported I/O standards include: HT, LVCMOS (1.2V, 1.5V, 1.8V, 2.5V), HSTL I (1.2V,1.5V,1.8V), HSTL II (1.5V,1.8V), HSTL III (1.5V,1.8V), LVDS, Extended LVDS, RSDS, Bus LVDS, LVPECL, SSTL I (1.8V, 2.5V), SSTL II (1.8V, 2.5V), and SSTL (1.5V).
5. Supported I/O standards include: HT, LVDS, LVDSEXT, RSDS, BLVDS, ULVDS, LVPECL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVTTL, PCI33, PCI66, PCI-X, GTL, GTL+, HSTL I (1.2V, 1.5V, 1.8V), HSTL II (1.5V, 1.8V),
HSTL III (1.5V, 1.8V), HSTL IV (1.5V, 1.8V), SSTL2 I, SSTL II, SSTL18 I, and SSTL18 II.
Available User I/O: SelectIO Interface Pins
(4, 5)
(GTX Low-Power Transceivers, GTH High-Speed Transceivers)
FFA Packages (FF): Flip-chip, fine-pitch BGA (1.0 mm ball spacing)
1. EasyPath FPGAs provide a conversion-free, low-risk path for volume production.
7
SPARTAN
-6 FPGAS
XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX45 XC6SLX75 XC6SLX100 XC6SLX150 XC6SLX25T XC6SLX45T XC6SLX75T XC6SLX100T XC6SLX150T
600 1,430 2,278 3,758 6,822 11,662 15,822 23,038 3,758 6,822 11,662 15,822 23,038
3,840 9,152 14,579 24,051 43,661 74,637 101,261 147,443 24,051 43,661 74,637 101,261 147,443
4,800 11,440 18,224 30,064 54,576 93,296 126,576 184,304 30,064 54,576 93,296 126,576 184,304
75 90 136 229 401 692 976 1,355 229 401 692 976 1,355
12 32 32 52 116 172 268 268 52 116 172 268 268
216 576 576 936 2,088 3,096 4,824 4,824 936 2,088 3,096 4,824 4,824
Clock Resources
2 2 2 2 4 6 6 6 2 4 6 6 6
132 200 232 266 358 408 480 576 250 296 348 498 540
66 100 116 133 179 204 240 288 125 148 174 249 270
8 16 32 38 58 132 180 180 38 58 132 180 180
- - - - - - - - 1 1 1 1 1
0 2 2 2 2 4 4 4 2 2 4 4 4
- - - - - - - - 2 4 8 8 8
-1L, -2, -3 -1L, -2, -3, -3N -1L, -2, -3, -3N -1L, -2, -3, -3N -1L, -2, -3, -3N -1L, -2, -3, -3N -1L, -2, -3, -3N -1L, -2, -3, -3N -2, -3, -3N -2, -3, -3N -2, -3, -3N -2, -3, -3N -2, -3, -3N
-1L, -2, -3 -1L, -2, -3, -3N -1L, -2, -3, -3N -1L, -2, -3, -3N -1L, -2, -3, -3N -1L, -2, -3, -3N -1L, -2, -3, -3N -1L, -2, -3, -3N -2, -3, -3N -2, -3, -3N -2, -3, -3N -2, -3, -3N -2, -3, -3N
Configuration
2.7 2.7 3.7 6.4 11.9 19.6 26.5 33.8 6.4 11.9 19.6 26.5 33.8
Package Body Area
CPG196
(7)
8 x 8 mm 106 106 106
TQG144
(7)
20 x 20 mm 102 102
XILINX SPARTAN
-6 FPGAS
DSP48A1 Slices
(5)
Block RAM (18 Kb each)
(3)
Clock Management Tiles (CMT)
(4)
Endpoint Block for PCI Express
Memory Controller Blocks
GTP Low-Power Transceivers
Commercial
(10)
Maximum Single-Ended Pins
Maximum Differential Pairs
Logic Resources
Memory Resources
I/O Resources
Embedded Hard IP
Resources
Speed Grades
Slices
(1)
Logic Cells
(2)
CLB Flip-Flops
Spartan-6 LX FPGAs
Optimized for Lowest-Cost Logic, DSP, and Memory
(1.2V, 1.0V)
Spartan-6 LXT FPGAs
with High-Speed Serial Connectivity
(1.2V)
Maximum User I/O: SelectIO Interface Pins (GTP Transceivers)
(6)
Chip Scale Packages (CPG): Pb-free, wire-bond, chip scale BGA (0.5 mm ball spacing)
TQFP Packages (TQG): Pb-free, thin QFP (0.5 mm lead spacing)
Industrial
(10)
Part Number
CSG225
(8)
13 x 13 mm 132 160 160
CSG324 15 x 15 mm 200 232 226 218 190 (2) 190 (4)
CSG484
(9)
19 x 19 mm 320 328 338 338 296 (4) 292 (4) 296 (4) 296 (4)
FT(G)256 17 x 17 mm 186 186 186
FG(G)484
(9)
23 x 23 mm 266 316 280 326 338 250 (2) 296 (4) 268 (4) 296 (4) 296 (4)
FG(G)676 27 x 27 mm 358 408 480 498 348 (8) 376 (8) 396 (8)
FG(G)900 31 x 31 mm 576 498 (8) 540 (8)
XMP071 (v1.2)
Notes: 1. Each slice contains four LUTs and eight flip-flops.
2. Spartan-6 FPGA logic cell ratings reflect the increased logic capacity offered by the new 6-input LUT architecture.
3. Block RAM are fundamentally 18Kb in size. Each block can also be used as two independent 9 Kb blocks.
4. Each CMT contains two DCMs and one PLL.
5. Each DSP48A1 slice contains an 18x18 multiplier, an adder, and an accumulator.
6. The LX device pinouts are not compatible with the LXT device pinouts.
7. CPG196 and TQG144 do not have memory controller support. -3N is not available for these packages.
8. CSG225 has X8 memory controller support in the LX9 and LX16 devices. There is no memory controller in the LX4 devices.
9. Devices in the FG(G)484 and CSG484 packages have support for two memory controllers.
10. Devices with -3N speed grade do not support MCB functionality
BGA Packages (FGG): Pb and Pb-free, wire-bond, fine-pitch BGA (1.0 mm ball spacing)
BGA Packages (FTG): Pb and Pb-free, wire-bond, fine-pitch thin BGA (1.0 mm ball spacing)
Chip Scale Packages (CSG): Pb-free, wire-bond, chip scale BGA (0.8 mm ball spacing)
8
VI RTEX
-5 FPGAS
XC5VLX30 XC5VLX50 XC5VLX85 XC5VLX110 XC5VLX155 XC5VLX220 XC5VLX330 XC5VLX20T XC5VLX30T XC5VLX50T XC5VLX85T XC5VLX110T XC5VLX155T XC5VLX220T XC5VLX330T
- - XCE5VLX85 XCE5VLX110 XCE5VLX155 XCE5VLX220 XCE5VLX330 - - - XCE5VLX85T XCE5VLX110T XCE5VLX155T XCE5VLX220T XCE5VLX330T
4,800 7,200 12,960 17,280 24,320 34,560 51,840 3,120 4,800 7,200 12,960 17,280 24,320 34,560 51,840
30,720 46,080 82,944 110,592 155,648 221,184 331,776 19,968 30,720 46,080 82,944 110,592 155,648 221,184 331,776
19,200 28,800 51,840 69,120 97,280 138,240 207,360 12,480 19,200 28,800 51,840 69,120 97,280 138,240 207,360
320 480 840 1,120 1,640 2,280 3,420 210 320 480 840 1,120 1,640 2,280 3,420
32 48 96 128 192 192 288 26 36 60 108 148 212 212 324
1,152 1,728 3,456 4,608 6,912 6,912 10,368 936 1,296 2,160 3,888 5,328 7,632 7,632 11,664
4 12 12 12 12 12 12 2 4 12 12 12 12 12 12
2 6 6 6 6 6 6 1 2 6 6 6 6 6 6
400 560 560 800 800 800 1,200 172 360 480 480 680 680 680 960
200 280 280 400 400 400 600 86 180 240 240 340 340 340 480
32 48 48 64 128 128 192 24 32 48 48 64 128 128 192
- - - - - - - - - - - - - - -
- - - - - - - 1 1 1 1 1 1 1 1
- - - - - - - 2 4 4 4 4 4 4 4
- - - - - - - 4 8 12 12 16 16 16 24
- - - - - - - - - - - - - - -
-1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2 -1, -2 -1, -2 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2 -1, -2
-1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1
Configuration 8.4 12.6 21.9 29.1 41.1 53.2 79.8 6.3 9.4 14.1 23.4 31.2 43.1 55.2 82.7
XILINX VIRTEX
-5 FPGAS
Speed Grades
I/O Resources
(4,5)
Clock Resources
Memory
Resources
RocketIO GTP Low-Power Transceivers
Logic Resources
DSP48E Slices
Embedded Hard
IP Resources
(6)
Digital Clock Managers (DCM)
RocketIO GTX High-Speed Transceivers
Commercial
Industrial
CLB Flip-Flops
Phase-Locked Loop (PLL)/PMCD
Virtex-5 LX FPGAs
Optimized for High-Performance Logic
(1.0V)
Virtex-5 LXT FPGAs
Optimized for High-Performance Logic with
Low-Power Serial Connectivity
(1.0V)
PowerPC 440 Processor Blocks
Endpoint Blocks for PCI Express
Part Number
EasyPath FPGA Cost Reduction
Solutions
(1)
Slices
(2)
Logic Cells
(3)
Package
(7)
Area
FF324 19 x 19 mm 220 220
FF676 27 x 27 mm 400 440 440 440
FF1153 35 x 35 mm 560 560 800 800
FF1760 42.5 x 42.5 mm 800 800 800 1,200
FF323 19 x 19 mm 172 (4) 172 (4)
FF665 27 x 27 mm 360 (8) 360 (8)
FF1136 35 x 35 mm 480 (12) 480 (12) 640 (16) 640 (16)
FF1738 42.5 x 42.5 mm 680 (16) 680 (16) 680 (16) 960 (24)
FF1156 35 x 35 mm
FF1759 42.5 x 42.5 mm
XMP069 (v1.1)
Notes: 1. EasyPath FPGAs provide a conversion-free, low-risk path for volume production.
2. A single Virtex-5 FPGA CLB comprises two slices, each containing four 6-input LUTs and four flip-flops (twice the number found in a Virtex-4 FPGA slice), for a total of eight 6-input LUTs and eight flip-flops per CLB.
3. Virtex-5 FPGA logic cell ratings reflect the increased logic capacity offered by the 6-input LUT architecture.
6. One System Monitor block is included in all devices.
5. Supported I/O standards include: HT, LVDS, LVDSEXT, RSDS, BLVDS, ULVDS, LVPECL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVTTL, PCI33, PCI66, PCI-X, GTL, GTL+, HSTL I (1.2V, 1.5V, 1.8V), HSTL II (1.5V, 1.8V), HSTL III (1.5V, 1.8V), HSTL IV (1.5V, 1.8V), SSTL2 I,
SSTL2 II, SSTL18 I, and SSTL18 II.
(4,5)
(GTP/GTX Serial Transceivers)
9
VI RTEX
-5 FPGAS
XC5VSX35T XC5VSX50T XC5VSX95T XC5VSX240T XC5VFX30T XC5VFX70T XC5VFX100T XC5VFX130T XC5VFX200T XC5VTX150T XC5VTX240T
- XCE5VSX50T XCE5VSX95T XCE5VSX240T - XCE5VFX70T XCE5VFX100T XCE5VFX130T XCE5VFX200T XCE5VTX150T XCE5VTX240T
5,440 8,160 14,720 37,440 5,120 11,200 16,000 20,480 30,720 23,200 37,440
34,816 52,224 94,208 239,616 32,768 71,680 102,400 131,072 196, 608 148,480 239,616
21,760 32,640 58,880 149,760 20,480 44,800 64,000 81,920 122,880 92,800 149,760
520 780 1,520 4,200 380 820 1,240 1,580 2,280 1,500 2,400
84 132 244 516 68 148 228 298 456 228 324
3,024 4,752 8,784 18,576 2,448 5,328 8,208 10,728 16,416 8,208 11,664
4 12 12 12 4 12 12 12 12 12 12
2 6 6 6 2 6 6 6 6 6 6
360 480 640 960 360 640 680 840 960 680 680
180 240 320 480 180 320 340 420 480 340 340
192 288 640 1,056 64 128 256 320 384 80 96
- - - - 1 1 2 2 2 - -
1 1 1 1 1 3 3 3 4 1 1
4 4 4 4 4 4 4 6 8 4 4
8 12 16 24 - - - - - - -
- - - - 8 16 16 20 24 40 48
-1, -2, -3 -1, -2, -3 -1, -2 -1, -2 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2 -1, -2 -1, -2
-1, -2 -1, -2 -1, -2 -1 -1, -2 -1, -2 -1, -2 -1, -2 -1 -1, -2 -1, -2
Configuration 13.4 20.0 35.8 79.7 13.6 27.1 39.4 49.3 70.9 43.4 65.8
Package
(7)
Area
Virtex-5 SXT FPGAs
Optimized for DSP with Low-Power
Serial Connectivity
(1.0V)
Slices
(2)
EasyPath FPGA Cost Reduction Solutions
(1)
Logic Cells
(3)
Phase-Locked Loop (PLL)/PMCD
XILINX VIRTEX
-5 FPGAS
Endpoint Blocks for PCI Express Embedded Hard IP
Resources
(6)
Speed Grades
(4, 5)
Logic Resources
Memory Resources
Clock Resources
I/O Resources
(4,5)
Virtex-5 FXT FPGAs
Optimized for Embedded Processing with High-Speed
Serial Connectivity
(1.0V)
Virtex-5 TXT FPGAs
Optimized for Ultra-High
Bandwidth
(1.0V)
Part Number
Industrial
CLB Flip-Flops
DSP48E Slices
Commercial
Package
(7)
Area
FF324 19 x 19 mm
FF676 27 x 27 mm
FF1153 35 x 35 mm
FF1760 42.5 x 42.5 mm
FF323 19 x 19 mm
FF665 27 x 27 mm 360 (8) 360 (8) 360 (8) 360 (8)
FF1136 35 x 35 mm 480 (12) 640 (16) 640 (16) 640 (16)
FF1738 42.5 x 42.5 mm 960 (24) 680 (16) 840 (20) 960 (24)
FF1156 35 x 35 mm 360 (40)
FF1759 42.5 x 42.5 mm 680 (40) 680 (48)
XMP069 (v1.1)
Notes: 1. EasyPath FPGAs provide a conversion-free, low-risk path for volume production.
3. Virtex-5 FPGA logic cell ratings reflect the increased logic capacity offered by the new 6-input LUT architecture.
6. One System Monitor block included in all devices.
5. Supported I/O standards include: HT, LVDS, LVDSEXT, RSDS, BLVDS, ULVDS, LVPECL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVTTL, PCI33, PCI66, PCI-X, GTL, GTL+, HSTL I (1.2V, 1.5V, 1.8V), HSTL II (1.5V, 1.8V), HSTL III (1.5V, 1.8V), HSTL IV (1.5V, 1.8V),
SSTL2 I, SSTL2 II, SSTL18 I, and SSTL18 II.
2. A single Virtex-5 FPGA CLB comprises two slices, each containing four 6-input LUTs and four flip-flops (twice the number found in a Virtex-4 FPGA slice), for a total of eight 6-input LUTs and eight flip-flops per CLB.
(4, 5)
10
VI RTEX
-4 FPGAS
XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140
- - XCE4VLX40 XCE4VLX60 XCE4VLX80XCE4VLX100XCE4VLX160XCE4VLX200 - XCE4VSX35 XCE4VSX55 - - XCE4VFX40 XCE4VFX60 XCE4VFX100 XCE4VFX140
6,144 10,752 18,432 26,624 35,840 49,152 67,584 89,088 10,240 15,360 24,576 5,472 8,544 18,624 25,280 42,176 63,168
13,824 24,192 41,472 59,904 80,640 110,592 152,064 200,448 23,040 34,560 55,296 12,312 19,224 41,904 56,880 94,896 142,128
12,288 21,504 36,864 53,248 71,680 98,304 135,168 178,176 20,480 30,720 49,152 10,944 17,088 37,248 50,560 84,352 126,336
96 168 288 416 560 768 1,056 1,392 160 240 384 86 134 291 395 659 987
48 72 96 160 200 240 288 336 128 192 320 36 68 144 232 376 552
864 1,296 1,728 2,880 3,600 4,320 5,184 6,048 2,304 3,456 5,760 648 1,224 2,592 4,176 6,768 9,936
4 8 8 8 12 12 12 12 4 8 8 4 4 8 12 12 20
0 4 4 4 8 8 8 8 0 4 4 0 0 4 8 8 8
320 448 640 640 768 960 960 960 320 448 640 320 320 448 576 768 896
160 224 320 320 384 480 480 480 160 224 320 160 160 224 228 384 448
32 48 64 64 80 96 96 96 128 192 512 32 32 48 128 160 192
- - - - - - - - - - - 1 1 2 2 2 2
- - - - - - - - - - - 2 2 4 4 4 4
- - - - - - - - - - - 0 8 12 16 20 24
-10,-11, -12 -10,-11, -12 -10,-11, -12 -10,-11, -12 -10,-11, -12 -10,-11, -12 -10,-11, -12 -10,-11 -10,-11, -12 -10,-11, -12 -10,-11, -12 -10,-11, -12 -10,-11, -12 -10,-11, -12 -10,-11, -12 -10,-11, -12 -10,-11
-10,-11 -10,-11 -10,-11 -10,-11 -10,-11 -10,-11 -10,-11 -10 -10,-11 -10,-11 -10,-11 -10,-11 -10,-11 -10,-11 -10,-11 -10,-11 -10
Configuration 4.8 7.8 12.3 17.7 23.3 30.7 40.3 51.4 9.1 13.7 22.7 4.8 7.2 14.9 21.0 33.0 47.9
Package
(6)
Area
XILINX VIRTEX
-4 FPGAS
Logic Resources
Memory
Resources
Clock Resources
Logic Cells
CLB Flip-Flops
Industrial
Commercial
RocketIO Serial Transceivers
SFA Packages (SF): Flip chip fine pitch BGA (0 8 mm ball spacing)
PowerPC Processor Blocks
I/O Resources
(3,4)
(4, 5)
(RocketIO Transceivers)
Embedded Hard IP
Resources
Speed Grades
DSP48 Slices
Maximum Single-Ended I/Os
Phase-Matched Clock Dividers (PMCD)
Virtex-4 FX FPGAs
Optimized for Embedded Processing and Serial Connectivity
(1.2V)
Part Number
EasyPath FPGA Cost Reduction Solutions
(1)
Slices
(2)
Virtex-4 LX FPGAs
Optimized for High-Performance Logic
(1.2V)
Virtex-4 SX FPGAs
Optimized for DSP
(1.2V)
SF363 17 x 17 mm 240 240 240
FF668 27 x 27 mm 320 448 448 448 320 448 320
FF1148 35 x 35 mm 640 640 768 768 768 640
FF1513 40 x 40 mm 960 960 960
FF672 27 x 27 mm 320 (8) 352 (12) 352 (12)
FF1152 35 x 35 mm 448 (12) 576 (16) 576 (16)
FF1517 40 x 40 mm 768 (20) 768 (24)
XMP070 (v1.0)
Notes: 1. EasyPath FPGAs provide a conversion-free and low-risk path for volume production.
2. Each slice comprises two 4-input logic function generators (LUTs), two storage elements, wide-function multiplexers, and carry logic.
5. All Virtex-4 LX and Virtex-4 SX devices available in the same package are footprint-compatible.
6. All products are available Pb-free and RoHS-Compliant.
4. Supported I/O standards include: LDT-25, LVDS-25, LVDSEXT-25, BLVDS-25, ULVDS-25, LVPECL-25, LVCMOS25, LVCMOS18, LVCMOS15, LVCMOS33, LVTTL, PCI-X, PCI133, PCI66, GTL, GTL+, HSTL I (1.5V, 1.8V), HSTL II (1.5V, 1.8V), HSTL III (1.5V, 1.8V), HSTL IV (1.5V, 1.8V),
SSTL2 I, SSTL2 II, SSTL18 I, and SSTL18 II.
SFA Packages (SF): Flip-chip, fine-pitch BGA (0.8 mm ball spacing)
11
EXTENDED SPARTAN
-3A FPGAS
XC3S50A/AN XC3S200A/AN XC3S400A/AN XC3S700A/AN XC3S1400A/AN XC3SD1800A XC3SD3400A
50K 200K 400K 700K 1400K 1800K 3400K
704 1,792 3,584 5,888 11,264 16,640 23,872
1,584 4,032 8,064 13,248 25,344 37,440 53,712
1,408 3,584 7,168 11,776 22,528 33,280 47,744
11 28 56 92 176 260 373
3 16 20 20 32 84 126
54 288 360 360 576 1,512 2,268
Yes Yes Yes Yes Yes No No
- / 627 - / 3,054 - / 2,380 - / 5,779 - / 12,251 - -
Clock Resources
2 4 4 8 8 8 8
144 / 144 248 / 195 311 372 502 519 469
64 / 64 112 / 90 142 165 227 227 213
3 16 20 20 32 84
(4)
126
(4)
Yes Yes Yes Yes Yes Yes Yes
-4, -5 -4, -5 -4, -5 -4, -5 -4, -5 -4, -5 -4, -5
-4 -4 -4 -4 -4 -4 -4
Configuration
0.4 1.2 1.9 2.7 4.8 8.2 11.7
Package
(6)
Footprint Size
XILINX EXTENDED SPARTAN
-3A FPGAS
Extended Spartan-3A FamiIy
Optimized for Lowest Total Cost
Part Number
System Gates
(1)
Slices
(2)
Logic Cells
CLB Flip-Flops
Industrial
Single Chip Option
User Flash (Kb)
(3)
Digital Clock Managers (DCMs)
I/O Standards Supported
Logic Resources
Memory Resources
Non-Volatile Capability
I/O Resources
Embedded Hard IP Resources
Speed Grades
Maximum User I/Os
VQFP Packages (VQ): Very thin QFP (0.5 mm lead spacing)
Multipliers/DSP48A Blocks
LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVCMOS12, HSTL15 Class I, HSTL15 Class III, HSTL18 Class I, HSTL18 Class II, HSTL18 Class III, PCI 3.3V 32/64bit 33MHz, PCI 3.3V 64bit/66MHz,
SSTL3 Class I, SSTL3 Class II, SSTL2 Class I, SSTL2 Class II, SSTL18 Class I, SSTL18 Class II, Bus LVDS, LVDS25 & 33, LVPECL25 & 33, Mini-LVDS25 & 33, RSDS25 & 33, TMDS33, and PPDS25 & 33
Device DNA Security
Commercial
VQ100 16 x 16 mm 68 / -
(7)
68 / -
(7)
TQ144 22 x 22 mm 108 / 108
FT256 17 x 17 mm 144 / 144 195 / 195 195 / 195 161 / -
(7)
161 / -
(7)
CS484 19 x 19 mm 309
(5)
309
(5)
FG320 19 x 19 mm 248 / -
(7)
251 / -
(7)
FG400 21 x 21 mm 311 / 311 311 / -
(7)
FG484 23 x 23 mm 372 / 372 375 / 375
FG676 27 x 27 mm 502 / 502 519 469
XMP072 (v1.1)
Notes: 1. System gates include 20%-30% of CLBs used as RAMs.
3. Spartan-3AN User Flash is the remaining storage capacity in the on-chip flash after storing the configuration bitstream.
4. Integrated in the DSP48A slices (Advanced Multiply Accumulate element).
5. The low-power option is exclusively available in CS(G)484 package and Industrial temperature range.
6. All products are Pb-free and RoHS-Compliant; check data sheet for Pb package availability.
7. Package is not available in nonvolatile Spartan-3AN family.
Chip Scale Packages (CS): Wire-bond, chip-scale, BGA (0.8 mm ball spacing)
BGA Packages (FG): Wire-bond, fine-pitch, BGA (1.0 mm ball spacing)
TQFP Packages (TQ): Thin QFP (0.5 mm lead spacing)
BGA Packages (FT): Wire-bond, fine-pitch, thin BGA (1.0 mm ball spacing)
12
SPARTAN
-3A, 3E FPGAS
XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E
50K 200K 400K 1,000K 1,500K 2,000K 4,000K 5,000K 100K 250K 500K 1,200K 1,600K
768 1,920 3,584 7,680 13,312 20,480 27,648 33,280 960 2,448 4,656 8,672 14,752
1,728 4,320 8,064 17,280 29,952 46,080 62,208 74,880 2,160 5,508 10,476 19,512 33,192
1,536 3,840 7,168 15,360 26,624 40,960 55,296 66,560 1,920 4,896 9,312 17,344 29,504
12 30 56 120 208 320 432 520 15 38 73 136 231
4 12 16 24 32 40 96 104 4 12 20 28 36
72 216 288 432 576 720 1,728 1,872 72 216 360 504 648
Clock Resources
2 4 4 4 4 4 4 4 2 4 4 8 8
124 173 264 391 487 565 633 633 108 172 232 304 376
56 76 116 175 221 270 300 300 40 68 92 124 156
Embedded Hard IP Resources 4 12 16 24 32 40 96 104 4 12 20 28 36
-4, -5 -4, -5 -4, -5 -4, -5 -4, -5 -4, -5 -4, -5 -4, -5 -4, -5 -4, -5 -4, -5 -4, -5 -4, -5
-4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4
Configuration
0.4 1 1.7 3.2 5.2 7.7 11.3 13.3 0.6 1.4 2.3 3.8 6
Package Footprint Size
VQ100 16 x 16 mm 63 63 66 66 66
XILINX SPARTAN
-3, 3E FPGAS
System Gates
(1)
Slices
(2)
Logic Cells
Part Number
Spartan-3E FPGAs
Logic Optimized
Speed Grades
I/O Resources
Memory Resources
Logic Resources
Dedicated Multipliers
Commercial
Industrial
CLB Flip-Flops
Spartan-3 FPGAs
Optimized for High-Density and High I/O Designs
LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVCMOS12, GTL, GTL+, HSTL15 Class I, HSTL15 Class III, HSTL18 Class I,
HSTL18 Class II, HSTL18 Class III, PCI 3.3V 32/64bit 33MHz, SSTL2 Class I, SSTL2 Class II, SSTL18 Class I, Bus LVDS, LDT (ULVDS),
LVDS_ext, LVDS25 & 33, LVPECL25, and RSDS25
LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVCMOS12, HSTL18
Class I, HSTL18 Class III, PCI 3.3V 32/64bit 33MHz, PCI 3.3V 64bit/66MHz, SSTL2
Class I, SSTL18 Class I, Bus LVDS, LVDS25, LVPECL25, Mini-LVDS25, RSDS25
Maximum User I/Os
VQFP Packages (VQ): Very thin QFP (0.5 mm lead spacing)
VQ100 16 x 16 mm 63 63 66 66 66
CP132 8 x 8 mm 89 83 92 92
TQ144 22 x 22 mm 97 97 97 108 108
PQ208 30.6 x 30.6 mm 124 141 141 158 158
FT256 17 x 17 mm 173 173 173 172 190 190
FG320 19 x 19 mm 221 221 221 232 250 250
FG400 21 x 21 mm 304 304
FG456 23 x 23 mm 264 333 333 333
FG484 23 x 23 mm 376
FG676 27 x 27 mm 391 487 489 489 489
FG900 31 x 31 mm 565 633 633
XMP072 (v1.1)
3. All products are available Pb-free and RoHS-Compliant.
4. Available only in VQG100 package. VQG100 and VQ100 have identical pinouts.
PQFP Packages (PQ): Wire-bond, plastic, QFP (0.5 mm lead spacing)
FGA Packages (FT): Wire-bond, fine-pitch, thin BGA (1.0 mm ball spacing)
FGA Packages (FG): Wire-bond, fine-pitch, BGA (1.0 mm ball spacing)
Chip Scale Packages (CP): Wire-bond, chip-scale, BGA (0.5 mm ball spacing)
13
XI LI NX CPLD PRODUCTS
XILINX CPLD PRODUCTS
CooIRunner"-II FamiIy
XC2C32A XC2C64A XC2C128 XC2C256 XC2C384 XC2C512
750 1,500 3,000 6,000 9,000 12,000
32 64 128 256 384 512
56 56 56 56 56 56
3 3 3 3 3 3
16 16 16 16 16 16
Part Number
System Gates
Macrocells
Logic Resources
Product Terms Per Macrocell
Global Clocks
Product Term Clocks Per Function Block
Clock Resources
33 64 100 184 240 270
1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3
1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3
3.8 4.6 5.7 5.7 7.1 7.1
-4, -6 -5, -7 -6, -7 -6, -7 -7, -10 -7, -10
-6 -7 -7 -7 -10 -7
(1)
, -10
Package
(2)
Area
(3)
Maximum User I/Os
QFN Packages (QFG): Quad, flat, no-lead (0.5 mm lead spacing)
Industrial Speed Grades (Fastest to Slowest)
Speed Grades
Commercial Speed Grades (Fastest to Slowest)
Maximum I/O
I/O Resources
Input Voltage Compatible
Output Voltage Compatible
Min. Pin-to-Pin Logic Delay (ns)
QF32
(4)
5 x 5 mm 21
QF48
(4)
7 x 7 mm 37
VQ44 12 x 12 mm 33 33
VQ100 16 x 16 mm 64 80 80
CP56 6 x 6 mm 33 45
CP132 8 x 8 mm 100 106
g ( ) ( p g)
VQFP Packages (VQ): Very thin QFP (VQ44: 0.8 mm lead spacing, VQ100: 0.5 mm lead spacing)
TQ100 16 x 16 mm
TQ144 22 x 22 mm 100 118 118
PQ208 30.6 x 30.6 mm 173 173 173
FT256 17 x 17 mm 184 212 212
FBGA Packages (FG): Wire-bond, fine-line, BGA (1.0 mm ball spacing)
FG324 23 x 23 mm 240 270
XMP073 (v1.0)
Notes: 1. -7 speed grade is only available in FT(G)256 package.
2. All packages are available in Pb-Free and RoHS6 compliant versions.
3. Area dimensions for lead-frame product are inclusive of the leads.
4. Only available in RoHS6 compliant and Halogen-free packages.
FBGA Packages (FG): Wire bond, fine line, BGA (1.0 mm ball spacing)
14
XI LI NX CPLD PRODUCTS
XC9536XL XC9572XL XC95144XL XC95288XL
800 1,600 3,200 6,400
36 72 144 288
90 90 90 90
3 3 3 3
18 18 18 18
36 72 117 192
2.5/3.3/5 2.5/3.3/5 2.5/3.3/5 2.5/3.3/5
2.5/3.3 2.5/3.3 2.5/3.3 2.5/3.3
5 5 5 6
-5, -7, -10 -5, -7, -10 -5, -7, -10 -6, -7, -10
-7, -10 -7, -10 -7, -10 -7, -10
Package
(1)
Area
(2)
VQ44 12 x 12 mm 34 34
VQ64 12 x 12 mm 36 52
PC44 17.5 x 17.5 mm 34 34
CS48 7 x 7 mm 36 38
CS144 12 x 12 mm 117
CS280 16 16 192
XILINX CPLD PRODUCTS
System Gates
Macrocells
Global Clocks
XC9500XL FamiIy
Part Number
Speed Grades
VQFP Packages (VQ): Very thin QFP (VQ44: 0.8 mm lead spacing, VQ64: 0.5 mm lead spacing)
PLCC Packages (PC): Wire-bond, plastic, chip carrier (1.27 mm lead spacing)
Min. Pin-to-Pin Logic Delay (ns)
Commercial Speed Grades (Fastest to Slowest)
Industrial Speed Grades (Fastest to Slowest)
Maximum User I/Os
I/O Resources
Clock Resources
Logic Resources
Maximum I/O
Input Voltage Compatible
Output Voltage Compatible
CS280 16 x 16 mm 192
TQ100 16 x 16 mm 72 81
TQ144 22 x 22 mm 117 117
PQ208 30.6 x 30.6 mm 168
FG256 17 x 17 mm 192
BG256 27 x 27 mm 192
XMP073 (v1.0)
Notes: 1. All packages are available in Pb-Free and RoHS6 compliant versions.
2. Area dimensions for lead-frame product are inclusive of the leads.
FBGA Packages (BG): Wire-bond, fine-line, BGA (1.0 mm ball spacing)
15
XI LI NX CONFIGURATION SOLUTIONS
XiIinx Configuration Memory Cross-Reference
Part Number XCF01S XCF02S XCF04S XCF08P XCF16P XCF32P XCF128X
XC6VLX75T XCF32P XC6SLX4 XCF04S XC3S50A XCF01S Density 1 Mb 2 Mb 4 Mb 8 Mb 16 Mb 32 Mb 128 Mb
XC6VLX130T XCF128X XC6SLX9 XCF04S XC3S200A XCF02S JTAG Programmable Yes Yes Yes Yes Yes Yes Indirect
XC6VLX195T XCF128X XC6SLX16 XCF04S XC3S400A XCF02S Serial Configuration Yes Yes Yes Yes Yes Yes No
XC6VLX240T XCF128X XC6SLX25 XCF08P XC3S700A XCF04S SelectMAP Configuration - - - Yes Yes Yes Yes
XC6VLX365T XCF128X XC6SLX25T XCF08P XC3S1400A XCF08P Compression - - - Yes Yes Yes No
XC6VLX760 (2)XCF128X + CPLD XC6SLX45 XCF16P Design Rev - - - Yes Yes Yes Yes
XC6VLX550T (2)XCF128X + CPLD XC6SLX45T XCF16P XC3SD1800A XCF08P VCC (V) 3.3 3.3 3.3 1.8 1.8 1.8 1.8
XC6VSX315T XCF128X XC6SLX75 XCF32P XC3SD3400A XCF16P VCCO (V) 1.8-3.3 1.8-3.3 1.8-3.3 1.8-3.3 1.8-3.3 1.8-3.3 2.5-3.3
XC6VSX475T (2)XCF128X + CPLD XC6SLX75T XCF32P VCCJ (V) 2.5-3.3 2.5-3.3 2.5-3.3 2.5-3.3 2.5-3.3 2.5-3.3 N/A
XC6VHX250T XCF128X XC6SLX100 XCF32P XC3S100E XCF01S Clock (MHz) 33 33 33 40 40 40 50
XC6VHX255T XCF128X XC6SLX100T XCF32P XC3S250E XCF02S Standard Package VO20 VO20 VO20 FS48 FS48 FS48 FT64
XC6VHX380T XCF128X XC6SLX150 XCF32P
(1)
XC3S500E XCF04S VOG20 VOG20 VOG20 FSG48 FSG48 FSG48 FTG64
XC6VHX565T (2)XCF128X + CPLD XC6SLX150T XCF32P
(1)
XC3S1200E XCF04S - - - VOG48 VOG48 VOG48 -
XC3S1600E XCF08P
XC5VLX30 XCF08P XC4VLX15 XCF08P Notes:
XC5VLX50 XCF16P XC4VLX25 XCF08P XC3S50 XCF01S Virtex-5 or Virtex-6 FPGA JTAG port.
XC5VLX85 XCF32P XC4VLX40 XCF16P XC3S200 XCF01S
XC5VLX110 XCF32P XC4VLX60 XCF32P XC3S400 XCF02S refer to UG161, Platform Flash User Guide .
XC5VLX155 XCF128X XC4VLX80 XCF32P XC3S1000 XCF04S
XC5VLX220 XCF128X XC4VLX100 XCF32P XC3S1500 XCF08P
XC5VLX330 XCF128X XC4VLX160 XCF32P + XCF08P XC3S2000 XCF08P
2. For more information regarding design-in considerations of Platform Flash PROMs,
Spartan-3A FPGAs
Spartan-3E FPGAs
Spartan-3 FPGAs
Spartan-3A DSP FPGAs
1. The iMPACT software tool supports XCF128X JTAG programming indirectly via the
XILINX CONFIGURATION SOLUTIONS
Virtex-6 FPGAs
PIatform FIash FamiIy Packages and Features
Pb-Free Package
Virtex-5 FPGAs
PIatform FIash/XL FIash Memory
Virtex-4 FPGAs
Spartan-6 FPGAs
PIatform FIash/XL FIash Memory PIatform FIash/XL FIash Memory
XC5VLX330 XCF128X XC4VLX160 XCF32P + XCF08P XC3S2000 XCF08P
XC5VLX20T XCF08P XC4VLX200 XCF32P + XCF32P XC3S4000 XCF16P
XC5VLX30T XCF16P XC4VFX12 XCF08P XC3S5000 XCF16P
XC5VLX50T XCF16P XC4VFX20 XCF08P
XC5VLX155T XCF128X XC4VFX100 XCF32P
XC5VLX220T XCF128X XC4VFX140 XCF32P + XCF16P
XC5VLX330T XCF128X XC4VSX25 XCF16P
XC5VSX35T XCF16P XC4VSX35 XCF16P
XC5VSX50T XCF32P XC4VSX55 XCF32P
XC5VSX95T XCF128X or XCF32P
(1)
XC5VSX240T XCF128X Notes: 1. Assumes typical compression benchmarks;
XC5VFX30T XCF16P compression should be confirmed using ISE tools
XC5VFX70T XCF32P
XC5VFX100T XCF128X
XC5VFX130T XCF128X
XC5VFX200T XCF128X
XC5VTX150T XCF128X
XC5VTX240T XCF128X XMP074 (v1.0)
16
XI LI NX CONFIGURATION SOLUTIONS
Configuration Hardware Products Key Configuration SoIutions AppIication Notes
XiIinx DownIoad CabIe Chart Configuration AppIication Notes for In-System Programming and Remote Update
Platform Cable USB II Xilinx In-System Programtming Using an Embedded Microcontroller, a microprocessor solution -XAPP058
HW-USB-II-G Embedded In-System Programming, JTAG ACE Player Solution - XAPP424
Connection to PC USB 1.1 (Basic Speed) or USB 2.0 (High-Speed)
Multiple-Boot with Platform Flash PROMs and Spartan-3E FPGAs - XAPP483
I/O Voltage Support 1.5V, 1.8V, 2.5V, 3.3V, and 5V
A CPLD-Based Configuration and Revision Manager for Xilinx Platform Flash PROMs and FPGAs - XAPP693
Multiple Cable Management Yes (Users can easily name and control individual cables through Xilinx iMPACT software)
Updating a Platform Flash PROM Design Revision In-System Using SVF - XAPP972
Input Power Requirements Bus Powered (+5VDC)
Low-Profile In-System Programming Using XCF32P Platform Flash PROMs - XAPP975
Configuration Modes
JTAG (IEEE Std 1149.1), Slave Serial, IEEE Std 1532, Direct SPI with automatic PROG_B control,
Indirect programming of SPI and parallel flash memory devices
(1)
MultiBoot with Virtex-5 FPGAs and Platform Flash XL - XAPP1100
Stand-Alone Programming Support Download cable only
Configuration AppIication Notes for Data Storage
OS Support
Windows XP Professional (32 and 64 bit)
Windows Vista (32 and 64 bit)
Xilinx Device Support All Xilinx FPGAs, CPLDs, Platform Flash PROMs, XC18V00 PROMs, and System ACE Tool
Third-Party Flash Memory Support
Direct programming of specific SPI Flash memory devices
(1)
Indirect programming of specific SPI and parallel flash memory devices
(1)
Device and Board Interface
Ribbon cable or flying wires
(shipped with both)
RoHS Compliant Yes
Dynamic Bus Mode Reconfiguration of PCI-X and PCI Designs - XAPP938
Miscellaneous
Improved target interface protection
FPGA-based for feature growth
Target system MUX control (PGND) for dynamic JTAG bus sharing
Maximum Target Clock Speed 12 MHz
Design Guides for Configuration
Platform Flash XL User Guide - UG438
Platform Flash PROM User Guide - UG161
Bulletproof Configuration Best Practices Guide for Spartan-3A FPGAs - XAPP986
g g
Data storage with Platform Flash XCF02S/XCF04S PROMs - XAPP544
XILINX CONFIGURATION SOLUTIONS
Configuration AppIication Note for PCI/PCI-X
Configuration AppIication Notes for 3rd Party FIash Memory
A best-practices example using BPI flash for Virtex-5 FPGAs configuration - XAPP973
A best-practices example using SPI flash for Spartan-3A FPGAs configuration - XAPP974
Part Number
PIatform CabIe USB II - State-of-the-art Xilinx cable with industry-leading performance recommended for new designs. For in-system programming
using Xilinx iMPACT programming software connected via a simple four-wire header to the FPGA, PROM, or CPLD device on target board.
Configuration AppIication Note for Code Storage
MicroBlaze Processor Platform Flash/PROM Boot Loader and User Data Storage - XAPP482
Notes: 1. See XAPP951 for a list of SPI devices that Xilinx supports via direct programming and XAPP974 for a
list of SPI devices that Xilinx supports via indirect programming System ACE TechnoIogy
For multiple FPGA configuration and for designs utilizing system-level features, use the System ACE solution.
System ACE TooI CF
Memory Density Up to 8 Gb
Number of Components 2
Minimum Board Specifications 25 cm
Compression No
FPGA Configuration Mode JTAG
Multiple Designs Unlimited
Software Storage Yes
Removable Yes
IRL Hooks Yes
Maximum Configuration Speed 30 Mb/s
Nonvolatile Media CompactFlash
Pb-free solutions are available. For more information about Pb-free solutions, visit www.xilinx.com/pbfree.
XMP074 (v1.0)
A best practices example using SPI flash for Spartan 3A FPGAs configuration XAPP974
**To download these application notes, visit the 'Documentation' section at
www.xilinx.com/products/design_resources/config_sol/
17
XI LI NX DESIGN TOOLS I SE
DESIGN SUITE
ISE Design
Suite Device
Support
ISE WebPACK TooI ISE Design Suite
Logic Edition
Embedded Edition
DSP Edition
ISE Design Suite Comparison TabIe ISE
WebPACK
TooI
Logic
Edition
Embedded
Edition
DSP
Edition
System
Edition
XILINX DESIGN TOOLS - ISE
DESIGN SUITE 13
DSP Edition
System Edition
(Device Limited)
Virtex-4 FPGAs Virtex-4 FPGAs SE Foundation Tools with SE Simulator (Sim) \ \ \ \ \
LX: XC4VLX15, XC4VLX25 LX: All PlanAhead Design Analysis Tool \ \ \ \ \
SX: XC4VSX25 SX: All ChipScope Pro Logic Analyzer \ \ \ \
FX: XC4VFX12 FX: All ChipScope Pro Serial /O Toolkit \ \ \ \
Embedded Development Kit (EDK) \ \
Virtex-5 FPGAs Virtex-5 FPGAs Software Development Kit (SDK) \ \
LX: XC5VLX30, XC5VLX50 LX: All System Generator for DSP \ \ LX: XC5VLX30, XC5VLX50 LX: All System Generator for DSP \ \
LXT: XC5VLX20T - XC5VLX50T LXT: All
FXT: XC5VFX30T SXT: All Targeted Stand-AIone Products
FXT: All Software Development Kit (SDK)
Virtex-6 FPGAs Virtex-6 FPGAs ChipScope Pro and ChipScope Pro Serial /O Toolkit
XCLX75T All Embedded Development Kit (EDK)
System Generator for DSP
Virtex-7 FPGAs
None
Virtex-7 FPGAs
All
Kintex FPGAs
Kintex-7 FPGAs
XC7K70T XC7K160T
Kintex-7 FPGAs
All
Virtex FPGAs
Usage
Embedded software developers who do not require SE tools
Lab Environments
Spartan FPGA Design and SE WebPACK Tool Users
XC7K70T, XC7K160T All
Spartan-3 FPGAs Spartan-3 FPGAs: All
XC3S50 - XC3S1500
Spartan-3A FPGAs
All
Spartan-3AN FPGAs
All
Spartan-3A DSP FPGAs
XC3SD1800A
Spartan-3E FPGAs
All
Spartan-6 FPGAs
Spartan-3A FPGAs: All
Spartan-3AN FPGAs: All
Spartan-3 DSP FPGAs: All
Spartan-3E FPGAs: All
Spartan-6 FPGAs: All
XA (Xilinx Automotive)
s
i
o
n
a
l

3
2
/
6
4
-
B
i
t
*
o
n
a
l

3
2
/
6
4
-
B
i
t
*
0
8
L
i
n
u
x

4

W
S
3
2
/
6
4
-
b
i
t
L
i
n
u
x

5

W
S
3
2
/
6
4
-
b
i
t
r
i
s
e

1
1

3
2
/
6
4
-
b
i
t
Spartan FPGAs
Spartan 6 FPGAs
XC6SLX4 - XC6SLX75T
XA (Xilinx Automotive) Spartan-3
FPGAs
All
XA (Xilinx Automotive) Spartan-6
FPGAs
All ISE Design Suite
Operating System Support
W
i
n
d
o
w
s

X
P

P
r
o
f
e
s
s
W
i
n
d
o
w
s

7

P
r
o
f
e
s
s
i
o
W
i
n
d
o
w
s

S
e
r
v
e
r

2
0
0
R
e
d

H
a
t

E
n
t
e
r
p
r
i
s
e

L
R
e
d

H
a
t

E
n
t
e
r
p
r
i
s
e

L
S
U
S
E

L
i
n
u
x

E
n
t
e
r
p
r
SE Design Entry and mplementation Tools \ \ \ \ \ \
SE Simulator (Sim) \ \ \ \ \ \
CoolRunner XPLA3
CoolRunner-
SE WebPACK \ \ \ \ \ \
ChipScope Pro and ChipScope Pro Serial /O Toolkit \ \ \ \ \ \
Embedded Development Kit (EDK) and Platform Studio \ \ \ \ \ \
XC9500 Series Software Development Kit (SDK) \ \ \ \ \ \
System Generator for DSP \ \ \ \ \ \
XMP075 (v2.0)
*US and Japanese: Full Support. Chinese: Limited Support.
CoolRunner-
CoolRunner-A
CPLDs
All
All (Except 9500XV Family)
Note: Windows Vista Operating Systems are not supported in 13.1
XMP075 (v1.1) mportant: Verify all data in this document with the device data sheets found at www.xilinx.com 17
18
XI LI NX AEROSPACE & DEFENSE SOLUTIONS
XQ6VLX130T XQ6VLX240T XQ6VLX550T XQ6VSX315T XQ6VSX475T
Virtex-6Q FPGAs
Defense-Grade FPGAs
Part Number
XILINX AEROSPACE & DEFENSE SOLUTIONS
Q Q Q Q Q
Logic Resources 128,000 241,000 550,000 315,000 476,000
1,740 3,650 6,200 5,090 7,640
264 416 632 704 1064
9,504 14,976 22,752 25,344 38,304
Clock Resources 10 12 18 12 18
I/O Resources 600 720 840 720 840
480 768 864 1,344 2,016
2 2 2 2 2
DSP48E1 Slices
Interface Blocks for PCI Express
Memory Resources
Mixed Mode Clock Manager (MMCM)
Logic Cells
Embedded Hard IP
Resources
4 4 4 4 4
20 24 36 24 36
-1 -1 - -1 -
-1, -2
(2)
-1, -2
(2)
-1
(2,3)
-1, -2
(2)
-1
(2,3)
Package Area
RF784
(1)
29 X 29 mm 400 (12) 400 (12)
RF1156 35 x 35 mm 600 (20) 600 (20) 600 (20) 600 (20)
FFG1156
(4)
35 x 35 mm 600 (20) 600 (20) 600 (20) 600 (20)
RF1759 42 5 x 42 5 mm 720 (24) 840 (36) 720 (24) 840 (36)
Maximum User I/O: SelectIO Interface Pins (GTX Serial Transceivers)
Miscellaneous
Speed Grades: Military (M: -55C - 125C)
Speed Grades: Industrial (I: -40C - 100C)
GTX Low-Power Transceivers
Resources
RF1759 42.5 x 42.5 mm 720 (24) 840 (36) 720 (24) 840 (36)
XMP076 (v2.2)
Notes: 1. RF is ruggedized, leaded flip chip package.
2. -L1 speed grade is under investiation for I-temp, please contact A&D marketing for more information.
3. -2 speed grade is under investigation for LX550T I-temp and SX475T I-temp, please contact A&D marketing for more information.
4. No M-temp for FFG.
19
XQ6SLX75 XQ6SLX150 XQ6SLX75T XQ6SLX150T
Part Number
Spartan-6Q FPGAs
Defense-Grade FPGAs
Q Q Q Q
75,000 147,000 75,000 147,000
93,000 184,000 93,000 184,000
692 1,355 692 1,355
172 268 172 268
3,096 4,824 3,096 4,824
Clock Resources 6 6 6 6
132 180 132 180
- - 1 1
Memory Resources
DSP48A1 Slices
Logic Cells
CLB Flip-Flops
Logic Resources
2 2 4 4
- - 8 8
- -2 -2 -2
-L1, -2 -L1, -2 -2, -3 -2, -3
Package Area
CS(G)484
(1,2,3)
19 x 19 mm 328 338 292 (4) 296 (4)
FG484
(2,3)
23 x 23 mm 270 338 268 (4) 296 (4)
FG(G)676
(1)
27 x 27 mm 348 (8) 396 (8)
XMP076 (v2 2)
Maximum SelectIO Interface Pins (GTP Serial Transceivers)
Miscellaneous
Speed Grades: Extended (Q: -40C - 125C)
Speed Grades: Industrial (I: -40C - 100C)
XMP076 (v2.2)
Notes: 1. Pb-free (additional G) not available for Spartan-6 Q-temp devices.
2. Devices in the CS(G)484 and FG484 support two memory controllers.
3. Due to the GTP transceivers in the LXT devices, pinouts for the LX and LXT devices are not compatible.
20
XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VLX200T
4 800 12 960 17 280 17 280 24 320 34 560 51 840 8 160 14 720 37 440 11 200 16 000 20 480 30 720
Defense-Grade FPGAs
Virtex-5Q FPGAs
Part Number
Slices
(2)
4,800 12,960 17,280 17,280 24,320 34,560 51,840 8,160 14,720 37,440 11,200 16,000 20,480 30,720
30,720 82,944 110,592 110,592 155,648 221,184 331,776 52,224 94,208 239,616 71,680 102,400 131,072 196,608
19,200 51,840 69,120 69,120 97,280 138,240 207,360 32,640 58,880 149,670 44,880 64,000 81,920 122,880
320 840 1,120 1,120 1,640 2,280 3,420 780 1,520 4,200 820 1,240 1,580 2,280
36 96 128 148 212 212 324 132 244 516 148 228 298 456
1,296 3,456 4,608 5,328 7,632 7,632 11,664 4,752 8,784 18,576 5,328 8,208 10,728 16,416
Clock Resources 4 12 12 12 12 12 12 12 12 12 12 12 12 12
2 6 6 6 6 6 6 6 6 6 6 6 6 6
I/O R
Phase-Locked Loop/PMCD
Digital Clock Manager (DCM)
Logic Resources
Memory
Resources
Slices
(2)
Logic Cells
(3)
CLB Flip-Flops
360 560 800 680 680 680 960 480 640 960 640 680 840 960
180 280 400 340 340 340 480 240 320 480 320 340 420 480
32 48 64 64 128 128 192 288 640 1,056 128 256 320 384
- - - - - - - - - - 1 2 2 2
1 - - 1 1 1 1 1 1 1 3 3 3 4
4 - - 4 4 4 4 4 4 4 4 4 6 8
8 - - 16 16 16 24 12 16 24 - - - -
- - - - - - - - - - 16 16 20 24
Configuration 9 4 21 9 29 1 31 2 43 1 55 2 82 7 20 35 8 79 7 27 1 39 4 49 3 70 9
I/O Resources
Embedded Hard
IP Resources
DSP48E Slices
Configuration 9.4 21.9 29.1 31.2 43.1 55.2 82.7 20 35.8 79.7 27.1 39.4 49.3 70.9
-1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1 -1 -1, -2 -1 -1 -1, -2 -1, -2 -1, -2 -1
I I I I I I I I I I I, M
7
I, M
7
I I
Package Area
EF676 27 x 27 mm 440 440
EF1153 35 x 35 mm 800
FF323 19 x 19 mm 172 (4)
EF665 27 x 27 mm 360 (8) 360 (8)
EF1136 35 x 35 mm 640 (16) 640 (16) 640 (16) 640 (16) 640 (16)
(4)
Manufacturing Grades
Miscellaneous
Speed Grades
( ) ( ) ( ) ( ) ( )
EF1738 42.5 x 42.5 mm 680 (16) 960 (24) 680 (16) 840 (20)
FF1738 42.5 x 42.5 mm 960 (24) 960 (24)
XMP076 (v2.2)
Notes: 1. A single Virtex-5Q FPGA CLB comprises two slices, with each containing four 6-input LUTs and four flip-flops (twice the number found in a Virtex-4 FPGA slice), for a total of eight 6-LUTs and eight flip-flops per CLB.
2. Virtex-5 FPGA logic cell ratings reflect the increased logic capacity offered by the new 6-input LUT architecture.
5. One system monitor block included in all devices.
4. I/O standards supported: HT, LVDS, LVDSEXT, RSDS, BLVDS, ULVDS, LVPECL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVTTL, PCI33, PCI66, PCI-X, GTL, GTL+, HSTL I (1.2V,1.5V,1.8V), HSTL II (1.5V,1.8V), HSTL III (1.5V,1.8V), HSTL IV (1.5V,1.8V), SSTL2 I, SSTL2 II,
SSTL18 I, and SSTL18 II.
6. Available I/O for each device-package combination: number of SelectIO interface pins (number of RocketIO transceivers).
7. M-grade available only in -1 speed grade and EF1136 package.
Grade
V Xilinx V-Grade Flow
(1)
Military Ceramic Tj = -55C to +125C
H
B SMD Radiation Tolerant and Non-RT SMD Military Ceramic Tj = -55C to +125C
http://www.xilinx.com/products/milaero/rpt003.pdf
Flip-Chip Radiation Tolerant Ceramic
Description Temperature
Tj = -55C to +125C
T 55C 125C N
M Military Ceramic or Plastic Tj = -55C to +125C
I
Notes: 1. Per ADQ0007
Military Plastic
Industrial Plastic
Tj = -55C to +125C
Tj = -40C to +100C
21
XQ4VLX25 XQ4VLX40 XQ4VLX60 XQ4VLX100 XQ4VLX160 XQ4VSX55 XQ4VFX60 XQ4VFX100 XQ2VP40 XQ2VP70 XQ2V1000 XQ2V3000 XQ2V6000
1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.5V 1.5V 1.5V 1.5V 1.5V
10,752 18,432 26,624 49,152 67,584 24,576 25,280 42,176 19.392 33,088 5,120 14,336 33,792
24,192 41,472 59.904 110,592 152,064 55,296 56,880 94,896 44,632 74,448 11,520 32,256 76,032
21,504 36,864 53,248 98,304 135,168 49,152 50,560 84,352 38,784 66,176 10,240 28,672 67,584
168 288 416 768 1,056 384 395 659 606 1,034 160 448 1,056
72 96 160 240 288 320 232 376 192 328 40 96 144
1,296 1,728 2,880 4,320 5,184 5,760 4,176 6,768 3,456 5,904 720 1,728 2,592
Clock Resources
8 8 8 12 12 8 12 12 8 8 8 12 12
448 640 640 960 960 640 576 768 804 996 432 720 1,104
224 320 320 480 480 320 228 384 396 492 216 360 552
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
48 64 64 96 96 512 128 160 - - - - -
- - - - - - - - 192 328 40 96 144
- - - - - - 16 20 8 or 12 20 - - -
- - - - - - 2 2 2 2 - - -
-10 -10 -10 -10 -10 -10 -10 -10 -5 -5 -4 -4 -4
4.8 12.3 17.7 30.7 40.3 22.7 21 33 15.5 25.6 4.1 10.5 21.9
M I, M M I XMP076 (v2.1) M I, M I N N N M, N, B M
SF363, FF668 FF668 F668, FF1148, EF6 FF1148 FF1148 FF1148 EF672, FFG1152* FF1152 FF1152, FG676 FF1704 FG456, BG575 CG717, BG728 CF1144
XMP076 (v2.2)
Packages
Logic Resources
Memory Resources
I/O Resources
Slices
(1)
Digitally Controlled Impedance
Logic Cells
CLB Flip-Flops
Miscellaneous
Speed Grades
Embedded Hard IP
Resources
DSP Slices
18 x 18 Multipliers
RocketIO Transceivers
Defense-Grade FPGAs
Virtex-II Pro XQ FPGAs Virtex-II XQ FPGAs Virtex-4Q FPGAs
Core Voltage
Part Number
( )
Notes: 1. Each slice comprises two 4-input logic function generators (LUTs), two storage elements, wide-function multiplexers, and carry logic.
Grade
V
H
B
N
M
I
Notes: 1. Per ADQ0007.
Military Plastic
Military Ceramic or Plastic
Industrial Plastic
Description
Temperature
Tj = -40C to +100C
Tj = -55C to +125C
Tj = -55C to +125C
Tj = -55C to +125C
Tj = -55C to +125C
Tj = -55C to +125C
Device Xilinx V-Grade Flow
(1)
Military Ceramic
Device Flip-Chip Radiation Tolerant Ceramic
SMD Radiation Tolerant and Non-RT SMD Military Ceram
22
Virtex-5QV FPGAs Virtex-II XQR FPGAs
XQR5VFX130 XQR4VLX200 XQR4VSX55 XQR4VFX60 XQR4VFX140 XQR2V3000 XQVR300 XQVR600
1.0V 1.2V 1.2V 1.2V 1.2V 1.5V 2.5V 2.5V
20,480 89,088 24,576 25,280 63,168 14,336 3,072 6,912
130,000 200,448 55,296 56,880 142,128 32,256 6,912 15,552
81920 178,176 49,152 50,560 126,336 28,672 6,144 13,824
1580 1,392 384 395 987 448 1,711 3,523
298 - - - - - - -
- 336 320 232 552 96 - -
- - - - - - 16 24
10,728 6,048 5,760 4,176 9,936 1,728 64 96
12 12 8 12 20 12 -
24 - - - - - - -
- - - - - 4 4
836 960 640 576 896 720 316 316
414 480 320 288 448 360 -
Yes Yes Yes Yes Yes Yes - -
320 - - - - - - -
- 96 512 128 192 - - -
- - - - - 96 - -
6 - - 4 4 - - -
- - - 2 2 - - -
18 - - - - - - -
-1 -10 -10 -10 -10 -4 -4 -4
49.2 51.4 22.7 21.0 47.9 10.5 1.7 3.5
Block RAM/FIFO (18 Kb each)
Logic Resources
Digitally Controlled Impedance
Space-Grade Devices
I/O Resources
Memory Resources
Virtex XQR FPGAs Virtex-4QV FPGAs
Slices
(1)
Logic Cells
Part Number
Core Voltage
CLB Flip-Flops
Mi ll
DSP Slices
18 x 18 Multipliers
Phase Lock Loop (PLL)
Clock Resources
Embedded Hard IP
Resources
Enhanced DSP Slices (DSP48E)
Multi-Gigabit Serial Trasceivers (MGT)
Delay Lock Loop (DLL)
Speed Grades
V V V V V M, V M, V, B M, V, B
700 300 300 300 300 200 100 100
>125 >125 >125 >125 >125 >160 >125 >125
Package
(2)
Area
CG717
(3)
35 x 35 mm 516
CF1144
(4)
35 x 35 mm 576
CF1140
(5)
35 x 35 mm 640
CF1509
(6)
40 x 40 mm 960 768
CF1752
(7)
45 x 45 mm 836
CB228 1.55 x 1.55 in 162 162
XMP077 (v2.0)
Notes:
2. For information on DSCC SMD availability, contact Xilinx. Grade Description Temperature
3. The BG728 and CG717 packages are footprint/pin compatible. V Device Xilinx V-Grade Flow
(1)
Military Ceramic TC = -55C to +125C
4. The CF1144 and FF1152 packages are footprint/pin compatible. H Device Flip-Chip Radiation Tolerant Ceramic Tj = -55C to +125C
5. The CF1140 and FF1148 packages are footprint/pin compatible. B SMD Radiation Tolerant and Non-RT SMD Military Ceramic TC = -55C to +125C
N Military Plastic Tj = -55C to +125C
M Military Ceramic or Plastic
7. The CF1752 and FF1738 are footprint/pin compatible. I Industrial Plastic Tj = -40C to +100C
6. For the XQR4VLX200, the CF1509 and FF1513 packages are footprint/pin
compatible. For the XQR4VFX140, the CF1509 and the FF1517 are footprint/pin
compatible.
Tj = -55C to +125C (Plastic),
TC = -55C to +125C (Ceramic)
Available User I/Os
CQFP Packages (CB): Ceramic, brazed, quad flat pack (0.025 inch lead spacing)
CFA Packages (CF): Flip-chip, ceramic column grid array (1.0 mm ball spacing)
Total Ionizing Dose (krad)
CGA Packages (CG): Ceramic column grid array (1.27 mm ball spacing)
SEL Immunity (MeV-cm2/mg)
1. Each slice comprises two 4-input logic function generators (LUTs), two storage
elements, wide-function multiplexers, and carry logic.
Miscellaneous
23
XQ1701L XQ17V16 XQ18VQ4 XQF32P XQR1701L XQR17V16
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
1M 16M 4M 32M 1M 16M
M, N M, N N M M, V M, V
- - - - 50 50
CC44, VQ44 CC44, VQ44 VQ44 VQ48 CC44 CC44
Package
(2)
Area
CC44 0.69 x 0.69 in
VQ44 12 x 12 mm
VQ48 20 x 20 mm
Notes: 1. Xilinx configuration PROMs have adjustable I/O voltages for compatibility with all Xilinx FPGAs.
2. The CC44 and PC44 packages are footprint/pin compatible. For information on DSCC qualification contact Xilinx.
Grade
V TC = -55C to +125C
H Tj = -55C to +125C
B TC = -55C to +125C
N Military Plastic Tj = -55C to +125C
M T 55C 125C (Pl i ) T 55C 125C (C i )
SMD Radiation Tolerant and Non-RT SMD Military Ceramic
Mili C i Pl i
Defense-Grade
Configuration PROMs
Total Ionizing Dose (krad)
Packages
Part Number
Core Voltage
(1)
Storage Bits
Temperature
Description
Device Xilinx V-Grade Flow
(1)
Military Ceramic
Device Flip-Chip Radiation Tolerant Ceramic
Space-Grade Devices
Radiation Tolerant
Configuration PROMs
M Tj = -55C to +125C (Plastic), TC = -55C to +125C (Ceramic)
I Industrial Plastic Tj = -40C to +100C
XMP078 (v1.0)
Military Ceramic or Plastic
24
XI LI NX AUTOMOTIVE SOLUTIONS
XA6SLX4
(10,11)
XA6SLX9 XA6SLX16 XA6SLX25
(10)
XA6SLX45 XA6SLX75 XA6SLX25T
(10)
XA6SLX45T XA6SLX75T
600 1,430 2,278 3,758 6,822 11,662 3,758 6,822 11,662
3,840 9,152 14,579 24,051 43,661 74,637 24,051 43,661 74,637
4,800 11,440 18,224 30,064 54,576 93,296 30,064 54,576 93,296
75 90 136 229 401 692 229 401 692
12 32 32 52 116 172 52 116 172
216 576 576 936 2,088 3,096 936 2,088 3,096
Clock Resources
2 2 2 2 4 6 2 4 6
132 200 232 266 316 280 250 296 268
66 100 116 133 158 140 125 148 134
8 16 32 38 58 132 38 58 132
- - - - - - 1 1 1
0 2 2 2 2 2 2 2 2
- - - - - - 2 4 4
-2, -3 -2, -3 -2, -3 -2, -3 -2, -3 -2, -3 -2, -3 -2, -3 -2, -3
I, Q I, Q I, Q I, Q I, Q I, Q I, Q I, Q I, Q
Q2 2011 Q2 2011 Q2 2011 Q2 2011 Q2 2011 Q2 2011 Q2 2011 Q2 2011 Q2 2011
Configuration
2.6 2.6 3.6 6.2 11.4 18.8 6.2 11.4 18.8
Package Area
CSG225
(8)
13 x 13 mm 132 160 160
CSG324 15 x 15 mm 200 232 226 218 190 (2) 190 (4)
Maximum Differential Pairs
XILINX AUTOMOTIVE SOLUTIONS
Part Number
Slices
(1)
Logic Cells
(2)
CLB Flip-Flops
Spartan-6 LX FPGAs
(1.2V)
Spartan-6 LXT FPGAs
Optimized for Lowest-Cost Logic, DSP, and Memory with High-
Speed Serial Connectivity (1.2V)
Memory Resources
(3)
(4)
I/O Resources
Logic Resources
Miscellaneous
Maximum User I/O: SelectIO Interface Pins (GTP Transceivers)
(7)
Chip Scale Packages (CSG): Pb-free wire-bond, chip-scale, BGA (0.8 mm ball spacing)
Speed Grade
Temperature Grade
(6)
XA Released
DSP48A1 Slices
(5)
Endpoint Block for PCI Express
CSG324 15 x 15 mm 200 232 226 218 190 (2) 190 (4)
FTG256 17 x 17 mm 186 186 186
FGG484
(9)
23 x 23 mm 266 316 280 250 (2) 296 (4) 268 (4)
XMP079 (v1.3.1)
Notes: 1. Each slice contains four LUTs and eight flip-flops.
2. Spartan-6 FPGA logic cell ratings reflect the increased logic capacity offered by the new 6-input LUT structure.
3. Block RAM are fundamentally 18 Kb in size. Each block can also be used as two independent 9 Kb blocks.
4. Each CMT contains two DCMs and one PLL.
5. Each DSP48A1 slice contains an 18x18 multiplier, an adder, and an accumulator.
6. Temperature Range Automotive I (Tj = -40C to +100C); Automotive Q (Tj = -40C to + 125C).
7. The LX device pinouts are not compatible with the LXT devices.
8. CSG225 has memory controller support in the LX9 and LX16 devices. There is no memory controller in the XA6SLX4 devices.
9. Devices in the FGG484 have support for two memory controllers.
10. BPI configuration mode not available.
11. SelectMAP configuration modes not available.
Preliminary product information, subject to change. Please contact your Xilinx representative for the latest information.
BGA Packages (FGG): Pb-free wire-bond, fine-pitch, BGA (1.0 mm ball spacing)
BGA Packages (FTG): Pb-free wire-bond, fine-pitch, thin BGA (1.0 mm ball spacing)
25
XA3S50 XA3S200 XA3S400 XA3S1000 XA3S1500 XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E
50K 200K 400K 1,000K 1,500K 100K 250K 500K 1,200K 1,600K
768 1,920 3,584 7,680 13,312 960 2,448 4,656 8,672 14,752
1,728 4,320 8,064 17,280 29,952 2,160 5,508 10,476 19,512 33,192
1,536 3,840 7,168 15,360 26,624 1,920 4,896 9,312 17,344 29,504
12 30 56 120 208 15 38 73 136 231
4 12 16 24 32 4 12 20 28 36
72 216 288 432 576 72 216 360 504 648
Clock Resources
2 4 4 4 4 2 4 4 8 8
124 173 264 333 487 108 172 190 304 376
56 76 116 149 221 40 68 77 124 156
- - - - - - - - - -
4 12 16 24 32 4 12 20 28 36
- - - - - - - - - -
I, Q I, Q I, Q I, Q I I, Q I, Q I, Q I, Q I, Q
-4 -4 -4 -4 -4 -4 -4 -4 -4 -4
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Configuration
0.4 1 1.7 3.2 5.2 0.6 1.4 2.3 3.8 6
Package Footprint Area
Miscellaneous
Block RAM Blocks
CLB Flip-Flops
Logic Cells
DSP48A Slices
XA Released
RoHS (Pb-free)
Speed Grade
Temperature Grades
(4)
Device DNA Security
Logic Resources
Memory Resources
I/O Resources
Embedded Hard IP
Resources
Slices
(2)
System Gates
(1)
Spartan-3E FPGAs Spartan-3 FPGAs
LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVCMOS12, HSTL18 Class I, HSTL18 Class III,
PCI 3.3V 32/64-bit 33 MHz, SSTL2 Class I, SSTL18 Class I, Bus LVDS, LVDS25, LVPECL25, Mini-LVDS25,
and RSDS25
LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVCMOS12, HSTL15 Class I, HSTL15 Class III,
HSTL18 Class I, HSTL18 Class II, HSTL18 Class III, PCI 3.3V 32/64-bit 33 MHz, SSTL3 Class I, SSTL3
Class II, SSTL2 Class I, SSTL2 Class II, SSTL18 Class I, SSTL18 Class II, Bus LVDS, LVDS25, LVDS33,
LVPECL25, LVPECL33, Mini-LVDS25, Mini-LVDS33, RSDS25, RSDS33, TMDS25, TMDS33, PPDS25, and
PPDS33
Part Number
Maximum User I/Os
XMP079 (v1.3DRAFT) Important: Verify all data in this document with the device data sheets found at www.xilinx.com 25
VQG100 16 x 16 mm 63 63 66 66
CPG132 8 x 8 mm 83 92 92
TQG144 22 x 22 mm 97 108 108
PQG208 30.6 x 30.6 mm 124 141 141 158 158
FTG256 17 x 17 mm 173 173 173 172 190 190
FGG400 19 x 19 mm 304 304
FGG456 21 x 21 mm 264 333 333
FGG484 23 x 23 mm 376
FGG676 27 x 27 mm 487
XMP079 (v1.3.1)
4. Temperature Range Automotive I (Tj = -40C to +100C); Automotive Q (Tj = -40C to +125C).
VQFP Packages (VQ): Very thin, QFP (0.5 mm lead spacing)
Maximum User I/Os
26
XA3S200A XA3S400A XA3S700A XA3S1400A XA3SD1800A XA3SD3400A
200K 400K 700K 1,400K 1,800K 3,400K
1,792 3,584 5,888 11,264 16,640 23,872
4,032 8,064 12,248 25,344 37,440 53,712
3,584 7,168 11,776 22,528 33,280 47,744
28 56 92 176 260 373
16 20 20 32 84 126
288 360 360 576 1,512 2,268
Clock Resources
4 4 8 8 8 8
195 311 372 375 519 469
90 142 165 165 227 213
- - - - 84 126
16 20 20 32 84
(3)
126
(3)
Yes Yes Yes Yes Yes Yes
I, Q I, Q I, Q I, Q I, Q I
-4 -4 -4 -4 -4 -4
Configuration
1.2 1.9 2.7 4.8 8.2 11.7
XA Released
Maximum User I/Os
RoHS (Pb-free)
DSP48A Slices
LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVCMOS12, HSTL15 Class I, HSTL15 Class III, HSTL18 Class I, HSTL18 Class II, HSTL18 Class III, PCI 3.3V 32/64-bit 33 MHz, SSTL3 Class I, SSTL3
Class II, SSTL2 Class I, SSTL2 Class II, SSTL18 Class I, SSTL18 Class II, Bus LVDS, LVDS25, LVDS33, LVPECL25, LVPECL33, Mini-LVDS25, Mini-LVDS33, RSDS25, RSDS33, TMDS25, TMDS33, PPDS25, and
PPDS33
Device DNA Security
Temperature Grades
(4)
Speed Grade
Spartan-3A DSP FPGAs Spartan-3A FPGAs
Part Number
System Gates
(1)
Block RAM Blocks
Slices
(2)
Logic Cells
CLB Flip-Flops
Miscellaneous
Logic Resources
Memory Resources
I/O Resources
FTG256 17 x 17 mm 195 195
CSG484 19 x 19 mm 309 309
FGG400 21 x 21 mm 311 311
FGG484 23 x 23 mm 372 375
FGG676 27 x 27 mm 519 469
XMP079 (v1.3.1)
4. Temperature Range Automotive I (Tj = -40C to +100C); Automotive Q (Tj = -40C to +125C).
Maximum User I/Os
27
XA9536XL XA9572XL XA95144XL XA2C32A XA2C64A XA2C128 XA2C256 XA2C384
800 1,600 3,200 750 1,500 3,000 6,000 9,000
36 72 144 32 64 128 256 384
90 90 90 56 56 56 56 56
3 3 3 3 3 3 3 3
18 18 18 16 16 16 16 16
34 72 117 33 64 100 118 118
2.5/3.3/5 2.5/3.3/5 2.5/3.3/5 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3
2.5/3.3 2.5/3.3 2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3
15.5 15.5 15.5 5.5 6.7 7 7 9.2
-15 -15 -15 -6 -7 -7 -7 -10
-15 -15 -15 -7 -8 -8 -8 -11
I, Q I, Q I, Q I, Q I, Q I, Q I, Q I, Q
Yes Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes
Package Area
(2)
VQG44 12 x 12 mm 34 34 33 33
VQG64 12 x 12 mm 52
VQG100 16 x 16 mm 64 80 80
TQG100 16 x 16 mm 72
Maximum User I/Os
Output Voltage Compatible (V)
Minimum Pin-to-Pin Logic Delay
Automotive I Speed Grades
Automotive Q Speed Grades
Input Voltage Compatible (V)
XA9500XL FamiIy
VQFP Packages (VQ): Very thin QFP (VQG44: 0.8 mm lead spacing; VQG64 and VQG100: 0.5 mm lead spacing)
System Gates
Part Number
Macrocells
Global Clocks
CooIRunner"-II FamiIy
XA Released
Temperature Grades
(1)
RoHS (Pb-free)
Maximum I/O
Logic Resources
Clock Resources
I/O Resources
Speed Grades
Miscellaneous
TQG100 16 x 16 mm 72
TQG144 22 x 22 mm 118 118
CPG132 8 x 8 mm 100
CSG144 12 x 12 mm 117
XMP079 (v1.3.1)
Notes: 1. Temperature Grade XA CPLD Automotive I (TA = -40C to +85C); Automotive Q (TA = -40C to +105C with Tj MAXIMUM = +125C).
2. Area dimensions for lead-frame products are inclusive of the leads.
28
XI LI NX BOARDS AND KITS
XILINX BOARDS AND KITS
Product Name Purpose Part Number Devices Supported Features
Virtex-6 FPGA ML605 Evaluation Kit
www.xilinx.com/ml605
General-purpose FPGA Evaluation kit EK-V6-ML605-G XC6VLX240T-1FFG1156
x8 PCI Express, FMC (HPC & LPC), DDR3 SO-DIMM (512 MB), PlatformFlash & BPI Flash Memory, System ACE
USB-To-UART, USB 2.0 Host & Device, 10/100/1000 Ethernet, SFP, DVI Out, 16x2 Character Display
Virtex-6 FPGA ML623 Characterization Kit
GTX Characterization Kit CK-V6-ML623-G XC6VLX240T-1FFG1156
40 SMA pairs, System ACE controller, SuperClock-2 module, 10 differential SMA connector pairs for GTX transceiver
clock inputs, Three FMC HPC connectors (Each with 79 differential user-defined pairs, no GTX transceivers), USB-to-
UART bridge
Virtex-6 FPGA Connectivity Kit Serial Connectivity Kit with Targeted Reference Design DK-V6-CONN-G XC6VLX240T-1FFG1156
ML605 (EK-V6-ML605-G) + Serial Connectivity FMC Module (HW-FMC-XM104-G) and Serial Connectivity Reference
Design
Virtex-6 FPGA Embedded Kit Embedded Kit with Targeted Reference Design DK-V6-EMBD-G XC6VLX240T-1FFG1156 ML605 (EK-V6-ML605-G) + Embedded Reference Design
Virtex-6 FPGA DSP Kit DSP Kit with Targeted Reference Design AES-V6DSP-LX240T-G XC6VLX240T-1FFG1156 ML605 (EK-V6-ML605-G) + DSP Reference Design
Virtex-6 FPGA Broadcast Connectivity Kit Broadcast Connectivity Kit with Targeted Reference Design
DK-V6-BCCN-G
XC6VLX240T-1FFG1156 ML605 (EK-V6-ML605-G) + Broadcast FMC Module and Broadcast Reference Design
Virtex-5 FPGA ML501
General-purpose FPGA development board HW-V5-ML501-UNI-G XC5VLX50FFG676
DDR2 SO-DIMM (256 MB), ZBT SRAM (1 MB), NOR Flash, PlatformFlash PROM and SPI Flash Memory, System
ACE CompactFlash, JTAG Header or External JTAG Connector, 2x USB, 2x PS/2, 10/100/1000 Ethernet, RS-232, 2x
Audio In/Out, DVI/VGA Video, XGI Expansion Port
Virtex-5 FPGA ML505
General-purpose FPGA and RocketIO GTP development
board
HW-V5-ML505-UNI-G XC5VLX50TFF1136
DDR2 SO-DIMM (256 MB), ZBT SRAM (1 MB), Linear, platform, and SPI flash, System ACE CompactFlash, JTAG
Header or External JTAG Connector, 2x USB, 2x PS/2, 10/100/1000 Ethernet, RS-232, 2x Audio In/Out, DVI/VGA Video,
XGI Expansion Port, MGT support with PCI Express, SFP, SMA, SGMII
Virtex-5 FPGA ML506
General-purpose FPGA, DSP, and RocketIO GTP transceiver
development board
HW-V5-ML506-UNI-G XC5VSX50TFF1136
Virtex-5 FPGA ML507
General-purpose FPGA , PPC440 processor, and RocketIO
GTX transceiver development platform
HW-V5-ML507-UNI-G XC5VFX70TFF1136
Virtex-5 FPGA ML510
Advanced hardware/software embedded processing
development platform
HW-V5-ML510-G XC5VFX130T-FFG1738
32-bit component DDR memory and 64-bit DDR2 DIMM, 512 MB CompactFlash card and System ACE CompactFlash
controller for configuration, Two onboard 10/100/1000 Ethernet PHYs with RJ-45 connectors, Two PCI Express
interface, VGA graphics interface, ATX Form Factor, 4x PCI 32-bit/33MHz slots, 2x USB ports, 2x SATA ports, 2x RS-
232, 2x PS/2, XPM Expansion Port
Virtex-5 FPGA ML523
RocketIO GTP transceiver characterization development
platform
HW-V5-ML523-UNI-G XC5VLX110T-FF1136
16 RocketIO GTP Transceivers connected to SMA pairs, 8 RocketIO GTP REFCLK inputs connected to SMA pairs,
SuperClk module supporting a wide range of clock frequencies, Power indicator LEDs, General-purpose DIP switches,
LEDs, and pushbutton switches
Virtex-6 FPGA DeveIopment Boards and Kits
Virtex-5 FPGA Gigabit Ethernet Development Kit
www.xilinx.com/ gbedevkit
Virtex-5 FPGA Gigabit Ethernet development HW-V5GBE-DK-UNI-G XC5VLX50T-1FF1136C
Quick Start Guide and platform USB programming cable, ISE evaluation software and access to LogiCORE IP,
Resource CD (reference designs, labs, and demonstrations), Connectors: GbE - SFP and RJ-45 connectors, 10/100
Mb/s, RJ-45 connector
Virtex-5 LXT Development Kit for PCI Express, PCI-
X and PCI
www.xilinx.com/v5pciekit
Application development board for PCI Express and PCI HW-V5-ML555-G
Virtex-5 FPGA LXT XC5VLX50T-
1FF1136CES
Quick Start Guide and platform USB programming cable, ISE evaluation software and access to LogiCORE IP, Resource
CD (reference designs, labs, and demonstrations), Connectors: PCIe - 8-land add-in card connector, PCI/PCI-X; standard
edge connector
Virtex-5 FPGA Embedded Kit
www.xilinx.com/v5embedded
Advanced embedded processing development kit DK-V5-EMBD-ML507-G X5LX50T-1FFG1136C
Powerful Virtex-5 FPGA MC507 development board, Full seat of Platform Studio Embedded tool suite, Full seat of ISE
Foundation FPGA design software, Reference designs, USB JTAG probe, flash device, cables, and power supply
Virtex-4 FPGA ML401
General-purpose FPGA development board HW-V4-ML401-UNI-G XC4VLX25-FF668
64 MB DDR SDRAM, ZBT synchronous SRAM, 10/100/1000 tri-speed Ethernet PHY transceiver, USB interface device
with host and peripheral ports, RS-232 serial port, XGI Expansion Port
Virtex-4 FPGA ML402
General-purpose FPGA/DSP development board HW-V4-ML402-UNI-G XC4VSX35-FF668
Virtex-4 FPGA ML403
General-purpose FPGA/PPC processor development board HW-V4-ML403-UNI-G XC4VFX12-FF668
Virtex-4 FPGA ML405
General-purpose FPGA/PPC/RocketIO transceiver
development board
HW-V4-ML405-UNI-G XC4VFX20-FF672
128 MB SDRAM DDR SDRAM, ZBT synchronous DRAM, MGT: Serial ATA host connectors (x2), MGT: SFP connector
(x1), MGT: SMA connector connected to one RocketIO MGT, XGI Expansion Port
Virtex-4 FPGA ML410
Embedded system development platform HW-V4-ML410-UNI-G XC4VFX60-11FFG1152
ATX form factor motherboard, 64 MB DD and 256 MB DDR2 DIMM, 512 MB CompactFlash card and System ACE
CompactFlash controller for configuration, 10/100/1000 tri-speed Ethernet PHY transceiver, RJ-45 connectors (x2), XPM
Expansion Port
Virtex-4 FPGA ML423
RocketIO transceiver characterization HW-V4-ML423-UNI-G XC4VFX100-11FF1152
20 RocketIO GTP Transceivers connected to SMA pairs, 10 RocketIO GTP REFCLK inputs connected to SMA pairs,
SuperClk module supporting a wide range of clock frequencies, Power indicator LEDs, General-purpose DIP switches,
LEDs, and pushbutton switches
29
Spartan-6 FPGA SP601 Evaluation Kit
www.xilinx.com/sp601
General-purpose FPGA development board
EK-S6-SP601-G
EK-S6-SP601-G-J (Japan)
XC6SLX16-CS324
Onboard configuration circuitry, Quad SPI flash 64 MB, 16 MB parallel (BPI) flash, DDR2 component memory 128 MB
Spartan-6 FPGA SP605 Evaluation Kit
www.xilinx.com/sp605
General-purpose FPGA evaluation board
EK-S6-SP605-G
EK-S6-SP605-G-J (Japan)
XC6SLX45T-FGG484 -3
Onboard JTAG configuration circuitry, 128 MB Platform Flash XL, Quad SPI flash 64 MB, System ACE 2G
CompactFlash card
Avnet Spartan-6 LX150T Development Kit
http://www.xilinx.com/products/devkits/AES-S6DEV-
LX150T-G.htm
General-purpose FPGA evaluation board AES-S6DEV-LX150T-G XC6SLX150T-3FGG676
The Xilinx Spartan-6 LX150T Development Kit provides a complete development platform for designing and verifying
applications based on the Xilinx Spartan-6 LXT FPGA family.
Avnet Spartan-6 LX16 Evaluation Kit
http://www.xilinx.com/products/devkits/AES-S6EV-
LX16-G.htm
General-purpose FPGA evaluation board AES-S6EV-LX16-G XC6SLX16-CSG324
Utilizing Spartan-6, Avnet introduces the first-ever battery-powered Xilinx FPGA development board, the Xilinx Spartan-6
LX16 Evaluation Kit.
Spartan-6 FPGA Embedded Kit
http://www.xilinx.com/products/devkits/DK-S6-EMBD-
G.htm
Spartan-6 FPGA Embedded Kit
DK-S6-EMBD-G
DK-S6-EMBD-G-J (Japan)
XC6SLX45T-FGG484 -3
Embedded Design Platforms enable rapid software application development as well as easy customization of the
processor hardware subsystems.
Spartan-6 FPGA Connectivity Kit
http://www.xilinx.com/products/devkits/DK-S6-CONN-
G.htm
Spartan-6 FPGA Connectivity Kit
DK-S6-CONN-G
DK-S6-CONN-G-J (Japan)
XC6SLX45T-FGG484 -3
The Spartan-6 FPGA Connectivity kit is a complete, easy-to-use Connectivity Development and Demonstration platform
for designing with standards based protocols - PCIe, Ethernet, implementing low-cost protocol bridging, providing higher
efficiency alternative to LVDS communication, etc in multiple market segments.
Spartan-6 FPGA DSP Kit
http://www.xilinx.com/products/devkits/AES-S6DSP-
LX150T-G.htm
Spartan-6 FPGA DSP Development AES-S6DSP-LX150T-G XC6SLX150T-3
Wireless, aerospace and defense, instrumentation and medical imaging applications continue to demand greater
performance to support standards, while high-level design flows continue to improve to provide an easier entry point for
using FPGAs for DSP.
Spartan-6 FPGA Industrial Ethernet Kit
http://www.xilinx.com/products/devkits/AES-S6IEK-
LX150T-G.htm
Spartan-6 FPGA Industrial Ethernet Developmet AES-S6IEK-LX150T-G XC6SLX150T-3FGG676
The Spartan-6 FPGA Industrial Ethernet Kit is a comprehensive design environment for rapid prototyping and
development of leading edge industrial applications in connectivity, motor control, and embedded processing.
Spartan-6 FPGA Industrial Video Processing Kit
http://www.xilinx.com/products/devkits/AES-S6IVK-
LX150T-G.htm
Spartan-6 FPGA Industrial Video Processing AES-S6IVK-LX150T-3FGG676 XC6SLX150T-3
The Spartan-6 FPGA Industrial Video Processing Kit is a comprehensive design environment for rapid prototyping and
streamlined development of high resolution video conferencing, video surveillance and machine vision systems.
Spartan-6 FPGA Consumer Video Kit
http://www.xilinx.com/products/devkits/TB-6S-
CVK.htm
Spartan-6 FPGA Consumer Video TB-6S-CVK XC6SLX150T-3
Speed up development of video algorithms and incorporate the latest video interface standards right out of the box. The
Spartan-6 FPGA Consumer Video Kit is a comprehensive design environment for developing and debugging advanced
video algorithms.
Spartan-6 FPGA DeveIopment Boards and Kits
Spartan-3 FPGA DeveIopment Kits
Spartan-3A FPGA Starter Kit
www.xilinx.com/s3astarter
Low-cost Spartan-3A FPGA board evaluation kit HW-SPAR3A-SK-UNI-G XC3S700A-FG484
Evaluation board with Spartan-3A FPGA, onboard 10/100 Ethernet PHY, SPI based ADC and DAC circuitry, 64 MB
DDR2, two 16 Mb SPI serial flash. Interfaces include a 2x16 LCD display and various I/O ports, including a PS/2 port, a
VGA display port, and two serial ports. Kit includes evaluation board, power supply with universal adaptors, programming
cable, quick-start guide, design tools, evaluation software, and collateral.
Spartan-3AN FPGA Starter Kit
www.xilinx.com/s3anstarter
Low-cost Spartan-3AN FPGA board evaluation kit HW-SPAR3AN-SK-UNI-G XC3S700AN-4FGG484C
Evaluation board with Spartan-3AN FPGA, onboard 10/100 Ethernet PHY, SPI based ADC and DAC circuitry, 64 MB
DDR2, and two 16 Mb SPI serial flash. Interfaces include a 2x16 LCD display and various I/O ports, including a PS/2 port,
a VGA display port, and two serial ports. Kit includes evaluation board, power supply with universal adaptors,
programming cable, quick-start guide, design tools, evaluation software, and collateral.
Spartan-3A DSP FPGA 1800A Edition
XtremeDSP Solution Starter Board
www.xilinx.com/s3adspstarter
Low-cost, entry-level environment for developing signal
processing designs
HW-SD1800A-DSP-SB-UNI-G XC3SD1800A-4FGG676C
Memory: 128 MB (32M x 32) DDR2 SDRAM; 16M x 8 parallel / BPA configuration flash; 64 Mb SPI configuration/storage
flash (with 4 extra SPI selects), EXP expansion connector
Spartan-3E FPGA Starter Kit
www.xilinx.com/s3estarterkit
Low-cost Spartan-3E FPGA development kit HW-SPAR3E-SK-UNI-G XC3S700A-FG484
Evaluation board with Spartan-3E FPGA, CoolRunner-II CPLD, 128 Mb parallel flash, 16 Mb SPI flash, 64 MB DDR
SDRAM, Interfaces include Ethernet 10/100 PHY, two RS-232 serial ports, PS/2 style mouse/keyboard, 2x16 character
LCD, Kit includes evaluation board, power supply with universal adaptors, programming cable, quick-start-guide, design
tools evaluation software, and collateral.
XtremeDSP Solution Video Kit
www.xilinx.com/vsk_s3
Video application development on Spartan-3A FPGAs DO-SEADSP-VIDEO-SK-UNI-G XC3SD3400A-4FGG676C
Includes full seats of System Generator and EDK, Example video reference designs, Complete documentation, Platform
USB cable, power supply, and video cables, Carrier board: Spartan-3A FPGA DSP DPFA F3400A Development Board,
Mezzanine card: FMC-video
Spartan-3A DSP S3D1800A MicroBlaze Processor
Edition Embedded Development HW/SW Kit
www.xilinx.com/s3adspmb
Flexible embedded processing development kit DO-SD1800A-EDK-DK-UNI-G XC3SD1800A-4FGG676C
Full seat of Platform Studio embedded tool suite, ISE WebPACK FPGA design software, Reference designs, USB
programming download cable, UART, Ethernet cables and power supply
Spartan-3A DSP FPGA 3400A Edition XtremeDSP
Solution Development Platform
www.xilinx.com/s3adap_dp
Spartan-3A FPGA DSP application development solution HW-SD3400A-DSP-DB-UNI-G XC3SD3400A-4FGG676C
Onboard 256 MB DDR2 SDRAM; 256 Mb flash; 9 Mb ZBT SRAM; 32 Mb Platform flash 16 Mb SPI EEPROM; 256 MB
CompactFlash, Two FMC and a LPC expansion connector
30
CoolRunner-II CPLD Starter Kit Featuring the
DataGATE Low-Power Advantage
www.xilinx.com/products/devkits/SK-CRII-L-G.htm
General-purpose CPLD evaluation board SK-CRII-L-G XC2C256-TQ144
Complete 'out-of-the-box' evaluation platform, CoolRunner-II CPLD utility window, Easy set-up and monitoring, DataGATE
evaluation "switch", Free reference designs
FMC Debug Mezzanine Card
www.xilinx.com/products/devkits/HW-FMC-DBG-
G.htm
FMC XM105 Debug Mezzanine Card HW-FMC-XM105-G
VITA 57.1 FMC HPC connector, Single-ended signals from the carrier board, clocks, JTAG, and power, 40 single-ended
I/O (20 pairs) on the LPC pins, 80 single-ended I/O (40 pairs) on the HPC pins, Mictor connector 38 pins female Mictor
connector
FMC XM104 Connectivity Card
www.xilinx.com/xm104
FMC Connectivity HW-FMC-XM104-G
The FMC XM104 Connectivity Card is designed to provide access to eight serial transceivers on the FMC HPC connector
found on Xilinx FMC-supported boards including Virtex-6 ML605. These eight serial transceivers can be accessed
through one CX4 (x4 transceivers), two SATA (x2 transceivers), and eight SMA (x2 transceivers) connectors.
XMP080 (v1.0)
FMC Daughter-cards
CPLD Starter Kits
31
XI LI NX
I P CORES, REFERENCE DESIGNS, AND I NSTRUCTOR LED TRAI NI NG COURSES

Advanced IP
Quickly and easily search for IP Cores from Xilinx and its 3rd party alliance partners at www.xilinx.com/ipcenter.
Reference Designs
Reference Designs can be found under the 'Topics' tab of the Documentation Center, www.xilinx.com/documentation.
FPGA Curriculum Learning Level
*ISE Design Tool Flow
Designing with Verilog
Designing with VHDL
FPGA Design for ASIC Users
Designing with the Virtex-6 and Spartan-6 Families
*Essentials of FPGA Design
Design Techniques for Lower Cost
Debugging Techniques Using the ChipScope Pro Tools
*Designing for Performance
Designing with the PlanAhead Analysis and Design Tool
TMRTool
*Advanced FPGA Implementation
4
XILINX IP CORES, REFERENCE DESIGNS, and INSTRUCTOR LED TRAINING COURSES
Instructor Led Training Courses
*Recommended Courseware
Elective Courseware
1
2
3
Advanced VHDL
Embedded Hardware Curriculum Learning Level
*Embedded Systems Development 3
*Advanced Embedded Systems Development 4
Embedded Software Curriculum Learning Level
*Embedded Systems Software Development 3
*Embedded Open-Source Linux Development 4
Connectivity Curriculum Learning Level
*Designing a LogiCORE PCI Express System
*Designing with Multi-Gigabit Serial I/O
*Designing with Ethernet MAC Controllers
*Signal Integrity and Board Design for Xilinx FPGAs
DSP Curriculum Learning Level
*DSP Design Using System Generator 3
XMP082 (v1.0)
3
32
XI LI NX PRODUCTIVITY ADVANTAGE
XiIinx Productivity Advantage (XPA) www.xiIinx.com/xpa
1 Year 2 Years 3 Years Description
DS-XPA-10K Custom XPA for $0 - $10,000
DS-XPA-50K DS-XPA2-50K DS-XPA3-50K Custom XPA for $10,001 - $50,000
Note: Multi-year option only available when the 1 year deal list price is greater than $40,000.
XMP083 (v1.0)
Custom XPA Part Numbers
XILINX PRODUCTIVITY ADVANTAGE
Xilinx Productivity Advantage (XPA) helps you efficiently migrate your FPGA designs to our hardware platforms through a customizable
software and services bundle. With the help of a Xilinx sales representative and application engineering team, you can choose the right mix of
productivity solutions at the start of your design. Bundle and save today!
XMP083 (v1.0) Important: Verify all data in this document with the device data sheets found at www.xilinx.com 32 XMP083 (v1.0) Important: Verify all data in this document with the device data sheets found at www.xilinx.com 32
Corporate Headquarters
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
USA
Tel: 408-559-7778
www.xilinx.com
Europe
Xilinx Europe
One Logic Drive
Citywest Business Campus
Saggart, County Dublin
Ireland
Tel: +353-1-464-0311
www.xilinx.com
Japan
Xilinx K.K.
Art Village Osaki Central Tower 4F
1-2-2 Osaki, Shinagawa-ku
Tokyo 141-0032 Japan
Tel: +81-3-6744-7777
japan.xilinx.com
Asia Pacific Pte. Ltd.
Xilinx, Asia Pacific
5 Changi Business Park
Singapore 486040
Tel: +65-6407-3000
www.xilinx.com
Copyright 2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the
United States and other countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. The PowerPC name and logo are
registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their respective owners. Distributed by:

FPGA Product Selection Guide

Uploaded by

Copyright:

Available Formats

FPGA Product Selection Guide

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

FPGA Product Selection Guide

Uploaded by

Copyright:

Available Formats

Product Selection Guides

Design Suite ......................................................................................................................... 17

I P CORES, REFERENCE DESIGNS, AND I NSTRUCTOR LED TRAI NI NG COURSES

You might also like