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    Experiment No. 7: Steps To Implement The Multiplexer

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    Rishit Bhatia
    The document describes designing a 4:1 multiplexer using VHDL. It outlines the objective to implement a 4x1 multiplexer and describes the design process which includes generating behavioral VHDL code, simulating the design, synthesizing it, assigning pin locations, generating programming files, and programming the FPGA device. The conclusion states that a 4x1 multiplexer was successfully implemented and describes how the inputs and output are mapped to switches and LEDs.

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    Attribution Non-Commercial (BY-NC)
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    Experiment No. 7: Steps To Implement The Multiplexer

    Uploaded by

    Rishit Bhatia
    20 views2 pages
    The document describes designing a 4:1 multiplexer using VHDL. It outlines the objective to implement a 4x1 multiplexer and describes the design process which includes generating behavioral VHDL code, simulating the design, synthesizing it, assigning pin locations, generating programming files, and programming the FPGA device. The conclusion states that a 4x1 multiplexer was successfully implemented and describes how the inputs and output are mapped to switches and LEDs.

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    Exp 10

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    The document describes designing a 4:1 multiplexer using VHDL. It outlines the objective to implement a 4x1 multiplexer and describes the design process which includes generating behavioral VHDL code, simulating the design, synthesizing it, assigning pin locations, generating programming files, and programming the FPGA device. The conclusion states that a 4x1 multiplexer was successfully implemented and describes how the inputs and output are mapped to switches and LEDs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    20 views2 pages

    Experiment No. 7: Steps To Implement The Multiplexer

    Uploaded by

    Rishit Bhatia
    The document describes designing a 4:1 multiplexer using VHDL. It outlines the objective to implement a 4x1 multiplexer and describes the design process which includes generating behavioral VHDL code, simulating the design, synthesizing it, assigning pin locations, generating programming files, and programming the FPGA device. The conclusion states that a 4x1 multiplexer was successfully implemented and describes how the inputs and output are mapped to switches and LEDs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    of 2

    EXPERIMENT NO.

    7
    AIM:Design of 4:1 MUX using VHDL.

    OBJECTIVE:
    Implementation of 4x1 multiplexer using VHDL.

    DESIGN DESCRIPTION:
    A Multiplexer (MUX) is a device that allows digital information from several sources to be routed onto a single line for transmission. The basic multiplexer has several data input lines and a single output line. It also has data select inputs which permit digital data on any one of the inputs to be switched to the output line. Multiplexers are also called data selectors. Y = S1 S0 I0 + S1 S0 I1 + S1 S0 I2 + S1 S0 I3

    FIG. 4:1 MUX PROCEDURE:


    Steps to implement the Multiplexer:1. 2. Start the Xilinx project navigator by using the desktop shortcut or by using start-> programs->Xilinx ISE ->project navigator. In the project navigator window go to filenew projectselect device.

    3. 4. 5. 6. 7. 8. 9.

    10. 11. 12.

    13. 14. 15. 16. 17.

    Click on the symbol of FPGA device and then right click on new sourceVHDL module and give name Multiplexerdefine ports->finish. Generate the behavioral VHDL code for the Multiplexer. Check the syntax and remove the existing errors. Simulate the design using Modelsim. Synthesize the design using XST. To run the synthesis, right click on synthesis, and choose the run option, or double-click on synthesize in the processes for current source window. In user constraints, assign pin no. for AND gate as follow:a loc=P111 b loc=P110 c loc=P109 d loc=P109 s1 loc=P98 s0 loc=P99 y loc=p71 Then save and minimize the window. Make the settings of JTAG clock, go to generate programming file right click on that and then select properties. Then go to startup option and select the clock. Run the Xilinx implementation tools. Once the synthesis is complete we can place and route our design into our Xilinx device and you can also get some post place and route timing information about the design. This procedure runs through the basic flow for implementation. Right click on implement design and choose the run option or double leftclick on implementation design. Right click on general programming file and choose the run option or double left click on generate programming file. This will generate the bit stream. Double- click the Xilinx device .then select and11.bitand file type-FPGA bit files(.bit) then open Right click on Xilinx device and program the device. Apply input to DIP switch. Output is displayed on LEDs.

    CONCLUSION:Design of 4x1 Multiplexer is implemented. Switch sw5 for input a Switch sw4 for input b Switch sw3 for input c Switch sw2 for input d Switch sw1 for input s1 Switch sw0 for input s0 Green led d1 for output y

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