Adsp Manual

EINSTEN COLLEGE OF ENGINEERING
(An Institution with NBA Accredited Engineering Departments)
Sir. C. V. Raman Nagar, Tirunelveli – 627012.
LABORATORY MANUAL
SUBJECT CODE - NAME
AP4152 ADVANCED DIGITAL DESIGN

LABORATORY
Name: ..............................................................
Reg. No: ............................................................
Year-Section: ....................................................
Department: .....................................................
INDEX
S.NO NAME OF THE EXPERIMENT MARK SIGNATURE
7
EX NO:1 DATE:
DESIGN THE SIMULATION OF SHIFT REGISTER
AIM:
To design and simulate the Shift Register using XILINX tool.

APPARATUS REQUIRED
S.No Name of the equipment/ software Quantity

1 PC with Windows 1
2 Xilinx Project navigator 1
THEORY:
Shift register are the registers which are used to shift the stored bit
in one or both directions. In this section, shift register is implemented
which can be used for shifting data in both direction. Further it can be
used as parallel to serial converter or serial to parallel converter. Verilog
files required for this example are listed below.
PROCEDURE:
To start ISE, double click the desktop icon, Xilinx ISE 8.2i (or)
start - > All programs - > Xilinx 8.2i - > Project navigator.
To create a new project: Select File > New Project... The New Project Wizard
appears.
1. Type project name in the Project Name field. Verify that

HDL is selected from the Top-Level Source Type list.
2. Click Next to move to the device properties page.
3. Fill in the properties in the table as shown below:
♦ Product Category: All
♦ Family: Spartan3
♦ Device: XC3S400
♦ Package: PQ208
♦ Speed Grade: -4
♦ Top-Level Module Type: HDL
♦ Synthesis Tool: XST (VHDL/Verilog)
♦ Simulator: ISE Simulator (VHDL/Verilog)
♦ Verify that Enable Enhanced Design Summary is
selected.
4. Keep other properties as such and click next (3 times)
5. Project summary window will open. Click finish.
To Create a Verilog Source
6. Sources - > XC3S400-4PQ208 (right click) - > Click the
New Source button. New Project Wizard will open.
7. Select Verilog Module as the source type. Type file name.
Click Next.
8. Define module will open. Click next.
9. New source wizard summary will open. Click finish.
10. Minimize the design summary & maximize the verilog
program editor.
11. Type the program and save.
12. Check synthesis/implementation option is selected in
sources for window.
13. Expand synthesis XST (in processes window) & double
click check syntax.
14. Expand synthesis XST (in processes window) & double
click view RTL schematic. Double click in the symbol, to
view the logic diagram. Close the RTL window.
To verify functionality using Behavioral simulation
15. Select behavioral simulation in sources for window.
16. Select the verilog file in the Sources window.
17. Create a new test bench source by selecting Project →
New Source.
18. In the New Source Wizard, select Test Bench Waveform
as the source type, and type file name in the File Name
field. Click next (2 times).
19. The New source wizard Summary will open. Click finish.
20. Initial timing & clock wizard will open. Select clock
information - > single clock. Keep other settings as such.
Click finish.
21. Set the input waveforms, save & close the test bench
waveform window.
22. Select the test bench waveform file in the hierarchy.
23. Expand the Xilinx ISE simulator in processes window.
Double click simulate behavioral model.
24. Click the simulation tab, to view the simulation results.
PROGRAM:
module shift_register #(
parameter N = 8)(
input wire clk, reset,
input wire [1:0] ctrl,
input wire [N-1:0] data,
output wire [N-1:0] q_reg);
reg [N-1:0] s_reg, s_next;always @(posedge clk, posedge reset)begin
if(reset)
s_reg <= 0; // clear the content
else if (clk == 1'b1)
s_reg <= s_next; // otherwise save the next stateend
always @(ctrl, s_reg)begin

case (ctrl)
0 : s_next = s_reg; // no operation (to read data for serial to parallel)
1 : s_next = {data[N-1], s_reg[N-1:1]}; // right shift
2 : s_next = {s_reg[N-2:0], data[0]}; // left shift
3 : s_next = data; // load data (for parallel to serial)
endcaseend
assign q_reg = s_reg;endmodule
OUTPUT
RESULT
Thus the Shift Register was designed, simulated and extracted

successfully using Xilinx tool.
EX NO:2 DATE:
DESIGN THE SIMULATION OF ASYNCHRONOUS COUNTER

AIM
To design and simulate the Asynchronous Counter using Xilinx tool.
APPARATUS REQUIRED

1. PC with Windows 1
2. Xilinx Project navigator 1
THEORY
In Asynchronous Counter is also known as Ripple

Counter, different flip flops are triggered with different clock, not
simultaneously. While in Synchronous Counter, all flip flops are
triggered with same clock simultaneously and Synchronous Counter is
faster than asynchronous counter in operation.
PROCEDURE
To create a new project:
1. Select File > New Project... The New Project Wizard appears.
♦ Device: XC3S400
♦ Package: PQ208
♦ Speed Grade: -4
selected.
5.Keep other properties as such and click next (3 times)
1. Sources - > XC3S400-4PQ208 (right click) - > Click the New
Source button. New Project Wizard will open.
2. Select Verilog Module as the source type. Type file name. Click
Next.
5. Minimize the design summary & maximize the verilog program
editor.
7. Check synthesis/implementation option is selected in sources for
window.
8. Expand synthesis XST (in processes window) & double click
check syntax.
view RTL schematic. Double click in the symbol, to view the
logic diagram. Close the RTL window.
3. Create a new test bench source by selecting Project → New
Source.
4. In the New Source Wizard, select Test Bench Waveform as the
source type, and type file name in the File Name field. Click
next (2 times).
6. Initial timing & clock wizard will open. Select clock
information - > single clock. Keep other settings as such. Click
finish.
7. Set the input waveforms, save & close the test bench waveform
window.
9. Expand the Xilinx ISE simulator in processes window. Double
click simulate behavioral model.
PROGRAM
Asynchronous counter
module asynchronouscounter(clk, clear, q);
input clk,clear;
output reg [3:0] q;
always @(posedge clk or posedge clear)
q[0]<=~q[0];
always @(posedge q[0] or posedge clear)
q[1]<=~q[1];
q[2]<=~q[2];
begin
if(clear)
q =4'b0000;
else
q[3]=~q[3];
end
Endmodule
OUTPUT
RESULT
Thus the Asynchronous Counter was designed, simulated and
extracted successfully using Xilinx tool.
EX NO:3 DATE:
DESIGN THE SIMULATION OF UPDOWN COUNTER
AIM
To design and simulate the Updown Counter using XILINX tool.
APPARATUS REQUIRED

1. PC with Windows 1
2. Xilinx Project navigator 1
THEORY
Counters are used in many different applications. Some count up

from zero and provide a change in state of output upon reaching a
predetermined value; others count down from a preset value to zero to
provide an output state change.
PROCEDURE
1. Select File > New Project... The New Project Wizard appears.
2. Type project name in the Project Name field. Verify that HDL is
selected from the Top-Level Source Type list.
♦ Device: XC3S400
♦ Package: PQ208
♦ Speed Grade: -4
selected.
1. Sources - > XC3S400-4PQ208 (right click) - > Click the New Source
button. New Project Wizard will open.
2. Select Verilog Module as the source type. Type file name. Click Next.
5. Minimize the design summary & maximize the verilog program editor.
window.
8. Expand synthesis XST (in processes window) & double click check
syntax.
9. Expand synthesis XST (in processes window) & double click view RTL
schematic. Double click in the symbol, to view the logic diagram. Close
the RTL window.
3. Create a new test bench source by selecting Project → New Source.
4. In the New Source Wizard, select Test Bench Waveform as the source
type, and type file name in the File Name field. Click next (2 times).
6. Initial timing & clock wizard will open. Select clock information - >
single clock. Keep other settings as such. Click finish.
7. Set the input waveforms, save & close the test bench waveform window.
9. Expand the Xilinx ISE simulator in processes window. Double click
simulate behavioral model.
PROGRAM:
Up down counter
module updowncounter(clk, clear, updown, q);
input clk,clear,updown;
output reg [3:0] q;
always@(posedge clear or posedge clk)
begin
if(clear)
q <=4'b0000;
else if(updown==0)
q <= q+1'b1;
else
q <= q-1'b1;
end
endmodule
OUTPUT
RESULT
Thus the Updown Counter was designed, simulated and extracted successfully
using Xilinx tool.
EX NO:4 DATE:
DESIGN THE SIMULATION OF SEQUENTIAL MACHINES THAT IS

FLIPFLOPS AND LATCHES
AIM
To design and simulate the Sequential machines that is flip

flops and latches using XILINX tool.
APPARATUS REQUIRED

1 PC with Windows 1
THEORY
In Verilog, signal assignment statements that begin with the
keyword “assign” are known as a continuous assignment statements.

Continuous assignment statements model wires in physical circuits that
are continuously driven to some value (a ‘0’ or a ‘1’). When the Verilog
simulator evaluates the right-hand side of a continuous assignment
statement, a new output value can be immediately calculated based on the
input signal values, and the calculated value can be assigned to the output
signal wire (on the left of the assignment operator).
In some cases, output signal values can only be assigned after the Verilog
simulator executes a procedure to check the status of one or more of the
input signals. Consider a flip-flop for example. A simple “if-then”
procedure must be executed to determine if an active clock edge has just
occurred before a new output value can be assigned: “if a rising clock
edge has occurred, then assign the output Q the value present on the input
D”. Verilog includes procedural assignment statements to check
conditions like this prior to making an assignment.
The example code below illustrates Verilog code for defining various
memory devices.
D-Latch. Note the sensitivity list contains the Gate, Reset and Data
signals, because changes on any of these signals can cause the output to
change state. Also note Rst is checked first - if reset is asserted, the output
is driven to ‘0’ and the always block is exited.
The example code below shows the same D-Latch code, but the
sensitivity list signals are replaced by the wild card character “*”. Using
the wild card character directs the synthesizer to construct a sensitivity
list that includes all signals on the right-hand side of assignment
statements that can cause output changes.
D-Flip-Flop. Note the use of the “posedge” procedures in the

sensitively list. Alternatively, just the signal names could have been used,
and then signal levels could be checked with if statements. Also note the
check for reset comes before Q is assigned - this defines an
“asynchronous reset”.
PROCEDURE
Select File > New Project... The New Project Wizard appears.
♦ Device: XC3S400
♦ Package: PQ208
♦ Speed Grade: -4
selected.
1.Sources - > XC3S400-4PQ208 (right click) - > Click the New Source
2.Select Verilog Module as the source type. Type file name. Click Next.
3.Define module will open. Click next.
4.New source wizard summary will open. Click finish.
5.Minimize the design summary & maximize the verilog program editor.
6.Type the program and save.
7.Check synthesis/implementation option is selected in sources for
window.
8.Expand synthesis XST (in processes window) & double click check
syntax.
9.Expand synthesis XST (in processes window) & double click view RTL
schematic. Double click in the symbol, to view the logic diagram.
Close the RTL window.
1.Select behavioral simulation in sources for window.
2.Select the verilog file in the Sources window.
3.Create a new test bench source by selecting Project → New Source.
4.In the New Source Wizard, select Test Bench Waveform as the source
type, and type file name in the File Name field. Click next (2 times).
5.The New source wizard Summary will open. Click finish.
6.Initial timing & clock wizard will open. Select clock information - >
single clock. Keep other settings as such. Click finish.
7.Set the input waveforms, save & close the test bench waveform window.
8.Select the test bench waveform file in the hierarchy.
9.Expand the Xilinx ISE simulator in processes window. Double click
PROGRAM
D-Flip-Flop.
always @ (posedge(clk), posedge(rst))
Begin
if (rst == 1) Q <= 1'b0; // Q is reset to 0
else Q <= D;
End
D-Latch.
always @ (D, G, rst)begin
if (rst == 1)
Q <= 1'b0; // Q is reset to 0
else if (G == 1)
Q <= D;end
OUTPUT
D Flip-Flop.
D LATCH
RESULT
Thus the Sequential machines that is flipflops and latches was

designed, simulated and extracted successfully using Xilinx tool.
EX NO:5 DATE:
DESIGN THE SIMULATION OF SERIAL ADDER
AIM
To design and simulate the Serial Adder using XILINX tool.

APPARATUS REQUIRED

1 PC with Windows 1
THEORY
A serial adder is used to add two binary numbers in serial form.

The two binary numbers to be added serially are stored in two shift
registers. The circuit adds one pair at a time with the help of one full
adder.
PROCEDURE
To create a new project: Select File > New Project... The New Project Wizard
appears.
1. Type project name in the Project Name field. Verify that HDL is selected
from the Top-Level Source Type list.
♦ Device: XC3S400
♦ Package: PQ208
♦ Speed Grade: -4
selected.
5.Project summary window will open. Click finish.
5. Minimize the design summary & maximize the verilog program editor.
7. Check synthesis/implementation option is selected in sources for window.
8. Expand synthesis XST (in processes window) & double click check syntax.
9. Expand synthesis XST (in processes window) & double click view RTL
schematic. Double click in the symbol, to view the logic diagram. Close
the RTL window.
4. In the New Source Wizard, select Test Bench Waveform as the source type,
and type file name in the File Name field. Click next (2 times).
6. Initial timing & clock wizard will open. Select clock information - > single
clock. Keep other settings as such. Click finish.
7. Set the input waveforms, save & close the test bench waveform window.
9. Expand the Xilinx ISE simulator in processes window. Double click
10.Click the simulation tab, to view the simulation results.
PROGRAM
module serial(sum,cout,a,b,clk);
input [3:0] a,b;
input clk;
wire [3:0] x,z;
output [3:0] sum;
output cout;
wire s,cin;
//input cin;
//initial begin
//cin=cinp;
//end
fa k(s,cout,x[0],z[0],cin); //1 bit full adder
dff q(cin,cout,clk); //d flipflop to store the cout value after each 1
bit full adder operation
sipo m(sum,s,clk); //serial sum(s) converted to parallel output(4
bit sum)///
shift g(x,a,clk); //shifts the input a
shift h(z,b,clk); //shifts the input b
endmodule
OUTPUT
RESULT
Thus the Serial Adder was designed, simulated and extracted

EX NO:6 DATE:
SIMULATION OF ARITHMETIC LOGIC UNIT
AIM
To design and simulate the Arithmetic logic unit using

XILINX tool.
APPARATUS REQUIRED

1 PC with Windows 1
THEORY
An arithmetic logic unit (ALU) is a digital circuit used to perform

arithmetic and logic operations. It represents the fundamental building
block of the central processing unit (CPU) of a computer. Modern CPUs
contain very powerful and complex ALUs. In addition to ALUs, modern
CPUs contain a control unit (CU).
PROCEDURE
To create a new project: Select File > New Project... The New Project
Wizard appears.
♦ Device: XC3S400
♦ Package: PQ208
♦ Speed Grade: -4
selected.
5.Project summary window will open. Click finish.
editor.
window.
8. Expand synthesis XST (in processes window) & double click check
syntax.
9. Expand synthesis XST (in processes window) & double click view
RTL schematic. Double click in the symbol, to view the logic
diagram. Close the RTL window.
source type, and type file name in the File Name field. Click next
(2 times).
6. Initial timing & clock wizard will open. Select clock information -
> single clock. Keep other settings as such. Click finish.
window.
PROGRAM
module alu(
input [7:0] A,B, // ALU 8-bit Inputs
input [3:0] ALU_Sel,// ALU Selection
output [7:0] ALU_Out, // ALU 8-bit Output
output CarryOut // Carry Out Flag
);
reg [7:0] ALU_Result;
wire [8:0] tmp;
assign ALU_Out = ALU_Result; // ALU out
assign tmp = {1'b0,A} + {1'b0,B};

assign CarryOut = tmp[8]; // Carryout flag
always @(*)
begin
case(ALU_Sel)
4'b0000: // Addition
ALU_Result = A + B ;
4'b0001: // Subtraction
ALU_Result = A - B ;
4'b0010: // Multiplication
ALU_Result = A * B;
4'b0011: // Division
ALU_Result = A/B;
4'b0100: // Logical shift left
ALU_Result = A<<1;
4'b0101: // Logical shift right
ALU_Result = A>>1;
4'b0110: // Rotate left
ALU_Result = {A[6:0],A[7]};
4'b0111: // Rotate right
ALU_Result = {A[0],A[7:1]};
4'b1000: // Logical and
ALU_Result = A & B;
4'b1001: // Logical or
ALU_Result = A | B;
4'b1010: // Logical xor

ALU_Result = A ^ B;
4'b1011: // Logical nor
ALU_Result = ~(A | B);
4'b1100: // Logical nand
ALU_Result = ~(A & B);
4'b1101: // Logical xnor
ALU_Result = ~(A ^ B);
4'b1110: // Greater comparison
ALU_Result = (A>B)?8'd1:8'd0 ;
4'b1111: // Equal comparison
ALU_Result = (A==B)?8'd1:8'd0 ;
default: ALU_Result = A + B ;
endcase
end
endmodule
OUTPUT
RESULT
Thus the Arithmetic logic unit was designed, simulated and

extracted successfully using Xilinx tool.
EX NO:7 DATE:
DESIGN THE SIMULATION OF 4 BIT MULTIPLIER
AIM
To design and simulate the 4 Bit Multiplier using XILINX tool.

APPARATUS REQUIRED

1 PC with Windows 1
THEORY
A 4-bit multiplication the algorithm will complete in no more than
4 cycles. The technique is simply one of long multiplication. Below you
can see the long multiplication of two 4-bit values to produce an 8-bit
result.
PROCEDURE
To create a new project: Select File > New Project... The New Project
Wizard appears.

♦ Device: XC3S400
♦ Package: PQ208
♦ Speed Grade: -4
selected.
1. Sources - > XC3S400-4PQ208 (right click) - > Click the New
Source button. New Project Wizard will open.
2. Select Verilog Module as the source type. Type file name. Click
Next.
editor.
window.
check syntax.
9. Expand synthesis XST (in processes window) & double click view
RTL schematic. Double click in the symbol, to view the logic diagram.
Close the RTL window.
source type, and type file name in the File Name field. Click next
(2 times).
6. Initial timing & clock wizard will open. Select clock information -
> single clock. Keep other settings as such. Click finish.
window.
PROGRAM
module multiplier(a, b, out);

input [3:0] a,b;
output [7:0] out;
assign out=(a*b);
endmodule
OUTPUT
RESULT
Thus the 4 Bit Multiplier was designed, simulated and extracted

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EINSTEN COLLEGE OF ENGINEERING

(An Institution with NBA Accredited Engineering Departments)

Sir. C. V. Raman Nagar, Tirunelveli – 627012.

SUBJECT CODE - NAME

AP4152 ADVANCED DIGITAL DESIGN

Reg. No: ............................................................

S.NO NAME OF THE EXPERIMENT MARK SIGNATURE

DESIGN THE SIMULATION OF SHIFT REGISTER

To design and simulate the Shift Register using XILINX tool.

S.No Name of the equipment/ software Quantity

1. Type project name in the Project Name field. Verify that

input wire clk, reset,

input wire [1:0] ctrl,

input wire [N-1:0] data,

output wire [N-1:0] q_reg);

reg [N-1:0] s_reg, s_next;always @(posedge clk, posedge reset)begin

s_reg <= 0; // clear the content

else if (clk == 1'b1)

s_reg <= s_next; // otherwise save the next stateend

always @(ctrl, s_reg)begin

0 : s_next = s_reg; // no operation (to read data for serial to parallel)

1 : s_next = {data[N-1], s_reg[N-1:1]}; // right shift

2 : s_next = {s_reg[N-2:0], data[0]}; // left shift

3 : s_next = data; // load data (for parallel to serial)

assign q_reg = s_reg;endmodule

Thus the Shift Register was designed, simulated and extracted

DESIGN THE SIMULATION OF ASYNCHRONOUS COUNTER

To design and simulate the Asynchronous Counter using Xilinx tool.

S.No Name of the equipment/ software Quantity

In Asynchronous Counter is also known as Ripple

DESIGN THE SIMULATION OF UPDOWN COUNTER

S.No Name of the equipment/ software Quantity

Counters are used in many different applications. Some count up

DESIGN THE SIMULATION OF SEQUENTIAL MACHINES THAT IS

To design and simulate the Sequential machines that is flip

S.No Name of the equipment/ software Quantity

In Verilog, signal assignment statements that begin with the

keyword “assign” are known as a continuous assignment statements.

D-Flip-Flop. Note the use of the “posedge” procedures in the

To create a new project:

always @ (posedge(clk), posedge(rst))

if (rst == 1) Q <= 1'b0; // Q is reset to 0

always @ (D, G, rst)begin

Q <= 1'b0; // Q is reset to 0

Thus the Sequential machines that is flipflops and latches was

DESIGN THE SIMULATION OF SERIAL ADDER

To design and simulate the Serial Adder using XILINX tool.

S.No Name of the equipment/ software Quantity

A serial adder is used to add two binary numbers in serial form.

Thus the Serial Adder was designed, simulated and extracted

SIMULATION OF ARITHMETIC LOGIC UNIT

To design and simulate the Arithmetic logic unit using

S.No Name of the equipment/ software Quantity

An arithmetic logic unit (ALU) is a digital circuit used to perform

input [7:0] A,B, // ALU 8-bit Inputs

input [3:0] ALU_Sel,// ALU Selection

output [7:0] ALU_Out, // ALU 8-bit Output

output CarryOut // Carry Out Flag

reg [7:0] ALU_Result;