Shrivastava Thesis

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ANALYSIS AND DESIGN OF A 3-STAGE VOLTAGE RECTIFIER MULTIPLIER

AND 2-STAGE MULTI-PHASE VOLTAGE DOUBLER FOR AN ENERGY


HARVESTING SYSTEM

By

Ravindranath Shrivastava, B.E.

A Thesis
In
ELECTRICAL ENGINEERING
Submitted to the Graduate Faculty
of Texas Tech University in
Partial Fulfillment of
the Requirements for
the Degree of

MASTER OF SCIENCE
IN
ELECTRICAL ENGINEERING

Approved
Richard Gale
Chair of Committee

Changzhi Li

Peggy Gordon Miller


Dean of the Graduate School

August, 2012
©Copyright 2012, Ravindranath Shrivastava
Texas Tech University, Ravindranath Shrivastava, August 2012

ACKNOWLEDGEMENT6

I joined Texas Tech University in the Spring 2012 with a desire to learn and contribute
towards the top class Research at the Department. I developed a keen interest in Analog
IC Design after I had taken classes like 'Analog IC Design' and 'Communication IC
Design' class. I performed very well in the class projects and kept developing my design
capabilities.

Due to my interest in Integrated Circuit Design, I joined the research group at the 'Analog
and RF Research Lab'. There I got to study many circuits which I wouldn't have learned
just through classes. Also I developed self learning skills, where I could analyze various
kinds of circuits ranging from 'DC-DC converters' types to OPAMP Circuits to ON-Chip
Oscillators.

I greatly appreciate all the help offered by Dr. Richard Gale and Dr. Changzhi Li towards
the completion of this project. I also appreciate all the facilities the Department and the
Lab has provided me. It not only made possible the completion of the project, but also
helped me learn many design and lab skills.

I would also like to thank my family and friends who supported me during my pursuit of
the Master's Degree.

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Texas Tech University, Ravindranath Shrivastava, August 2012

TABLE OF CONTENTS

ACKNOWLEDGMENTS ............................................................................................. ii
ABSTRACT .............................................................................................................. iv
LIST OF TABLES .......................................................................................................v
LIST OF FIGURES ................................................................................................... vi
I. ENERGY HARVESTING AND LINK MONITORING SYSTEM...................................1
1.1 Need for Energy Harvesting ..........................................................................1
1.2 Need for Link Monitoring ..............................................................................1
1.3 Misalignment of the TX and RX coil ............................................................2
1.4 Power Management System: Block Diagram ................................................3
II. 3 STAGE VOLTAGE MULTIPLIER .......................................................................6
2.1 Voltage Multiplier using NMOS Diode .........................................................6
2.2 Bulk Modulation of NMOS Diode ................................................................8
2.3 PMOS Diode instead of NMOS Diode ........................................................13
2.4 PMOS Diode – 3 Stage Voltage Multiplier .................................................13
2.5 Input Voltage Boosting using LC Network .................................................16
2.6 Battery Charging using 5 Stage Voltage Multiplier ....................................18
2.7 Simulations Results - 3 Stage Voltage Multiplier........................................21
III. 2-STAGE MULTIPHASE CHARGE PUMP ..........................................................24
3.1 Need for Voltage Regulation and Voltage Boosting using MVPD .............24
3.2 Multi Phase Voltage Doubler (MVPD) – Charge Pump .............................25
3.3 Main Power Stage ........................................................................................28
3.4 Circuit Analysis for MPVD .........................................................................32
3.5 PMOS Capacitor ..........................................................................................34
3.6 Non Overlapping Clock Generator ..............................................................38
3.7 Clock Generation Circuitry using D Flip Flop ............................................38
IV. DESIGN OF FEEDBACK CONTROL FOR CHARGE PUMP ..................................42
4.1 Introduction to Feedback Control – Frequency Control ..............................42

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Texas Tech University, Ravindranath Shrivastava, August 2012

4.2 OPAMP Design – Error Amplifier ..............................................................42


4.2.1 Telescopic Cascode OPAMP ................................................................43
4.2.2 Rail to Rail Folded Triple Cascode OPAMP for Gain Boosting ..........47
4.2.3 Rail to Rail Folded Triple Cascode OPAMP – Simulation Results .....53
4.3 Voltage Controlled Oscillator ......................................................................59
4.3.1 Ring Oscillator Basics...........................................................................59
4.3.2 Basic Differential Delay Cell ................................................................62
4.3.3 Modified Differential Cell – Constant Load Current Technique ..........63
4.3.4 Modified Differential Cell – Simulation Results ..................................66
4.3.5 VCO Characteristics .............................................................................67
4.3.6 Wideband Ring VCO using adaptive load control ...............................69
4.3.7 Wideband Ring VCO – Simulation Results .........................................73
V. MPVD - SIMULATION RESULTS .......................................................................75
VI. CONCLUSION AND FUTURE WORK .................................................................78
REFERENCES..........................................................................................................79

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Texas Tech University, Ravindranath Shrivastava, August 2012

ABSTRACT

The reliability and the efficiency of the wireless link between the TX/RX for wireless
sensor devices depends on environmental conditions such as change in the physical
distance or changes in the orientation between transmitter and receiver. So the need arises
to monitor and the ability to adjust the wireless link between TX/RX without interrupting
the operation of the wireless sensor. Also the ambient wireless energy can also be
harvested to power the wireless sensor circuitry. We propose an N-Stage Voltage
Multiplier/Rectifier built in AMI06 process using a Schottky diode to convert the ambient
RF Energy into DC voltage which can be measured to evaluate the strength of the
Wireless link. The proposed system can be used to monitor and vary the wireless link
parameters such as the resonant matching condition between the TX/RX antenna coil and
physical alignment without interrupting the operation of the wireless sensor. Also the DC
energy harvested can be boosted further by our proposed multiphase charge pump to a
higher DC Level which can be used by the wireless sensor circuitry. The DC power
harvested can also be used alongside the on board battery which will lead to an increase
in battery efficiency. The voltage multiplier/rectifier and charge pump involving the
power stage and the feedback circuitry can be built on the same die as the wireless sensor
circuitry which can lead to a less bulky system.

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Texas Tech University, Ravindranath Shrivastava, August 2012

LIST OF TABLES

4.1 The performance characteristic of the Triple Cascode OPAMP 73


4.2 The table of the relationship between the control voltage and the output 83
frequency of the VCO
4.3 Performance Characteristics of the Wideband VCO 89

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Texas Tech University, Ravindranath Shrivastava, August 2012

LIST OF FIGURES

1.1 The above figure shows the misalignment between the primary and the 1
secondary coil
1.2 Simplified block diagram of the Energy Harvesting and Non Interruptive 2
Link Monitoring System using Resonant Coils
2.1.1 NMOS diode with its gate terminal connected to the drain. 5
2.1.2 The above diagram shows the working of the NMOS Diode when the Vin 6
changes from 0 to Vm and back to 0
2.2.1 Bulk Modulation NMOS diode with its gate and bulk terminal connected to 8
the drain
2.2.2 Modulation of Vth in above circuit when the input voltage varies. We can 9
see the decrease in the Vth value as Vin increase beyond Vload
2.3.1 The vertical cross section of the Bulk Connected Forward Biased NMOS 10
Diode. The Internal Diode i.e. the Source (n+) and the Body (p) also
conducts leading to increase in forward current increasing output voltage
2.3.2 The vertical cross section of the Bulk Connected Forward Biased PMOS 11
Diode. The Internal Diode i.e. the Drain (p-) and the Body (n) also
conducts leading to increase in forward current increasing output voltage
2.3.3 PMOS diode with its bulk - gate terminal connected to the drain used in the 11
3 Stage Voltage Multiplier instead of NMOS Diode
2.3.4 The schematic of a single stage voltage doubler based on the Dickson’s 12
Charge Pump design
2.4.1 3-Stage Voltage Multiplier Each stage contains 2 diodes and 2 Caps. The 12
Caps are implemented using PMOS Caps so that we get value as large as
100pF on Chip. The Diodes as basically PMOS Drain-Bulk Connected
Diodes

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Texas Tech University, Ravindranath Shrivastava, August 2012

2.4.2 Negative Half The diode D1 is ON and D2 is OFF so current flows as 13


shown below and Charges C1 to Vin peak i.e. Vm
2.4.3 Positive Half D1 is OFF and D2 is ON and C1 is already charged to Vm is 14
previous half. So C1 and Vin both charge the Cap C2 to 2Vm
2.4.4 The actual schematic of the 3 Stage Voltage Multiplier with PMOS used as 14
diodes
2.4.5 The PMOS Capacitance schematic with terminal marked 15
2.5.1 The cadence schematic of the 3 stage multiplier using the LC resonant 16
circuit connected at the input for voltage boosting. Also the LC parallel
resonant tank used at the input of the circuit to boost the voltage at the
actual input of the multiplier
2.5.2 The waveform at the input of the 3 Stage Multiplier circuit block boosted 16
from 257mVpp to 600mVpp
2.5.3 The waveform at the input of the 3 Stage Multiplier circuit block boosted 17
from 344mVpp to 811mVpp
2.6.2 5 Stage Voltage Multiplier with Rload disconnected from the rest of the 18
circuit in order to simulated battery charging
2.6.2 Input power = -21 to -27dBm, Cload – 500pF, NMOS Size –90u/1u, 18
NMOS Diodes used. In this simulation NMOS diodes where used unlike
the ones shown in Fig 2.6.1
2.6.3 Input power = -21 dBm, Cload – 500pF, PMOS Size –180u/1u, Vripple – 19
9.94mVpp, In this simulation NMOS diodes where used
2.6.5 Input power = -21 to -27dBm, Cload – 500pF, NMOS Size – 90u/1u, 19
PMOS – 2*NMOS
2.6.6 Input power = -27dBm, Load Resistance – 10K, Cload – 500pF, NMOS 20
Size – 90u/1u, PMOS – 2*NMOS
2.7.1 Input Power vs PCE We can see that for the PMOS Diode Size selected the 21
PCE is maximum for load resistance around 10K Ohms

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Texas Tech University, Ravindranath Shrivastava, August 2012

2.7.2 Input Power vs Output Voltage As the load current reduces the output 22
voltage does increase as seen in the 2nd graph
2.7.3 Lower load current leads to reduction in PCE. Load Currents ranging from 22
200uA to 600uA provide good PCE
2.7.4 The Transient Response of the 3 Stage Voltage Multiplier done with 10 K 23
load and input power as low as -9dBm. VDC above 100mV can be
harvested with 10.3uA load current
3.1 A Basic Linear Regulator implemented using an OPAMP and Power 25
MOSFET. The main problem with this is, it has drop out voltage across
MOSFET and if the Vin < Vdd then boosting Vin is not possible
3.2.1 PWM Control Main Block Diagram of the 2 Stage Multi Phase Charge 27
Pump along with the voltage controlled feedback loop
3.2.2 Frequency Regulation The main block diagram of Multi Phase Voltage 28
Doubler (MVPD) as a Charge Pump with Frequency control technique
implemented using a VCO
3.3.1 The Cadence schematic of the main power stage of the charge pump. The 29
upper part shows the main CMOS switches, Dead Time Control block, the
Non Overlapping clock generation circuitry and CMOS switch drivers
3.3.1 The Cadence schematic of the main power stage of the charge pump. The 30
upper part shows the main CMOS switches, Dead Time Control block, the
Non Overlapping clock generation circuitry and CMOS switch drivers
3.3.3 Phase 1 – MPVD 30
3.3.4 Phase 2 - MPVD 30
3.3.5 Phase 3 - MPVD 31
3.3.6 Phase 4 - MPVD 32
3.3.7 The waveform of the above mentioned circuit. The explanation for the 32
waveform is given above
3.3.8 The actual waveforms to the switches S1-S8. Due to pin parasitic elements, 33

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Texas Tech University, Ravindranath Shrivastava, August 2012

high frequency usage the switching waveforms get distorted


3.5.1 The graph shows the relationship between the values of Total Capacitance 36
seen at the gate when the gate voltage is varied
3.5.2 The relationship between the Capacitance and W/L Ratio 37
3.5.3 The PMOS Capacitance schematic with terminal marked 37
3.6.1 For the small time interval ∆T as described below, the switches S1 and S4 38
can be ON for a short period of time connecting the input to ground
through S1-S4 creating short circuit and damaging the power switches
3.6.2 Waveform explaining the difference between Overlapping Clock and Non 38
Overlapping clock
3.6.3 The schematic of the circuit used to generate a Non-Overlapping waveform 39
as shown the above
3.7.1 The switching waveform for the charge pump and the output of the D Flip 40
Flop circuitry as shown in the Fig 3.7.2
3.7.2 a) The D Flip Flop is used to divide the CLK by half. The AND Gate are 41
used to generate the clocks for the 2nd Stage of the Charge Pump. b) The
1st Stage requires the generation non-overlapping clocks, so simple circuit
proposed in is used to generate it
3.7.3 The schematics of the D Flip Flop which is used to divide the switching 41
frequency by 2
4.1.1 The feedback loop of the Charge Pump. The Vref decides the output 43
voltage of the charge pump and it can be tweaked to change the output
voltage of the charge pump
4.2.1.1 The schematic of a Telescopic Folded Cascode OPAMP 45
4.2.2.1 The Rail to Rail input stage for the Folded Cascode OPAMP makes sure 47
that the input swing can be increased up to the Rails. Also the Folded
configuration isolates the input stage from the output stage
4.2.2.2 The effective gm of the input pair of the OPAMP and the variation in its 48

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Texas Tech University, Ravindranath Shrivastava, August 2012

value from gm-2gm-gm over a range of values of Vincm from 0 to VDD


4.2.2.3 The schematic of a Rail to Rail Double Folded Cascode OPAMP 48
4.2.3.1 The schematic of the Rail to Rail Triple Folded Cascode OPAMP 50
4.2.3.2 The breakdown of the Rout resistance of the OPAMP. The Rout1 and 51
Rout2 resistance calculation is shown below
4.2.3.3 The breakdown of the Rout1 resistance looking down into the PMOS load 52
of the OPAMP
4.2.3.3 The breakdown of the Rout2 resistance looking down into the NMOS load 54
of the OPAMP
4.2.4.1 OPAMP connected in Non Inverting Configuration with a gain of 50. Rf - 55
500M Ohms and R1 – 10M Ohms
4.2.4.2 Transient Response of the input given to the above test circuit 56
4.2.4.3 Transient Response of the OPAMP for the above Circuit 56
4.2.4.4 The biasing of the upper portion of the output stage of the Triple Cascode 57
OPAMP along with the operating points of the devices
4.2.4.5 The plot of the Vds voltages of M4/5, M6/7 and M8/9 devices of the 57
OPAMP when the input voltage is varied from 0 to VDD in an unity gain
Non Inverting Configuration
4.2.4.4 The gain and phase response of the OPAMP with the DC Gain of 101dB 58
and the unity gain bandwidth of 2.3MHz. The graph also shows the phase
margin of 58 degree
4.2.4.5 Plot of CMMR of the OPAMP. CMRR – 102dB 59
4.2.4.6 Plot of PSRR of the OPAMP. PSRR – 139dB 59
4.3.1.1 The block diagram of a basic 3 stage Ring Oscillator with 3 differential 61
cells and buffers at the output. The 3rd stage is connected to the 1st with
180 degree of inversion
4.3.1.2 The above waveform shows the output of each stage of the Ring Oscillator. 62
It can be seen that a phase shift of 60 degree is present between the A1 and

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Texas Tech University, Ravindranath Shrivastava, August 2012

A2 and similarly between A2 and A3


4.3.1.3 The Frequency Response of the 3 Stages of the Ring Oscillator which 63
shows the phase shift introduced
4.3.2.1 The schematic of the basic differential delay cell with variable negative 64
load
4.3.2.2 The half circuit of the above mentioned delay cell 65
4.3.3.1 The schematic of a differential cell formed using differential input pair, 67
Cascode load and cross coupled differential pair for negative resistance
4.3.4.1 The cadence schematic of a ring oscillator using 3 differential cells and 68
NOT gate the output for wave-shaping. The circuit at the left of the figure
is just used for generating bias voltages
4.3.4.2 The waveform of the output of the VCO when a control voltage of 1.5V is 68
applied which generates an output frequency of 32.1MHz
4.3.4.3 The waveform of the output of the VCO when a control voltage of 0.43V is 69
applied which generates an output frequency of 5.2MHz
4.3.5.1 The plot of characteristics of the VCO showing the relationship between 69
the control voltage on the X axis and the Output Frequency on the Y axis
4.3.6.1 The schematic of the differential cell used in the design. The Vb1 and Vb2 71
is changed respective of Vcontrol to get high bandwidth VCO
4.3.6.2 The graph shows the variation in the value of bias voltages with respect to 72
the change in value of control voltage
4.3.6.3 The OPAMP used in an inverting configuration to generate Vb1 and Vb2 72
required to reduce the load resistance when the value of control voltage
increases
4.3.6.4 The Figure shows the reduction of load resistance with increase in control 73
voltage
4.3.6.5 The plot of the product Rl * gm3 w.r.t. control voltage. It shows that for 74
most of the values of control voltage the product remain less than zero

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Texas Tech University, Ravindranath Shrivastava, August 2012

4.3.6.6 The plot of the product Requivalent w.r.t. control voltage. It shows large 74
variation of resistance w.r.t. to Control Voltage
4.3.7.1 The characteristic of the VCO showing the variation of frequency w.r.t. to 75
Control Voltage
4.4.1 The complete schematic of the charge pump in cadence 77
4.4.2 The cadence schematic of the feedback circuitry of the charge pump 78
4.4.3 The frequency response of the feedback loop of the circuit with 51 Degree 78
of phase margin. This shows that the feedback shows stability
4.4.4 The Waveform shows the load regulation taking place when the load 79
current changes from 2.5mA to 2mA
4.4.5 The Waveform shows the load regulation taking place when the load 79
current changes from 0.5mA to 2.5mA

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Texas Tech University, Ravindranath Shrivastava, August 2012

CHAPTER I

ENERGY HARVESTING AND LINK MONITORING SYSTEM

Energy Harvesting is a wide field which involves the development of systems which
can extract energy from sources like mechanical motion, ambient heat, U.V. rays,
Ambient Radio Waves etc. It has one of the fastest growing markets with products
already available in the market like wireless phone chargers, laptop charging, charging
of implantable biomedical devices etc. In this thesis we will be going through some of
these applications, as to how energy harvesting hardware can be implemented as a
SoC. In particular we are interested in harvesting RF energy from a known source
which can be further converted into a usable form i.e. DC. Implantable Biomedical
sensors and other biomedical devices include Pacemakers, Vital Signs Monitoring
Sensors, Functional Electrical Simulators (FES), and Left Ventricles Assist Devices
(LVAD) use on board battery for powering up. As the transistor size decreases, the
size of the sensor can also be shrunk down to a small scale.

1.1 Need for Energy Harvesting

- Need for small battery size and frequent need to replace the battery
- Movement and Exploration is somewhat necessary for the speedy recovery of the
patient and Wired sensors limit movement of the patient
- Replacement of batteries of the Sensors requires tissue to be opened up every time.
- Wired sensors require an incision through the tissue for a wire to power up the
sensor, exposing the tissue. There are chances of infection of the exposed soft
tissue.
- We propose a RF Energy Harvesting system (see Fig 2), which can be
implemented along with the biomedical sensor on the same die, acting as the
power source for the sensor.

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Texas Tech University, Ravindranath Shrivastava, August 2012

1.2 Need for Link Monitoring

- Complete Energy Transfer between the TX and RX coil is only possible if they are
properly tuned which depends on the alignment of the coil.

- The Inductive Coils cannot be tuned at the time of Manufacturing.

- Tuning of TX coil can be done after implantation. But feedback from the Receiver
is required to know if maximum energy transfer is still taking place.

- The strength of the received signal depends upon the distance between the
transmitter and receiver antennas.

- We also propose a Non Interruptive Link Monitoring and Adaptive System which
monitors the misalignment between the RX/TX coils and adaptively tunes the RX
coil to the overcome the misalignment.

1.3 Misalignment of the TX and RX coil

The RX-TX antenna are supposed to be aligned in the manner shown in position 3 in
the below shown figure 1.1. This positioning leads to maximum energy getting
transferred from the transmitter coil to the receiver coil. The figure also shows
misalignments that can take place leading to reduction in efficiency of the system. The
parameters of the RX coil need to be tweaked so as to take care of the misalignment.

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Texas Tech University, Ravindranath Shrivastava, August 2012

Fig 1.1: The above figure shows the misalignment between the primary and the
secondary coil. The primary coil is kept at a constant position and the secondary coil
will be kept at the 5 positions shown. (The above figure is not to the scale)

1.4 Power Management System – Block Diagram

The system will consist of an energy source like an oscillator combined with a power
amplifier driving a series tuned LC coil.

Fig 1.2: Simplified block diagram of the Energy Harvesting and Non Interruptive Link
Monitoring System using Resonant Coils.

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Texas Tech University, Ravindranath Shrivastava, August 2012

Transmitter: The transmitter will consist of a TX inductor coil driven with a PA and
a Cap. C is present to tune the coil. The PA amplifier can be a simple Class A power
amplifier which is used to boost not only the modulated carrier wave but also the serve
the purpose of driving the TX coil at maximum output power. The coil is made up of
PCB inductor as shown below with only 4 turns. A series capacitor is used to realize
series resonance and the parallel capacitor is used to fine tune the coil. The basic idea
of using the series resonance is that when the TX coil and the RX coil are in resonance
maximum energy can be transferred [1].

Receiver Coil: The RX coil consists of an inductor coil and a capacitor bank (digitally
controlled) for adaptive tuning. The RX coil also uses series resonance to attain
maximum energy transfer and it uses a digitally controlled capacitor bank to fine tune
In case of any miss-alignment between the coils.

3 Stage Voltage Multiplier: Converts the RF voltage to usable DC voltage which is


be fed into a Regulator to ensure regulated power supply for the sensor circuitry.

Regulator - Charge Pump: The output voltage of the Voltage Multiplier can vary and
so can the load current. But the other sensor circuitry being powered by the Energy
Harvesting System needs regulated constant DC Voltage. Also sometimes the voltage
provided by the Energy Harvester can be less than the voltage needed to run the sensor
circuitry. So the need to Regulate and Boost the unregulated output of the energy
harvester arises. The Energy Harvester and DC-DC Convertor will be discussed in this
thesis.

Data Acquisition and Adaptive Control Logic: Now as explained earlier, the power
at the output of the RX coil depends upon the alignment between the TX and RX coil.
If the coils are misaligned, the capacitor value show next to the RX coil needs to be
adjusted to take care of the misalignment. For this we need a data Acquisition system
which is a low power ADC and a control logic unit to control the value of the tunable

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Texas Tech University, Ravindranath Shrivastava, August 2012

cap. The unit adjusts the Cap bank to retune RX coil in case of a misalignment. ADC
samples the DC voltage at the Rectifier’s Output which will give an idea about the rate
of energy transfer between the RX and TX coil. If the Cload capacitor at the output of
3 Stage Voltage Rectifier/Multiplier charge at a faster rate than no misalignment or
very less misalignment is present. If the rate of transfer of charge into the load
capacitor decreases, then the some misalignment is present and we need to adjust the
value of the tunable capacitor.

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Texas Tech University, Ravindranath Shrivastava, August 2012

CHAPTER 2
3-STAGE VOLTAGE MULTIPLIER

The output of the RX coil is just a pure sinusoidal RF signal that needs to be rectified
and harvested in a very efficient manner so that we can use it further for supplying
power to the rest of the sensor circuitry. The basic Dickson’s charge pump design was
chosen and modified later to detect lower input power levels. The Dickson’s Charge
Pump is just a simple Full Wave Rectifier which can be cascaded to form a Multiplier
to Harvest as much Charge as possible. The details of the circuit will be discussed
later. First we’ll start with basic understanding of a simple rectifier circuit. And later
we will concentrate on how we can increase the ON Current in a simple rectifier
circuit leading to increase in the output voltage of the rectifier. Also how that
particular technique can be applied to a 3 Dickson’s stage voltage multiplier and how
it helps in energy harvesting. A battery can also be charged using this Multipliers and
it will be shown how a low power input signal can be still used to charge a battery
over time.

2.1 Voltage Multiplier using NMOS Diode


The schematic shown in the figure shows a very simple half wave rectifier with
NMOS Diode with diode connection used to convert AC to DC. The gate of the
NMOS diode is connected to the drain so that the diode turns on when the input
voltage goes above Vth. Also we will be discussing later as how the diode conduct to
some extent when the input is lower than Vth but the conduction current is very less
compared to the current in ON Stage. Schottky Diodes have low turn voltage but they
have large leakage current issues so are avoided for now. The Figure 2.1.2 shows the
working of the NMOS Diode when the input voltage varies from 0 to Vm and back to
0. The NMOS Diode conducts in the 2 regions when the input voltage swings out
there 3 below mentioned regions.

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OFF Region: From the region t0 to t1 the Vin is less than Vload. When Vin – Vload,
which is basically Vgs, is less than zero the device is completely OFF and no current
will flow through the diode.

Fig 2.1.1: NMOS diode with its gate terminal connected to the drain.

Fig 2.1.2: The above diagram shows the working of the NMOS Diode when the Vin
changes from 0 to Vm and back to 0 [11].

Sub Threshold Region: From the region t1 to t2 the Vin is greater than Vload and
less than Vth. As soon as the Vin goes above Vload, Vgs becomes positive. Now Vgs
is still less than Vth and the Vgs and Vds is greater than zero. So the device has started
conducting in the Sub-Threshold Region. The diode current is comparatively less
compared to the conduction in the Saturation Region.

I = I e ζ (2.1.1)

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Texas Tech University, Ravindranath Shrivastava, August 2012

Where:
kT
V = Thermal Voltage which is gievn by V =
q
ζ > 1 "hich is called as the non ideality factor

Saturation Region: From the region t2 to t3 Vin – Vload = Vgs is greater than Vth
and Vds is greater than Vgs-Vth. Now as the Vgs – Vth < Vds and Vgs > Vth then the
diode enters the saturation region. The current is given by:
,
I = β%V&' − V)* + (2.1.2)
Where:
W
β = Process and dependent factor
L
V)* = Threshold Voltage of the NMOS device
After the region from t3 to t4 the same Sub Threshold Conduction takes place and the
so on.

2.2 Bulk Modulation of NMOS Diode


The NMOS performance can be characterized by the Power Conversion Efficiency
(PCE) of the diode. The power conversion efficiency (PCE) of the single stage diode
rectifier is given by:
789: 789:
PCE = ==
7;< 7>) ? 7@8 A
(2.2.1)

PB'' = PCDE + PGHI (2.2.2)

PCDE - Power loss occurring due to the forward voltage drop i.e. the voltage required
to turn on the diode. PGHI is the loss due to reverse leakage current.

Now the PCE is observed to be less when the input power is very less, mostly below
0dBm. As the input power drops the Pout is very much comparable to the Ploss and so

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Texas Tech University, Ravindranath Shrivastava
Shrivastava,, August 2012

the PCE drops. The Ploss also decides the lowest input power below which no energy
can be harvested. Below a certain value of Pin, Ploss just become large in comparison
to Pout. The PCE of the device can only be improved by reduction in the losse
losses.
s. Now
as we can see from the equation 2.1.4 the Ploss component is mostly made up of P FWD
loss and PREV loss. Now PREV is comparatively less in the case of NMOS Diodes as the
Vth is very high. The most prominent loss present in the NMOS diodes is the Forw
Forward
ard
Loss which is basically due to the presence of large Vth. Now if we can come up with
a technique which can reduce the Vth of the NMOS Diode when it is ON and increase
the Vth when the NMOS Diode is reverse biased then the losses can be reduced to a
lar
large
ge extent. The threshold voltage of a NMOS is given by the below mentioned
equation 2.2.3 where the VSB potential and the surface potential Phi decides the
instantaneous
nstantaneous value of the Vth [7
[7].
].

In the schematic Fig 2.2.1 the body of the diode is connected ttoo the drain of the
NMOS along with the gate. So now the VSB can be given by the difference between
the Vin and Vload. As the VLM increases above VBN ,,VOP reduces and at a point
becomes negative reducing the Vth value. Now for positive values of Vin the Vth
reduces thereby reducing the Forward losses (Fig 2.2.2).

Also as the VLM decreases in the negative half cycle, the VOP increases and become
positive and thereby increases the instantaneous Vth thereby reducing reverse leakage.
So lookin
lookingg at the overall picture we can state that the Vth will be modulated by the
bulk to drain connection easily. The concept can also be explained by the Fig 2.2.2. It
shows the graph of Vin compared with Vload and also the plot of Vth with time. In the
region before t1 the Vin is less than Vload (OFF Region) the instantaneous Vth will be
increase as the VSB increases in this region.

(2.2.3)

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Texas Tech University, Ravindranath Shrivastava, August 2012

Fig 2.2.1: Bulk Modulation NMOS diode with its gate and bulk terminal connected to
the drain.

Now after the region t1 the as shown in the Fig 2.2.2, the VSB starts to become less and
reduces making the Vth less. This can observe in the 2nd graph in the same figure. So
this in turn increases the forward current of the diode.

Fig 2.2.2: Modulation of Vth in above circuit when the input voltage varies. We can
see the decrease in the Vth value as Vin increase beyond Vload.

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Texas Tech University, Ravindranath Shrivastava, August 2012

Now the working of the diode can also be explained by using the actual structure of
the diode. Looking at the Fig 2.3.1 we can see that the NMOS diode body terminal (p
type) is connected to the drain. In forward biased condition the Vdrain is higher than
the Vsource. If basically the Vbody is at higher potential than the Vsource leading to
internal conduction of the P (body)-N (source) diode. Also the channel is conducting
at the same time leading to increase in total forward current.

Now when the Vdrain is less than Vsource, then the P (body)-N (source) diode is
reversed biased leading to reduction in the leakage. But in the case if the body
terminal is not shorted to the drain and instead shorted to gnd, then the internal diode
is reverse biased and the internal diode will still conduct as P(body) is at higher
potential compared to the N(source) leading to some leakage. This leakage will result
in losing some charge from the Co capacitor during the negative half cycle. So this can
be avoided by shorting the body terminal to the drain.

2.3 PMOS Diode instead of NMOS Diode

Now in order to make sure that the bulk modulation works when the Layout of the
diode is being done, the body (p) has to be isolated from the rest of the substrate. The
P-Substrate of a die is always connected to the GND, so now if the body region of a
NMOS diode is to be isolated from the rest of the substrate so that the body to drain
connection can be made, we are required to use double well (See Fig 2.3.1). So in
order to do the isolation between P-Substrate and the Body of the NMOS, the Layout
of bulk connected NMOS Diode requires an N-Well be implanted inside the p-
substrate and then a P-Well is implanted inside the N Well for isolation between the
substrate (p) and body (p). This requires the use some special process and 0.6u process
does not provide the facility of double well, but allows a single well. Instead we use
PMOS in a Bulk-Drain connection as shown in Fig 2.3.2. The Bulk Modulation
scheme still holds true for PMOS.

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Internal Diode

P Well
N Well

P Substrate

Fig 2.3.1: The vertical cross section of the Bulk Connected Forward Biased NMOS
Diode. The Internal Diode i.e. the Source (n+) and the Body (p) also conducts leading
to increase in forward current increasing output voltage.

Fig 2.3.2: The vertical cross section of the Bulk Connected Forward Biased PMOS
Diode. The Internal Diode i.e. the Drain (p-) and the Body (n) also conducts leading to
increase in forward current increasing output voltage.

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So here in this case of PMOS diode, a N Well is implanted inside the P-Substrate, as
body terminal of the PMOS is N. Now the same connection can be made. Also we can
see from the figure 2.3.2 the source is at higher potential compared to the body. Now
so the internal diode can easily conduct in the forward biased condition and is off in
the reverse biased condition.

Fig 2.3.3: PMOS diode with its bulk - gate terminal connected to the drain used in the
3-Stage Voltage Multiplier instead of NMOS Diode.

C
C

Fig 2.3.4: The schematic of a single stage voltage doubler based on the Dickson’s
Charge Pump design.

The above figure 2.3.4 shows a single stage Dickson's Charge pump which is also
called as the voltage doubler. The input is a sinusoidal signal, in our case a 27.17MHz
RF Signal, which needs to be rectified and converted into DC. During the negative
half cycle of the signal the D1 conducts and D2 is OFF. So the capacitor C1 charges to
Vm in this cycle. Now when Vin positive, the Diode D1 is OFF and D2 is ON. Now
the current flows through C1-D2 to C2. Now C1 is already charged to Vm and the
Vin's peak voltage is Vm. So the capacitor C2 charges to 2Vm.

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2.4 PMOS Diode – 3-Stage Voltage Multiplier


The voltage doubler given in Fig 2.3.4 can be extended to 3 stages to get a higher
boosting power. So 2 stages can give a gain of 4, and 3 stages can give a gain of 6.
The Fig 2.4.1 shows the schematic of the 3 stage voltage multiplier which just 3 stages
of Fig 2.3.4 in cascade.

Fig 2.4.1: 3-Stage Voltage Multiplier: Each stage contains 2 diodes and 2 Caps. The
Caps are implemented using PMOS Caps so that we get value as large as 100pF on
Chip. The Diodes are basically PMOS Drain-Bulk Connected Diodes.

Working: The 2 figures show the working of the Multiplier during the Positive and
Negative Input Voltage Cycle.

Fig 2.4.2: Negative Half: The diode D1 is ON and D2 is OFF so current flows as
shown below and Charges C1 to Vin peak i.e. Vm.

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During the negative half cycle and plus the positive half cycle, we already know that
the C2 charges to 2Vm. Now in the next negative half cycle, the D3 is ON and D4 is
OFF. So the capacitor C3 charges to 2Vm + Vm = 3Vm. Also the charge in the
capacitor C1 of the 1st stage gets replenished to Vm.

During the positive half cycle of the waveform, the Diodes D4 is ON and Diodes D3 is
OFF. So the capacitor charges to 3Vm + Vm = 4Vm. Also the charge of the capacitor
C2 is replenished to 2Vm. This process goes on and on charging the Capacitor Cload
to 6Vm. Now do take into consideration that the charges across each capacitor is
assumed to be multiples of Vm. But in real cases scenario, the complete charge is
comparatively less due to diode drop and other non idealities. Also we observe that
there is no load resistor across the load capacitor. So if a load is present than during
the negative half cycle the Cload will be providing charge to Rload causing drop in
potential across the Cload.

Fig 2.4.3: Positive Half: D1 is OFF and D2 is ON and C1 is already charged to Vm is


previous half. So C1 and Vin both charge the Cap C2 to 2Vm.

The circuit mentioned in figure 2.4.4. has the 3-stage charge pump with ‘PMOS
diodes’ and load resistance. Also the capacitors C1 to C5 are ON-Chip capacitors
made by using PMOS Capacitor as shown in Figure 2.4.5. The Sizing of the PMOS
diode and PMOS Caps has to be chosen carefully so that it fits comfortably on the die.

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If the next stage is the Charge Pump (MPVD) and this along with the 3-Stage Voltage
Multiplier are to be inserted on the same die, then the capacitors of the MPVD should
be just kept external caps due to Die Area concerns.

Fig 2.4.4: The actual schematic of the 3 Stage Voltage Multiplier with PMOS used as
diodes.

Fig 2.4.5: The PMOS Capacitance schematic with terminal marked.

2.5 Input Voltage Boosting using LC Network

The voltage of the AC waveform at the input of the Voltage Multiplier is less
compared to the turn on voltage of the diode when input power is as low as -21dBm.
Now if somehow this voltage can be boosted than it becomes easier to turn on the
diodes. The boosting is done using a series capacitor and parallel inductor at the input
of the Voltage Multiplier as shown in the Fig 2.5.1. The Q is of the inductor is a very

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important parameter which decides how much of the voltage can be boosted. For the
calculation of the LC values we use the basic formulae for resonance [8].

R
fQ =
, SL √U V
(2.5.1)

And the Voltage at the output of the LC network is given by:


R U
V>) = W V'
G V
(2.5.2)

Rs - Series resistance of the inductor


Vs - Input voltage to the LC Network
Vout - Output voltage of the LC network and the input voltage to the Voltage
Multiplier

LC
Voltage
Boosting

Fig 2.5.1: The cadence schematic of the 3 stage multiplier using the LC resonant
circuit connected at the input for voltage boosting. Also the LC parallel resonant tank
used at the input of the circuit to boost the voltage at the actual input of the multiplier.

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Fig 2.5.2: The waveform at the input of the 3 Stage Multiplier circuit block boosted
from 257mVpp to 600mVpp.

Fig 2.5.3: The waveform at the input of the 3 Stage Multiplier circuit block boosted
from 344mVpp to 811mVpp.

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2.6 Battery Charging using 5 Stage Voltage Multiplier

Voltage Multiplier – 5 Stages of Charge Pump


Below shown is the schematic of a Charge Pump Voltage Doublers having 5 stages.
This charge pump is basically single stage in fig 2.3.4 arranged in cascade. The output
voltage (ideally) of this circuit is linearly proportional to the number of stages. The Fig
2.6.1 shown cell is connected in up to 5 stages. Also the capacitors used to store
charge are implemented using PMOS capacitor. In order to use PMOS as a capacitor,
the gate terminal is used as the positive terminal and the body, drain and source is
shorted and used as negative terminal. The size of the PMOS capacitor is set to
1m/1.05u. The sizes of the PMOS diode D2 is set to 180u/1u. The input power is an
AC signal of 27.12MHz and the power is varied from 7dBm to -21dBm and the output
voltage is recorded. Here one think has to be noted that the Cload is basically a battery
with 500pF of capacitance and Rload is disconnected from the circuit.

Fig 2.6.2: 5 Stage Voltage Multiplier with Rload disconnected from the rest of the
circuit in order to simulated battery charging

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Fig 2.6.2: Input power = -21 to -27dBm, Cload – 500pF, NMOS Size –90u/1u, NMOS
Diodes used. In this simulation NMOS diodes where used unlike the ones shown in
Fig 2.6.1

The Vout - 650mV for Pin - -27dBm with charging time equals to 50ms
The Vout - 700mV for Pin - -24dBm with charging time equals to 50ms
The Vout - 750mV for Pin - -21dBm with charging time equals to 50ms

Fig 2.6.3: Input power = -21 dBm, Cload – 500pF, PMOS Size –180u/1u, Vripple –
9.94mVpp, In this simulation NMOS diodes where used.

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Fig 2.6.5: Input power = -21 to -27dBm, Cload – 500pF, NMOS Size – 90u/1u, PMOS
– 2*NMOS
The Vout - 600mV for Pin - -27dBm with charging time equals to 80ms +
The Vout - 600mV for Pin - -24dBm with charging time equals to 70ms
The Vout - 600mV for Pin - -21dBm with charging time equals to 50ms

Fig 2.6.6: Input power = -27dBm, Load Resistance – 10K, Cload – 500pF, NMOS
Size – 90u/1u, PMOS – 2*NMOS

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2.7 Simulations Results – 3-Stage Voltage Multiplier


The PCE of the Voltage Multiplier increases with increase in input power (see figure
2.7.1). Also the PCE is low for low input power as the Pout is comparable to the losses
in the multiplier. Also as the load resistance decreases, i.e. the load current increases
the PCE drops due large charge being lost to the load. But also for large load
resistance, like 100K, the losses are comparable to the load current and diode current.
So the power delivered by a single diode becomes comparable to the losses in the
diode. 10K load gives us the most efficiency. Also after some input power, mostly
around 10dBm, the PCE starts to saturate as the Pin increases.

100
Power Conversion Efficiency

10
Rload -
10K
Rload -
1 500
Rload -
100K

0.1
-20 -10 0 10 20 30
Input Power (dBm)

Fig 2.7.1: Input Power vs PCE: We can see that for the PMOS Diode Size selected
the PCE is maximum for load resistance around 10K Ohms. We also observe that as
the Input power increases the PCE improves but saturates after Pin > 10dBm

Now looking at the figure 2.7.2 we can say that the Vout is very a linear function of
Pin. Fig 2.7.3 shows the optimum load current for different input power. As the load
current increases beyond a certain point the PCE drops. Also lower load current can
lead to low PCE.

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Texas Tech University, Ravindranath Shrivastava, August 2012

For Pin - 0dBm the load around 200uA will give us maximum PCE i.e. above 40%.
For Pin - 6dBm the load around 500uA will give us maximum PCE i.e. above 60%
PCE can go as high as 80% is the Pin is more than 10dBm and the load current is
1mA.

10
Output Voltage (Vdc)

Rload - 500
1
Rload - 1K
Rload - 10K
0.1 Rload - 100K

0.01
-20 -10 0 10 20 30
Input Power (dBm)

Fig 2.7.2: Input Power vs Output Voltage: As the load current reduces the output
voltage does increase as seen in the 2nd graph.

70
Power Conversion Efficiency

60

50

40 Pin - 0dBm
Pin - 3dBm
30
Pin - 6dBm
20

10

0
000.0E+0 200.0E-6 400.0E-6 600.0E-6 800.0E-6 1.0E-3
Load Current (A)

Fig 2.7.3: Lower load current leads to reduction in PCE. Load Currents ranging from
200uA to 600uA provide good PCE.

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Fig 2.7.4: The Transient Response of the 3 Stage Voltage Multiplier done with 10 K
load and input power as low as -9dBm. VDC above 100mV can be harvested with
10.3uA load current. If N harvesters are used in parallel then current as high as
N*10.3uA can be generated.

Now the W/L is around 2880/1 and this leads to increase in Energy Harvesting
capability of the diode. The Pin is around -9dBm and the Vout goes as high 103mV in
the presence of load resistance equals to 10K. So it shows that if the W/L is not a
constraint then Energy Harvesting capability can be improved. Any PMOS diode
becomes bigger than 2880/1, it is not preferable due to chip area constraints.

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CHAPTER 3
2-STAGE MULTIPHASE CHARGE PUMP

In the systems like implantable sensors the energy is harvested from various types of
energy harvesters as mentioned in the previous chapters. The output voltage of these
energy harvesters is mostly in the range of 200mV to 800mV and rarely does it go
above 1 Volt. Such low supply voltages make it difficult to power up devices like the
implantable sensors, the signal conditioning circuits for the sensors and the Wireless
Circuitry. So the need for a voltage booster arises. The Switching DC-DC Boost
Converter can be used to boost the voltage to a higher supply voltage and can be done
very efficiently. But these converters do require external components, like the inductor
(energy storing element) and output capacitor for filtering out the ripple and to store
enough charge. So we can use a charge pump to boost up the power supply up to a
significant voltage when the input supply voltage from the energy harvester is very
low.

3.1 Need for Voltage Regulation and Voltage Boosting using


MVPD
- The load may vary over time depending on the state of the sensor

- The line voltage may also vary depending upon the alignment of the TX/RX
coil and the distance between the coils.

- TX can be designed to run on low power resulting in less Vdc at the output of
the Voltage Multiplier.

- Low supply voltage cannot power up the implantable sensors, the signal
conditioning circuits for the sensor and the Wireless Circuitry

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Shrivastava,, August 2012

-
- Fig 3.1: A Basic Linear Regulator implemented using an OPAMP and Power
MOSFET. The main problem with this is, it has drop out voltage across
MOSFET and if the Vin < Vdd then boosting Vin is not possible

3.1.1 Disadvantages of using a Linear R


Regulator
egulator for Voltage Regulation
Linear Regulators have known to have the least output ripple and are very easy to
design com
compared
pared to their switching counter parts. But they have inherent
disadvantages. They main issue in using a Linear Regulator, as shown in Fig 3.1, is
that they have a Drop Out Voltage across the Power MOS as shown in the figure. So
the Vdd, which is regulated output voltage is lower than the Input Voltage to the
regulator i.e. Vrect here. Linear are not able to boost the input voltage also. In this
application the linear regulator can have input voltage as low as 0.5 V which basically
cannot be boost up to any usable supply voltage using this regulator. So here arises the
need to have a boost converter which can boost low input voltages. In energy
harvesting application we can have conditions when the input power is less and so the
boosting could be necessary. So for that we choose a 2 stage charge pump which can
have a gain as high as 4.

3.2 Analysis and Design: Multi Phase Voltage Doubler (MVPD) –


Charge Pump

Charge pumps do not require an external inductor as the energy storing element.
Capacitors are most
mostly
ly used as the energy storing element. The charge pump proposed

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by Dickson was the 1st of its kind were the capacitors are used as the energy storing
element. The number of stages of the charge pump decides the gain of the charge
pump. In the Dickson’s Charge Pump the 2 capacitor are used per stage and which
may lead to large on chip area for the same amount of gain. Instead we use the Multi
Phase Voltage Doubler (MPVD) proposed by Starzyk [13] proposes a design which
basically provides larger gain compared to older charge pump designs with less
number of capacitors. The MPVD can provide a gain of 2Y , where N is the number of
stages. Each stage has only one capacitor and there is an extra output capacitor. So for
an N stage MPVD we have N+1 number capacitors which can be lead to saving lot of
area on chip. The charge also has 4 power switches per stage, so N a Stage MPVD will
have 4N switches. This charge pump can be used any application which requires a
much input DC voltage to be boosted and be used a power supply. Now if this Charge
Pump if is to be used as a regulator, a feedback voltage regulation mechanism needs to
be in place.

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Fig 3.2.1: PWM Control: Main Block Diagram of the 2 Stage Multi Phase Charge
Pump along with the voltage controlled feedback loop.

The paper published by Yuen-Haw Change [12] suggests a method to regulate the
output voltage by current mode control and PWM to be used. This technique is shown
in the figure 3.2.1 and it shows that a current sense resistor is used to sense the load
current and the Pulse Width of the switching waveform is controlled according to the
load conditions. The above design has a current sense resistor which will sense the
amount of load current and generate Vsense proportional to the load current. The Error
Amplifier will generate a signal which will be proportional to the Vsense called
Verror. The Verror is given to a comparator which compares it a saw tooth waveform
and generate a pulse width modulated switching waveform signal. The pulse width is
proportional to the load current so that the output voltage is maintained at a constant
output voltage.

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Vout
S5 S6 4 Volt DC
S1 S2 Cout Rload

Vin
1 Volt DC
C1 C2
S7 S8
S4 S3

VCC
Vsense
S1

R current sense
S2 Control LPF
Control . Clock Generation Voltage
Signals for . CLK Error Amplifier
MOS Switches . Circuitry
.
S8
Controlling
Switching Vref
Frequency

Fig 3.2.2: Frequency Regulation: The main block diagram of Multi Phase Voltage
Doubler (MVPD) as a Charge Pump with Frequency control technique implemented
using a VCO.

One of the drawback of using the above method in our design is that the load current
when varied over a wide range, say from 5mA to as low as 100uA, it becomes difficult
to control the pulse width of the gate control signal. Also as the switching frequency is
fixed the efficiency will be very low under low load or very high load conditions. It
has demonstrated by Fengjing Qiu [14] that the efficiency of the charge pump is very
much depending upon choosing the right switching frequency for the right load. So we
propose a frequency control technique for the feedback control system which instead
of using PWM uses Frequency Control to regulate the output voltage.

The Frequency Regulation works on the principle that higher the switching frequency,
higher will be charge that can be delivered to the output capacitor. For low load
conditions the switching frequency doesn’t have to very high to maintain Vout =
4 Vin. But as the load current goes up, the Vout will start to drop as only finite
amount of charge will be delivered to the output capacitor at low switching frequency.

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So feedback will sense the increase in the load current and speed up the clock to make
sure the output voltage does not drop. The Rsense resistor is present to sense the load
current and generates a Vsense and it will be amplified by the Error Amplifier. A
VCO is present in the feedback loop system which is driven a control voltage. The
control voltage is basically the Error Voltage generated by the Error Amplifier. The
Error Voltage is basically proportional to the load current and as the load current
increases the control voltage or the error signal will increase, increasing the switching
frequency of the charge pump bringing back the Vout to regulated voltage.

3.3 Main Power Stage

This charge pump has one capacitor and 4 power switches per stage and has an ideal
DC gain of 2M where n stands for the number of stages. The capacitors C1 and C2 are
on chip and the output capacitor Cout is off chip. The on chip capacitors were PMOS
capacitors instead of capacitors made out of poly1-ploy2. PMOS capacitors are used
so that higher capacitances can be achieved without using too much area on the die.
The above block diagram represents a 2 stage multiphase charge pump which can be
used to obtain a gain of 4 (ideally). The switches are NMOS and PMOS switch
implemented on chip itself. Every stage contains 4 switches and along with a single
capacitor per stage. As shown in the below shown waveforms in figure 3.3.3 to 3.3.7
show the working of the charge pump over a period of a complete cycle. Let’s assume
that input voltage is set to a voltage of Vm.

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Texas Tech University, Ravindranath Shrivastava, August 2012

Fig 3.3.1: The Cadence schematic of the main power stage of the charge pump. The
upper part shows the main CMOS switches, Dead Time Control block, the Non
Overlapping clock generation circuitry and CMOS switch drivers

Fig 3.3.2: The main power stage of the charge pump represented using ideal switches

• Interval T1: The switches S2-S4 are initially closed and S1 & S3 are open. So
the current flows from input through S2- S4 and charges the capacitor C1
to Vm.

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Fig 3.3.3: Phase 1 – MPVD

• Interval T2: The switches S2-S4 are closed and S1 & S3 are open and the
current flows from input through C1 to the 2nd stage. In the 2nd stage the S6-S7
are open and S5-S8 are closed. So the current flows from the input through C1
and C2 charging C2 to 2Vm.

Fig 3.3.4: Phase 2 – MPVD

• Interval T3: The switches S1-S3 are open and S2 & S4 are closed. So the
current flows from input through S2- S4 and charges the capacitor C1 to Vm
once again. Also the all the switches in the 2nd stage are open so that C2 can
retain its charge.

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Fig 3.3.5: Phase 3 – MPVD

• Interval T4: By this time C1 and C2 are charged to Vm and 2Vm. In this
interval the S1-S3 and S5-S8 are closed and the rest are open. So the output
capacitor is connected to the charge pump and is charged by the input, C1 and
C2 to 4Vm. As the input voltage is Vm and C1 and C2 have Vm and 2Vm
stored in them, the output capacitor is charged to 4Vm (ideally).

Fig 3.3.6: Phase 4 – MPVD

• This keeps on repeating so that the voltage across Cout is maintained to 4Vm.

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Fig 3.3.7: The waveform of the above mentioned circuit. The explanation for the
waveform is given above.

As we can see from the S1-S3 and S2-S4 are closed alternately, so the waveform for
S2-S4 should be the inverted version of S1-S3. Also the switches S6-S7 and S5-S8 are
only open during 1 out of all 4 phases. The switches S1-S3 are open in the T2 phase
and the switches S5-S8 are open during the T4 phase. So the clocks for the 2nd stage
can be generated using the main clock i.e. S1 which we will see later.

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Fig 3.3.8: The actual waveforms to the switches S1-S8. Due to pin parasitic elements,
high frequency usage the switching waveforms get distorted.

3.4 Circuit Analysis for MPVD


The above MPVD circuit can be analyzed with in the 4 phases described above. Now
we will analyze the circuit for each phase and accordingly derive design equations for
the MPVD. The equations described in Y.H. Chang’s paper can also be used for
getting a rough estimate of the component values.

3.4.1 Stability:

In the paper published by Y.H. Chang [14] they have proven stability criteria of the 2
stage MPVD by deriving the location of the poles of the power stage.

R
Output Pole: p1 = −
G[ ∗ V8
(3.4.1)

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Texas Tech University, Ravindranath Shrivastava, August 2012

Co is the output capacitor of the charge pump.


Rl – load resistance of the charge pump

The pole p1 is the dominant pole of the system which decides the unity gain
frequency. The other two poles p2 and p3 are located at very high frequencies are not
of much importance provided Co is selected comparatively higher than C1 and C2.
The value of the Co is important factor deciding the stability of the Charge Pump. The
non dominant poles for the charge pump are given by [14]:

] – √_
p2 = −
`GV
(3.4.2)
]? √_
p2 = −
`GV
(3.4.3)

R = rc + 2 ∗ rs
rc – Series resistance of the on chip capacitors
rs – Series ON Resistance of the switches

C is the capacitors used as energy storage devices. Here they are assumed to be
capacitances of the same value. The value of the C is comparatively very small than
Cl. Also as the sizes of the MOSFET switches is pretty large their ON Resistance is
also very small making the poles p1 and p2 to be present at very high frequency. Also
suggested by Y.H. Chang [14] in their paper there is a simple condition to be met in
order to make the charge pump stable and to make the poles p2 and p3 very high
frequency poles.

R U C ≫ 8 R C (3.4.4)
R
f' >
G[ V8
(3.4.5)

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3.4.2 Power Conversion Efficiency

The input/output power for this MPVD can be easily computed from the below
mentioned equations,
PLM = VLM ILM
V VLM 16 VLM
,
P>) = V I = 4 VLM I = 4 VLM d e = 4 VLM d4 e=
RU RU RU

The efficiency of the MVVD can thus be given by the ratio of Output Power to the
Input Power.
ijk
gh
789: Rn Igh
η= = =
l[
7gh Igh mgh G[ mgh
(3.4.6)

3.5 PMOS Capacitor

The PMOS is used as a capacitor in this device. The drain, source and body is
connected together and used as the negative terminal and the gate of the device is used
as the positive terminal. The Cgs of the PMOS is the main capacitor including in the
Cgd and Cgb. Now as the drain and source terminals are shorted together the Vds = 0,
Vgs > 0 and Vgs – Vth > Vds. So the device is mostly operating in the triode region.
Now if the device is operating in the triode region then the capacitances are given by:

C&' = CoOp W + ½ Cqr W L


C& = CoEp W + ½ Cqr W L
C&s = CoPp Ltuu

Where CoOp , CoEp and CoPp are the overlap capacitances due to overlap between gate
poly and source, drain and substrate areas respectively. So when the gate is used the

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Texas Tech University, Ravindranath Shrivastava, August 2012

one terminal of the capacitor and the source, drain and body shorted is used as another
terminal the total capacitance is the sum of all the three capacitances mentioned above.

C q wU = C&' + C& + C&s


xyzy{| = } =x~€ + x~€ A + x~‚€ |ƒ„„ + xz } | (3.5.1)

The capacitance obtained by using this technique can lead capacitances as large as
300pF possible on chip just by using PMOS in manner shown in the figure 3.5.3.

3.5.1 Variation of Capacitance versus Gate Voltage


The capacitance of the PMOS-CAP device also varies with respect to the gate voltage.
It is also observed that at particular voltage the capacitance becomes constant
irrespective to the variation in voltage. It is also observed that the breakdown voltage
of the PMOS is mostly 13.95 volts. But care should be taken that the gate voltage does
not exceed 5 volts. Even though the equation does not suggests a relationship between
the Gate Voltage and Total Capacitance, there still dependence on the gate voltage and
the total capacitance. Leff is also dependent on the gate voltage and it does increase
with increase in gate voltage. But after a particular voltage approximately equal to Vth
the Capacitance becomes independent of gate of voltage.

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Fig 3.5.1: The graph shows the relationship between the values of Total Capacitance
seen at the gate when the gate voltage is varied.

3.5.2 Variation of Capacitance versus PMOS


PMOS-CAP
CAP size

The voltage app


applied
lied to the Gate of the PMOS
PMOS--Cap
Cap is constant 1 volt and the W/L ratio
of the PMOS is varied. It is observed that large value of Capacitance can be attained
using this technique. Also it is observed that a linear relationship between the
capacitance and the W/L ratio.

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Capacitance Variation vs W/L Ratio


350

300

250

200
Capacitance (pF)
150

100

50

0
0 20000 40000 60000 80000 100000 120000
W/L Ratio
Capacitance Variation vs W/L Ratio

Fig 3.5.2: The relationship between the Capacitance and W/L Ratio.

Fig 3.5.3: The PMOS Capacitance schematic with terminal marked.

3.6 Non Overlapping Clock Generator

Need for Non – Overlapping clocks: In the first stage of the power stage, a short
circuit path to ground can develop through S1 and S4 due to usage of overlapping
clocks. Below is an example of overlapping clocks where the switch S1 and S2 are

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ON for few nanoseconds leading to the input supply to be connected to ground for that
short period of time. This can lead to short circuit condition leading to passage of large
amount of current through switches S1 and S4 in turn damaging the switches over
time. Also it leads to losing power form the input power source and thus resulting is
reduction in the efficiency of the convertor.

Fig 3.6.1: For the small time interval ∆T as described below, the switches S1 and
S4 can be simultaneously ON for a short period of time connecting the input to
ground through S1-S4 creating short circuit and damaging the power switches.

Fig 3.6.2: Waveform explaining the difference between Overlapping Clock and
Non Overlapping clock.

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In the below shown figure, the gate waveforms of the switches S1 and S4 are
shown when the clocks are overlapping and for a period of ∆T the switch S1 is not
completely OFF and switch S4 turns ON leading to short circuit through S1 and
S4. The same can be said about the switches S2 and S3. The below mentioned
circuit is used to generate the Non-Overlapping clocks for the switches S1 and S2
by using NOR Gates and Not gates.

Fig 3.6.3: The schematic of the circuit used to generate a Non-Overlapping


waveform as shown the above [4].

3.7 Clock Generation Circuitry using D Flip Flop

As explained in the previous sections 3.3 a four phase clock is required to be


generated to for the switches of the 2 stages of the charge pump. The 4 phase clocks
for the switches are shown below in the waveform diagram. The S1-S3 is out of phase
of S2-S4. Theses clocks can be generated using the schematic given in Fig 3.6.3. Now
we need to generate the clocks S6-S7 and S5-S8 as shown below. We can notice that
these 2 clocks are of half the frequency compared to S1 with different ON period. So
now the 1st step is to divide the clocks S1 by 2.

For this we use the D-Flip-Flop circuitry with QB output of the Flip Flop shorted to
the D input and the S1 is connected to the clock terminal of the D Flip Flop (Fig
3.7.2). This circuitry will generate a clock at the output terminal which is at half the
frequency of S1 clock. The divided by 2 clock is shown in the figure 3.7.3 and the
inverted version of it is also shown. The inverted version of the divided clock is

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generated at the QB terminal of the Flip Flop. The clocks S6-S7 is generated by
passing the clock S1 and Q through an AND Gate. Similarly the clock S5-S8 can be
generated in the same manner by passing QB and S1 through another AND Gate.

QB

Fig 3.7.1: The switching waveform for the charge pump and the output of the D Flip
Flop circuitry as shown in the Fig 3.7.2

The schematic shown in the Fig 3.7.3 shows the cadence schematic of the same
circuitry shown in the Fig 3.7.2. The 2 latches are marked which when connected in
series makes up the D Flip Flop. The Flip Flop is connected in the same manner as
shown in Fig 3.7.2. and the clocks for the 2nd stage of the charge pump are generated.

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Fig 3.7.2: a) The D Flip Flop is used to divide the CLK by half. The AND Gate are
used to generate the clocks for the 2nd Stage of the Charge Pump. b) The 1st Stage
requires the generation non-overlapping clocks, so simple circuit proposed in is used
to generate it. Non Overlapping CLKs help avoid Switch S1 & S4 turned ON at the
same time which may lead to reduction in Efficiency.

Q
D
S

QB

CL S
CL
Latch 1 Latch 2

Fig 3.7.3: The schematics of the D Flip Flop which is used to divide the switching
frequency by 2.

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CHAPTER 4
DESIGN OF FEEDBACK CONTROL FOR CHARGE PUMP
4.1 Introduction to Feedback Control – Frequency Control

The charge pump output will be used to provide supply voltage to other wireless
sensor circuitry and the just any other voltage regulator the output of the charge pumps
needs to be regulated to a desired output voltage. As mentioned in the Section 1 of
chapter 3 there are 2 ways of implementing the feedback control mechanism, one by
controlling the duty cycle of the switching gate pulses and the other ways is to control
the switching frequency. In both the techniques mentioned, Error Amplifier plays an
important role in detecting the load current.

Fig 4.1.1: The feedback loop of the Charge Pump. The Vref decides the output voltage
of the charge pump and it can be tweaked to change the output voltage of the charge
pump.

In our design the output load current of the charge pump is monitored by a current
sense resistor. The voltage across the current sense resistor fed into this Error

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Amplifier and the gain of the Amplifier is decided by the Feedback Resistor as show
in the fig 4.1.1. The Error Amplifier generates a Control Voltage which is proportional
to the Vsense voltage. The Control Voltage drives the Vcontrol terminal of the VCO.
Due to increase in the load current of the charge pump the output voltage of the charge
pump will drop, as the output capacitor of the charge pump can only provide some
finite amount of charge. As the load current increases, the Vsense voltage across the
Rsense resistor also increases. Then in turn the Vcontrol voltage also increase by a
proportional value as Iload increases increasing the switching frequency of the VCO.
As the switching frequency of the VCO increases the Vout of the charge pump goes
back to the original voltage level thereby regulating the Vout.

4.2 OPAMP Design – Error Amplifier

While design the OPAMP for this application there are few design consideration that
need to be taken into account before we proceed further to chose the topology for the
OPAMP.

Design Consideration for the OPAMP for Low Power Charge Pump Application
• Large Open Loop gain makes sure that the Error Amplifier will be highly
sensitive to the slightest change in output current of the OPAMP.
• In the Frequency Control configuration, the VCO control voltage spans over a
large range and so the output swing of the OPAMP needs to be large too.
• In order to monitor a large range of output current of the charge pump, the CM
input voltage range of the OPAMP needs to be large also.
• The gain of the OPAMP at the switching frequency of the charge pump should
be negligible so that it does not amplify the ripples present in the DC at the
output of the charge pump.
• The charge pump is designed for low power applications, with typical output
current of 5mA, the current consumption of the OPAMP has to be maintained
as low as possible.

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4.2.1 Telescopic Cascode OPAMP

The Telescopic Configuration is known for its low power high gain property. The high
gain of the Telescopic Cascode is derived from the fact that the Rout of the device is
very high leading large gain given by:

Av tBt'‡SL‡ = gmR ∗ ˆ‰gmR ∗ rqYR ∗ rqYŠ ‹||‰gmn ∗ rqYn ∗ rqY` ‹


Assuming gmS = gmM = gm
r,
Av = gm ∗ gm ∗
tBt'‡SL‡
2
&Žk Qk8
Av tBt'‡SL‡ =
,
(4.2.0)

Fig 4.2.1.1: The schematic of a Telescopic Folded Cascode OPAMP which has a
high Open Loop gain given by the gmR ∗ ˆ‰gmR ∗ rqYR ∗ rqYŠ ‹||‰gmn ∗ rqYn ∗
rqY` ‹ .

But the telescopic cascade has its draw backs too. It is difficult to maintain the high
output swing in the Telescopic OPAMP without pushing the output stage devices out

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of saturation. As shown in the figure 4.2.1.1 of the Telescopic Cascode, the gain of the
OPAMP is very high and it can be achieved using very low supply current. It is quite
difficult to bias the cascade because of the many numbers of devices present between
GND and VDD. The device Mcs is a current source which is required to maintain the
required a constant current drive. But it consumes its own head room contributing to
the biasing problems. Biasing can still be resolved by careful simulations, but the
output swing is limited in the case due to the presence of the current source because at
any cost the output swing should not fall because a certain value of VqEŠ + VqE, +
VVO . The output swing of the OPAMP is given by 2 ∗ VEE – =VqER + VqE] + VVO_ +
|VqE_ | + |VqE |A‘ which shows that it puts a limitation on the output swing of the
OPAMP.

4.2.2 Rail to Rail Folded Cascode OPAMP

Telescopic Cascode can be replaced by the Folded Cascode configuration so that the
current source at the output stage can be removed and the input can be isolated from
the output circuitry. Below in Figure 4.2.2.1 showing the input circuitry of the Rail to
Rail Folded Cascode OPAMP which has a very wide input common mode range. Also
it makes sure that input stage is isolated from the output stage and it does not affect the
output swing.

The Rail to Rail Input stage is made up of the N-Input Differential Pair in parallel with
a P-Input Differential pair both with their independent current sources. The N input
differential pair has a NMOS current source which decides the lower limit of the
common mode input voltage. The Turn ON voltage of the N pair is given
by VEO]='N)A + VoOYR . Any common mode input voltage less than this will drive the
M3 out of saturation turning off the N Pair. But in order that the OPAMP common
mode input can go below this limit we have P-Input differential pair in parallel. This
pair is driven by a PMOS current source between it and VDD. This P-Input pair can

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still remain in the saturation even if the input common mode voltage falls
below VEO]='N)A + VoOYR . For the P-Input stage the Turn ON or the upper limit of
the VinV’ is given by VEE − “ VEOR`='N)A “ − “ VoOij “. For any input greater than this
turns off M18 and as the current source M18 driven out of saturation eventually
turning off the P-Input Differential Pair. But for the common mode input greater than
VEE − “ VEO='N)A “ − “ VoOij “ the N-Input pair is still ON and provides the required
gain. So this increases the common mode input voltage swing for the device.

Also the effective gmtuu of the input stage also is dependent on the common mode
input voltage. As VLMV’ is at the center between VDD and GND both the input stages
are ON and so the equivalent gmtuu is 2gm (considering that the gm of both the pairs is
the same). But when either the N-Pair or the P-Pair are OFF the effective gm is less
than 2gm, mostly equal to gm.

Fig 4.2.2.1: The Rail to Rail input stage for the Folded Cascode OPAMP makes sure
that the input swing can be increased up to the Rails. Also the Folded configuration
isolates the input stage from the output stage.

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4.2.2.1 Variation in the Tran-conductance of the Rail to Rail Input Stage

• GM = 2gm if Vin in certain range

• GM = gm if Vin above or below than range

Fig 4.2.2.2: The effective gm of the input pair of the OPAMP and the variation in its
value from gm-2gm-gm over a range of values of Vincm from 0 to VDD.

So this is one of the drawbacks of using PMOS/NMOS Rail to Rail input stage but the
advantages outweighs the drawbacks. Now this Rail to Rail stage can be applied to a
Double Cascode as shown below in figure 4.2.2.3

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Fig 4.2.2.3: The schematic of a Rail to Rail Double Folded Cascode OPAMP
The above figure shows the schematic of Rail – Rail Folded Cascode OPAMP which
can be very ideal for our application. The OPAMP gain is given by the below
mentioned equation:
ro, ro,
AvE>sBt VN'‡t = %gmM + gmS + ∗ ”gmM ∗ ||gmS ∗ •
2 2

The values of ro is comparatively less compared to previous circuit as the ro1 comes
in parallel with ro4 and also on the lower side ro10 comes in parallel with ro13
reducing the gain by few dBs. Assuming gmp = gmn = gm we can simplify the above
equation as:
Ÿ ¡ ¢—¡
{–—˜™šƒ x›œ—žƒ =
¡
(4.2.1)

But still as we use two input stage, as we explained earlier, the GM of the input is
mostly 2gm bringing the gain back to the same value as shown in the equation 4.2.1.
Also looking at the output node of the OPAMP we can see that the Rout and Cout will

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be comparatively higher than Resistance and parasitic capacitance at any other node.
So the Rout and Cout decide the dominant pole of this OPAMP. All the other poles
are situated at very high frequency making Rout*Cout as the deciding factor in the
stability of the OPAMP. Additional compensation capacitor can be avoided for
stability if the Rout is designed properly making the OPAMP self stabilizing. If a
larger gain is desired then there are 2 techniques that can be used to modify the above
design a) Cascode Gain Boosting b) Triple Cascode Configuration. Now the Gain
Boosting OPAMP, if designed properly, can provide you with a gain above 100dB
easily along with large bandwidth. But one of the main issues with it compensation
and very careful design and simulations are required to do design it. Rather it is much
simpler to modify the above design to a Folded Triple Cascode configuration with the
same Rail to Rail input stage.

4.2.3 Rail to Rail Folded Triple Cascode OPAMP for Gain Boosting

The triple cascade configuration was chosen for the main reason to get large gain out
of the OPAMP with a small quiescent current consumption as possible. The Triple
Cascode configuration as shown in Fig 4.2.3.1 does require many bias voltages which
do increase the complexity of biasing circuitry. The biasing circuitry can be designed
using a very simple circuitry consisting of PMOS and NMOS biased using a resistor.
The Triple Cascode Circuitry is shown in the Figure 4.2.3.1 which is very similar to
the previous configuration, expect to an additional PMOS and NMOS pair in upper
and lower output stage. The main problems arises with this configuration when
deciding the bias point for the PMOS and NMOS pair and to maintain them in
saturation state as the output swings above and below the output bias point. The
biasing is done in such a way that the Veff = Vgs − Vth of each device is not large
so that the devices do not turn off that easily. So for example the Veff of the M4/5 is
chosen to as low as 20mV and so on. So even if the output terminal swings the devices
barely turn off at the extreme point of the Rails. Later in the simulation results we will
see some more information how the devices where biased.

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Fig 4.2.3.1: The schematic of the Rail to Rail Triple Folded Cascode OPAMP

4.2.3.1 Analysis of the Triple Cascode configuration

The output resistance of the Triple Cascode is explained in the Fig 4.2.3.2 to Fig
4.2.3.4. Now from Figure 4.2.3.2 we can see that the device M1/2 comes is parallel
with M4/5. So the ro1 || r04 is the top most resistance and similarly r14 || r16 is present
at the bottom. Let breakdown the calculation of the Rout of the OPAMP into two
parallel resistances Rout1 and Rout2, where Rout1 is the resistance on the PMOS side
and Rout2 is resistance looking into the NMOS side. Let’s calculate each one of them
separately:

RoutR = Rout’R ∗ gm` ∗ ro` (4.2.2)

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Fig 4.2.3.2: The breakdown of the Rout resistance of the OPAMP. The Rout1 and
Rout2 resistance calculation is shown below.

In order to calculate Rout1 we will calculate Rout1’ first which the equivalent
resistance looking into the drain of device M6. The resistance Rout1’ looking into the
drain of given by (see fig 4.2.3.3)

Rout1′ = gm6 ∗ ro6 ∗ =ro1|| ro4A


Now substituting this in the equation 4.2.2 we get:
RoutR = gm6 ∗ ro6 ∗ =ro1|| ro4A ∗ gm` ∗ ro`
Assuming gmn = gm` = gmS and rqR = rqŠ = rq we get:
Q£
RoutR = gmS , ∗
,
(4.2.3)

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Similarly we can calculate the value of Rout2 using the same method to:
Q£
Rout , = gmM , ∗
,
(4.2.4)

Fig 4.2.3.3: The breakdown of the Rout1 resistance looking down into the PMOS load
of the OPAMP

Now the gain of the Rail to Rail Folded Cascode OPAMP is given by:
Av = %gmM + gmS + ∗ =R >)R ||Rout , A
Substituting the Rout1 and Rout2 in the above equation we get:
¢—§ ¢—§
{– = %Ÿ ¤ + Ÿ ¥+ ∗ ¦Ÿ ¤
¡
∗ || Ÿ ¥
¡
∗ ¨
¡ ¡
(4.2.4)

Assuming gmM = gmS = gm

Then the final gain of the amplifier is given by,

Av = =2 ∗ gmA ∗ ”gm2 ∗ •
ro3
4

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=Ÿ ¢— A§
{–©¢ª¥šƒ =
¡
(4.2.5)

Now comparing the equation 4.2.5 and equation 4.2.1 we can see gain of a Triple
Cascode OPAMP is of 3rd order making the gain very high. The difference between
the gains of the two OPAMP is given by:

%g ro +
2

Avdouble cascode db = 20 log « m ¬ = 40 log ¦ m ¨


g ro
2 2

%g ro +
3

AvTriple cascode db = 20 log « m ¬ = 60 log ¦ m ¨


g ro
2 2
Ÿ ¢—
{–y¢ª¥šƒ ›œ—žƒ ž™ − {–ž—˜™šƒ ›œ—žƒ ž™ = ¡€ š—Ÿ ¦ ¨
¡
(4.2.6)

So the gain of the triple Cascode is "20 log ¦ ¨ " higher than that of the previous
gm ro
2

OPAMP making the gain very high depending on the value of gm and ro.

Fig 4.2.3.3: The breakdown of the Rout2 resistance looking down into the NMOS
load of the OPAMP

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Shrivastava,, August 2012

4.2.3.2 Stability Analysis of Triple Cascode OPAMP - Pole Zero

Cascode configuration has the output pole as the Dominant pole deciding the BW of
the OPAMP. It can be seen later from the simulation results that the output pole will
be the dominant pole and it is easy to make the OPAMP stable with careful
simulations.

P1 =
1
=Cout ∗ Rout A
Cout = Parasitic capacitance at the output of the OPAMP
Rout = Output resistance of the OPAMP

4.2.4 Rail to Rail Folded Triple Cascode OPAMP – Simulation


Results
The below are some simulation results of the OPAMP performed on the Test Bench to
verify the performance of the OPAMP as designed. The OPAMP in figure 4.2.4.1 is
being tested for transient response with a sinusoidal input given at a particular
frequency.

Fig 4.2.4.1
4.2.4.1:: OPAMP connected in Non Inverting Configuration with a gain of 50. Rf
- 500M Ohms and R1 – 10M Ohms

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Figure 4.2.4.2 shows the input waveform given to the OPAMP connected in a Non
Inverting Conjuration with input voltage set to 20mVpp and Frequency set to 100Hz.
The gain of the OPAMP is set to 50 by using the resistors 500M and Rf and 10M as
R1 and setting the biasing conditions on both the terminals to 1.5 volts, midway
between rails. So the output waveform observed in the figure 4.2.4.3 shows that an
easily the OPAMP can provide the closed loop gain of 50 with an output of 1Vpp.

Waveform - Input
1.509
Amplitude (Volts)

1.504

1.499

1.494

1.489
1.09E-01 1.14E-01 1.19E-01 1.24E-01 1.29E-01 1.34E-01 1.39E-01
Time (sec)

Fig 4.2.4.2: Transient Response of the input given to the above test circuit.

Waveform - Output
2.1

1.9
Amplitude (Volts)

1.7

1.5

1.3

1.1

0.9
1.09E-01 1.14E-01 1.19E-01 1.24E-01 1.29E-01 1.34E-01 1.39E-01
Time (sec)

Fig 4.2.4.3: Transient Response of the OPAMP for the above Circuit.

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Let’s look at some DC simulation performed on the OPAMP and see if the devices are
biased properly so that they are completely ON. The upper devices M4/5 is biased
such that Veff is set to 20mV, M6/7 have Veff of 50mV and Veff of M8/9 is set to
61mV. The OPAMP is connected in a Non Inverting Unity gain configuration and the
input varies from GND to VDD and the output is also expected to swing from GND to
VDD. As we can see from the fig 4.2.4.5, which is the plot of the Vds voltages of all
the PMOS devices shown in the below mentioned figure, the devices are mostly ON
when the output terminal swings from GND to VDD. So we can conclude that the
devices are ON for the entire range of input voltage.

M4 M5

M6 M7

M8 M9

Fig 4.2.4.4: The biasing of the upper portion of the output stage of the Triple Cascode
OPAMP along with the operating points of the devices.

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Fig 4.2.4.5: The plot of the Vds voltages of M4/5, M6/7 and M8/9 devices of the
OPAMP when the input voltage is varied from 0 to VDD in a unity gain Non Inverting
Configuration.

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Frequency Response of the OPAMP

Fig 4.2.4.4: The gain and phas


phasee response of the OPAMP with the DC Gain of 101dB
and the unity gain bandwidth of 2.3MHz. The graph also shows the phase margin of
58 degree.

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Common Mode Rejection Ratio

CMRR @ 3Volts VDD


120
100
80
60
CMRR (dB)

40
20
0
-20
-40
1 10 100 1000 10000 100000 10000001000000010000000 1E+09
Frequency (Hz)

Fig 4.2.4.5: Plot of CMMR of the OPAMP. CMRR – 102dB

Power Supply Rejection Ratio

PSRR @ 3Volts VDD


160
140
120
100
PSRR (dB)

80
60
40
20
0
1 10 100 1000 10000 100000 10000001000000010000000 1E+09

Frequency (Hz)

Fig 4.2.4.6: Plot of PSRR of the OPAMP. PSRR – 139dB

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Table 4.1: The performance characteristic of the Triple Cascode OPAMP


Electrical Conditions Min Typical Max Units
Characteristics
Large Signal Voltage Max -> Vincm – 85 101 101 dB
Gain 1.5V
Typ. -> Vincm –
2.5V
Common Mode Vincm -> 1.5V - 102 - dB
Rejection Ratio
Power Supply Vincm -> 1.5V - 139 - dB
Rejection Ratio
Input Offset Voltage Min -> VDD = 2.5 V 4.24 - 20.91 mV
Max -> VDD = 3 V
Input Common Vincm -> 1.5V 0 - VDD V
Mode Input Range
Phase Margin Max -> Vincm – 58 73.71 Degree
2.5V
Typ. -> Vincm –
1.5V
Gain Margin Vincm -> 1.5V - 10.36 - dB
Output Voltage Vincm -> 1.5V 0.028 - 2.95 V
Swing
Unity Gain - - 2.33 MHz
Bandwidth
Power Consumption Max - > VDD = 3 V 0.16 - 1.33 uWatts
Min -> VDD = 2.5V

Here are some performance characteristics of the OPAMP showing that the OPAMP is
pretty much ideal to be used as an error amplifier. The power consumption of the

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OPAMP is below 1.33uW as the supply current of the OPAMP as low as 443nA. So
this is an ideal candidate for low power application.

4.3 Voltage Controlled Oscillator

The basic regulation techniques of the Charge Pump realizes on the controlling the
switching frequency depending on the load conditions. As the load current goes up the
output voltage has to be kept constant. And this can be done by increase the frequency
of the switching waveform for the CMOS power switches of the charge pump. In
order to realize a Voltage Controlled Oscillator, there are 2 types of topologies that
can be realized a) LC Oscillator and b) Ring Oscillator. The LC topology was not
selected because the frequency required for this application is pretty low (in few MHz
range) and selecting an LC Oscillator would increase the size LC component to such
an extent that it becomes impossible to fit them on chip. So the Ring Oscillator
topology was selected to design an ON-Chip VCO with limited sized components.

4.3.1 Ring Oscillator Basics

Ring Oscillator functions on the principle of 360 degree phase shift present in the
closed loop system at the frequency of oscillation along with gain greater than 3dB
[15]. In the above block diagram we can see that the each differential delay cell is
present to insert some amount of phase shift to the signal.

Fig 4.3.1.1: The block diagram of a basic 3 stage Ring Oscillator with 3 differential
cells and buffers at the output. The 3rd stage is connected to the 1st with 180 degree of
inversion.

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Each differential cell is identical and provides a constant phase shift of 60 degree. The
3rd cell is connected to the 1st cell with a phase shift of 180 degree. Also the 3rd cell
will introduced its own phase shift of 60 degree. The total phase shift around the entire
closed loop is 60+60+60+180 = 360 degree. Let’s try to understand the working of the
Ring Oscillator with respect to the frequency response of each Differential Cell. At the
frequency of oscillation of the VCO, if you measure the phase shift between the output
and input of the each differential cell, a shift change of 60 degree will be observed.
Also the gain of the differential cell at the same frequency should be greater than 3dB
or 2. The gain should be present to satisfy the Barkhausen’s criteria for oscillations. So
considering the overall transfer function of the entire system, the each stage of ring
oscillator should a frequency dependent 60 degree phase shift and gain per stage
should be 3dB so that the oscillator can oscillate at a frequency given by √3 wo .

A
3

A
2

A
1

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Fig 4.3.1.2: The above waveform shows the output of each stage of the Ring
Oscillator. It can be seen that a phase shift of 60 degree is present between the A1 and
A2 and similarly between A2 and A3.

The same phenomena can be observed from the waveform of the each differential
stage of the Ring Oscillator. As we can see that each differential stage introduces a
phase shift of 60 which is evident from the waveform of A2 and A1 and from A3 and
A2. The same phenomena can be observed from the Frequency response of a
differential cell of the Ring oscillator as shown below.

Fig 4.3.1.3: The Frequency Response of the 3 Stages of the Ring Oscillator which
shows the phase shift introduced

The above Frequency Response of a Differential Delay Cell shows it introduces a 60


Degree Phase shift at the frequency of 100 MHz and the gain of the Delay Cell is
greater than 3dB (around 23 dB). The control voltage of the VCO is kept at 3 Volts
which makes it to that the phase shift at 100 MHz is approximately 60 degree. If the

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control voltage is reduced, the frequency of oscillation will reduce and so will the 60
phase shift point also. The gain may change as the control voltage changes because the
control voltage somewhat decides the biasing conditions of the delay cell, but as long
as the gain is above 3dB it will keep on oscillating a frequency dependent on the
control voltage.

4.3.2 Basic Differential Delay Cell

Ring Oscillator using a Differential Cell with Cross Coupled Differential Pair for
Negative Resistance Generation is used this design. In order to realize the differential
cell we chose positive feedback configuration realizes using the cross-coupled
differential pair M3/4 and the M1/2 are just input differential pair. The Cascode load is
used to realize large load resistances values which replace the need for using large
load resistance.

Fig 4.3.2.1: The schematic of the basic differential delay cell with variable negative
load

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The load resistance required to obtain an oscillation the range of 100 KHz is in Mega-
Ohms. As there are 3 differential cells present and each differential pair having 2 load
resistances, the total number On-Chip load resistances in Mega-Ohms becomes 6
which will consume large chip area. So instead PMOS Cascode load is used to realize
large load resistance for On-Chip design purposes. In the below mentioned figure of
the basic differential delay cell Rp is marked as the load resistance looking into the
Cascode load. This resistance Rl comes in parallel with the negative resistance –Rn
generated by the cross couple pair as shown below and also in the illustration on Fig
4.3.2.2. The equivalent resistance Req is decides the frequency of oscillation.

Fig 4.3.2.2: The half circuit of the above mentioned delay cell

The parallel combination of the negative resistance Rn in parallel with Rl given by :


RL – Load Resistance due to PMOS cascode load.
RN – Negative load resistance generated due to presence of cross coupled NMOS pair.
Requ = =−RN A||=RL A = =RL A||=−1/gm A
+ RN RL
Requ =
RN – RP

Requ =
RL
%1® gm RL +
(4.3.1)

Also I6 = %Vcontrol – Vth +


1 W 2
un COX (4.3.2)
2 L

And gm3 = W2 un COX


W
I6
L

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Texas Tech University, Ravindranath Shrivastava, August 2012

gm3 ∝ ° I6
So from equation 8.2.2 and above relationship we get:
gm3 ∝ %Vcontrol – Vth + (4.3.3)

From equation 4.3.1 we can see that the equivalent resistance is positive if the product
of the gm *Rl is less than 1. So as long as the condition is met the VCO will oscillate.
Now from the Fig 4.3.1 we can see that the control voltage is connected to the gate of
M6. Now if the control voltage is increased the current through M3/4 will increase
increasing the value of gm. As gm*Rl increases, the Requ also increases decreasing
the frequency of oscillations. So by controlling the gm of the cross coupled pair by
using a control voltage the frequency of oscillations can be controlled.

Also the Cascode Load Resistance is given by the following equation:


Rl = gmp ∗ r2op (4.3.4)

The bias point at the output of the circuit should remain constant. But as the control
voltage is changed the current through the M3/4 changes, but the current through
M1/2 is constant. So as the control voltage varies the current through the Cascode
Load does not remain constant. This change in current in current through the load
changes the Rl which is dependent on the gm of the Cascode PMOS devices. Now as
the control voltage increases, the value of Rl increases and so does the value of gm
(from equation 4.3.3 and 4.3.6).
As mentioned above: gmp ∝ ° I6

So gmp ∝ %Vcontrol – Vth + (4.3.5)

From equation 8.2.4 and 8.2.5 we can notice that:


Rl ∝ %Vcontrol – Vth + (4.3.6)

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Texas Tech University, Ravindranath Shrivastava, August 2012

So the product Rl*gm approaches unity much faster, as control voltage increases
(equation 4.3.1). This will reduce the Frequency control range of the VCO. In order to
avoid this change in Rl we have to make sure if the current through M3/4 increases by
some amount, the current through M1/2 should decrease by the same amount so that
the current through the Cascode Load is constant and Rl doesn’t change much.

4.3.3 Modified Differential Cell – Constant Load Current Technique

The schematic shown in the Fig 4.3.3.1 is modified in such a way that if the current
through M3 increases than the current through M1 should decrease by the same
amount so that the current through the load resistance can remain constant. This in
turn will keep the load resistance and the bias conditions at the output constant
irrespective of the value of the control voltage. In this circuit there is current source
Wp7 is used to get a constant current source and the current through Wp6 is controlled
by the control voltage. As the control voltage goes down Ip6 increases and current
through Ip5 reduces because the Ip7 is always constant. Now the current I5 is
proportional to Ip5 and I6 is proportional to Ip6. So as I6 increases with lowering
control voltage, I5 will reduce by the same amount if the W/L ratios of M5 and M6 are
the same. Using this technique the frequency range of VCO can be increased.

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Texas Tech University, Ravindranath Shrivastava, August 2012

Fig 4.3.3.1: The schematic of a differential cell formed using differential input pair,
Cascode load and cross coupled differential pair for negative resistance.

4.3.4 Modified Differential Cell – Simulation Results

The schematic of the ring oscillator shows the 3 differential cells connected in series
with only the output of the 3rd cell connected to the input of the 1st cell in inverted
manner to bring about 180 Degree of phase shift. The rest of the 180 degree phase
shift is contributed by the internal phase delays introduced by each differential cell.
The Ring Oscillator in total consumes 60uA of supply current for a 3Volts power
supply and can generate oscillation frequency ranging from 5.2MHz to 32MHz.

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Fig 4.3.4.1: The cadence schematic of a ring oscillator using 3 differential cells and
NOT gate the output for wave-shaping. The circuit at the left of the figure is just used
for generating bias voltages.

Fig 4.3.4.2: The waveform of the output of the VCO when a control voltage of 1.5V is
applied which generates an output frequency of 32.1MHz.

Fig 4.3.4.3: The waveform of the output of the VCO when a control voltage of 0.43V
is applied which generates an output frequency of 5.2MHz.

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Texas Tech University, Ravindranath Shrivastava, August 2012

4.3.5 VCO Characteristics

Below is the relationship between the control voltage applied to the VCO and the
Frequency of the output waveform. It can be noticed that the output frequency range
of the VCO is not large enough. We will be exploring a slight modification in the
above design to increase the oscillation frequency.

35.0E+6

30.0E+6

25.0E+6
Frequency (Hz)

20.0E+6

15.0E+6

10.0E+6

5.0E+6

400.0E-3
0.4 0.6 0.8 1 1.2 1.4 1.6
Control Voltage (Vdc)

Fig 4.3.5.1: The plot of characteristics of the VCO showing the relationship between
the control voltage on the X axis and the Output Frequency on the Y axis.

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Texas Tech University, Ravindranath Shrivastava, August 2012

Table 4.2: The table of relationship between control voltage and the output frequency
of the VCO
Control Voltage (V) Time Period (s) Frequency (Hz)
0.43 1.91E-07 5.2E+6
0.44 1.68E-07 6.0E+6
0.45 1.49E-07 6.7E+6
0.46 1.34E-07 7.5E+6
0.47 1.20E-07 8.3E+6
0.48 1.10E-07 9.1E+6
0.5 9.46E-08 10.6E+6
0.6 6.40E-08 15.6E+6
0.7 5.96E-08 16.8E+6
0.8 5.83E-08 17.2E+6
0.9 5.72E-08 17.5E+6
1 5.61E-08 17.8E+6
1.1 4.38E-08 22.8E+6
1.2 3.31E-08 30.2E+6
1.3 3.14E-08 31.8E+6
1.4 3.13E-08 32.0E+6
1.5 3.12E-08 32.1E+6

Also it is observed that the relationship between the control voltage and the frequency
is not quite linear. So it becomes kind of difficult to use the VCO in the feedback of
the charge pump.

4.3.6 Wideband Ring VCO using adaptive load control

The idea behind this technique is that as the value of the gm goes up the product of gm
* Rl approaches the value of 1. But if the value of Rl is varied in such a way that as

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Texas Tech University, Ravindranath Shrivastava, August 2012

the gm goes up, the value of Rl goes down so the product of gm*Rl stays below 1 but
varies over a large range below 1. So we can see from the below mentioned equation
that the value of Requ stays positive and as the product gm*Rl varies over a wide
range varying the Requ over large range. This variation of Requ over a large range can
lead to large oscillation frequency range.

Fig 4.3.6.1: The schematic of the differential cell used in the design. The Vb1 and
Vb2 is changed respective of Vcontrol to get high bandwidth VCO

Requ =
RL
%1® gm RL +
(4.3.1)

The value of the Rl can be controlled by controlling the bias voltages of the PMOS
Cascode load devices. Now the aim is to reduce the Rl as the control voltage goes up.
And the Rl can be reduced by reducing the bias voltage of the PMOS Cascode devices
with respect to control voltage. The Fig 4.3.6.2 shows the decrease of bias voltages
Vb1 and Vb2 with respect to the increase in control voltage. This is achieved using
Inverting Amplifier as shown in the Fig 4.3.6.3. The value of Vb1 is varied from
2.32V to 1.89V and the value of Vb2 is varied from 1.91V to 1.54V, as control voltage
varies from 0 to 3 Volts.

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Texas Tech University, Ravindranath Shrivastava, August 2012

2.4
2.3
2.2
2.1
Bias Voltage (Vb1)
Bias Voltage (Vb2)
2 Vb1
1.9
1.8 Vb2
1.7
1.6
1.5
1.4
0 0.5 1 1.5 2 2.5 3 3.5
Control Voltage (V)

Fig 4.3.6.2: The graph shows the variation in the value of bias voltages with respect to
the change in value of control voltage

Fig 4.3.6.3: The OPAMP used in an inverting configuration to generate Vb1 and Vb2
required to reduce the load resistance when the value of control voltage increases.

As expected the value of the load resistance should drop when the value of bias
voltages drop. So a variation load resistance from 3.7GOhms to 1.1MOhms is
achieved using this technique. This large variation helps in getting a very large range
of Requivalent resistance at the output node of the delay cell leading large variation in
frequency, as we will see shortly.

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Texas Tech University, Ravindranath Shrivastava, August 2012

10.0E+9

1.0E+9

Rload (Ohms)
100.0E+6

10.0E+6

1.0E+6

100.0E+3
0 0.5 1 1.5 2 2.5 3 3.5
Control Voltage (V)

Fig 4.3.6.4: The Figure shows the reduction of load resistance with increase in control
voltage.

10.0E+0

1.0E+0
Rl * gm3

100.0E-3

10.0E-3

1.0E-3
0 0.5 1 1.5 2 2.5 3 3.5
Control Voltage (V)

Fig 4.3.6.5: The plot of the product Rl * gm3 w.r.t. control voltage. It shows that for
most of the values of control voltage the product remain less than zero.

Also as the value of Rl reduces, so does the product of gm * Rl also reduce, assuming
that gm3 varies to a less extent compared to the value of Rl. So we can get large
variation in the value of the Requivalent and in turn large variation in the value of the
oscillation frequency. This can be asserted form the equation 4.3.1. The large variation

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of the product Rl*gm3 is shown in the below mentioned graph. We can see from the
graph that the value of the product Rl * gm3 stays below the 1 for most values of
control voltages. The value of the product goes as low as 0.01 affecting the equation
4.3.1 by decreasing the Requivalent value.
Equivalent Resistance (Ohms)

100.0E+6

10.0E+6

1.0E+6

100.0E+3
0 0.5 1 1.5 2 2.5 3 3.5
Control Voltage (V)

Fig 4.3.6.6: The plot of the product Requivalent w.r.t. control voltage. It shows large
variation of resistance w.r.t. to Control Voltage.

Now taking the reduction the product of Rl*gm3 from Fig 4.3.6.5 and reduction in the
value of Rload from Figure 4.3.6.4 we expect form equation 4.3.1 that the value of the
Requivalent should reduce to a very extent. So the from the final graph in the Fig
4.3.6.6 we can easily see the variation in the value of the value of Requivalent. Later
we will look at the large frequency range variation that can be derived using this type
of design.

4.3.7 Wideband Ring VCO – Simulation Results

We can see as compared to the Frequency Range of the previous design we can get a
very large range from this design. The graph shows that the frequency of the VCO can
vary from 100 KHz to as high as 100MHz when the control voltage is varied from 0 to

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Texas Tech University, Ravindranath Shrivastava, August 2012

2.8 Volts. This large variation allows the charge pump to regulate a large range of load
conditions ranging from few micro Amps to as high as 5mA and even more, as we will
see later in the simulation results.

100.0E+6

10.0E+6
Frequency (Hz)

1.0E+6

100.0E+3

10.0E+3
0 0.5 1 1.5 2 2.5 3
Control Voltage (Vdc)

Fig 4.3.7.1: The characteristic of the VCO showing the variation of frequency w.r.t. to
Control Voltage.
Table 4.3: Performance Characteristics of the Wideband VCO

Electrical Min Typical Max Units


Characteristics

Oscillation 0.1 - 35 MHz


Frequency Range

Tuning Voltage 0 - 2 V

Tuning Sensitivity 1.9 - 62.3 MHz/V

Output Voltage 0 - 2.5 V

Power Dissipation 3.3 - 603 uWatts

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Texas Tech University, Ravindranath Shrivastava, August 2012

CHAPTER 5
SIMULATION RESULTS – CHARGE PUMP

The figure 4.4.1 shows the schematic of the Charge Pump designed in Cadence. We
can see the main block in the schematic is the charge pump power stage (Fig 3.3.1).
The OPAMP we discussed earlier is used here as the Error Amplifier and the 1st order
LPF is used to filter out any ripple present in the Vsense voltage. The VCO is also the
VCO discussed in the Fig 4.3.6.1. The simulation is done for load regulation using a
Voltage Controlled Current Source with its GM set to 1mA/V and as the Voltage
changes from 0.5V to 2.5V, the current varies from 0.5mA to 2.5mA.

90

845M

250M

37.5M

Fig 4.4.1: The complete schematic of the charge pump in cadence.

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Texas Tech University, Ravindranath Shrivastava, August 2012

Feedback Loop Analysis


The Figures 4.4.3 show the test-bench setup to plot the frequency response of the
feedback. The Feedback should not have large phase shift before the gain drops to
unity. The phase margin of 51Degree is present in the feedback loop and the unity
gain frequency is around 14.39 KHz.

Fig 4.4.2: The cadence schematic of the feedback circuitry of the charge pump

Fig 4.4.3: The frequency response of the feedback loop of the circuit with 51 Degree
of phase margin. This shows that the feedback shows stability.

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Fig 4.4.4: The Waveform shows the load regulation taking place when the load
current changes from 2.5mA to 2mA.

Fig 4.4.5: The Waveform shows the load regulation taking place when the load
current changes from 0.5mA to 2.5mA

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Texas Tech University, Ravindranath Shrivastava, August 2012

CHAPTER 6
CONCLUSION AND FUTURE WORK

6.1 Future Scope


• Implementation of a more efficient compensation scheme in the feedback for faster
response time of the feedback.

• Improving the BW of the OPAMP to speed up the Feedback loop.

• Improving the Charge Pump to handle higher loads

• Design a Data Acquisition System for monitoring the strength of the link between
the RX and TX

• Design of a adaptive link adjustment system to increase the efficiency of Wireless


links

6.2 Conclusion
• Design of Voltage Multiplier which can convert AC to usable DC for Input Power
as low as -9dBm

• 3 Stage Voltage Multiplier can achieve efficiency as high as 80% under certain
conditions. Typical efficiency of about 60% can easily be achieved using this
device.

• Voltage Multiplier can be used to charge batteries with input AC power as low as -
25dBm

• The Charge Pump Design can provide DC boosting with conversion gain of 3.3
(average) and conversion efficiency of 68%

• The Voltage Regulation circuitry has been designed successfully using OPAMP
and VCO

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