HB97E CPU 21x-2CM03 15-14

VIPA System 200V
CPU | Manual
HB97E_CPU | RE_21x-2CM03 | Rev. 15/14
April 2015
Copyright © VIPA GmbH. All Rights Reserved.
This document contains proprietary information of VIPA and is not to be disclosed or used except in accordance with applicable
agreements.
This material is protected by the copyright laws. It may not be reproduced, distributed, or altered in any fashion by any entity (either
internal or external to VIPA), except in accordance with applicable agreements, contracts or licensing, without the express written
consent of VIPA and the business management owner of the material.
For permission to reproduce or distribute, please contact:
VIPA, Gesellschaft für Visualisierung und Prozessautomatisierung mbH
Ohmstraße 4, D-91074 Herzogenaurach, Germany
Tel.: +49 (91 32) 744 -0
Fax.: +49 9132 744 1864
EMail: [email protected]
http://www.vipa.com
Note
Every effort has been made to ensure that the information contained in this document was complete and accurate at the time of
publishing. Nevertheless, the authors retain the right to modify the information. This customer document describes all the hardware
units and functions known at the present time. Descriptions may be included for units which are not present at the customer site. The
exact scope of delivery is described in the respective purchase contract.
CE Conformity Declaration
Hereby, VIPA GmbH declares that the products and systems are in compliance with the essential requirements and other relevant
provisions.
Conformity is indicated by the CE marking affixed to the product.
Conformity Information
For more information regarding CE marking and Declaration of Conformity (DoC), please contact your local VIPA customer service
organization.
Trademarks
VIPA, SLIO, System 100V, System 200V, System 300V, System 300S, System 400V, System 500S and Commander Compact are
registered trademarks of VIPA Gesellschaft für Visualisierung und Prozessautomatisierung mbH.
SPEED7 is a registered trademark of profichip GmbH.
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Information product support

Contact your local VIPA Customer Service Organization representative if you wish to report errors or questions regarding the contents
of this document. If you are unable to locate a customer service center, contact VIPA as follows:
VIPA GmbH, Ohmstraße 4, 91074 Herzogenaurach, Germany
Telefax:+49 9132 744 1204
Technical support
Contact your local VIPA Customer Service Organization representative if you encounter problems with the product or have questions
regarding the product. If you are unable to locate a customer service center, contact VIPA as follows:
VIPA GmbH, Ohmstraße 4, 91074 Herzogenaurach, Germany
Telephone: +49 9132 744 1150 (Hotline)
Manual VIPA System 200V Contents
Contents
About this manual .................................................................................... 1

Safety information .................................................................................... 2
Chapter 1 Basics and Assembly ..................................................... 1-1
Safety Information for Users................................................................. 1-2
System conception ............................................................................... 1-3
Dimensions .......................................................................................... 1-5
Installation ............................................................................................ 1-7
Demounting and module exchange .................................................... 1-11
Wiring................................................................................................. 1-12
Installation guidelines ......................................................................... 1-14
General data ...................................................................................... 1-17
Chapter 2 Hardware description ..................................................... 2-1
Properties............................................................................................. 2-2
Structure .............................................................................................. 2-3
Technical Data ..................................................................................... 2-7
Chapter 3 Deployment CPU 21x-2CM03.......................................... 3-1
Assembly.............................................................................................. 3-2
Start-up behavior.................................................................................. 3-2
Addressing ........................................................................................... 3-3
Hints for the deployment of the MPI interface....................................... 3-5
Hardware configuration - CPU.............................................................. 3-6
Hardware configuration - I/O modules .................................................. 3-8
Setting CPU parameters ...................................................................... 3-9
Project transfer................................................................................... 3-13
Operating modes................................................................................ 3-17
Firmware update ................................................................................ 3-19
Factory reset ...................................................................................... 3-21
VIPA specific diagnostic entries ......................................................... 3-22
Using test functions for control and monitoring of variables................ 3-24
Chapter 4 CANopen communication .............................................. 4-1
Principles CAN bus .............................................................................. 4-2
Project engineering of the CPU 21x-2CM03......................................... 4-4
Modes ................................................................................................ 4-13
Process image of the CPU 21x-2CM03.............................................. 4-14
CANopen - Messages ........................................................................ 4-16
Object directory .................................................................................. 4-21
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 i

Contents Manual VIPA System 200V
ii HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Manual VIPA System 200V About this manual
About this manual
This manual describes the System 200V CPU 21x-2CM03 from VIPA. Here
you may find every information for commissioning and operation.
Overview Chapter 1: Basics and Assembly

The focus of this chapter is on the introduction of the VIPA System 200V.
Here you will find the information required to assemble and wire a
controller system consisting of System 200V components.
Besides the dimensions the general technical data of System 200V will be
found.
Chapter 2: Hardware description

Here the hardware components of the CPU are described. The technical
data are at the end of the chapter.
Chapter 3: Deployment CPU 21x-2CM03

This chapter describes the deployment of the CPU in the System 200V.
The description refers directly to the CPU and to the deployment in
connection with peripheral modules, mounted on a profile rail together with
the CPU at the backplane bus.
Chapter 4: CANopen communication

Content of this chapter is the Deployment of the 21x-2CM03 under
CANopen. Here you’ll find all information required for the usage of the
integrated CAN master.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1

About this manual Manual VIPA System 200V
Objective and This manual describes the System 200V CPU 21x-2CM03 from VIPA.
contents It contains a description of the construction, project implementation and
usage.
This manual is part of the documentation package with order number
HB97E_CPU and relevant for:
Product Order number as of state:
CPU-HW CPU-FW CAN
CPU 21xCAN VIPA CPU 21x-2CM03 01 V 4.1.7 V 1.2.8
Target audience The manual is targeted at users who have a background in automation
technology.
Structure of the The manual consists of chapters. Every chapter provides a self-contained
manual description of a specific topic.
Guide to the The following guides are available in the manual:

document • an overall table of contents at the beginning of the manual
• an overview of the topics for every chapter
Availability The manual is available in:

• printed form, on paper
• in electronic form as PDF-file (Adobe Acrobat Reader)
Icons Important passages in the text are highlighted by following icons and
Headings headings:
Danger!
Immediate or likely danger.
Personal injury is possible.
Attention!
Damages to property is likely if these warnings are not heeded.
Note!
Supplementary information and useful tips.
2 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Manual VIPA System 200V Safety information
Safety information
Applications The CPU 21x is constructed and produced for:

conforming with • all VIPA System 200V components
specifications
• communication and process control
• general control and automation applications
• industrial applications
• operation within the environmental conditions specified in the technical
data
• installation into a cubicle
Danger!
This device is not certified for applications in
• in explosive environments (EX-zone)
Documentation The manual must be available to all personnel in the

• project design department
• installation department
• commissioning
• operation
The following conditions must be met before using or commissioning

the components described in this manual:
• Hardware modifications to the process control system should only be

carried out when the system has been disconnected from power!
• Installation and hardware modifications only by properly trained

personnel.
• The national rules and regulations of the respective country must be

satisfied (installation, safety, EMC ...)
Disposal National rules and regulations apply to the disposal of the unit!
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3

Safety information Manual VIPA System 200V
4 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Manual VIPA System 200V Chapter 1 Basics and Assembly
Chapter 1 Basics and Assembly
Overview The focus of this chapter is on the introduction of the VIPA System 200V.
Here you will find the information required to assemble and wire a controller
system consisting of System 200V components.
Besides the dimensions the general technical data of System 200V will be
found.
Contents Topic Page

Chapter 1 Basics and Assembly ..................................................... 1-1
Safety Information for Users................................................................. 1-2
System conception ............................................................................... 1-3
Dimensions .......................................................................................... 1-5
Installation ............................................................................................ 1-7
Demounting and module exchange .................................................... 1-11
Wiring................................................................................................. 1-12
Installation guidelines ......................................................................... 1-14
General data ...................................................................................... 1-17
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1-1

Chapter 1 Basics and Assembly Manual VIPA System 200V
Safety Information for Users
Handling of VIPA modules make use of highly integrated components in MOS-

electrostatic Technology. These components are extremely sensitive to over-voltages
sensitive modules that can occur during electrostatic discharges.
The following symbol is attached to modules that can be destroyed by
electrostatic discharges.
The Symbol is located on the module, the module rack or on packing

material and it indicates the presence of electrostatic sensitive equipment.
It is possible that electrostatic sensitive equipment is destroyed by energies
and voltages that are far less than the human threshold of perception.
These voltages can occur where persons do not discharge themselves
before handling electrostatic sensitive modules and they can damage
components thereby, causing the module to become inoperable or
unusable.
Modules that have been damaged by electrostatic discharges can fail after
a temperature change, mechanical shock or changes in the electrical load.
Only the consequent implementation of protection devices and meticulous
attention to the applicable rules and regulations for handling the respective
equipment can prevent failures of electrostatic sensitive modules.
Shipping of Modules must be shipped in the original packing material.

electrostatic
sensitive modules
Measurements and When you are conducting measurements on electrostatic sensitive modules
alterations on you should take the following precautions:
electrostatic
sensitive modules • Floating instruments must be discharged before use.
• Instruments must be grounded.
Modifying electrostatic sensitive modules you should only use soldering
irons with grounded tips.
Attention!
Personnel and instruments should be grounded when working on
electrostatic sensitive modules.
1-2 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

System conception
Overview The System 200V is a modular automation system for assembly on a

35mm profile rail. By means of the peripheral modules with 4, 8 and 16
channels this system may properly be adapted matching to your
automation tasks.
CPU 215 SM 221 SM 221 SM 221 SM 221

DI 8xDC24V DI 8xDC24V DI 8xDC24V DI 8xDC24V
R RN
ST 1 1 1 1
S MR
.0 2 .0 2 .0 2 .0 2
MMC .1 3 .1 3 .1 3 .1 3
PW .2 4 .2 4 .2 4 .2 4
SF .3 5 .3 5 .3 5 .3 5
FC .4 6 .4 6 .4 6 .4 6
M
2
MC P .5 7 .5 7 .5 7 .5 7
I
.6 8 .6 8 .6 8 .6 8
.7 9 .7 9 .7 9 .7 9
X1
DC I0 I0 I0 I0
24V + 1
X 2 - 2 X 2 X 2 X 2 X 2
3 4 3 4 3 4 3 4 3 4
VIPA 215-1BA03 VIPA 221-1BF00 VIPA 221-1BF00 VIPA 221-1BF00 VIPA 221-1BF00
Components The System 200V consists of the following components:

• Head modules like CPU and bus coupler
• Periphery modules like I/O, function und communication modules
• Power supplies
• Extension modules
Head modules With a head module CPU respectively bus

interface and DC 24V power supply are
CPU 214 IM 253DP integrated to one casing.
RN
R ST 9 9 Via the integrated power supply the CPU
MR
S
MMC ADR. respectively bus interface is power
PW
PW
SF
ER supplied as well as the electronic of the
FC M
P2
RD
DE
D
P
connected periphery modules.
MC I
X1
X1
DC + 1 DC + 1
24V 24V
X 2 - 2 - 2
X 8
3 4 9 10
VIPA 214-1BC03 VIPA 253-1DP00
Periphery modules The modules are direct installed on a

35mm profile rail and connected to the
SM 221
DI 8xAC/..48V
n
DI 16xDC24V
1
head module by a bus connector, which
1
.0
.1
2
3
was mounted on the profile rail before.
1 .2 4
.02
.13
2
3
.3
.4
5
6
Most of the periphery modules are
.24
.35
4
5
.5
.6
.7
7
8
9
equipped with a 10pin respectively 18pin
.46 6
.0
.1
10
11
connector. This connector provides the
.57 7
.68 8
.2
.3
.4
12
13
14
electrical interface for the signaling and
.79
N10
9
I0
.5
.6
15
16
supplies lines of the modules.
.7 17
X 2 18
3 4 n+1 X 2
VIPA 221-1FF30 VIPA 221-1BH10 3 4
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1-3

Power supplies With the System 200V the DC 24V power

supply can take place either externally or
PS 207/2 via a particularly for this developed power
OH
L
N
supply.
G
100-240V AC
P
E The power supply may be mounted on the
OL
550-230mA
50-60Hz
profile rail together with the System 200V
OK
OUT DC 24V / ∑Ι:2A
modules. It has no connector to the back-
X1
+
4A (peak)
1
plane bus.
DC 24V
- 2
+ 3
DC 24V
- 4
X 2
3 4
VIPA 207-1BA00
Expansion The expansion modules are complemen-

modules tary modules providing 2- or 3wire con-
CM 201 nection facilities.
X1. X2.
The modules are not connected to the
backplane bus.
X 2
3 4
VIPA 201-1AA00
Structure/ • Profile rail 35mm

dimensions • Dimensions of the basic enclosure:
1tier width: (HxWxD) in mm: 76x25.4x74 in inches: 3x1x3
Installation Please note that you can only install header modules, like the CPU, the PC
and couplers at slot 1 or 1 and 2 (for double width modules).
1 2 3
[1] Head module
(double width)
[2] Head module
(single width)
4 [3] Periphery module
[4] Guide rails
Note
0 1
A maximum of 32 modules can
be connected at the back plane
bus. Take attention that here the
maximum sum current of 3.5A
is not exceeded.
Please install modules with a
D
P
high current consumption direct-
ly beside the header module.
Clack
1-4 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Dimensions
Dimensions 1tier width (HxWxD) in mm: 76 x 25.4 x 74

Basic enclosure 2tier width (HxWxD) in mm: 76 x 50.8 x 74
Installation
dimensions
80 mm
60 mm
Installed and wired
dimensions
In- / Output 85 mm
84 mm
modules 74 mm
cm
2,77mm
24
76 mm
76,62 mm
88 mm
ca. 110 mm
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1-5

Function modules/ 89 mm
88 mm
Extension modules 85 mm
84,46 mm
11
4,66mm
mm
27 mm
24
768 mm
cm
CPUs (here with 91mm
89 mm
EasyConn from 85 mm
VIPA)
11 mm
5 mm
mm
27 mm
24
768mm
cm
65 mm
12 cm
125 mm
1-6 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Installation
General The modules are each installed on a 35mm profile rail and connected via a
bus connector. Before installing the module the bus connector is to be
placed on the profile rail before.
Profile rail For installation the following 35mm profile rails may be used:
35 mm
1,5 mm
35 mm
1 mm
15 mm
7,5 mm
27 mm 27 mm
Order number Label Description

290-1AF00 35mm profile rail Length 2000mm, height 15mm
290-1AF30 35mm profile rail Length 530mm, height 15mm
Bus connector System 200V modules communicate via a backplane bus connector. The
backplane bus connector is isolated and available from VIPA in of 1-, 2-, 4-
or 8tier width.
The following figure shows a 1tier connector and a 4tier connector bus:
The bus connector is to be placed on the profile rail until it clips in its place
and the bus connections look out from the profile rail.
Order number Label Description
290-0AA10 Bus connector 1tier
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1-7

Installation on a The following figure shows the installation of a 4tier width bus connector in
profile rail a profile rail and the slots for the modules.
The different slots are defined by guide rails.
1 2 3
[1] Header module
(double width)
[2] Header module
(single width)
[3] Peripheral module
[4] Guide rails
PW
ER
RD
BA
ADR. 0 1
DC24V
+ 1
- 2
R
S
MMC
PW
SF
FC
MC
Assembly regarding • Use bus connectors as long as possible.

the current
consumption • Sort the modules with a high current consumption right beside the
header module. In the service area of www.vipa.com a list of current
consumption of every System 200V module can be found.
1-8 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Assembly
possibilities
hoizontal assembly vertical Please regard the allowed environmental temperatures:
assembly
• horizontal assembly: from 0 to 60°C
• vertical assembly: from 0 to 40°C
• lying assembly:
0 1
from 0 to 40°C
lying assembly The horizontal assembly always starts at the left side with
a header module, then you install the peripheral modules
beside to the right.
You may install up to 32 peripheral modules.
0 1
Please follow these rules during the assembly!

• Turn off the power supply before you install or remove
80 mm
any modules!
• Make sure that a clearance of at least 60mm exists
above and 80mm below the middle of the profile rail.
60 mm
• Every row must be completed from left to right and it

1 2 3
has to start with a header module.
[1] Header module (double width)

[2] Header module (single width)
4
[3] Peripheral modules
[4] Guide rails
• Modules are to be installed side by side. Gaps are not

permitted between the modules since this would
interrupt the backplane bus.
• A module is only installed properly and connected
electrically when it has clicked into place with an
audible click.
• Slots after the last module may remain unoccupied.
Note!
A maximum of 32 modules can be connected at the back plane bus. Take
attention that here the maximum sum current of 3.5A is not exceeded.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1-9

Assembly
procedure
• Install the profile rail. Make sure that a clearance of at least 60mm
exists above and 80mm below the middle of the profile rail.
• Press the bus connector into the profile rail until it clips securely into
place and the bus-connectors look out from the profile rail. This
provides the basis for the installation of your modules.
• Start at the outer left location with the installation of your header
module and install the peripheral modules to the right of this.
1 2 3 [1] Header module
(double width)
[2] Header module
(single width)
[3] Peripheral module
[4] Guide rails
4
• Insert the module that you are installing into the profile rail at an angle
of 45 degrees from the top and rotate the module into place until it
clicks into the profile rail with an audible click. The proper connection
to the backplane bus can only be guaranteed when the module has
properly clicked into place.
Attention!
Power must be turned off before modules are
installed or removed!
Clack
1-10 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Demounting and module exchange
• Remove if exists the wiring to the module, by pressing both

locking lever on the connector and pulling the connector.
1
• The casing of the module has a spring loaded clip at the

bottom by which the module can be removed.
2
• The clip is unlocked by pressing the screwdriver in an upward

direction.
3
• Withdraw the module with a slight rotation to the top.

4
Attention!
Power must be turned off before modules are installed or
removed!
Please regard that the backplane bus is interrupted at the point
where the module was removed!
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1-11

Wiring
Overview Most peripheral modules are equipped with a 10pole or a 18pole connector.
This connector provides the electrical interface for the signaling and supply
lines of the modules.
The modules carry spring-clip connectors for interconnections and wiring.
The spring-clip connector technology simplifies the wiring requirements for
signaling and power cables.
In contrast to screw terminal connections, spring-clip wiring is vibration
proof. The assignment of the terminals is contained in the description of the
respective modules.
You may connect conductors with a diameter from 0.08mm2 up to 2.5mm2
(max. 1.5mm2 for 18pole connectors).
The following figure shows a module with a 10pole connector.
[1] Locking lever

[2] Pin no. at the module
[3] Pin no. at the connector
1 [4] Wiring port
1 2 [5] Opening for screwdriver
1 1
2
2 3
2
3 3
4 4
5
34 5
5
6 6
7 7
8 8
9 9
10 10
Note!
The spring-clip is destroyed if you push the screwdriver into the wire port!
Make sure that you only insert the screwdriver into the square hole of the
connector!
1-12 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Wiring procedure
• Install the connector on the module until it locks with an audible click.
For this purpose you press the two clips together as shown.
The connector is now in a permanent position and can easily be wired.
The following section shows the wiring procedure from top view.
• Insert a screwdriver at an angel into the square opening as shown.

• Press and hold the screwdriver in the opposite direction to open the
contact spring.
• Insert the stripped end of the wire into the round opening. You can use
wires with a diameter of 0.08mm2 to 2.5mm2
(1.5mm2 for 18pole connectors).
• By removing the screwdriver the wire is connected safely with the plug
connector via a spring.
Note!
Wire the power supply connections first followed by the signal cables
(inputs and outputs).
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1-13

Installation guidelines
General The installation guidelines contain information about the interference free
deployment of System 200V systems. There is the description of the ways,
interference may occur in your control, how you can make sure the
electromagnetic digestibility (EMC), and how you manage the isolation.
What means EMC? Electromagnetic digestibility (EMC) means the ability of an electrical device,
to function error free in an electromagnetic environment without being
interferenced res. without interferencing the environment.
All System 200V components are developed for the deployment in hard
industrial environments and fulfill high demands on the EMC. Nevertheless
you should project an EMC planning before installing the components and
take conceivable interference causes into account.
Possible Electromagnetic interferences may interfere your control via different ways:
interference • Electromagnetic fields (RF coupling)
causes
• Magnetic fields with power frequency
• I/O signal conductors
• Bus system
• Current supply
• Protected earth conductor
Depending on the spreading medium (lead bound or lead free) and the
distance to the interference cause, interferences to your control occur by
means of different coupling mechanisms.
One differs:
• galvanic coupling
• capacitive coupling
• inductive coupling
• radiant coupling
1-14 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Basic rules for In the most times it is enough to take care of some elementary rules to
EMC guarantee the EMC. Please regard the following basic rules when installing
your PLC.
• Take care of a correct area-wide grounding of the inactive metal parts
when installing your components.
- Install a central connection between the ground and the protected
earth conductor system.
- Connect all inactive metal extensive and impedance-low.
- Please try not to use aluminum parts. Aluminum is easily oxidizing
and is therefore less suitable for grounding.
• When cabling, take care of the correct line routing.
- Organize your cabling in line groups (high voltage, current supply,
signal and data lines).
- Always lay your high voltage lines and signal res. data lines in
separate channels or bundles.
- Route the signal and data lines as near as possible beside ground
areas (e.g. suspension bars, metal rails, tin cabinet).
• Proof the correct fixing of the lead isolation.
- Data lines must be laid isolated (for details see below).
- Analog lines must be laid isolated. When transmitting signals with
small amplitudes the one sided laying of the isolation may be
favorable.
- Lay the line isolation extensively on an isolation/protected earth con-
ductor rail directly after the cabinet entry and fix the isolation with
cable clamps.
- Make sure that the isolation/protected earth conductor rail is
connected impedance-low with the cabinet.
- Use metallic or metalized plug cases for isolated data lines.
• In special use cases you should appoint special EMC actions.
- Wire all inductivities with erase links, which are not addressed by the
System SLIO modules.
- For lightening cabinets you should avoid luminescent lamps.
• Create a homogeneous reference potential and ground all electrical
operating supplies when possible.
- Please take care for the targeted employment of the grounding
actions. The grounding of the PLC is a protection and functionality
activity.
- Connect installation parts and cabinets with the System SLIO in star
topology with the isolation/protected earth conductor system. So you
avoid ground loops.
- If potential differences between installation parts and cabinets occur,
lay sufficiently dimensioned potential compensation lines.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1-15

Isolation of Electrical, magnetically and electromagnetic interference fields are

conductors weakened by means of an isolation, one talks of absorption.
Via the isolation rail, that is connected conductive with the rack,
interference currents are shunt via cable isolation to the ground. Hereby
you have to make sure, that the connection to the protected earth conduc-
tor is impedance-low, because otherwise the interference currents may
appear as interference cause.
When isolating cables you have to regard the following:

• If possible, use only cables with isolation tangle.
• The hiding power of the isolation should be higher than 80%.
• Normally you should always lay the isolation of cables on both sides.
Only by means of the both-sided connection of the isolation you achieve
high quality interference suppression in the higher frequency area.
Only as exception you may also lay the isolation one-sided. Then you
only achieve the absorption of the lower frequencies. A one-sided
isolation connection may be convenient, if:
- the conduction of a potential compensating line is not possible
- analog signals (some mV res. µA) are transferred
- foil isolations (static isolations) are used.
• With data lines always use metallic or metalized plugs for serial
couplings. Fix the isolation of the data line at the plug rack. Do not lay
the isolation on the PIN 1 of the plug bar!
• At stationary operation it is convenient to strip the insulated cable
interruption free and lay it on the isolation/protected earth conductor line.
• To fix the isolation tangles use cable clamps out of metal. The clamps
must clasp the isolation extensively and have well contact.
• Lay the isolation on an isolation rail directly after the entry of the cable in
the cabinet. Lead the isolation further on to the System 200V module
and don't lay it on there again!
Please regard at installation!

At potential differences between the grounding points, there may be a
compensation current via the isolation connected at both sides.
Remedy: Potential compensation line.
1-16 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

General data
Structure/ • Profile rail 35mm

dimensions • Peripheral modules with recessed labelling
• Dimensions of the basic enclosure:
Reliability • Wiring by means of spring pressure connections (CageClamps) at the

front-facing connector, core cross-section 0.08 ... 2.5mm2 or 1.5mm2
(18pole plug)
• Complete isolation of the wiring when modules are exchanged
• Every module is isolated from the backplane bus
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1-17

General data
Conformity and approval

Conformity
CE 2006/95/EC Low-voltage directive
2004/108/EC EMC directive
Approval
UL UL 508 Approval for USA and Canada
others
RoHS 2011/65/EU Product is lead-free; Restriction of the use of
certain hazardous substances in electrical and
electronic equipment
Protection of persons and device protection

Type of protection - IP20
Electrical isolation
to the field bus - electrically isolated
to the process level - electrically isolated
Insulation resistance EN 61131-2 -
Insulation voltage to reference earth
Inputs / outputs - AC / DC 50V, test voltage AC 500V
Protective measures - against short circuit
Environmental conditions to EN 61131-2

Climatic
Storage / transport EN 60068-2-14 -25…+70°C
Operation
Horizontal installation EN 61131-2 0…+60°C
Vertical installation EN 61131-2 0…+60°C
Air humidity EN 60068-2-30 RH1 (without condensation, rel. humidity 10…95%)
Pollution EN 61131-2 Degree of pollution 2
Mechanical
Oscillation EN 60068-2-6 1g, 9Hz ... 150Hz
Shock EN 60068-2-27 15g, 11ms
Mounting conditions
Mounting place - In the control cabinet
Mounting position - Horizontal and vertical
EMC Standard Comment

Emitted EN 61000-6-4 Class A (Industrial area)
interference
Noise immunity EN 61000-6-2 Industrial area
zone B
EN 61000-4-2 ESD
8kV at air discharge (degree of severity 3),
4kV at contact discharge (degree of severity 2)
EN 61000-4-3 HF field immunity (casing)
80MHz … 1000MHz, 10V/m, 80% AM (1kHz)
1.4GHz ... 2.0GHz, 3V/m, 80% AM (1kHz)
2GHz ... 2.7GHz, 1V/m, 80% AM (1kHz)
EN 61000-4-6 HF conducted
150kHz … 80MHz, 10V, 80% AM (1kHz)
EN 61000-4-4 Burst, degree of severity 3
)
EN 61000-4-5 Surge, installation class 3 *
)
* Due to the high-energetic single pulses with Surge an appropriate external protective circuit with
lightning protection elements like conductors for lightning and overvoltage is necessary.
1-18 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Manual VIPA System 200V Chapter 2 Hardware description
Chapter 2 Hardware description
Overview Here the hardware components of the CPU are described. The technical
data are at the end of the chapter.
Contents Topic Page

Chapter 2 Hardware description ..................................................... 2-1
Properties............................................................................................. 2-2
Structure .............................................................................................. 2-3
Technical data...................................................................................... 2-7
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 2-1

Chapter 2 Hardware description Manual VIPA System 200V
Properties
CPU 21x-2CM03 • Instruction set compatible with Siemens STEP7

• Configuration by means of the Siemens SIMATIC manager
• Integrated V-Bus controller for controlling System 200V peripherals
• Integrated 24V power supply
• Total address range: 1024Byte inputs, 1024Byte outputs
(128Byte process image each)
• 96 / 128kByte of work memory "on board"
• 144 / 192kByte of load memory "on board"
• MMC slot (for user program)
• Battery backed clock
• MP2I interface for data transfer
• Status LEDs for operating mode and diagnostics
• Integrated CAN master
CPU 214CAN CPU 215CAN
R RN R RN
ST ST
S MR S MR
MMC MMC
RN PW RN PW
IF SF IF SF
BA C FC M BA C FC M
2 2
ER A MC P ER A MC P
N I N I
X1 X1
DC DC
24V + 1 24V + 1
X 2
3 4
- 2 X 2
3 4
- 2
VIPA 214-2CM03 VIPA 215-2CM03
Order data Type Order number Description

CPU 214CAN VIPA 214-2CM03 SPS CPU 214 with CAN master and
96/144kByte of work/load memory
CPU 215CAN VIPA 215-2CM03 SPS CPU 214 with CAN master and
128/192kByte of work/load memory
2-2 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Structure
Front view CPU 21xCAN [1] Operating mode switch

1
CPU 21xCAN [2] LEDs of the CPU
R RN
ST
[3] Slot for MMC
2
S MR 3 memory card
2
MMC [4] MP I interface
RN PW [5] Slot for 24V DC power supply
IF SF [6] LEDs of the CAN master
BA
6 C
FC
M [7] CAN interface
2
ER A MC P 4
N I
7
X1
DC
24V + 1
X 2
- 2 5
3 4
VIPA 21x-2CM03
CAN MP 2 I
Interfaces
1 n. c. 1 reserved
1
2 CAN low 5
2 M24V
6 3 CAN Ground 9 3 RxD/TxD-P (line B)
2 4
7
4 n. c. 8
4 RTS
3 5 shield 3 5 M5V
8 7
4
6 Ground 6 P5V
2
9 7 CAN high 6 7 P24V
5 1
8 n. c. 8 RxD/TxD-N (line A)
9 n. c. 9 n.c.
X1
+ 1 + DC 24 V
- 2 0V
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 2-3

Power supply The CPU has an internal power supply. This is connected to an external
supply voltage via two terminals located on the front of the unit.
The power supply requires DC 24V (20.4 ... 28.8V). In addition to the
electronic circuitry of the CPU this supply voltage is used for the modules
connected to the backplane bus.
The electronic circuitry of the CPU is not dc-insulated from the supply
voltage. The power supply is protected against reverse polarity and short
circuits.
Note!
Please ensure that the polarity of the supply voltage is correct.
MP2I interface The MPI unit provides the link for the data transfer between the CPU and
the PC. Via bus communication you are able to exchange programs and
data between different CPUs that are linked over MPI.
For a serial exchange between the partners you normally need a special
MPI-converter. But now you are also able to use the VIPA "Green Cable"
(Order-No. VIPA 950-0KB00), which allows you to establish a serial peer-
to-peer connection over the MPI interface.
Please regard the "Hints for the deployment of the MPI interface" in
chapter "Deployment CPU 21x".
CAN interface The CPU 21x-2CM03 is connected to the CAN system by means of a 9pin
plug.
Note!
More details on the CAN master see chapter "CANopen communication".
2-4 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Memory The CPUs have an integrated work and a load memory. The memories are
management battery-buffered.
Order number Work memory Load memory

VIPA 214-2CM03 96kByte 144kByte
VIPA 215-2CM03 128kByte 192kByte
In the load memory there are program code and blocks stored together
with the header information.
The program parts and blocks, which are relevant for the running program,
are loaded to the work memory during the program sequence.
Operating mode With the operating mode switch you may switch the CPU between STOP
switch and RUN.
During the transition from STOP to RUN the operating mode START-UP is
driven by the CPU.
RN
ST
By Switching to MR (Memory Reset) you request an overall reset with
MR
following load from MMC, if a project there exists.
MMC slot You may install a VIPA MMC memory card in this slot as external storage
memory card device (Order No.: VIPA 953-0KX10).
The access to the MMC takes always place after an overall reset.
Battery backup for A rechargeable battery is installed on every CPU 21x to safeguard the
clock and RAM contents of the RAM when power is removed. This battery is also used to
buffer the internal clock.
The rechargeable battery is maintained by a charging circuit that receives
its power from the internal power supply and that maintain the clock and
RAM for a max. period of 30 days.
Attention!
Due to a long storage of the CPU, the battery may be discharged
excessively. Please connect the CPU at least for 24 hours to the power
supply, to achieve the full buffer capacity.
After a power reset and with an empty battery the CPU starts with a BAT
error and executes an overall reset, because with an empty battery the
RAM content is undefined.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 2-5

LEDs CPU The CPU has got LEDs on its front side. In the following the usage and the
according colors of the LEDs is described.
Name Color Description

PW green Indicates CPU power on.
R green CPU status is RUN.
S yellow CPU status is STOP.
SF red Is turned on if a system error is detected
(hardware defect)
FC yellow Is turned on when variables are forced (fixed).
MC yellow This LED blinks when the MMC is accessed.
LEDs CAN The LEDs are located in the left half of the front panel and they are used
for diagnostic purposes. The following table shows the color and the
significance of these LEDs.
Name Color Description

RN green CAN master RUN
On: CAN master state is RUN
Off: CAN master state is STOP
ER red Error
On: During initialization and at slave failure
Off: All slaves are in the state "operational"
BA yellow BA (Bus active)
On: CAN bus communication respectively state
"operational"
Blinking (1Hz): shows state "pre-operational"
Blinking (10Hz): shows state "prepared"
IF red Initialization
On: Initialization error at wrong parameterization
Off: Initialization is OK
Note!
If all LEDs are blinking with 1Hz, the CAN master awaits valid parameters
from the CPU. If the CAN master is not supplied with parameters by the
CPU his LEDs get off after 5s.
2-6 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Technical data
214-2CM03 Order no. 214-2CM03

Type CPU 214CAN
Technical data power supply
Power supply (rated value) DC 24 V
Power supply (permitted range) DC 20.4...28.8 V
Reverse polarity protection 9
Current consumption (no-load operation) 110 mA
Current consumption (rated value) 1.5 A
Inrush current 65 A
I²t 0.75 A²s
Max. current drain at backplane bus 3A
Power loss 5W
Load and working memory
Load memory, integrated 144 KB
Load memory, maximum 144 KB
Work memory, integrated 96 KB
Work memory, maximal 96 KB
Memory divided in 50% program / 50% data -
Memory card slot MMC-Card with max. 512
MB
Hardware configuration
Racks, max. 4
Modules per rack, max. total max. 32
Number of integrated DP master -
Number of DP master via CP 8
Operable function modules 32
Operable communication modules PtP 32
Operable communication modules LAN -
Command processing times
Bit instructions, min. 0.18 µs
Word instruction, min. 0.78 µs
Double integer arithmetic, min. 1.8 µs
Floating-point arithmetic, min. 40 µs
Timers/Counters and their retentive
characteristics
Number of S7 counters 256
S7 counter remanence adjustable 0 up to 64
S7 counter remanence adjustable C0 .. C7
Number of S7 times 256
S7 times remanence adjustable 0 up to 128
S7 times remanence adjustable not retentive
Data range and retentive characteristic
Number of flags 8192 Bit
Bit memories retentive characteristic adjustable adjustable 0 up to 256
Bit memories retentive characteristic preset MB0 .. MB15
Number of data blocks 2047
Max. data blocks size 16 KB
Number range DBs 1 ... 2047
Max. local data size per execution level 1024 Byte
Max. local data size per block 1024 Byte
Blocks
Number of OBs 14
Maximum OB size 16 KB
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 2-7

Order no. 214-2CM03

Total number DBs, FBs, FCs -
Number of FBs 1024
Maximum FB size 16 KB
Number range FBs 0 ... 1023
Number of FCs 1024
Maximum FC size 16 KB
Number range FCs 0 ... 1023
Maximum nesting depth per priority class 8
Maximum nesting depth additional within an error 1
OB
Time
Real-time clock buffered 9
Clock buffered period (min.) 30 d
Type of buffering Vanadium Rechargeable
Lithium Batterie
Load time for 50% buffering period 20 h
Accuracy (max. deviation per day) 10 s
Number of operating hours counter 8
Clock synchronization -
Synchronization via MPI -
Synchronization via Ethernet (NTP) -
Address areas (I/O)
Input I/O address area 1024 Byte
Output I/O address area 1024 Byte
Process image adjustable -
Input process image preset 128 Byte
Output process image preset 128 Byte
Input process image maximal 128 Byte
Output process image maximal 128 Byte
Digital inputs 8192
Digital outputs 8192
Digital inputs central 512
Digital outputs central 512
Integrated digital inputs -
Integrated digital outputs -
Analog inputs 512
Analog outputs 512
Analog inputs, central 128
Analog outputs, central 128
Integrated analog inputs -
Integrated analog outputs -
Communication functions
PG/OP channel 9
Global data communication 9
Number of GD circuits, max. 4
Size of GD packets, max. 22 Byte
S7 basic communication 9
S7 basic communication, user data per job 76 Byte
S7 communication 9
S7 communication as server 9
S7 communication as client -
S7 communication, user data per job 160 Byte
Number of connections, max. 16
Functionality Sub-D interfaces
Type MP²I
Type of interface RS485
2-8 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Order no. 214-2CM03

Connector Sub-D, 9-pin, female
Electrically isolated -
MPI 9
MP²I (MPI/RS232) 9
DP master -
DP slave -
Point-to-point interface -
Type CAN
Type of interface CAN
Connector Sub-D, 9-pin, male
Electrically isolated 9
MPI -
MP²I (MPI/RS232) -
DP master -
DP slave -
Functionality MPI
PG/OP channel 9
Routing -
S7 communication 9
Transmission speed, min. 19.2 kbit/s
Transmission speed, max. 187.5 kbit/s
Datasizes
Input bytes 0
Output bytes 0
Parameter bytes 3
Diagnostic bytes 0
Housing
Material PPE / PA 6.6
Mounting Profile rail 35 mm
Mechanical data
Dimensions (WxHxD) 50.8 x 76 x 80 mm
Weight 150 g
Environmental conditions
Operating temperature 0 °C to 60 °C
Storage temperature -25 °C to 70 °C
Certifications
UL508 certification yes
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 2-9

215-2CM03 Order no. 215-2CM03

Type CPU 215CAN
Technical data power supply
Power supply (rated value) DC 24 V
Power supply (permitted range) DC 20.4...28.8 V
Reverse polarity protection 9
Current consumption (no-load operation) 110 mA
Current consumption (rated value) 1.5 A
Inrush current 65 A
I²t 0.75 A²s
Max. current drain at backplane bus 3A
Power loss 5W
Load and working memory
Load memory, integrated 192 KB
Load memory, maximum 192 KB
Work memory, integrated 128 KB
Work memory, maximal 128 KB
Memory divided in 50% program / 50% data -
Memory card slot MMC-Card with max. 512
MB
Hardware configuration
Racks, max. 4
Modules per rack, max. total max. 32
Number of integrated DP master -
Number of DP master via CP 8
Operable function modules 32
Operable communication modules PtP 32
Operable communication modules LAN -
Command processing times
Bit instructions, min. 0.18 µs
Word instruction, min. 0.78 µs
Double integer arithmetic, min. 1.8 µs
Floating-point arithmetic, min. 40 µs
Timers/Counters and their retentive
characteristics
Number of S7 counters 256
S7 counter remanence adjustable 0 up to 64
S7 counter remanence adjustable C0 .. C7
Number of S7 times 256
S7 times remanence adjustable 0 up to 128
S7 times remanence adjustable not retentive
Data range and retentive characteristic
Number of flags 8192 Bit
Bit memories retentive characteristic adjustable adjustable 0 up to 256
Bit memories retentive characteristic preset MB0 .. MB15
Number of data blocks 2047
Max. data blocks size 16 KB
Number range DBs 1 ... 2047
Max. local data size per execution level 1024 Byte
Max. local data size per block 1024 Byte
Blocks
Number of OBs 14
Maximum OB size 16 KB
Total number DBs, FBs, FCs -
Number of FBs 1024
Maximum FB size 16 KB
Number range FBs 0 ... 1023
Number of FCs 1024
2-10 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14
Order no. 215-2CM03

Maximum FC size 16 KB
Number range FCs 0 ... 1023
Maximum nesting depth per priority class 8
Maximum nesting depth additional within an error 1
OB
Time
Real-time clock buffered 9
Clock buffered period (min.) 30 d
Type of buffering Vanadium Rechargeable
Lithium Batterie
Accuracy (max. deviation per day) 10 s
Number of operating hours counter 8
Clock synchronization -
Synchronization via MPI -
Synchronization via Ethernet (NTP) -
Address areas (I/O)
Input I/O address area 1024 Byte
Output I/O address area 1024 Byte
Process image adjustable -
Input process image preset 128 Byte
Output process image preset 128 Byte
Input process image maximal 128 Byte
Output process image maximal 128 Byte
Digital inputs 8192
Digital outputs 8192
Digital inputs central 512
Digital outputs central 512
Integrated digital inputs -
Integrated digital outputs -
Analog inputs 512
Analog outputs 512
Analog inputs, central 128
Analog outputs, central 128
Integrated analog inputs -
Integrated analog outputs -
Communication functions
PG/OP channel 9
Number of GD circuits, max. 4
Size of GD packets, max. 22 Byte
S7 basic communication, user data per job 76 Byte
S7 communication 9
S7 communication, user data per job 160 Byte
Functionality Sub-D interfaces
Type MP²I
Type of interface RS485
Connector Sub-D, 9-pin, female
Electrically isolated -
MPI 9
MP²I (MPI/RS232) 9
DP master -
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 2-11

Order no. 215-2CM03

DP slave -
Type CAN
Type of interface CAN
Connector Sub-D, 9-pin, male
Electrically isolated 9
MPI -
MP²I (MPI/RS232) -
DP master -
DP slave -
Functionality MPI
PG/OP channel 9
Routing -
S7 communication 9
Transmission speed, min. 19.2 kbit/s
Transmission speed, max. 187.5 kbit/s
Datasizes
Input bytes 0
Output bytes 0
Parameter bytes 3
Diagnostic bytes 0
Housing
Material PPE / PA 6.6
Mounting Profile rail 35 mm
Mechanical data
Dimensions (WxHxD) 50.8 x 76 x 80 mm
Weight 150 g
Environmental conditions
Operating temperature 0 °C to 60 °C
Storage temperature -25 °C to 70 °C
Certifications
UL508 certification yes
2-12 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Manual VIPA System 200V Chapter 3 Deployment CPU 21x-2CM03
Chapter 3 Deployment CPU 21x-2CM03
Overview This chapter describes the deployment of the CPU in the System 200V.
The description refers directly to the CPU and to the deployment in
connection with peripheral modules, mounted on a profile rail together with
the CPU at the backplane bus.
Content Topic Page

Chapter 3 Deployment CPU 21x-2CM03.......................................... 3-1
Assembly.............................................................................................. 3-2
Start-up behavior.................................................................................. 3-2
Addressing ........................................................................................... 3-3
Hints for the deployment of the MPI interface....................................... 3-5
Hardware configuration - CPU.............................................................. 3-6
Hardware configuration - I/O modules .................................................. 3-8
Setting CPU parameters ...................................................................... 3-9
Project transfer................................................................................... 3-13
Operating modes................................................................................ 3-17
Firmware update ................................................................................ 3-19
Factory reset ...................................................................................... 3-21
VIPA specific diagnostic entries ......................................................... 3-22
Using test functions for control and monitoring of variables................ 3-24
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3-1

Chapter 3 Deployment CPU 21x-2CM03 Manual VIPA System 200V
Assembly
Note!
Information about assembly and cabling may be found at chapter "Basics
and Assembly".
Start-up behavior
Turn on power When the CPU is delivered it has been reset. After the power supply has
supply been switched on, the CPU changes to the operating mode the operating
mode lever shows. After a STOP→RUN transition the CPU switches to
RUN without program.
Note!
Due to a long storage of the CPU, the battery may be discharged
excessively. Please connect the CPU at least for 24 hours to the power
supply, to achieve the full buffer capacity.
Boot procedure with The CPU switches to RUN with the program stored in the battery buffered
valid data in the CPU RAM.
Boot procedure The accumulator/battery is automatically loaded via the integrated power
with empty battery supply and guarantees a buffer for max. 30 days. If this time is exceeded,
the battery may be totally discharged. This means that the battery buffered
RAM is deleted.
In this state, the CPU executes an overall reset because with an empty
battery the RAM content is undefined. If a MMC with a S7PROG.WLD is
plugged, program code and data blocks are transferred from the MMC into
the work memory of the CPU.
If there is no MMC, the project from the internal Flash is loaded.
Depending on the position of the operating mode switch, the CPU remains
in STOP respectively switches to RUN. Due to the battery error the CPU
can only boot if there was an OB81 configured. Otherwise a manual restart
(STOP/RUN) respectively PG command is necessary.
On a start-up with an empty battery the SF LED is on and thus points to an
entry in the diagnostic buffer. Information about the Event-IDs can be found
at "VIPA specific diagnostic entries".
Attention!
After a power reset and with an empty battery the CPU starts with a BAT
error and executes an overall reset.
3-2 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Addressing
Automatic To provide specific addressing of the installed peripheral modules, certain

addressing addresses must be allocated in the CPU.
The CPU contains a peripheral area (addresses 0 ... 1023) and a process
image of the inputs and the outputs (for both each address 0 ... 127).
When the CPU is initialized it automatically assigns peripheral addresses to
the digital input/output modules starting from 0.
If there is no hardware projecting, analog modules are allocated to even
addresses starting from address 128.
Signaling states in The signaling states of the lower addresses (0 ... 127) are additionally
the process image saved in a special memory area called the process image.
The process image is divided into two parts:
• process image of the inputs (PII)
• process image of the outputs (PIQ)
Peripheral area Process image

0 0
. .
. Digital modules . Inputs
. . PII
127 127
128 0
. .
. Analog modules .
Outputs
. . PIQ
1023 127
The process image is updated automatically when a cycle has been

completed.
Read/write access You may access the modules by means of read or write operations on the
peripheral bytes or on the process image.
Note!
Please remember that you may access different modules by means of read
and write operations on the same address.
The addressing ranges of digital and analog modules are different when
they are addressed automatically.
Digital modules: 0 ... 127
Analog modules: 128 ... 1023
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3-3

Example for auto- The following figure illustrates the automatic allocation of addresses:
matic address
allocation
Slot: 1 2 3 4 5 6
DIO 8xDC24V
DO 8xDC24V
DI 16xDC24V
DI 8xDC24V
AO 4x12Bit
AI 4x12Bit
CPU 21x
PII rel. Addr. Peripheral area Peripheral area rel. Addr PIQ
0 Input byte 0 Output byte 0 0
. . . .
. . . .
. . . .

analog digital
analog digital
. .
. .. .. .. .
. . .
. .

. .
. .. .. .
. .
. .
Modifying allocated You may change the allocated addresses at any time by means of the
addresses by Siemens SIMATIC manager. In this way you may also change the addres-
configuration ses of analog modules to the range covered by the process image
(0 ... 127) and address digital modules above 127.
The following pages describe the required preparations and the procedure
for this type of configuration.
3-4 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Hints for the deployment of the MPI interface
2 2
What is MP I? The MP I jack combines 2 interfaces in 1:
• MP interface
• RS232 interface
Please regard that the RS232 functionality is only available by using the
Green Cable from VIPA.
Deployment as The MP interface provides the data transfer between CPUs and PCs. In a
MP interface bus communication you may transfer programs and data between the
CPUs interconnected via MPI.
Connecting a common MPI cable, the MPI jack supports the full MPI
functionality.
Important notes for the deployment of MPI cables!

Deploying MPI cables at the CPUs from VIPA, you have to make sure that
Pin 1 is not connected. This may cause transfer problems and in some
cases damage the CPU!
Especially PROFIBUS cables from Siemens, like e.g. the
2
6XV1 830-1CH30, must not be deployed at MP I jack.
For damages caused by nonobservance of these notes and at improper
deployment, VIPA does not take liability!
Deployment as For the serial data transfer from your PC, you normally need a MPI
RS232 interface only transducer. Fortunately you may also use the "Green Cable" from VIPA.
via "Green Cable" You can order this under the order no. VIPA 950-0KB00.
The "Green Cable" supports a serial point-to-point connection for data

2
transfer via the MP I jack exclusively for VIPA CPUs.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3-5

Hardware configuration - CPU
Overview For the project engineering of the CPU 21x and the other System 200V
modules connected to the same VIPA bus, the hardware configurator from
Siemens is to be used.
To address the directly plugged peripheral modules, you have to assign a
special address in the CPU to every module.
The address allocation and the parameterization of the modules takes
place in the Siemens SIMATIC manager as a virtual PROFIBUS system.
For the PROFIBUS interface is standardized software sided, the
functionality is guaranteed by including a GSD-file into the Siemens
SIMATIC manager.
Transfer your project into the CPU via the MPI interface.
Requirements The following conditions must be fulfilled for project engineering:

• The Siemens SIMATIC manager is installed at PC respectively PU
• The GSD files have been included in Siemens hardware configurator
• Serial connection to the CPU (e.g. MPI-Adapter)
Note!
The configuration of the CPU requires a thorough knowledge of the
Siemens SIMATIC manager and the hardware configurator!
Including the • Go to www.vipa.com > Service > Download > PROFIBUS GSD files and
GSD-file download the file System_100V_-_200V_Vxxx.zip.
• Extract the file to your work directory. The vipa_21x.gsd (German)
respectively vipa_21x.gse (English) can be found at the directory
CPU21x.
• Start the Siemens hardware configurator and close every project.
• Go to Options > Install new GSD file
• Navigate to the directory CPU21x and choose the corresponding file
vipa_21x.gsd (German) or vipa_21x.gse (English)
Now the modules of the VIPA System 200V are integrated in the hardware
catalog at PROFIBUS-DP \ Additional field devices \ I/O \
VIPA_System_200V.
3-6 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Proceeding To be compatible with the Siemens SIMATIC manager the following steps
should be executed:
• Start the hardware configurator from

Slot Module
PROFIBUS (1): DP master system (1) Siemens with a new project.
1
2
X2
CPU 315-2DP
DP
• Insert a profile rail from the hardware
3 catalog.
PB- (1) VIPA_CPU • Place at slot 2 the following CPU from
Addr.:2 PB- Siemens:
CPU 21x
Addr.:1 CPU 214
R
S
MMC
RN
ST
MR
CPU 315-2DP (315-2AF03 0AB00 V1.2)

PW
SF
FC 2
MC
• For the System 200V create a new

PROFIBUS subnet.
• Attach the slave system
"VIPA_CPU21x" to the subnet with
PROFIBUS-Address 1.
After installing the vipa_21x.gsd the
Slot Module slave system may be found at the
0 CPU 21x-2CM03 hardware catalog at PROFIBUS DP >
1 Additional field devices > IO >
... VIPA_System_200V.
• Place always at the 1. slot the
corresponding CPU 21x-2CM03, by
taking it from the hardware catalog.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3-7

Hardware configuration - I/O modules
Hardware After the hardware configuration of the CPU place the System 200V
configuration of modules in the plugged sequence.
the modules In order to address the installed peripheral modules individually, specific
addresses in the CPU have to be assigned to them.
Slot Module
1
2 CPU 315-2DP PROFIBUS (1): DP master system (1)
X2 DP
3
PB- (1) VIPA_CPU

Addr.:2 PB-
CPU 21x
Addr.:1 CPU 214
R
S
RN
MR
MMC
ST
PW
SF
FC 2
MC
DIO 8xDC24V
DO 8xDC24V
DI 8xDC24V
Parameter DIO
AO 4x12Bit
AI 4x12Bit
Param : ......... Param : .........

Param : ......... Param : .........
Param : ......... Param : .........
CPU 21x Slot Modul Param : ......... Param : .........
1 CPU
2 DI
3 DO
4 DIO
5 AI
6 AO
7
8
...
Parameterization For parameterization double-click during the project engineering at the slot
overview on the module you want to parameterize. In the appearing dialog
window you may set the wanted parameters.
Parameterization By using the SFCs 55, 56 and 57 you may alter and transfer parameters
during runtime for wanted modules during runtime.
For this you have to store the module specific parameters in so called
"record sets".
More detailed information about the structure of the record sets is to find in
the according module description.
3-8 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Setting CPU parameters
Parameterization Since the CPU from VIPA is to be configured as Siemens CPU 315-2DP
via Siemens (315-2AF03 0AB00 V1.2) in the Siemens hardware configurator, the
CPU 315-2AF03 parameters of the VIPA CPU may be set with "Object properties" of the
CPU 315-2DP during hardware configuration.
Via a double-click on the CPU 315-2DP the parameter window of the CPU
may be accessed.
Using the registers you get access to every standard parameter of the
CPU.
Parameter CPU
Slot Module Param : ......... Param : .........

1 Param : ......... Param : .........
2 CPU 315-2DP Param : ......... Param : .........
X2 DP Param : ......... Param : .........
3
(1) VIPA_CPU
CPU 21x
CPU 214
RN
R ST
S MR
MMC
PW
SF
FC
2
MC
Supported The CPU does not evaluate each parameter, which may be set at the
parameters hardware configuration.
The following parameters are supported by the CPU at this time:
General
Short description The short description of the Siemens CPU 315-2AF03 is CPU 315-2DP.
Order No. / Order number and firmware are identical to the details in the "hardware
Firmware catalog" window.
Name The Name field provides the short description of the CPU. If you change
the name the new name appears in the Siemens SIMATIC manager.
Comment In this field information about the module may be entered.
Startup
Startup when If the checkbox for "Startup when expected/actual configuration differ" is
expected/actual deselected and at least one module is not located at its configured slot or if
another type of module is inserted there instead, then the CPU does not
configuration differs
switch to RUN mode and remains in STOP mode.
If the checkbox for "Startup when expected/actual configuration differ" is
selected, then the CPU starts even if there are modules not located in their
configured slots of if another type of module is inserted there instead, such
as during an initial system start-up.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3-9
Monitoring time for This operation specifies the maximum time for the ready message of every
ready message by configured module after PowerON. Here connected PROFIBUS DP slaves
modules [100ms] are also considered until they are parameterized. If the modules do not
send a ready message to the CPU by the time the monitoring time has
expired, the actual configuration becomes unequal to the preset
configuration.
Monitoring time for The maximum time for the transfer of parameters to parameterizable
transfer of modules. If not every module has been assigned parameters by the time
parameters to this monitoring time has expired; the actual configuration becomes unequal
modules [100ms] to the preset configuration.
Cycle/Clock
memory
Update OB1 This parameter is not relevant.
process image
cyclically
Scan cycle Here the scan cycle monitoring time in milliseconds may be set. If the scan
monitoring time cycle time exceeds the scan cycle monitoring time, the CPU enters the
STOP mode. Possible reasons for exceeding the time are:
• Communication processes
• a series of interrupt events
• an error in the CPU program
Minimum scan This parameter is not relevant.

cycle time
Scan cycle load Using this parameter you can control the duration of communication
from Communi- processes, which always extend the scan cycle time so it does not exceed
cation a specified length.
If the cycle load from communication is set to 50%, the scan cycle time of
OB 1 can be doubled. At the same time, the scan cycle time of OB 1 is still
being influenced by asynchronous events (e.g. hardware interrupts) as
well.
OB85 call up at I/O The preset reaction of the CPU may be changed to an I/O access error that
access error occurs during the update of the process image by the system.
The VIPA CPU is preset such that OB 85 is not called if an I/O access error
occurs and no entry is made in the diagnostic buffer either.
Clock memory Activate the check box if you want to use clock memory and enter the
number of the memory byte.
Note!
The selected memory byte cannot be used for temporary data storage.
3-10 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Retentive Memory
Number of Memory Enter the number of retentive memory bytes from memory byte 0 onwards.
Bytes from MB0
Number of S7 Enter the number of retentive S7 timers from T0 onwards. Each S7 timer
Timers from T0 occupies 2bytes.
Number of S7 Enter the number of retentive S7 counter from C0 onwards.

Counters from C0
Areas These parameters are not relevant.
Interrupts
Priority Here the priorities are displayed, according to which the hardware interrupt
OBs are processed (hardware interrupt, time-delay interrupt, async. error
interrupts).
Time-of-day
interrupts
Priority Here the priorities may be specified according to which the time-of-day
interrupt is processed.
With priority "0" the corresponding OB is deactivated.
Active Activate the check box of the time-of-day interrupt OBs if these are to be
automatically started on complete restart.
Execution Select how often the interrupts are to be triggered. Intervals ranging from
every minute to yearly are available. The intervals apply to the settings
made for start date and time.
Start date / time Enter date and time of the first execution of the time-of-day interrupt.
Process image This parameter is not supported.

partition
Cyclic interrupts
Priority Here the priorities may be specified according to which the corresponding
cyclic interrupt is processed. With priority "0" the corresponding interrupt is
deactivated.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3-11

Execution Enter the time intervals in ms, in which the watchdog interrupt OBs should
be processed. The start time for the clock is when the operating mode
switch is moved from STOP to RUN.
Phase offset Enter the delay time in ms for current execution for the watch dog interrupt.
This should be performed if several watchdog interrupts are enabled.
Phase offset allows to distribute processing time for watchdog interrupts
across the cycle.
Process image This parameter is not supported.

partition
Protection
Level of protection Here 1 of 3 protection levels may be set to protect the CPU from
unauthorized access.
Protection level 1 (default setting):
• No password adjustable, no restrictions
Protection level 2 with password:
• Authorized users: read and write access
• Unauthorized user: read access only
Protection level 3:
• Authorized users: read and write access
• Unauthorized user: no read and write access
3-12 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Project transfer
Overview There are the following possibilities for project transfer into the CPU:
• Transfer via MPI
• Transfer via MMC when using a MMC programmer
Transfer via MPI The structure of a MPI net is electrically identical with the structure of a
PROFIBUS net. This means the same rules are valid and you use the
same components for the build-up. The single participants are connected
with each other via bus interface plugs and PROFIBUS cables. Per default
the MPI net runs with 187.5kbaud. VIPA CPUs are delivered with MPI
address 2.
MPI programming The MPI programming cables are available at VIPA in different variants.
cable The cables provide a RS232 res. USB plug for the PC and a bus enabled
RS485 plug for the CPU.
Due to the RS485 connection you may plug the MPI programming cables
directly to an already plugged plug on the RS485 jack. Every bus
participant identifies itself at the bus with an unique address, in the course
of the address 0 is reserved for programming devices.
Terminating resistor A cable has to be terminated with its surge impedance. For this you switch
on the terminating resistor at the first and the last participant of a network
or a segment.
Please make sure that the participants with the activated terminating
resistors are always power supplied. Otherwise it may cause interferences
on the bus.
Transfer with MPI programming cable (MPI communication)
STEP7
from Siemens
VIPA
USB-MPI Ad apter
M PI
Erro r
Active
Power
Terminating MPI net Terminating

USB
VIPA 950 -0 KB31
MPI programming cable
Transfer via Green Cable (serial communication)

Via exclusively direct plugging of the Green Cable to a MP2I jack you may
establish a serial connection between PC and CPU. Set the PC-COM port
and the transfer rate 38400Baud at Local port. The settings of the register
MPI are ignored at employment of the Green Cable.
STEP7
from Siemens
MPI net
Green Cable
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3-13

Configure MPI Hints for configuring a MPI interface are to find in the documentation of
your programming software.
The "Green Cable" has the order number VIPA 950-0KB00.
Attention!
Please regard, that you may use the "Green Cable" exclusively at VIPA
2
CPUs with MP I-interface!
Please regard the hints for deploying the Green Cable and the MP2I jack!
Approach transfer • Connect your PC to the MPI jack of your CPU via a MPI programming
via MPI interface cable.
• Load your project in the SIMATIC manager from Siemens.
• Choose in the menu Options > Set PG/PC interface
• Select in the according list the "PC Adapter (MPI)"; if appropriate you
have to add it first, then click on [Properties].
• Set in the register MPI the transfer parameters of your MPI net and type
a valid address.
• Switch to the register Local connection
• Set the COM port of the PC and the transfer rate 38400Baud for the
MPI programming cable from VIPA.
• Via PLC > Load to module you may transfer your project via MPI to the
CPU and save it on a MMC via PLC > Copy RAM to ROM if one is
plugged.
Note!
Please make sure to adjust the transfer rate to 38400Baud when using the
"Green Cable" from VIPA.
3-14 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Hints for the The Green Cable is a green connection cable, manufactured exclusively for
Green Cable the deployment at VIPA System components.
The Green Cable is a programming and download cable for VIPA CPUs
2
MP I jack and VIPA field bus masters. The Green Cable from VIPA is
available under the order no. VIPA 950-0KB00.
The Green Cable allows you to:

• transfer projects serial
Avoiding high hardware needs (MPI transducer, etc.) you may realize a
2
serial point-to-point connection via the Green Cable and the MP I jack.
This allows you to connect components to your VIPA-CPU that are able
to communicate serial via a MPI adapter like e.g. a visualization
system.
• execute firmware updates of the CPUs and field bus masters
Via the Green Cable and an upload application you may update the
2
firmware of all recent VIPA CPUs with MP I jack and certain field bus
masters (see Note).
Important notes for the deployment of the Green Cable

Nonobservance of the following notes may cause damages on system
components.
For damages caused by nonobservance of the following notes and at
improper deployment, VIPA does not take liability!
Note to the application area

The Green Cable may exclusively deployed directly at the concerning jacks
of the VIPA components (in between plugs are not permitted). E.g. a MPI
cable has to be disconnected if you want to connect a Green Cable.
At this time, the following components support Green Cable:
2
VIPA CPUs with MP I jack and field bus masters from VIPA.
Note to the lengthening

The lengthening of the Green Cable with another Green Cable res. The
combination with further MPI cables is not permitted and causes damages
of the connected components!
The Green Cable may only be lengthened with a 1:1 cable
(all 9 pins are connected 1:1).
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3-15

Transfer via The MMC (Memory Card) serves as external transfer and storage medium.
MMC There may be stored several projects and sub-directories on a MMC
storage module. Please regard that your current project is stored in the root
directory and has one of the following file names:
• S7PROG.WLD
• S7PROGF.WLD
• AUTOLOAD.WLD
With File > Memory Card File > New in the Siemens SIMATIC manager a
new wld file may be created. After the creation copy the blocks from the
project blocks folder and the System data into the wld file.
Transfer The transfer of the application program from the MMC into the CPU takes
MMC → CPU place depending on the file name after an overall reset or PowerON.
• S7PROG.WLD is read from the MMC after overall reset and transferred
into the battery buffered RAM.
• S7PROGF.WLD is read from the MMC after overall reset and
transferred into the battery buffered RAM and additionally into the Flash
memory. An access to the Flash memory only takes place at empty
battery of the buffer and when no MMC with user program is plugged-in.
• AUTOLOAD.WLD is read after PowerON from the MMC and transferred
into the battery-buffered RAM .
During the transfer the "MC" LED blinks. Please regard that your user
memory serves for enough space, otherwise your user program is not
completely loaded and the SF LED gets on. Execute a compression before
the transfer, for this does not happen automatically.
Transfer When the MMC has been installed, the write command stores the content
CPU → MMC of the battery buffered RAM as S7PROG.WLD on the MMC and in the
internal Flash memory.
The write command is controlled by means of the block area of the
Siemens SIMATIC manager PLC > Copy RAM to ROM. During the write
process the "MC"-LED of the CPU is blinking. When the LED expires the
write process is finished.
If this project is to be loaded automatically from the MMC with PowerON,
you have to rename this on the MMC to AUTOLOAD.WLD.
Transfer control After a MMC access, an ID is written into the diagnostic buffer of the CPU.
To monitor the diagnosis entries, you select PLC > Module Information in
the Siemens SIMATIC manager. Via the register "Diagnostic Buffer" you
reach the diagnosis window.
Information about the Event-IDs can be found at "VIPA specific diagnostic
entries".
3-16 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Operating modes
Overview The CPU can be in one of 3 operating modes:

• Operating mode STOP
• Operating mode START-UP
• Operating mode RUN
Certain conditions in the operating modes START-UP and RUN require a

specific reaction from the system program. In this case the application
interface is often provided by a call to an organization block that was
included specifically for this event.
Operating mode • The application program is not processed.

STOP • If there has been a processing before, the values of counters, timers,
flags and the process image are retained during the transition to the
STOP mode.
• Outputs are inhibited, i.e. all digital outputs are disabled.
• RUN-LED (R) off
• STOP-LED (S) on
Operating mode • During the transition from STOP to RUN the system calls the start-up
START-UP organization block OB 100. The processing time for this OB is not
monitored. The start-up OB may issue calls to other blocks.
• All digital outputs are disabled during the start-up, i.e. outputs are
inhibited.
• RUN-LED blinks as soon as the OB 100 is operated and for at least
3s, even if the start-up time is shorter or the CPU gets to
STOP due to an error. This indicates the start-up.
• STOP-LED off
When the CPU has completed the start-up OB, it assumes the operating
mode RUN.
Operating mode • The application program in OB 1 is processed in a cycle. Under the

RUN control of alarms other program sections can be included in the cycle.
• All timers and counters being started by the program are active and the
process image is updated with every cycle.
• The BASP-signal (outputs inhibited) is deactivated, i.e. all digital outputs
are enabled.
• RUN-LED on
• STOP-LED off
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3-17

Function security The CPUs include security mechanisms like a watchdog (100ms) and a
parameterizable cycle time surveillance (parameterizable min. 1ms) that
stop res. execute a RESET at the CPU in case of an error and set it into a
defined STOP state.
The VIPA CPUs are developed function secure and have the following
system properties:
Event concerns Effect

RUN → STOP general BASP (Befehls-Ausgabe-Sperre, i.e. command
output lock) is set.
central digital outputs The outputs are disabled.
central analog outputs The Outputs are disabled.
- Voltage outputs issue 0V
- Current outputs 0...20mA issue 0mA
- Current outputs 4...20mA issue 4mA
If configured also substitute values may be
issued.
decentral outputs Same behavior as the central digital/analog
outputs.
decentral inputs The inputs are cyclically be read by the decentra-
lized station and the recent values are put at
disposal.
STOP → RUN general First the PII is deleted, then OB 100 is called. After
res. PowerON the execution of the OB, the BASP is reset and
the cycle starts with:
Delete PIO → Read PII → OB 1.
central analog outputs The behavior of the outputs at restart can be
preset.
decentral inputs The inputs are cyclically be read by the decentra-
lized station and the recent values are put at
disposal.
RUN general The program execution happens cyclically and can
therefore be foreseen:
Read PII → OB 1 → Write PIO.
PII = Process image inputs

PIO = Process image outputs
3-18 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Firmware update
Overview There is the opportunity to execute a firmware update for the CPU and its
components via MMC. For this an accordingly prepared MMC must be in
the CPU during the startup.
So a firmware files can be recognized and assigned with startup, a file
name is reserved for each updateable component (see table below).
After PowerON and CPU STOP the CPU checks if there is a firmware file
on the MMC. If this firmware version is different to the existing firmware
version, this is indicated by blinking of the LEDs and the firmware may be
installed by an update request.
Latest Firmware at The latest firmware versions are to be found in the service area at
www.vipa.com www.vipa.com
Find out CPU A label on the rear of the module indicates the firmware version.
firmware version You may display the current firmware version of your CPU via the Siemens
SIMATIC manager. To display the firmware version, you go online with the
CPU via your PG or PC and start the Siemens SIMATIC manager.
Via PLC > Module status, register "General", the current firmware version
is evaluated and displayed.
Load firmware and • Go to www.vipa.com

transfer it to MMC • Click on Service > Download > Firmware.
with reserved file
• Navigate to via System 200V > CPU to your CPU and download
name
according to your hardware version the zip file to your PC.
• Open the zip file and copy the bin files to your MMC.
• Rename this accordingly
Reserved file By means of a reserved file name in the CPU 21x-2CM03 you may transfer
names a firmware per MMC:
Component File name New file name

order no._release_version.ZIP at MMC
CPU Bx000... .bin firmware.bin
CANopen Bx000... .bin can00.bin
master
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3-19

Attention!
When installing a new firmware you have to be extremely careful. Under
certain circumstances you may destroy the CPU, for example if the voltage
supply is interrupted during transfer or if the firmware file is defective.
In this case, please call the VIPA-Hotline!
Please regard that the version of the update firmware has to be different
from the existing firmware otherwise no update is executed.
Transfer firmware 1. Switch the operating mode switch of your CPU in position ST. Turn off
from MMC into the voltage supply. Plug the MMC with the firmware files into the CPU.
CPU Please take care of the correct plug-in direction of the MMC. Turn on
the voltage supply.
2. After a short boot-up time, the alternate blinking of the LEDs SF and
FC shows that at least a differing firmware file was found on the MMC.
3. You start the transfer of the firmware as soon as you tip the operating
mode switch lever downwards to MR within 10s and leave it in ST
position.
4. During the update process, the LEDs SF and FC are alternately
blinking and MC LED is on. This may last several minutes.
5. The update is successful finished when the LEDs PW, S, SF, FC and
MC are on. If they are blinking fast, an error occurred.
6. Turn Power OFF and ON. Now it is checked by the CPU, whether
further current firmware versions are available at the MMC. If so, again
the LEDs SF and FC flash after a short start-up period. Continue with
point 3.
If the LEDs do not flash, the firmware update is ready.
Now a factory reset should be executed (see next page). After that the
CPU is ready for duty.
1 2 3 4 5 6
Preparation Firmware Start update Update runs Update Error

recognized terminates
RN at MMC error free
ST R R R R R R
S S S S S S
MR
PW PW PW PW PW PW
Tip RN RN
SF SF SF SF SF SF
MMC stecken ST
FC FC ST FC FC FC FC Power
MC MC MR MR MC MC MC MC OFF/ON
Power OFF/ON 10 Sec.
3-20 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Factory reset
Proceeding With the following proceeding the internal RAM of the CPU is completely
deleted and the CPU is reset to delivery state.
Please note that here also the MPI address is reset to the address 2!
1. Switch the CPU to STOP.

2. Push the operating mode switch down to position MR for 30s. Here the
S LED flashes. After a few seconds the stop LED changes to static
light. Now the S LED changes between static light and flashing.
Starting here count the static light states of the S LED.
3. After the 6. static light release the operating mode switch and tip it
downwards to MR. Now the RUN LED lights up once. This means that
the RAM was deleted completely.
4. For the confirmation of the resetting procedure the LEDs PW and S are
on.
5. Then you have to switch the power supply off and on.
The proceeding is shown in the following Illustration:
1 2 3 4 5
CPU in Request factory reset Start factory reset Factory reset

STOP executed
R R R R R
S S S S S
PW
Tip RN
PW
6x PW
RN Tip RN
PW PW
SF SF SF SF SF
ST ST ST
FC FC FC FC FC Power
MC MR MC MC MR MR MC MC OFF/ON
30 Sec. 1 Sec.
Note!
After the firmware update you always should execute a Factory reset.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3-21

VIPA specific diagnostic entries
Entries in the You may read the diagnostic buffer of the CPU via the Siemens SIMATIC
diagnostic buffer manager. Besides of the standard entries in the diagnostic buffer, the VIPA
CPUs support some additional specific entries in form of event-IDs.
Monitoring the To monitor the diagnostic entries you choose the option PLC > Module
diagnostic entries Information in the Siemens SIMATIC manager. Via the register "Diagnostic
Buffer" you reach the diagnostic window:
Module information
Path: Accessible Nodes MPI = 2 Operating mode CPU: RUN

... Diagnostic Buffer ... ... ... ... ...
Nr. Time of day Date Event

8 ... ... ...
9 ... ... ...
10 13:18:11:370 19.12.2011 Event-ID: 16# E0CC
11 ... ... ...
12 ... ... ...
13 ... ... ... VIPA-ID
Details:
...
... ... ... ...
The diagnosis is independent from the operating mode of the CPU. You
may store a max. of 100 diagnostic entries in the CPU.
The following page shows an overview of the VIPA specific Event-IDs.
3-22 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Overview of the
Event-IDs
Event-ID Description
0xE003 Error at access to I/O devices
Zinfo1: I/O address
Zinfo2: Slot
0xE004 Multiple parameterization of a I/O address
Zinfo1: I/O address
Zinfo2: Slot
0xE005 Internal error – Please contact the VIPA-Hotline!
0xE007 Configured in-/output bytes do not fit into I/O area
0xE009 Error at access to standard back plane bus
0xE010 Not defined module group at backplane bus recognized
Zinfo2: Slot
Zinfo3: Type ID
0xE011 Master project engineering at Slave-CPU not possible or wrong slave configuration
0xE012 Error at parameterization
0xE013 Error at shift register access to VBUS digital modules
0xE014 Error at Check_Sys
0xE015 Error at access to the master
Zinfo2: Slot of the master (32=page frame master)
0xE016 Maximum block size at master transfer exceeded
Zinfo1: I/O address
Zinfo2: Slot
0xE017 Error at access to integrated slave
0xE018 Error at mapping of the master I/O devices
0xE019 Error at standard back plane bus system recognition
0xE01A Error at recognition of the operating mode (8 / 9 Bit)
0xE0CC Communication error MPI / Serial
0xE100 MMC access error

0xE101 MMC error file system
0xE102 MMC error FAT
0xE104 MMC error at saving
0xE200 MMC writing finished (Copy Ram to Rom)
0xE210 MMC reading finished (reload after overall reset)
0xE300 Internal Flash writing ready (Copy RAM to ROM)
0xE310 Internal Flash reading finished (reload after battery failure)
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3-23

Using test functions for control and monitoring of variables
Overview For troubleshooting purposes and to display the status of certain variables
you can access certain test functions via the menu item Debug of the
Siemens SIMATIC manager.
The status of the operands and the VKE can be displayed by means of the
test function Debug > Monitor.
You can modify and/or display the status of variables by means of the test
function PLC > Monitor/Modify Variables.
Debug > Monitor This test function displays the current status and the VKE of the different
operands while the program is being executed.
It is also possible to enter corrections to the program.
Note!
When using the test function “Monitor” the PLC must be in RUN mode!
The processing of the states may be interrupted by means of jump

commands or by timer and process-related alarms. At the breakpoint the
CPU stops collecting data for the status display and instead of the required
data it only provides the PG with data containing the value 0.
For this reason, jumps or time and process alarms can result in the value
displayed during program execution remaining at 0 for the items below:
• the result of the logical operation VKE

• Status / AKKU 1
• AKKU 2
• Condition byte
• absolute memory address SAZ. In this case SAZ is followed by a "?".
The interruption of the processing of statuses does not change the

execution of the program. It only shows that the data displayed is no
longer.
3-24 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

PLC > This test function returns the condition of a selected operand (inputs,
Monitor/Modify outputs, flags, data word, counters or timers) at the end of program-
Variables execution.
This information is obtained from the process image of the selected
operands. During the "processing check" or in operating mode STOP the
periphery is read directly from the inputs. Otherwise only the process
image of the selected operands is displayed.
Control of outputs
It is possible to check the wiring and proper operation of output-modules.
You can set outputs to any desired status with or without a control
program. The process image is not modified but outputs are no longer
inhibited.
Control of variables
The following variables may be modified:
I, Q, M, T, C and D.
The process image of binary and digital operands is modified
independently of the operating mode of the CPU.
When the operating mode is RUN the program is executed with the
modified process variable. When the program continues they may,
however, be modified again without notification.
Process variables are controlled asynchronously to the execution sequence
of the program.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3-25

3-26 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Manual VIPA System 200V Chapter 4 CANopen communication
Chapter 4 CANopen communication
Overview Content of this chapter is the Deployment of the 21x-2CM03 under

CANopen. Here you’ll find all information required for the usage of the
integrated CAN master.
Content Topic Page

Chapter 4 CANopen communication .............................................. 4-1
Principles CAN bus .............................................................................. 4-2
Project engineering of the CPU 21x-2CM03......................................... 4-4
Modes ................................................................................................ 4-13
Process image of the CPU 21x-2CM03.............................................. 4-14
CANopen - Messages ........................................................................ 4-16
Object directory .................................................................................. 4-21
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-1

Chapter 4 CANopen communication Manual VIPA System 200V
Principles CAN bus
General The CAN bus (Control Area Network) is an international standard for open
field bus systems intended for building, manufacturing and process
automation applications that was originally designed for automotive
applications.
Due to its extensive error detection facilities, the CAN bus system is
regarded as the most secure bus system. It has a residual error probability
-11
of less than 4.7x10 . Bad messages are flagged and retransmitted
automatically.
In contrast to PROFIBUS and INTERBUS-S, CAN defines under the CAL-
level-7-protocol (CAL=CAN application layer) defines various level-7 user
profiles for the CAN bus. One standard user profile defined by the CIA
(CAN in Automation) e.V. is CANopen.
CANopen CANopen is a user profile for industrial real-time systems, which is

currently supported by a large number of manufacturers. CANopen was
published under the heading of DS-301 by the CAN in Automation
association (CIA). The communication specifications DS-301 define
standards for CAN devices. These specifications mean that the equipment
supplied by different manufacturers is interchangeable. The compatibility of
the equipment is further enhanced by the equipment specification DS-401
that defines standards for the technical data and process data of the
equipment. DS-401 contains the standards for digital and analog
input/output modules.
CANopen comprises a communication profile that defines the objects that
must be used for the transfer of certain data as well as the device profiles
that specify the type of data that must be transferred by means of other
objects.
The CANopen communication profile is based upon an object directory that
is similar to the profile used by PROFIBUS. The communication profile DS-
301 defines two standard objects as well as a number of special objects:
• Process data objects (PDO)

PDOs are used for real-time data transfers
• Service data objects (SDO)
SDOs provide access to the object directory for read and write
operations
4-2 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Communication CAN is based on a linear bus topology. You can use router nodes to
medium construct a network. The number of devices per network is only limited by
the performance of the bus driver modules.
The maximum distance covered by the network is determined by the
runtimes of the signals. This means that a data rate of 1Mbaud limits the
network to 40m and 80kBaud limits the network to 1000m.
The CAN bus communication medium employs a screened three-core
cable (optionally a five-core).
The CAN bus operates by means of differential voltages. For this reason it
is less sensitive to external interference than a pure voltage or current
based interface. The network must be configured as a serial bus, which is
terminated by a 120Ω terminating resistor.
Your VIPA CAN bus coupler contains a 9pin socket. You must use this
socket to connect the CAN bus coupler as a slave directly to your CAN bus
network.
All devices on the network use the same baud rate.
Due to the bus structure of the network it is possible to connect or
disconnect any station without interruption to the system. It is therefore also
possible to commission a system in various stages. Extensions to the
system do not affect the operational stations. Defective stations or new
stations are recognized automatically.
Bus access Bus access methods are commonly divided into controlled (deterministic)
method and uncontrolled (random) bus access systems.
CAN employs a Carrier-Sense Multiple Access (CSMA) method, i.e. all
stations have the same right to access the bus as long as the bus is not in
use (random bus access).
Data communications is message related and not station related. Every
message contains a unique identifier, which also defines the priority of the
message. At any instance only one station can occupy the bus for a
message.
CAN bus access control is performed by means of a collision-free, bit-
based arbitration algorithm. Collision-free means that the final winner of the
arbitration process does not have to repeat his message. The station with
the highest priority is selected automatically when more than one station
accesses the bus simultaneously. Any station that is has information to
send will delay the transmission if it detects that the bus is occupied.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-3

Project engineering of the CPU 21x-2CM03

Overview The project engineering of the CANopen master happens in WinCoCT
(Windows CANopen Configuration Tool) from VIPA. You export your
project from WinCoCT as wld-file. This wld-file can then be imported into
the hardware configurator from Siemens.
Create a virtual PROFIBUS system "VIPA_CPU21x" and include the CPU
21x-CAN (VIPA 21x-2CM03) at the 1. slot.
Fast introduction For the deployment of System 200V modules and the CAN master, you
have to include the System 200V modules into the hardware catalog via the
GSD-file from VIPA. For the project engineering in the hardware
configurator you have to execute the following steps:
• Start WinCoCT and project the CANopen network.
• Create a master group with and insert a CANopen master via .

• Activate the master function via "Device Access" and "Device is NMT
Master".
• Activate in the register "CANopen Manager" Device is NMT Master and
confirm your entry.
• Set parameters like diagnosis behavior and CPU address ranges with
"Set PLC Parameters".
• Create a "slave" group with and add your CANopen slaves via
.
• Add modules to your slaves via "Modules" and parameterize them if
needed.
• Set your process data connections in the matrix via "Connections" and
proof your entries if needed in the process image of the master.
• Save the project and export it as wld-file.
• Include vipa_21x.gsd in the hardware configurator from Siemens.
• Switch to the Siemens SIMATIC manager and copy the data block from
the CAN-wld-file into the block directory.
• Project the PROFIBUS-DP master system in the hardware configurator
with the following Siemens-CPU: CPU 315-2DP (6ES7 315-2AF03-0AB0
V1.2)
• The DP master receives an address >1.
• Add the System 200V DP slave system "VIPA_CPU21x" from the
hardware catalog to the master system.
• The slave system always requires the address 1.
• Place the System 200V modules in plugged sequence starting with the
CPU 21x-2CM03 at the 1. slot.
• Save all and transfer the PLC project together with the wld-file via MPI
into the CPU.
In the following, these steps are explained more detailed.
4-4 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Precondition for The hardware configurator is a part of the Siemens SIMATIC manager. It
the project serves the project engineering. The modules that can be parameterized
engineering with are monitored in the hardware catalog.
For the deployment of the System 200V modules, the inclusion of the
System 200V modules into the hardware catalog is necessary. This
happens via a GSD-file vipa_21x.gsd from VIPA.
Note!
For the project engineering a thorough knowledge of the Siemens
SIMATIC manager and the hardware configurator from Siemens is
required!
Include GSD-file • Copy the delivered VIPA GSD-file VIPA_21x.gsd into your GSD-
directory... \siemens\step7\s7data\gsd
• Start the hardware configurator from Siemens.
• Close all projects.
• Choose Options > Install new GSD-file.
• Select VIPA_21x.GSD.
Now the modules of the System 200V from VIPA are integrated in the
hardware catalog and can be projected.
Note
To be compatible to the Siemens SIMATIC manager, the System 200V CPUs from VIPA
have to be projected as
CPU 315-2DP (6ES7 315-2AF03-0AB0 V1.2)!
To be able to directly address the modules, you have to include them in the hardware
configurator from Siemens in form of a virtual PROFIBUS system. By including the
GSD-file from VIPA, you are able to access the complete function range of the
modules.
Engineer the CAN master in your virtual PROFIBUS system by placing a CPU 21x-
2CM03 on the 1. slot.
The concrete project engineering happens in the CANopen configuration tool
WinCoCT. You may export your project as wld-file and transfer it as DB into your PLC
program.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-5

WinCoCT WinCoCT (Windows CANopen Configuration Tool is a configuration tool

developed from VIPA to allow the comfortable project engineering of
CANopen networks.
WinCoCT monitors the CANopen network topology in a graphical user
interface. Here you may place, parameterize and group field devices and
controls and engineer connections.
The selection of the devices happens via a list that can be extended for
your needs with an EDS-file (Electronic Data Sheet) at any time.
A right click onto a device opens a context menu consisting partly of static
and partly of dynamic components.
For the configuration of the process data exchange, all process data are
monitored in a matrix with the device inputs as rows and the device outputs
as columns. Mark a cross point to create the wanted connection.
The telegram collection and optimization is executed by WinCoCT.
4-6 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Set project Via Tools > Project options you may preset CAN specific parameters like
parameters baud rate, selection of the master etc.
More detailed information is to find in the WinCoCT manual.
Parameter WinCoCT allows you to preset VIPA specific parameters for the CAN
CAN master master by doing a right click onto the master and call the following dialog
window with Set PLC-Parameters:
PLC Type Reserved for later extensions
Slot number Slot number at the bus

0: For the addressing of the CAN master integrated in the CPU
1 ... 32: For the addressing of CAN master at the standard bus
CANopen Fix at 0x195

DeviceProfileNumber
Behavior at Here you can define the reaction of the output channels if the CPU
PLC-STOP switches to STOP. The following values are available:
Switch substitute value 0: Sets all outputs to 0
Keep last value: Keeps the recent state of the outputs.
Behavior at Slave Here you set the reaction for the slave input data in case of a slave failure.
breakdown Switch substitute value 0: The data is set to 0.
Keep the last value: The recent date remain unchanged.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-7

Diagnostic This area allows you to define the diagnostic reaction of the CAN master.
Diagnostic: Activates the diagnostic function
CANopen state: When activated, the CAN master sends its state
"preoperational" or "operational" to the CPU. You may request the state via
SFC 13.
Slave failure/recovery: When activated, the OB 86 is called in the CPU in
case of slave failure and reboot.
Error control: If this option is selected, the NMT master sends all Guarding
errors as diagnosis to the CPU, that calls the OB 82.
Emergency Telegram: At activation, the NMT master sends all Emergency
telegrams as diagnosis to the CPU, that calls the OB 82.
Address range in The following fields allow you to preset the address ranges in the CPU for
the CPU the CANopen master in- and output ranges. Each block consists of 4Byte.
Input addr. 6000, Input blocks
PI basic address in the CPU that are occupied from 0x6000 CAN input
data. For input blocks max. 16 (64Byte) can be entered.
Output addr. 6000, Output blocks
PO basic address in the CPU that are occupied from 0x6000 CAN output
data. For output blocks max. 16 (64Byte) can be entered.
Input addr. A000, Input blocks
PI basic address in the CPU that are occupied from 0xA000 CAN input
network variables. For input blocks max. 80 (320Byte) can be entered.
Output addr. A000, Output blocks
PO basic address in the CPU that are occupied from 0xA000 CAN output
network variables. For output blocks max. 80 (320Byte) can be entered.
Activate CANopen To enable the master to access a CANopen slave, you have to register it at
slave in the the according master via WinCoCT. Right click onto your CAN master,
CANopen Manager choose "Device access" and switch to the register "CANopen Manager".
Via [Change] you can register every single slave res. via [Global] all slaves
at your master and preset the error behavior.
Please don’t forget to apply the settings into your project engineering
by clicking on [Apply to slaves].
4-8 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Steps of the The following text describes the approach of the project engineering with
project an abstract sample:
engineering The project engineering is divided into three parts:
• CAN master project engineering in WinCoCT and export as wld-file
• Import CAN master project engineering
• Project engineering of the CPU 21x-2CM03 an the System 200V
modules
Hardware structure System 200V
CPU 21xCAN DI DO DIO AI AO FM
Preconditions For the project engineering of a CANopen system, the most recent EDS-
file has to be transferred into the EDS-directory of WinCoCT.
For the deployment of the System 200V modules, you have to include the
System 200V modules with the GSD-file VIPA_21x.gsd from VIPA into the
hardware catalog.
CAN master project • Copy the required EDS-files into the EDS-directory and start WinCoCT.
engineering in
WinCoCT
• Create a "master" group via and insert a CANopen
master via (VIPA_21x_2CM03.eds).
• Create a "slave" group with and add your CANopen
slaves via .
• Right click on the according slave and add the needed
modules via „Modules“.
• Parameterize the modules with [Parameter] res. via the
according object directory.
• Right click on the master and open the dialog "Device
Access".
• Activate Device is NMT Master in the register "CANopen
Manager" and register the according slaves at the master.
Don’t forget to apply your settings into your project
engineering with [Apply to slaves]!
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-9

• Right click onto the master and open the VIPA specific dialog
"Set PLC Parameters". Here you may adjust the diagnosis
behavior and the address ranges that the master occupies in
the CPU.
Under "Slot number" type the slot no. 0 for your
CPU 21x-2CM03. At export, WinCoCT creates the DB 2000.
• Change to the register "Connections" in the main window.

Here the process data are shown in a matrix as inputs (1.
column) and as outputs (1. row).
To monitor the process data of a device with a "+" click on
the according device.
• For helping you, you may only define a connection when the
appearing cross has green color. Select the according cell
with the mouse pointer in row and column in the matrix and
click on it. → The cell is marked with a "3". You can control
the connection by changing into "Devices", click on the
master and monitor the process image of the master via
"Device Access".
• Save your project.
• Via File > Export your CANopen project is exported into a
wld-file. The name is the combination of project name + node
address + ID Master/Slave.
Now your CANopen project engineering under WinCoCT is
ready.
Import into PLC • Start the Siemens SIMATIC manager with your PLC project for the
program CPU 21x-2CM03.
• Open the wld-file via File > Memory Card File > open
• Copy the DB 2000 into your block directory.
As soon as you transfer this block to the CPU, it is recognized by the CPU
and the according parameters are transferred to the CAN master.
This is only possible if your CAN master CPU is included in the hardware
configuration as virtual PROFIBUS system. The approach is to find at the
following pages.
4-10 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Hardware configura- The hardware configuration of the System 200V has the following
tion CPU 21x-2CM03 approach:
and System 200V
modules • Start the hardware configurator from Siemens with a new project and
add a profile rail from the hardware catalog.
• Add the CPU 315-2DP (6ES7 315-2AF03-0AB0 V1.2). Create a new
PROFIBUS subnet for that.
• Add the System "VIPA_CPU21x" to the subnet. This is to find in the
hardware catalog under PROFIBUS DP > Additional field devices > IO >
VIPA_System_200V. Assign the PROFIBUS address 1 to this module.
• Place the CPU 21x-2CM03 at the 1. slot from the hardware catalog in
your configurator.
• Include your System 200V modules in the plugged sequence.
• If needed, parameterize the CPU res. the modules. The parameter
window opens with a double click on the according module.
• Save your project.
Hardware strukture
System 200V
Project
engineering 3 1 System 300
Slot Module
1
2 CPU 315-2DP
DP master system
X2 DP
X1
3
MPI/DP
2
4 vipa_21x
5
6
7 Profibus-Adr.: 1
8
9
10
11
System 200V
Module
CPU 21xCAN
DI
DO
DIO
AI
AO
FM
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-11

Conclusion The following picture shows the conclusion of the engineering steps:
WinCoCT
Export
wld file
Hardware structure Import 2

System 200V
Project
engineering 4 3 System 300
Slot Module
1
2 CPU 315-2DP
DP master system
X2 DP
X1
3
MPI/DP
5
4 vipa_21x
5
6
7 Profibus-Adr.: 1
8
9
10
11
System 200V
Module
CPU 21xCAN
DI
DO
DIO
AI
AO
FM
4-12 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Modes
Power On STOP → RUN (automatically)

After POWER ON and at valid project data in
the CPU, the master switches automatically into
RUN. The master has no operating mode lever.
DB2xxx von time_out >
n n
SPS? 10s? After POWER ON, the project data is
automatically send from the CPU to the CAN
j
j master. This establishes a communication to
IF-LED on the CAN slaves.
At active communication and valid bus
DB2xxx OK? n
IF-LED on parameters, the CAN master switches into the
ERR-LED on
state "operational". The LEDs RUN and BA are
j
on.
At invalid parameters, the CAN master remains
in STOP and shows the parameterization error
Typ = Master? n configuriere Slave
via the IF-LED.
j ERR-LED off
IF-LED aus
RUN
configuriere Master In RUN, the RUN- and BA-LEDs are on. Now
IF-LED off
BA-LED blinks (1Hz)
data can be exchanged.
configuriere Slaves
Slave: In case of an error, like e.g. slave failure, the
pre-operational
ERR-LED at the CAN master is on and an
LED BA on alarm is send to the CPU.
Master conditions:
operational wait to Master-
communication
Slaves: operational
all Slaves ERR-LED on

n configuriere Slave
operational?
ERR-LED off Configuration

n
ok?
Data exchange Slave: operational
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-13

Process image of the CPU 21x-2CM03
The process image is build of the following parts:

• Process image for input data (PI) for RPDOs
• Process image for output data (PO) for TPDOs
Every part consists of 64Byte "Digital-Data"- and 320Byte "Network
Variables".
Input data For input data, the following objects are available:
• 8 Bit digital input (Object 0x6000)
• 8 Bit input network variables (Object 0xA040)
Like to see in the following illustration, the objects of the digital input data
use the same memory area of the CPU.
For example, an access to Index 0x6000 with Subindex 2 corresponds an
access to Index 0x6100 with Subindex 1. Both objects occupy the same
memory cell in the CPU.
Please regard that the input network variables also use the same memory
area.
Mapping CMS* CPU

DW W B Offset +
0 0
0
1 1
0
2 2
1
3 3
TPDO
4 4
CAN OUT PDO1 2
5 5
PO PI DI
PDO2
PDO3 1
6 6
3
7 7
. 8 8
. 4
. 9 9
. . .
. . .
. . .
*) CMS = CANopen Master/Slave
4-14 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Output data For the digital output data, the assignment is similar.
For output data, the following objects are available:
• 8 Bit digital output (Object 0x6200)
• 8 Bit output network variables (Object 0xA400)
• 64 Bit output network variables (Object 0xA8C0)
Like to see in the following illustration, the objects of the digital output data
use the same memory area of the CPU.
For example, an access to Index 0x6200 with Subindex 2 corresponds an
access to Index 0x6300 with Subindex 1. Both objects occupy the same
memory cell in the CPU.
Please regard that the output network variables also use the same memory
area.
Mapping CMS* CPU

DW W B Offset +
0 0
0
1 1
0
2 2
1
3 3
RPDO
4 4
CAN IN PDO1 2
5 5
PI PO DO
PDO2
PDO3 1
6 6
3
7 7
. 8 8
. 4
. 9 9
. . .
. . .
. . .
*) CMS = CANopen Master/Slave
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-15

CANopen - Messages
Identifier All CANopen messages have the following structure according to

CIA DS-301:
Identifier
Byte Bit 7 ... Bit 0
1 Bit 3 ... Bit 0: most significant 4 bits of the module-ID
Bit 7 ... Bit 4: CANopen function code
2 Bit 3 ... Bit 0: data length code (DLC)
Bit 4: RTR-Bit: 0: no data (request code)
1: data available
Bit 7 ... Bit 5: Least significant 3 bits of the module-ID
Data Data
Byte Bit 7 ... Bit 0
3 ... 10 Data
An additional division of the 2Byte identifier into function portion and a

module-ID gives the difference between this and a level 2 message. The
function determines the type of message (object) and the module-ID
addresses the receiver.
CANopen devices exchange data in the form of objects. The CANopen
communication profile defines two different object types as well as a
number of special objects.
The VIPA CAN master supports the following objects:

• 40 Transmit PDOs (PDO Linking, PDO Mapping)
• 40 Receive PDOs (PDO Linking, PDO Mapping)
• 2 Standard SDOs (1 Server, 127 Clients)
• 1 Emergency Object
• 1 Network management Object NMT
• Node Guarding
• Heartbeat
Note!
The exact structure and data content of all objects is described in the CiA-
Profiles DS-301, DS-302, DS-401 and DS-405.
4-16 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Structure of the A CANopen device can be structured as follows:

device model Communication Application
Status machine Status machine

Object directory
Index Subind. Value

Application
NMT
entry 1 Object
Heartbeat or
entry 2
CAN bus system

Node Guarding
Process (I/Os)
Application
entry 3 Object
SDO .
. Application
SDO
Object
.
PDO .. Application
. Object
PDO
entry n
Application
SYNC
Object
Communication
Serves the communication data objects and the concerning functionality for
data transfer via the CANopen network.
Application
The application data objects contain e.g. in- and output data. In case of an
error, an application status machine switches the outputs in a secure state.
The object directory is organized as 2 dimension table. The data is addres-
sed via index and sub-index.
Object directory
This object directory contains all data objects (application data +
parameters) that are accessible and that influence the behavior of
communication, application and status machines.
PDO In many field bus systems the whole process image is transferred - mostly
more or less cyclically. CANopen is not limited to this communication
principle, for CAN supports more possibilities through multi master bus
access coordination.
CANopen divides the process data into segments of max. 8Byte. These
segments are called process data objects (PDOs). Every PDO represents
one CAN telegram and is identified and prioritized via its specific CAN
identifier.
For the exchange of process data, the VIPA CAN-Master supports 80
PDOs. Every PDO consists of a maximum of 8 data bytes. The transfer of
PDOs is not verified by means of acknowledgments since the CAN protocol
guarantees the transfer.
There are 40Tx transmit PDOs for input data and 40Rx receive PDOs for
output data. The PDOs are named seen from the CAN-Master:
Receive PDOs (RxPDOs) are received by the CAN-Master and contain
input data.
Transmit PDOs (TxPDOs) are send by the CAN-Master and contain output
data.
The assignment of the PDOs to input or output data occurs via WinCoCT
automatically.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-17

SDO For access to the object directory, the Service-Data-Object (SDO) is used.
The SDO allows you a read or write access to the object directory. In the
CAL-Layer-7-Protocol you find the specification of the Multiplexed-Domain-
Transfer-Protocol that is used by the SDOs. This protocol allows you to
transfer data with any length. At need, the messages are divided into
several CAN messages with identical identifier (segmentation). A SDO is
transferred acknowledged, i.e. every reception of a message is
acknowledged.
Note!
A more detailed description of the SDO telegrams is to find in the CiA norm
DS-301.
In the following only the error messages are described that may occur at a
wrong parameter communication.
SFC 219 CAN_TLGR Every CPU has the SFC 219 integrated. This allows you to start a SDO
SDO request to CAN read or write access from your PLC program to the CAN master.
master
You address your master via the slot number and the destination slave via
its CAN address. The process data is defined by index and subindex. Via
SDO every access transfers max. one data word process data. The SFC
219 contains the following parameters:
Name Declaration Type Comment
Request IN BOOL
Slot_Master IN BYTE
NodeID IN BYTE
Transfertyp IN BYTE
Index IN DWORD
Subindex IN DWORD
CANopenError OUT DWORD
RetVal OUT WORD
Busy OUT BOOL
DataBuffer IN_OUT ANY
Request Control parameter: 1: Start the order
Slot_Master Depending on the slot number.

0: for addressing the integrated CAN master
1 ... 32: for addressing stand-alone System 200V CAN master
NodelD Address of the CANopen node (1...127)
Transfer type 40h, 60h: Read SDO 61h: Write SDO (undefined length)
23h: Write SDO (1 DWORD)
2Bh: Write SDO (1 WORD)
2Fh: Write SDO ( 1 BYTE)
Index CANopen Index
Subindex CANopen Subindex
4-18 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

CANopenError If no error occurs CANopenError returns value 0.

In case of error the CANopenError contains one of the following error
messages which are generated in the CAN master:
Code Description
0x05030000 Toggle bit not alternated
0x05040000 SDO protocol timed out
0x05040001 Client/server command specifier not valid or unknown
0x05040002 Invalid block size (block mode only)
0x05040003 Invalid sequence number (block mode only)
0x05040004 CRC error (block mode only)
0x05040005 Out of memory
0x06010000 Unsupported access to an object
0x06010001 Attempt to read a write only object
0x06010002 Attempt to write a read only object
0x06020000 Object does not exist in the object dictionary
0x06040041 Object cannot be mapped to the PDO
0x06040042 The number and length of the objects to be mapped would exceed PDO length
0x06040043 General parameter incompatibility reason
0x06040047 General internal incompatibility in the device
0x06060000 Access failed due to an hardware error
0x06070010 Data type does not match, length of service parameter does not match
0x06070012 Data type does not match, length of service parameter too high
0x06070013 Data type does not match, length of service parameter too low
0x06090011 Sub-index does not exist
0x06090030 Value range of parameter exceeded (only for write access)
0x06090031 Value of parameter written too high
0x06090032 Value of parameter written too low
0x06090036 Maximum value is less than minimum value
0x08000000 general error
0x08000020 Data cannot be transferred or stored to the application
0x08000021 Data cannot be transferred or stored to the application because of local control
0x08000022 Data cannot be transferred or stored to the application because of the present
device state
0x08000023 Object dictionary dynamic generation fails or no object dictionary is present
(e.g. object dictionary is generated from file and generation fails because of an
file error)
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-19

RetVal When the function has been executed successfully, the return value
contains the valid length of the respond data: 1: BYTE, 2: WORD, 4:
DWORD.
If an error occurs during function processing, the return value contains an
error code.
Value Description
F021h Invalid slave address (Call parameter equal 0 or above 127)
F022h Invalid Transfer type (Value unequal 60h, 61h)
F023h Invalid data length (data buffer to small, at SDO read access it should be at
least 4Byte, at SDO write access 1Byte, 2Byte or 4Byte).
F024h The SFC is not supported
F025h Write buffer in the CANopen master full, service can not be processed at this
time.
F026h Read buffer in the CANopen master full, service can not be processed at this
time.
F027h The SDO read or write access returned wrong answer, see CANopen Error
Codes.
F028h SDO-Timeout (no CANopen participant with this Node-Id has been found).
Busy Busy = 1: The read/write job is not yet completed.
DataBuffer SFC data communication area. Set here an ANY pointer of the type Byte.
Read SDO: Destination area for the SDO data that were read.
Write SDO: Source area for the SDO data that were write.
Note
Unless a SDO demand was processed error free, RetVal contains the
length of the valid response data in 1, 2 or 4 byte and the CANopenError the
value 0.
4-20 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Object directory
Structure The CANopen object directory contains all relevant CANopen objects for
the bus coupler. Every entry in the object directory is marked by a 16Bit
index.
If an object exists of several components (e.g. object type Array or
Record), the components are marked via an 8Bit sub-index.
The object name describes its function. The data type attribute specifies
the data type of the entry.
The access attribute defines, if the entry may only be read, only be written
or read and written.
The object directory is divided into the following 3 parts:
Communication This area contains the description of all relevant parameters for the
specific profile area communication.
(0x1000 – 0x1FFF)
0x1000 – 0x1011 General communication specific parameters
(e.g. device name)
0x1400 – 0x1427 Communication parameters (e.g. identifier) of the
receive PDOs
0x1600 – 0x1627 Mapping parameters of the receive PDOs
The mapping parameters contain the cross-
references to the application objects that are
mapped into the PDOs and the data width of the
depending object.
0x1800 – 0x1827 Communication and mapping parameters of the
0x1A00 – 0x1A27 transmit PDOs
Manufacturer specific Here you find the manufacturer specific entries. The CAN master from
profile area VIPA has no manufacturer specific entries.
(0x2000 – 0x5FFF)
Standardized device This area contains the objects for the device profile acc. DS-401.
profile area
(0x6000 – 0x9FFF)
Note!
For the CiA norms are exclusively available in English, we adapted the
object tables. Some entries are described below the according tables.
A more detailed description of the table entries is to find below the
according table.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-21

Object directory Index Content of Object

overview 1000h Device type
1001h Error register
1005h COB-ID SYNC
1006h Communication Cycle Period
1007h Synchronous Window Length
1008h Manufacturer Hardware Version
1009h Hardware Version
100Ah Software Version
100Ch Guard Time
100Dh Life Time Factor
1016h Consumer Heartbeat Time
1017h Producer Heartbeat Time
1018h Identity Object
1400h to 1427h Receive PDO Communication Parameter
1600h to 1627h Receive PDO Mapping Parameter
1800h to 1827h Transmit PDO Communication Parameter
1A00h to 1A27h Transmit PDO Mapping Parameter
1F22h Concise DCF
1F25h Post Configuration
1F80h NMT StartUp
1F81h Slave Assignment
1F82h Request NMT
1F83h Request Guarding
6000h Digital-Input-8-Bit Array (see DS 401)
6100h Digital-Input-16-Bit Array (see DS 401)
6120h Digital-Input-32Bit Array (see DS 401)
6200h Digital-Output-8-Bit Array (see DS 401)
A040h Dynamic Unsigned8 Input
A4C0h Dynamic Unsigned8 Output
A580h Dynamic Unsigned16 Output
A680h Dynamic Unsigned32 Output
A8C0h Dynamic Unsigned64 Output
4-22 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Device Type
Index Sub- Name Type Attr. Map. Default value Meaning
index
0x1000 0 Device Unsigned32 ro N 0x00050191 Statement of device type
Type
The 32Bit value is divided into two 16Bit fields:
MSB LSB
Additional information Device profile number
0000 0000 0000 wxyz (bit) 405dec=0x0195
The "additional information" contains data related to the signal types of the
I/O device:
z=1 digital inputs
y=1 digital outputs
x=1 analog inputs
w=1 analog outputs
Error register
Index
0x1001 0 Error Unsigned8 ro Y 0x00 Error register
Register
Bit 7 Bit 0
ManSpec reserved reserved Comm. reserved reserved reserved Generic
ManSpec.: Manufacturer specific error, specified in object 0x1003.

Comm.: Communication error (overrun CAN)
Generic: A not more precisely specified error occurred (flag is set at
every error message)
SYNC identifier
Index
0x1005 0 COB-Id sync Unsigned32 ro N 0x80000080 Identifier of the SYNC
message message
The lower 11Bit of the 32Bit value contain the identifier (0x80=128dez),
while the MSBit indicates whether the device receives the SYNC telegram
(1) or not (0).
Attention: In contrast to the PDO identifiers, the MSB being set indicates
that this identifier is relevant for the node.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-23

SYNC interval
index
0x1006 0 Communi- Unsigned32 rw N 0x00000000 Maximum length of the
cation SYNC interval in µs.
cycle period
If a value other than zero is entered here, the master goes into error state if
no SYNC telegram is received within the set time during synchronous PDO
operation.
Synchronous
Window Length
index
0x1007 0 Synchronous Unsigned32 rw N 0x00000000 Contains the length of time
window window for synchronous
length PDOs in µs.
Device name
index
0x1008 0 Manufacturer Visible string ro N Device name of the bus
device name coupler
VIPA 21x-2CM03
Since the returned value is longer than 4Byte, the segmented SDO
protocol is used for transmission.
Hardware version
index
0x1009 0 Manufacturer Visible string ro N Hardware version number of
Hardware bus coupler
version
1.00
4-24 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Software version
index
0x100A 0 Manufacturer Visible string ro N Software version number
Software CANopen software
version
1.xx
Guard time
index
0x100C 0 Guard time Unsigned16 rw N 0x0000 Interval between two guard
[ms] telegrams. Is set by the NMT
master or configuration tool.
Life time factor

index
0x100D 0 Life time Unsigned8 rw N 0x00 Life time factor x guard time
factor = life time (watchdog for life
guarding)
If a guarding telegram is not received within the life time, the node enters
the error state. If the life time factor and/or guard time =0, the node does
not carry out any life guarding, but can itself be monitored by the master
(node guarding).
Consumer
Heartbeat Time
index
0x1016 0 Consumer Unsigned8 ro N 0x05 Number of entries
heartbeat
time
1...127 Unsigned32 rw N 0x00000000 Consumer heartbeat time
Structure of the "Consumer Heartbeat Time" entry::

Bits 31-24 23-16 15-0
Value Reserved Node-ID Heartbeat time
Encoded as Unsigned8 Unsigned8 Unsigned16
As soon as you try to configure a consumer heartbeat time unequal zero

for the same node-ID, the node interrupts the SDO download and throws
the error code 0604 0043hex.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-25

Producer
Heartbeat Time
index
0x1017 0 Producer Unsigned16 rw N 0x0000 Defines the cycle time of
heartbeat heartbeat in ms
time
Identity Object
index
0x1018 0 Identity Unsigned8 ro N 0x04 Contains general
Object Information about the device
(number of entries)
1 Vendor ID Unsigned32 ro N 0xAFFEAFFE Vendor ID
2 Product Unsigned32 ro N 0x2142CA02 Product Code
Code
3 Revision Unsigned32 ro N Revision Number
Number
4 Serial Unsigned32 ro N Serial Number
Number
Communication
parameter RxPDO
index
0x1400 0 Number of Unsigned8 ro N 0x02 Communication parameter
... Elements for the first receive PDOs,
Subindex 0: number of
0x1427
following parameters
1 COB-ID Unsigned32 rw N 0xC0000200 COB-ID RxPDO1
+ NODE_ID
2 Transmis- Unsigned8 rw N 0xFF Transmission type of the
sion type PDO
Sub-index 1 (COB-ID): The lower 11Bit of the 32Bit value (Bits 0-10)
contain the CAN identifier, the MSBit (Bit 31) shows if the PDO is active (0)
or not (1), Bit 30 shows if a RTR access to this PDO is permitted (0) or not
(1).
The sub-index 2 contains the transmission type.
4-26 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Mapping RxPDO
index
0x1600 0 Number of Unsigned8 rw N 0x01 Mapping parameter of the first
... Elements receive PDO; subindex 0:
number of mapped objects
0x1627
1 1. mapped Unsigned32 rw N 0x62000108 (2 byte index,
object 1 byte subindex,
1 byte bit-width)
1 byte bit-width)
... ... ... ... ... ... ...
1 byte subindex,
1 byte bit-width)
The reception PDOs get a default mapping automatically from the master
depending on the connected modules.
Communication
parameter TxPDO1
index
0x1800 0 Number of Unsigned8 ro N 0x05 Communication parameter
... Elements of the first transmit PDO,
subindex 0: number of
0x1827
following parameters
1 COB-ID Unsigned32 rw N 0x80000180 + COB-ID TxPDO1
NODE_ID
2 Transmis- Unsigned8 rw N 0xFF Transmission type of the
sion type PDO
3 Inhibit time Unsigned16 rw N 0x0000 Repetition delay

[value x 100 µs]
5 Event time Unsigned16 rw N 0x0000 Event timer [value x 1 ms]
Sub-index 1 (COB-ID): The lower 11Bit of the 32Bit value (Bits 0-10)
contain the CAN identifier, the MSBit (Bit 31) shows if the PDO is active (0)
or not (1), Bit 30 shows if a RTR access to this PDO is permitted (0) or not
(1). The sub-index 2 contains the transmission type, sub-index 3 the
repetition delay time between two equal PDOs. If an event timer exists with
a value unequal 0, the PDO is transmitted when the timer exceeds.
If a "inhibit timer" exists, the event is delayed for this time.
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-27

Mapping TxPDO1
index
0x1A00 0 Number of Unsigned8 rw N depending on Mapping parameter of the
... Elements the first transmit PDO;
components subindex 0: number of
0x1A27
fitted mapped objects
1 byte bit-width)
1 byte bit-width)
... ... ... ... ... ... ...
1 byte bit-width)
The send PDOs get a default mapping automatically from the coupler
depending on the connected modules.
Concise DCF
index
0x1F22 Array Concise DCF Domain rw N
This object is required for the Configuration Manager. The Concise-DCF is

the short form of the DCF (Device Configuration File).
Post
Configuration
index
0x1F25 Array ConfigureSlave Unsigned32 rw N 0x00000000
Via this entry, the Configuration Manager can be forced to transfer a stored
configuration into the net.
The configuration can be initiated for a defined node at any time via the
index 0x1F25.
Subindex 0 has the value 128.
Subindex x (with x = 1..127): Starts the reconfiguration for nodes with the
node ID x.
Subindex 128: reconfiguration of all nodes.
For example: If you want to initiate the configuration for node 2 and there
are configuration data for this node available, you have to write the value
0x666E6F63 (ASCII = "conf") to the object 1F25h Subindex 2.
4-28 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

NMT Start-up
index
0x1F80 0x00 NMTStartup Unsigned32 rw N 0x00000000
Define the device as NMT master.
Bit Meaning
Bit 0 0 : Device is NOT the NMT Master. All other bits have to be
ignored. The objects of the Network List have to be ignored.
1 : Device is the NMT Master.
Bit 1 0 : Start only explicitly assigned slaves.
1 : After boot-up perform the service NMT Start Remote Node
All Nodes
Bit 2...31 Reserved by CiA, always 0
Slave Assignment
index
0x1F81 0x00 SlaveAssignment Unsigned32 rw N 0x00000000
Enter the nodes that are controlled by the master. For every assigned node
you need one entry.
Subindex 0 has the value 127. Every other Subindex corresponds with the
Node-ID of the node.
Byte Bit Description

Byte 0 Bit 0 0: Node with this ID is not a slave
1: Node with this ID is a slave. After configuration
(with Configuration Manager) the Node will be set to
state Operational.
Bit 1 0: On Error Control Event or other detection of a
booting slave inform the application.
1: On Error Control Event or other detection of a
booting slave inform the application and automatically
start Error Control service.
Bit 2 0: On Error Control Event or other detection of a
booting slave do NOT automatically configure and
start the slave.
1: On Error Control Event or other detection of a
booting slave do start the process Start Boot Slave.
Bit 3...7 Reserved by CiA, always 0
Byte 1 8 Bit Value for the RetryFactor
Byte 2,3 16 Bit Value for the GuardTime
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-29

Request NMT
Index
0x1F82 0x00 RequestNMT Unsigned8 rw N 0x00000000
If a totally automatic start of the stack is not wanted, the functionalities:

• Status change
• Start of the guarding
• Configuration via CMT
can be also executed at request for every node. The request always
happens via objects in the object directory.
The switch of the communication state of all nodes in the network
(including the local slaves) happens via the entry 1F82h in the local object
directory:

Subindex x (with x=1..127): Initiates the NMT service for nodes with Node ID x.
Subindex 128: Initiates NMT service for all nodes.
At write access, the wanted state is given as value.
State Value
Prepared 4
Operational 5
ResetNode 6
ResetCommunication 7
PreOperational 127
Request Guarding
index
0x1F83 0x00 RequestGuarding Unsigned32 rw N 0x00000000

Subindex x (with x=1..127): Initiates guarding for the slave with Node ID x.
Value Write Access Read Access

1 Start Guarding Slave actually is guarded
0 Stop Guarding Slave actually is not guarded
Subindex 128: Request Start/Stop Guarding for all nodes.
4-30 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

8bit Digital inputs

index
0x6000 0x00 8bit digital Unsigned8 ro N 0x01 Number of available digital
input block 8bit input blocks
0x01 1. input Unsigned8 ro Y 1. digital input block

block
... ... ... ... ... ... ...
block
16bit Digital inputs

Index
0x6100 0x00 16bit digital Unsigned8 ro N depending on Number of available digital
input block the fitted 16bit input blocks
components
0x01 1. input Unsigned16 ro N 1. digital input block
block
... ... ... ... ... ... ...
block
32bit Digital inputs

index
0x6120 0x00 32bit digital Unsigned8 ro N depending on Number of available digital
input block the compo- 32bit input blocks
nents fitted
block
... ... ... ... ... ... ...
block
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-31

8bit Digital
outputs
index
0x6200 0x00 8bit digital Unsigned8 ro N 0x01 Number of available digital
output block 8bit output blocks
0x01 1. output Unsigned8 rw Y 1. digital output block

block
... ... ... ... ... ... ...
block
16bit Digital
outputs
index
0x6300 0x00 16bit digital Unsigned8 ro N Depending on Number of available digital
input block the compo- 16bit output blocks
nents fitted
0x01 1. output Unsigned16 rw N 1. digital output block
block
... ... ... ... ... ... ...
block
32bit Digital
outputs
index
0x6320 0x00 32bit digital Unsigned8 ro N Depending on Number of available digital
nents fitted
block
... ... ... ... ... ... ...
block
4-32 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

8bit Network input variables

index
0xA040 0x00 8bit digital Unsigned8 ro N 0x01 Number of available digital
input block 8bit input blocks

block
... ... ... ... ... ... ...
block

index
0xA100 0x00 16bit digital Unsigned8 ro N depending on Number of available digital
input block the fitted 16bit input blocks
components
block
... ... ... ... ... ... ...
0xA0 160. input Unsigned16 ro N 160. digital input block
block

index
nents fitted
block
... ... ... ... ... ... ...
block

index
nents fitted
block
... ... ... ... ... ... ...
block
HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 4-33

8bit Network output variables

index
0xA400 0x00 8bit digital Unsigned8 ro N 0x01 Number of available digital
output block 8bit output blocks

block
... ... ... ... ... ... ...
block

index
0xA580 0x00 16bit digital Unsigned8 ro N Depending on Number of available digital
nents fitted
block
... ... ... ... ... ... ...
0xA0 160. output Unsigned16 rw N 160. digital output block
block

index
0xA680 0x00 32bit digital Unsigned8 ro N Depending on Number of available digital
nents fitted
block
... ... ... ... ... ... ...
block

index
0xA8C0 0x00 64bit digital Unsigned8 ro N Depending on Number of available digital
nents fitted
block
... ... ... ... ... ... ...
block
4-34 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

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VIPA System 200V

Information product support

About this manual .................................................................................... 1

HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 i

ii HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

About this manual

Overview Chapter 1: Basics and Assembly

Chapter 2: Hardware description

Chapter 3: Deployment CPU 21x-2CM03

Chapter 4: CANopen communication

HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1

Guide to the The following guides are available in the manual:

Availability The manual is available in:

2 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Applications The CPU 21x is constructed and produced for:

Documentation The manual must be available to all personnel in the

The following conditions must be met before using or commissioning

• Hardware modifications to the process control system should only be

• Installation and hardware modifications only by properly trained

• The national rules and regulations of the respective country must be

HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 3

4 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Chapter 1 Basics and Assembly

Contents Topic Page

HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1-1

Safety Information for Users

Handling of VIPA modules make use of highly integrated components in MOS-

The Symbol is located on the module, the module rack or on packing

Shipping of Modules must be shipped in the original packing material.

1-2 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Overview The System 200V is a modular automation system for assembly on a

CPU 215 SM 221 SM 221 SM 221 SM 221

Components The System 200V consists of the following components:

Head modules With a head module CPU respectively bus

Periphery modules The modules are direct installed on a

HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1-3

Power supplies With the System 200V the DC 24V power

Expansion The expansion modules are complemen-

Structure/ • Profile rail 35mm

1-4 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Dimensions 1tier width (HxWxD) in mm: 76 x 25.4 x 74

HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1-5

1-6 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Order number Label Description

HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1-7

Assembly regarding • Use bus connectors as long as possible.

1-8 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Please follow these rules during the assembly!

• Every row must be completed from left to right and it

has to start with a header module.

[1] Header module (double width)

• Modules are to be installed side by side. Gaps are not

HB97E - CPU - RE_21x-2CM03 - Rev. 15/14 1-9

1-10 HB97E - CPU - RE_21x-2CM03 - Rev. 15/14

Demounting and module exchange

• Remove if exists the wiring to the module, by pressing both

• The casing of the module has a spring loaded clip at the

• The clip is unlocked by pressing the screwdriver in an upward

• Withdraw the module with a slight rotation to the top.