8259 PIC Microcontroller

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Intel 8259 is a Programmable Interrupt Controller (PIC). There are 5
hardware interrupts and 2 hardware interrupts in Intel 8085 and Intel 8086
microprocessors respectively. But by connecting Intel 8259 with these
microprocessors, we can increase their interrupt handling capability. Intel 8259
combines the multi-interrupt input sources into a single interrupt output.
Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7. For example,
Interfacing of 8085 and 8259 increases the interrupt handling capability of 8085
microprocessor from 5 to 8 interrupt levels.
Features of Intel 8259 PIC are as follows:
1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered -
interrupt level.
3. We can mask individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by
cascading further 8259 PICs.
5. Clock cycle is not required.
Pin Diagram of 8259 – We can see through above diagram that there are total
28 pins in Intel 8259 PIC where Vcc : 5V Power supply and Gnd : ground.
Block Diagram of 8259 PIC microprocessor –

The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write
Logic, Cascade Buffer Comparator, Control Logic, Priority Resolver and 3
registers- ISR, IRR, IMR.
1. Data bus buffer – This Block is used as a mediator between 8259 and
8085/8086 microprocessor by acting as a buffer. It takes the control
word from the 8085 (let say) microprocessor and transfer it to the
control logic of 8259 microprocessor. After selection of Interrupt by
8259 microprocessor (based on priority of the interrupt), it transfer the
opcode of the selected Interrupt and address of the Interrupt service
sub routine to the other connected microprocessor. The data bus buffer
consists of 8 bits represented as D0-D7 in the block diagram. Thus,
shows that a maximum of 8 bits data can be transferred at a time.
2. Read/Write logic – This block works only when the value of pin CS is
low (as this pin is active low). This block is responsible for the flow of
data depending upon the inputs of RD and WR. These two pins are
active low pins used for read and write operations.
3. Control logic – It is the center of the PIC and controls the functioning of
every block. It has pin INTR which is connected with other
microprocessor for taking interrupt request and pin INT for giving the
output. If 8259 is enabled, and the other microprocessor Interrupt flag
 is high then this causes the value of the output INT pin high and in this
way 8259 responds to the request made by other microprocessor.
4. Interrupt request register (IRR) – It stores all the interrupt level
which are requesting for Interrupt services.
5. Interrupt service register (ISR) – It stores the interrupt level which
are currently being executed.
6. Interrupt mask register (IMR) – It stores the interrupt level which
have to be masked by storing the masking bits of the interrupt level.
7. Priority resolver – It examines all the three registers and set the
priority of interrupts and according to the priority of the interrupts,
interrupt with highest priority is set in ISR register. Also, it reset the
interrupt level which is already been serviced in IRR.
8. Cascade buffer – To increase the Interrupt handling capability, we can
further cascade more number of pins by using cascade buffer. So,
during increment of interrupt capability, CSA lines are used to control
multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master
mode else in slave mode. In Non Buffered mode, SP/EN pin is used to specify
whether 8259 work as master or slave and in Buffered mode, SP/EN pin is used
as an output to enable data bus.

Advantages:

Interrupt Management: The 8259 PIC is designed to handle interrupts

efficiently and effectively, allowing for faster and more reliable processing of
interrupts in a system.
Flexibility: The 8259 PIC is programmable, meaning that it can be customized to
suit the specific needs of a given system, including the number and type of
interrupts that need to be managed.
Compatibility: The 8259 PIC is compatible with a wide range of
microprocessors, making it a popular choice for managing interrupts in many
different systems.
Multiple Interrupt Inputs: The 8259 PIC can manage up to 8 interrupt inputs,
allowing for the management of complex systems with multiple devices.
Ease of Use: The 8259 PIC includes simple interface pins and registers, making it
relatively easy to use and program.

Disadvantages:

Cost: While the 8259 PIC is relatively affordable, it does add cost to a system,
particularly if multiple PICs are required.
Limited Number of Interrupts: The 8259 PIC can manage up to 8 interrupt
inputs, which may be insufficient for some applications.
Complex Programming: Although the interface pins and registers of the 8259
PIC are relatively simple, programming the 8259 can be complex, requiring
careful attention to interrupt prioritization and other parameters.
Limited Functionality: While the 8259 PIC is a useful peripheral for interrupt
management, it does not include more advanced features, such as DMA (direct
memory access) or advanced error correction.

Block Diagram of 8259 Microprocessor

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  8259 microprocessor can be programmed according to given interrupts
condition and it can be provided either with level or edge-triggered
interrupt level.
 It can be programmed to either work in 8085 or in 8086
microprocessors.
 Individual interrupt bits can be masked.
 By cascading Nine 8259’s in Master-Slave Configuration we can handle
up to 64 interrupt pins.

It contains 3 registers commonly known as ISR, IRR, IMR & there is 1 priority
resolver (PR).

1. Interrupt Request Register (IRR): It stores those bits which are

requested for their interrupt services.
 2. Interrupt Service Register (ISR): It stores the interrupt levels which
is currently being served.
3. Interrupt Mask Register (IMR): It stores interrupt levels that have to
be masked. These interrupt levels are already accepted by the 8259
microprocessor.
Priority Resolver (PR): It examines all the 3 registers and sets the priority of
interrupts and sets the interrupt levels in ISR which has the highest priority and
the rest of the interrupt bit is IRR which is already accepted.
SP/EN (low active pin): If its value is 1 it works in master mode & if its value=e
is 0 then it works in slave mode.
Cascade Buffer: It is used to cascade more number of Programmable Interrupt
Controller to increase the interrupts handling capability up to 64 levels.

Advantages:

Interrupt management: The 8259 microprocessor is a specialized chip that is

dedicated to managing interrupts, which can help to improve system
performance and reduce the workload on the main CPU.
Programmability: The 8259 microprocessor is programmable, which means
that it can be customized to handle specific types of interrupts and to prioritize
different interrupt requests.
Compatibility: The 8259 microprocessor is compatible with a wide range of
microprocessors, making it a popular choice for interrupt management in many
different systems.
Multiple interrupt inputs: The 8259 microprocessor can handle multiple
interrupt inputs, which makes it a useful peripheral for managing complex
systems with multiple devices.
Ease of use: The 8259 microprocessor includes simple interface pins and
registers, making it relatively easy to use and program.
Disadvantages:

Cost: While the 8259 microprocessor is relatively affordable, it does add cost to a
system, particularly if multiple 8259s are required.
Limited functionality: While the 8259 microprocessor is a useful peripheral for
interrupt management, it does not include more advanced features, such as DMA
(direct memory access) or advanced error correction.
Limited number of interrupts: The 8259 microprocessor can only handle a
limited number of interrupt requests at once, which may be insufficient for some
applications.
Complex programming: Although the interface pins and registers of the 8259
microprocessor are relatively simple, programming the 8259 can be complex,
requiring careful attention to interrupt prioritization and other parameters.

Command words of 8259 PIC

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Command word of 8259 is divided into two parts :
 Initialization command words(ICW)
 Operating command words(OCW)
Initialization command words(ICW) :
 ICW is given during the initialization of 8259 i.e. before its start
functioning.
 ICW1 and ICW2 commands are compulsory for initialization.
 ICW3 command is given during a cascaded configuration.
 If ICW4 is needed, then it is specified in ICW1.
 The sequence order of giving ICW commands is fixed i.e. ICW 1 is given
first and then ICW2 and then ICW3.
 Any of the ICW commands can not be repeated, but the entire
initialization process can be repeated if required.
Operating command words(OCW) :
 OCW is given during the operation of 8259 i.e. microprocessor starts
using 8259.
 OCW commands are not compulsory for 8259.
 The sequence order of giving OCW commands is not fixed.
 The OCW commands can be repeated.
Initialization sequence of 8259 :
ICW1 command :
 The control word is recognized as ICW1 when A0 = 0 and D4 = 1.
 It has the control bits for Edge and level triggering mode, single/cascaded
mode, call address interval and whether ICW4 is required or not.
 Address lines A7 to A5 are used for interrupt vector addresses.
When the ICW1 is loaded, then the initializations performed are:
 The edge sense circuit is reset because, by default, 8259 interrupt is edge
triggered.
 The interrupt mask register is cleared.
 IR7 is assigned to priority 7.
 Slave mode address is assigned as 7.
 When D0 = 0, this means IC 4 command is not required. Therefore,
functions used in IC4 are reset.
 Special mask mode is reset and status read is assigned to IRR.
ICW2 command :
 The control word is recognized as ICW2 when A0= 1.
 It stores the information regarding the interrupt vector address.
 In the 8085 based system, the A15 to A8 bits of control word is used for
interrupt vector addresses.
 In the 8086 based system, T6 to T3 bits are inserted instead of A15 to A8 and
A10 to A8 are used for selecting interrupt level, i.e. 000 for IR0 and 111 for
IR7.
 Initialization of 8259 by ICW1 and ICW2 command words

ICW3 :
ICW3 command word is used when there is more than one 8259 present in the
system i.e. when SNGL bit in ICW 1 is 0, then it will load 8-bit slave register.

ICW3

ICW4 :
 When AEOI = 1, then Automatic end of interrupt mode is selected.
 When SFMN = 1, then a special fully nested mode is selected.
 when BUF = 0 , then Non buffered mode is used (i.e. M/S is don’t care)
and when M/S = 1, then 8259 is master, otherwise it is a slave.
 when µPM = 1, then 8086 operations are performed, otherwise 8085
operations are performed.
 ICW4

Operational command word(OCW) :

OCW1 –
It is used to set and reset the mask bits in IMR(interrupt mask register). M7 –
M0 describes 8 mask bits

OCW2 –
It is used for selecting the mode of operation of 8259. Here L2 to L0 are used to
describe interrupt level on which action need to be performed.
Detailed operations are described in the diagram below.
OCW3 –
 When the ESMM (Enable special mask mode ) bit is set, then the SMM
bit is don’t care. If SMM = 1 and ESMM = 1, then 8259 will enter in
Special mask mode.
 If ESMM = 1 and SMM = 0, then 8259 will return into normal mask
mode.
 RR and RIS are used to give the read register command.
 P = 1 is used for poll command.