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    HD Multi-Standard Decoder: Highly Integrated Soc For HDTV Receivers

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    HD Multi-Standard Decoder: Highly Integrated Soc For HDTV Receivers

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    m16

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    9 views2 pages

    HD Multi-Standard Decoder: Highly Integrated Soc For HDTV Receivers

    Uploaded by

    dobrev666

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    © All Rights Reserved
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    of 2

    FACTSHEET

    MB86H60
    HD MULTI-STANDARD DECODER

    HD MULTI-STANDARD DECODER
    Highly integrated SoC for HDTV receivers
    JTAG SPDIF 4x I2S L/R HD SD HDMI

    Stereo Digital ITU-R656 7x Video DAC


    DAC RGB
    ARM11 HDMI 1.2
    @ 324MHz &
    HDCP
    Audio Decoder HD Video Baseband Video Processor
    Processor Decoder
    Cache TCM RGB Scaler Flicker MV
    De-matrix Fixer
    MPEG-1/2 L1, 2, 3 H.264
    MPEG-2/4 AAC MPEG-2 Display NTSC/PAL TTX, WSS, OSD
    MMU Timer others CC, VBID 2D
    Controller Encoder

    Internal Bus

    Transport Ethernet USB 2.0 Interfaces


    DMA HS OTG
    Controller Stream Decoder MAC
    DDR2 Controller 2x UART IR Rx Universal
    Memory Parallel
    Controller 2x I2C 2x ISO7816 Interface
    Section
    DPLL Filter
    GPIO SPI
    DVB
    Descrambler
    ...

    2x DDR2 TS Input TS Output Flash ATA CI

    MB86H60 block diagram.

    Description This cost effective, low power, high definition media processor
    The MB86H60 is a highly integrated System-on-Chip is able to decode both MPEG-2 and H.264/AVC compressed
    incorporating all the processing functions required by digital video up to HD resolution (1920 x 1080i). HD video can be
    HDTV receivers, including those for digital video, audio and provided either via the copy-protected HDMI output or
    graphics - ideal for IDTV sets and set-top boxes. analogue component outputs. Simultaneously the video signal
    can be scaled down and offered in standard definition (SD)
    The MB86H60 incorporates the high performance ARM resolution. The picture quality on these SD component
    processor 1176JZF-STM featuring an integrated memory outputs may be optimised by using cross-colour and cross-
    management unit (MMU), a floating point co-processor, luminance filters. A digital RGB output and an ITU-R 656
    ARM’s Jazelle® technology and Thumb® instruction set input and output are also available.
    extensions for compact code. The ARM11 provides all the
    processing power needed to enable a whole host of The integrated audio processor can decode a wide variety of
    middleware software. Just two 16-bit DDR2 memories are audio standards required by the broadcast market such as
    required for operation. MPEG-1/2 Layer 1, 2, 3 and MPEG-2/4 AAC. Furthermore,
    support for DolbyTM Digital (AC-3) and DolbyTM Digital Plus is
    planned. Available audio outputs are four I2S, SPDIF and
    stereo analogue outputs.

    1
    FACTSHEET
    MB86H60
    HD MULTI-STANDARD DECODER

    Advanced connectivity is provided by a USB 2.0 high speed For evaluating the device and starting software development,
    On-The-Go (OTG) controller, a 10/100 Base-T Ethernet Fujitsu offers the MB86H60 development kit. It comprises
    MAC and a DMA ATA controller. Integrated peripherals the evaluation board, documentation, schematics and a
    include two serial ports, two ISO7816 smart card interfaces, comprehensive software package including drivers, sample
    two I2C controllers, LED and keypad controller, IR receiver, applications, tools, an operating system and more.
    SPI output, PWM output and 96 GPIO pins. The number of
    usable GPIOs depends on the system configuration since they
    are shared among other IO functions.

    Features • Display controller supporting 5 layers: Video, 2x OSD


    • ARM1176JZF-S™ @ 324MHz with 16K-I/16K-D cache, (YCrCb or RGB), cursor, background
    16K-I/16K-D TCM, FPU, MMU • Teletext, WSS, CC, VBID insertion
    • Bootable from NOR or serial flash • Cross colour and luminance filters
    • 2x16-bit DDR2 SDRAM interface @ 324MHz • PAL/NTSC/SECAM digital encoder
    • HD video decoder supporting H.264/AVC Level 4.0 high • HDMI 1.2 Link and PHY with HDCP
    profile and MPEG-2 HD/SD MP@HL • 3x DAC for analogue HD video output (YPrPb)
    • Programmable audio processor, audio firmware available • 4x DAC for analogue SD video output
    or planned for MPEG-1/2 Layer 1, 2 and 3 (MP3), • Digital RGB888 output (HD) and ITU-R 656 I/O (SD)
    MPEG-2/4 AAC and MPEG-4 HE-AAC, DolbyTM • 4x I2S, SPDIF output, stereo audio DAC
    Digital and DolbyTM Digital Plus • 2x UART, 2x ISO7816 smart card, 2x I2C, PWM, IR RX,
    • USB 2.0 high speed OTG controller SPI
    • Ethernet 10/100 Base-T MAC • 96 GPIO (flexible pin assignment, shared with other
    • Hardware acceleration unit (DMA): DMA ATA I/O functions)
    (16MByte/s), TDES, memory copy, etc. • 5 digit 7-segment LED display and keypad controller
    • Universal processor interface supporting NOR flash, • Internal clock recovery (no external VCXO required)
    common interface and ATA • PBGA 484 package, 27mm x 27mm
    • 4x transport stream decoder and DVB descrambler (3x • Fujitsu CMOS 90nm technology
    external input, 1x output) • Operating temperature range: 0 to +70°C

    ASK FUJITSU MICROELECTRONICS EUROPE


    ARM1176JZF-S is the trademark of ARM Limited. Dolby is a registered trademark of Contact us on +49(0) 61 03 69 00 or visit
    Dolby Laboratories. Any other trademarks or trade names mentioned are the http://emea.fujitsu.com/microelectronics
    property of their respective owners.

    2 FME-M16-0508

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