Synthesis

Think
Hardware

1
 Gajski and Kuhn’s Y Chart
Behavioral Structural
Functional block
Logic

Systems Processor
Algorithms Hardware Modules
Register Transfer ALU’s / Registers
Logic Gates / Flip Flops
Transfer functions Transistors

Rectangles
Cells / Module plans
Floor Plans
Circuit
Clusters
Algorithmic Physical partitions
Architectural
Physical

Y Chart
§ The Y-Chart by Walker and Thomas, based on work by Gajski
and Kuhn. Every design description has a domain (behavioural,
structural, or physical) and a level of detail.
§ Outer edges are less abstract.
§ Synthesis design steps are depicted by trajectories taken from
one of the outer circles (abstract - low detail) towards the centre
(specific - high detail).
§ Ex –
¢ Creating a structural description from a behavioral one is logical
synthesis.
¢ Creating a physical description from a structural one is layout
synthesis.
§ Analysis – Extraction and Simulation, derive an abstract
description from a more specific one. Reverse of synthesis.

2
 Design Basics
§ Design Object - Describes an electronic design in a particular domain
and on a particular level of detail, as it exists at a particular point in
time. The set of all design objects for a single electronic design is
referred to as a module. A design object is uniquely identified by the
tuple (module, domain, level of detail, version).
§ Synthesis steps - Transform design objects from a low level of detail
in the behavioural domain to higher levels of detail in the structural or
physical domains.
¢ They are one-to-many transformations, i.e. there are a number of possible
ways of implementing the design using the lower level design objects.
§ Abstraction - Another approach to handle design complexity. The
objective for abstraction is information hiding and simplification of
reuse. When using a design module, deal only with its interfaces
without information on the intricacies of an underlying implementation

Design Basics
§ Hierarchy - Another approach to handle design complexity. A kind of
recursive approach, in which, the higher level modules ( compound)
contain sub-modules ( components) which further contain sub-
modules (components).
§ Instance A component may appear more than once in a compound
module. Every singular appearance is called a instances.
§ Design methodology - Assuming a top-down design methodology
Views, Abstraction and Hierarchical decomposition are used to reduce
design complexity.
¢ Design starts with a behavioral description of a design on a low level of detail, called
as top-level. It describes behavior of the design in terms of HDL constructs like
communicating processes, function / procedure (recursive) procedures, loops,
abstract data types, or variables.
¢ The design is either self-contained or has an interface defined in terms of high-level
data types. The design implementation is then partitioned into a hierarchy of
functional blocks, each of which is again defined by its behavior.

3
 Synthesis - Definition
§ In the context of the abstractions and domains synthesis can be
defined as-
A general term that describes the process of transformation of
the model of a design, from one level of abstraction in one
domain [ say HDL] to a lower ( more detailed ) level of
abstraction in same or other domain.
§ These transformations try to improve upon a set of objective
metrics (e.g., area, speed, power dissipation) of a design, while
satisfying a set of constraints.
§ Synthesis in its most generic form simply refers to the
incorporation of additional lower level implementation details
into a digital design, however, most current tools expect the
output to be a net list of gates that are optimized for area,
power, or latency.

Synthesis vs. simulation

§ Some Simulation constructs are not supported by Synthesis
tools. eg. y <= a and b after 5 ns; ( all timing clauses)
§ Synthesis tools ignore initial values.
eg. signal sum :std_logic = ‘0’;
§ Care should be taken that a simulation - synthesis mismatch
does not occur. Ex : Incomplete sensitivity lists.

process (a,b, c) process (a,b) Incomplete

Sensitivity list
begin begin
y <= a and b or c; y <= a and b or c;
end process; end process;

4
 What is Synthesis?
§ Synthesis = Translation + Optimization
§ Y = (A . B) + (C . D);
§ Synthesis is Target device technology Specific as shown below:

what is common / different in these three implementations?

A A A
B B Y
B Y
Y LUT
C C
C D
D
D

Generic ASIC FPGA

Synthesizer will try to use the best architectural resource of the target.

Synthesis Process
§ Translation [ language synthesis] : Design at higher level of
abstraction is compiled into known language elements.
§ Optimization – Algorithms are applied to make design small &
run fast.
§ Design is mapped using architecture specific techniques.

Translation
Optimization
a,b,c,d,sel : in std_logic;
Mapping
Z : out std_logic;
Z < = a + b when sel = 1
else c+d;

Hardware description
Intermediate
Written thinking about
Mix of boolean, other operations & Gate level
hardware
memory elements Technology specific

5
Synthesis – Target Technology Specific
a case sel is
a
b
sel[0]
LUT when “00” => z <= a; b F
sel[0]
sel[1] when “01” => z <= b;
when “10” => z <= c; H z
c
d z when “11” => z <= d;
sel[0] LUT
LUT when others => z <=
a
G
sel[1] cascade
b CLB
sel[0]
(others => ‘X’);
end case;

o
a sel[1]
sel[1]
b o
z a o
b a
c sel[0]
b
d z
z o
sel[0] a c
b o
PFUMUX d
sel[1] sel[0]
sel[0] o
o
Lucent Technologies

Synthesis – Design Flow

HDL behavioral
description

RTL synthesis
RTL optimization

High-level description with

Boolean Equations

Logic optimization

Structured Boolean
Equations

Technology/Mapping Gate-
level optimization

(optimized) netlist

6
 Synthesis – Design Flow
§ Synthesis and Optimization processes generate a gate-level net list for the
target technology.
§ This netlist can be optimized under constraints such as area or speed.

Synthesis process is as follows :

§ Translation – Input data is transformed into a description based on Boolean
equations.
§ A technology-independent logic-level optimization based upon the Boolean
equations, is performed by applying rules of Boolean Algebra.
¢ This eliminates redundant logic and reduces the area requirement or
delay of the circuit.
¢ Logic level optimization is split into two phases :
Flattening and Structuring

§ Technology Mapping:
Mapping is technology dependent, the optimized logic is mapped to the
Technology library.
It implies mapping truth table of a portion of the logic to the truth table of a
particular cell in the target technology. Synthesizer selects smallest cell that
matches functionality.

Logic Level Optimization Tasks

§ Flattening converts multilevel combinational logic into 2 level sum
of products form.

§ Structuring is the opposite of flattening, it adds structure to

generic design by extracting common logic factors &
representing them as intermediate nodes to produce compact
logic
Y = A.B.C Flatten Y2 = A.B.C + A.B.D
Six gates
Y2 = Y + A.B.D Y3 = A.B + C+ D
Y3 = A.B + C+ D
Structure
Original equation
M = A.B
N = C+D
Four gates
Y2 = A.B.[C + D] = M.N
Y3 = M + N

7
 Flattening
§ Flattening
¢ Is the process where all the design hierarchy ( multi level logic) is
removed, the entire design is transformed into a flat, generic,
2-Level, sum-of-products (AND-OR form ).
¢ Factorization Most effective in 2-level from.
Performing boolean factorization and reduction in combinational
logic
¢ Transudation Reducing gate count by removing redundant logic

ƒY1 = (A + B)
A
ƒX1 = Y1.C = (A.C) + (B.C)
X1
A Y1 C
B
X1 B
C

Flattening
§ All intermediate brackets are removed.

§ Resulting equations do not imply any structure.

§ Good optimization results are obtained.

§ Tradeoff : In case of structured logic

ex. A Carry Look ahead adder, flattening would destroy its
characteristic structure and the associated properties.

§ Also, flattening cannot be applied to every logic circuit because

the number of product terms may become very large.

8
 Structuring
§ New intermediate variables are inserted during the structuring
process.
§ For ex. : If /B. occurs 10 times then the tool may assign X= /B
and use X everywhere. – create fan out problems.
§ Finally, the subfunctions are substituted into the original
equations.
§ Compared to the logic before structuring, the resulting area is
reduced. A
B Y0
C

A
Y1
C

Synthesis Process – Review

§ Translation process converts RTL to a Boolean form .
§ Optimization is done on the converted Boolean equations.
§ The optimized logic is then mapped to the Technology library.

Design
Constraints Libraries

Synthesis

Netlist Report

9
Synthesis Advantages
§ Speeds up the design process and hence fast time to market.
§ Forces higher Levels of Abstraction.
Leads to fewer errors, ease in debugging and code Portability.
§ Ability to search design space
¢ Encourages top-down design
¢ Can explore tradeoffs among many possible designs
¢ Allows technology independent design. A synthesized design can be
resynthesized into new technologies
A popular use is migrating FPGA designs to ASICs
§ Makes IC technology more accessible i.e. provides capability to non-
experts
§ Design meets criteria of Timing, Size, and Power, therefore bigger
possibility of meeting the design specifications in the first go.
§ Enables designer to focus on larger design goals, as it is easier to
relate RTL to Hardware.

Behavioral Synthesis Tasks

§ Resource Allocation:
¢ Selection of structures to implement functions.
§ Design Transformation:
¢ Changing a design to achieve a goal or meet a constraint without
adding additional detail.
§ (De)composition:
¢ Decomposing a function so it can be mapped into existing
structural components.
¢ Creating composite structures with no physical realization to
implement specified functions.
§ Event Scheduling:
¢ Scheduling available resources for each operation.

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 High Level Optimization
§ An advantage of synthesizing hardware language (i.e. VHDL) is the
Ability to analyze the code & perform optimizations on the descriptions
that can not be done by logic level optimization tools.
¢ High level operations may no longer be apparent at the gate level.
§ May powerful transformations no longer possible at logic optimization
¢ Comparator sharing for relational operations
¢ Function transformations
¢ Resource sharing/allocations e.g. ALU to perform numerous operations.
¢ bit pruning: providing only bits that are needed.
¢ Constant folding: replacing operators whose arguments are constants with
constants.
¢ Constant propagation
¢ Expression sharing
¢ Expression migration: moving repeated expressions out of loops, if clauses
& case statement clauses where possible.
¢ Dead code removal.

Synthesis Tools - Expectations

All Synthesis tools do not perform all expectations and do not
have all features.
Following are some of the expectations from a good synthesis
tool.
§ Should perform Technology Specific Optimizations.
e.g. Vendor specific FPGAs and CPLDs.
§ Best Optimization techniques should be available.
§ Designer should have control over the Synthesis Process.
§ Tool should have a broad Language Coverage.
§ Should provide a user friendly Debugging Environment.
§ Should have fast compile times.
Ideally, Compile time should be proportional to design density.
§ Should provide a clean and seamless link to the Backend Tools.

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Synthesis Tools - Features
§ Cost depends upon features.
§ Synthesis tools should provide features such as
¢ Control over Critical Path Synthesis.
¢ Identify & ignore all False paths.
A X
B
EnA EnA
C
D Y
EnB EnB
False Paths
¢ Resource Sharing of Adders, Incrementors, Decrementors and
Multipliers.
¢ Automatic RAM Inference.

Synthesis – State Machines

§ FPGA Designs are generally driven by Complex Finite State
Machines [ FSMs ].
§ Synthesizers have built in intelligence to detect and implement
FSM’s.
¢ They consider the FPGA architecture while implementing FSM’s.
¢ FPGA architectures are generally rich in Flip-flops.
Hence 1-hot Implementation Usually Yield the Best Results.

§ Synthesizers have a built in utility called as the FSM Compiler.

§ These decisions are taken by the FSM compiler.
We need not worry about these issues

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 Synthesis – State Machines
§ FSM Encoding
¢ Re-encodes Extracted State Machines, to One-hot or Binary
Coding as the need be.
¢ Optionally user can specify the desired Encoding Style. Hence
easily explore performance of different encoding styles without
changing HDL code.
¢ All FSM compilers support Sequential, Gray, One Hot encoding.

§ Optimizes
¢ States by, Analyzing the reachable States and removing the
Unreachable States
¢ Optimizes Next State Decoding Logic

§ Provides flexibility to user to turn on FSM Compiler on a SM by

SM Basis.

Memory Modeling

§ Memory can be described explicitly and implicitly.

¢ Structural instantiation is the explicit style of description.
¢ User can access specific hardware resources.
¢ Components have to reside in the library and the library needs to be
compiled and made visible within the users description.

§ Behavioral description is the implicit style of representation.

§ Today’s FPGAs have “Block Rams” built in them

Tools have the capability to map RAM inferred, to “Block Rams”.

13
 Latches and Flip-flops
When are latches inferred instead of Flip flops?
§ The class of storage element inferred during synthesis is
concerned with the:
¢ Library selected for synthesis.
¢ The expression of the behavior, i.e., the use of Level-sensitive vs.
Edge-sensitive trigger criteria.
Flip-Flop Reset and Preset
§ Flip flops should be either reset or preset usually on start up due to
the following reasons :
¢ Initial state of the Flip-flop may not be known after power up.
¢ Initial state of the Flip-flop might not be the desired value.
¢ We should place the system into a known state during operation as a
recovery feature.
¢ Simulation may fail or give wrong results.

Hardware Modeling Examples - Latch

§ Latch
data
y
begin D
process ( enable) Q
begin enable Latch
If enable = ‘1’ then C
y <= data ;
endif ;
end process;

14
 Synchronous and Asynchronous Reset
§ Synchronous Reset § Asynchronous Reset
Flip-flop reset on the active Flip-flop reset as soon as reset
edge of the clock while is asserted.
reset is held active.
if ( RST = ‘1’ ) then
if ( CLK’ event and CLK = ‘1’) Q <= ‘0’;
if ( RST = ‘1’ ) then elsif ( CLK’event and CLK = ‘1’) then
Q <= ‘0’; Q <= D;
else end if;
Q <= D;
end if;
end if;
d D
rst
Q q

d 0
D Clk
0 1 Q q

rst
clk

Hardware modeling - Multiplexer

§ architecture mux_a of mux is § “With-select” Statement
begin
process (in1, in2, ctrl) architecture with_ex_a of with_ex is
begin begin
if ctrl = '0' then with ctrl select
out1 <= in1; out1 <= in2 when '1',
else in1 when others;
out1 <= in2; end with_ex_a;
end if;
end process;
end mux_a;

30

15
 Hardware Modeling - Case
§ Case Is a series of parallel checks to check a condition.
§ Should always be complete and should be terminated with
“default” clause which will guarantee that all conditions are
covered.
§ Should be locally static I.e. we cannot have a “check” condition
that changes when it is being evaluated
process (A, B, C,D,SEL) A 00
begin
case SEL is
B 01 Y
when “00” => Y <= A; C 10
when “01” => Y <= B; D 11
when “10” => Y <= C;
when others => Y <= D; SEL
end case 2
End process

Hardware Modeling Examples “if else”

Generating Priority Logic
process (A, B, C,D,SEL)
D 0
begin
if SEL(2) = ‘1’ then C 1

Y = A;
SEL SEL[0] 0
elsif SEL(1) =‘1’ then
3
Y = B; 1
B
elsif SEL(0) = ‘1’ then
Y = C; SEL[1] 0
Y
else 1
A
Y =D;
end process; SEL[2]

16
 Hardware Modeling - Tri-state Buffer
§ Tri-state buffer

architecture tri_ex_a of tri_ex is

begin
out1 <= in1 when control = '1' else
'Z';
end tri_ex_a;

In1 Out1

CONTROL

33

Modeling Bidirectional Ports

§ The bi-directional signal gives two way communication. Can act in input
mode as well as output mode

§ Structure of a bi-directional signal

In Data
buffer
Data

Out Data
buffer
Control logic decides when output
CONTROL driver will be active

Hence when modeling bi-directional bus always SPLIT THE BIDIRECTIONAL

SIGNAL INTERNALLY INTO SEPARATE INPUT- BUS & OUTPUT-BUS.

17
 Modeling Bidirectional Ports
Consider communication between two bidirectional buses A & B.

process (dir, int_outbus, ext_bus)

begin
If dir=‘1’ then -- when dir = 1 internal data is output
ext_bus <= int_outbus;
end process;

int_inbus <= ext_bus when dir=‘0’ else --when dir =0 external

‘Z’; --is input data

DIR DATA FLOW

1 B to A
0 A to B

Signals
§ Represents wires within a circuit.
§ Signals can be used to connect design entities together &
communicate changes in values within a design.
§ Signals should be used instead of inout signals.
§ Each signal has a history of values i.e holds a list of values which
include current value of signal & set of possible future values that
are to appear on the signal.

architecture and_gt of anding is

signal temp : std_logic;
begin
U1 : AND2 portmap (a,b,temp); >
U2 : AND2 portmap (temp,a,b;
end and_gt;

18
 Variables
§ Variables are used and declared in a process.
¢ A variable cannot be used to communicate between processes.
§ Are objects with single current value and are used to store the
intermediate values between the sequential VHDL statements.
§ Can be declared & used inside the process statement only. But
retain their value throughout the entire simulation.

process ( a ) Note : a_int contains the total

variable a_int : integer := 1; number of events that occurred on
signal a
begin
a_int := a_int + 1;
end process;

Signals vs Variables
§ Signals or variables are the objects used to store intermediate value in
sequential region.
§ A Signal has three properties attached to it Type, Value, Time.
§ A Variable has only two properties attached to it Type and Value.

§ Signal assignments are done using <=

¢ Signal assignments are done at the end of process.
¢ Signals represent physical wires in the circuit.

§ Variable assignments are done using :=

¢ Variables assignments are done immediately and are executed
sequentially.
¢ Variables may or may not represent physical wires.

19
 Signals Vs Variables
§ Order dependency
¢ Signal assignments are order independent. Signal are updated at the end of
process.
Signals represent physical wires in the circuit.
¢ Variable assignments are order dependent, Variables assignments are
done immediately and are executed sequentially. Variables may or may not
represent physical wires.

§ Signal assignments under a clocked process are translated into

registers.
§ Variable assignment under a clocked process may or may not be
translated into registers.
§ Computed value is assigned to signal after specified delay called delta
delay
§ Variable assignment occurs immediately.

39

Hardware Modeling - “For loop”

process (word)
variable result : std_logic;
begin
result := ‘0’;
for I in 0 to 7 loop
result := result xor word (I);
end loop;
result0 <= result;
end process;

Assignment - Draw the hardware inferred if result is declared as a

SIGNAL
40

20
 Signals and Variables

architecture var of parity is

begin
process(a)
variable temp : std_logic;
begin
temp := '0';
for i in 0 to n loop
temp:=temp xor a(i);
end loop;
p<=temp;
end process;
end var;

Synthesis Guidelines
§ Style of HDL coding often has a direct impact on the results the
synthesis tool delivers.
¢ Partitioning of designs plays a very crucial role in achieving good
synthesis results.
¢ Synthesis tools provides best results when the critical path lies in
one hierarchical block as opposed to traversing multiple hierarchical
blocks.
§ Avoid OVER-Constraining the design - Design performance
suffers.
¢ Critical timing paths get the best placement and fastest routing
options.
¢ As the number of critical paths increases, the ability to obtain the
design performance objectives decreases.
¢ Run time increases.

21
 Guidelines - Fixed Tool / Target
§ Use technology primitives (macros) from the target technology
libraries wherever possible.
§ Try small designs on the target technology to find its limitations
and strengths.
§ Partition the design correctly.
¢ Eliminate glue logic at the top level.
¢ Partition block size based on the logic function.
¢ Separate random logic from structured logic – data path logic.
¢ It is recommended that Timing-Sensitive modules are separated
from the Area-Sensitive modules.
This allows designers to apply different optimization strategies
depending on the design goals.

Synthesis Guidelines
§ Use “case” statements rather than “if-else” statements whenever
possible.

Code 1 code 2
if (s = ‘0’) then Process(s)
pout = c; begin
elsif (s =“0”) then case s is
pout <= d; When “00” => pout <= c;
elsif (s=“10”) then When “01” => pout <= d;
pout <= e; When “10” => pout <= e;
else When others => pout <= f;
pout <= f; End case;
end if;

Case statements results in a better implementation. Why?

22
 Synthesis Guidelines
§ Careful use of parentheses can direct the synthesizer to
implement a circuit that maximizes its performance.

§ y <= a + b + c + d; y <= (a +b) + (c +d)

a b a b c d

+ c
+ +
+ d
+
y

+
y

Resource Sharing
§ Synthesis tools automatically performs a limited amount of
Resource sharing of arithmetic expressions that are mutually
exclusive.
§ Limitations of Resource sharing:
¢ Operators must be of the same type (for example, two adders)
¢ Operands must be of the same width (for example, 8-bit adders)

a ¢ The Hardware inferred by the Synthesizer becomes tool dependent.

a Process(sel)
c
begin
+

b + y if (sel = ‘0’)
y y = a + b;
b else
c d y = c + d;
end if;
+

d end process;
sel
sel

23
 Tricks - Operators Inside Loops
§ Operators are resource intensive compared to multiplexers. If
there is an operator inside a loop, the synthesis tool has to
evaluate all conditions.
§ Here the synthesis tool builds four adders and one multiplexer.
This implementation is only advisable if the select line “req” is a
late arriving signal. offset 0
Vsum 0
data +
always@(req or offset) offset 1
Vsum 1
begin
for(i = 1'b0; i <= 3; i = i+1)
data +
vsum[i] = data + offset[i]; offset 2
Vsum 2 SUM
sum = vsum[req];
end
data +
offset 3
Vsum 3
data + req

Good Coding Practices

§ Good coding style means that,
¢ The Synthesis tool can identify constructs within your code that it
can easily map to technology features.
¢ It is written while thinking hardware.

§ All Programmable Devices may have its own unique

architectural resources. For ex: Xilinx Virtex series has inbuilt
RAM.
¢ Readymade cores (Macros) are provided by vendors which are
optimized to the target technology.
– Ex. Cores in Xilinx.
¢ Many Synthesis tools automatically infer the architectural resource.
For ex. Synplify & Xilinx ISE have a feature called as “Automatic
RAM Inferencing”

24
 Good Coding Practices - Optimization
§ It is possible to change the functionality of the design slightly,
without violating the design specification constraints, and
improve the implementation for synthesis.
[2:0]
always @(posedge clk) din[2:0]
[2:0] =
begin count11 [2:0]
0 [2:0]
if (count==din) 000 D[2:0]
1
count<=3'b0; Q[2:0] [2:0] q[3:0]
count_5[2:0]
else clk q2:0]

count<=count+3'b1; [2:0]
[2:0]
end 1 +
un3_count[2:0]

§ Synthesizer infers a N-Bit Comparator since the HDL description

indicates that comparison has to be done for the range of the
input signal for each clock cycle.

Resource Sharing
§ Remedy
¢ Forced Resource Sharing
¢ Try to minimize the amount of Tool-specific features.

§ Sharing of operators can be forced.

sig1 <= a when x = ‘1’ else

c;
sig2 <= b when x = ‘1’ else
d;
z <= sig1 + sig2;

What is the Hardware generated ?

25
 Good Coding Practices - Optimization
§ If the specification allows that the comparison is done with 0,
and reduces the overall circuit size loading the counter with din,
and then counting down to zero.
always @(posedge clk) [0]
[1]
begin [2]
if (count==3'b0) count8 [2:0]
0 [2:0]
count<=din; sel[2:0]
[2:0] [2:0]
1
D[2:0]
Q[2:0] [2:0] q[3:0]
else count_5[2:0]
clk q[2:0]
count<=count-3'b1;
end if 111 +
[2:0]

un1_count[2:0]

§ Comparisons to constants are cheaper to implement. The above

behavior is much easier to synthesize, and results in a smaller
circuit

Decoder Optimization
always @ ( sel) dout[3:0]
begin
[1]
case (sel) [1:0] un1_un1_dout20
[0]
2'd0 : dout = 4'b0001; sel[1:0]
dout20 [1]
2'd1 : dout = 4'b0010; un1_dout20
2'd2 : dout = 4'b0100; [0]
default : dout = 4'd1000; [1]
end case [0] dout19

end [1]

always @ ( sel)
begin
case (sel) is [1 ]

2'd0 : dout = 4'b0001; [1 :0 ] [1 :0 ] [1 :0 ]

00 [3 :0 ] [3 :0 ]
2'd1 : dout = 4'b0010; [0 ]
s [1 :0 ] u n 1 _ s [1 :0 ] y _ 1 [3 :0 ] y [3 :0 ]
// 2’d2 : dout = 4’b0100; [0 ]
// 2'd3 : dout = 4’b1000;
default : dout = 4'bz;
end case
end

26
 Duplicating Logic to Improve Speed

§ Most synthesis tools have a fanout control

¢ Be careful, the tools don’t always pick the best implementation
creating a more difficult design to place and route
§ Better to explicitly duplicate logic in code
¢ you may need to use the syn_keep option for combinational logic
§ Good Examples to duplicate:
¢ Address and control lines to large RAM
¢ Clock enables
¢ Synchronous reset signal
¢ Other high fan out nets

Tricks- Duplicating Logic

§ We can duplicate the logic which generates the signal for
minimizing fan-out.
§ Trade-off : Loading effect of signals is reduced thereby
speeding propagation at the cost of Logic and Interconnect
complexity.
fn1 D Q fn1 D Q

CLK CLK

fn1 D Q

CLK

27
 Tricks – Reducing Logic Levels
§ Reducing Logic Levels on Critical Paths
¢ Meeting timing constraints on a critical path with too many logic
levels becomes difficult because each logic level on the critical path
in an design can add significant delay.
¢ To ensure that timing constraints can be met, logic level usage must
be considered when describing the behavior of a design.
¢ The signal “critical” is a late arriving signal. The signal “critical” goes
through three logic levels.
CpuG
Critical
Obi
Sar
Des
CpuR

Tricks - Operand Reordering

§ Definition
¢ Use algebraic identities to prioritize signals
“A + B = C” is equivalent to “A = C - B”
§ Pros and Cons
¢ Can dramatically improve timing on critical signals
¢ Usually no area penalty
¢ Requires minor changes to source code

§ When to use it
¢ A small subset of signals have priority
¢ Need to move critical signals past an operator

28
 Operand Reordering
signal Addr, offset, target [31:0];
signal match ;
If (addr + offset = target) then
match <= ‘1’;
end if;

[31:0]
target[31:0] [31:0]
[31:0] [31:0]
addr[31:0]
[31:0] = match
[31:0] [31:0]
offset[31:0] +
match
match_1[31:0]
Original source - target has priority

Gated Clock
§ Remedy: A Synchronous method
Also called as early TC detection.

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 Constraints
§ Constraints are means of communicating our requirements to the
Synthesis and Backend tools.
§ Categories of constraints are :
¢ Timing Constraints
Maximum frequency
Duty cycle
Input delays
Output delays
False paths
§ Run a trial run without constraints to get an idea of what is
possible and what is not.
§ Leave some allowances for future expansions also.

Common VHDL / Synthesis Misperceptions

§ VHDL and its synthesis tools produce unexpected results

§ VHDL does not produce efficient circuitry
§ The synthesis tool will not produce what is desired
§ VHDL is for software folks

VHDL and Design

§ One should not start writing VHDL code until the design is well
understood and analyzed
§ Anyone can pick up a VHDL book and learn syntax
§ Anyone can pick up a synthesis manual and learn directives
§ But how do we create reliable circuits?

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 Keys to Success with Synthesis
§ “Think in Hardware”
¢ Be sure what will be used; e.g., latch, mux
¢ Be aware of relative timing of different signals with respect to the
clock edge
¢ Improve performance by:
Avoiding unnecessary priority structures in logic
Optimizing logic for late arriving signals
Structuring arithmetic for performance
Avoiding area inefficient code
Buffering high fanout signals
Pipelining for high performance

Keys to Success with Synthesis

Key Ingredients for Successful and Reliable Designs:
VHDL through Synthesis

§ Remember … the goal is to design reliable hardware.

§ VHDL – looks like software, however, the designer must
understand proper hardware design techniques including the
electrical characteristics of the employed technology
§ VHDL RTL must functionally match gate level (post synthesis) for
simulation purposes. This requires enforcing strict coding rules

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 Keys to Success with Synthesis
§ Designer must be familiar with the synthesis tools and their
interpretation of VHDL code
¢ Combinatorial circuits vs. Sequential
¢ Clock structures and potential skew
¢ Proper State machine implementation
¢ Arithmetic circuitry
¢ Clock domain crossings
¢ Reset logic
¢ When to use specific Synthesis directives

§ VHDL Coding Style is very important

Keys to Success with Synthesis

Importance of VHDL Coding Styles.

§ No Synthesis tool can be as efficient as proper Coding Style

§ ASICS and FPGAs will be smaller and faster.
§ Proper VHDL Coding Style is easier to verify
§ We would like to shorten the Design Cycle. Coding Style will
affect
¢ Quality of Synthesis: drive to tool to better results,
¢ FPGA mapping or design: can take advantage of the technology
¢ Place and Route: designs that are well thought out will have a clean
route

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 Coding Style Specifics - Think “Hardware”
§ Architect with comprehension of your target’s features (ASIC and
FPGA)
§ Separate Combinational and Registered blocks
§ Watch out for inferred latches
§ Pay attention to large fan-out nets
§ Consider how you code state machines
§ Be careful with designing long paths of logic
§ Be aware of when you are able to use Resource sharing

Keys to Success with Synthesis

§ Simulate your design before synthesis
¢ Logic errors that are not caught are passed on during synthesis and the
synthesized results will contain the same logic errors.
§ Avoid mixed clock edges
¢ If a large number of both positive and negative edge flip-flops are required
then they should be placed in different modules.
§ Coding for performance:
¢ Common mistake is to ignore hardware and start coding as if
programming. To achieve best performance, the designer must think about
Hardware.
§ Be aware of tool-specific “templates”
§ Avoid use of mode “buffer”
¢ Gate level VHDL Simulation models from ASIC vendors never use the
mode buffer.
¢ There is a potential for a port mode type mismatch when using mode
“buffer”. This may result into problems during integration of different
blocks.

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Synthesis Shortcomings
§ Design partitioning
A difficult problem requiring much user interaction

§ Circuit timing estimates

High-level synthesis tools must use pre-layout estimates which
lose accuracy for large circuits ( errors may accumulate)

§ Designer finds it difficult to associate resulting design with

original description
e.g. HDL Analyst in Synplify a good featured but not user
friendly

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