Introduction

(What is Logic Synthesis?)

VLSI Design, EE, FAST-NU, Islamabad 3

 What is Logic Synthesis?
module counter(
input c l k , r s t n , load,
• Synthesis is the process that converts RTL input [ 1 : 0 ] i n , output
reg [ 1 : 0 ] o u t ) ;
into a technology- specific gate-level netlist,
always @(posedge c l k )
optimized for a set of pre-defined i f ( ! r s t n ) out <= 2 ' b 0 ; else
constraints. i f ( l o a d ) out <= i n ; el s e
out <= out + 1 ;
• You start with: endmodule
• A behavioral RTL design

Synthesis
Standard Cell Library
• A standard cell library
• A set of design constraints Design Constraints
• You finish with: module counter ( c l k , r s t n , l o a d , i n , out ) ;
input [ 1 : 0 ] i n ;
• A gate-level netlist, mapped to the output [ 1 : 0 ] o u t ;
input c l k , r s t n ,
standard cell library load;

• (For FPGAs: LUTs, flip-flops, and RAM blocks) w ire N6, N7, n5, n6, n7, n8;

• Hopefully, it’s also efficient in terms of speed, FFPQ1 out_reg_1 ( . D ( N 7 ) , . C K ( c l k ) , . Q ( o u t [ 1 ] ) ) ;

FFPQ1 out_reg_0 ( . D ( N 6 ) , . C K ( c l k ) , . Q ( o u t [ 0 ] ) ) ;
area, power, etc. NAN2D1 U8 ( . A1 ( o u t [ 0 ] ) , . A 2 ( n 5 ) , . Z ( n 8 ) ) ;
NAN2D1 U9 ( . A1 ( n 5 ) , . A 2 ( n 7 ) , . Z ( n 6 ) ) ;
INVD1 U10 ( . A( l o a d ) , . Z ( n 5 ) ) ;
VLSI Design, EE, FAST-NU, Islamabad
endmodule 4
 What is Logic Synthesis?

• Given: Finite-State Machine F(X, Y, Z, λ, δ)

where:
• X: Input alphabet
• Y: Output alphabet
• Z: Set of internal states
• λ: X × Z → Z (Next State Function)
• δ: X × Z → Y
• Target: Circuit C(G, W) where:
• G: set of circuit components
G = {Boolean gates, flip-flops, etc.}
• W: set of wires connecting G
5
 Motivation

• Why perform logic synthesis?

• Automatically manages many details of the design process:
• Fewer bugs
• Improves productivity
• Abstracts the design data (HDL description) from any particular implementation technology
• Designs can be re-synthesized targeting different chip technologies;
• E.g.: first implement in FPGA then later in ASIC
• In some cases, leads to a more optimal design than could be achieved by
manual means (e.g.: logic optimization)

• Why not logic synthesis?

• May lead to less than optimal designs in some cases

6
Simple Example
module foo ( a , b , s 0 , s 1 , f ) ;
input [ 3 : 0 ] a;
input [ 3 : 0 ] b;
i n p u t s 0,s 1;
output [ 3 : 0 ] f ;
reg f ;

always @(a or b or s0 or s1)

i f ( ! s 0 && s1 | | s0)
f=a;
else
f=b;
endmodule
 Goals of Logic Synthesis
• Minimize area
• In terms of literal count, cell count, register count, etc.
• Minimize power
• In terms of switching activity in individual gates, deactivated circuit blocks, etc.
• Maximize performance
• In terms of maximal clock frequency of synchronous systems, throughput for
asynchronous systems
• Any combination of the above
• Combined with different weights
• Formulated as a constraint problem
• “Minimize area for a clock speed > 300MHz”
• More global objectives
• Feedback from layout
• Actual physical sizes, delays, placement and routing
8
 How does it work?
Variety of general and ad-hoc (special case) methods:
• Instantiation:
• Maintains a library of primitive modules (AND, OR,etc.) and user defined modules
• “Macro expansion”/substitution:
• A large set of language operators (+, - , Boolean operators, etc.)
and constructs ( i f - e l s e , case) expand into special circuits
• Inference:
• Special patterns are detected in the language description and treated specially
(e.g.,: inferring memory blocks from variable declaration and read/write statements, FSM detection
and generation from always@(posedge c l k ) blocks)
• Logic optimization:
• Boolean operations are grouped and optimized with logic minimization techniques
• Structural reorganization:
• Advanced techniques including sharing of operators, and retiming of circuits (moving FFs), and
others

9
 Basic Synthesis Flow
• Syntax Analysis:
• Read in HDL files and check for syntax errors.
read_hdl – v e r i l o g sourceCode/toplevel.v Syntax Analysis

• Library Definition:
• Provide standard cells and IP Libraries. Library Definition
read_libs “ / d e s i g n / d a t a / m y _ f a b / d i g i t a l / l i b / T T 1 V 2 5 C . l i b ”

• Elaboration and Binding: Elaboration and

Binding
• Convert RTL into Boolean structure.
• State reduction, encoding, register infering.
Constraint Definition
• Bind all leaf cells to provided libraries.
elaborate t o p l e v e l

• Constraint Definition:
• Define clock frequency and other design constraints.
read_sdc s dc /c ons trai nts .s dc

10
 Basic Synthesis Flow Syntax Analysis

• Pre-mapping Optimization:
Library Definition
• Map to generic cells and perform additional heuristics.
syn_generic
Elaboration and
• Technology Mapping: Binding
• Map generic logic to technology libraries.
syn_map Constraint Definition
• Post-mapping Optimization:
• Iterate over design, changing gate sizes, Boolean literals, Pre-mapping
architectural approaches to try and meet constraints. Optimization
syn_opt
• Report and export Technology Mapping
• Report final results with an emphasis on timing reports.
r e p o r t ti mi ng –num paths 10 > r e p o r t s / t i m i n g _ r e p o r t s . r p t Post-mapping
Optimization
• Export netlist and other results for further use.
wri te_hdl > e x p o r t / n e t l i s t . v Report and export
11
Compilation
(What is Logic Synthesis?)

VLSI Design, EE, FAST-NU, Islamabad 12

 1 2 3 4 5 6
Introduction Compilation Library Def. LE Liberty Other
F

Syntax
Analysis
Library
Definition
Elaboration
and Binding
Pre-mapping
Optimization
Constraint

Compilation Definition
Technology
Mapping

…but aren’t we talking about synthesis? Post-mapping

Optimization
Report and
export

Integrated Circuit Design Lab

 Compilation in the Synthesis Flow Syntax
Analysis
Library
Definition
Elaboration

• Before starting to synthesize, and Binding

Pre-mapping
Optimization
we need to check the syntax for correctness. Constraint
Definition
• Synthesis vs. Compilation: Technology
Mapping
• Compiler Post-mapping
• Recognizes all possible constructs in a formally defined program language Optimization
Report and
• Translates them to a machine language representation export

of execution process
• Synthesis
• Recognizes a target dependent subset of a hardware
description language
• Maps to collection of concrete hardware resources
• Iterative tool in the design flow

14
 Compilation with NC-Verilog

• To compile your Verilog code for syntax Syntax

Analysis
checking, use the NC-Verilog tool: Library
Definition
ncvlog <filename.v> Elaboration
and Binding
• This will quickly run compilation on your Verilog source code Pre-mapping
Optimization
and point you to syntax errors.
Constraint
• Alternatively, use the i r u n super command: Definition
Technology
i r u n -compile <filename.v> Mapping
Post-mapping
Optimization
Report and
export

15
 1 2 3 4 5 6
Introduction Compilation Library Def. LE Liberty Other
F

Syntax
Analysis
Library
Definition
Elaboration
and Binding
Pre-mapping
Optimization
Constraint
Definition

Library Definition Technology

Mapping
Post-mapping
Optimization
Report and
export

16 Integrated Circuit Design Lab

 It’s all about the standard cells…
• The library definition stage tells the synthesizer where to Syntax
Analysis

look for Library

Definition

leaf cells for binding and the target library for technology Elaboration
and Binding

mapping. Pre-mapping
Optimization
• We can provide a list of paths to search for libraries in: Constraint
Definition
set_db init_lib_searc h_path “ / d e s i g n / d a t a / m y _ f a b / d i g i t a l / l i b / ” Technology

• And we have to provide the name of a specific library, usually

Mapping
Post-mapping
characterized for a single corner: Optimization

read_libs “TT1V25C.lib” Report and

export

• We also need to provide . l i b files for IPs, such as memory

macros, I/Os, and others.
Make sure you understand all the warnings about the libs that the
synthesizer spits out, even though you probably can’t fix them.

17
 But what is a library? Syntax
Analysis
Library
Definition

• A standard cell library is a collection of well defined and Elaboration

and Binding
appropriately characterized logic gates that can be used to Pre-mapping
Optimization
implement a digital design. Constraint

• Similar to LEGO, standard cells must meet predefined

Definition
Technology
specifications to be flawlessly manipulated by synthesis, Mapping
Post-mapping
place, and route algorithms. Optimization
Report and
• Therefore, a standard cell export

library is delivered with a

collection of files
that provide all the information needed
by the various EDA tools.
18
 What cells are in a standard cell library?
• Combinational logic cells (NAND, NOR, INV, etc.):
Syntax
Analysis
• Variety of drive strengths for all cells. Library
Definition
• Complex cells (AOI, OAI, etc.) Elaboration
• Fan-In <= 4 and Binding
Pre-mapping
• Buffers/Inverters Optimization
Constraint
• Larger variety of drive strengths. Definition
AND-OR
• “Clock cells” with balanced rise and fall delays. Technology
INVERT Mapping
• Delay cells (AOI) Post-mapping
Optimization
• Level Shifters
Report and
• Sequential Cells: export

• Many types of flip flops: pos/negedge, set/reset, Q/QB, enable

• Latches
• Integrated Clock Gating cells
• Physical Cells:
• Fillers, Tap cells, Antennas, DeCaps, EndCaps, Tie Cells
19
 Syntax
Multiple Drive Strengths and VTs Analysis
Library
• Multiple Drive Strength Definition

• Each cell will have various sized output stages. Elaboration

and Binding
• Larger output stage  Pre-mapping
Optimization
better at driving fanouts/loads.
Constraint
• Smaller drive strength  Definition
Technology
less area, leakage, input cap. Mapping
Post-mapping
• Often called X2, X3, or D2, D3, etc. Optimization
Report and
• Multiple Threshold (MT-CMOS) export

• A single additional mask can provide more or less doping

in a transistor channel, shifting the threshold voltage.
• Most libraries provide equivalent cells with
three or more VTs: SVT, HVT,LVT
This enables tradeoff between speed vs. leakage.
• All threshold varieties have same footprint and therefore can
be swapped without any placement/routing iterations.
20
 Cell Width
Example Syntax
Analysis

• NAND standard cell layout Library

Definition

• Pay attention to:

Elaboration
and Binding

• Cell height Pre-mapping

Optimization

• Cell width Constraint

Cell Height
Definition
• Voltage rails Technology
Mapping
• Well definition Post-mapping
• Pin Placement Optimization
Report and
• PR Boundary export

• Metal layers

Ideally, Standard Cells should

be routed entirely in M1 !
21
Example
 Example

NOR3D0 NOR3D4

AND2D0

INVD0 INVD1 INVD2 NORD0 AND2D0

Example
 Syntax
Analysis
Clock Cells Library
Definition

• General standard cells are optimized for speed. Elaboration

and Binding

• That doesn’t mean they’re balanced… Pre-mapping

Optimization
 tp,LH  t p,HL  Constraint
min tpd  min  t p,LH  t p,HL
Definition

 2 
 Technology
Mapping
• This isn’t good for clock nets… Post-mapping
Optimization
• Unbalanced rising/falling delays will result in unwanted skew. Report and
• Special “clock cells” are designed with balanced rising/falling delays to export

minimize skew.
• These cells are usually less optimal for data and so should not be used.
• In general, only buffers/inverters should be used on clock nets
• But sometimes, we need gating logic.
• Special cells, such as integrated clock gates, provide
logic for the clock networks.
25
 Sequentials Syntax
Analysis
Library
Definition
Elaboration
• Flip Flops and Latches, including and Binding
Pre-mapping
• Positive/Negative Edge Triggered Optimization

• Synchronous/Asynchronous Reset/Set Constraint

Definition
• Q/QB Outputs Technology
Mapping
• Enable Post-mapping

• Scan Optimization
Report and
• etc., etc. export

26
Example
 Syntax

Filler and Tap Cells Analysis

Library
Definition

• Filler cells Must be inserted in empty areas in rows Elaboration

and Binding
• Ensure well and diffusion mask continuity
Pre-mapping
• Ensure density rules on bottom layers Optimization
• Provide dummy poly for scaled technologies Constraint
Definition
• Sometimes, special cells are needed at the boundaries of
Technology
rows - “End Caps” Mapping
• Other fillers may include MOSCAPs Post-mapping
Optimization
between VDDand GNDfor voltage stability - “DeCAP cells” Report and
export

• Well Taps needed to ensure local body voltage

• Eliminate latch-up
• No need to tap every single cell
• Back or forward biasing for performance/leakage optimization
• N-w ell voltage different from VDD
• Substrate or P-w ell (triple well process) voltage different from VSS
• Bias voltage routed as signal pin or special power net
24
 Engineering Change Order (ECO) Cells
• An Engineering Change Order (ECO) is a very late change in the design.
• ECOs usually are done after place and route.
• However, re-spins of a chip are often done without
recreating all-masks. This is known as a “Metal-Fix”.
• ECOs usually require small changes in logic.
• How can we do this after placement?
• Or worse – after tapeout???
• Solution – Spare (Bonus) Cells!
• Cells without functionality
• Cells are added during design (fill)
• In case of problems (after processing) new metal
and via mask cells get their wanted functionality
• Cell combinations can create more complex functions

• Ex. AND,NAND,NOR,XOR,FF,MUX, INV,..

25
• Special standard cells are used to differentiate from real cells.
 Syntax
Analysis

My favorite word… ABSTRACTION! Library

Definition
Elaboration

• So, what is a cell?

and Binding
Pre-mapping
Optimization
• I guess that the detailed layout is sufficient to know (guess) Constraint
anything and everything about a standard cell. Definition

• Or it would be easier, if we got the whole Technology

Mapping
Open Access database of the cell… Post-mapping
Optimization
• But do we really need to know everything? Report and
export
• For example, does logic simulation need to know
if your inverter is CMOS or Pseudo-NMOS?
• And does a logic synthesizer need to know
what type of transistors you used?
• No!
• To make life (and calculations) simpler, we will abstract away this info.
• Each tool will get only the data it really needs.
26
 Syntax

What files are in a standard cell Analysis

Library

library?
Definition
Elaboration
and Binding
• Behavioral Views: Behavioral (.v) Pre-mapping

• Verilog (or Vi t a l ) description used for simulation, Optimization

Constraint
logic equivalence. Abstract (.lef) Definition

• Physical Views: Technology

Mapping
• Layout of the cells (GDSII format) for DRC, LVS, Custom Layout. Layout (.gds)
Post-mapping
Optimization
• Abstract of the cells (LEF format) for P&R, RC extraction.
• Transistor Level: Spice (.spi, .cdl) Report and
export
• Spice/Spectre netlist for LVS, transistor-level simulation.
• Often provided both with parasitics (post-layout) and without. Timing (.lib)
• Timing/Power:
• Liberty files with characterization of timing and power for STA.
• Power Grid Views:
• Needed for IR Drop analysis.
• Others: Open Access (.oa)
• Symbols for displaying the cells in various tools.
27 • OALibraries for easy integration with Virtuoso.
 1 2 3 4 5 6
Introduction Compilation Library Def. LEF Liberty Other

Syntax
Analysis
Library
Definition
Elaboration
and Binding
Pre-mapping
Optimization
Constraint
Definition

Library Exchange Format (LEF) Technology

Mapping
Post-mapping
Optimization
Report and
export

Integrated Circuit Design Lab

 Library Exchange Format (LEF)
VDD
• Abstract description of the layout
A B
for P&R
• Readable ASCII Format.
Y Layout View
• Contains detailed PIN information for
connecting.
• Does not include front-end of the line GND
(poly, diffusion, etc.) data. VDD
• Abstract views only contain the
following: A B Metal
• Outline of the cell (size and shape) Pins
• Pin locations and layer (usually on M1) Y
• Metal blockages Abstract View
(Areas in a cell where metal of a certain NAND_1
layer is being used, but is not a pin) GND
29
 Syntax
Analysis

Library Exchange Format (LEF) Library

Definition
Elaboration
and Binding
Pre-mapping
Optimization
Constraint
Definition
Technology
Mapping
Post-mapping
Optimization
Report and
export

30
 Syntax
Analysis
Technology LEF Library
Definition

• Technology LEF Files contain (simplified) information about Elaboration

and Binding
the technology for use by the placer and Pre-mapping
Optimizatio n
router: SITE CORE
Constraint
CLASS CORE; Definition
• •Layers
Name, such as M1, M2, etc. SIZE 0.2 X 1 2 . 0 ; Technology
ENDCORE Mapping

• Layer type, such as routing, cut ( via ) LAYER MET1 Post-mapping

Optimizatio n
TYPE ROUTING ;
• Electrical properties (R, C) PITCH 3.5 ; Report and
export
• Design Rules WIDTH 1.2 ;
• Antenna data SPACING 1.4 ;
DIRECTION HORIZONTAL ;
• Preferred
• SITE (x and routing
y griddirection
of the library)
RESISTANCE RPERSQ.7E-01 ;
• COREsites are minimum standard cell size CAPACITANCE CPERSQDIST .46E-04 ;
• Can have site for double height cells! LAYER VIA
ENDMET1
TYPE CUT;
• IOs have special SITE. ENDVIA
• Via definitions
Additional files provide parasitic extraction rules. These can be
• Units
• Grids for layout and routing basic (“cap tables”) or more detailed (“QRC techfile). These may be
31
provided as part of th
 VDD Syntax
Analysis

Technology LEF W1
Library
Definition
Elaboration
and Binding

• Cell height is measured in Tracks W4

Pre-mapping
Optimization
• A Track is one M1pitch Constraint
W3 Definition
• E.g., An 8-Track Cell has room for W2
H
Technology
8 horizontal M1 wires. Mapping
Post-mapping
• The more tracks, the wider the Optimization
Report and
transistors, the faster the cells. export

• 7-8 low-track libraries for area W1

efficiency VSS

• 11-12 tall-track libraries for

Parameter Symbol
performance, but have high leakage
Cell height (# tracks) H
• 9-10 standard-track libraries for a Power rail width W1
reasonable area-performance tradeoff Vertical grid W2
Horizontal grid W3
N-Well height W4
36
 Syntax
Analysis

Technology LEF Library

Definition
Elaboration
Cell and Binding

• Cells must fit into a predefined Origin Pre-mapping

Optimization
grid Constraint
Definition
• The minimum Height X Width Technology
PR Mapping
is called a SITE. Boundary Post-mapping
Optimization
• Must be a multiple of the minimum Report and
X-grid unit and row height. Horizontal export

• Cells can be double-height, for example. Grid

• Pins should coincide with routing

Vertical
tracks Grid

• This enables easy connection

SITE CORE
of higher
metals to the cell. CLASS CORE;
SYMMETRYXY;
SIZE 0.2 X 1 2 . 0 ;
ENDCORE
37
 The Chip Hall of Fame

• After checking out two Intel chips, we better

not forget

wikichip.org

• Racking up Kahoot points on your smartphone?

Then you probably should pay tribute to the granddaddy of that chip inside.
• Release date: April 1985 Manufactured by VLSI Technology
• Transistor Count: 25,000 Process: 3 um CMOS
• 32-bit ARMv1 architecture
• ARM stands for “Acorn RISC Machine”
• The reference design was written in 808 lines of BASIC!
• Never sold as a commercial product, but as a co-processor for BBC Micro.
2017 Inductee to the IEEE Chip Hall of Fame
 1 2 3 4 5 6
Introduction Compilation Library Def. LE Liberty Other
F

Syntax
Analysis
Library
Definition
Elaboration
and Binding
Pre-mapping
Optimization
Constraint
Definition

Liberty Timing Models (.lib) Technology

Mapping
Post-mapping
Optimization
Report and
export

Integrated Circuit Design Lab

 Syntax
Analysis

Liberty (.lib): Introduction Library

Definition
Elaboration
and Binding

• How do we know the delay through a gate in a logic Pre-mapping

Optimization
path? Constraint
Definition
• Running SPICE is way too complex. Technology
Mapping
• Instead, create a timing model that will simplify the calculation. Post-mapping

• Goal:
Optimization

tpd Report and

• Propagation
• For Delay
every timing arc, (t pd)
calculate: export

• Output transition (trise, tfall)

• Based on:
• Input net transition (trise, tfall)
tf
• Output Load Capacitance (Cload)

Note that every . l i b will provide timing/power/noise information for a

single corner, i.e., process, voltage, temperature, RCX, etc.
36
 Syntax

Liberty (.lib): General

Analysis
Library
Definition
Elaboration
• Timing data of standard cells l i b r a r y (n a m e of libra ry) {
. . . / * L i b r a r y l e v e l simple and complex a t t r i b u t e s * /
and Binding
Pre-mapping
is provided in the Liberty / * Cell definitions * / Optimization

format. c e l l (cell_name) { Constraint

Definition
. . . / * c e l l l e v e l simple a t t r i b u t e s * /
• Library: / * p in groups w i t h i n the c e l l * / Technology
Mapping
• General information common to pin(pin_name) {
. . . / * p in l e v e l simple a t t r i b u t e s * / Post-mapping
all cells in the library. Optimization
• For example, operating conditions, / * t im in g group w i t h i n the p in l e v e l * / Report and
timing(){ export
wire load models, look-up tables . . . / * t im in g l e v e l simple a t t r i b u t e s * / }
• Cell: . . . / * a d d i t i o n a l t im in g groups * /

• Specific information about each . . . / * more p in d e scrip t io n s * /

} / *} end o f coef lpl in
/ * end */*/
standard cell. . . . / * more c e l l s * /
• For example, function, area. } / * end o f l i b r a r y * /

• Pin:
• Timing, power, capacitance,
leakage, functionality, etc.
characteristics of
37
each pin in each cell.  Adam Teman, 201 8
 Syntax
Analysis

Liberty (.lib): Timing Models Library

Definition
Elaboration
and Binding
• Non-Linear Delay Model Pre-mapping
Optimization

(NLDM) Constraint
Definition
• Ramp voltage source
• Driver model: Technology
• Fixed drive resistance lu_table_template(delay_template_5x5) { Mapping
variable_1 : i n p u t _ n e t _ t r a n s i t i o n ;
• Receiver model: variable_2 : total_output_net_capacitance; Optimization
Post-mapping

• Min/max rise/fall input caps Report0"

index_1 ( " 1 0 0 0 . 0, 1001.0, 1002.0, 1003.0, 1004. and
);
export
• Very fast index_2 ( " 1 0 0 0 . 0, 1001.0, 1002.0, 1003.0, 1 0 0 4 . 0 " ) ;
}
• Doesn’t model cap variation during transition.
• Loses accuracy beyond 130nm c e l l (INVX1) {
pin(Y) {

tpd =f tinput ,Cload 

timing() {
tpd cell_rise(delay_template_5x5) {
values ( \
"0.147955, 0.218038, 0.359898, 0.922746, 1.76604", \
tf "0.224384, 0.292903, 0.430394, 0.991288, 1.83116", \
"0.365378, 0.448722, 0.584275, 1.13597, 1.97017", \
"0.462096, 0.551586, 0.70164, 1.24437, 2.08131", \
"0.756459, 0.874246, 1.05713, 1.62898, 2.44989"); }
38
 Syntax
Analysis

Liberty (.lib): Timing Models Library

Definition
Elaboration
and Binding

• Non-Linear Delay Model Pre-mapping

Optimization
(NLDM) Constraint
Definition
• Delay calculation Technology
Mapping
interpolation Post-mapping
Optimization
Report and
export

39
 Liberty (.lib): Timing Models

• Current Source Models

(CCS, ECSM)
• Model a cell's nonlinear output
Courtesy: Cadence
behavior as a current source
• Driver model:
• Nonlinear current source
• Receiver model:
• Changing capacitance
• Requires many more values
• Requires a bit more
calculation
• Essential under 130nm
• Within 2% of SPICE.
Courtesy: Synopsys
40
 Syntax
Analysis

Liberty (.lib): Timing Models Library

Definition
Elaboration
and Binding

• NLDM vs CCS/ECSM Pre-mapping

Optimization
Constraint
Definition
Technology
Mapping
Post-mapping
Optimization
Report and
export

41 Courtesy: Synopsys A
 Syntax
Analysis

Liberty (.lib): Wire Load Models Library

Definition
Elaboration
and Binding

• How do you estimate the parasitics (RC) of a net Pre-mapping

Optimization
before placement and routing? Constraint
Definition

• Wire Load Models estimate the parasitics based on the Technology

Mapping

fanout of a net. l i b r a r y (myLib) {

Post-mapping
Optimization
wire _load( “ WLM1” ) Report and
r e s i s t a n c e : 0.0006 ; / / Rper u n i t length export
capacitance: 0.0001 ; / / Cper u n i t length
area : 0.1 ; / / Area per u n i t length
slope : 1.5 ; / / Used f o r l i n e a r e xt r a p o l a t i o n
f a n o ut_l eng th(1, 0.002) ; / / f o r f o =1 , Lwire=0.002
f a n o ut_l eng th(2, 0.006) ; / / f o r f o =2 , Lwire=0.006
f a n o ut_l eng th(3, 0.009) ; / / f o r f o =3 , Lwire=0.009
f a n o ut_l eng th(4, 0.015) ; / / f o r f o =4 , Lwire=0.015
f a n o ut_l eng th(5, 0.020) ; / / f o r f o=5, Lwire=0.020
f a n o ut_l eng th(6, 0.028) ; / / f o r f o =6 , Lwire=0.028
}
} / * end o f l i b r a r y * /
http://www.vlsi-expert.com/
46
 Syntax
Analysis

Physical-Aware Synthesis Library

Definition
Elaboration
and Binding

• Due to the lack of accuracy, wireload models lead to very Pre-mapping

Optimization

poor correlation between synthesis and post-layout in Constraint

Definition
nanometer technologies. Technology
Mapping

• Instead, use physical information during synthesis Post-mapping

Optimization

• Synopsys calls this “Topographical Mode” Report and

export

• Cadence calls this “Physical Synthesis”

• Physical-Aware Synthesis basically runs placement inside the
synthesizer to obtain more accurate parasitic estimation:
• Without a floorplan, just using .lef files
• After first iterations, import a floorplan .def to the synthesizer.
syn_opt - p h ys i c a l

47
 1 2 3 4 5 6
Introduction Compilation Library Def. LE Liberty Other
F

Syntax
Analysis
Library
Definition
Elaboration
and Binding
Pre-mapping
Optimization
Constraint
Definition

Other Contents of SC Library Technology

Mapping
Post-mapping
Optimization
Report and
export

Integrated Circuit Design Lab

 Syntax
Analysis

Other contents of SC Library Library

Definition
Elaboration
and Binding

• Many other files and formats may be provided as Pre-mapping

Optimization
part of a standard cell library: Constraint
Definition
• GDS Technology

• Ve r i l o g
Mapping
Post-mapping

• ATPG
Optimization
Report and

• Power Grid Models export

• OA Databases
• Spice Models
• etc.

45
 Syntax
Analysis

Documentation and Datasheets Library

Definition
Elaboration
and Binding

• So, are we just supposed to look through and see Pre-mapping

Optimization
what the vendor decided to provide us with? Constraint
Definition
• Yes! Technology
• However they probably supplied some PDFs describing the library. Mapping
Post-mapping
• And usually there are data sheets with numbers for each corner. Optimization
Report and
export

46 www.vlsi.ce.titech.ac.jp/kunieda/lecture
 Syntax
Analysis

And what about other IPs? Library

Definition
Elaboration
and Binding

• All IPs will be provided as a library, including most of Pre-mapping

Optimization
the views a standard cell library will have. Constraint
Definition
Technology
Mapping

• These are required for integration of the macros in the Post-mapping

Optimization
standard design flow (simulation, synthesis, P&R, Report and
export
verification, etc.)

• Memories (SRAMs) are a special case, as they usually

come with a memory compiler that generates the
particular memory cut the designer requires.

47
Thank You

VLSI Design, EE, FAST-NU, Islamabad 52