AT93C57

Features
• Low-voltage and Standard-voltage Operation

– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• User-selectable Internal Organization
– 1K: 128 x 8 or 64 x 16
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
•
•
3-wire Serial Interface
2 MHz Clock Rate (5V) Compatibility
3-wire Serial
• Self-timed Write Cycle (10 ms max)
• High Reliability EEPROMs
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years 1K (128 x 8 or 64 x 16)
– ESD Protection: >4000V
• Automotive Grade and Extended Temperature Devices Available 2K (256 x 8 or 128 x 16)
• 8-pin PDIP, 8-lead JEDEC and EIAJ SOIC, and 8-lead TSSOP Packages
4K (512 x 8 or 256 x 16)
Description
The AT93C46/56/57/66 provides 1024/2048/4096 bits of serial electrically erasable
programmable read only memory (EEPROM) organized as 64/128/256 words of 16 AT93C46
bits each, when the ORG pin is connected to VCC and 128/256/512 words of 8 bits
each when it is tied to ground. The device is optimized for use in many industrial and
commercial applications where low power and low voltage operations are essential.
AT93C56
The AT93C46/56/57/66 is available in space saving 8-pin PDIP and 8-lead JEDEC
and EIAJ SOIC packages.
AT93C57
(continued)
Pin Configurations AT93C66

8-pin PDIP
Pin Name Function
CS Chip Select
CS 1 8 VCC
SK Serial Data Clock SK 2 7 DC
DI Serial Data Input DI 3 6 ORG
DO 4 5 GND
DO Serial Data Output
GND Ground
VCC Power Supply 8-lead SOIC
ORG Internal Organization
CS 1 8 VCC
DC Don’t Connect
SK 2 7 DC
DI 3 6 ORG
8-lead SOIC DO 4 5 GND
Rotated (R)
(1K JEDEC Only)
8-lead TSSOP
DC 1 8 ORG
CS 1 8 VCC
VCC 2 7 GND
SK 2 7 DC
CS 3 6 DO
DI 3 6 ORG
SK 4 5 DI Rev. 0172L–10/99
DO 4 5 GND
1
The AT93C46/56/57/66 is enabled through the Chip Select ERASE/WRITE ENABLE state. When CS is brought “high”
pin (CS), and accessed via a 3-wire serial interface consist- following the initiation of a WRITE cycle, the DO pin out-
ing of Data Input (DI), Data Output (DO), and Shift Clock puts the READY/BUSY status of the part.
(SK). Upon receiving a READ instruction at DI, the address The AT93C46 is available in 4.5V to 5.5V, 2.7V to 5.5V,
is decoded and the data is clocked out serially on the data 2.5V to 5.5V, and 1.8V to 5.5V versions. The
output pin DO. The WRITE cycle is completely self-timed AT93C56/57/66 is available in 4.5V to 5.5V, 2.7V to 5.5V,
and no separate ERASE cycle is required before WRITE. and 2.5V to 5.5V versions.
The WRITE cycle is only enabled when the part is in the
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground .....................................-1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage .......................................... 6.25V conditions for extended periods may affect
device reliability
DC Output Current........................................................ 5.0 mA
Block Diagram
Note: 1. When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 organiza-
tion is selected. If the ORG pin is left unconnected, then an internal pullup device (of approximately 1 MΩ) will select the x
16 organization. This feature is not available on 1.8V devices.
2 AT93C46/56/57/66
AT93C46/56/57/66
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol Test Conditions Max Units Conditions
COUT Output Capacitance (DO) 5 pF VOUT = 0V
CIN Input Capacitance (CS, SK, DI) 5 pF VIN = 0V
Note: 1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V,
TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Unit
VCC1 Supply Voltage 1.8 5.5 V
READ at 1.0 MHz 0.5 2.0 mA
ICC Supply Current VCC = 5.0V
WRITE at 1.0 MHz 0.5 2.0 mA
ISB1 Standby Current VCC = 1.8V CS = 0V 0 0.1 µA
ISB2 Standby Current VCC = 2.5V CS = 0V 6.0 10.0 µA
ISB3 Standby Current VCC = 2.7V CS = 0V 6.0 10.0 µA
ISB4 Standby Current VCC = 5.0V CS = 0V 17 30 µA
IIL Input Leakage VIN = 0V to VCC 0.1 1.0 µA
IOL Output Leakage VIN = 0V to VCC 0.1 1.0 µA
VIL1 (1) Input Low Voltage -0.6 0.8
4.5V ≤ VCC ≤ 5.5V V
VIH1(1) Input High Voltage 2.0 VCC + 1
VIL2 (1) Input Low Voltage -0.6 VCC x 0.3
1.8V ≤ VCC ≤ 2.7V V
VIH2(1) Input High Voltage VCC x 0.7 VCC + 1
VOL1 Output Low Voltage IOL = 2.1 mA 0.4 V

4.5V ≤ VCC ≤ 5.5V
VOH1 Output High Voltage IOH = -0.4 mA 2.4 V
VOL2 Output Low Voltage IOL = 0.15 mA 0.2 V

1.8V ≤ VCC ≤ 2.7V
VOH2 Output High Voltage IOH = -100 µA VCC - 0.2 V
Note: 1. VIL min and VIH max are reference only and are not tested.
3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
4.5V ≤ VCC ≤ 5.5V 0 2

SK Clock 2.7V ≤ VCC ≤ 5.5V 0 1
fSK MHz
Frequency 2.5V ≤ VCC ≤ 5.5V 0 0.5
1.8V ≤ VCC ≤ 5.5V 0 0.25
4.5V ≤ VCC ≤ 5.5V 250

2.7V ≤ VCC ≤ 5.5V 250
tSKH SK High Time ns
2.5V ≤ VCC ≤ 5.5V 500
1.8V ≤ VCC ≤ 5.5V 1000
4.5V ≤ VCC ≤ 5.5V 250

2.7V ≤ VCC ≤ 5.5V 250
tSKL SK Low Time ns
2.5V ≤ VCC ≤ 5.5V 500
1.8V ≤ VCC ≤ 5.5V 1000
4.5V ≤ VCC ≤ 5.5V 250

Minimum CS 2.7V ≤ VCC ≤ 5.5V 250
tCS ns
Low Time 2.5V ≤ VCC ≤ 5.5V 500
1.8V ≤ VCC ≤ 5.5V 1000
4.5V ≤ VCC ≤ 5.5V 50

2.7V ≤ VCC ≤ 5.5V 50
tCSS CS Setup Time Relative to SK ns
2.5V ≤ VCC ≤ 5.5V 100
1.8V ≤ VCC ≤ 5.5V 200
4.5V ≤ VCC ≤ 5.5V 100

2.7V ≤ VCC ≤ 5.5V 100
tDIS DI Setup Time Relative to SK ns
2.5V ≤ VCC ≤ 5.5V 200
1.8V ≤ VCC ≤ 5.5V 400
tCSH CS Hold Time Relative to SK 0 ns
4.5V ≤ VCC ≤ 5.5V 100

2.7V ≤ VCC ≤ 5.5V 100
tDIH DI Hold Time Relative to SK ns
2.5V ≤ VCC ≤ 5.5V 200
1.8V ≤ VCC ≤ 5.5V 400
4.5V ≤ VCC ≤ 5.5V 250

2.7V ≤ VCC ≤ 5.5V 250
tPD1 Output Delay to ‘1’ AC Test ns
2.5V ≤ VCC ≤ 5.5V 500
1.8V ≤ VCC ≤ 5.5V 1000
4.5V ≤ VCC ≤ 5.5V 250

2.7V ≤ VCC ≤ 5.5V 250
tPD0 Output Delay to ‘0’ AC Test ns
2.5V ≤ VCC ≤ 5.5V 500
1.8V ≤ VCC ≤ 5.5V 1000
4.5V ≤ VCC ≤ 5.5V 250

2.7V ≤ VCC ≤ 5.5V 250
tSV CS to Status Valid AC Test ns
2.5V ≤ VCC ≤ 5.5V 500
1.8V ≤ VCC ≤ 5.5V 1000
4.5V ≤ VCC ≤ 5.5V 100

CS to DO in High AC Test 2.7V ≤ VCC ≤ 5.5V 100
tDF ns
Impedance CS = VIL 2.5V ≤ VCC ≤ 5.5V 200
1.8V ≤ VCC ≤ 5.5V 400
0.1 10 ms
tWP Write Cycle Time
4.5V ≤ VCC ≤ 5.5V 1 ms
(1)
Endurance 5.0V, 25°C, Page Mode 1M Write Cycles
Note: 1. This parameter is characterized and is not 100% tested.
4 AT93C46/56/57/66
AT93C46/56/57/66
Instruction Set for the AT93C46

Address Data
Op
Instruction SB Code x8 x 16 x8 x 16 Comments
READ 1 10 A6 - A0 A5 - A0 Reads data stored in memory, at
specified address.
EWEN 1 00 11XXXXX 11XXXX Write enable must precede all
programming modes.
ERASE 1 11 A6 - A0 A5 - A0 Erase memory location An - A0.
WRITE 1 01 A6 - A0 A5 - A0 D7 - D0 D15 - D0 Writes memory location An - A0.
ERAL 1 00 10XXXXX 10XXXX Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V.
WRAL 1 00 01XXXXX 01XXXX D7 - D0 D15 - D0 Writes all memory locations. Valid
EWDS 1 00 00XXXXX 00XXXX Disables all programming instructions.
Instruction Set for the AT93C57

Address Data
Op
specified address.
EWEN 1 00 11XXXXXX 11XXXXX Write enable must precede all
programming modes.
ERASE 1 11 A7 - A0 A6 - A0 Erase memory location An - A0.
ERAL 1 00 10XXXXXX 10XXXXX Erases all memory locations. Valid
WRAL 1 00 01XXXXXX 01XXXXX D7 - D0 D15 - D0 Writes all memory locations. Valid
EWDS 1 00 00XXXXXX 00XXXXX Disables all programming instructions.
5
Instruction Set for the AT93C56 and AT93C66
Address Data
Op
specified address.
EWEN 1 00 11XXXXXXX 11XXXXXX Write enable must precede all
programming modes.
ERASE 1 11 A8 - A0 A7 - A0 Erases memory location An - A0.
ERAL 1 00 10XXXXXXX 10XXXXXX Erases all memory locations. Valid
WRAL 1 00 01XXXXXXX 01XXXXXX D7 - D0 D15 - D0 Writes all memory locations. Valid
when VCC = 5.0V ± 10% and Disable
Register cleared.
EWDS 1 00 00XXXXXXX 00XXXXXX Disables all programming instructions.
Functional Description
The AT93C46/56/57/66 is accessed via a simple and ver- WRITE (WRITE): The Write (WRITE) instruction contains
satile 3-wire serial communication interface. Device opera- the 8 or 16 bits of data to be written into the specified mem-
tion is controlled by seven instructions issued by the host ory location. The self-timed programming cycle, tWP, starts
processor. A valid instruction starts with a rising edge after the last bit of data is received at serial data input pin
of CS and consists of a Start Bit (logic “1”) followed by the DI. The DO pin outputs the READY/BUSY status of the part
appropriate Op Code and the desired memory Address if CS is brought high after being kept low for a minimum of
location. 250 ns (tCS). A logic “0” at DO indicates that programming
READ (READ): The Read (READ) instruction contains is still in progress. A logic “1” indicates that the memory
the Address code for the memory location to be read. After location at the specified address has been written with the
the instruction and address are decoded, data from the data pattern contained in the instruction and the part is
selected memory location is available at the serial output ready for further instructions. A READY/BUSY status can-
pin DO. Output data changes are synchronized with the ris- not be obtained if the CS is brought high after the end
ing edges of serial clock SK. It should be noted that a of the self-timed programming cycle, tWP.
dummy bit (logic “0”) precedes the 8- or 16-bit data output ERASE ALL (ERAL): The Erase All (ERAL) instruction
string. programs every bit in the memory array to the logic “1”
ERASE/WRITE (EWEN): To assure data integrity, the state and is primarily used for testing purposes. The DO pin
part automatically goes into the Erase/Write Disable outputs the READY/BUSY status of the part if CS is
(EWDS) state when power is first applied. An Erase/Write brought high after being kept low for a minimum of 250 ns
Enable (EWEN) instruction must be executed first before (tCS). The ERAL instruction is valid only at V CC = 5.0V ±
any programming instructions can be carried out. Please 10%.
note that once in the Erase/Write Enable state, program- WRITE ALL (WRAL): The Write All (WRAL) instruction
ming remains enabled until an Erase/Write Disable programs all memory locations with the data patterns spec-
(EWDS) instruction is executed or VCC power is removed ified in the instruction. The DO pin outputs the
from the part. READY/BUSY status of the part if CS is brought high after
ERASE (ERASE): The Erase (ERASE) instruction pro- being kept low for a minimum of 250 ns (tCS). The WRAL
grams all bits in the specified memory location to the logical instruction is valid only at VCC = 5.0V ± 10%.
“1” state. The self-timed erase cycle starts once the ERASE/WRITE DISABLE (EWDS): To protect against
ERASE instruction and address are decoded. The DO pin accidental data disturb, the Erase/Write Disable (EWDS)
outputs the READY/BUSY status of the part if CS is instruction disables all programming modes and should be
brought high after being kept low for a minimum of 250 ns executed after all programming operations. The operation
(tCS). A logic “1” at pin DO indicates that the selected mem- of the READ instruction is independent of both the EWEN
ory location has been erased, and the part is ready for and EWDS instructions and can be executed at any time.
another instruction.
6 AT93C46/56/57/66
AT93C46/56/57/66
Timing Diagrams
Synchronous Data Timing
Note: 1. This is the minimum SK period.
Organization Key for Timing Diagrams

AT93C46 (1K) AT93C56 (2K) AT93C57 (2K) AT93C66 (4K)
I/O x8 x 16 x8 x 16 x8 x 16 x8 x 16
(1) (2)
AN A6 A5 A8 A7 A7 A6 A8 A7
DN D7 D15 D7 D15 D7 D15 D7 D15
Note: 1. A8 is a DON’T CARE value, but the extra clock is required.
2. A7 is a DON’T CARE value, but the extra clock is required.
READ Timing
7
EWEN Timing
tCS
CS
SK
DI 1 0 0 1 1 ...
EWDS Timing
tCS
CS
SK
DI 1 0 0 0 0 ...
WRITE Timing
tCS
CS
SK
DI 1 0 1 AN ... A0 DN ... D0
HIGH IMPEDANCE
DO BUSY READY
tWP
WRAL Timing(1)
tCS
CS
SK
DI 1 0 0 0 1 ... DN ... D0
BUSY
HIGH IMPEDANCE
DO READY
tWP
Note: 1. Valid only at VCC = 4.5V to 5.5V.
8 AT93C46/56/57/66
AT93C46/56/57/66
ERASE Timing
tCS
CS CHECK STANDBY
STATUS
SK
DI 1 1 1 AN AN-1 AN-2 ... A0
tSV tDF
HIGH IMPEDANCE BUSY HIGH IMPEDANCE

DO
READY
tWP
TERAL Timing(1)
tCS
CS CHECK STANDBY
STATUS
SK
DI 1 0 0 1 0
tSV tDF
HIGH IMPEDANCE BUSY HIGH IMPEDANCE
DO
READY
tWP
Note: 1. Valid only at VCC = 4.5V to 5.5V.
9
AT93C46 Ordering Information
tWP (max) ICC (max) ISB (max) fMAX
(ms) (µA) (µA) (kHz) Ordering Code Package Operation Range
10 2000 30.0 2000 AT93C46-10PC 8P3 Commercial
AT93C46-10SC 8S1 (0°C to 70°C)
AT93C46R-10SC 8S1
AT93C46W-10SC 8S2
AT93C46-10TC 8T
30.0 2000 AT93C46-10PI 8P3 Industrial
AT93C46-10SI 8S1 (-40°C to 85°C)
AT93C46R-10SI 8S1
AT93C46W-10SI 8S2
AT93C46-10TI 8T
10 800 10.0 1000 AT93C46-10PC-2.7 8P3 Commercial
AT93C46-10SC-2.7 8S1 (0°C to 70°C)
AT93C46R-10SC-2.7 8S1
AT93C46W-10SC-2.7 8S2
AT93C46-10TC-2.7 8T
10.0 1000 AT93C46-10PI-2.7 8P3 Industrial
AT93C46-10SI-2.7 8S1 (-40°C to 85°C)
AT93C46R-10SI-2.7 8S1
AT93C46W-10SI-2.7 8S2
AT93C46-10TI-2.7 8T
Package Type
8P3 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8T 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
Blank Standard Operation (4.5V to 5.5V)
-2.7 Low Voltage (2.7V to 5.5V)
R Rotated Pinout
10 AT93C46/56/57/66
AT93C46/56/57/66
AT93C46 Ordering Information (Continued)

AT93C46-10SC-2.5 8S1 (0°C to 70°C)
AT93C46R-10SC-2.5 8S1
AT93C46W-10SC-2.5 8S2
AT93C46-10TC-2.5 8T
AT93C46-10SI-2.5 8S1 (-40°C to 85°C)
AT93C46R-10SI-2.5 8S1
AT93C46W-10SI-2.5 8S2
AT93C46-10TI-2.5 8T
AT93C46-10SC-1.8 8S1 (0°C to 70°C)
AT93C46R-10SC-1.8 8S1
AT93C46W-10SC-1.8 8S2
AT93C46-10TC-1.8 8T
AT93C46-10SI-1.8 8S1 (-40°C to 85°C)
AT93C46R-10SI-1.8 8S1
AT93C46W-10SI-1.8 8S2
AT93C46-10TI-1.8 8T
Package Type
Options
R Rotated Pinout
11
AT93C56-10SC 8S1 (0°C to 70°C)
AT93C56W-10SC 8S2
AT93C56-10SI 8S1 (-40°C to 85°C)
AT93C56W-10SI 8S2
AT93C56-10SC-2.7 8S1 (0°C to 70°C)
AT93C56W-10SC-2.7 8S2
AT93C56-10SI-2.7 8S1 (-40°C to 85°C)
AT93C56W-10SI-2.7 8S2
AT93C56-10SC-2.5 8S1 (0°C to 70°C)
AT93C56W-10SC-2.5 8S2
AT93C56-10SI-2.5 8S1 (-40°C to 85°C)
AT93C56W-10SI-2.5 8S2
Package Type
Options
12 AT93C46/56/57/66
AT93C46/56/57/66

AT93C57-10SC 8S1 (0°C to 70°C)
AT93C57W-10SC 8S2
AT93C57-10SI 8S1 (-40°C to 85°C)
AT93C57W-10SI 8S2
AT93C57-10SC-2.7 8S1 (0°C to 70°C)
AT93C57W-10SC-2.7 8S2
AT93C57-10SI-2.7 8S1 (-40°C to 85°C)
AT93C57W-10SI-2.7 8S2
Package Type
Options
13
AT93C66-10SC 8S1 (0°C to 70°C)
AT93C66W-10SC 8S2
AT93C66-10TC 8T
AT93C66-10SI 8S1 (-40°C to 85°C)
AT93C66W-10SI 8S2
AT93C66-10TI 8T
AT93C66-10SC-2.7 8S1 (0°C to 70°C)
AT93C66W-10SC-2.7 8S2
AT93C66-10TC-2.7 8T
AT93C66-10SI-2.7 8S1 (-40°C to 85°C)
AT93C66W-10SI-2.7 8S2
AT93C66-10TI-2.7 8T
AT93C66-10SC-2.5 8S1 (0°C to 70°C)
AT93C66W-10SC-2.5 8S2
AT93C66-10TC-2.5 8T
AT93C66-10SI-2.5 8S1 (-40°C to 85°C)
AT93C66W-10SI-2.5 8S2
AT93C66-10TI-2.5 8T
Package Type
Options
14 AT93C46/56/57/66
AT93C46/56/57/66
Packaging Information
8P3, 8-pin, 0.300" Wide, 8S1, 8-lead, 0.150" Wide,
Plastic Dual Inline Package (PDIP) Plastic Gull Wing Small Outline (JEDEC SOIC)
Dimensions in Inches and (Millimeters) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 BA
.400 (10.16) .020 (.508)

.355 (9.02) .013 (.330)
PIN
1
.280 (7.11) .157 (3.99) .244 (6.20)

.240 (6.10) .150 (3.81) .228 (5.79)
PIN 1
.037 (.940)
.300 (7.62) REF .027 (.690)
.050 (1.27) BSC
.210 (5.33) MAX .100 (2.54) BSC

SEATING .196 (4.98)
PLANE .189 (4.80)
.068 (1.73)
.015 (.380) MIN
.150 (3.81) .053 (1.35)
.115 (2.92) .022 (.559)
.070 (1.78) .014 (.356)
.045 (1.14)
.010 (.254)
.325 (8.26) .004 (.102)
.300 (7.62)
0 0
15
REF REF .010 (.254)
.012 (.305) 8
.008 (.203)
.007 (.203)
.430 (10.9) MAX
.050 (1.27)
.016 (.406)
8S2, 8-lead, 0.200" Wide, 8T, 8-lead, 0.170" Wide,

Plastic Gull Wing Small Outline (EIAJ SOIC) Thin Shrink Small Outline Package (TSSOP)
Dimensions in Inches and (Millimeters) Dimensions in Millimeters and (Inches)*
.020 (.508) PIN 1

.012 (.305)
6.50 (.256)
.213 (5.41) .330 (8.38) 6.25 (.246)
.205 (5.21) .300 (7.62)
PIN 1
.050 (1.27) BSC 0.30 (.012)

0.19 (.008)
.212 (5.38)
3.10 (.122)
.203 (5.16)
1.05 (.041) 2.90 (.114)
.080 (2.03) 1.20 (.047) MAX
0.80 (.033)
.070 (1.78)
.65 (.026) BSC 0.15 (.006)

.013 (.330) 0.05 (.002)
.004 (.102)
4.5 (.177)
0 4.3 (.169)
REF .010 (.254)
8 0.20 (.008)
.007 (.178)
0.09 (.004)
.035 (.889)
0.75 (.030)
.020 (.508) 0 REF 0.45 (.018)
8
*Controlling dimension: millimeters
15
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© Atmel Corporation 1999.

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Features

• Low-voltage and Standard-voltage Operation

Pin Configurations AT93C66

VOL1 Output Low Voltage IOL = 2.1 mA 0.4 V

VOL2 Output Low Voltage IOL = 0.15 mA 0.2 V

4.5V ≤ VCC ≤ 5.5V 0 2

4.5V ≤ VCC ≤ 5.5V 250

4.5V ≤ VCC ≤ 5.5V 250

4.5V ≤ VCC ≤ 5.5V 250

4.5V ≤ VCC ≤ 5.5V 50

4.5V ≤ VCC ≤ 5.5V 100

tCSH CS Hold Time Relative to SK 0 ns

4.5V ≤ VCC ≤ 5.5V 100

4.5V ≤ VCC ≤ 5.5V 250

4.5V ≤ VCC ≤ 5.5V 250

4.5V ≤ VCC ≤ 5.5V 250

4.5V ≤ VCC ≤ 5.5V 100

Instruction Set for the AT93C46

Instruction Set for the AT93C57

Note: 1. This is the minimum SK period.

Organization Key for Timing Diagrams

Note: 1. Valid only at VCC = 4.5V to 5.5V.

DI 1 1 1 AN AN-1 AN-2 ... A0

HIGH IMPEDANCE BUSY HIGH IMPEDANCE

Note: 1. Valid only at VCC = 4.5V to 5.5V.

AT93C46 Ordering Information (Continued)

AT93C57 Ordering Information

.400 (10.16) .020 (.508)

.280 (7.11) .157 (3.99) .244 (6.20)

.210 (5.33) MAX .100 (2.54) BSC

8S2, 8-lead, 0.200" Wide, 8T, 8-lead, 0.170" Wide,

.020 (.508) PIN 1

.050 (1.27) BSC 0.30 (.012)

.65 (.026) BSC 0.15 (.006)

*Controlling dimension: millimeters

© Atmel Corporation 1999.

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