Body
Body
Body
Faraday’s law implies that the varying magnetic flux in a coil with N turns will
generate a voltage V at the two ends of the coil. Thus, the basic component of
inductive sensors is a coil which generates a magnetic field in front of the sensor
of the coil and the target decreases and hence the inductance of the coil increases
when the distance between the sensor and the target decreases. The magnetic field
conducting target, the magnetic field emerging from the coil induces an eddy
current in the approaching target surface. The eddy current creates an opposing
magnetic field which is absorbed by the coil according to Ampere’s law. Figure
1.1(b) shows the magnetic field of an eddy current sensor. This phenomenon
results in a decrease of the inductance of the coil. Therefore, we can measure the
inductance of the coil to tell the distance between the coil and the target. The eddy
current inductive sensors are more widely applied in industry since the magnetic
1
field of these sensors penetrates the target only to the level of the orders of skin
depth δ, which is approximately equal to 1 / πfσµ , where µ and σ are the
the electromagnetic field. As a result, the sensing capability will not be restricted
i i
N N
S S
(a) (b)
Figure 1.1 Magnetic field of a inductive sensor sensing (a) a ferromagnetic and (b)
a conductive target.
important role in extracting the inductance variation with regard to changes in the
distance or proximity of the target. The sensitivity of the sensing system can be
highly restricted by the interface circuitry. Bridge circuits and oscillators are the
two most popular interface circuits for inductive proximity sensors [2].
Wheatstone bridge circuits are used due to their high linearity and
2
inductance of the sensing coil, and it keeps its balance value of L1L2/L4 to generate
a zero output voltage until the presence of a nearby conducting target decreases its
inductance to 1-ε. The unbalanced bridge in turn provides an a.c. output voltage
The oscillators are more widely used in industry because of their simplicity
detector circuit. The oscillator circuit can be either a tuned or relaxation oscillator
The inductive coil forms the inductance portion of the LC circuit and carries a
approaching conducting target causes a change in the magnetic field around the
sensor, the impedance of the coil is decreased, and therefore either or both the
frequency and the amplitude of the oscillator signal change. The change of
detector circuit which can be either a Schimitt trigger level detector that generates
readout circuit that provides more accurate distance information between the
sensor and the metal target. Recently, a differential relaxation oscillator has been
proposed [5]. It has the advantages of both the bridge and oscillator circuits and
3
L1L2
Lx = (1-ε)
L4
L1
Lx
AC voltage +
source VAC 2 VACL1 L4 ε
L4
L Vout ~ 2
(L1 + L 2)
-
Figure 1.2 A bridge interface circuit with Lx as the inductance of the sensing coil.
The monolithic integration of the sensing element together with the interface
with the standard silicon circuits. A miniaturized flat-coil inductor has been proven
interface circuits. When the coil is scaled down, however, the inductance
factor [8]. Moreover, the downscaling causes a dramatic increase of the serial
conductor making up the coil, and l and A are respectively the length and cross
section of the coil. From the interface circuits’ point of view, the serial resistance
4
degrade the linearity of the bridge interface circuit because the sensing coil loses its
A two-coil eddy current proximity sensor has been proposed to avoid the
drawbacks of scaling down the sensor system [9]. The two coils build a flat
transformer structure in which one coil carries the periodic excitation signals to
generate the magnetic field and the other acts as a pick-up coil detecting the
magnetic field variation. The separation between the sensor and a metal target is
reflected in the phase shift between the electrical signals in the two coils. From the
a.c. simulation result of this sensing element model, it is found that the sensitivity
of this design is not sensitive to variation in the coils’ series resistance. Therefore,
reading, and ideally this reading is a function of only one parameter (distance or
proximity). However, in the real world, several components are attributed to the
variation of the output reading, and therefore the sensing performance can be
improve the sensitivity of the reading and to get more knowledge of the
environment which we want to sense, several studies [1][2] suggest making use of
the relationships of the many output variables rather than relying solely on the ideal
one-output function of one parameter. In the two-coil sensor design, for a fixed
distance between the sensor and a target plate of a certain material, there is an
operating frequency at which the sensor achieves its maximum sensitivity to target
5
proximity. This frequency is found to be related to the conductivity of the target
material. Therefore, the conductivity of the target and the frequency for the
maximum sensitivity can be regarded as the second input and output of this sensor
system, respectively.
1. extracting both of the two outputs, the operation frequency for the
order to get accurate information about both the proximity and the
resistance, and
the requirement of the input and output stages are also covered.
Chapter three explains how to design the electronic interface circuitry. Two
simulation.
6
Chapter four quantifies the characteristics of the sensor and the interface
Finally, chapter five summarizes the thesis and addresses additional work to
7
Chapter 2: Two-Coil Inductive Sensing Element
that are caused by the increase in the coil resistance when the coil is scaled down.
are an exciting coil, a pick-up coil, and a target plate. In this chapter, we will
discuss how to build a simple SPICE model out of these three components, and in
the following chapters, this model will be used to design and simulate the interface
electrical circuit.
In this section, only planar rectangular spiral coils are considered. This is
because the planar structure can be easily fabricated by the standard CMOS
process and because the rectangular spiral coil has been shown to achieve the
The total coil resistance is calculated by summing the resistance of each segment
making up the coil. For a high frequency current, however, Eq. (2-1) will no
longer be valid due to the skin depth effect by which the current traveling in the
8
conductor is confined in a very thin layer, the thickness of which is approximately
proportional to the inverse of the square root of the frequency. In this sensor
model, the operating frequency range will be shown to be within the range low
enough for designers to keep the d.c. formula. Also, the skin depth phenomena has
permeability µ, is
2 li AMD µ
Li = C li ln − 125
. + + T , (2-2)
GMD
li 4
where C is 0.0002 nH µm − 1 and T is the frequency correction factor ( T = 1 for
microwave frequencies). GMD and AMD are the geometric mean distance and
follows,
GMD 1 1 1 1
ln( )= - + 4 + 6 + 8 + ........ (2-3)
d d 2 d d d
12 60 168 360
w w w w
AMD = w + t, (2-4)
where d is the distance between conductor filaments of the coil. The mutual
inductance between segments i and another segment with the same length a
9
Mi = C •li •Qi , (2-5)
equation
li li 2
0.5 2 0.5
GMD GMD
Qi = ln + 1 + − 1 + + . (2-6)
GMD
GMD li li
It can be shown that the mutual inductance between two segments is inversely
segment j
d
segment m
P m q
Figure 2.1 Calculation of the mutual inductance between two coil segments with
different lengths [10].
So far, it is supposed that each element of the coil has the same length,
however, this statement is not valid for most cases. For two segments with
different lengths j and m as shown in Figure 2.1, the mutual inductance, Mj,m,
10
where each M term on the right hand side is calculated by Eq.(2-5).
where the first term is the sum of the self inductance of each segment in the coil,
and the second and third terms represent the sums of all the positive and negative
inductance is positive when the current flow in two parallel segments is in the same
direction or negative when the current flow is in opposite directions. Take a simple
rectangular spiral coil shown in Figure 2.2 with a current I flowing in the direction
where each Li and Mi,j are calculated by Eq. (2-2) through Eq. (2-7).
1 5
3
11
2.1.3 Calculation of the Mutual Inductance between a Coil and a Conducting
Plate
current flowing in the coil excites the eddy current on the plate. The eddy current
then produces a magnetic field normal to the plate, which creates the magnetic flux
linkage in the coil. To reduce the complexity of solving the Poisson’s equation of
this system directly, the method of images is applied instead. By assuming that the
plate has zero resistivity and is infinite in extent, the conducting plate can be
replaced by the coil’s image being placed below the plate surface at a distance
equal to the distance between the coil and the plate surface, as drawn in Figure 2.3.
The current in the image coil flows in the opposite direction but at the same
magnitude as that in the coil. This can be done by imaging the signal source driving
the coil to the plate. Therefore, the calculation of the mutual inductance between
the coil and the plate placed at a distance d from each other is simplified by the
from each other. This calculation can be evaluated by Eq. (2.3) through Eq. (2.7) if
12
B1 B1
I1 I1
d d
Inductor Inductor
I2
B2
Figure 2.3 Illustration of the image theory for a system consisting of a sensing coil
and a metal target plate.
The two-coil inductive sensor model is based on the derivation of the one-
coil inductive sensor model. So the one-coil modeling algorithm will be discussed
target plate is present by the transformer circuit model in Figure 2.4. Vi, Ii, Ri, and
Li are the images of V1, I1, R1, and L1, respectively, so that Vi = V1, Ii = I1, Ri =
R1, and Li = L1. Besides, Mi is the mutual inductance between the coil and its
13
Leff_i = L1 - Mi. (2-10)
The minus sign is a result of the image current traveling in the opposite direction to
I1 Ii
R1 Ri
V1 L1 Mi Vi
Li
Figure 2.4 One-coil inductive sensor model based on the image theory.
A simplified circuit model [9] is drawn in Figure 2.5. In this case, the image
voltage source is removed, and Is, Ls and Rs are no longer necessarily equal to I1,
L1 and R1. The Kirchoff’s current loop equations for this circuit are
Solving the two equations above, we obtain the effective impedance of the sensing
circuit,
V1 ω 2 Ms 2 Rs ω 2 Ms 2 Ls
zeff_s = = R1 + + jω L1 − . (2-13)
I1 Rs 2 + ω 2 Ls 2 Rs 2 + ω 2 Ls 2
The effective impedance can be divided into the imaginary and the real parts as the
14
When the frequency ω is much higher than Rs / Ls, the dependence on frequency of
Reff_s and Leff_s is eliminated and thus Eq. (2-14) and Eq. (2-15) become
Ms 2
Leff_s’= L1 - (2-16)
Ls
Ms 2 Rs
Reff_s’= R1 + . (2-17)
Ls 2
In the following sections, it can be verified that ω is almost always much higher
than Rs / Ls for the two-coil sensor so that Eq. (2-16) and Eq. (2-17) can always be
applied.
I1 Is
R1
V1 L1 Ms Ls
Rs
To force the simplified model in Fig. 2.5 to match the image theory model
in Figure 2.4, the effective inductance in two cases must be equal, which implies
Ms 2
Mi = . (2-18)
Ls
This is done by equating Eq. (2-10) and Eq. (2-17).
the image theory model the parameters of which are known already. According to
Eq. (2-18), it is found that a relation between Ms and Ls is needed to draw these
15
two parameters from the known Mi. This relation can be acquired as described in
the following.
in two ways as shown in Figure 2.6(a) and (b). Figure 2.6(c) and (d) are the
equivalent circuits of the two connection schemes with the method of images
applied. The resistance of the coil is neglected to simplify the problem and the
image voltage source is removed as the simplified model in Figure 2.5. The
effective inductances seen by the voltage source in the two cases are
Mg 2
Leff_a = Lc - (2-19)
Lg
If the grounded plane conductor has infinite conductivity, then the effective
inductance seen by the voltage source in the two cases should be the same, which
which implies Ls = Ms in the simplified model in Figure (2.5). Moreover, Eq. (2-
18) becomes
Mi = Ms = Ls. (2-23)
16
i1 i2
sensing coil
V segment
i1
V Lc Lg
i2
Mg
Grounded
plane conductor
(a) (c)
i1
sensing coil V
segment
i1
V i1
Lg Lc
Grounded Mg
plane conductor
(b) (d)
Figure 2.6 Two connection schemes for extracting the sensor model parameters.
For the simplified model in Figure 2.5, R1 and L1 can be obtained by the
methods indicated in Section 2.1.1 and 2.1.2, and Ls and Ms are equal to Mi which
can be calculated by the technique described in Section 2.1.3. The only parameter
for microstrip transmission lines is utilized to calculate Rs. Figure 2.7 shows the
ground plane at the distance of h. The distance k is a measure of how long the
magnetic fields spread before reaching the ground plane. With k = 3h + w/2, the
impedance per unit length of the microstrip obtained using this quasi-static model
17
microstrip over a ground plane can be replaced by a microstrip over a conductor
noted that the plane resistance depends on both the distance between the
microstrip and the ground plane and the conductivity of the ground plane.
microstrip
ground plane k
Figure 2.7 Using the model of a microstrip over a ground plane to calculate the
resistance of the target plate [11].
The two-coil inductive proximity sensor has two identical coils, one of
which provides the excitation magnetic signals while the other picks up the
Their individual impedance and the mutual inductance between them (Rprimary,
Rsecondary, Lprimary, Lsecondary and M12 as shown in Figure 2.8) can be calculated using
the method discussed in Section 2.1.1 and 2.1.2. The target plate is modeled based
on the simplified one-coil model in Figure 2.5, where Lplate is equal to Mplate based
on Eq. (2.23). The values of Mplate and Rplate are obtained by the image theory and
the quasi-static model mentioned in Section 2.1.3 and 2.2.1, respectively. Cg and
18
Rg are added as the gap resistor and capacitor between the sensor and the plate
because SPICE does not allow the existence of a floating circuit. A very large and
a very small value are assigned to Rg and Cg, respectively, in order to eliminate
their effects.
target plate
Rplate
Lplate
Cg Rg Rg Cg
Rprimary M plate Mplate Rsecondary
R1
Interface
V Lprimary M12 Lsecondary circuit
Figure 2.8 The schematic SPICE model of the two-coil sensor with a target plate.
For a certain two-coil sensor design, all the parameters are fixed for any
situation except Rplate and Mplate (also Lplate, which has the same value as Mplate).
Mplate relies on the distance between the target plate and the sensor while Rplate is
related to both the proximity and the conductivity of the target plate. Thus, it can
be affirmed that there is a unique solution set of proximity and conductivity of the
target for a given set of Rplate and Mplate. Also, this can explain another reason why
the simplified model (Figure 2.5) is preferable to the image model (Figure 2.4). By
using the image model, we can only extract the information about the distance of a
target, which is ideally a perfect conductor, through the single electronic variable
Mi. However, the effects of the nonideal conductivity of the target material are
19
seen as a reason for the degradation of sensing capability. With the simplified
model, the two physical parameters, distance and conductivity of the target, can
both be transferred to the magnitudes of the two electronic components, Rplate and
Mplate.
B
D
Figure 2.9 The mask design of a planar rectangular spiral two-coil sensor, where A
and B are the two terminals of one coil while C and D are the two
terminals of the other.
20
2.3 TWO-COIL INDUCTIVE SENSOR SIMULATION
Ref. [9] has proven that the simulation of the two-coil model is matched
quite well to the measurement results of a prototype sensor built on a copper PCB
to the two-coil SPICE model in Figure 2.8. The driving circuit of the HP4194A
contains an ideal voltage source and a series resistor, and its detecting circuit is a
load resistor. The PSpice schematic circuit is shown in Figure 2.10. The
coupling factor between the two inductors L1 and L2 is defined as M12 / L1 L2 ,
Figure 2.10 The PSpice schematic circuit of the two-coil sensor together with the
equivalent circuit of the HP4194 Gain/Phase Analyzer.
21
The variation of Rplate and Lplate is reflected in the phase difference between
the electric signals in the pick-up coil and the driving coil. This can be described
more precisely as the phase difference between node voltage Voutput and Vsource in
Figure 2.10. Despite the fact that the gain of Voutput / Vsource also depends on Rplate
and Lplate, the gain is generally very low ( below -50dB for frequencies lower than
show the influence of the variation of Lplate, Rplate, and Rprimary on the phase versus
frequency curves, respectively. It is observed that Rprimary has little effect on the
phase shift in the frequency range concerned so that this design is independent of
the resistance variation that arises from the process deviation. There exists a
minimum phase shift for each concave curve in the frequency range from 10KHz
to 1MHz. At the frequency at which the minimum phase shift occurs, the
sensitivity of the phase shift to Lplate achieves its maximum ( Figure 2.11 ( a ) ).
The value of the minimum phase shift decreases when Lplate increases for a fixed
Rplate, while the frequency at which the phase shift achieves its minimum increases
when Rplate increases for a fixed Lplate (Figure 2.11( b )). It is desirable to determine
the values of Lplate and Rplate by the minimum phase shift Φ and the frequency f at
which the minimum phase shift occurs. However, this can be done only if the
system has a unique solution set of Lplate and Rplate for a measurement result of Φ
22
90
15nH
80 25nH
35nH
70
45nH
60 55nH
50
40
30
1E+3 10E+3 100E+3 1E+6 10E+6
Frequency(Hz)
Figure 2.11( a ) Simulation of the phase shift between Voutput and Vsource with
different values of Lplate. ( Rplate = 0.01Ω and Rprimary = 0.36Ω )
90
0.01Ω
85 0.03Ω
0.07Ω
80
0.1Ω
75
70
65
60
1E+3 10E+3 100E+3 1E+6 10E+6
Frequency(Hz)
Figure 2.11( b ) Simulation of the phase shift between Voutput and Vsource with
different values of Rplate. ( Rprimary = 0.36Ω and Lplate = 35nH )
23
90
0 .1 Ω
85 1Ω
10Ω
80
100Ω
75 1 κΩ
70
65
60
1E+3 10E+3 100E+3 1E+6 10E+6
Frequency (Hz)
Figure 2.11( c ) Simulation of the phase shift between Voutput and Vsource with
different values of Rprimary. (Rplate = 0.01Ω and Lplate = 35nH)
understand the input and output requirements of the sensing element. For the
output requirement, it is obvious that the stage following the sensing element
should have a high input impedance to reduce its effect on the sensing
performance. For the input circuit, we notice that the driving source of an
parallel resistance of 50Ω . Since the input impedance of the sensing element is
much lower than 50Ω in the relevant frequency range, the parallel resistance of
50Ω can be neglected and therefore the required driving component turns out to
be an ideal current source. Moreover, the phase shift between Voutput and Vsource in
24
Figure 2.11 is equivalent to the phase shift between Voutput and the ideal current
controlled current source, the current output of which is in phase with the
source, the simulation results of the phase shift between Voutput and Vsource (Figure
2.12) are matched to those in Figure 2.11. The phase shift of Φ (Voutput) -
The first part of Eq.(2-25), which is shown in Figure 2.13( a ) and is equivalent to
the phase shift between the source and the output voltages if an ideal voltage
shaped curve and decreases dramatically at higher frequencies. This explains why
an ideal voltage source is not desired. The second part of Eq. (2-25), which is
equivalent to the phase of the input impedance, increases from zero to 90§ as the
frequency goes up (Figure 2.13( b )), as a result of that the input impedance of the
Figure 2.11( a ). Besides, both the first and the second parts of Eq. (2-25) vary
25
Vin Voutput
+
Two-coil
Vsource I = AV source Sensing Rload
- Element
Figure 2.12 Circuit for simulating the sensing element with a ideal voltage-
controlled current source as the driving component. ( Rload = 50Ω )
90
15nH
80
25nH
70
35nH
60
45nH
50
55nH
40
30
20
10
0
1E+3 10E+3 100E+3 1E+6 10E+6
Frequency(Hz)
Figure 2.13( a ) Simulation of the phase shift between Voutput and Vin in Figure 2.12
with different values of Lplate for an ideal voltage controlled current
source as the driving circuit. (Rplate = 0.01Ω and Rprimary = 0.36Ω )
26
90
15nH
80
25nH
70
35nH
60
45nH
50
55nH
40
30
20
10
0
1E+3 1E+4 1E+5 1E+6 1E+7 1E+8
Frequency (Hz)
Figure 2.13( b ) Simulation of the phase shift between Vin and Vsource in Figure 2.12
with different values of Lplate for an ideal voltage controlled current
source as the driving circuit. (Rplate = 0.01Ω and Rprimary = 0.36Ω )
27
Chapter 3: The Interface Circuit Design
driving circuit, a phase detector, and a feedback loop to adjust the operation
frequency to f, the frequency at which the minimum phase shift occurs. Two
simulation with the third-level 0.8µm CMOS process models available through the
MOSIS services ( Table 3.1 ). The 0.8µm process is chosen because its 5Volt
operating voltage is a reasonable magnitude for the analog integrated circuit design
28
The performance of each circuit component is characterized by its linearity
error or accuracy. The linearity error is defined as the maximum deviation of the
actual transfer function from the best fitted straight line that describes the output
signal, while the accuracy is specified as the ratio of the maximum error of the
controlled current source which creates enough power to excite the eddy current
untuned operating frequencies. Their outputs are typically square waves and
of the VCO output in this case. Several studies have proposed methods to design a
which can produce a frequency range of two decades (10KHz ~ 1MHz) and can be
fabricated by the standard CMOS process, the circuit shown in Figure 3.1 is
chosen.
The VCO is based on the operation of the astable multivibrator. M1, M2,
M5 and M6 form a current mirror whose current value corresponds to the input
comparator and sources or sinks current of the magnitude of that in the current
29
mirror. Due to the basic relationship between the voltage and current on a
derived as
1 IC1 IC1
f= = = , (3-1)
2 ∆t 2C1∆V 2C1(VTRP + − VTRP − )
where VTRP+ and VTRP- are the positive and negative trip points of the comparator
with hysteresis, respectively, and the capacitor charging current, IC1 is ideally
equal to i1. Because C1, VTRP+ and VTRP- are fixed for a certain design, the
Vdd = 2.5V
M1 M2
Vin
i2
i1 Comparator with hysteresis
M3
Vout
-
M4
C1
+
i3
R2
R1
M5 M6
Vss = -2.5V
Figure 3.1 Schematic diagram of a VCO compatible with CMOS technology [16].
30
As the input voltage decreases from Vdd ( = 2.5Volt), M1, M2, M5 and M6
change from the turn-off region to the saturation region and the current in the
current mirror increases from zero amperes. This small current guarantees a two
decade difference between the minimum current and the maximum current. For the
in the current mirror need to be in the saturation region which makes I1, I2 and I3
in Figure 3.1 equivalent to each other via transistor matching. To reduce the
µeffCoxW/L, where µeff is the effective mobility of electrons or holes, Cox is the gate
oxide capacitance per area and W/L is the width-to-length ratio of the gate area.
Also, the β3/β4 ratio must be adjusted to set the trip point of the CMOS inverter at
zero volt. When the input voltage continues to decrease, M1 enters its linear region
and the relation between the frequency output and the voltage input is no longer
square but linear. Referring to Figure 3.2, the output frequency is roughly a linear
function ( with linearity error of 18KHz ) in the input range from -2.5Volt to
proportional to the square of the input voltage for higher input voltage.
For the VCO in Figure 3.1, the gate of either PMOS M1 or NMOS M5 can
be chosen as the input. Since the active loading MOS (M5 in our case) of the input
stage is always in the saturation region, it should be assigned the kind of MOS
gate of PMOS is chosen to be the input node since the channel-length modulation
31
parameter of p-channel devices (λp) is higher than that of n-channel devices (λn) in
During the SPICE simulation, the VCO output signal may not be a periodic
waveform but a d.c. voltage. This problem can be solved by restricting the
maximum time step of the transient analysis to a small number via setting the
Since the phase shift of the two-coil sensor is very sensitive to the
operating frequency, the driving signal needs to have a pure sinusoidal waveform.
The triangle waves generated by the VCO have significant odd harmonic contents
that are undesirable. It is not practical to apply filters to remove them due to the
more commonly used for reducing the harmonic contents of the VCO output.
32
Instead of diode and bipolar shaping networks which require more sophisticated
design and are not appropriate for standard CMOS process, a simple CMOS sine-
and M4 performs the sine-shaping function. The total harmonic distortion (THD),
defined as [17]
THD = 100 ( D2 2 + D 32 + D 4 2 + ......) , (3-2)
where Dk ( k = 2, 3, ..) are the ratios between the amplitude of the kth harmonic
and that of the fundamental in the Fourier series representation of the output
algorithm but providing a THD under 5% and being independent of the VCO
offset voltage, device characteristics and temperature can be built [18]. The
transient simulation results of the sinusoidal VCO are plotted in Figure 3.5.
V dd
M3 M4
Sinusoidal Output
VCO Signal M1 M2
Vbias
Vss
33
12
10
0
10 100 1000
Frequency (KHz)
Figure 3.5 The waveform at the sine-shaper output, VCO output, comparator with
hysteresis output and the current flowing in the VCO capacitor.
The driving circuit for the primary coil requires an ideal voltage-controlled
current source which is also called the transconductance amplifier. The class AB
output amplifier in Figure 3.6 ( a ) was formed utilizing discrete components and
34
was shown to provide enough power to the two-coil sensor by David Lee and
David Onsongs [19]. Since the maximum current the two Darlington BJTs
(NTE245 and NTE246) can provide is 1 Ampere and the load impedance of the
swing much lower than the ±15Volt power supply voltages required for the power
BJTs to generate 1 Ampere. In this case, the two transistors rather than the
V dd Vdd
M1
Vg1 VB1
NTE245
M2
1N5226B + VB2
io
io io
Vin Vin Vin
M3
1N5226B +
VB3
NTE246
M4
Vg2 VB4
Vss Vss
Vss
35
The two most widely used approaches to designing a transconductance
amplifier compatible with CMOS process are a differential stage approach with
Figure 3.6 ( b ). The latter is far simpler than the former; however, its linear
performance depends critically on the matching between the NMOS and the
and p-channel transistors no longer affects the linearity. With identical NMOS
devices, M1 and M3, and identical PMOS devices, M2 and M4, the current flowing
where
βeff = βnβp / ( βn + βp ) 2 , (3-5)
VTN1, VTN3, VTP2, and VTP4 are the threshold voltages of M1, M2, M3 and M4,
Io = IM2 - IM3 = -βeff (Vg1 + Vg2 - ΣVT) Vin + βeff (Vg1 + Vg2 - ΣVT) ∆VT/2, (3-6)
where
ΣVT = VTN3 + VTN3 + VTP2 + VTP4 (3-7)
If four wells are used ( VBS = 0 for each transistor ) and Vg1 = Vg2, then Io has an
ideal linear relation with Vin. However, with a low operation voltage ( ±2.5Volt ),
it is difficult to isolate each well from the substrate. So, the two-well structure is
36
applied here, i.e., VB1 = VB3 = Vss and VB2 = VB4 = Vdd, and thus the body effect
causes a nonlinear effect in Eq. (3-6). The d.c. offset and second-order current
The biasing circuit providing Vg1 and Vg2 can be implemented by either a
resistors of the biasing circuit together with the parasitic capacitors CGD and CGS of
the transistors add high order poles and zeros to the phase shift curve in the
frequency range discussed in Chapter 2. The additional poles and zeros destroy the
concave-shaped curves and are sensitive to the change of the magnitude of the
biasing resistors caused by process variation. On the other hand, the equivalent
resistance of an MOS voltage divider with the parasitic capacitors of its four
transistors can also add a pole, which moves down to the relevant frequency range
when the parasitic capacitors increase as a result of the fact that large area
MOSFETs are used to provide the 500mA output current. A simple way to avoid
adding extra poles or zeros to the phase shift curve is to connect Vg1 and Vg2 to Vdd
2.5Volt and Vg2 = -2.5Volt , the relation, (W/L)p ≅ 5(W/L)n, is obtained for the n-
channel and p-channel devices in the linear transconductance element. Besides, for
the standard CMOS process, the large area transistors can be implemented by
37
configuration or various doping values for different regions [21][22]. This parallel
arrangement would result in an output current with the magnitude of the sum of
one hundred elements in parallel each with W/L of 1180µm/0.8µm for NMOS and
200µm/0.8µm for PMOS leads to a linearity error of 6.7mA for input voltage
within ±0.6Volt and a transconductance of 726mA/Volt. For the a.c. analysis, the
phase of the current output is almost equal to that of the voltage input with a
corresponding to the phase difference between the output signal of the sensing
element and the input signal of the transconductance amplifier. A prototype phase
chosen to perform the amplification function for the small signal in the pick-up coil
because its close-loop frequency response of phase drops only 1§ from 0§ within
38
1MHz. This small amount of the phase drop implies that the phase difference
between the signal at the pick-up coil and the transconductance input
Figure 3.7 Phase detector built by discrete components (Vdd = -Vss = 15Volt).
Figure 3.8 Transient simulation results of the prototype phase detector. From
bottom to top: waveforms at the pick-up coil, the op-amp output, the
first comparator ( U2 in Figure 3.7 ) output, the second comparator
out put ( U3 in Figure 3.7 ), and the XOR output.
39
signal can be taken as the phase difference between the pulses at the outputs of the
two comparators with a maximum error of 1§. The XOR gate then produces the
absolute difference of the pulses at the two comparator outputs. The ratio of
average pulse width over the pulse period of the pulses at the XOR output is
proportional to the phase difference between the two comparator output signals.
Since the XOR gate is a simple digital component, a buffer is needed to provide
enough power to charge the capacitor in the integrator. Finally, the integrator
averages the pulse train and generates a d.c. voltage in its settling time. Figure 3.8
explains the operation of the phase detector by showing the waveforms obtained
Figure 3.6 ( b ) fed by an ideal a.c. voltage signal, Rplate = 0.015Ω , Lplate = 50nH
Relating these factors to the prototype circuit described above, it is clear that,
ideally, the input offset voltage and the resolution of the comparators and the
ripple and the settling time of the integrator should ideally be zero.
prototype except that the op-amp of the first stage is taken away because
3.9. Three inverter pairs are added to increase the gain and the drive capability,
and thus the rise and fall times of the output can be reduced. The first two stages
40
are connected from -2.5Volt to 2.5Volt because a larger power supply is needed to
keep each transistor biased in the saturation region, while the sources of n-channel
transistors of the inverter pairs are connected to the ground since the XOR gate
requires a non-negative pulse train input. For the XOR gate described in the next
paragraph as the load and with one of the inputs connected to the ground, the
input offset voltage and resolution of the comparator are 0.55mV and 0.1mV,
respectively, and the fall time and rise time are within 10ns in the frequency range
VN VP Vout
Vbias
Vss=-2.5V
Two schemes to implement XOR gates are examined. The novel one in
Figure 3.10 ( a ) inhabits a much smaller area than that of the conventional XOR
gate in Figure 3.10 ( b ), however, the input impedance of the two input nodes is
different so that the phase response of frequency for the two comparators is
different. As a result, the phase difference between the two comparator output
signals deviates from the phase difference between the transconductance input and
41
the sensing element output signals. On the other hand, the conventional CMOS
XOR gate has approximately the same input impedance for both inputs, and in this
case, the two comparator outputs will not interfere with each other during a.c.
analysis as they will in the tiny XOR because of the isolation of the high gate
impedance at the XOR inputs. The buffer stage following the XOR gate can be
A
B
A B
A+B
A+B
(a) (b)
Figure 3.10 Schematics of XOR gate: ( a ) Transmission gate XOR (tiny XOR)
[23] ( b ) Conventional XOR.
The peak-to-peak ripple voltage and the settling time of the single-pole
integrator in the prototype circuit are derived as
Vripple ≈T × IR / C1 (3-9)
where T is the period of the operating frequency, C1 and R3 are the capacitor and
the resistor of the integrator as shown in Figure 3.7, respectively, and IR is the
42
integrator, low ripples are required; however, decreasing the ripple increases the
settling time. This trade-off can be minimized by filtering the single-pole integrator
integrator is designed with high ripples but a fast settling time, and the ripples are
then reduced by the high-order low-pass filter. Except for the frequency range
below 30KHz, during which the ripples increase dramatically, this approach results
in a resolution within 0.004% ( with 0.1mVolt of ripple and 2.5Volt full scale
output ) and a settling time of 2ms, compared with 0.4% ( with 60mV of ripple
and 15Volt full scale output) and a settling time of 0.5ms for the single-pole design
Gain/Phase Analyzer. The operating frequency scans from an initial value ( 20KHz,
in our case) and increases by a fixed amount in logarithmic scale at each rising
edge of the clock pulse until the polarity of the slope of the phase response to the
frequency becomes positive. The block diagram and the waveform plotted in
Figure 3.11 and Figure 3.12, respectively, illustrate how this feedback loop
functions.
comes in response to the operating frequency in the previous clock cycle (a clock
cycle means half of the period of Clock1 and Clock2). Two control clocks, Clock1
43
Main Circuit Clock2 OR Reset
Reset
Vinitial
(frequency=20KHz) Sinusoidal Inductance Phase Sample
Reset Transconductance
VCO shaping
amplifier Sensor detector & hold
circuit 1
Clock1OR Reset
1+δ
D (Clock3orReset)and D
Sample
Phase Readout
Frequency
& hold
Voltage Sample to 2
D Level & hold voltage
Translator converter
Clock1
Comparator+
Frequency Readout 1
-
D Clock2
Clock1NORClock2 Clock1ORClock2
Comparator+
2 -
Latch Latch D
Control signalD 2 1
Logic 0
Reset
Figure 3.11 Block diagram of the sensor system with successive feedback loop.
The dashed line indicates the main circuit which will be discussed in
Chapter 4.
47.5
Reset
Clock1
37.5
Clock2
Clock3
27.5
Phas_dec_out
SH1
17.5
SH2
comp1
7.5
comp2
Dcontrol
-2.5
0 2 4 6 8 10
Time (ms)
Figure 3.12 Clock and control signal waveforms (From top to bottom: Reset,
Clock1, Clock2, Clock3, the outputs of phase detector, sample-and-
hold circuit 1, sample-and-hold circuit 2, comparator 1, and
comparator 2, and the control signal D as illustrated in Figure 3.11.)
44
and Clock2, of the same period but with 180§ phase difference are needed for
sampling the phase detector output because the transit time will result in
and the phase detector if only one clock is used here. The voltage outputs of the
two sample-and-hold circuits, V(φn) and V(φn-1), one of which corresponds to the
present operating frequency fn and the other to the previous one fn-1, are compared
by the following comparators. If V(φn) - V(φn-1) is negative, i.e., the slope of the
frequency response of phase shift is negative, the ‘D’ control signal in Figure 3.11
will be given the value of logic high. On the other hand, if V(φ(n)) - V(φ(n-1)) is
positive, i.e., the slope of the frequency response of phase shift becomes positive,
the ‘D’ control signal will change to logic low and keep logic low during all the
following clock cycles. The ‘D’ control signal plays the role of determining
whether the operating frequency fn+1 of the next cycle should continue to increase
During Clock3, which rises right after each pulse of Clock1 and Clock2 with a
period determined by the settling time of the phase detector and the FVC, the
sample-and-hold circuit in the sub-loop samples the FVC output. Then the sampled
voltage increases by timing 1 + δif the ‘D’ control signal is logic high or keeps the
same value if the ‘D’ control signal is logic low. A voltage level translator follows
to translate the voltage level from the FVC scale (0 to 2.5Volt) to the VCO scale
(-2.5Volt to 2.5Volt) and feeds the new voltage value to the VCO, which then
45
Note that the frequency of Clock1 and Clock2 is half of that of Clock3 as a
result and the three clocks do not overlap at any time. The pulse width of Clock3
should be short enough to keep the sampled FVC output unchanged with the
variation of the VCO input through the feedback loop during the sampling time.
proportional to the input frequency. The FVC circuit is based on the configuration
[17][24][25], as shown in Figure 3.13. The waveforms are drawn in Figure 3.14.
The input comparator ( comparator A ) converts the sinusoidal waves at the sine-
cross the zero threshold at each falling edge of the input pulse for any frequency
concerned is generated through the coupling capacitor C1 and triggers the flip-flop
built with two NAND gates. The one-shot output of the flip-flop, in turn, closes
the switch S1 and thus pulls a constant current Iref out of the capacitor Cos until Cos
is charged to the reference voltage Vref. The flip-flop then changes its holding value
and waits for the next trigger. During this period, Cos is discharged to zero through
the switch S2, which is closed by the flip-flop output. The duration Tos of the
current pulse flowing through Cos does not depend on the input frequency but is
Also, the voltage output Vo is obtained by integrating the one-shot pulse train,
which has the duration of Tos and the frequency of the sine-shaper output signal.
46
Vdd
Vdd
Vdd
R2
sine shaper
output + C1
Co mpa rato rA -
- Co mpa ra to r1
R1 + One-shot R
Vo
Vs
s
Vs
s
Vdd
VRef One-shot
+
Compa ra to r2
-
Co s Vs s
S2 S
1
IRe f
V ss
Figure 3.14 Transient simulation results of the FVC. (Form top to bottom: the
FVC input, the comparator A output, the comparator 1 input and
output, and the one-shot.)
47
Thus,
Tos
Vo = Vdd × = Vdd ×Tos × f , (3-12)
T
where T and f are the period and frequency of the sine-shaper output signal,
respectively, and the one-shot signal has the pulse height of Vdd, which is 2.5Volt
in this case. All the comparators and the integrator are constructed by the same
Tos has to be no longer than the period of the maximum frequency but long
enough to achieve good resolution, i.e., high dVo/df. By setting Cos = 50pF , Vref = -
0.5Volt, and Iref = 28µA, Tos has the value of 0.886µs and dVo/df is 2.2mV/KHz.
Moreover, the simulation of this FVC results in a linearity error below 2mV.
Figure 3.15. The capacitor CH is charged to the input voltage when switch φ is
closed and holds the voltage when φ is open. Since the pulse width of the three
clocks controlling the sample-and-hold circuits is 10µs and their periods are 2ms
or 4ms, the capacitor CH has to be small and the switch’s driving capability has to
be high in order to attain a charging time within 10µs. On the other hand, CH has
enough to hold the charges for a comparably longer time of approximately 2ms or
4ms. Due to this trade-off, the value of the capacitor and the area of the switch
should be selected carefully to satisfy both the requirements. Besides, the gate
current of the positive input of the op amp should be eliminated to reduce the
48
To insure the stability of the feedback loop, the op amp should be
common mode range ( CMR ) of the op amp should include the whole possible
output range of the phase detector and the FVC. The CMR is defined as the range
of common-mode values of the input signals that the op amp continuously senses
and amplifies the difference between the two input signals with the same gain [16].
-
A1 Vout
Vin +
φ
CH
always positive. If a PMOS alone or a CMOS pair is applied instead, the voltage
difference between the body, which is connected to the most positive voltage,
2.5Volt, and the drain/source of the PMOS may not be high enough to maintain
the inverse-biased p-n junction between them, and thus the undesirable leakage
current will become very high. Dummy transistors are used to couple with each
single-transistor switch for the purpose of avoiding the clock feedthrough effect.
All the switches of sample-and-hold circuits are closed during ‘Reset’ to precharge
the capacitors gradually, otherwise the capacitors may not be able to follow the
sharp voltage increase during the first clock. For the following clock cycles, the
49
changes at the outputs of the phase detector and FVC are comparably small due to
the small frequency step, so the sample-and-hold circuits can accurately follow the
changes.
By carefully designing this system with the 0.8µm process parameters, the
sample-and-hold circuit decays by only 1mV during a holding time of 4ms with the
accuracy of 1% in the input range from -2.5Volt to 2.3 Volt. Input signals above
2.3Volt exceed the CMR of the op amp, so that the accuracy is degraded to 5%.
For the same reason, the voltage level translator has the linearity error of 10mV for
the whole input range except for input signals above 2.05Volt for which the
Instead of the fixed frequency steps in logarithmic scale for the successive
feedback scheme, the iterative feedback loop generates frequency steps that are
determined by the outputs of the phase detector and FVC during the last two clock
cycles. Besides, the frequency step can be either positive or negative as opposed to
The block diagram of this design is drawn in Figure 3.16. Both the phase
detector and FVC have two sample-and-hold circuits that sample their output
voltages in turn by applying the same clock signals, Clock1 and Clock2, as those
used to control the switches in the successive feedback loop. Thus the phase
information Φ n-1 and Φ n-2 and the frequencies fn-1 and fn-2 for the last two clock
cycles can be stored in the form of voltage. An analog computer takes the outputs
50
of the four sample-and-hold circuits as its input signals and Clock1 and Clock2 as
its control signals and calculates the frequency step ∆ fn for the next clock cycle.
At the end of Clock1 or Clock2, the summation of ∆ fn and the last frequency fn-1 is
the same as Clock3 in the successive feedback design, the sample-and-hold circuit
5 samples the voltage containing the frequency information for the next clock cycle
Clock1OR Reset1
Reset1
Sample
1.3Volt & hold
(20KHz) Reset2 5
1.05Volt
(50KHz)
Figure 3.16 Block diagram of the sensor system with iterative feedback loop.
proportional to the last frequency fn-1 and increases when the difference between Φ n-
51
with the last phase shift Φ n-1. This will be explained in Chapter 4. Thus, the transfer
where A, B,... and l are unknown coefficients and constants. The polarity of ∆ fn is
determined by that of Φ n-2 - Φ n-1 and that of fn-1 - fn-2. And for the same Φ n-1, Φ n-2, fn-1
and fn-2, the magnitude of positive ∆ fn should be larger than that for negative ∆ fn
because the approximately symmetric concave curve of the phase shift is drawn in
The coefficients and constants of the transfer function are obtained by trial-
and-error on the spreadsheet until the lowest number of the average clock cycles
required for ∆ fn to converge and for the frequency variation to be below the
(3-14)
where
∆fno = 0.0028 × ( fn − 1 + 10) × Φ n − 2 − Φ n − 1 × (Φ n − 1 + 35)
× IF (Φ n − 2 − Φ n − 1 > 0, 1 , -1)
× IF ( fn − 1 − fn − 2 > 0, 1 , -1 ), (3-15)
analog computer is shown in Figure 3.17. Φ n-1 - Φ n-2 is calculated by the difference
ensures that the input impedance seen by each input is ideally infinite, and its
52
accuracy is 0.1% in the phase shift range concerned ( 25§ to 85§). The square
converters, which will be described in the next section. Note that all the frequency
and phase terms in Eq. (3-14) and Eq. (3-15) have to be converted to voltages
through the transfer functions of the FVC and the phase detector to propagate in
the voltage-based analog computer. And the output ∆ f in Figure 3.18 is an analog
voltage signal corresponding to the frequency step through the VCO transfer
function. As a result, the linearity of the transfer function of the FVC, VCO and
phase detector will have a serious influence on the accuracy of the analog
computer.
(1meg)AND(dF0)
(1meg)AND(dF0)
Clock1
dF0
Clock2 dF0
dF
dF
Clock1
-1/1.5 1.99V
SH2_out
Clock2
Vφ(n-1) Vx_2 × Vy_2
-1 -1 1/2.45 -1/2.45
SH1_out
1meg
Vy_2 Multifunction
Clock1 2.5V Converter
∆f
Vx_2 2
SH3_out 16.2mV 1/2.5
Clock2 Vy Multifunction
Vf(n-1) Converter sqrt (Vx)× VY
SH4_out -6
Vx 1
Clock2
Difference 6
Amplifier
Clock1
Vφ(n-1) -Vφ(n-2)
dP
dP
53
V1 -
+ R4
R3
R2 -
R1 + +
R2 R3
R4 R2
R4 Vo= (1+2
R3 R 1 )(V2-V1)
-
-
V2 +
transistors ( MM5262 ) with very low threshold voltage to satisfy the low power
supply requirement are added to the integrated circuit simulated. Knowing that the
negative input node of each op amp can be taken as virtual ground, we get
Vx Vy Vx Vo
Ix = , Iy = , Ix = , Io = . (3-16)
Rx Ry Rx Ro
By setting all the resistors of the same magnitude ( 10KΩ ), the ratio between any
two currents is equal to the one that exists between their corresponding voltages.
The exponential I-V characteristic of the bipolar transistors gives the following
relations,
V 1 − VAy _ out
Io = Is exp (3-17)
VT
− VAy _ out
Iy = Is exp . (3-18)
VT
Dividing Eq. (3-17) by Eq. (3-18) and rearranging the terms, we obtain
Io
V 1 = VT ln . (3-19)
Iy
54
By the same method, V3 can be written as
Iz
V 3 = VT ln . (3-20)
Ix
With R1 = R2 = 50Ω in Figure 3.19 ( b ), V3 = 0.5 V1, so that Eq. (3-19) and Eq.
Ry Iy Io Ro
Qy VAy_ou t Qo V1 V2 V3
Vy Vo
- -
Ay Ao
+ + R1
R2
V1
Ix Rx (b)
Vx
Rz Iz
Qz Qx
Vy
- - V1 V2 V3
Az Ax V2
+ +
V3
(a) (c)
Figure 3.20 and 3.21 show the accuracy of the circuit in computing the square root
and in the multiplication modes, respectively. The accuracy can be better than 1%
55
if the input signals are converted to 1Volt full scale before being fed to the
multifunction converter.
9
8
7
5
4
3
2
0
0 0.5 1 1.5 2 2.5
Vz ( Volt )
1x102
Vy=0.05V
1
1x10 Vy=0.5V
0 Vy=1V
1x10
-1
1x10
-2
1x10
-3
1x10
-4
1x10
-5
1x10
0 0.5 1 1.5 2 2.5
Vz ( Volt )
56
During the SPICE simulation, stability problems can occur in the iterative
feedback circuit even though each op amp employed is compensated properly. The
use of large bypass capacitors with one end connected to the negative inputs of the
op amps Az and Ay in Figure 3.19 ( a ) and the other connected to ground can
57
Chapter 4: Characteristics of the Sensor and the Interface Circuits
In this chapter, we will describe the performance of the sensor and the
interface circuits by referring to the SPICE simulation results. The sensitivity of the
sensing element with an ideal voltage-controlled current source as the input will be
quantified at first, and then the resolution of the main circuit in Figure 3.11 with an
input of an ideal voltage source will be determined. Finally, the successive and
desirable that the change of an output signal is caused by only one measurand so
that the output readout can be converted to a physical quantity easily and
accurately. The two-coil sensor system that we are interested in has two output
signals, the minimum phase shift and the frequency at which the minimum phase
shift occurs, and two measurands, resistance and inductance ( Rplate and Lplate) of
the target plate, as indicated in Chapter 2. The a.c. analysis is applied to the circuit
parameters relate to the measurands. The simulation results are given in Figure 4.1
and Figure 4.2. It is observed that the minimum phase shift is independent of the
resistance of the target plate. This means that if a pair of electrical output signals is
measured, a unique pair of Rplate and Lplate measurands can be determined. The
average sensitivity of the minimum phase shift to the target plate inductance is 1.14
degree/nH with a linearity of 8 degrees. The linearity is not so ideal, but in this
58
case, this phenomenon will not have any significant effect on the sensing
80
0.03Ω
70
0.05Ω
60 0.07Ω
50 0.09 Ω
40 0.1Ω
30
10 15 20 25 30 35 40 45 50 55
Lplate (nH)
Figure 4.1 The minimum phase shift vs. the target plate inductance for diverse
fixed values of the target plate resistance. The input stage is an ideal
voltage-controlled current source.
1000
10nH
900
15nH
800
20nH
700
25nH
600 30nH
500 35nH
400 40nH
300 45nH
200 50nH
100 55nH
0
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Rplate (Ohm)
Figure 4.2 The frequency at the minimum phase shift vs. the target plate resistance
for diverse fixed values of the target plate inductance. The input stage
is an ideal voltage controlled current source.
59
For a specific Lplate, which is extracted from the minimum phase shift
readout via Figure 4.1, Rplate can be derived from the frequency at which the
minimum phase shift occurs by referring to Figure 4.2. The sensitivity of the
frequency at which the minimum phase shift occurs to Rplate ranges from 69.6 to
174 KHz /0.01Ω , and the linearity is within 700Hz for each fixed value of Lplate.
measurand that can cause a change in the output signal [12]. According to this
the resolution of the practical sensing system before any feedback is involved, the
main circuit shown in Figure 3.11 is simulated through the a.c. analysis. The result
is given in Figure 4.3. Due to the fact that the output impedance of the
transconductance amplifier is not infinite, the minimum phase shift changes with
the target plate resistance for a fixed target plate inductance and this change can be
as high as 0.8 degree. Because the magnitude of this change is not random but
modifying the minimum phase shift at the output Φ to Φ ′through the following
equation,
f − fo
Φ ' = Φ + A × + ∆Φ ′, (4-1)
k
where f is the frequency readout at which the minimum phase shift occurs and
60
the coefficients and constant are listed in Table 4.1. The variation of the minimum
phase shift due to the change of Rplate for a fixed Lplate is thus below 0.03 degree as
listed in the ‘ Φ ′error ’ in Table 4.1. The resolution of Lplate is also shown in the
60 0.07Ω
50 0.09 Ω
40 0.1Ω
30
10 15 20 25 30 35 40 45 50 55
Lplate (nH)
Figure 4.3 The simulation results of the main circuit: the minimum phase shift vs.
the target plate inductance for diverse fixed target plate resistance.
i Φ (degree) k (KHz/Ω) A(degree/Ω) fo (KHz) ∆Φ ’(degree) Φ ’ error (degree) Lplate Resolution (nH)_
2 ≥82 214 0.209 181 0.193 0.011 0.02
3 79~82 140 0.137 125 0.13 0.02 0.03
4 76~79 106 0.103 99 0.099 0.01 0.01
5 72~76 88 0.08 84 0.082 0.03 0.04
6 67~72 78 0.709 75.5 0.07 0.005 0.005
7 62~67 73 0.0626 71 0.124 0.01 0.009
8 56~62 71 0.057 70 0.057 0.01 0.007
9 49~56 73 0.0538 72 0.055 0.002 0.001
10 37~49 81 0.0535 80 0.054 0.003 0.001
11 ≤37 109 0.0616 107 0.061 0.002 0.001
Table 4.1 Adjustment parameters for the minimum phase sift readout of the main
circuit. A is the slope of the minimum phase shift vs. Rplate for each
Lplate of i×5nH, k is the slope in Figure 4.2 for each Lplate of i×5nH, fo
is the frequency at which the minimum phase shift happens for each
Lplate of i×5nH and Rplate=0.01Ω , and ∆Φ ′is the fitting constant. Φ ′
error is the magnitude of the maximum variation of Φ ′caused by the
change in Rplate for each fixed Lplate of i×5nH. Lplate resolution is
derived from dividingΦ ′error by the differential of the curve in
Figure 4.1 at each Lplate of i×5nH.
61
So far, it is supposed that the transconductance amplifier is a linear device
so that the small signal model used here is valid. However, the input signal of the
providing a large current at the output and enhancing the power efficiency. With
this large signal of 0.2Volt, the nonlinear effect of the transconductance amplifier
must be taken into account. The method used to evaluate the degradation of
resolution caused by the nonlinear effect is illustrated in Figure 4.4. With -0.2Volt
and +0.2Volt as the input offset voltage, the a.c. performance deviates from the
expected performance with the ideal input offset voltage of 0V. The magnitudes of
the deviation, which depend on the values of Rplate and Lplate and can be taken as
the minimum detectable changes in the phase ( ∆Φ ) and the minimum effective
changes in the frequency ( ∆f ), respectively, are shown in Table 4.2 as well as the
resolution of Rplate and Lplate if only the nonlinear effect is considered. Three values
of Rplate are chosen to test three different frequency ranges, and for each Rplate, two
values of Lplate, one of which corresponds to the sharpest phase response ( low Φ )
and the other relates to the smoothest one ( high Φ ), are applied. We observed
that the resolution degrades with higher Rplate and lower Lplate, i.e., higher
Volt, otherwise there will be a d.c. current flowing through the primary coil, the
62
85.5 Voffset=-0.2V
Voffset=0V
84.5 Voffset=0.2V
83.5
82.5
∆f
81.5
∆Φ
80.5
5 6
1x10 1x10
Frequency ( Hz )
Table 4.2 Minimum detectable changes in phase shift (∆Φ ) and minimum effective
changes in frequency (∆f) of the main circuit due to nonlinear effects
of the transconductance amplifier. The resolutions of Lplate (∆Lplate)
and Rplate (∆Rplate) are then derived from dividing ∆Φ and ∆f by the
differential of the curve in Figure 4.1 and k at the specified Lplate and
Rplate, respectively. Coefficient δis calculated by Eq. (4-2).
63
result, the variation of the coil resistance will change the d.c. biasing condition of
the transconductance amplifier and thus cause deviation in the a.c. performance.
The phase detector and the FVC do not influence the a.c. performance, but
the ripples at the d.c. output of the integrator restrict the resolution. The amplitude
of the ripples is 0.1mV, which can be converted to 0.0073§ and 45Hz via the
Summing up the effects drawn by the three sources causing the degradation
of the resolution, the finite output impedance and the nonlinear effect of the
transconductance amplifier, and the ripple at the integrator output, it is evident that
the resolution of the main circuit is dominated by the nonlinear effect of the
transconductance amplifier.
In Section 3.3, the coefficient which determines the frequency step, δ, was
not quantified. Now, since the minimum effective changes of the frequency have
been obtained by the simulation of the main circuit, δcan be given in Table 4.2 by
applying
∆f
δ= , (4-2)
f
where ∆f is as listed in Table 4.2 and f is the frequency at which the minimum
phase shift occurs for the specified Lplate and Rplate. It is observed that the smoother
the phase response to frequency is, the larger δis. Since the smoother phase
response to frequency corresponds to the longer distance between the sensor and
64
the metal target, it is clear that there is a tradeoff between the resolution of the
detection for the shorter distance and the maximum detectable proximity if a fixed
δvalue is chosen.
Φ of Sensor a.c.
with Ideal 43.388§ 78.321§ 30.453§ 81.691§ 43.388§ 70.255§ analysis
Input Stage
(Section 4.1)
Φ of Main a.c.
Circuit†† 43.388§ 78.321§ 30.453§ 81.68§ 43.389§ 70.257§ analysis
(Section 4.2)
Accuracy of Φ
of Successive 0.73% -1.5% 1.0% * 2.6% * transient
Feedback analysis
Scheme
Accuracy of Φ transient
of Iterative -0.79% -5.6% 0.30% 1.8% 0.89% -3.6% analysis
Feedback
Scheme
Resolution of
Lplate with 0.06 0.1 0.04 0.1 0.07 0.1 transient
Iterative analysis
Feedback
Scheme (nH)†
Table 4.3 Comparison of the accuracy of phase readouts of the successive and
iterative feedback schemes, where 85§ is taken as the full-scale
output signal. Φ is the minimum phase readout. * The circuit could
not sense a change in the polarity of the slope of the phase response
to the frequency in the scanning frequency range. †A refined VCO
with the level one model applied is used here. ††The phase readings
shown have been converted to Φ ′by Eq. ( 4-1 ).
Letting δbe fixed to 0.025, the desired δvalue for Lplate = 50nH and Rplate
= 0.01Ω , in the circuit shown in Figure 3.11, the successive feedback circuit is
simulated for the six conditions given in Table 4.2 through transient analysis. Table
4.3 and Table 4.4 list the accuracy of the phase and frequency outputs. Due to the
65
nonlinear characteristic of the VCO and the voltage level translator, the average
effective magnitudes of δare 0.025, 0.05 and 0.075 in the three frequency ranges
concerned, respectively, and are very close to the desirable values of δfor lower Φ
in Table 4.2. Therefore, the accuracy for lower Φ is within 2% while the change of
the polarity of the slope of the phase response to the frequency may never be
Table 4.4 Comparison of the accuracy of the frequency readouts of the successive
and iterative feedback schemes, where 1MHz is taken as the full-scale
output signal. f is the frequency readout. * The circuit could not
sense a change in the polarity of the slope of the phase response to
the frequency in the scanning frequency range. †A refined VCO with
the level one model applied is used here.
66
4.3.2 Performance of the Iterative Feedback
tradeoff described in the previous section. Eq. (3-14) and Eq. (3-15) are thus
applied to determine the frequency steps. The accuracy of the iterative feedback
circuit is shown in Table 4.3 and Table 4.4 to compare with that of the successive
feedback scheme. Due to the 1mV decay at the outputs of the sample-and-hold
circuits during a clock cycle, there is a ±0.5mV variation at each phase readout,
which is 0.037§ after being converted by the transfer function of the phase
detector. This is the reason why the operation frequency still varies after
convergence is achieved. The frequency variations observed are listed in Table 4.4
and are generally lower than the minimum effective frequency steps in Table 4.1,
so this phenomena can be ignored. But the ±0.5mV variation at the phase readings
and generating a generally lower error compared to the successive scheme. But the
accuracy in the frequency output is still unsatisfactory for higher Φ because the
circuit converges at a much lower frequency than the desired value. Since the
phase response to the frequency is quite flat for higher Φ , the accuracy of the
phase reading does not reflect this phenomenon. One of the possible factors
contributing to this problem is the high THD of the sinusoidal signal at the output
phase detector to be sensitive not only to the phase shift but also to the operating
67
frequency. Hence, a decrease in the phase shift due to an increase in the operating
though a good sine-shaping circuit can be built by using the 0.8µm CMOS model,
the serious channel length modulation effect of the model limits the performance of
the VCO. Referring to the VCO configuration illustrated in Figure 3.1, the channel
length modulation effect destroys the equivalence among i1, i2 and i3 and also
makes the sourcing and sinking currents of the VCO capacitor, i2 and i3, vary with
the output voltage ( Vout ). In the time domain, the varying current results in a
nonlinear increase or decrease of the output voltage, while the unequal sourcing
are reflected in the form of higher order harmonics in the Fourier series
representation of the output waveform of the sine-shaping circuit, which are then
amplified by the transformer with a gain higher than that for the fundamental
harmonic.
amplitude of the desired signals at the secondary coil is so low (several millivolts)
that a significant error can be generated by the offset voltage of the comparator in
the phase detector. Thus an amplifier should to be added between the secondary
coil and the comparator, while another amplifier of the same design should also be
put before the other comparator in the phase detector to avoid any phase error
68
amplifiers are added in the phase detector, the accuracy of the frequency and the
phase can be improved to be below 8% and 0.6%, respectively, for all the high Φ
conditions specified in Table 4.3 and Table 4.4. The resolution of the refined
interface circuitry is also listed in the tables and is approximately of the same order
as that shown in Table 4.2. Therefore, it can be concluded that the nonlinear
The iterative feedback scheme is also superior to the successive one with
respect to sensor response time. The total number of clock cycles needed for the
the frequency output and can be as high as fifty, compared with that of the iterative
feedback scheme which has an average of fifteen and does not depend on the
frequency output.
Although the a.c. analysis of the two-coil sensing element has been shown
lose sensing capability for coil resistance higher than 1Ω when the transient
analysis is performed in the interface circuit. This is a result of the output voltage
swing of the transconductance amplifier being higher than the range in which the
linear transfer function can be held if the coil resistance increases above 1Ω and the
output current is still kept higher than 200mA to excite the eddy current in the
target plate. For the higher coil resistance, say 200Ω , the reason for the loss of
sensitivity is simply that the output voltage swing exceeds the power supply
voltage. Therefore, we have shown that the circuit discussed is immune to process
69
deviations, which cause a resistance variation of several tens of percentage points,
but the circuit would require some redesign if it were to be used with a scaled
70
Chapter 5: Summary and Conclusion
An interface circuit for the two-coil proximity sensor has been designed
and simulated using the 0.8µm CMOS model available through the MOSIS
service. Except for several bipolar transistors, which can be fabricated on the same
chip if a BiCMOS process is available, the whole circuit with the sensing element
signal driving the primary coil is generated by an on-chip VCO and conditioned by
a transconductance amplifier. For the output stage, a phase detector and a FVC
extract the phase shift and the operation frequency, respectively, in the forms of
d.c. voltage. Feedback schemes are applied to make the operation frequency
converge to the value at which the minimum phase shift happens. The two
measurands, Lplate and Rplate, can thus be determined by the two d.c. voltage output
readings representing the minimum phase shift and the operation frequency at
which the minimum phase shift occurs, respectively. It is observed that the
undesirable higher order harmonics in the Fourier series representation of the input
signal so that the sinusoidal output signal is seriously distorted. The configuration
bandpass filter has to be added to the output stage to reduce this problem.
71
Another main factor degrading the resolution and accuracy of the circuitry
Section 4.2. Further investigations are necessary to avoid the tradeoff between the
linearity of the transfer function and the power efficiency of the transconductance
amplifier.
iterative feedback loop is to convert the analog signals at the outputs of the FVC
and the phase detector into the digital domain by means of analog-to-digital
the nonlinear effect and offset voltage of the analog computing components, such
eliminated.
the target can also be identified by using multiple output readings. Further work
needs to be done to quantify the relationship between the two measurands, Lplate
and Rplate, and the two physical parameters, distance and conductivity of the target
plate.
fabricated with a mask design similar to the one described in Figure 2.9 [27]. The
removed to eliminate the effect drawn by the parasitic capacitance and the resistive
72
loss. The coil resistance and inductance are 5.5Ω and 10nH, respectively. Based on
dimension of the coils, the resistance of the target plate ( Rplate ) is scaled up and
the inductance of the target plate ( Lplate ) is scaled down proportionally to the
scale factor, if the target distance is scaled down as well. The coupling factor
between the two coils remains the same [8]. The a.c. analysis of the sensor model
in Figure 2.10 with the parameters specified above shows that the characteristic of
the phase response to the frequency remains approximately the same except that
the operation frequency range increases by the inverse square of the scale factor.
Therefore, the interface circuit can be applied to the micromachining sensor if the
phase shift between the output current and input voltage. Also, the operation
frequency range of the FVC and the VCO needs to be enhanced by the inverse
73
Bibliography
[3] D. Dixon and R. Hoehener, Inductive Prox: An Old Sensor with New
Wrinkles, Chilton’s Instruments and Control Systems, vol. 62, n 10, pp.
55-58, 1989.
74
[11] E. Tuncer and D. P. Neikirk, Highly Accurate Quasi-Static Modeling of
Microstrip Lines Over Lossy Substrates, IEEE Microwave and Guided
Wave Letters, vol. 2, no. 10, pp.409-411, 1992.
[12] Lj. Ristic and R. Roop, Sensor Technology and Devices, Norwood, MA:
Artech House, 1994.
[16] P. Allen and D. Holberg, CMOS Analog Circuit Design, New York, NY:
Oxford University Press, Inc. , 1987.
[18] H. Eaton and J. Lesho, A Low Voltage, Low Power, BiCMOS, Audio-
Frequency Voltage Controlled Oscillator with Sinusoidal Output, IEEE
Symposium in Circuits and Systems, vol. 2, pp. 1463-1466, 1993.
75
[23] N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A
systems perspective, Addison-Wesley Publishing Company, 1992.
[24] R. M. Stitt and R. Burt, Get F-V Converters to Settle Fast Without Ripple,
Electronic Design, pp. 73-80, 1991.
76
Vita
Huei-Ching You was born in Taichung, Taiwan on June 24, 1974, the
daughter of Lih Liu and Hon-Fai Yau. After completing her work at National
Normal University Affiliated High school, Taipei, Taiwan, in 1992, she entered
National Tsing Hua University, Hsin Chu, Taiwan. In June, 1996, she received the
University. She entered the Graduate School at The University of Texas at Austin
in August, 1996.
Permanent address: 2F, No. 17, Aly. 5, Lane 171, Kun-Yang St.
Nang-Kung, Taipei 115
Taiwan
77