ATtiny212 14 412 14 Automotive DS40002229A
ATtiny212 14 412 14 Automotive DS40002229A
ATtiny212 14 412 14 Automotive DS40002229A
Automotive
tinyAVR® 1-series
Introduction
The ATtiny212/214/412/414 Automotive are members of the tinyAVR® 1-series of microcontrollers, using the AVR®
processor with hardware multiplier, running at up to 16 MHz, with 2/4 KB Flash, 128/256 bytes of SRAM, and 64/128
bytes of EEPROM in a 8- and 14-pin package. The tinyAVR® 1-series uses the latest technologies with a flexible,
low-power architecture, including Event System, accurate analog features, and Core Independent Peripherals (CIPs).
Features
• CPU
– AVR® CPU
– Running at up to 16 MHz
– Single-cycle I/O access
– Two-level interrupt controller
– Two-cycle hardware multiplier
• Memories
– 2/4 KB In-system self-programmable Flash memory
– 64/128 bytes EEPROM
– 128/256 bytes SRAM
– Write/erase endurance:
• Flash 10,000 cycles
• EEPROM 100,000 cycles
– Data retention:
• 40 years at 55°C
• System
– Power-on Reset (POR)
– Brown-out Detector (BOD)
– Clock options:
• 16 MHz low-power internal RC oscillator
• 32.768 kHz Ultra Low-Power (ULP) internal RC oscillator
• 32.768 kHz external crystal oscillator
• External clock input
– Single-Pin Unified Program and Debug Interface (UPDI)
– Three sleep modes:
• Idle with all peripherals running for immediate wake-up
• Standby
– Configurable operation of selected peripherals
• Power-Down with full data retention
• Peripherals
– One 16-bit Timer/Counter type A (TCA) with a dedicated period register and three compare channels
– One 16-bit Timer/Counter type B (TCB) with input capture
Table of Contents
Introduction.....................................................................................................................................................1
Features......................................................................................................................................................... 1
3. Block Diagram.......................................................................................................................................12
4. Pinout.................................................................................................................................................... 13
4.1. 8-Pin SOIC................................................................................................................................. 13
4.2. 14-Pin SOIC............................................................................................................................... 13
7. Memories.............................................................................................................................................. 16
7.1. Overview.................................................................................................................................... 16
7.2. Memory Map.............................................................................................................................. 17
7.3. In-System Reprogrammable Flash Program Memory................................................................17
7.4. SRAM Data Memory.................................................................................................................. 18
7.5. EEPROM Data Memory............................................................................................................. 18
7.6. User Row....................................................................................................................................18
7.7. Signature Bytes.......................................................................................................................... 18
7.8. I/O Memory.................................................................................................................................19
7.9. Memory Section Access from CPU and UPDI on Locked Device..............................................21
7.10. Configuration and User Fuses (FUSE).......................................................................................22
9. AVR® CPU............................................................................................................................................ 43
9.1. Features..................................................................................................................................... 43
9.2. Overview.................................................................................................................................... 43
9.3. Architecture................................................................................................................................ 43
9.4. Arithmetic Logic Unit (ALU)........................................................................................................ 45
9.5. Functional Description................................................................................................................45
9.6. Register Summary......................................................................................................................50
9.7. Register Description................................................................................................................... 50
36.13. TWI...........................................................................................................................................498
36.14. VREF........................................................................................................................................501
36.15. ADC..........................................................................................................................................502
36.16. DAC..........................................................................................................................................504
36.17. AC............................................................................................................................................ 505
36.18. UPDI Timing.............................................................................................................................506
36.19. Programming Time...................................................................................................................507
Trademarks................................................................................................................................................ 551
32 KB ATtiny3216 ATtiny3217
2 KB ATtiny212 ATtiny214
Pins
8 14 20 24
Devices with different Flash memory sizes typically also have different SRAM and EEPROM.
ATtiny214
ATtiny412
ATtiny414
Pins 8 14 8 14
SRAM 128B 128B 256B 256B
Flash 2 KB 2 KB 4 KB 4 KB
EEPROM 64B 64B 128B 128B
Max. frequency (MHz) 16 16 16 16
16-bit Timer/Counter type A (TCA) 1 1 1 1
16-bit Timer/Counter type B (TCB) 1 1 1 1
12-bit Timer/Counter type D (TCD) 1 1 1 1
...........continued
ATtiny212
ATtiny214
ATtiny412
ATtiny414
Real-Time Counter (RTC) 1 1 1 1
USART 1 1 1 1
SPI 1 1 1 1
TWI (I2C) 1 1 1 1
ADC 1 1 1 1
ADC channels 6 10 6 10
DAC 1 1 1 1
AC 1 1 1 1
AC inputs 1p/1n 1p/1n 1p/1n 1p/1n
Peripheral Touch Controller (PTC) No No No No
Configurable Custom Logic 1 1 1 1
Window Watchdog 1 1 1 1
Event System channels 6 6 6 6
General purpose I/O 6 12 6 12
External interrupts 6 12 6 12
CRCSCAN 1 1 1 1
3. Block Diagram
Figure 3-1. tinyAVR® 1-series Block Diagram
Analog peripherals
® analog
Digital peripherals
analog peripherals
Core components
Flash
M M M
S
SDA
SCL TWI0
Note: The block diagram represents the largest device of the tinyAVR 1-series, both in terms of pin count and Flash
size. See sections 2.1 Configuration Summary and 5.1 Multiplexed Signals for an overview of the features of the
specific devices in this data sheet.
4. Pinout
VDD 1 8 GND
PA6 2 7 PA3/EXTCLK
PA7 3 6 PA0/RESET/UPDI
PA1 4 5 PA2
Analog function
VDD 1 14 GND
PA4 2 13 PA3/EXTCLK
PA5 3 12 PA2
PA6 4 11 PA1
PA7 5 10 PA0/RESET/UPDI
TOSC1/PB3 6 9 PB0
TOSC2/PB2 7 8 PB1
Analog function
Notes:
1. Pin names are of type Pxn, with x being the PORT instance (A, B) and n the pin number. The notation for
signals is PORTx_PINn. All pins can be used as event input.
2. All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous
detection.
3. Alternate pin positions. For selecting the alternate positions, refer to section 16. PORTMUX - Port Multiplexer.
Table 5-2. PORT Function Multiplexing, Eight Pins
SOIC 8-Pin Pin Name Other/ ADC0 AC0 DAC0 USART0 SPI0 TWI0 TCA0 TCB0 TCD0 CCL
(1,2) Special
6 PA0 RESET/UPDI AIN0 XDIR SS LUT0-IN0
4 PA1 AIN1 TxD(3) MOSI SDA WO1 LUT0-IN1
5 PA2 EVOUT0 AIN2 RxD(3) MISO SCL WO2 LUT0-IN2
7 PA3 EXTCLK AIN3 OUT XCK SCK WO0/WO3
8 GND
1 VDD
2 PA6 AIN6 AINN0 OUT TxD MOSI(3) WO0 WOA LUT0-OUT
3 PA7 AIN7 AINP0 RxD MISO(3) WO0(3) WOB LUT1-OUT
Notes:
1. Pin names are of type Pxn, with x being the PORT instance (A, B) and n the pin number. Notation for signals is
PORTx_PINn. All pins can be used as event inputs.
2. All pins can be used for external interrupts, where pins Px2 and Px6 of each port have full asynchronous
detection.
3. Alternate pin positions. For selecting the alternate positions, refer to section 16. PORTMUX - Port Multiplexer.
7. Memories
7.1 Overview
The main memories are SRAM data memory, EEPROM data memory, and Flash program memory. Also, the
peripheral registers are located in the I/O memory space.
Table 7-1. Physical Properties of Flash Memory
0x1400
EEPROM 64/128B
0x1440 (For EEPROM 64B)/
0x1480 (For EEPROM 128B)
(Reserved)
0x3F80/0x3F00
Flash Code
2/4 KB
Internal SRAM
128/256B
0x3FFF
(Reserved)
0x8000
Flash Code
2/4 KB
The Program Counter (PC) is 11-bit wide to address the whole program memory. The procedure for writing Flash
memory is described in detail in the documentation of the Nonvolatile Memory Controller (NVMCTRL) peripheral.
The entire Flash memory is mapped in the memory space and is accessible with normal LD/ST instructions as well as
the LPM instruction. For LD/ST instructions, the Flash is mapped from address 0x8000. For the LPM instruction, the
Flash start address is 0x0000.
The ATtiny212/214/412/414 Automotive also has a CRC peripheral that is a master on the bus.
Figure 7-2. Flash and the Three Sections
FLASHSTART: 0x8000
BO OT
BOOTEND>0: 0x8000+BOOTEND*256
AP PL ICA TIO N
FLASH
CO DE
APPEND>0: 0x8000+APPEND*256
AP PL ICA TIO N
DA TA
FLASHEND
Name: GPIORn
Offset: 0x00 + n*0x01 [n=0..3]
Reset: 0x00
Property: -
These are general purpose registers that can be used to store data, such as global variables and flags, in the bit-
accessible I/O memory space.
Bit 7 6 5 4 3 2 1 0
GPIOR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
7.9 Memory Section Access from CPU and UPDI on Locked Device
The device can be locked so that the memories cannot be read using the UPDI. The locking protects both the Flash
(all Boot, Application Code, and Application Date sections), SRAM, and the EEPROM including the FUSE data. This
prevents successful reading of application data or code using the debugger interface. Regular memory access from
within the application is still enabled.
The device is locked by writing a non-valid key to the LOCKBIT bit field in FUSE.LOCKBIT.
Table 7-5. Memory Access Unlocked (FUSE.LOCKBIT Valid Key)(1)
Notes:
1. Read operations marked No in the tables may appear to be successful, but the data are not valid. Hence, any
attempt of code validation through the UPDI will fail on these memory sections.
2. In the Locked mode, the USERROW can be written using the Fuse Write command, but the current
USERROW values cannot be read out.
Important: The only way to unlock a device is through a CHIPERASE. No application data are retained.
7.10.2.1 Device ID n
Name: DEVICEIDn
Offset: 0x00 + n*0x01 [n=0..2]
Default: [Device ID]
Property: -
Each device has a device ID identifying this device and its properties such as memory sizes, pin count, and die
revision. This can be used to identify a device and hence, the available features by software. The Device ID consists
of three bytes: SIGROW.DEVICEID[2:0].
Bit 7 6 5 4 3 2 1 0
DEVICEID[7:0]
Access R R R R R R R R
Default x x x x x x x x
Name: SERNUMn
Offset: 0x03 + n*0x01 [n=0..9]
Default: [device serial number]
Property: -
Each device has an individual serial number, representing a unique ID. This can be used to identify a specific device
in the field. The serial number consists of ten bytes: SIGROW.SERNUM[9:0].
Bit 7 6 5 4 3 2 1 0
SERNUM[7:0]
Access R R R R R R R R
Default x x x x x x x x
Name: OSC16ERR3V
Offset: 0x22
Default: [Oscillator frequency error value]
Property: -
Bit 7 6 5 4 3 2 1 0
OSC16ERR3V[7:0]
Access R R R R R R R R
Default x x x x x x x x
Name: OSC16ERR5V
Offset: 0x23
Default: [Oscillator frequency error value]
Property: -
Bit 7 6 5 4 3 2 1 0
OSC16ERR5V[7:0]
Access R R R R R R R R
Default x x x x x x x x
Name: WDTCFG
Offset: 0x00
Default: 0x00
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
WINDOW[3:0] PERIOD[3:0]
Access R R R R R R R R
Default 0 0 0 0 0 0 0 0
Name: BODCFG
Offset: 0x01
Default: 0x00
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
The bit values of this fuse register are written to the corresponding BOD configuration registers at start-up.
Bit 7 6 5 4 3 2 1 0
LVL[2:0] SAMPFREQ ACTIVE[1:0] SLEEP[1:0]
Access R R R R R R R R
Default 0 0 0 0 0 0 0 0
Notes:
• The values in the description are typical
• Refer to the BOD and POR Characteristics in Electrical Characteristics for maximum and minimum values
Name: OSCCFG
Offset: 0x02
Default: 0x01
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
OSCLOCK FREQSEL[1:0]
Access R R R
Default 0 0 1
Name: TCD0CFG
Offset: 0x04
Default: 0x00
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
The bit values of this fuse register are written to the corresponding bits in the TCD.FAULTCTRL register of TCD0 at
start-up.
Bit 7 6 5 4 3 2 1 0
CMPDEN CMPCEN CMPBEN CMPAEN CMPD CMPC CMPB CMPA
Access R R R R R R R R
Default 0 0 0 0 0 0 0 0
Name: SYSCFG0
Offset: 0x05
Default: 0xF6
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
CRCSRC[1:0] RSTPINCFG[1:0] EESAVE
Access R R R R R
Default 1 1 0 1 0
Note: When configuring the RESET pin as GPIO, there is a potential conflict between the GPIO actively driving the
output, and a high-voltage UPDI enable sequence initiation. To avoid this, the GPIO output driver is disabled for 768
OSC32K cycles after a System Reset. Enable any interrupts for this pin only after this period.
Name: SYSCFG1
Offset: 0x06
Default: 0x07
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
SUT[2:0]
Access R R R
Default 1 1 1
Name: APPEND
Offset: 0x07
Default: 0x00
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
APPEND[7:0]
Access R R R R R R R R
Default 0 0 0 0 0 0 0 0
Name: BOOTEND
Offset: 0x08
Default: 0x00
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
BOOTEND[7:0]
Access R R R R R R R R
Default 0 0 0 0 0 0 0 0
7.10.4.9 Lockbits
Name: LOCKBIT
Offset: 0x0A
Default: 0xC5
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
LOCKBIT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 0 0 0 1 0 1
...........continued
Base Address Name Description
0x0F00 SYSCFG System Configuration
0x1000 NVMCTRL Nonvolatile Memory Controller
0x1100 SIGROW Signature Row
0x1280 FUSES Device-specific fuses
0x1300 USERROW User Row
Note:
1. The availability of this register depends on the device pin count. PORTB/VPORTB is available for devices with
14 pins or more. PORTC/VPORTC is available for devices with 20 pins or more.
...........continued
Vector Number Program Address Peripheral Source Description
(word)
11 0x0B TCA0_LCMP1/ TCA0, LCMP1/CMP1
TCA0_CMP1
12 0x0C TCA0_CMP2/ TCA0, LCMP2/CMP2
TCA0_LCMP2
13 0x0D TCB0_INT TCB0 - Timer Counter Type B
14 0x0E TCD0_OVF TCD0 - Timer Counter Type D, OVF
15 0x0F TCD0_TRIG TCD0, TRIG
16 0x10 AC0_AC AC0 – Analog Comparator
17 0x11 ADC0_RESRDY ADC0 – Analog-to-Digital Converter, RESRDY
18 0x12 ADC0_WCOMP ADC0, WCOMP
19 0x13 TWI0_TWIS TWI0 - Two-Wire Interface/I2C, TWIS
20 0x14 TWI0_TWIM TWI0, TWIM
21 0x15 SPI0_INT SPI0 - Serial Peripheral Interface
22 0x16 USART0_RXC USART0 - Universal Asynchronous Receiver-
Transmitter, RXC
23 0x17 USART0_DRE USART0, DRE
24 0x18 USART0_TXC USART0, TXC
25 0x19 NVMCTRL_EE NVM - Nonvolatile Memory
Note:
1. The availability of the port pins depends on the device pin count. PORTB is available for devices with 14 pins
or more. PORTC is available for devices with 20 pins or more.
0x00 Reserved
0x01 REVID 7:0 REVID[7:0]
Name: REVID
Offset: 0x01
Reset: [revision ID]
Property: -
Bit 7 6 5 4 3 2 1 0
REVID[7:0]
Access R R R R R R R R
Reset
9. AVR® CPU
9.1 Features
• 8-bit, High-Performance AVR RISC CPU:
– 135 instructions
– Hardware multiplier
• 32 8-bit Registers Directly Connected to the ALU
• Stack in RAM
• Stack Pointer Accessible in I/O Memory Space
• Direct Addressing of up to 64 KB of Unified Memory
• Efficient Support for 8-, 16-, and 32-bit Arithmetic
• Configuration Change Protection for System-Critical Features
• Native On-Chip Debugging (OCD) Support:
– Two hardware breakpoints
– Change of flow, interrupt, and software breakpoints
– Run-time read-out of Stack Pointer (SP) register, Program Counter (PC), and Status Register (SREG)
– Register file read- and writable in Stopped mode
9.2 Overview
All AVR devices use the AVR 8-bit CPU. The CPU is able to access memories, perform calculations, control
peripherals, and execute instructions in the program memory. Interrupt handling is described in a separate section.
9.3 Architecture
To maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate buses for
program and data. Instructions in the program memory are executed with a single-level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions
to be executed on every clock cycle.
Refer to the Instruction Set Summary section for a summary of all AVR instructions.
Instruction
Decode
Status
Register ALU
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALU operation
using two register operands is executed, and the result is stored in the destination register.
clkCPU
Total Execution Time
ICALL Decremented by 2 A return address is pushed onto the stack with a subroutine call or interrupt
RCALL
POP Incremented by 1 Data are popped from the stack
A return address is popped from the stack with a return from subroutine or return
RET RETI Incremented by 2
from interrupt
During interrupts or subroutine calls, the return address is automatically pushed on the stack as a word pointer, and
the SP is decremented by two. The return address consists of two bytes and the Least Significant Byte (LSB) is
pushed on the stack first (at the higher address). As an example, a byte pointer return address of 0x0006 is saved on
the stack as 0x0003 (shifted one bit to the right), pointing to the fourth 16-bit instruction word in the program memory.
The return address is popped off the stack with RETI (when returning from interrupts) and RET (when returning from
subroutine calls), and the SP is incremented by two.
The SP is decremented by ‘1’ when data are pushed on the stack with the PUSH instruction, and incremented by ‘1’
when data are popped off the stack using the POP instruction.
To prevent corruption when updating the SP from software, a write to SPL will automatically disable interrupts for up
to four instructions or until the next I/O memory write, whichever comes first.
A
A
V
V
R
DATAH DATAH R
D
D
A
TEMP A
TEMP T
T
A
A
DATAL B DATAL B
U
U
S
S
For a 16-bit write operation, the low byte register (e.g. DATAL) of the 16-bit register must be written before the high
byte register (e.g. DATAH). Writing the low byte register will result in a write to the temporary (TEMP) register instead
of the low byte register, as shown in the left side of Figure 9-6. When the high byte register of the 16-bit register is
written, TEMP will be copied into the low byte of the 16-bit register in the same clock cycle, as shown in the right side
of Figure 9-6.
Figure 9-7. 16-Bit Register Read Operation
A
A
V
V
R
DATAH DATAH R
D
D
A
TEMP A
TEMP T
T
A
A
DATAL B DATAL B
U
U
S
S
For a 16-bit read operation, the low byte register (e.g. DATAL) of the 16-bit register must be read before the high byte
register (e.g. DATAH). When the low byte register is read, the high byte register of the 16-bit register is copied into
the temporary (TEMP) register in the same clock cycle, as show in the left side of Figure 9-7. Reading the high byte
register will result in a read from TEMP instead of the high byte register, as shown in right side of Figure 9-7.
The described mechanism ensures that the low and high bytes of 16-bit registers are always accessed
simultaneously when reading or writing the registers.
Interrupts can corrupt the timed sequence if an interrupt is triggered during a 16-bit read/write operation and a 16-bit
register within the same peripheral is accessed in the interrupt service routine. To prevent this, interrupts should be
disabled when writing or reading 16-bit registers. Alternatively, the temporary register can be read before and
restored after the 16-bit access in the interrupt service routine.
9.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
In order to write to registers protected by CCP, these steps are required:
1. The software writes the signature that enables change of protected I/O registers to the CCP bit field in the
CPU.CCP register.
2. Within four instructions, the software must write the appropriate data to the protected register.
Most protected registers also contain a Write Enable/Change Enable/Lock bit. This bit must be written to ‘1’ in
the same operation as the data are written.
The protected change is immediately disabled if the CPU performs write operations to the I/O register or data
memory, if load or store accesses to Flash, NVMCTRL, or EEPROM are conducted, or if the SLEEP instruction
is executed.
0x00
... Reserved
0x03
0x04 CCP 7:0 CCP[7:0]
0x05
... Reserved
0x0C
7:0 SP[7:0]
0x0D SP
15:8 SP[15:8]
0x0F SREG 7:0 I T H S V N Z C
Name: CCP
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CCP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: SP
Offset: 0x0D
Reset: Top of stack
Property: -
The CPU.SP register holds the Stack Pointer (SP) that points to the top of the stack. After being reset, the SP points
to the highest internal SRAM address.
Only the number of bits required to address the available data memory, including external memory (up to 64 KB), is
implemented for each device. Unused bits will always read as ‘0’.
The CPU.SPL and CPU.SPH register pair represents the 16-bit value, CPU.SP. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
To prevent corruption when updating the SP from software, a write to CPU.SPL will automatically disable interrupts
for the next four instructions or until the next I/O memory write, whichever comes first.
Bit 15 14 13 12 11 10 9 8
SP[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset
Bit 7 6 5 4 3 2 1 0
SP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset
Name: SREG
Offset: 0x0F
Reset: 0x00
Property: -
The Status Register contains information about the result of the most recently executed arithmetic or logic
instructions. For details about the bits in this register and how they are influenced by different instructions, see the
Instruction Set Summary section.
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
10.1 Features
• Unified Memory
• In-System Programmable
• Self-Programming and Boot Loader Support
• Configurable Sections for Write Protection:
– Boot section for boot loader code or application code
– Application code section for application code
– Application data section for application code or data storage
• Signature Row for Factory-Programmed Data:
– ID for each device type
– Serial number for each device
– Calibration bytes for factory-calibrated peripherals
• User Row for Application Data:
– Can be read and written from software
– Can be written from UPDI on locked device
– Content is kept after chip erase
10.2 Overview
The NVM Controller (NVMCTRL) is the interface between the CPU and Nonvolatile Memories (Flash, EEPROM,
Signature Row, User Row and fuses). These are reprogrammable memory blocks that retain their values even when
they are not powered. The Flash is mainly used for program storage and can also be used for data storage. The
EEPROM is used for data storage and can be programmed while the CPU is running the program from the Flash.
NVMCTRL
Signature Row
User Row
10.3.1.1 Flash
The Flash is divided into a set of pages. A page is the basic unit addressed when programming the Flash. It is only
possible to write or erase a whole page at a time. One page consists of several words.
The Flash can be divided into three sections in blocks of 256 bytes for different security. The three different sections
are BOOT, Application Code (APPCODE), and Application Data (APPDATA).
Figure 10-2. Flash Sections
FLASHSTART : 0x8000
BOOT
BOOTEND>0: 0x8000+BOOTEND*256
APPLICATION
CODE
APPEND>0: 0x8000+APPEND*256
APPLICATION
DATA
Section Sizes
The sizes of these sections are set by the Boot Section End fuse (FUSE.BOOTEND) and the Application Code
Section End fuse (FUSE.APPEND).
The fuses select the section sizes in blocks of 256 bytes. The BOOT section stretches from the start of the Flash until
BOOTEND. The APPCODE section runs from BOOTEND until APPEND. The remaining area is the APPDATA
section. If APPEND is written to ‘0’, the APPCODE section runs from BOOTEND to the end of Flash (removing the
APPDATA section). If BOOTEND and APPEND are written to ‘0’, the entire Flash is regarded as the BOOT section.
APPEND may either be set to ‘0’ or a value greater than or equal to BOOTEND.
Table 10-1. Setting Up Flash Sections
Notes:
1. See also the BOOTEND and APPEND descriptions.
2. Interrupt vectors are by default located after the BOOT section. This can be changed in the interrupt controller.
If FUSE.BOOTEND is written to 0x04 and FUSE.APPEND is written to 0x08, the first 4*256 bytes
will be BOOT, the next 4*256 bytes will be APPCODE, and the remaining Flash will be APPDATA.
10.3.1.2 EEPROM
The EEPROM is divided into a set of pages where one page consists of multiple bytes. The EEPROM has byte
granularity on erase/write. Within one page, only the bytes marked to be updated will be erased/written. The byte is
marked by writing a new value to the page buffer for that address location.
10.3.2.1 Read
Reading of the Flash and EEPROM is done by using load instructions with an address according to the memory map.
Reading any of the arrays while a write or erase is in progress will result in a bus wait, and the instruction will be
suspended until the ongoing operation is complete.
10.3.2.3 Programming
For page programming, filling the page buffer and writing the page buffer into Flash, User Row, and EEPROM are
two separate operations.
Before programming a Flash page with the data in the page buffer, the Flash page must be erased. The page buffer
is also erased when the device enters a Sleep mode. Programming an unerased Flash page will corrupt its content.
The Flash can either be written with the erase and write separately, or one command handling both:
Alternative 1:
10.3.2.4 Commands
Reading the Flash/EEPROM and writing the page buffer is handled with normal load/store instructions. Other
operations, such as writing and erasing the memory arrays, are handled by commands in the NVM.
To execute a command in the NVM:
1. Confirm that any previous operation is completed by reading the Busy Flags (EEBUSY and FBUSY) in the
NVMCTRL.STATUS register.
2. Write the NVM command unlock to the Configuration Change Protection register in the CPU (CPU.CCP).
3. Write the desired command value to the CMD bits in the Control A register (NVMCTRL.CTRLA) within the next
four instructions.
10.3.4 Interrupts
Table 10-2. Available Interrupt Vectors and Sources
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags
(NVMCTRL.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding bit in the Interrupt Control
(NVMCTRL.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the NVMCTRL.INTFLAGS register for
details on how to clear interrupt flags.
Register Key
NVMCTRL.CTRLA SPM
10.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
CMD[2:0]
Access R/W R/W R/W
Reset 0 0 0
10.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
BOOTLOCK APCWP
Access R/W R/W
Reset 0 0
10.5.3 Status
Name: STATUS
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
WRERROR EEBUSY FBUSY
Access R R R
Reset 0 0 0
Name: INTCTRL
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
EEREADY
Access R/W
Reset 0
Name: INTFLAGS
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
EEREADY
Access R/W
Reset 0
10.5.6 Data
Name: DATA
Offset: 0x06
Reset: 0x00
Property: -
The NVMCTRL.DATAL and NVMCTRL.DATAH register pair represents the 16-bit value, NVMCTRL.DATA. The low
byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset
+ 0x01.
Bit 15 14 13 12 11 10 9 8
DATA[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
10.5.7 Address
Name: ADDR
Offset: 0x08
Reset: 0x00
Property: -
The NVMCTRL.ADDRL and NVMCTRL.ADDRH register pair represents the 16-bit value, NVMCTRL.ADDR. The low
byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset
+ 0x01.
Bit 15 14 13 12 11 10 9 8
ADDR[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
11.1 Features
• All Clocks and Clock Sources are Automatically Enabled when Requested by Peripherals
• Internal Oscillators:
– 16 MHz Oscillator (OSC20M)
– 32.768 kHz Ultra Low-Power Oscillator (OSCULP32K)
• External Clock Options:
– 32.768 kHz Crystal Oscillator (XOSC32K)(1)
– External clock
• Main Clock Features:
– Safe run-time switching
– Prescaler with 1x to 64x division in 12 different settings
Note:
1. Available for devices with 14 pins or more.
11.2 Overview
The Clock Controller (CLKCTRL) peripheral controls, distributes and prescales the clock signals from the available
oscillators. The CLKCTRL supports internal and external clock sources.
The CLKCTRL is based on an automatic clock request system, implemented in all peripherals on the device. The
peripherals will automatically request the clocks needed. If multiple clock sources are available, the request is routed
to the correct clock source.
The Main Clock (CLK_MAIN) is used by the CPU, RAM, and the I/O bus. The main clock source can be selected and
prescaled. Some peripherals can share the same clock source as the main clock, or run asynchronously to the main
clock domain.
Other RTC
NVM RAM CPU CLKOUT
Int. WDT BOD TCD
Peripherals Prescaler
CLK_CPU CLK_PER
CLK_RTC CLK_WDT CLK_BOD CLK_TCD
TCD
CLKCSEL
Main Clock Prescaler
CLK_MAIN
RTC
Main Clock Switch CLKSEL
DIV32
XOSC32K
OSCULP32K
OSC20M
XOSC32K
SEL
– CLK_TCD is used by the TCD. It will be requested when the TCD is enabled. The clock source can only be
changed if the peripheral is disabled.
The clock source for the Main Clock domain is configured by writing to the Clock Select (CLKSEL) bits in the Main
Clock Control A (CLKCTRL.MCLKCTRLA) register. The asynchronous clock sources are configured by registers in
the respective peripheral.
If an external clock source fails while used as CLK_MAIN source, only the WDT can provide a mechanism
CAUTION
to switch back via System Reset.
CLK_MAIN is fed into a prescaler before it is used by the peripherals (CLK_PER) in the device. The prescaler divides
CLK_MAIN by a factor from 1 to 64.
Figure 11-2. Main Clock and Prescaler
OSC20M
Main Clock Prescaler
32.768 kHz Osc. CLK_MAIN CLK_PER
32.768 kHz crystal Osc. (Div 1, 2, 4, 8, 16, 32,
64, 6, 10, 24, 48)
External clock
The Main Clock and Prescaler configuration (CLKCTRL.MCLKCTRLA, CLKCTRL.MCLKCTRLB) registers are
protected by the Configuration Change Protection Mechanism, employing a timed write procedure for changing these
registers.
#include <assert.h>
/* Baud rate compensated with factory stored frequency error */
/* Asynchronous communication without Auto-baud (Sync Field) */
/* 16MHz Clock, 3V and 600 BAUD */
Register Key
CLKCTRL.MCLKCTRLB IOREG
CLKCTRL.MCLKLOCK IOREG
CLKCTRL.XOSC32KCTRLA IOREG
CLKCTRL.MCLKCTRLA IOREG
CLKCTRL.OSC20MCTRLA IOREG
CLKCTRL.OSC20MCALIBA IOREG
CLKCTRL.OSC20MCALIBB IOREG
CLKCTRL.OSC32KCTRLA IOREG
Name: MCLKCTRLA
Offset: 0x00
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
CLKOUT CLKSEL[1:0]
Access R/W R/W R/W
Reset 0 0 0
Name: MCLKCTRLB
Offset: 0x01
Reset: 0x11
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
PDIV[3:0] PEN
Access R/W R/W R/W R/W R/W
Reset 1 0 0 0 1
Name: MCLKLOCK
Offset: 0x02
Reset: Based on OSCLOCK in FUSE.OSCCFG
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
LOCKEN
Access R/W
Reset x
Name: MCLKSTATUS
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
EXTS XOSC32KS OSC32KS OSC20MS SOSC
Access R R R R R
Reset 0 0 0 0 0
Name: OSC20MCTRLA
Offset: 0x10
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
RUNSTDBY
Access R/W
Reset 0
Name: OSC20MCALIBA
Offset: 0x11
Reset: Based on FREQSEL in FUSE.OSCCFG
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
CAL20M[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset x x x x x x
Name: OSC20MCALIBB
Offset: 0x12
Reset: Based on FUSE.OSCCFG
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
LOCK TEMPCAL20M[3:0]
Access R R/W R/W R/W R/W
Reset x x x x x
Name: OSC32KCTRLA
Offset: 0x18
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
RUNSTDBY
Access R/W
Reset 0
Name: XOSC32KCTRLA
Offset: 0x1C
Reset: 0x00
Property: Configuration Change Protection
The SEL and CSUT bits cannot be changed as long as the ENABLE bit is set, or the XOSC32K Stable (XOSC32KS)
bit in CLKCTRL.MCLKSTATUS is high.
To change settings safely, write a '0' to the ENABLE bit and wait until XOSC32KS is '0' before re-enabling the
XOSC32K with new settings.
Bit 7 6 5 4 3 2 1 0
CSUT[1:0] SEL RUNSTDBY ENABLE
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
12.1 Features
• Power Management for Adjusting Power Consumption and Functions
• Three Sleep Modes:
– Idle
– Standby
– Power-Down
• Configurable Standby Mode where Peripherals Can Be Configured as ON or OFF
12.2 Overview
Sleep modes are used to shut down peripherals and clock domains in the device in order to save power. The Sleep
Controller (SLPCTRL) controls and handles the transitions between Active and sleep modes.
There are four modes available: One Active mode in which software is executed, and three sleep modes. The
available sleep modes are Idle, Standby and Power-Down.
All sleep modes are available and can be entered from the Active mode. In Active mode, the CPU is executing
application code. When the device enters sleep mode, the program execution is stopped. The application code
decides which sleep mode to enter and when.
Interrupts are used to wake the device from sleep. The available interrupt wake-up sources depend on the configured
sleep mode. When an interrupt occurs, the device will wake up and execute the Interrupt Service Routine before
continuing normal program execution from the first instruction after the SLEEP instruction. Any Reset will take the
device out of sleep mode.
The content of the register file, SRAM and registers, is kept during sleep. If a Reset occurs during sleep, the device
will reset, start and execute from the Reset vector.
Interrupt Request
SLPCTRL CPU
Sleep State
Interrupt Request
Peripheral
12.3.1 Initialization
To put the device into a sleep mode, follow these steps:
1. Configure and enable the interrupts that are able to wake the device from sleep.
Also, enable global interrupts.
If there are no interrupts enabled when going to sleep, the device cannot wake up again. Only a
WARNING
Reset will allow the device to continue operation.
2. Select which sleep mode to enter and enable the Sleep Controller by writing to the Sleep Mode (SMODE) bit
field and the Enable (SEN) bit in the Control A (SLPCTRL.CTRLA) register.
The SLEEP instruction must be executed to make the device go to sleep.
12.3.2 Operation
...........continued
Group Peripheral Active in Sleep Mode
Clock Idle Standby Power-Down
Wake-Up Sources PORT Pin interrupt X X X
TWI Address Match interrupt X X X
USART Start-of-Frame interrupts X X(1)
ADC interrupts X X(1)
RTC interrupts X X(1) X(2)
TCBn Capture interrupt X X(1)
All other interrupts X
Notes:
1. The RUNSTBY bit of the corresponding peripheral must be set to enter the Active state.
2. Only the PIT is available in the Power-Down sleep mode.
3. Sampled mode only.
The start-up time for the different clock sources is described in the Clock Controller (CLKCTRL) section.
In addition to the normal wake-up time, it is possible to make the device wait until the BOD is ready before executing
code. This is done by writing 0x3 to the BOD Operation mode in Active and Idle bits (ACTIVE) in the BOD
Configuration fuse (FUSE.BODCFG). If the BOD is ready before the normal wake-up time, the total wake-up time will
be the same. If the BOD takes longer than the normal wake-up time, the wake-up time will be extended until the BOD
is ready. This ensures correct supply voltage whenever code is executed.
12.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SMODE[1:0] SEN
Access R R R R R R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
13.1 Features
• Returns the Device to an Initial State after a Reset
• Identifies the Previous Reset Source
• Power Supply Reset Sources:
– Power-on Reset (POR)
– Brown-out Detector (BOD) Reset
• User Reset Sources:
– External Reset (RESET)
– Watchdog Timer (WDT) Reset
– Software Reset (SWRST)
– Universal Program Debug Interface (UPDI) Reset
13.2 Overview
The Reset Controller (RSTCTRL) manages the Reset of the device. It issues a device Reset, sets the device to its
initial state, and allows the Reset source to be identified by software.
VDD POR
Pull-up
resistor BOD UPDI
WDT
All other
peripherals
UPDI
CPU (SW)
13.3.1 Initialization
The RSTCTRL is always enabled, but some of the Reset sources must be enabled individually (either by Fuses or by
software) before they can request a Reset.
After a Reset from any source, the registers in the device with automatic loading from the Fuses or from the
Signature Row are updated.
13.3.2 Operation
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
VDD VBOT+
VBOT-
TIME-OUT tTOUT
INTERNAL
RESET
tEXT
Register Key
RSTCTRL.SWRR IOREG
Name: RSTFR
Offset: 0x00
Reset: 0xXX
Property: -
All flags are cleared by writing a '1' to them. They are also cleared by a Power-on Reset (POR), with the exception of
the Power-on Reset Flag (PORF).
Bit 7 6 5 4 3 2 1 0
UPDIRF SWRF WDRF EXTRF BORF PORF
Access R/W R/W R/W R/W R/W R/W
Reset x x x x x x
Name: SWRR
Offset: 0x01
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
SWRE
Access R/W
Reset 0
14.1 Features
• Short and Predictable Interrupt Response Time
• Separate Interrupt Configuration and Vector Address for Each Interrupt
• Interrupt Prioritizing by Level and Vector Address
• Non-Maskable Interrupts (NMI) for Critical Functions
• Two Interrupt Priority Levels: 0 (Normal) and 1 (High):
– One of the interrupt requests can optionally be assigned as a priority level 1 interrupt
– Optional round robin priority scheme for priority level 0 interrupts
• Interrupt Vectors Optionally Placed in the Application Section or the Boot Loader Section
• Selectable Compact Vector Table (CVT)
14.2 Overview
An interrupt request signals a change of state inside a peripheral and can be used to alter the program execution.
The peripherals can have one or more interrupts. All interrupts are individually enabled and configured. When an
interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition occurs.
The CPU Interrupt Controller (CPUINT) handles and prioritizes the interrupt requests. When an interrupt is enabled
and the interrupt condition occurs, the CPUINT will receive the interrupt request. Based on the interrupt's priority level
and the priority level of any ongoing interrupt, the interrupt request is either acknowledged or kept pending until it has
priority. After returning from the interrupt handler, the program execution continues from where it was before the
interrupt occurred, and any pending interrupts are served after one instruction is executed.
The CPUINT offers NMI for critical functions, one selectable high-priority interrupt and an optional round robin
scheduling scheme for normal-priority interrupts. The round robin scheduling ensures that all interrupts are serviced
within a certain amount of time.
Interrupt Controller
Priority
Decoder
INT REQ
Peripheral 1
CPU RETI
CPU INT ACK
CPU
CPU INT REQ
INT REQ
Peripheral n
Global
STATUS Interrupt
LVL0PRI Enable Wake-up
LVL1VEC SLPCTRL
CPU.SREG
14.3.1 Initialization
An interrupt must be initialized in the following order:
1. Configure the CPUINT if the default configuration is not adequate (optional):
– Vector handling is configured by writing to the respective bits (IVSEL and CVT) in the Control A
(CPUINT.CTRLA) register.
– Vector prioritizing by round robin is enabled by writing a ‘1’ to the Round Robin Priority Enable (LVL0RR)
bit in CPUINT.CTRLA.
– Select the Priority Level 1 vector by writing the interrupt vector number to the Interrupt Vector with Priority
Level 1 (CPUINT.LVL1VEC) register.
2. Configure the interrupt conditions within the peripheral and enable the peripheral’s interrupt.
3. Enable interrupts globally by writing a ‘1’ to the Global Interrupt Enable (I) bit in the CPU Status (CPU.SREG)
register.
14.3.2 Operation
After the Program Counter is pushed on the stack, the program vector for the interrupt is executed. See the following
figure.
(1)
If an interrupt occurs during the execution of a multi-cycle instruction, the instruction is completed before the interrupt
is served, as shown in the following figure.
Figure 14-3. Interrupt Execution of Multi-Cycle Instruction
(1)
If an interrupt occurs when the device is in a sleep mode, the interrupt execution response time is increased by five
clock cycles, as shown in the figure below. Also, the response time is increased by the start-up time from the selected
sleep mode.
Figure 14-4. Interrupt Execution From Sleep
(1)
A return from an interrupt handling routine takes four to five clock cycles, depending on the size of the Program
Counter. During these clock cycles, the Program Counter is popped from the stack, and the Stack Pointer is
incremented.
Note:
1. Devices with 8 KB of Flash or less use RJMP instead of JMP, which takes only two clock cycles.
Static Scheduling
If several level 0 interrupt requests are pending at the same time, the one with the highest priority is scheduled for
execution first. The following figure illustrates the default configuration, where the interrupt vector with the lowest
address has the highest priority.
Figure 14-5. Default Static Scheduling
Lowest Address IVEC 0 Highest Priority
IVEC 1
:
:
:
:
:
:
Here, value Y has been written to CPUINT.LVL0PRI, so that interrupt vector Y+1 has the highest priority. Note that, in
this case, the priorities will wrap so that the lowest address no longer has the highest priority. This does not include
RESET and NMI, which will always have the highest priority.
Refer to the interrupt vector mapping of the device for available interrupt requests and their interrupt vector number.
: :
: :
: :
IVEC n IVEC n
The round robin scheduling for LVL0 interrupt requests is enabled by writing a ‘1’ to the Round Robin Priority Enable
(LVL0RR) bit in the Control A (CPUINT.CTRLA) register.
Register Key
IVSEL in CPUINT.CTRLA IOREG
CVT in CPUINT.CTRLA IOREG
14.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
IVSEL CVT LVL0RR
Access R/W R/W R/W
Reset 0 0 0
14.5.2 Status
Name: STATUS
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
NMIEX LVL1EX LVL0EX
Access R R R
Reset 0 0 0
Name: LVL0PRI
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
LVL0PRI[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: LVL1VEC
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
LVL1VEC[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
15.1 Features
• System for Direct Peripheral-to-Peripheral Signaling
• Peripherals Can Directly Produce, Use and React to Peripheral Events
• Short Response Time
• Up to Four Parallel Asynchronous Event Channels Available
• Up to Two Parallel Synchronous Event Channels Available
• Channels Can Be Configured to Have One Triggering Peripheral Action and Multiple Peripheral Users
• Peripherals Can Directly Trigger and React to Events from Other Peripherals
• Events Can Be Sent and/or Received by Most Peripherals, and by Software
• Works in Active Mode and Standby Sleep Mode
15.2 Overview
The Event System (EVSYS) enables direct peripheral-to-peripheral signaling. It allows a change in one peripheral
(the event generator) to trigger actions in other peripherals (the event users) through event channels, without using
the CPU. It is designed to provide short and predictable response times between peripherals, allowing for
autonomous peripheral control and interaction, and also for the synchronized timing of actions in several peripheral
modules. It is thus a powerful tool for reducing the complexity, size, and the execution time of the software.
A change of the event generator’s state is referred to as an event and usually corresponds to one of the peripheral’s
interrupt conditions. Events can be directly forwarded to other peripherals using the dedicated event routing network.
The routing of each channel is configured in software, including event generation and use.
Only one trigger from an event generator peripheral can be routed on each channel, but multiple channels can use
the same generator source. Multiple peripherals can use events from the same channel.
A channel path can be either asynchronous or synchronous to the main clock. The mode must be selected based on
the requirements of the application.
The Event System can directly connect analog and digital converters, analog comparators, I/O port pins, the real-time
counter, timer/counters, and the configurable custom logic peripheral. Events can also be generated from software
and the peripheral clock.
Sync source 0
To sync user
Sync source 1 ..
.. .
.
Sync source n
Async user y
Async event channel ”l” Async user 0
Async event channel 0
.. To async user
Async source 0 .
Async source 1 ..
.. .
.
Async source m
Timer/Counter ADC
Compare Match
Channel Sweep
Event
Over-/Underflow
| Routing
Single
Network Conversion
Error
15.2.3.1 Clocks
The EVSYS uses the peripheral clock for I/O registers and software events. When correctly set up, the routing
network can also be used in sleep modes without any clock. Software events will not work in sleep modes where the
peripheral clock is halted.
15.3.1 Initialization
Before enabling events within the device, the event users multiplexer and event channels must be configured.
15.3.2 Operation
The event user multiplexers are configured by writing to the corresponding registers:
• Event users supporting both synchronous and asynchronous events are configured by writing to the respective
asynchronous User Channel Input Selection n (EVSYS.ASYNCUSERn) register
• The users of synchronous-only events are configured by writing to the respective Synchronous User Channel
Input Selection n (EVSYS.SYNCUSERn) register
The default setup of all user multiplexers is OFF.
15.3.3 Interrupts
Not applicable.
15.3.6 Synchronization
Asynchronous events are synchronized and handled by compatible event users. Event user peripherals not
compatible with asynchronous events can only be configured to listen to synchronous event channels.
Name: ASYNCSTROBE
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ASYNCSTROBE[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: SYNCSTROBE
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SYNCSTROBE[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: ASYNCCHn
Offset: 0x02 + n*0x01 [n=0..3]
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ASYNCCH[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Note: Not all pins of a port are available on devices with low pin counts. Check the Pinout Diagram and/or the I/O
Multiplexing table for details.
Name: SYNCCHn
Offset: 0x0A + n*0x01 [n=0..1]
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SYNCCH[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Note: Not all pins of a port are available on devices with low pin counts. Check the Pinout Diagram and/or the I/O
Multiplexing table for details.
Name: ASYNCUSERn
Offset: 0x12 + n*0x01 [n=0..12]
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ASYNCUSER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Value Name
0x0 OFF
0x1 SYNCCH0
0x2 SYNCCH1
0x3 ASYNCCH0
0x4 ASYNCCH1
0x5 ASYNCCH2
0x6 ASYNCCH3
Other -
Name: SYNCUSERn
Offset: 0x22 + n*0x01 [n=0..1]
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SYNCUSER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Value Name
0x0 OFF
0x1 SYNCCH0
0x2 SYNCCH1
Other -
16.1 Overview
The Port Multiplexer (PORTMUX) can either enable or disable the functionality of pins, or change between default
and alternative pin positions. This depends on the actual pin and property and is described in detail in the PORTMUX
register map.
For available pins and functionalities, refer to Table 5-1.
16.3.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
EVOUT1 EVOUT0
Access R/W R/W
Reset 0 0
16.3.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
TWI0 SPI0 USART0
Access R/W R/W R/W
Reset 0 0 0
16.3.3 Control C
Name: CTRLC
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
TCA00
Access R/W
Reset 0
17.1 Features
• General Purpose Input and Output Pins with Individual Configuration:
– Pull-up
– Inverted I/O
• Interrupts and Events:
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
• Asynchronous Pin Change Sensing that Can Wake the Device From all Sleep Modes
• Efficient and Safe Access to Port Pins
– Hardware Read-Modify-Write (RMW) through dedicated toggle/clear/set registers
– Mapping of often-used PORT registers into bit-accessible I/O memory space (virtual ports)
17.2 Overview
The I/O pins of the device are controlled by instances of the PORT peripheral registers. Each PORT instance has up
to eight I/O pins. The PORTs are named PORTA, PORTB, PORTC, etc. Refer to the I/O Multiplexing and
Considerations section to see which pins are controlled by what instance of PORT. The base addresses of the PORT
instances and the corresponding Virtual PORT instances are listed in the Peripherals and Architecture section.
Each PORT pin has a corresponding bit in the Data Direction (PORTx.DIR) and Data Output Value (PORTx.OUT)
registers to enable that pin as an output and to define the output state. For example, pin PA3 is controlled by DIR[3]
and OUT[3] of the PORTA instance.
The input value of a PORT pin is synchronized to the Peripheral Clock (CLK_PER) and then made accessible as the
data input value (PORTx.IN). The value of the pin can be read whether the pin is configured as input or output.
The PORT also supports asynchronous input sensing with interrupts and events for selectable pin change conditions.
Asynchronous pin change sensing means that a pin change can trigger an interrupt and wake the device from sleep,
including sleep modes where CLK_PER is stopped.
All pin functions are individually configurable per pin. The pins have hardware Read-Modify-Write functionality for a
safe and correct change of the drive values and/or input and sense configuration.
The PORT pin configuration controls input and output selection of other device functions.
Pull-up Enable
DIRn
D Q
Peripheral Override
R
OUTn
D Q
Pxn
Peripheral Override
R
Invert Enable
Synchronizer
INn
Synchronous
Q D Q D
Input
R R
Sense Configuration
Interrupt
Interrupt
Generator
Asynchronous
Input/Event
Input Disable
Peripheral Override
Analog
Input/Output
17.3.1 Initialization
After Reset, all outputs are tri-stated, and digital input buffers enabled even if there is no clock running.
The following steps are all optional when initializing PORT operation:
• Enable or disable the output driver for pin Pxn by respectively writing ‘1’ to bit n in the PORTx.DIRSET or
PORTx.DIRCLR register
• Set the output driver for pin Pxn to high or low level respectively by writing ‘1’ to bit n in the PORTx.OUTSET or
PORTx.OUTCLR register
• Read the input of pin Pxn by reading bit n in the PORTx.IN register
• Configure the individual pin configurations and interrupt control for pin Pxn in PORTx.PINnCTRL
Important: For lowest power consumption, disable the digital input buffer of unused pins and pins that
are used as analog inputs or outputs.
Specific pins, such as those used to connect a debugger, may be configured differently, as required by their special
function.
17.3.2 Operation
The digital input buffer for pin n can be disabled by writing the INPUT_DISABLE setting to ISC. This can reduce
power consumption and may reduce noise if the pin is used as analog input. While configured to INPUT_DISABLE,
bit n in PORTx.IN will not change since the input synchronizer is disabled.
17.3.3 Interrupts
Table 17-2. Available Interrupt Vectors and Sources
Each PORT pin n can be configured as an interrupt source. Each interrupt can be individually enabled or disabled by
writing to ISC in PORTx.PINnCTRL.
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of the
peripheral (peripheral.INTFLAGS).
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGS register for
details on how to clear interrupt flags.
When setting or changing interrupt settings, take these points into account:
• If an Inverted I/O Enable (INVEN) bit is toggled in the same cycle as ISC is changed, the edge caused by the
inversion toggling may not cause an interrupt request
• If an input is disabled by writing to ISC while synchronizing an interrupt, that interrupt may be requested on re-
enabling the input, even if it is re-enabled with a different interrupt setting
• If the interrupt setting is changed by writing to ISC while synchronizing an interrupt, that interrupt may not be
requested
as per the table below. See the I/O Multiplexing and Considerations section for further details on which pins support
fully asynchronous pin change sensing.
Table 17-3. Behavior Comparison of Sense Pins
Note:
1. If a partially asynchronous input pin is used for wake-up from sleep with CLK_PER stopped, the required level
must be held long enough for the MCU to complete the wake-up to trigger the interrupt. If the level disappears,
the MCU can wake up without any interrupt generated.
17.3.4 Events
PORT can generate the following events:
Table 17-4. Event Generators in PORTx
Generator Name
Description Event Type Generating Clock Domain Length of Event
Peripheral Event
PORTx PINn Pin level Level Asynchronous Given by pin level
All PORT pins are asynchronous event system generators. PORT has as many event generators as there are PORT
pins in the device. Each event system output from PORT is the value present on the corresponding pin if the digital
input buffer is enabled. If a pin input buffer is disabled, the corresponding event system output is zero.
PORT has no event inputs. Refer to the Event System (EVSYS) section for more details regarding event types and
Event System configuration.
Important: The PORTs will always use the Peripheral Clock (CLK_PER). Input synchronization will halt
when this clock stops.
Name: DIR
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DIR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DIRSET
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DIRSET[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DIRCLR
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DIRCLR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DIRTGL
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DIRTGL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: OUT
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
OUT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: OUTSET
Offset: 0x05
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
OUTSET[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: OUTCLR
Offset: 0x06
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
OUTCLR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: OUTTGL
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
OUTTGL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: IN
Offset: 0x08
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
IN[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTFLAGS
Offset: 0x09
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
INT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: PINnCTRL
Offset: 0x10 + n*0x01 [n=0..7]
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
INVEN PULLUPEN ISC[2:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Note:
1. If the digital input buffer for pin n is disabled, bit n in the Input Value (PORTx.IN) register will not be updated.
Name: DIR
Offset: 0x00
Reset: 0x00
Property: -
Access to the Virtual PORT registers has the same outcome as access to the regular registers but allows for memory
specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space
where the regular PORT registers reside.
Bit 7 6 5 4 3 2 1 0
DIR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: OUT
Offset: 0x01
Reset: 0x00
Property: -
Access to the Virtual PORT registers has the same outcome as access to the regular registers but allows for memory
specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space
where the regular PORT registers reside.
Bit 7 6 5 4 3 2 1 0
OUT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: IN
Offset: 0x02
Reset: 0x00
Property: -
Access to the Virtual PORT registers has the same outcome as access to the regular registers but allows for memory
specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space
where the regular PORT registers reside.
Bit 7 6 5 4 3 2 1 0
IN[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTFLAGS
Offset: 0x03
Reset: 0x00
Property: -
Access to the Virtual PORT registers has the same outcome as access to the regular registers but allows for memory
specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space
where the regular PORT registers reside.
Bit 7 6 5 4 3 2 1 0
INT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
18.1 Features
• Brown-out Detector Monitors the Power Supply to Avoid Operation Below a Programmable Level
• Three Available Modes:
– Enabled mode (continuously active)
– Sampled mode
– Disabled
• Separate Selection of Mode for Active and Sleep Modes
• Voltage Level Monitor (VLM) with Interrupt
• Programmable VLM Level Relative to the BOD Level
18.2 Overview
The Brown-out Detector (BOD) monitors the power supply and compares the supply voltage with the programmable
brown-out threshold level. The brown-out threshold level defines when to generate a System Reset. The Voltage
Level Monitor (VLM) monitors the power supply and compares it to a threshold higher than the BOD threshold. The
VLM can then generate an interrupt as an “early warning” when the supply voltage is approaching the BOD threshold.
The VLM threshold level is expressed as a percentage above the BOD threshold level.
The BOD is controlled mainly by fuses and has to be enabled by the user. The mode used in Standby sleep mode
and Power-Down sleep mode can be altered in normal program execution. The VLM is controlled by I/O registers as
well.
When activated, the BOD can operate in Enabled mode, where the BOD is continuously active, or in Sampled mode,
where the BOD is activated briefly at a given period to check the supply voltage level.
VDD
BOD
+
BOD
Reset
BOD Threshold -
VLM
+
VLM
Interrupt
VLM Threshold -
18.3.1 Initialization
The BOD settings are loaded from fuses during Reset. The BOD level and operating mode in Active and Idle sleep
mode are set by fuses and cannot be changed by software. The operating mode in Standby and Power-Down sleep
mode is loaded from fuses and can be changed by software.
The Voltage Level Monitor function can be enabled by writing a ‘1’ to the VLM Interrupt Enable (VLMIE) bit in the
Interrupt Control (BOD.INTCTRL) register. The VLM interrupt is configured by writing the VLM Configuration
(VLMCFG) bits in BOD.INTCTRL. An interrupt is requested when the supply voltage crosses the VLM threshold
either from above, below, or any direction.
The VLM functionality will follow the BOD mode. If the BOD is disabled, the VLM will not be enabled, even if the
VLMIE is ‘1’. If the BOD is using Sampled mode, the VLM will also be sampled. When the VLM interrupt is enabled,
the interrupt flag will be set according to VLMCFG when the voltage level is crossing the VLM level.
The VLM threshold is defined by writing the VLM Level (VLMLVL) bits in the Control A (BOD.VLMCTRLA) register.
18.3.2 Interrupts
Table 18-1. Available Interrupt Vectors and Sources
The VLM interrupt will not be executed if the CPU is halted in Debug mode.
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
Register Key
SLEEP in BOD.CTRLA IOREG
18.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: Loaded from fuse
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
SAMPFREQ ACTIVE[1:0] SLEEP[1:0]
Access R R R R/W R/W
Reset x x x x x
18.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: Loaded from fuse
Property: -
Bit 7 6 5 4 3 2 1 0
LVL[2:0]
Access R R R R R R R R
Reset 0 0 0 0 0 x x x
Notes:
• Refer to the BOD and POR Characteristics in Electrical Characteristics for further details
• Values in the description are typical values
Name: VLMCTRLA
Offset: 0x08
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
VLMLVL[1:0]
Access R/W R/W
Reset 0 0
Name: INTCTRL
Offset: 0x09
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
VLMCFG[1:0] VLMIE
Access R/W R/W R/W
Reset 0 0 0
Name: INTFLAGS
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
VLMIF
Access R/W
Reset 0
Name: STATUS
Offset: 0x0B
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
VLMS
Access R
Reset 0
19.1 Features
• Programmable Voltage Reference Sources:
– One for each ADC peripheral
– One for each AC and DAC peripheral
• Each Reference Source Supports Five Different Voltages:
– 0.55V
– 1.1V
– 1.5V
– 2.5V
– 4.3V
19.2 Overview
The Voltage Reference (VREF) peripheral provides control registers for the voltage reference sources used by
several peripherals. The user can select the reference voltages for the ADC0 by writing to the ADC0 Reference
Select (ADC0REFSEL) bit field in the Control A (VREF.CTRLA) register, and for both AC0 and DAC0 by writing to the
DAC0 Reference Select (DAC0REFSEL) bit field in the Control A (VREF.CTRLA) register.
A voltage reference source is enabled automatically when requested by a peripheral. The user can enable the
reference voltage sources (and thus, override the automatic disabling of unused sources) by writing to the respective
Force Enable (ADC0REFEN, DAC0REFEN) bit in the Control B (VREF.CTRLB) register. This may be done to
decrease start-up time, at the cost of increased power consumption.
Reference reque st
Reference enable
Reference se lect
0.55V
1.1V
Band gap Reference 1.5V Inte rnal
Gen erator
BUF Reference
2.5V
4.3V
Band gap
ena ble
19.3.1 Initialization
The default configuration will enable the respective source when the ADC0, AC0, or DAC0 is requesting a reference
voltage. The default reference voltages are 0.55V but can be configured by writing to the respective Reference Select
(ADC0REFSEL, DAC0REFSEL) bit field in the Control A (VREF.CTRLA) register.
19.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ADC0REFSEL[2:0] DAC0REFSEL[2:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
19.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ADC0REFEN DAC0REFEN
Access R/W R/W
Reset 0 0
20.1 Features
• Issues a System Reset if the Watchdog Timer is not Cleared Before its Time-out Period
• Operating Asynchronously from System Clock Using an Independent Oscillator
• Using the 1.024 kHz Output of the 32.768 kHz Ultra Low-Power Oscillator (OSCULP32K)
• 11 Selectable Time-out Periods, from 8 ms to 8s
• Two Operation Modes:
– Normal mode
– Window mode
• Configuration Lock to Prevent Unwanted Changes
• Closed Period Timer Activation After First WDT Instruction for Easy Setup
20.2 Overview
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It allows the system to
recover from situations such as runaway or deadlocked code by issuing a Reset. When enabled, the WDT is a
constantly running timer configured to a predefined time-out period. If the WDT is not reset within the time-out period,
it will issue a system Reset. The WDT is reset by executing the Watchdog Timer Reset (WDR) instruction from
software.
The WDT has two modes of operation: Normal mode and Window mode. The settings in the Control A (WDT.CTRLA)
register determine the mode of operation.
A Window mode defines a time slot or "window" inside the time-out period during which the WDT must be reset. If the
WDT is reset outside this window, either too early or too late, a system Reset will be issued. Compared to the Normal
mode, the Window mode can catch situations where a code error causes constant WDR execution.
When enabled, the WDT will run in Active mode and all sleep modes. It is asynchronous (i.e., running from a CPU
independent clock source). For this reason, it will continue to operate and be able to issue a system Reset even if the
main clock fails.
The CCP mechanism ensures that the WDT settings cannot be changed by accident. For increased safety, a
configuration for locking the WDT settings is available.
CLK_WDT
COUNT
PERIOD =
System
Reset
CTRLA
WDR
(instruction)
20.3.1 Initialization
• The WDT is enabled when a non-zero value is written to the Period (PERIOD) bits in the Control A
(WDT.CTRLA) register
• Optional: Write a non-zero value to the Window (WINDOW) bits in WDT.CTRLA to enable the Window mode
operation.
All bits in the Control A register and the Lock (LOCK) bit in the STATUS (WDT.STATUS) register are write-protected
by the Configuration Change Protection mechanism.
The Reset value of WDT.CTRLA is defined by a fuse (FUSE.WDTCFG), so the WDT can be enabled at boot time. If
this is the case, the LOCK bit in WDT.STATUS is set at boot time.
20.3.2 Clocks
A 1.024 kHz Oscillator Clock (CLK_WDT_OSC) is sourced from the internal Ultra Low-Power Oscillator,
OSCULP32K. Due to the ultra low-power design, the oscillator is not very accurate, and so the exact time-out period
may vary from device to device. This variation must be kept in mind when designing software that uses the WDT to
ensure that the time-out periods used are valid for all devices.
The 1.024 kHz Oscillator Clock, CLK_WDT_OSC, is asynchronous to the system clock. Due to this asynchronicity,
writing to the WDT Control register will require synchronization between the clock domains.
20.3.3 Operation
WDT Timeout
System Reset
Here: 5 10 15 20 25 30 35 t [ms]
TO WDT = 16 ms TOWDT
Normal mode is enabled as long as the WINDOW bit field in the Control A (WDT.CTRLA) register is 0x0.
Here: 5 10 15 20 25 30 35 t [ms]
TOWDTW =TOWDT = 8 ms TOWDTW TOWDT
The Window mode is enabled by writing a non-zero value to the WINDOW bit field in the Control A (WDT.CTRLA)
register, and disabled by writing it to 0x0.
LOCK in WDT.STATUS can only be written to ‘1’. It can only be cleared in Debug mode.
If the WDT configuration is loaded from fuses, LOCK is automatically set in WDT.STATUS.
20.3.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domain, the Control A (WDT.CTRLA)
register is synchronized when written. The Synchronization Busy (SYNCBUSY) flag in the STATUS (WDT.STATUS)
register indicates if there is an ongoing synchronization.
Writing to WDT.CTRLA while SYNCBUSY=1 is not allowed.
The following registers are synchronized when written:
• PERIOD bits in Control A (WDT.CTRLA) register
• Window Period (WINDOW) bits in WDT.CTRLA
The WDR instruction will need two to three cycles of the WDT clock to be synchronized. Issuing a new WDR instruction
while a WDR instruction is being synchronized will be ignored.
Register Key
WDT.CTRLA IOREG
LOCK bit in WDT.STATUS IOREG
20.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: From FUSE.WDTCFG
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
WINDOW[3:0] PERIOD[3:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset x x x x x x x x
20.5.2 Status
Name: STATUS
Offset: 0x01
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
LOCK SYNCBUSY
Access R/W R
Reset 0 0
21.1 Features
• 16-Bit Timer/Counter
• Three Compare Channels
• Double-Buffered Timer Period Setting
• Double-Buffered Compare Channels
• Waveform Generation:
– Frequency generation
– Single-slope PWM (Pulse-Width Modulation)
– Dual-slope PWM
• Count on Event
• Timer Overflow Interrupts/Events
• One Compare Match per Compare Channel
• Two 8-Bit Timer/Counters in Split Mode
21.2 Overview
The flexible 16-bit PWM Timer/Counter type A (TCA) provides accurate program execution timing, frequency and
waveform generation, and command execution.
A TCA consists of a base counter and a set of compare channels. The base counter can be used to count clock
cycles or events, or let events control how it counts clock cycles. It has direction control and period setting that can
be used for timing. The compare channels can be used together with the base counter to do compare match control,
frequency generation, and pulse-width waveform modulation.
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each timer/
counter clock or event input.
A timer/counter can be clocked and timed from the peripheral clock, with optional prescaling, or from the Event
System. The Event System can also be used for direction control or to synchronize operations.
By default, the TCA is a 16-bit timer/counter. The timer/counter has a Split mode feature that splits it into two 8-bit
timer/counters with three compare channels each.
A block diagram of the 16-bit timer/counter with closely related peripheral modules (in grey) is shown in the figure
below.
Timer/Counter
Base Counter Prescaler
CLK_PER
Timer Period
Control Logic
Counter Event
System
Compare Channel 0
Compare Channel 1
PORTS
Compare Channel 2
Comparator
Waveform
Buffer Generation
Base Counter
Clock Select
CTRL A
BV PERBUF
Mode
CTRL B
Event
PER Action
EVCTRL
‘‘count’’
Counter
‘‘clear’’
OVF
(INT Req. and Event)
‘‘load’’
CNT Control Logic
‘‘direction’’
Event
TOP
UPDATE
=
BOTTOM
=0
Compare Unit n
CMPn
Waveform
Generation
WOn Out
‘‘match’’ CMPn
= (INT Req. and Event)
The Counter (TCAn.CNT) register, Period and Compare (TCAn.PER and TCAn.CMPn) registers, and their
corresponding buffer registers (TCAn.PERBUF and TCAn.CMPnBUF) are 16-bit registers. All buffer registers have a
Buffer Valid (BV) flag that indicates when the buffer contains a new value.
During normal operation, the counter value is continuously compared to zero and the period (PER) value to
determine whether the counter has reached TOP or BOTTOM. The counter value can also be compared to the
TCAn.CMPn registers.
The timer/counter can generate interrupt requests, events, or change the waveform output after being triggered by
the Counter (TCAn.CNT) register reaching TOP, BOTTOM, or CMPn. The interrupt requests, events, or waveform
output changes will occur on the next CLK_TCA cycle after the triggering.
CLK_TCA is either the prescaled peripheral clock or events from the Event System, as shown in the figure below.
Figure 21-3. Timer/Counter Clock Logic
Event
CLKSEL
EVACT (Encoding)
CLK_TCA
CNT
CNTxEI
21.3.1 Definitions
The following definitions are used throughout the documentation:
Table 21-1. Timer/Counter Definitions
Name Description
BOTTOM The counter reaches BOTTOM when it becomes 0x0000.
MAX The counter reaches MAXimum when it becomes all ones.
TOP The counter reaches TOP when it becomes equal to the highest value in the count sequence.
The update condition is met when the timer/counter reaches BOTTOM or TOP, depending on the
UPDATE Waveform Generator mode. Buffered registers with valid buffer values will be updated unless the Lock
Update (LUPD) bit in the TCAn.CTRLE register has been set.
...........continued
Name Description
CNT Counter register value.
CMP Compare register value.
PER Period register value.
In general, the term timer is used when the timer/counter is counting periodic clock ticks. The term counter is used
when the input signal has sporadic or irregular ticks. The latter can be the case when counting events.
21.3.2 Initialization
To start using the timer/counter in a basic mode, follow these steps:
1. Write a TOP value to the Period (TCAn.PER) register.
2. Enable the peripheral by writing a ‘1’ to the ENABLE bit in the Control A (TCAn.CTRLA) register.
The counter will start counting clock ticks according to the prescaler setting in the Clock Select (CLKSEL) bit
field in the TCAn.CTRLA register.
3. Optional: By writing a ‘1’ to the Enable Count on Event Input (CNTEI) bit in the Event Control (TCAn.EVCTRL)
register, events are counted instead of clock ticks.
4. The counter value can be read from the Counter (CNT) bit field in the Counter (TCAn.CNT) register.
21.3.3 Operation
MAX
‘‘update’’
TOP
CNT
BOTTOM
DIR
It is possible to change the counter value in the Counter (TCAn.CNT) register when the counter is running. The write
access to TCAn.CNT has higher priority than count, clear or reload, and will be immediate. The direction of the
counter can also be changed during normal operation by writing to DIR in TCAn.CTRLE.
BV EN CMPnBUF
EN CMPn
UPDATE
CNT
‘‘match’’
=
Both the TCAn.CMPn and TCAn.CMPnBUF registers are available as I/O registers. This allows initialization and
bypassing of the buffer register and the double-buffering function.
BOTTOM
New TOP written to New TOP written to
PER that is higher PER that is lower
than current CNT. than current CNT.
A counter wrap-around can occur in any mode of operation when counting up without buffering, as the TCAn.CNT
and TCAn.PER registers are continuously compared. If a new TOP value is written to TCAn.PER that is lower than
the current TCAn.CNT, the counter will wrap first, before a compare match occurs.
Figure 21-7. Unbuffered Dual-Slope Operation
Counter wrap-around
MAX
‘‘update’’
‘‘write’’
CNT
BOTTOM
With Buffering: When double-buffering is used, the buffer can be written at any time and still maintain correct
operation. The TCAn.PER is always updated on the UPDATE condition, as shown for dual-slope operation in the
figure below. This prevents wrap-around and the generation of odd waveforms.
MAX
‘‘update’’
‘‘write’’
CNT
BOTTOM
New Period written to New Period written to
New PER is updated
PERB that is higher PERB that is lower
with PERB value.
than current CNT. than current CNT.
Note: Buffering is used in figures illustrating TCA operation if not otherwise specified.
CNT TOP
BOTTOM
WG Output
The waveform frequency (fFRQ) is defined by the following equation:
f CLK_PER
�FRQ =
2� CMPn+1
where N represents the prescaler divider used (see the CLKSEL bit field in the TCAn.CTRLA register), and fCLK_PER
is the peripheral clock frequency.
The maximum frequency of the waveform generated is half of the peripheral clock frequency (fCLK_PER/2) when
TCAn.CMP0 is written to 0x0000 and no prescaling is used (N = 1, CLKSEL = 0x0 in TCAn.CTRLA).
CNT
CMPn
BOTTOM
Output WOn
The TCAn.PER register defines the PWM resolution. The minimum resolution is 2 bits (TCAn.PER = 0x0002), and
the maximum resolution is 16 bits (TCAn.PER = MAX-1).
The following equation calculates the exact resolution in bits for single-slope PWM (RPWM_SS):
log PER+2
�PWM_SS =
log 2
The single-slope PWM frequency (fPWM_SS) depends on the period setting (TCAn.PER), the peripheral clock
frequency fCLK_PER and the TCA prescaler (the CLKSEL bit field in the TCAn.CTRLA register). It is calculated by the
following equation where N represents the prescaler divider used:
�CLK_PER
�PWM_SS =
� PER+1
CMPn
CNT TOP
BOTTOM
Using dual-slope PWM results in half the maximum operation frequency compared to single-slope PWM operation,
due to twice the number of timer increments per period.
The Period (TCAn.PER) register defines the PWM resolution. The minimum resolution is 2 bits (TCAn.PER =
0x0003), and the maximum resolution is 16 bits (TCAn.PER = MAX).
The following equation calculates the exact resolution in bits for dual-slope PWM (RPWM_DS):
log PER+1
�PWM_DS =
log 2
The PWM frequency depends on the period setting in the TCAn.PER register, the peripheral clock frequency
(fCLK_PER) and the prescaler divider selected in the CLKSEL bit field in the TCAn.CTRLA register. It is calculated by
the following equation:
�CLK_PER
�PWM_DS =
2� ⋅ PER
N represents the prescaler divider used.
OUT
Waveform WOn
CMPnEN INVEN
A RESET command will set all timer/counter registers to their initial values. A RESET command can be issued only
when the timer/counter is not running (ENABLE = 0 in the TCAn.CTRLA register).
Block Diagram
Figure 21-13. Timer/Counter Block Diagram Split Mode
‘‘
‘‘
‘‘
Control Logic
‘‘
‘‘
‘‘
21.3.4 Events
The TCA can generate the events described in the table below. All event generators except TCAn_HUNF are shared
between Normal mode and Split mode operation.
Note: The conditions for generating an event are identical to those that will raise the corresponding interrupt flag in
the TCAn.INTFLAGS register for both Normal mode and Split mode.
The TCA has one event user for detecting and acting upon input events. The table below describes the event user
and the associated functionality.
Table 21-3. Event User in TCA
The specific actions described in the table above are selected by writing to the Event Action Event Action (EVACT)
bits in the Event Control (TCAn.EVCTRL) register. Input events are enabled by writing a ‘1’ to the Enable Count on
Event Input (CNTEI) bit in the Event Control (TCAn.EVCTRL) register.
Event inputs are not used in Split mode.
Refer to the Event System (EVSYS) chapter for more details regarding event types and Event System configuration.
21.3.5 Interrupts
Table 21-4. Available Interrupt Vectors and Sources in Normal Mode
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
21.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CLKSEL[2:0] ENABLE
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMP2EN CMP1EN CMP0EN ALUPD WGMODE[2:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Note:
1. When counting up.
Name: CTRLC
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMP2OV CMP1OV CMP0OV
Access R/W R/W R/W
Reset 0 0 0
21.5.4 Control D
Name: CTRLD
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SPLITM
Access R/W
Reset 0
Name: CTRLECLR
Offset: 0x04
Reset: 0x00
Property: -
This register can be used instead of a Read-Modify-Write (RMW) to clear individual bits by writing a ‘1’ to its bit
location.
Bit 7 6 5 4 3 2 1 0
CMD[1:0] LUPD DIR
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: CTRLESET
Offset: 0x05
Reset: 0x00
Property: -
This register can be used instead of a Read-Modify-Write (RMW) to set individual bits by writing a ‘1’ to its bit
location.
Bit 7 6 5 4 3 2 1 0
CMD[1:0] LUPD DIR
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: CTRLFCLR
Offset: 0x06
Reset: 0x00
Property: -
This register can be used instead of a Read-Modify-Write (RMW) to clear individual bits by writing a ‘1’ to its bit
location.
Bit 7 6 5 4 3 2 1 0
CMP2BV CMP1BV CMP0BV PERBV
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: CTRLFSET
Offset: 0x07
Reset: 0x00
Property: -
This register can be used instead of a Read-Modify-Write (RMW) to set individual bits by writing a ‘1’ to its bit
location.
Bit 7 6 5 4 3 2 1 0
CMP2BV CMP1BV CMP0BV PERBV
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: EVCTRL
Offset: 0x09
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
EVACT[2:0] CNTEI
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTCTRL
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMP2 CMP1 CMP0 OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTFLAGS
Offset: 0x0B
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMP2 CMP1 CMP0 OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: DBGCTRL
Offset: 0x0E
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: TEMP
Offset: 0x0F
Reset: 0x00
Property: -
The Temporary register is used by the CPU for 16-bit single-cycle access to the 16-bit registers of this peripheral. The
register is common for all the 16-bit registers of this peripheral and can be read and written by software. For more
details on reading and writing 16-bit registers, refer to Accessing 16-Bit Registers in the AVR CPU section.
Bit 7 6 5 4 3 2 1 0
TEMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CNT
Offset: 0x20
Reset: 0x00
Property: -
The TCAn.CNTL and TCAn.CNTH register pair represents the 16-bit value, TCAn.CNT. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
CPU and UPDI write access has priority over internal updates of the register.
Bit 15 14 13 12 11 10 9 8
CNT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: PER
Offset: 0x26
Reset: 0xFFFF
Property: -
TCAn.PER contains the 16-bit TOP value in the timer/counter in all modes of operation, except Frequency Waveform
Generation (FRQ).
The TCAn.PERL and TCAn.PERH register pair represents the 16-bit value, TCAn.PER. The low byte [7:0] (suffix L)
is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit 15 14 13 12 11 10 9 8
PER[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
PER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Name: CMPn
Offset: 0x28 + n*0x02 [n=0..2]
Reset: 0x00
Property: -
This register is continuously compared to the counter value. Normally, the outputs from the comparators are used to
generate waveforms.
TCAn.CMPn registers are updated with the buffer value from their corresponding TCAn.CMPnBUF register when an
UPDATE condition occurs.
The TCAn.CMPnL and TCAn.CMPnH register pair represents the 16-bit value, TCAn.CMPn. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit 15 14 13 12 11 10 9 8
CMP[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: PERBUF
Offset: 0x36
Reset: 0xFFFF
Property: -
This register serves as the buffer for the Period (TCAn.PER) register. Writing to this register from the CPU or UPDI
will set the Period Buffer Valid (PERBV) bit in the TCAn.CTRLF register.
The TCAn.PERBUFL and TCAn.PERBUFH register pair represents the 16-bit value, TCAn.PERBUF. The low byte
[7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit 15 14 13 12 11 10 9 8
PERBUF[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
PERBUF[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Name: CMPnBUF
Offset: 0x38 + n*0x02 [n=0..2]
Reset: 0x00
Property: -
This register serves as the buffer for the associated Compare n (TCAn.CMPn) register. Writing to this register from
the CPU or UPDI will set the Compare Buffer valid (CMPnBV) bit in the TCAn.CTRLF register.
The TCAn.CMPnBUFL and TCAn.CMPnBUFH register pair represents the 16-bit value, TCAn.CMPnBUF. The low
byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset
+ 0x01.
Bit 15 14 13 12 11 10 9 8
CMPBUF[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CMPBUF[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
21.7.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CLKSEL[2:0] ENABLE
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
HCMP2EN HCMP1EN HCMP0EN LCMP2EN LCMP1EN LCMP0EN
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: CTRLC
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
HCMP2OV HCMP1OV HCMP0OV LCMP2OV LCMP1OV LCMP0OV
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
21.7.4 Control D
Name: CTRLD
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SPLITM
Access R/W
Reset 0
Name: CTRLECLR
Offset: 0x04
Reset: 0x00
Property: -
This register can be used instead of a Read-Modify-Write (RMW) to clear individual bits by writing a ‘1’ to its bit
location.
Bit 7 6 5 4 3 2 1 0
CMD[1:0] CMDEN[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: CTRLESET
Offset: 0x05
Reset: 0x00
Property: -
This register can be used instead of a Read-Modify-Write (RMW) to set individual bits by writing a ‘1’ to its bit
location.
Bit 7 6 5 4 3 2 1 0
CMD[1:0] CMDEN[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTCTRL
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
LCMP2 LCMP1 LCMP0 HUNF LUNF
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: INTFLAGS
Offset: 0x0B
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
LCMP2 LCMP1 LCMP0 HUNF LUNF
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: DBGCTRL
Offset: 0x0E
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: LCNT
Offset: 0x20
Reset: 0x00
Property: -
TCAn.LCNT contains the counter value for the low byte timer. CPU and UPDI write access has priority over count,
clear or reload of the counter.
Bit 7 6 5 4 3 2 1 0
LCNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: HCNT
Offset: 0x21
Reset: 0x00
Property: -
TCAn.HCNT contains the counter value for the high byte timer. CPU and UPDI write access has priority over count,
clear or reload of the counter.
Bit 7 6 5 4 3 2 1 0
HCNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: LPER
Offset: 0x26
Reset: 0xFF
Property: -
The TCAn.LPER register contains the TOP value for the low byte timer.
Bit 7 6 5 4 3 2 1 0
LPER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Name: HPER
Offset: 0x27
Reset: 0xFF
Property: -
The TCAn.HPER register contains the TOP value for the high byte timer.
Bit 7 6 5 4 3 2 1 0
HPER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Name: LCMPn
Offset: 0x28 + n*0x02 [n=0..2]
Reset: 0x00
Property: -
The TCAn.LCMPn register represents the compare value of Compare Channel n for the low byte timer. This register
is continuously compared to the counter value of the low byte timer, TCAn.LCNT. Normally, the outputs from the
comparators are then used to generate waveforms.
Bit 7 6 5 4 3 2 1 0
LCMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: HCMPn
Offset: 0x29 + n*0x02 [n=0..2]
Reset: 0x00
Property: -
The TCAn.HCMPn register represents the compare value of Compare Channel n for the high byte timer. This register
is continuously compared to the counter value of the high byte timer, TCAn.HCNT. Normally, the outputs from the
comparators are then used to generate waveforms.
Bit 7 6 5 4 3 2 1 0
HCMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
22.1 Features
• 16-bit Counter Operation Modes:
– Periodic interrupt
– Time-out check
– Input capture
• On event
• Frequency measurement
• Pulse-width measurement
• Frequency and pulse-width measurement
– Single-shot
– 8-bit Pulse-Width Modulation (PWM)
• Noise Canceler on Event Input
• Synchronize Operation with TCAn
22.2 Overview
The capabilities of the 16-bit Timer/Counter type B (TCB) include frequency and waveform generation, and input
capture on event with time and frequency measurement of digital signals. The TCB consists of a base counter and
control logic that can be set in one of eight different modes, each mode providing unique functionality. The base
counter is clocked by the peripheral clock with optional prescaling.
Clock Select
CTRLA
Mode
CTRLB
Event Action
EVCTRL
Count Events
Counter
Control
Clear
CNT Logic CAPT
(Interrupt Request
and Events)
BOTTOM
=0
CCMP
Waveform
Match WO
= Generation
The timer/counter can be clocked from the Peripheral Clock (CLK_PER), or a 16-bit Timer/Counter type A
(CLK_TCAn).
Figure 22-2. Timer/Counter Clock Logic
CTRLA
CLK_PER
DIV2 CLK_TCB
CLK_TCAn CNT
Control
Events Logic
The Clock Select (CLKSEL) bit field in the Control A (TCBn.CTRLA) register selects one of the prescaler outputs
directly as the clock (CLK_TCB) input.
Setting the timer/counter to use the clock from a TCAn allows the timer/counter to run in sync with that TCAn.
By using the EVSYS, any event source, such as an external clock signal on any I/O pin, may be used as a control
logic input. When an event action controlled operation is used, the clock selection must be set to use an event
channel as the counter input.
22.3.1 Definitions
The following definitions are used throughout the documentation:
Table 22-1. Timer/Counter Definitions
Name Description
BOTTOM The counter reaches BOTTOM when it becomes 0x0000
MAX The counter reaches maximum when it becomes 0xFFFF
TOP The counter reaches TOP when it becomes equal to the highest value in the count sequence
CNT Counter register value
CCMP Capture/Compare register value
Note: In general, the term ‘timer’ is used when the timer/counter is counting periodic clock ticks. The term ‘counter’
is used when the input signal has sporadic or irregular ticks.
22.3.2 Initialization
By default, the TCB is in Periodic Interrupt mode. Follow these steps to start using it:
1. Write a TOP value to the Compare/Capture (TCBn.CCMP) register.
2. Optional: Write the Compare/Capture Output Enable (CCMPEN) bit in the Control B (TCBn.CTRLB) register
to‘1’. This will make the waveform output available on the corresponding pin, overriding the value in the
corresponding PORT output register.
3. Enable the counter by writing a ‘1’ to the ENABLE bit in the Control A (TCBn.CTRLA) register.
The counter will start counting clock ticks according to the prescaler setting in the Clock Select (CLKSEL) bit
field in the Control A (TCBn.CTRLA) register.
4. The counter value can be read from the Count (TCBn.CNT) register. The peripheral will generate a CAPT
interrupt and event when the CNT value reaches TOP.
4.1. If the Compare/Capture register is modified to a value lower than the current Count register, the
peripheral will count to MAX and wrap around.
22.3.3 Operation
22.3.3.1 Modes
The timer can be configured to run in one of the eight different modes described in the sections below. The event
pulse needs to be longer than one system clock cycle in order to ensure edge detection.
MAX CAPT
(Interrupt Request
and Event)
TOP
CNT
BOTTOM
TOP changed to
CNT set to BOTTOM
a value lower than CNT
Event Detector
MAX
TOP
CNT
BOTTOM
TOP changed to a value lower CNT set to
than CNT BOTTOM
The figure below shows the input capture unit configured to capture on the falling edge of the event input signal. The
CAPT Interrupt flag is automatically cleared after the low byte of the Compare/Capture (TCBn.CCMP) register has
been read.
Figure 22-5. Input Capture on Event
Event Detector
MAX
CNT
BOTTOM
It is recommended to write zero to the TCBn.CNT register when entering this mode from any other mode.
CAPT
Event Input (Interrupt Request
and Event)
Event Detector
MAX
CNT
BOTTOM
Copy CNT to CCMP, CNT set to Copy CNT to CCMP,
CAPT and restart BOTTOM CAPT and restart
Edge Detector
MAX
CNT
BOTTOM
CAPT
(Interrupt Request
Event Input and Event)
Event Detector
MAX
CNT
BOTTOM
Start Copy CNT to Stop counter and CPU reads the
counter CCMP CAPT CCMP register
Edge Detector
TOP
CNT
BOTTOM
Output
CAPT
Period (T) CCMPH=BOTTOM CCMPH=TOP CCMPH>TOP (Interrupt Request
and Event)
MAX
TOP
CCMPL
CNT
CCMPH
BOTTOM
Output
22.3.3.2 Output
Timer synchronization and output logic level are dependent on the selected Timer Mode (CNTMODE) bit field in
Control B (TCBn.CTRLB) register. In Single-Shot mode the timer/counter can be configured so that the signal
generation happens asynchronously to an incoming event (ASYNC = 1 in TCBn.CTRLB). The output signal is then
set immediately at the incoming event instead of being synchronized to the TCB clock. Even though the output is set
immediately, it will take two to three CLK_TCB cycles before the counter starts counting.
Writing the Compare/Capture Output Enable (CCMPEN) bit in TCBn.CTRLB to ‘1’ enables the waveform output. This
will make the waveform output available on the corresponding pin, overriding the value in the corresponding PORT
output register.
The different configurations and their impact on the output are listed in the table below.
Table 22-2. Output Configuration
It is not recommended to change modes while the peripheral is enabled as this can produce an unpredictable output.
There is a possibility that an interrupt flag is set during the timer configuration. It is recommended to clear the Timer/
Counter Interrupt Flags (TCBn.INTFLAGS) register after configuring the peripheral.
22.3.4 Events
The TCB can generate the events described in the following table:
Table 22-3. Event Generators in TCB
Generator Name
Description Event Type Generating Clock Domain Length of Event
Peripheral Event
TCBn CAPT CAPT flag set Pulse CLK_PER One CLK_PER period
The conditions for generating the CAPT event is identical to those that will raise the corresponding interrupt flag in
the Timer/Counter Interrupt Flags (TCBn.INTFLAGS) register. Refer to the Event System section for more details
regarding event users and Event System configuration.
The TCB can receive the events described in the following table:
Table 22-4. Event Users and Available Event Actions in TCB
User Name
Description Input Detection Async/Sync
Peripheral Input
Time-Out Check Count mode
Input Capture on Event Count mode
Input Capture Frequency Measurement Count mode
Sync
TCBn CAPT Input Capture Pulse-Width Measurement Count mode Edge
If the Capture Event Input Enable (CAPTEI) bit in the Event Control (TCBn.EVCTRL) register is written to ‘1’,
incoming events will result in an event action as defined by the Event Edge (EDGE) bit in Event Control
(TCBn.EVCTRL) register and the Timer Mode (CNTMODE) bit field in Control B (TCBn.CTRLB) register. The event
needs to last for at least one CLK_PER cycle to be recognized.
If the Asynchronous mode is enabled for Single-Shot mode, the event is edge-triggered and will capture changes on
the event input shorter than one system clock cycle.
22.3.5 Interrupts
Table 22-5. Available Interrupt Vectors and Sources
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
22.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUNSTDBY SYNCUPD CLKSEL[1:0] ENABLE
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
22.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ASYNC CCMPINIT CCMPEN CNTMODE[2:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: EVCTRL
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
FILTER EDGE CAPTEI
Access R/W R/W R/W
Reset 0 0 0
Name: INTCTRL
Offset: 0x05
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CAPT
Access R/W
Reset 0
Name: INTFLAGS
Offset: 0x06
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CAPT
Access R/W
Reset 0
TOP
Counter Mode Interrupt Set Condition CAPT
Value
Periodic Interrupt mode Set when the counter reaches TOP
Timeout Check mode Set when the counter reaches TOP CCMP CNT == TOP
Single-Shot mode Set when the counter reaches TOP
On Event, copy CNT to
Set on edge when the Capture register is
Input Capture Frequency CCMP, and restart
loaded and the counter restarts; the flag clears
Measurement mode counting (CNT ==
when the capture is read
BOTTOM)
Set when an event occurs and the Capture
Input Capture on Event
register is loaded; the flag clears when the
mode
capture is read --
Set on edge when the Capture register is On Event, copy CNT to
Input Capture Pulse-Width
loaded; the previous edge initialized the count; CCMP, and continue
Measurement mode
the flag clears when the capture is read counting
Input Capture Frequency Set on the second edge (positive or negative)
and Pulse-Width when the counter is stopped; the flag clears
Measurement mode when the capture is read
8-Bit PWM mode Set when the counter reaches CCML CCML CNT == CCML
22.5.6 Status
Name: STATUS
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUN
Access R
Reset 0
Name: DBGCTRL
Offset: 0x08
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: TEMP
Offset: 0x09
Reset: 0x00
Property: -
The Temporary register is used by the CPU for 16-bit single-cycle access to the 16-bit registers of this peripheral. The
register is common for all the 16-bit registers of this peripheral and can be read and written by software. For more
details on reading and writing 16-bit registers, refer to Accessing 16-Bit Registers in the AVR CPU section.
Bit 7 6 5 4 3 2 1 0
TEMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
22.5.9 Count
Name: CNT
Offset: 0x0A
Reset: 0x00
Property: -
The TCBn.CNTL and TCBn.CNTH register pair represents the 16-bit value TCBn.CNT. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
CPU and UPDI write access has priority over internal updates of the register.
Bit 15 14 13 12 11 10 9 8
CNT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
22.5.10 Capture/Compare
Name: CCMP
Offset: 0x0C
Reset: 0x00
Property: -
The TCBn.CCMPL and TCBn.CCMPH register pair represents the 16-bit value TCBn.CCMP. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
This register has different functions depending on the mode of operation:
• For Capture operation, these registers contain the captured value of the counter at the time the capture occurs
• In Periodic Interrupt/Time-Out and Single-Shot mode, this register acts as the TOP value
• In 8-bit PWM mode, TCBn.CCMPL and TCBn.CCMPH act as two independent registers: The period of the
waveform is controlled by CCMPL, while CCMPH controls the duty cycle.
Bit 15 14 13 12 11 10 9 8
CCMP[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CCMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
23.1 Features
• 12-bit Timer/Counter
• Programmable Prescaler
• Double-Buffered Compare Registers
• Waveform Generation:
– One Ramp mode
– Two Ramp mode
– Four Ramp mode
– Dual Slope mode
• Two Separate Input Channels
• Software and Input Based Capture
• Programmable Filter for Input Events
• Conditional Waveform Generation on External Events:
– Fault handling
– Input blanking
– Overload protection
– Fast emergency stop by hardware
• Half-Bridge and Full-Bridge Output Support
23.2 Overview
The Timer/Counter type D (TCD) is a high-performance waveform generator that consists of an asynchronous
counter, a prescaler, and compare, capture and control logic.
The TCD contains a counter that can run on a clock which is asynchronous to the peripheral clock. It contains
compare logic that generates two independent outputs with optional dead time. It is connected to the Event System
for capture and deterministic Fault control. The timer/counter can generate interrupts and events on compare match
and overflow.
This device provides one instance of the TCD peripheral, TCD0.
Compare/Capture
CMPASET_
CMPASET Unit A
BUF
= CMPASET/PROGEV
SET A (Event)
CMPACLR_ Waveform
CMPACLR WOA
BUF generator A
CLR A
= PROGEV (Event)
Event Input A Event Input
Logic A
Compare/Capture WOD
CMPBSET_
CMPBSET Unit B
BUF
= CMPBSET/PROGEV
SET B (Event)
CMPBCLR_ Waveform
CMPBCLR WOB
BUF generator B
CLR B
= CMPBCLR/PROGEV
Event Input (Event)
Event Input B Logic B TRIG OVF (INT Req.)
CAPTUREB_
CAPTUREB
BUF TRIGB (INT Req.)
The TCD core is asynchronous to the peripheral clock. The timer/counter consists of two compare/capture units,
each with a separate waveform output. There are also two extra waveform outputs which can be equal to the output
from one of the units. For each compare/capture unit, there is a pair of compare registers which are stored in the
respective peripheral registers (TCDn.CMPASET, TCDn.CMPACLR, TCDn.CMPBSET, TCDn.CMPBCLR).
During normal operation, the counter value is continuously compared to the compare registers. This is used to
generate both interrupts and events.
The TCD can use the input events in ten different input modes, selected separately for the two input events. The
input mode defines how the input events will affect the outputs, and where in the TCD cycle the counter must go
when an event occurs.
The TCD can select between four different clock sources that can be prescaled. There are three different prescalers
with separate controls, as shown below.
Figure 23-2. Clock Selection and Prescalers Overview
CLKSEL
Counter Counter clock
prescaler (CLK_TCD_CNT)
OSCHF
PLL Synchronization Synchronizer clock
EXTCLK CLK_TCD prescaler (CLK_TCD_SYNC)
CLK_PER
The TCD synchronizer clock is separate from the other module clocks, enabling faster synchronization between the
TCD domain and the I/O domain.
The total prescaling for the counter is:
SYNCPRESC_division_factor × CNTPRESC_division_factor
The delay prescaler is used to prescale the clock used for the input blanking/delayed event output functionality. The
prescaler can be configured independently allowing separate range and accuracy settings from the counter
functionality. The synchronization prescaler and counter prescaler can be configured from the Control A
(TCDn.CTRLA) register, while the delay prescaler can be configured from the Delay Control (TCDn.DLYCTRL)
register.
23.3.1 Definitions
The following definitions are used throughout the documentation:
Table 23-1. Timer/Counter Definitions
Name Description
TCD cycle The sequence of four states that the counter needs to go through before it has returned to the
same position.
...........continued
Name Description
Input blanking The functionality to ignore an event input for a programmable time in a selectable part of the TCD
cycle.
Asynchronous Allows the event to override the output instantly when an event occurs. It is used for handling
output control non-recoverable Faults.
One ramp The counter is reset to zero once during a TCD cycle.
Two ramp The counter is reset to zero two times during a TCD cycle.
Four ramp The counter is reset to zero four times during a TCD cycle.
Dual ramp The counter counts both up and down between zero and a selected top value during a TCD
cycle.
Input mode A predefined setting that changes the output characteristics, based on the given input events.
23.3.2 Initialization
To initialize the TCD:
1. Select the clock source and the prescaler from the Control A (TCDn.CTRLA) register.
2. Select the Waveform Generation Mode from the Control B (TCDn.CTRLB) register.
3. Optional: Configure the other static registers to the desired functionality.
4. Write the initial values in the Compare (TCDn.CMPxSET/CLR) registers.
5. Optional: Write the desired values to the other double-buffered registers.
6. Ensure that the Enable Ready (ENRDY) bit in the Status (TCDn.STATUS) register is set to ‘1’.
7. Enable the TCD by writing a ‘1’ to the ENABLE bit in the Control A (TCDn.CTRLA) register.
23.3.3 Operation
Notes:
1. The bits in the Control A (TCDn.CTRLA) register are enable-protected, except the ENABLE bit. They can only
be written when ENABLE is written to ‘0’ first.
2. This register is protected by the Configuration Change Protection Mechanism, requiring a timed write
procedure for changing its value settings.
Double-Buffered Registers
The double-buffered registers can be updated in normal I/O writes, while TCD is enabled and no synchronization
between the two clock domains is ongoing. Check that the CMDRDY bit in TCDn.STATUS is ‘1’ to ensure that it is
possible to update the double-buffered registers. The values will be synchronized to the TCD core domain when a
synchronization command is sent or when TCD is enabled.
Table 23-3. Issuing Synchronization Command
Note:
1. If synchronization is already ongoing, the action has no effect.
Static Registers
Static registers cannot be updated while TCD is enabled. Therefore, these registers must be configured before
enabling TCD. To see if TCD is enabled, check if ENABLE in TCDn.CTRLA is read as ‘1’.
Counter
Compare
value
values
CMPBCLR
CMPBSET
CMPACLR
CMPASET
WOA
WOB
In the figure above, CMPASET < CMPACLR < CMPBSET < CMPBCLR. In One Ramp mode, this is required to avoid
overlapping outputs during the on time. The figure below is an example where CMPBSET < CMPASET < CMPACLR
< CMPBCLR, which has overlapping outputs during the on time.
Compare Counter
values value
CMPBCLR
CMPACLR
CMPASET
CMPBSET
WOA
WOB
A match with CMPBCLR will always result in all outputs being cleared. If any of the other compare values are bigger
than CMPBCLR, their associated effect will never occur. If the CMPACLR is smaller than the CMPASET value, the
clear value will not have any effect.
Counter
value
CMPBCLR
CMPACLR
CMPBSET
CMPASET
WOA
WOB
In the figure above, CMPASET < CMPACLR and CMPBSET < CMPBCLR. This causes the outputs to go high. There
are no restrictions on the CMPASET and CMPACLR compared to the CMPBSET and CMPBCLR values.
In Two Ramp mode, it is not possible to get overlapping outputs without using the override feature. Even if
CMPASET/CMPBSET > CMPACLR/CMPBCLR, the counter resets at CMPACLR/CMPBCLR and will never reach
CMPASET/CMPBSET.
Counter
value
CMPBCLR
CMPACLR CMPBSET
CMPASET
WOA
WOB
There are no restrictions regarding the compare values, because there are no dependencies between them.
In Four Ramp mode, it is not possible to get overlapping outputs without using the override feature.
Counter
CMPBCLR value
CMPBSET
CMPASET
WOA
WOB
When starting the TCD in Dual Slope mode, the TCD counter starts at the CMPBCLR value and counts down. In the
first cycle, the WOB will not be set until the TCD counter matches the CMPBSET value when counting up.
When the Disable at End of Cycle Strobe (DISEOC) bit in the Control E (TCDn.CTRLE) register is set, the TCD will
automatically be disabled at the end of the TCD cycle.
Figure 23-8. Dual Slope Mode Starting and Stopping
TCD cycle
Counter
CMPBCLR value
CMPBSET
CMPASET
WOA
WOB
Start Stop
EVCTRLA.FILTER Synchronized
Change flow override
DLYPRESC INPUT
MODE
DLYTRIG
DLYSEL TC Core
Output state (Timer/Counter,
Output
compare values,
control
waveform generator)
INPUT
MODE
Synchronized
Change flow
override
EVCTRLB.FILTER
Digital
Input processing logic
Filter
Input Event B (Input mode logic B)
There is a delay of two/three clock cycles on the TCD synchronizer clock between receiving the input event,
processing it, and overriding the outputs. If using the asynchronous event detection, the outputs will override instantly
outside the input processing.
Input blanking uses the same logic as the programmable output event. For this reason, it is not possible to use both
at the same time.
The asynchronous event detection makes it possible to asynchronously override the output when the input event
occurs. What the input event will do depends on the input mode. The outputs have direct override while the counter
flow will be changed when the event is synchronized to the synchronizer clock (CLK_TCD_SYNC).
It is not possible to use asynchronous event detection and digital filter at the same time.
INPUTMODE One Ramp Mode Two Ramp Mode Four Ramp Mode Dual Slope Mode
0 Valid Valid Valid Valid
1 Valid Valid Valid Do not use
2 Do not use Valid Valid Do not use
3 Do not use Valid Valid Do not use
4 Valid Valid Valid Valid
5 Do not use Valid Valid Do not use
6 Do not use Valid Valid Do not use
7 Valid Valid Valid Valid
8 Valid Valid Valid Do not use
9 Valid Valid Valid Do not use
10 Valid Valid Valid Do not use
WOA
WOB
INPUT A
INPUT B
Input Mode 1: Stop Output, Jump to Opposite Compare Cycle, and Wait
An input event in Input mode 1 will stop the output signal, jump to the opposite dead time, and wait until the input
event goes low before the TCD counter continues.
If Input mode 1 is used on input A, an event will only have an effect if the TCD is in dead time A or on time A, and it
will only affect the WOA output. When the event is done, the TCD counter starts at dead time B.
Figure 23-11. Input Mode 1 on Input A
DTA OTA DTB OTB DTA OTA Wait DTB OTB DTA OTA
WOA
WOB
INPUT A
INPUT B
If Input mode 1 is used on input B, an event will only have an effect if the TCD is in dead time B or on time B, and it
will only affect the WOB output. When the event is done, the TCD counter starts at dead time A.
Figure 23-12. Input Mode 1 on Input B
DTA OTA DTB OTB Wait DTA OTA DTB OTB DTA OTA
WOA
WOB
INPUT A
INPUT B
Input Mode 2: Stop Output, Execute Opposite Compare Cycle, and Wait
An input event in Input mode 2 will stop the output signal, execute to the opposite dead time and on time, and then
wait until the input event goes low before the TCD counter continues. If the input is done before the opposite dead
time and on time have finished, there will be no waiting, but the opposite dead time and on time will continue.
If Input mode 2 is used on input A, an event will only have an effect if the TCD is in dead time A or on time A, and will
only affect the WOA output.
WOA
WOB
INPUT A
INPUT B
If Input mode 2 is used on input B, an event will only have an effect if the TCD is in dead time B or on time B, and it
will only affect the WOB output.
Figure 23-14. Input Mode 2 on Input B
DTA OTA DTB OTB DTA OTA Wait DTB OTB DTA OTA
WOA
WOB
INPUT A
INPUT B
Input Mode 3: Stop Output, Execute Opposite Compare Cycle while Fault Active
An input event in Input mode 3 will stop the output signal and start executing the opposite dead time and on time
repetitively, as long as the Fault/input is active. When the input is released, the ongoing dead time and/or on time will
finish, and then the normal flow will start.
If Input mode 3 is used on input A, an event will only have an effect if the TCD is in dead time A or on time A.
Figure 23-15. Input Mode 3 on Input A
DTA OTA DTB OTB DTA OTA DTB OTB DTB OTB DTA OTA
WOA
WOB
INPUT A
INPUT B
If Input mode 3 is used on input B, an event will only have an effect if the TCD is in dead time B or on time B.
WOA
WOB
INPUT A
INPUT B
Input Mode 4: Stop all Outputs, Maintain Frequency
When Input mode 4 is used, both input A and input B will give the same functionality. An input event will deactivate
the outputs as long as the event is active. The TCD counter will not be affected by events in this input mode.
Figure 23-17. Input Mode 4
DTA OTA DTB OTB DTA OTA DTB OTB DTA OTA DTB OTB
WOA
WOB
INPUT A/B
Input Mode 5: Stop all Outputs, Execute Dead Time while Fault Active
When Input mode 5 is used, both input A and input B give the same functionality. The input event stops the outputs
and starts on the opposite dead time if it occurs during an on time. If the event occurs during dead time, the dead
time will continue until the next on time is scheduled to start. Though, if the input is still active, the cycle will continue
with the other dead time. As long as the input event is active, alternating dead times will occur. When the input event
stops, the ongoing dead time will finish, and the next on time will continue in the normal flow.
Figure 23-18. Input Mode 5
DTA OTA DTB OTB DTA OTA DTB DTA DTB DTA DTB OTB
WOA
WOB
INPUT A/B
Input Mode 6: Stop All Outputs, Jump to Next Compare Cycle, and Wait
When Input mode 6 is used, both input A and input B will give the same functionality. The input event stops the
outputs and jumps to the opposite dead time if it occurs during an on time. If the event occurs during dead time, the
dead time will continue until the next on time is scheduled to start. As long as the input event is active, the TCD
counter will wait. When the input event stops, the next dead time will start, and normal flow will continue.
WOA
WOB
INPUT A/B
Input Mode 7: Stop all Outputs, Wait for Software Action
When Input mode 7 is used, both input A and input B will give the same functionality. The input events stop the
outputs and the TCD counter. It will be stopped until a Restart command is given. If the input event is still high when
the Restart command (RESTART bit in TCDn.CTRLE register) is given, it will stop again. When the TCD counter
restarts, it will always start on dead time A.
Figure 23-20. Input Mode 7
DTA OTA DTB OTB DTA OTA Wait DTA OTA
WOA
WOB
INPUT A/B
Software Restart
command
Input Mode 8: Stop Output on Edge, Jump to Next Compare Cycle
In Input mode 8, a positive edge on the input event while the corresponding output is ON will cause the output to stop
and the TCD counter to jump to the opposite dead time.
If Input mode 8 is used on input A and a positive edge on the input event occurs while in on time A, the TCD counter
jumps to dead time B.
Figure 23-21. Input Mode 8 on Input A
DTA OTA DTB OTB DTA OTA DTB OTB DTA OTA DTB OTB
WOA
WOB
INPUT A
OR
INPUT A
If Input mode 8 is used on input B and a positive edge on the input event occurs while in on time B, the TCD counter
jumps to dead time A.
WOA
WOB
INPUT B
OR
INPUT B
Input Mode 9: Stop Output on Edge, Maintain Frequency
In Input mode 9, a positive edge on the input event while the corresponding output is ON will cause the output to stop
during the rest of the on time. The TCD counter will not be affected by the event, only the output.
If Input mode 9 is used on input A and a positive edge on the input event occurs while in on time A, the output will be
OFF for the rest of the on time.
Figure 23-23. Input Mode 9 on Input A
DTA OTA DTB OTB DTA OTA DTB OTB DTA OTA
WOA
WOB
INPUT A
INPUT B
If Input mode 9 is used on input B and a positive edge on the input event occurs while in on time B, the output will be
OFF for the rest of the on time.
Figure 23-24. Input Mode 9 on Input B
DTA OTA DTB OTB DTA OTA DTB OTB DTA OTA
WOA
WOB
INPUT A
INPUT B
Input Mode 10: Stop Output at Level, Maintain Frequency
In Input mode 10, the input event will cause the corresponding output to stop, as long as the input is active. If the
input goes low while there must have been an on time on the corresponding output, the output will be deactivated for
the rest of the on time. The TCD counter is not affected by the event, only the output.
If Input mode 10 is used on input A and an input event occurs, the WOA will be OFF as long as the event lasts. If
released during an on time, it will be OFF for the rest of the on time.
WOA
WOB
INPUT A
INPUT B
If Input mode 10 is used on input B and an input event occurs, the WOB will be OFF as long as the event lasts. If
released during an on time, it will be OFF for the rest of the on time.
Figure 23-26. Input Mode 10 on Input B
DTA OTA DTB OTB DTA OTA DTB OTB DTA OTA
WOA
WOB
INPUT A
INPUT B
Input Mode Summary
Table 23-6 summarizes the conditions, as illustrated in the timing diagrams of the preceding sections.
Table 23-6. Input Mode Summary
...........continued
INPUTMODE Trigger → Output Affected Fault On/Active Fault Release/Inactive
7 Input A→{WOA, WOB} End on time and wait for software Start with dead time for
action. the current compare.
Input B→{WOA, WOB}
8 Input A→WOA End the current on time and continue
with the other off time.
Input B→WOB
9 Input A→WOA Block the current on time and
continue the sequence.
Input B→WOB
10 Input A→WOA Deactivate on time until the end of
the sequence while the trigger is
Input B→WOB active.
other - - -
Note: When using different modes on each event input, take into consideration possible conflicts, keeping in mind
that TCD has a single counter, to avoid unexpected results.
23.3.3.5 Dithering
If it is not possible to achieve the desired frequency because of the prescaler/period selection limitations, dithering
can be used to approximate the desired frequency and reduce the waveform drift.
The dither accumulates the fractional error of the counter clock for each cycle. When the fractional error overflows, an
additional clock cycle is added to the selected part of the TCD cycle.
Dither value
ACCUMULATOR REGISTER
The user can select where in the TCD cycle the dither will be added by writing to the Dither Selection (DITHERSEL)
bits in the Dither Control (TCDn.DITCTRL) register:
• On time B
• On time A and B
• Dead time B
• Dead time A and B
How much the dithering will affect the TCD cycle time depends on what Waveform Generation mode is used (see
Table 23-7). Dithering is not supported in Dual Slope mode.
Table 23-7. Mode-Dependent Dithering Additions to TCD Cycle
The differences in the number of TCD clock cycles added to the TCD cycle are caused by the different number of
compare values used by the TCD cycle. For example, in One Ramp mode, only CMPBCLR affects the TCD cycle
time.
For DITHERSEL configurations where no extra cycles are added to the TCD cycles, compensation is reached by
shortening the following output state.
The capture values can be obtained by reading first TCDn.CAPTUREAL/TCDn.CAPTUREBL and then
TCDn.CAPTUREAH/TCDn.CAPTUREBH registers.
Counter
Compare
value
values
EVENT
CMPBCLR
EVENT
CMPBSET
EVENT
* OVF
CMPACLR
EVENT
CMPASET
WOA
WOB
Counter
value
CMPBCLR
CMPBSET
CMPACLR
CMPASET
INPUT B
When using the override feature together with Faults detection (input modes), the CMPA (and CMPC/D if WOC/D
equals WOA) bit in TCDn.FAULTCTRL must be equal to CMPAVAL[0] and [2] in CTRL. If not, the first cycle after a
Fault is detected can have the wrong polarity on the outputs. The same applies to CMPB in the TCDn.FAULTCTRL
(and CMPC/D if WOC/D equals WOB) bit, which must be equal to CMPBVAL[0] and [2] in TCDn.CTRLD.
Due to the asynchronous nature of the TCD and that input events can immediately affect the output signal, there is a
risk of nanosecond spikes occurring on the output without any load on the pin. The case occurs in any input mode
different from ‘0’ and when an input event is triggering. The spike value will always be in the direction of the CMPx
values given by the TCDn.FAULTCTRL register.
23.3.4 Events
The TCD can generate the events described in the following table:
Table 23-8. Event Generators in TCD
Note:
1. The user can select the trigger and all the compare matches (including CMPACLR). Also, it is possible to delay
the output event from 0 to 255 TCD delay cycles.
The three events based on the counter match directly generate event strobes that last for one clock cycle on the TCD
counter clock. The programmable output event generates an event strobe that lasts for one clock cycle on the TCD
synchronizer clock.
The TCD can receive the events described in the following table:
User Name
Description Input Detection Async/Sync
Peripheral Input
Stop the output, jump to the opposite compare cycle
and wait.
Stop the output, execute the opposite compare cycle
and wait.
Stop the output, execute the opposite compare cycle
while the Fault is active.
Level
Stop all outputs, maintain the frequency.
Stop all outputs, execute dead time while the Fault is
TCDn Input A/ Input B active. Both
Input A and Input B are TCD event users that detect and act upon the input events. Additional information about input
events and how to configure them can be found in the 23.3.3.4 TCD Inputs section. Refer to the Event System
(EVSYS) section for more details regarding event types and Event System configuration.
23.3.5 Interrupts
Table 23-10. Available Interrupt Vectors and Sources
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags (TCDn.INTFLAGS)
register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the Interrupt Control
(TCDn.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
When several interrupt request conditions are supported by an interrupt vector, the interrupt requests are ORed
together into one combined interrupt request to the interrupt controller. The user must read the peripheral’s
INTFLAGS register to determine which of the interrupt conditions are present.
Register Key
TCDn.FAULTCTRL IOREG
23.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: Enable-protected
Bit 7 6 5 4 3 2 1 0
CLKSEL[1:0] CNTPRES[1:0] SYNCPRES[1:0] ENABLE
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
23.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
WGMODE[1:0]
Access R/W R/W
Reset 0 0
23.5.3 Control C
Name: CTRLC
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMPDSEL CMPCSEL FIFTY AUPDATE CMPOVR
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
23.5.4 Control D
Name: CTRLD
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMPBVAL[3:0] CMPAVAL[3:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
When used in One Ramp mode, WOA will only use the setup for dead time A (DTA) and on time A (OTA) to set the
output. WOB will only use dead time B (DTB) and on time B (OTB) values to set the output.
Table 23-13. One Ramp Mode
23.5.5 Control E
Name: CTRLE
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DISEOC SCAPTUREB SCAPTUREA RESTART SYNC SYNCEOC
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: EVCTRLA
Offset: 0x08
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CFG[1:0] EDGE ACTION TRIGEI
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: EVCTRLB
Offset: 0x09
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CFG[1:0] EDGE ACTION TRIGEI
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: INTCTRL
Offset: 0x0C
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
TRIGB TRIGA OVF
Access R/W R/W R/W
Reset 0 0 0
Name: INTFLAGS
Offset: 0x0D
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
TRIGB TRIGA OVF
Access R/W R/W R/W
Reset 0 0 0
23.5.10 Status
Name: STATUS
Offset: 0x0E
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
PWMACTB PWMACTA CMDRDY ENRDY
Access R/W R/W R R
Reset 0 0 0 0
Name: INPUTCTRLA
Offset: 0x10
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
INPUTMODE[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INPUTCTRLB
Offset: 0x11
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
INPUTMODE[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: FAULTCTRL
Offset: 0x12
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
CMPDEN CMPCEN CMPBEN CMPAEN CMPD CMPC CMPB CMPA
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DLYCTRL
Offset: 0x14
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DLYPRESC[1:0] DLYTRIG[1:0] DLYSEL[1:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: DLYVAL
Offset: 0x15
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DLYVAL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DITCTRL
Offset: 0x18
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DITHERSEL[1:0]
Access R/W R/W
Reset 0 0
Name: DITVAL
Offset: 0x19
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DITHER[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: DBGCTRL
Offset: 0x1E
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
FAULTDET DBGRUN
Access R/W R/W
Reset 0 0
23.5.19 Capture A
Name: CAPTUREA
Offset: 0x22
Reset: 0x00
Property: -
The TCDn.CAPTUREAL and TCDn.CAPTUREAH register pair represents the 12-bit TCDn.CAPTUREA value.
For capture operation, these registers constitute the second buffer level and access point for the CPU. The
TCDn.CAPTUREA registers are updated with the buffer value when an update condition occurs. The CAPTURE A
register contains the TCD counter value when a trigger A or software capture A occurs.
The TCD counter value is synchronized to CAPTUREA by either software or an event.
The capture register is blocked for an update of new capture data until the higher byte of this register is read.
Bit 15 14 13 12 11 10 9 8
CAPTUREA[11:8]
Access R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CAPTUREA[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
23.5.20 Capture B
Name: CAPTUREB
Offset: 0x24
Reset: 0x00
Property: -
The TCDn.CAPTUREBL and TCDn.CAPTUREBH register pair represents the 12-bit TCDn.CAPTUREB value.
For capture operation, these registers constitute the second buffer level and access point for the CPU. The
TCDn.CAPTUREB registers are updated with the buffer value when an update condition occurs. The CAPTURE B
register contains the TCD counter value when a trigger B or software capture B occurs.
The TCD counter value is synchronized to CAPTUREB by either software or an event.
The capture register is blocked for an update of new capture data until the higher byte of this register is read.
Bit 15 14 13 12 11 10 9 8
CAPTUREB[11:8]
Access R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CAPTUREB[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: CMPASET
Offset: 0x28
Reset: 0x00
Property: -
The TCDn.CMPASETL and TCDn.CMPASETH register pair represents the 12-bit TCDn.CMPASET value. This
register is continuously compared to the counter value. Then, the outputs from the comparators are used for
generating waveforms.
Bit 15 14 13 12 11 10 9 8
CMPASET[11:8]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CMPASET[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CMPBSET
Offset: 0x2C
Reset: 0x00
Property: -
The TCDn.CMPBSETL and TCDn.CMPBSETH register pair represents the 12-bit TCDn.CMPBSET value. This
register is continuously compared to the counter value. Then, the outputs from the comparators are used for
generating waveforms.
Bit 15 14 13 12 11 10 9 8
CMPBSET[11:8]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CMPBSET[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CMPACLR
Offset: 0x2A
Reset: 0x00
Property: -
The TCDn.CMPACLRL and TCDn.CMPACLRH register pair represents the 12-bit TCDn.CMPACLR value. This
register is continuously compared to the counter value. Then, the outputs from the comparators are used for
generating waveforms.
Bit 15 14 13 12 11 10 9 8
CMPACLR[11:8]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CMPACLR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CMPBCLR
Offset: 0x2E
Reset: 0x00
Property: -
The TCDn.CMPBCLRL and TCDn.CMPBCLRH register pair represents the 12-bit TCDn.CMPBCLR value. This
register is continuously compared to the counter value. Then, the outputs from the comparators are used for
generating waveforms.
Bit 15 14 13 12 11 10 9 8
CMPBCLR[11:8]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CMPBCLR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
24.1 Features
• 16-bit Resolution
• Selectable Clock Sources
• Programmable 15-bit Clock Prescaling
• One Compare Register
• One Period Register
• Clear Timer on Period Overflow
• Optional Interrupt/Event on Overflow and Compare Match
• Periodic Interrupt and Event
24.2 Overview
The RTC peripheral offers two timing functions: the Real-Time Counter (RTC) and a Periodic Interrupt Timer (PIT).
The PIT functionality can be enabled independently of the RTC functionality.
TOSC1
32.768 kHz Crystal Osc.
TOSC2
DIV32
PER
CLK_RTC = Overflow
Correction 15-bit
CNT
counter prescaler
= Compare
PIT CMP
RTC
Period
24.3 Clocks
The peripheral clock (CLK_PER) is required to be at least four times faster than the RTC clock (CLK_RTC) for
reading the counter value, regardless of the prescaler setting.
A 32.768 kHz crystal can be connected to the TOSC1 or TOSC2 pins, along with any required load capacitors.
Alternatively, an external digital clock can be connected to the TOSC1 pin.
24.4.1 Initialization
Before enabling the RTC peripheral and the desired actions (interrupt requests and output events), the source clock
for the RTC counter must be configured to operate the RTC.
The CLK_RTC clock configuration is used by both RTC and PIT functionality.
24.5.1 Initialization
To operate the PIT, follow these steps:
1. Configure the RTC clock CLK_RTC as described in section 24.4.1.1 Configure the Clock CLK_RTC.
2. Enable the interrupt by writing a ‘1’ to the Periodic Interrupt (PI) bit in the PIT Interrupt Control
(RTC.PITINTCTRL) register.
3. Select the period for the interrupt by writing the desired value to the Period (PERIOD) bit field in the Periodic
Interrupt Timer Control A (RTC.PITCTRLA) register.
4. Enable the PIT by writing a ‘1’ to the Periodic Interrupt Timer Enable (PITEN) bit in the RTC.PITCTRLA
register.
Note: The RTC peripheral is used internally during device start-up. Always check the Synchronization Busy bits in
the RTC.STATUS and RTC.PITSTATUS registers, and on the initial configuration.
The prescaler is OFF when both functions are OFF (RTC Peripheral Enable (RTCEN) bit in RTC.CTRLA and the
Periodic Interrupt Timer Enable (PITEN) bit in RTC.PITCTRLA are ‘0’), but it is running (that is, its internal counter is
counting) when either function is enabled. For this reason, the timing of the first PIT interrupt and the first RTC count
tick will be unknown (anytime between enabling and a full period).
Continuous Operation
After the first interrupt, the PIT will continue toggling every ½ PIT period resulting in a full PIT period signal.
CLK_RTC
Prescaler
..000000
..000001
..000010
..000100
..000101
..001000
..001001
..001010
..010000
..010001
..010010
..010100
..010101
..100000
..100001
..100010
..100100
..100101
..101000
..101001
..101010
..000011
..000110
..001011
..001100
..001101
..010011
..010110
..011000
..011001
..011010
..100011
..100110
..101011
..101100
..101101
..000111
..001110
..010111
..011011
..011100
..011101
..100111
..101110
..001111
..011110
..101111
..011111
counter
value (LSB)
Prescaler bit 3
(CYC16)
24.6 Events
The RTC can generate the events described in the following table:
The conditions for generating the OVF and CMP events are identical to those that will raise the corresponding
interrupt flags in the RTC.INTFLAGS register.
Refer to the (EVSYS) Event System section for more details regarding event users and Event System configuration.
24.7 Interrupts
Table 24-2. Available Interrupt Vectors and Sources
PIT Periodic Interrupt Timer A time period has passed, as configured by the PERIOD bit field in
interrupt RTC.PITCTRLA.
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
Note that:
24.9 Synchronization
Both the RTC and the PIT are asynchronous, operating from a different clock source (CLK_RTC) independently of
the peripheral clock (CLK_PER). For Control and Count register updates, it will take some RTC and/or peripheral
clock cycles before an updated register value is available in a register or until a configuration change affects the RTC
or PIT, respectively. This synchronization time is described for each register in the Register Description section.
For some RTC registers, a Synchronization Busy flag is available (CMPBUSY, PERBUSY, CNTBUSY, CTRLABUSY)
in the Status (RTC.STATUS) register.
For the RTC.PITCTRLA register, a Synchronization Busy flag is available (CTRLBUSY) in the Periodic Interrupt
Timer Status (RTC.PITSTATUS) register.
Check these flags before writing to the mentioned registers.
24.12.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUNSTDBY PRESCALER[3:0] RTCEN
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
24.12.2 Status
Name: STATUS
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMPBUSY PERBUSY CNTBUSY CTRLABUSY
Access R R R R
Reset 0 0 0 0
Name: INTCTRL
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMP OVF
Access R/W R/W
Reset 0 0
Name: INTFLAGS
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMP OVF
Access R/W R/W
Reset 0 0
24.12.5 Temporary
Name: TEMP
Offset: 0x4
Reset: 0x00
Property: -
The Temporary register is used by the CPU for 16-bit single-cycle access to the 16-bit registers of this peripheral. The
register is common for all the 16-bit registers of this peripheral and can be read and written by software. For more
details on reading and writing 16-bit registers, refer to Accessing 16-Bit Registers in the AVR CPU section.
Bit 7 6 5 4 3 2 1 0
TEMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DBGCTRL
Offset: 0x05
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: CLKSEL
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CLKSEL[1:0]
Access R/W R/W
Reset 0 0
24.12.8 Count
Name: CNT
Offset: 0x08
Reset: 0x0000
Property: -
The RTC.CNTL and RTC.CNTH register pair represents the 16-bit value, RTC.CNT. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Due to the synchronization between the RTC clock and main clock domains, there is a latency of two RTC clock
cycles from updating the register until this has an effect. The application software needs to check that the CNTBUSY
flag in RTC.STATUS is cleared before writing to this register.
Bit 15 14 13 12 11 10 9 8
CNT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
24.12.9 Period
Name: PER
Offset: 0x0A
Reset: 0xFFFF
Property: -
The RTC.PERL and RTC.PERH register pair represents the 16-bit value, RTC.PER. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Due to the synchronization between the RTC clock and main clock domains, there is a latency of two RTC clock
cycles from updating the register until this has an effect. The application software needs to check that the PERBUSY
flag in RTC.STATUS is cleared before writing to this register.
Bit 15 14 13 12 11 10 9 8
PER[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
PER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
24.12.10 Compare
Name: CMP
Offset: 0x0C
Reset: 0x0000
Property: -
The RTC.CMPL and RTC.CMPH register pair represents the 16-bit value, RTC.CMP. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit 15 14 13 12 11 10 9 8
CMP[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: PITCTRLA
Offset: 0x10
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
PERIOD[3:0] PITEN
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: PITSTATUS
Offset: 0x11
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CTRLBUSY
Access R
Reset 0
Name: PITINTCTRL
Offset: 0x12
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
PI
Access R/W
Reset 0
Name: PITINTFLAGS
Offset: 0x13
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
PI
Access R/W
Reset 0
Name: PITDBGCTRL
Offset: 0x15
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
25.1 Features
• Full-Duplex Operation
• Half-Duplex Operation:
– One-Wire mode
– RS-485 mode
• Asynchronous or Synchronous Operation
• Supports Serial Frames with Five, Six, Seven, Eight or Nine Data Bits and One or Two Stop Bits
• Fractional Baud Rate Generator:
– Can generate the desired baud rate from any system clock frequency
– No need for an external oscillator
• Built-In Error Detection and Correction Schemes:
– Odd or even parity generation and parity check
– Buffer overflow and frame error detection
– Noise filtering including false Start bit detection and digital low-pass filter
• Separate Interrupts for:
– Transmit complete
– Transmit Data register empty
– Receive complete
• Master SPI Mode
• Multiprocessor Communication Mode
• Start-of-Frame Detection
• IRCOM Module for IrDA® Compliant Pulse Modulation/Demodulation
• LIN Slave Support
25.2 Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a fast and flexible serial
communication peripheral. The USART supports a number of different modes of operation that can accommodate
multiple types of applications and communication devices. For example, the One-Wire Half-Duplex mode is useful
when low pin count applications are desired. The communication is frame-based, and the frame format can be
customized to support a wide range of standards.
The USART is buffered in both directions, enabling continued data transmission without any delay between frames.
Separate interrupts for receive and transmit completion allow fully interrupt-driven communication.
The transmitter consists of a single-write buffer, a Shift register, and control logic for different frame formats. The
receiver consists of a two-level receive buffer and a Shift register. The status information of the received data is
available for error checking. Data and clock recovery units ensure robust synchronization and noise filtering during
asynchronous data reception.
CLOCK GENERATOR
TRANSMITTER
XDIR
TXDATA TX Shift Register
TXD
RECEIVER
25.3.1 Initialization
Full Duplex Mode:
1. Set the baud rate (USARTn.BAUD).
2. Set the frame format and mode of operation (USARTn.CTRLC).
3. Configure the TXD pin as an output.
4. Enable the transmitter and the receiver (USARTn.CTRLB).
Notes:
• For interrupt-driven USART operation, global interrupts must be disabled during the initialization
• Before doing a reinitialization with a changed baud rate or frame format, be sure that there are no ongoing
transmissions while the registers are changed
One-Wire Half Duplex Mode:
1. Internally connect the TXD to the USART receiver (the LBME bit in the USARTn.CTRLA register).
2. Enable internal pull-up for the RX/TX pin (the PULLUPEN bit in the PORTx.PINnCTRL register).
25.3.2 Operation
FRAME
CLK_PER Edge
Detector
XCKO
Transmitter
TXCLK
Receiver
RXCLK
Operating Mode Conditions Baud Rate (Bits Per Seconds) USART.BAUD Register Value
Calculation
Asynchronous ����_��� 64 × ����_��� 64 × ����_���
����� ≤ ����� = ���� =
� � × ���� � × �����
�����.���� ≥ 64
Synchronous Master ����_��� ����_��� ����_���
����� ≤ ����� = ���� 15: 6 =
� � × ���� 15: 6 � × �����
�����.���� ≥ 64
The error flags are located in the RX buffer together with their corresponding frame. The RXDATAH register that
contains the error flags must be read before the RXDATAL register, since reading the RXDATAL register will trigger
the RX buffer to shift out the RXDATA bytes.
Note: If the Character Size bit field (the CHSIZE bits in the USARTn.CTRLC register) is set to nine bits, low byte
first (9BITL), the RXDATAH register will, instead of the RXDATAL register, trigger the RX buffer to shift out the
RXDATA bytes. The RXDATAL register must, in that case, be read before the RXDATAH register.
25.3.2.4.2 Disabling the Receiver
When disabling the receiver, the operation is immediate. The receiver buffer will be flushed, and data from ongoing
receptions will be lost.
25.3.2.4.3 Flushing the Receive Buffer
If the RX buffer has to be flushed during normal operation, repeatedly read the DATA location (USARTn.RXDATAH
and USARTn.RXDATAL registers) until the Receive Complete Interrupt Flag (the RXCIF bit in the
USARTn.RXDATAH register) is cleared.
XCK
INVEN = 0 Data transmit (TxD)
XCK
INVEN = 1 Data transmit (TxD)
XCK clock edge. If inverted I/O is enabled (INVEN = 1), the falling XCK clock edge represents the start of a new data
bit, and the received data will be sampled at the rising XCK clock edge.
Frame Formats
The serial frame for the USART in Master SPI mode always contains eight Data bits. The Data bits can be configured
to be transmitted with either the LSb or MSb first, by writing to the Data Order bit (UDORD) in the Control C register
(USARTn.CTRLC).
SPI does not use Start, Stop, or Parity bits, so the transmission frame can only consist of the Data bits.
Clock Generation
Being a master device in a synchronous communication interface, the USART in Master SPI mode must generate the
interface clock to be shared with the slave devices. The interface clock is generated using the fractional Baud Rate
Generator, which is described in 25.3.2.2.1 The Fractional Baud Rate Generator.
Each Data bit is transmitted by pulling the data line high or low for one full clock period. The receiver will sample bits
in the middle of the transmitter hold period as shown in the figure below. It also shows how the timing scheme can be
configured using the Inverted I/O Enable (INVEN) bit in the PORTx.PINnCTRL register and the USART Clock Phase
(UCPHA) bit in the USARTn.CTRLC register.
Figure 25-5. Data Transfer Timing Diagrams
INVEN = 0 INVEN = 1
XCK XCK
UCPHA = 0
XCK XCK
UCPHA = 1
...........continued
INVEN UCPHA Leading Edge (1) Trailing Edge (1)
0 1 Rising, transmit Falling, sample
1 0 Falling, sample Rising, transmit
1 1 Falling, transmit Rising, sample
Note:
1. The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock
cycle.
Data Transmission
Data transmission in Master SPI mode is functionally identical to general USART operation as described in the
Operation section. The transmitter interrupt flags and corresponding USART interrupts are also identical. See
25.3.2.3 Data Transmission for further description.
Data Reception
Data reception in Master SPI mode is identical in function to general USART operation as described in the Operation
section. The receiver interrupt flags and the corresponding USART interrupts are also identical, aside from the
receiver error flags that are not in use and always read as ‘0’. See 25.3.2.4 Data Reception for further description.
Note:
1. For the stand-alone SPI peripheral, this pin is used with the Multi-Master function or as a dedicated Slave
Select pin. The Multi-Master function is not available with the USART in Master SPI mode, and no dedicated
Slave Select pin is available.
arrows show the maximum synchronization error. Note that the maximum synchronization error is larger in Double-
Speed mode.
Figure 25-6. Start Bit Sampling
Sample
(RXMODE = 0x0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Sample
(RXMODE = 0x1) 0 1 2 3 4 5 6 7 8 1 2
When the clock recovery logic detects a falling edge from Idle (high) state to the Start bit (low), the Start bit detection
sequence is initiated. In the figure above, sample 1 denotes the first sample reading ‘0’. The clock recovery logic then
uses three subsequent samples (samples 8, 9, and 10 in Normal mode, and samples 4, 5, 6 in Double-Speed mode)
to decide if a valid Start bit is received. If two or three samples read ‘0’, the Start bit is accepted. The clock recovery
unit is synchronized, and the data recovery can begin. If less than two samples read ‘0’, the Start bit is rejected. This
process is repeated for each Start bit.
RxD BIT n
Sample
(CLK2X = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
Sample
(CLK2X = 1) 1 2 3 4 5 6 7 8 1
A majority voting technique is, like with clock recovery, used on the three center samples for deciding the logic level
of the received bit. The process is repeated for each bit until a complete frame is received.
The data recovery unit will only receive the first Stop bit while ignoring the rest if there are more. If the sampled Stop
bit is read ‘0’, the Frame Error flag will be set. The figure below shows the sampling of a Stop bit. It also shows the
earliest possible beginning of the next frame's Start bit.
Figure 25-8. Stop Bit and Next Start Bit Sampling
Sample
(CLK2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1
Sample
(CLK2X = 1) 1 2 3 4 5 6 0/1
A new high-to-low transition indicating the Start bit of a new frame can come right after the last of the bits used for
majority voting. For Normal-Speed mode, the first low-level sample can be at the point marked (A) in the figure
above. For Double-Speed mode the first low level must be delayed to point (B), being the first sample after the
majority vote samples. Point (C) marks a Stop bit of full length at the nominal baud rate.
D Rslow [%] Rfast [%] Maximum Total Error [%] Recommended Max. Receiver Error [%]
5 93.20 106.67 -6.80/+6.67 ±3.0
6 94.12 105.79 -5.88/+5.79 ±2.5
7 94.81 105.11 -5.19/+5.11 ±2.0
8 95.36 104.58 -4.54/+4.58 ±2.0
9 95.81 104.14 -4.19/+4.14 ±1.5
10 96.17 103.78 -3.83/+3.78 ±1.5
Notes:
• D: The sum of character size and parity size (D = 5 to 10 bits)
• RSLOW: The ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
• RFAST: The ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
Table 25-5. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode
D Rslow [%] Rfast [%] Maximum Total Error [%] Recommended Max. Receiver Error [%]
5 94.12 105.66 -5.88/+5.66 ±2.5
6 94.92 104.92 -5.08/+4.92 ±2.0
7 95.52 104.35 -4.48/+4.35 ±1.5
8 96.00 103.90 -4.00/+3.90 ±1.5
9 96.39 103.53 -3.61/+3.53 ±1.5
10 96.70 103.23 -3.30/+3.23 ±1.0
Notes:
• D: The sum of character size and parity size (D = 5 to 10 bits)
• RSLOW: The ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
• RFAST: The ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
The recommendations of the maximum receiver baud rate error were made under the assumption that the receiver
and transmitter equally divide the maximum total error.
The following equations are used to calculate the maximum ratio of the incoming data rate and the internal receiver
baud rate.
� �+1 � �+2
����� = ����� =
� � + 1 + �� − 1 � � + 1 + ��
• SM: Middle sample number used for majority voting. SM = 9 for Normal-Speed mode and SM = 5 for Double-
Speed mode.
• RSLOW: The ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
• RFAST: The ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
25.3.3.2.5 Auto-Baud
The auto-baud feature lets the USART configure its BAUD register based on input from a communication device.
This allows the device to communicate autonomously with multiple devices communicating with different baud rates.
The USART peripheral features two auto-baud modes: Generic Auto-Baud mode and LIN Constrained Auto-Baud
mode.
Both auto-baud modes must receive an auto-baud frame as seen in the figure below.
Figure 25-9. Auto-Baud Timing
Break Field Sync Field
Tbit
8 Tbit
The break field is detected when 12 or more consecutive low cycles are sampled and notifies the USART that it is
about to receive the synchronization field. After the break field, when the Start bit of the synchronization field is
detected, a counter running at the peripheral clock speed is started. The counter is then incremented for the next
eight Tbit of the synchronization field. When all eight bits are sampled, the counter is stopped. The resulting counter
value is in effect the new BAUD register value.
When the USART Receive mode is set to GENAUTO (the RXMODE bits in the USARTn.CTRLB register), the
Generic Auto-Baud mode is enabled. In this mode, one can set the Wait For Break (WFB) bit in the USARTn.STATUS
register to enable detection of a break field of any length (that is, also shorter than 12 cycles). This makes it possible
to set an arbitrary new baud rate without knowing the current baud rate. If the measured sync field results in a valid
BAUD value (0x0064 - 0xFFFF), the BAUD register is updated.
When USART Receive mode is set to LINAUTO mode (the RXMODE bits in the USARTn.CTRLB register), it follows
the LIN format. The WFB functionality of the Generic Auto-Baud mode is not compatible with the LIN Constrained
Auto-Baud mode. This means that the received signal must be low for 12 peripheral clock cycles or more for a break
field to be valid. When a break field has been detected, the USART expects the following synchronization field
character to be 0x55. If the received synchronization field character is not 0x55, the Inconsistent Sync Field Error
Flag (the ISFIF bit in the USARTn.STATUS register) is set, and the baud rate is unchanged.
One-Wire Mode
One-Wire mode is enabled by setting the Loop-Back Mode Enable (LBME) bit in the USARTn.CTRLA register. This
will enable an internal connection between the TXD pin and the USART receiver, making the TXD pin a combined
TxD/RxD line. The RXD pin will be disconnected from the USART receiver and may be controlled by a different
peripheral.
In One-Wire mode, multiple devices are able to manipulate the TxD/RxD line at the same time. In the case where one
device drives the pin to a logical high level (VCC), and another device pulls the line low (GND), a short will occur. To
accommodate this, the USART features an Open-Drain mode (the ODME bit in the USARTn.CTRLB register) which
prevents the transmitter from driving a pin to a logical high level, thereby constraining it to only be able to pull it low.
Combining this function with the internal pull-up feature (the PULLUPEN bit in the PORTx.PINnCTRL register) will let
the line be held high through a pull-up resistor, allowing any device to pull it low. When the line is pulled low the
current from VCC to GND will be limited by the pull-up resistor. The TXD pin is automatically set to output by hardware
when the Open-Drain mode is enabled.
When the USART is transmitting to the TxD/RxD line, it will also receive its own transmission. This can be used to
check for overlapping transmissions by checking if the received data are the same as the transmitted data as it
should be.
RS-485 Mode
RS-485 is a communication standard supported by the USART peripheral. It is a physical interface that defines the
setup of a communication circuit. Data are transmitted using differential signaling, making communication robust
against noise. RS-485 is enabled by writing to the RS485 bit field (USARTn.CTRLA).
The RS-485 mode supports external line driver devices that convert a single USART transmission into corresponding
differential pair signals. Writing RS485[0] to ‘1’ enables the automatic control of the XDIR pin that can be used to
enable transmission or reception for the line driver device. The USART automatically drives the XDIR pin high while
the USART is transmitting and pulls it low when the transmission is complete. An example of such a circuit is shown
in the figure below.
Figure 25-10. RS-485 Bus Connection
TX Driver
XDIR Differential Bus
USART +
-
RX Driver
RXD
The XDIR pin goes high one baud clock cycle in advance of data being shifted out to allow some guard time to
enable the external line driver. The XDIR pin will remain high for the complete frame including Stop bit(s).
Figure 25-11. XDIR Drive Timing
TxD St 0 1 2 3 4 5 6 7 Sp1
XDIR
Guard
Stop
time
Writing RS485[1] to ‘1’ enables the RS-485 mode which automatically sets the TXD pin to output one clock cycle
before starting transmission and sets it back to input when the transmission is complete.
RS-485 mode is compatible with One-Wire mode. One-Wire mode enables an internal connection between the TXD
pin and the USART receiver, making the TXD pin a combined TxD/RxD line. The RXD pin will be disconnected from
the USART receiver and may be controlled by a different peripheral. An example of such a circuit is shown in the
figure below.
TX Driver
XDIR Differential Bus
USART +
-
RX Driver
RXD
Encoded RxD
Pulse
Decoding
Decoded RxD
USART RXD
Decoded RxD TXD
Pulse
Encoding
Encoded RxD
The USART is set in IRCOM mode by writing 0x02 to the CMODE bits in the USARTn.CTRLC register. The data on
the TXD/RXD pins are the inverted values of the transmitted/received infrared pulse. It is also possible to select an
event channel from the Event System as an input for the IRCOM receiver. This enables the IRCOM to receive input
from the I/O pins or sources other than the corresponding RXD pin. This will disable the RxD input from the USART
pin.
For transmission, three pulse modulation schemes are available:
• 3/16 of the baud rate period
• Fixed programmable pulse time based on the peripheral clock frequency
• Pulse modulation disabled
For the reception, a fixed programmable minimum high-level pulse-width for the pulse to be decoded as a logical ‘0’
is used. Shorter pulses will then be discarded, and the bit will be decoded to logical ‘1’ as if no pulse was received.
When IRCOM mode is enabled, Double-Speed mode cannot be used for the USART.
25.3.4.1 Parity
Parity bits can be used by the USART to check the validity of a data frame. The Parity bit is set by the transmitter
based on the number of bits with the value of ‘1’ in a transmission and controlled by the receiver upon reception. If
the Parity bit is inconsistent with the transmission frame, the receiver may assume that the data frame has been
corrupted.
Even or odd parity can be selected for error checking by writing the Parity Mode (PMODE) bits in the
USARTn.CTRLC register. If even parity is selected, the Parity bit is set to ‘1’ if the number of Data bits with value ‘1’
is odd (making the total number of bits with value ‘1’ even). If odd parity is selected, the Parity bit is set to ‘1’ if the
number of data bits with value ‘1’ is even (making the total number of bits with value ‘1’ odd).
When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result
with the Parity bit of the corresponding frame. If a parity error is detected, the Parity Error flag (the PERR bit in the
USARTn.RXDATAH register) is set.
If LIN Constrained Auto-Baud mode is enabled (RXMODE = 0x03 in the USARTn.CTRLB register), a parity check is
only performed on the protected identifier field. A parity error is detected if one of the equations below is not true,
which sets the Parity Error flag.
�0 = ��0 XOR ��1 XOR ��2 XOR ��4
�1 = NOT ��1 XOR ��3 XOR ��4 XOR ��5
Figure 25-14. Protected Identifier Field and Mapping of Identifier and Parity Bits
Protected identifier field
Note: The SLEEP instruction will not shut down the oscillator if there is ongoing communication.
mode is enabled by writing a ‘1’ to the MPCM bit in the Control B register (USARTn.CTRLB). In this mode, a
dedicated bit in the frames is used to indicate whether the frame is an address or data frame type.
If the receiver is set up to receive frames that contain five to eight data bits, the first Stop bit is used to indicate the
frame type. If the receiver is set up for frames with nine data bits, the ninth bit is used to indicate frame type. When
the frame type bit is ‘1’, the frame contains an address. When the frame type bit is ‘0’, the frame is a data frame. If 5-
to 8-bit character frames are used, the transmitter must be set to use two Stop bits, since the first Stop bit is used for
indicating the frame type.
If a particular slave MCU has been addressed, it will receive the following data frames as usual, while the other slave
MCUs will ignore the frames until another address frame is received.
25.3.5 Events
The USART can generate the events described in the table below.
Table 25-7. Event Generators in USART
The table below describes the event user and its associated functionality.
Table 25-8. Event Users in USART
User Name
Description Input Detection Async/Sync
Peripheral Input
USARTn IREI USARTn IrDA event input Pulse Sync
25.3.6 Interrupts
Table 25-9. Available Interrupt Vectors and Sources
DRE Data Register Empty The transmit buffer is empty/ready to receive new data (DREIE)
interrupt
TXC Transmit Complete The entire frame in the Transmit Shift register has been shifted out and there
interrupt are no new data in the transmit buffer (TXCIE)
When an Interrupt condition occurs, the corresponding Interrupt flag is set in the STATUS register
(USARTn.STATUS).
An interrupt source is enabled or disabled by writing to the corresponding bit in the Control A register
(USARTn.CTRLA).
An interrupt request is generated when the corresponding interrupt source is enabled, and the Interrupt flag is set.
The interrupt request remains active until the Interrupt flag is cleared. See the USARTn.STATUS register for details
on how to clear Interrupt flags.
Name: RXDATAL
Offset: 0x00
Reset: 0x00
Property: -
Reading the USARTn.RXDATAL register will return the contents of the eight least significant RXDATA bits.
The receive buffer consists of a two-level buffer. The data buffer and the corresponding flags in the high byte of
RXDATA will change state whenever the receive buffer is accessed (read). If the CHSIZE bits in the USARTn.CTRLC
register are set to 9BIT Low byte first, read the USARTn.RXDATAL register before the USARTn.RXDATAH register.
Otherwise, always read the USARTn.RXDATAH register before the USARTn.RXDATAL register in order to get the
correct flags.
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: RXDATAH
Offset: 0x01
Reset: 0x00
Property: -
Reading the USARTn.RXDATAH register location will return the contents of the ninth RXDATA bit plus Status bits.
The receive buffer consists of a two-level buffer. The data buffer and the corresponding flags in the high byte of
USARTn.RXDATAH will change state whenever the receive buffer is accessed (read). If the CHSIZE bits in the
USARTn.CTRLC register are set to 9BIT Low byte first, read the USARTn.RXDATAL register before the
USARTn.RXDATAH register. Otherwise, always read the USARTn.RXDATAH register before the USARTn.RXDATAL
register in order to get the correct flags.
Bit 7 6 5 4 3 2 1 0
RXCIF BUFOVF FERR PERR DATA[8]
Access R R R R R
Reset 0 0 0 0 0
Name: TXDATAL
Offset: 0x02
Reset: 0x00
Property: -
The Transmit Data Buffer (TXB) register will be the destination for data written to the USARTn.TXDATAL register
location.
For 5-, 6-, or 7-bit characters the upper, unused bits will be ignored by the transmitter and set to zero by the receiver.
The transmit buffer can only be written when the DREIF flag in the USARTn.STATUS register is set. Data written to
the DATA bits when the DREIF flag is not set will be ignored by the USART transmitter. When data are written to the
transmit buffer, and the transmitter is enabled, the transmitter will load the data into the Transmit Shift register when
the Shift register is empty. The data are then transmitted on the TXD pin.
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: TXDATAH
Offset: 0x03
Reset: 0x00
Property: -
The USARTn.TXDATAH register holds the ninth data bit in the character to be transmitted when operating with serial
frames with nine data bits. When used, this bit must be written before writing to the USARTn.TXDATAL register
except if the CHSIZE bits in the USARTn.CTRLC register are is set to 9BIT low byte first, where the
USARTn.TXDATAL register should be written first.
This bit is unused in Master SPI mode of operation.
Bit 7 6 5 4 3 2 1 0
DATA[8]
Access R/W
Reset 0
Name: STATUS
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RXCIF TXCIF DREIF RXSIF ISFIF BDF WFB
Access R R/W R R/W R/W R/W R/W
Reset 0 0 1 0 0 0 0
user to set any BAUD rate through BREAK and SYNC as long as it falls within the valid range of the USARTn.BAUD
register. This bit will always read ‘0’.
25.5.6 Control A
Name: CTRLA
Offset: 0x05
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RXCIE TXCIE DREIE RXSIE LBME ABEIE RS485[1:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
25.5.7 Control B
Name: CTRLB
Offset: 0x06
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RXEN TXEN SFDEN ODME RXMODE[1:0] MPCM
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Name: CTRLC
Offset: 0x07
Reset: 0x03
Property: -
This register description is valid for all modes except the Master SPI mode. When the USART Communication Mode
bits (CMODE) in this register are written to ‘MSPI’, see CTRLC - Master SPI mode for the correct description.
Bit 7 6 5 4 3 2 1 0
CMODE[1:0] PMODE[1:0] SBMODE CHSIZE[2:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 1 1
Name: CTRLC
Offset: 0x07
Reset: 0x00
Property: -
This register description is valid only when the USART is in Master SPI mode (CMODE written to MSPI). For other
CMODE values, see CTRLC - Asynchronous mode.
See 25.3.3.1.3 USART in Master SPI Mode for a full description of the Master SPI mode operation.
Bit 7 6 5 4 3 2 1 0
CMODE[1:0] UDORD UCPHA
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: BAUD
Offset: 0x08
Reset: 0x00
Property: -
The USARTn.BAUDL and USARTn.BAUDH register pair represents the 16-bit value, USARTn.BAUD. The low byte
[7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Ongoing transmissions of the transmitter and receiver will be corrupted if the baud rate is changed. Writing to this
register will trigger an immediate update of the baud rate prescaler. For more information on how to set the baud rate,
see Table 25-1, Equations for Calculating Baud Rate Register Setting.
Bit 15 14 13 12 11 10 9 8
BAUD[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
BAUD[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DBGCTRL
Offset: 0x0B
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: EVCTRL
Offset: 0x0C
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
IREI
Access R/W
Reset 0
Name: TXPLCTRL
Offset: 0x0D
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
TXPL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: RXPLCTRL
Offset: 0x0E
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RXPL[6:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
26.1 Features
• Full Duplex, Three-Wire Synchronous Data Transfer
• Master or Slave Operation
• LSb First or MSb First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double-Speed (CK/2) Master SPI Mode
26.2 Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It
allows full duplex communication between an AVR® device and peripheral devices, or between several
microcontrollers. The SPI peripheral can be configured as either master or slave. The master initiates and controls all
data transactions.
The interconnection between master and slave devices with SPI is shown in the block diagram. The system consists
of two shift registers and a master clock generator. The SPI master initiates the communication cycle by pulling the
desired slave’s Slave Select (SS) signal low. The master and slave prepare the data to be sent to their respective
shift registers, and the master generates the required clock pulses on the SCK line to exchange data. Data are
always shifted from master to slave on the master output, slave input (MOSI) line, and from slave to master on the
master input, slave output (MISO) line.
DATA DATA
Buffer Buffer
mode mode
Buffer Buffer
mode mode
DATA DATA
The SPI is built around an 8-bit shift register that will shift data out and in at the same time. The Transmit Data
register and the Receive Data register are not physical registers but are mapped to other registers when written or
read: Writing the Transmit Data register (SPIn.DATA) will write the shift register in Normal mode and the Transmit
Buffer register in Buffer mode. Reading the Receive Data register (SPIn.DATA) will read the Receive Data register in
Normal mode and the Receive Data Buffer in Buffer mode.
In Master mode, the SPI has a clock generator to generate the SCK clock. In Slave mode, the received SCK clock is
synchronized and sampled to trigger the shifting of data in the shift register.
Pin Configuration
Signal Description
Master Mode Slave Mode
MOSI Master Out Slave In User defined(1) Input
MISO Master In Slave Out Input User defined(1,2)
SCK Serial Clock User defined(1) Input
SS Slave Select User defined(1) Input
Notes:
1. If the pin data direction is configured as output, the pin level is controlled by the SPI.
2. If the SPI is in Slave mode and the MISO pin data direction is configured as output, the SS pin controls the
MISO pin output in the following way:
– If the SS pin is driven low, the MISO pin is controlled by the SPI.
– If the SS pin is driven high, the MISO pin is tri-stated.
When the SPI module is enabled, the pin data direction for the signals marked with “Input” in Table 26-1 is
overridden.
26.3.1 Initialization
Initialize the SPI to a basic functional state by following these steps:
1. Configure the SS pin in the port peripheral.
2. Select SPI master/slave operation by writing the Master/Slave Select bit (MASTER) in the Control A register
(SPIn.CTRLA).
3. In Master mode, select the clock speed by writing the Prescaler bits (PRESC) and the Clock Double bit
(CLK2X) in SPIn.CTRLA.
4. Optional: Select the Data Transfer mode by writing to the MODE bits in the Control B register (SPIn.CTRLB).
5. Optional: Write the Data Order bit (DORD) in SPIn.CTRLA.
6. Optional: Setup Buffer mode by writing BUFEN and BUFWR bits in the Control B register (SPIn.CTRLB).
7. Optional: To disable the multi-master support in Master mode, write ‘1’ to the Slave Select Disable bit (SSD) in
SPIn.CTRLB.
8. Enable the SPI by writing a ‘1’ to the ENABLE bit in SPIn.CTRLA.
26.3.2 Operation
1. New bytes to be sent cannot be written to the DATA register (SPIn.DATA) before the entire transfer has
completed. A premature write will cause corruption of the transmitted data, and the Write Collision flag
(WRCOL in SPIn.INTFLAGS) will be set.
2. Received bytes are written to the Receive Data Buffer register immediately after the transmission is
completed.
3. The Receive Data Buffer register has to be read before the next transmission is completed or data will be lost.
This register is read by reading SPIn.DATA.
4. The Transmit Data Buffer and Receive Data Buffer registers are not used in Normal mode.
After a transfer has completed, the Interrupt Flag will be set in the Interrupt Flags register (IF in SPIn.INTFLAGS).
This will cause the corresponding interrupt to be executed if this interrupt and the global interrupts are enabled.
Setting the Interrupt Enable (IE) bit in the Interrupt Control register (SPIn.INTCTRL) will enable the interrupt.
Note: If the device is in Master mode and it cannot be ensured that the SS pin will stay high between two
transmissions, the status of the Master bit (the MASTER bit in SPIn.CTRLA) has to be checked before a new byte is
written. After the Master bit has been cleared by a low level on the SS line, it must be set by the application to re-
enable the SPI Master mode.
SCK
Write DATA
WRCOL
IF
Slave Buffer Mode with Wait for Receive Bit Written to ‘0’
In Slave mode, if the Wait for Receive bit (BUFWR in SPIn.CRTLB) is written to ‘0’, a dummy byte will be sent before
the transmission of user data starts. Figure 26-3 shows a transmission sequence with this configuration. Notice how
the value 0x45 is written to the Data register (SPIn.DATA) but never transmitted.
Figure 26-3. SPI Timing Diagram in Buffer Mode with BUFWR in SPIn.CTRLB Written to ‘0’
SS
SCK
Write DATA
DREIF
TXCIF
RXCIF
Slave Buffer Mode with Wait for Receive Bit Written to ‘1’
In Slave mode, if the Wait for Receive bit (BUFWR in SPIn.CRTLB) is written to ‘1’, the transmission of user data
starts as soon as the SS pin is driven low. Figure 26-4 shows a transmission sequence with this configuration. Notice
how the value 0x45 is written to the Data register (SPIn.DATA) but never transmitted.
Figure 26-4. SPI Timing Diagram in Buffer Mode with CTRLB.BUFWR Written to ‘1’
SS
SCK
Write DATA
DREIF
TXCIF
RXCIF
Note: In Slave mode, the SPI state machine will be reset when the SS pin is driven high. If the SS pin is driven high
during a transmission, the SPI will stop sending and receiving data immediately and both data received and data sent
must be considered lost. As the SS pin is used to signal the start and end of a transfer, it is useful for achieving
packet/byte synchronization and keeping the Slave bit counter synchronized with the master clock generator.
The SPI data transfer formats are shown below. Data bits are shifted out and latched in on opposite edges of the
SCK signal, ensuring sufficient time for data signals to stabilize.
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle.
Figure 26-5. SPI Data Transfer Modes
Cycle # 1 2 3 4 5 6 7 8
SPI Mode 0
SS
SCK
Sampling
MISO 1 2 3 4 5 6 7 8
MOSI 1 2 3 4 5 6 7 8
Cycle # 1 2 3 4 5 6 7 8
SPI Mode 1
SS
SCK
Sampling
MISO 1 2 3 4 5 6 7 8
MOSI 1 2 3 4 5 6 7 8
Cycle # 1 2 3 4 5 6 7 8
SPI Mode 2
SS
SCK
Sampling
MISO 1 2 3 4 5 6 7 8
MOSI 1 2 3 4 5 6 7 8
Cycle # 1 2 3 4 5 6 7 8
SPI Mode 3
SS
SCK
Sampling
MISO 1 2 3 4 5 6 7 8
MOSI 1 2 3 4 5 6 7 8
26.3.2.4 Events
The SPI can generate the following events:
26.3.2.5 Interrupts
Table 26-5. Available Interrupt Vectors and Sources
Conditions
Name Vector Description
Normal Mode Buffer Mode
• SSI: Slave Select Trigger Interrupt
• IF: Interrupt Flag interrupt • DRE: Data Register Empty interrupt
SPIn SPI interrupt
• WRCOL: Write Collision interrupt • TXC: Transfer Complete interrupt
• RXC: Receive Complete interrupt
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
26.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DORD MASTER CLK2X PRESC[1:0] ENABLE
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
26.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
BUFEN BUFWR SSD MODE[1:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: INTCTRL
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RXCIE TXCIE DREIE SSIE IE
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: INTFLAGS
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
IF WRCOL
Access R/W R/W
Reset 0 0
Name: INTFLAGS
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RXCIF TXCIF DREIF SSIF BUFOVF
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
26.5.6 Data
Name: DATA
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
27.1 Features
• Two-Wire Communication Interface
• Philips I2C Compatible
– Standard mode
– Fast mode
– Fast mode Plus
• System Management Bus (SMBus) 2.0 Compatible
– Support arbitration between Start/repeated Start and data bit
– Slave arbitration allows support for the Address Resolution Protocol (ARP)
– Configurable SMBus Layer 1 time-outs in hardware
• Independent Master and Slave Operation
– Combined (same pins)
– Single or multi-master bus operation with full arbitration support
• Hardware Support for Slave Address Match
– Operates in all Sleep modes
– 7-bit address recognition
– General call address recognition
– Support for address range masking or secondary address match
• Input Filter for Bus Noise Suppression
• Smart Mode Support
27.2 Overview
The Two-Wire Interface (TWI) is a bidirectional, two-wire communication interface (bus) with a Serial Data Line (SDA)
and a Serial Clock Line (SCL).
The TWI bus connects one or several slave devices to one or several master devices. Any device connected to the
bus can act as a master, a slave, or both. The master generates the SCL by using a Baud Rate Generator (BRG) and
initiates data transactions by addressing one slave and telling whether it wants to transmit or receive data. The BRG
is capable of generating the Standard mode (Sm) and Fast mode (Fm, Fm+) bus frequencies from 100 kHz up to 1
MHz.
The TWI will detect Start and Stop conditions, bus collisions and bus errors. Arbitration lost, errors, collision, and
clock hold are also detected and indicated in separate status flags available in both Master and Slave modes.
The TWI supports multi-master bus operation and arbitration. An arbitration scheme handles the case where more
than one master tries to transmit data at the same time. The TWI also supports Smart mode, which can auto-trigger
operations and thus reduce software complexity. The TWI supports Quick Command mode where the master can
address a slave without exchanging data.
RxDATA RxDATA ==
Figure 27-2. Basic TWI Transaction Diagram Topology for a 7-bit Address Bus
SDA
Direction
Transaction
Bus Driver Special Bus Conditions
'1' '0'
'0' '1'
27.3.2.1 Initialization
If used, the following bits must be configured before enabling the TWI device:
• The SDA Setup Time (SDASETUP) bit from the Control A (TWIn.CTRLA) register
• The SDA Hold Time (SDAHOLD) bit field from the Control A (TWIn.CTRLA) register
• The FM Plus Enable (FMPEN) bit from the Control A (TWIn.CTRLA) register
When an interrupt flag is set to ‘1’, the SCL is forced low. This will give the master time to respond or handle any
data, and will, in most cases, require software interaction. Clearing the interrupt flags releases the SCL. The number
of interrupts generated is kept to a minimum by an automatic handling of most conditions.
THIGH TLOW
TOF TSP TR
SCL
THD;STA TSU;DAT THD;DAT TSU;STO TBUF
TSU;STA
SDA
S P S
The SCL clock is designed to have a 50/50 duty cycle, where TOF is considered a part of TLOW. THIGH will not start
until a high state of SCL has been detected.The BAUD bit field in the TWIn.MBAUD register and the SCL frequency
are related by the following formula:
����_���
���� = (1)
10 + 2 × ���� + ����_��� × ��
���� + 5
���� = − ��� (3)
����_���
3. Check if your TLOW from equation 3 is above the specified minimum of the desired mode (TLOW_Sm= 4700 ns,
TLOW_Fm= 1300 ns, TLOW_Fm+= 500 ns)
– If the calculated TLOW is above the limit, use the BAUD value from equation 2
– If the limit is not met, calculate a new BAUD value using equation 4 below, where TLOW_mode is either
TLOW_Sm, TLOW_Fm, or TLOW_Fm+ from the mode specifications:
RESET
UNKNOWN
(0b00)
changes back to Idle. If a collision is detected, the arbitration is lost and the bus state becomes Busy until a
Stop condition is detected.
P P
Sr A M3 Sr A Sr
M4 BUSY
M4 BUSY
P P
IF Interrupt flag raised
Mn Diagram cases
Case M1: Address Packet Transmit Complete - Direction Bit Set to ‘0’
If a slave device responds to the address packet with an ACK, the Write Interrupt Flag (WIF) is set to ‘1’, the
Received Acknowledge (RXACK) flag is set to ‘0’, and the Clock Hold (CLKHOLD) flag is set to ‘1’. The WIF, RXACK
and CLKHOLD flags are located in the Master Status (TWIn.MSTATUS) register.
The clock hold is active at this point, forcing the SCL low. This will stretch the low period of the clock to slow down the
overall clock frequency, forcing delays required to process the data and preventing further activity on the bus.
The software can prepare to:
• Transmit data packets to the slave
Case M2: Address Packet Transmit Complete - Direction Bit Set to ‘1’
If a slave device responds to the address packet with an ACK, the RXACK flag is set to ‘0’, and the slave can start
sending data to the master without any delays because the slave owns the bus at this moment. The clock hold is
active at this point, forcing the SCL low.
The software can prepare to:
• Read the received data packet from the slave
Case M3: Address Packet Transmit Complete - Address not Acknowledged by Slave
If no slave device responds to the address packet, the WIF and the RXACK flags will be set to ‘1’. The clock hold is
active at this point, forcing the SCL low.
The missing ACK response can indicate that the I2C slave is busy with other tasks, or it is in a Sleep mode, and it is
not able to respond.
The software can prepare to take one of the following actions:
• Retransmit the address packet
• Complete the transaction by issuing a Stop condition in the Command (MCMD) bit field from the Master Control
B (TWIn.MCTRLB) register, which is the recommended action
bus error occurred during the procedure. An arbitration lost during the sending of the data packet is treated in the
same way as the above M4 case.
The RIF, CLKHOLD, ARBLOST and WIF flags are all located in the Master Status (TWIn.MSTATUS) register.
Note: The RIF and WIF flags are mutually exclusive and cannot be set simultaneously.
P S3 P S3 P S3
S4 A Sr S4 A Sr S4
S3 S ADDRESS R IF A IF S2 DATA A
P S3 P S3 P S3
Sn Diagram cases
27.3.3.1 SMBus
If the TWI is used in an SMBus environment, the Inactive Bus Time-Out (TIMEOUT) bit field from the Master Control
A (TWIn.MCTRLA) register must be configured. It is recommended to write to the Master Baud Rate (TWIn.MBAUD)
register before setting the time-out because it is dependent on the baud rate setting.
A frequency of 100 kHz can be used for the SMBus environment. For the Standard mode (Sm) and Fast mode (Fm),
the operating frequency has slew rate limited output, while for the Fast mode Plus (Fm+), it has x10 output drive
strength.
The TWI also allows for an SMBus compatible SDA hold time configured in the SDA Hold Time (SDAHOLD) bit field
from the Control A (TWIn.CTRLA) register.
DEVICE1_SDA
DEVICE2_SDA
SDA
bit 7 bit 6 bit 5 bit 4
(wired-AND)
SCL
S
The Quick Command mode is SMBus specific, where the R/W bit can be used to turn a device function on/off or to
enable/disable a low-power Standby mode. This mode can be enabled to auto-trigger operations and reduce the
software complexity.
After the master receives an ACK from the slave, either the Read Interrupt Flag (RIF) or Write Interrupt Flag (WIF)
will be set, depending on the value of the R/W bit. When either the RIF or WIF flag is set after issuing a Quick
Command, the TWI will accept a Stop command by writing the Command (MCMD) bit field in the Master Control B
(TWIn.MCTRLB) register.
The RIF and WIF flags, together with the value of the last Received Acknowledge (RXACK) flag are all located in the
Master Status (TWIn.MSTATUS) register.
Figure 27-8. Quick Command Frame Format
BUSY
SW Software interaction
27.3.4 Interrupts
Table 27-1. Available Interrupt Vectors and Sources
Master TWI Master interrupt • RIF: Read Interrupt Flag in TWIn.MSTATUS is set to ‘1’
• WIF: Write Interrupt Flag in TWIn.MSTATUS is set to ‘1’
When an interrupt condition occurs, the corresponding interrupt flag is set in the Master Status (TWIn.MSTATUS)
register or the Slave Status (TWIn.SSTATUS) register.
When several interrupt request conditions are supported by an interrupt vector, the interrupt requests are ORed
together into one combined interrupt request to the interrupt controller. The user must read the Interrupt flags from
the TWIn.MSTATUS register or the TWIn.SSTATUS register, to determine which of the interrupt conditions are
present.
27.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SDASETUP SDAHOLD[1:0] FMPEN
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: DBGCTRL
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: MCTRLA
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RIEN WIEN QCEN TIMEOUT[1:0] SMEN ENABLE
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Name: MCTRLB
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
FLUSH ACKACT MCMD[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Notes:
1. The ACKACT bit and the MCMD bit field can be written at the same time.
2. For a master write operation, the TWI will wait for new data to be written to the Master Data (TWIn.MDATA)
register.
Name: MSTATUS
Offset: 0x05
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RIF WIF CLKHOLD RXACK ARBLOST BUSERR BUSSTATE[1:0]
Access R/W R/W R/W R R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
The BUSERR flag can be cleared by choosing one of the following methods:
1. Writing a ‘1’ to it.
2. Writing to the Master Address (TWIn.MADDR) register.
The TWI bus error detector is part of the TWI Master circuitry. For the bus errors to be detected, the TWI Master must
be enabled (ENABLE bit in TWIn.MCTRLA is ‘1’), and the main clock frequency must be at least four times the SCL
frequency.
Name: MBAUD
Offset: 0x06
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
BAUD[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: MADDR
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: MDATA
Offset: 0x08
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: SCTRLA
Offset: 0x09
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DIEN APIEN PIEN PMEN SMEN ENABLE
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: SCTRLB
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ACKACT SCMD[1:0]
Access R/W R/W R/W
Reset 0 0 0
Note: 1. The ACKACT bit and the SCMD bit field can be written at the same time. The ACKACT will be updated
before the command is triggered.
Name: SSTATUS
Offset: 0x0B
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DIF APIF CLKHOLD RXACK COLL BUSERR DIR AP
Access R/W R/W R R R/W R/W R R
Reset 0 0 0 0 0 0 0 0
The TWI bus error detector is part of the TWI Master circuitry. For the bus errors to be detected by the slave, the TWI
Master must be enabled, and the main clock frequency must be at least four times the SCL frequency. The TWI
Master can be enabled by writing a ‘1’ to the ENABLE bit in the TWIn.MCTRLA register.
Name: SADDR
Offset: 0x0C
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: SDATA
Offset: 0x0D
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: SADDRMASK
Offset: 0x0E
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ADDRMASK[6:0] ADDREN
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
28.1 Features
• CRC-16-CCITT
• Check of the Entire Flash Section, Application Code, and/or Boot Section
• Selectable NMI Trigger on Failure
• User-Configurable Check During Internal Reset Initialization
28.2 Overview
A Cyclic Redundancy Check (CRC) takes a data stream of bytes from the NVM (either the entire Flash, only the Boot
section, or both the Boot section and the application code section) and generates a checksum. The CRC peripheral
(CRCSCAN) can be used to detect errors in the program memory.
The last location in the section to check has to contain the correct pre-calculated 16-bit checksum for comparison. If
the checksum calculated by the CRCSCAN and the pre-calculated checksums match, a status bit is set. If they do
not match, the Status register (CRCSCAN.STATUS) will indicate that it failed. The user can choose to let the
CRCSCAN generate a Non-Maskable Interrupt (NMI) if the checksums do not match.
An n-bit CRC applied to a data block of arbitrary length will detect any single alteration (error burst) up to n bits in
length. For longer error bursts a fraction 1-2-n will be detected.
The CRC generator supports CRC-16-CCITT.
Polynomial:
• CRC-16-CCITT: x16 + x12 + x5 + 1
The CRC reads byte-by-byte the content of the section(s) it is set up to check, starting with byte 0, and generates a
new checksum per byte. The byte is sent through a shift register as depicted below, starting with the Most Significant
bit. If the last bytes in the section contain the correct checksum, the CRC will pass. See 28.3.2.1 Checksum for how
to place the checksum. The initial value of the Checksum register is 0xFFFF.
Figure 28-1. CRC Implementation Description
data
15
x x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0
Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D
Source
CTRLB
CRC BUSY
CTRLA
Enable, calculation
Reset STATUS
CRC OK
CHECKSUM
NMI Req
28.3.1 Initialization
To enable a CRC in software (or via the debugger):
1. Write the Source (SRC) bit field of the Control B register (CRCSCAN.CTRLB) to select the desired mode and
source settings.
2. Enable the CRCSCAN by writing a ‘1’ to the ENABLE bit in the Control A register (CRCSCAN.CTRLA).
3. The CRC will start after three cycles. The CPU will continue executing during these three cycles.
The CRCSCAN can be configured to perform a code memory scan before the device leaves Reset. If this check fails,
the CPU is not allowed to start normal code execution. This feature is enabled and controlled by the CRCSRC field in
FUSE.SYSCFG0, see the Fuses chapter for more information.
If this feature is enabled, a successful CRC check will have the following outcome:
• Normal code execution starts
• The ENABLE bit in CRCSCAN.CTRLA will be ‘1’
• The SRC bit field in CRCSCAN.CTRLB will reflect the checked section(s)
• The OK flag in CRCSCAN.STATUS will be ‘1’
If this feature is enabled, a non-successful CRC check will have the following outcome:
• Normal code execution does not start, the CPU will hang executing no code
• The ENABLE bit in CRCSCAN.CTRLA will be ‘1’
• The SRC bit field in CRCSCAN.CTRLB will reflect the checked section(s)
• The OK flag in CRCSCAN.STATUS will be ‘0’
• This condition may be observed using the debug interface
28.3.2 Operation
When the CRC is operating in Priority mode, the CRC peripheral has priority access to the Flash and will stall the
CPU until completed.
In Priority mode the CRC fetches a new word (16-bit) on every third main clock cycle, or when the CRC peripheral is
configured to do a scan from start-up.
28.3.2.1 Checksum
The pre-calculated checksum must be present in the last location of the section to be checked. If the BOOT section is
to be checked, the checksum must be saved in the last bytes of the BOOT section, and similarly for APPLICATION
and the entire Flash. Table 28-1 shows explicitly how the checksum must be stored for the different sections. Also,
see the CRCSCAN.CTRLB register description for how to configure which section to check and the device fuse
description for how to configure the BOOTEND and APPEND fuses.
Table 28-1. Placement of the Pre-Calculated Checksum in Flash
28.3.3 Interrupts
Table 28-2. Available Interrupt Vectors and Sources
When the interrupt condition occurs the OK flag in the Status (CRCSCAN.STATUS) register is cleared to ‘0’.
A Non-Maskable Interrupt (NMI) is enabled by writing a ‘1’ to the respective Enable (NMIEN) bit in the Control A
(CRCSCAN.CTRLA) register, but can only be disabled with a System Reset. An NMI is generated when the OK flag
in the CRCSCAN.STATUS register is cleared, and the NMIEN bit is ‘1’. The NMI request remains active until a
System Reset and cannot be disabled.
An NMI can be triggered even if interrupts are not globally enabled.
– Writing the OK bit to ‘0’ can trigger a Non-Maskable Interrupt (NMI) if the NMIEN bit in CRCSCAN.CTRLA
is ‘1’. If an NMI has been triggered, no writes to the CRCSCAN are allowed.
– Writing the OK bit to ‘1’ will make the OK bit read as ‘1’ when the BUSY bit in CRCSCAN.STATUS is ‘0’.
Writes to CRCSCAN.CTRLA and CRCSCAN.CTRLB from the debugger are treated in the same way as writes from
the CPU.
28.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RESET NMIEN ENABLE
Access R/W R/W R/W
Reset 0 0 0
28.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
The CRCSCAN.CTRLB register contains the mode and source settings for the CRC. It is not writable when the CRC
is busy, or when an NMI has been triggered.
Bit 7 6 5 4 3 2 1 0
MODE[1:0] SRC[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
28.5.3 Status
Name: STATUS
Offset: 0x02
Reset: 0x02
Property: -
Bit 7 6 5 4 3 2 1 0
OK BUSY
Access R R
Reset 1 0
Bit 1 – OK CRC OK
When this bit is read as ‘1’, the previous CRC completed successfully. The bit is set to ‘1’ by default before a CRC
scan is run. The bit is not valid unless BUSY is ‘0’.
29.1 Features
• Glue Logic for General Purpose PCB Design
• Up to Two Programmable Look-up Tables LUT[1:0]
• Combinatorial Logic Functions: Any Logic Expression That Is a Function of up to Three Inputs
• Sequential Logic Functions:
– Gated D Flip-Flop
– JK Flip-Flop
– Gated D Latch
– RS Latch
• Flexible Look-up Table Inputs Selection:
– I/Os
– Events
– Subsequent LUT output
– Internal peripherals
• Analog comparator
• Timer/counters
• USART
• SPI
• Clocked by System Clock or Other Peripherals
• The Output Can Be Connected to I/O Pins or Event System
• Optional Synchronizer, Filter, or Edge Detector Available on Each LUT Output
29.2 Overview
The Configurable Custom Logic (CCL) is a programmable logic peripheral that can be connected to the device pins,
events or other internal peripherals. The CCL can serve as “glue logic” between the device peripherals and external
devices. The CCL can eliminate the need for external logic components, and can also help the designer to overcome
real-time constraints by combining core independent peripherals to handle the most time-critical parts of the
application independent of the CPU.
The CCL peripheral has a number of Look-up Tables (LUT). Each LUT consists of three inputs, a truth table, and a
filter/edge detector. Each LUT can generate an output as a user-programmable logic expression with three inputs.
The inputs can be individually masked.
The output can be generated from the inputs combinatorially and be filtered to remove spikes. An optional sequential
module can be enabled. The inputs to the sequential module are individually controlled by two independent, adjacent
LUT (LUT0/LUT1) outputs, enabling complex waveform generation.
Internal
FILTSEL EDGEDET SEQSEL
Events
I/O
Peripherals
TRUTH
Filter/ Edge
CLKSRC
Synch Detector LUT0-OUT
LUT0-IN[2] CLK_MUX_OUT
Sequential
clkCCL
ENABLE
LUT1
INSEL
Internal
FILTSEL EDGEDET
Events
I/O
Peripherals
TRUTH
Filter/ Edge
CLKSRC LUT1-OUT
Synch Detector
LUT1-IN[2] CLK_MUX_OUT
clkCCL
ENABLE
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be
mapped to several pins.
29.2.3.1 Clocks
By default, the CCL is using the peripheral clock of the device (CLK_PER).
Alternatively, the CCL can be clocked by a peripheral input that is available on LUT n input line 2 (LUTn_IN[2]). This
is configured by writing a ‘1’ to the Clock Source Selection (CLKSRC) bit in the LUT n Control A (CCL.LUTnCTRLA)
register. The Sequential block and the even LUT in the LUT pair (SEQn.clk = LUT2n.clk) are clocked by the same
clock. It is advised to disable the peripheral by writing a ‘0’ to the Enable (ENABLE) bit in the Control A (CCL.CTRLA)
register before configuring the CLKSRC bit in CCL.LUTnCTRLA.
Alternatively, the input line 2 (IN[2]) of an LUT can be used to clock the LUT and the corresponding Sequential block.
This is enabled by writing a ‘1’ to the CLKSRC bit in the CCL.LUTnCTRLA register.
The CCL must be disabled before changing the LUT clock source: Write a ‘0’ to the ENABLE bit in CCL.CTRLA.
29.2.3.3 Interrupts
Not applicable.
29.3.1 Initialization
The following bits are enable-protected, meaning that they can only be written when the corresponding even LUT is
disabled (ENABLE = ‘0’ in CCL.LUT0CTRLA):
• Sequential Selection (SEQSEL) in Sequential Control 0 (CCL.SEQCTRL0) register
The following registers are enable-protected, meaning that they can only be written when the corresponding LUT is
disabled (ENABLE = ‘0’ in CCL.LUT0CTRLA):
• LUT n Control x (CCL.LUTnCTRLx) register, except the ENABLE bit
Enable-protected bits in the CCL.LUTnCTRLx registers can be written at the same time as the ENABLE bit in
CCL.LUTnCTRLx is written to ‘1’, but not at the same time as the ENABLE bit is written to ‘0’.
The enable-protection is denoted by the enable-protected property in the register description.
29.3.2 Operation
...........continued
IN[2] IN[1] IN[0] OUT
1 0 0 TRUTH[4]
1 0 1 TRUTH[5]
1 1 0 TRUTH[6]
1 1 1 TRUTH[7]
Input Overview
The inputs can be individually:
• Masked
• Driven by Peripherals:
– Analog Comparator (AC) output
– Timer/Counters (TC) waveform outputs
• Driven by Internal Events from Event System
• Driven by Other CCL Submodules
The input selection for each input y of LUT n is configured by writing the input y source selection bit in the LUT n
Control x=[B,C] registers:
• INSEL0 in CCL.LUTnCTRLB
• INSEL1 in CCL.LUTnCTRLB
• INSEL2 in CCL.LUTnCTRLC
LUT0 SEQ 0
CTRL
(ENABLE)
LUT1
Peripherals
The different peripherals on the three input lines of each LUT are selected by writing to the respective LUT n Input y
bit fields in the LUT n Control B and C registers:
• INSEL0 in CCL.LUTnCTRLB
• INSEL1 in CCL.LUTnCTRLB
• INSEL2 in CCL.LUTnCTRLC
29.3.2.4 Filter
By default, the LUT output is a combinational function of the LUT inputs. This may cause some short glitches when
the inputs change the value. These glitches can be removed by clocking through filters if demanded by application
needs.
The Filter Selection (FILTSEL) bits in the LUT Control A (CCL.LUTnCTRLA) registers define the digital Filter options.
When a filter is enabled, the output will be delayed by two to five CLK cycles (a peripheral clock or alternative clock).
All internal Filter logic is cleared one clock cycle after the corresponding LUT is disabled.
Figure 29-5. Filter
FILTSEL
Input
OUT
G
D Q D Q D Q D Q
R R R R
CLK_MUX_OUT
CLR
CLK_MUX_OUT
odd LUT
R G D OUT
1 X X Clear
0 1 1 Set
0 Clear
0 X Hold state (no change)
JK Flip-Flop (JK)
The J-input is driven by the even LUT output (LUT2n), and the K-input is driven by the odd LUT output (LUT2n+1).
even LUT
CLK_MUX_OUT
odd LUT
R J K OUT
1 X X Clear
0 0 0 Hold state (no change)
0 0 1 Clear
0 1 0 Set
0 1 1 Toggle
odd LUT G
G D OUT
0 X Hold state (no change)
1 0 Clear
1 1 Set
RS Latch (RS)
The S-input is driven by the even LUT output (LUT2n), and the R-input is driven by the odd LUT output (LUT2n+1).
Figure 29-10. RS Latch
odd LUT R
S R OUT
0 0 Hold state (no change)
0 1 Clear
1 0 Set
1 1 Forbidden state
Edge Filter
IN[2] Detector
CLK_MUX_OUT
CLK_CCL
CLKSRC
LUT0 Sequential
logic
Edge Filter
IN[2] Detector
CLK_MUX_OUT
CLK_CCL
CLKSRC
LUT1
When the Clock Source (CLKSRC) bit is ‘1’, IN[2] is used to clock the corresponding filter and edge detector
(CLK_MUX_OUT). The Sequential logic is clocked by CLK_MUX_OUT of the even LUT in the pair. When the
CLKSRC bit is ‘1’, IN[2] is treated as MASKed (low) in the truth table.
The CCL peripheral must be disabled while changing the clock source to avoid undetermined outputs from the
peripheral.
29.3.3 Events
The CCL can generate the following output event:
• LUTnOUT: Look-up Table Output Value
The CCL can take the following actions on an input event:
• INx: The event is used as input for the truth table
If the Clock Source (CLKSRC) bit in the LUT n Control A (CCL.LUTnCTRLA) register is written to ‘1’, the LUT input 2
(IN[2]) will always clock the Filter, edge detector, and Sequential block. The availability of the IN[2] clock in sleep
modes will depend on the sleep settings of the peripheral employed.
29.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUNSTDBY ENABLE
Access R/W R/W
Reset 0 0
Name: SEQCTRL0
Offset: 0x01 [ID-00000485]
Reset: 0x00
Property: Enable-Protected
Bit 7 6 5 4 3 2 1 0
SEQSEL[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: LUTCTRLA
Offset: 0x05 + n*0x04 [n=0..1]
Reset: 0x00
Property: Enable-Protected
Bit 7 6 5 4 3 2 1 0
EDGEDET CLKSRC FILTSEL[1:0] OUTEN ENABLE
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: LUTCTRLB
Offset: 0x06 + n*0x04 [n=0..1]
Reset: 0x00
Property: Enable-Protected
Notes:
1. SPI connections to the CCL work only in master SPI mode.
2. USART connections to the CCL work only in asynchronous/synchronous USART Master mode.
Bit 7 6 5 4 3 2 1 0
INSEL1[3:0] INSEL0[3:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: LUTCTRLC
Offset: 0x07 + n*0x04 [n=0..1]
Reset: 0x00
Property: Enable-Protected
Bit 7 6 5 4 3 2 1 0
INSEL2[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
29.5.6 TRUTHn
Name: TRUTH
Offset: 0x08 + n*0x04 [n=0..1]
Reset: 0x00
Property: Enable-Protected
Bit 7 6 5 4 3 2 1 0
TRUTH[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
30.1 Features
• 50 ns Response Time for Supply Voltage Above 2.7V
• Zero-Cross Detection
• Selectable Hysteresis:
– None
– 10 mV
– 25 mV
– 50 mV
• Analog Comparator Output Available on Pin
• Comparator Output Inversion Available
• Flexible Input Selection:
– One Positive pins
– One Negative pins
– Output from the DAC
– Internal reference voltage
• Interrupt Generation On:
– Rising edge
– Falling edge
– Both edges
• Event Generation:
– Comparator output
30.2 Overview
The Analog Comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this
comparison. The AC can be configured to generate interrupt requests and/or events upon several different
combinations of input change.
The dynamic behavior of the AC can be adjusted by a hysteresis feature. The hysteresis can be customized to
optimize the operation for each application.
The input selection includes analog port pins, DAC output and internal reference voltage. The analog comparator
output state can also be output on a pin for use by external devices.
An AC has one positive input and one negative input. The positive input source is one of the analog input pins. The
negative input is chosen either from analog input pins or from internal inputs, such as an internal voltage reference.
The digital output from the comparator is ‘1’ when the difference between the positive and the negative input voltage
is positive, and ‘0’ otherwise.
Note: Refer to 30.1 Features for the number of AINN and AINP.
30.2.3.1 Clocks
This peripheral depends on the peripheral clock.
30.2.3.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
30.2.3.4 Events
The events of this peripheral are connected to the Event System.
30.3.1 Initialization
For basic operation, follow these steps:
1. Configure the desired input pins in the port peripheral.
2. Select the positive and negative input sources by writing the Positive and Negative Input MUX Selection
(MUXPOS and MUXNEG) bit fields in the MUX Control A (ACn.MUXCTRLA) register.
3. Optional: Enable the output to pin by writing a ‘1’ to the Output Pad Enable (OUTEN) bit in the Control A
(ACn.CTRLA) register.
4. Enable the AC by writing a ‘1’ to the ENABLE bit in the ACn.CTRLA register.
During the start-up time after enabling the AC, the output of the AC may be invalid.
The start-up time of the AC by itself is at most 2.5 µs. If an internal reference is used, the reference start-up time is
normally longer than the AC start-up time. The VREF start-up time is 60 µs at most.
30.3.2 Operation
30.3.2.1 Input Hysteresis
Applying an input hysteresis helps to prevent constant toggling of the output when the noise-afflicted input signals are
close to each other.
The input hysteresis can either be disabled or have one of three levels. The hysteresis is configured by writing to the
Hysteresis Mode Select (HYSMODE) bit field in the Control A (ACn.CTRLA) register.
30.3.3 Events
The AC will generate the following event automatically when the AC is enabled:
• The digital output from the AC (OUT in the block diagram) is available as an Event System source. The events
from the AC are asynchronous to any clocks in the device.
30.3.4 Interrupts
Table 30-2. Available Interrupt Vectors and Sources
When an Interrupt condition occurs, the corresponding Interrupt flag is set in the STATUS (ACn.STATUS) register.
An interrupt source is enabled or disabled by writing to the corresponding bit in the peripheral’s Interrupt Control
(ACn.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled and the Interrupt flag is set.
The interrupt request remains active until the Interrupt flag is cleared. See the ACn.STATUS register description for
details on how to clear Interrupt flags.
30.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUNSTDBY OUTEN INTMODE[1:0] LPMODE HYSMODE[1:0] ENABLE
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: MUXCTRLA
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
INVERT MUXPOS[1:0] MUXNEG[1:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: INTCTRL
Offset: 0x06
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMP
Access R/W
Reset 0
30.5.4 Status
Name: STATUS
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
STATE CMP
Access R R/W
Reset 0 0
31.1 Features
• 10-Bit Resolution
• 0V to VDD Input Voltage Range
• Multiple Internal ADC Reference Voltages
• External Reference Input
• Free-Running and Single Conversion Mode
• Interrupt Available on Conversion Complete
• Optional Interrupt on Conversion Results
• Temperature Sensor Input Channel
• Optional Event-Triggered Conversion
• Window Comparator Function for Accurate Monitoring or Defined Thresholds
• Accumulation up to 64 Samples per Conversion
31.2 Overview
The Analog-to-Digital Converter (ADC) peripheral produces 10-bit results. The ADC input can either be internal (e.g.,
a voltage reference) or external through the analog input pins. The ADC is connected to an analog multiplexer, which
allows the selection of multiple single-ended voltage inputs. The single-ended voltage inputs refer to 0V (GND).
The ADC supports sampling in bursts where a configurable number of conversion results are accumulated into a
single ADC result (Sample Accumulation). Further, a sample delay can be configured to tune the ADC sampling
frequency associated with a single burst. This is to tune the sampling frequency away from any harmonic noise
aliased with the ADC sampling frequency (within the burst) from the sampled signal. An automatic sampling delay
variation feature can be used to randomize this delay to slightly change the time between samples.
The ADC input signal is fed through a sample-and-hold circuit that ensures that the input voltage to the ADC is held
at a constant level during sampling.
The selectable voltage references from the internal Voltage Reference (VREF) peripheral, are VDD supply voltage, or
external VREF pin (VREFA).
A window compare feature is available for monitoring the input signal and can be configured to only trigger an
interrupt on user-defined thresholds for under, over, inside, or outside a window, with minimum software intervention
required.
AIN0 VDD
AIN1
..
.
AINn
DAC AD C RES
"accumulate"
VREF
"convert"
"sample"
"enable"
> WCMP
< (IRQ)
31.3.1 Initialization
The following steps are recommended to initialize the ADC operation:
1. Configure the resolution by writing to the Resolution Selection (RESSEL) bit in the Control A (ADCn.CTRLA)
register.
2. Optional: Enable the Free-Running mode by writing a ‘1’ to the Free-Running (FREERUN) bit in
ADCn.CTRLA.
3. Optional: Configure the number of samples to be accumulated per conversion by writing the Sample
Accumulation Number Select (SAMPNUM) bits in the Control B (ADCn.CTRLB) register.
4. Configure a voltage reference by writing to the Reference Selection (REFSEL) bit in the Control C
(ADCn.CTRLC) register. The default is the internal voltage reference of the device (VREF, as configured there).
5. Configure the CLK_ADC by writing to the Prescaler (PRESC) bit field in the Control C (ADCn.CTRLC) register.
6. Configure an input by writing to the MUXPOS bit field in the MUXPOS (ADCn.MUXPOS) register.
7. Optional: Enable Start Event input by writing a ‘1’ to the Start Event Input (STARTEI) bit in the Event Control
(ADCn.EVCTRL) register. Configure the Event System accordingly.
8. Enable the ADC by writing a ‘1’ to the ENABLE bit in ADCn.CTRLA.
Following these steps will initialize the ADC for basic measurements, which can be triggered by an event (if
configured) or by writing a ‘1’ to the Start Conversion (STCONV) bit in the Command (ADCn.COMMAND) register.
31.3.2 Operation
8-bit PRESCALER
CLK_PER
CLK_PER/128
CLK_PER/256
CLK_PER/16
CLK_PER/32
CLK_PER/64
CLK_PER/4
CLK_PER/2
CLK_PER/8
PRESC
CTRLC
CLK_PER
STCONV
CLK_PER/2
CLK_PER/4
CLK_PER/8
CLK_ADC
ENABLE
STCONV
RESRDY
RES Result
conversion
sample complete
Both sampling time and sampling length can be adjusted using the Sample Delay bit field in the Control D
(ADCn.CTRLD) register and the Sample Length bit field in the Sample Control (ADCn.SAMPCTRL) register. Both of
these control the ADC sampling time in some CLK_ADC cycles. This allows sampling of high-impedance sources
without relaxing conversion speed. See the register description for further information. Total sampling time is given
by:
2 + SAMPDLY + SAMPLEN
SampleTime =
�CLK_ADC
Figure 31-5. ADC Timing Diagram - Single Conversion With Delays
1 2 3 4 5 6 7 8 9 10 11 12 13
CLK_ADC
ENABLE
STCONV
RES Result
In Free-Running mode, a new conversion will be started immediately after the conversion completes, while the
STCONV bit is ‘1’. The sampling rate RS in Free-Running mode is calculated by:
�CLK_ADC
�S =
13 + SAMPDLY + SAMPLEN
Figure 31-6. ADC Timing Diagram - Free-Running Conversion
Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2
CLK_ADC
ENABLE
STCONV
RESRDY
RES Result
sample conversion
complete
Once the conversion starts, the channel and reference selections are locked to ensure sufficient sampling time for the
ADC. Continuous updating resumes in the last CLK_ADC clock cycle before the conversion completes (RESRDY in
ADCn.INTFLAGS is set). The conversion starts on the following rising CLK_ADC clock edge after the STCONV bit is
written to ‘1’.
IIH
ADCn
Rin
Cin
IIL
VDD/2
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see description for
REFSEL in ADCn.CTRLC and ADCn.MUXPOS).
RESH and RESL are the high and low bytes of the Result register (ADCn.RES), and TEMPSENSEn are the
respective values from the Signature row.
It is recommended to follow these steps in user code:
3. Enable the Window Comparator and select a mode by writing a non-zero value to the WINCM bit field in
ADCn.CTRLE.
When accumulating multiple samples, the comparison between the result and the threshold will happen after the last
sample was acquired. Consequently, the flag is raised only once, after taking the last sample of the accumulation.
31.3.3 Events
An ADC conversion can be triggered automatically by an event input if the Start Event Input (STARTEI) bit in the
Event Control (ADCn.EVCTRL) register is written to ‘1’.
When a new result can be read from the Result (ADCn.RES) register, the ADC will generate a result ready event.
The event is a pulse with a length of one clock period and handled by the Event System (EVSYS). The ADC result
ready event is always generated when the ADC is enabled.
See also the description of the Asynchronous User Channel n Input Selection in the Event System
(EVSYS.ASYNCUSERn).
31.3.4 Interrupts
Table 31-1. Available Interrupt Vectors and Sources
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
31.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUNSTBY RESSEL FREERUN ENABLE
Access R/W R/W R/W R/W
Reset 0 0 0 0
31.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SAMPNUM[2:0]
Access R/W R/W R/W
Reset 0 0 0
31.5.3 Control C
Name: CTRLC
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SAMPCAP REFSEL[1:0] PRESC[2:0]
Access R R/W R/W R/W R R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
31.5.4 Control D
Name: CTRLD
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
INITDLY[2:0] ASDV SAMPDLY[3:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
31.5.5 Control E
Name: CTRLE
Offset: 0x4
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
WINCM[2:0]
Access R/W R/W R/W
Reset 0 0 0
Name: SAMPCTRL
Offset: 0x5
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SAMPLEN[4:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
31.5.7 MUXPOS
Name: MUXPOS
Offset: 0x06
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
MUXPOS[4:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
31.5.8 Command
Name: COMMAND
Offset: 0x08
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
STCONV
Access R/W
Reset 0
Name: EVCTRL
Offset: 0x09
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
STARTEI
Access R/W
Reset 0
Name: INTCTRL
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
WCMP RESRDY
Access R/W R/W
Reset 0 0
Name: INTFLAGS
Offset: 0x0B
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
WCMP RESRDY
Access R/W R/W
Reset 0 0
Name: DBGCTRL
Offset: 0x0C
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
31.5.13 Temporary
Name: TEMP
Offset: 0x0D
Reset: 0x00
Property: -
The Temporary register is used by the CPU for 16-bit single-cycle access to the 16-bit registers of this peripheral. The
register is common for all the 16-bit registers of this peripheral and can be read and written by software. For more
details on reading and writing 16-bit registers, refer to Accessing 16-Bit Registers in the AVR CPU section.
Bit 7 6 5 4 3 2 1 0
TEMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
31.5.14 Result
Name: RES
Offset: 0x10
Reset: 0x00
Property: -
The ADCn.RESL and ADCn.RESH register pair represents the 16-bit value, ADCn.RES. The low byte [7:0] (suffix L)
is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
If the analog input is higher than the reference level of the ADC, the 10-bit ADC result will be equal the maximum
value of 0x3FF. Likewise, if the input is below 0V, the ADC result will be 0x000. As the ADC cannot produce a result
above 0x3FF values, the accumulated value will never exceed 0xFFC0 even after the maximum allowed 64
accumulations.
Bit 15 14 13 12 11 10 9 8
RES[15:8]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RES[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: WINLT
Offset: 0x12
Reset: 0x00
Property: -
This register is the 16-bit low threshold for the digital comparator monitoring the ADCn.RES register. The ADC itself
has a 10-bit output, RES[9:0], where the MSb is RES[9]. The data format in ADC and Digital Accumulation is 1’s
complement, where 0x0000 represents the zero, and 0xFFFF represents the largest number (full scale).
The ADCn.WINLTH and ADCn.WINLTL register pair represents the 16-bit value, ADCn.WINLT. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
When accumulating samples, the window comparator thresholds are applied to the accumulated value and not on
each sample.
Bit 15 14 13 12 11 10 9 8
WINLT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WINLT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: WINHT
Offset: 0x14
Reset: 0x00
Property: -
This register is the 16-bit high threshold for the digital comparator monitoring the ADCn.RES register. The ADC itself
has a 10-bit output, RES[9:0], where the MSb is RES[9]. The data format in ADC and Digital Accumulation is 1’s
complement, where 0x0000 represents the zero, and 0xFFFF represents the largest number (full scale).
The ADCn.WINHTH and ADCn.WINHTL register pair represents the 16-bit value, ADCn.WINHT. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit 15 14 13 12 11 10 9 8
WINHT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WINHT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
31.5.17 Calibration
Name: CALIB
Offset: 0x16
Reset: 0x01
Property: -
Bit 7 6 5 4 3 2 1 0
DUTYCYC
Access R/W
Reset 1
32.1 Features
• 8-bit Resolution
• Up to 350 ksps Conversion Rate
• High Drive Capabilities (DAC0)
• Functioning as Input to Analog Comparator (AC) or Analog-to-Digital Converter (ADC)
32.2 Overview
The Digital-to-Analog Converter (DAC) converts a digital value written to the Data (DAC.DATA) register to an analog
voltage. The conversion range is between GND and the selected reference voltage.
The DAC features an 8-bit resistor-string type DAC, capable of converting 350,000 samples per second (350 ksps).
The DAC uses the internal Voltage Reference (VREF) as the upper limit for conversion and has one continuous time
output with high drive capabilities, which can drive a 5 kΩ and/or 30 pF load. The DAC conversion can be started
from the application by writing to the Data Conversion registers.
DATA 8
DAC OUT
Output
Driver
VREF
ENABLE
CTRLA
OUTEN
...........continued
Dependency Applicable Peripheral
Debug Yes UPDI
32.2.3.1 Clocks
This peripheral depends on the peripheral clock.
The DAC0 has one analog output pin (OUT) that must be configured before it can be used.
A DAC is also internally connected to the AC and the ADC. To use this internal OUT as input, both output and input
must be configured in their respective registers.
32.2.3.3 Events
Not applicable.
32.2.3.4 Interrupts
Not applicable.
32.3.1 Initialization
To operate the DAC, the following steps are required:
1. Select the DAC reference voltage in the Voltage Reference (VREF) peripheral by writing the DAC and AC
Reference Selection (DACnREFSEL) bits in the Control x (VREF.CTRLx) register.
2. The conversion range is between GND and the selected reference voltage.
3. Configure the further usage of the DAC output:
3.1. Configure an internal peripheral (e.g., AC, ADC) to use the DAC output. Refer to the according
peripheral’s documentation.
3.2. Enable the output to a pin by writing a ‘1’ to the Output Enable (OUTEN) bit in the Control A
(DAC.CTRLA) register. This requires a configuration of the Port peripheral.
For DAC0, either one or both options are valid. Other instances of the DAC only support internal signaling.
4. Write an initial digital value to the Data (DAC.DATA) register.
5. Enable the DAC by writing a ‘1’ to the ENABLE bit in the DAC.CTRLA register.
32.3.2 Operation
32.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUNSTDBY OUTEN ENABLE
Access R/W R/W R/W
Reset 0 0 0
32.5.2 DATA
Name: DATA
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
33.1 Features
• UPDI One-Wire Interface for External Programming and On-Chip-Debugging (OCD)
– Enable programming by high-voltage or fuse
– Uses the RESET pin of the device for programming
– No GPIO pins occupied during the operation
– Asynchronous half-duplex UART protocol towards the programmer
• Programming:
– Built-in error detection and error signature generation
– Override of response generation for faster programming
• Debugging:
– Memory-mapped access to device address space (NVM, RAM, I/O)
– No limitation on the device clock frequency
– Unlimited number of user program breakpoints
– Two hardware breakpoints
– Support for advanced OCD features
• Run-time readout of the CPU Program Counter (PC), Stack Pointer (SP) and Status Register (SREG)
for code profiling
• Detection and signalization of the Break/Stop condition in the CPU
• Program flow control for Run, Stop and Reset debug instructions
– Nonintrusive run-time chip monitoring without accessing the system registers
– Interface for reading the result of the CRC check of the Flash on a locked device
33.2 Overview
The Unified Program and Debug Interface (UPDI) is a proprietary interface for external programming and OCD of a
device.
The UPDI supports programming of Nonvolatile Memory (NVM) space, Flash, EEPROM, fuses, lock bits, and the
user row. Some memory-mapped registers are accessible only with the correct access privilege enabled (key, lock
bits) and only in the OCD Stopped mode or certain Programming modes. These modes are unlocked by sending the
correct key to the UPDI. See the NVMCTRL - Nonvolatile Memory Controller section for programming via the NVM
controller and executing NVM controller commands.
The UPDI is partitioned into three separate protocol layers: the UPDI Physical (PHY) Layer, the UPDI Data Link (DL)
Layer and the UPDI Access (ACC) Layer. The default PHY layer handles bidirectional UART communication over the
UPDI pin line towards a connected programmer/debugger and provides data recovery and clock recovery on an
incoming data frame in the One-Wire Communication mode. Received instructions and corresponding data are
handled by the DL layer, which sets up the communication with the ACC layer based on the decoded instruction.
Access to the system bus and memory-mapped registers is granted through the ACC layer.
Programming and debugging are done through the PHY layer, which is a one-wire UART based on a half-duplex
interface using the RESET pin for data reception and transmission. The clocking of the PHY layer is done by a
dedicated internal oscillator.
The ACC layer is the interface between the UPDI and the connected bus matrix. This layer grants access via the
UPDI interface to the bus matrix with memory-mapped access to system blocks such as memories, NVM, and
peripherals.
The Asynchronous System Interface (ASI) provides direct interface access to select features in the OCD, NVM, and
System Management systems. This gives the debugger direct access to system information without requesting bus
access.
Bus Matrix
NVM
UPDI Pin
(RX/TX Data) UPDI UPDI
Physical Access
layer layer Peripherals
ASI Access
Controller
System
OCD
NVM
33.2.2 Clocks
The PHY layer and the ACC layer can operate on different clock domains. The PHY layer clock is derived from the
dedicated internal oscillator, and the ACC layer clock is the same as the peripheral clock. There is a synchronization
boundary between the PHY and the ACC layer, which ensures correct operation between the clock domains. The
UPDI clock output frequency is selected through the ASI, and the default UPDI clock start-up frequency is 4 MHz
after enabling or resetting the UPDI. The UPDI clock frequency can be changed by writing to the UPDI Clock Divider
Select (UPDICLKDIV) bit field in the ASI Control A (UPDI.ASI_CTRLA) register.
UPDI Controller
SYNCH
UPDI UPDI
Physical Access
layer layer
Clock Clock
Controller Controller
CLK_UPDI
CLK_UPDI
CLK_PER
source
CLK_PER
~ UPDICLKDIV ~
St 0 1 2 3 4 5 6 7 P S1 S2
IDLE
BREAK
SYNCH (0x55)
St P S1 S2
Synch Part
End_synch
ACK (0x40)
St P S1 S2
Frame Description
DATA A DATA frame consists of one Start (St) bit which is always low, eight Data bits, one Parity (P) bit for even
parity and two Stop (S1 and S2) bits which are always high. If the Parity bit or Stop bits have an incorrect
value, an error will be detected and signalized by the UPDI. The parity bit-check in the UPDI can be
disabled by writing to the Parity Disable (PARD) bit in the Control A (UPDI.CTRLA) register, in which case
the parity generation from the debugger is ignored.
IDLE This is a special frame that consists of 12 high bits. This is the same as keeping the transmission line in
an Idle state.
BREAK This is a special frame that consists of 12 low bits. It is used to reset the UPDI back to its default state
and is typically used for error recovery.
SYNCH The SYNCH frame is used by the Baud Rate Generator to set the baud rate for the coming transmission.
A SYNCH character is always expected by the UPDI in front of every new instruction, and after a
successful BREAK has been transmitted.
ACK The ACK frame is transmitted from the UPDI whenever an ST or an STS instruction has successfully
crossed the synchronization boundary and gained bus access. When an ACK is received by the
debugger, the next transmission can start.
The transmission baud rate of the PHY layer is related to the selected UPDI clock, which can be adjusted by writing
to the UPDI Clock Divider Select (UPDICLKDIV) bit field in the ASI Control A (UPDI.ASI_CTRLA) register. The
receive and transmit baud rates are always the same within the accuracy of the auto-baud.
Table 33-1. Recommended UART Baud Rate Based on UPDICLKDIV Setting
0.150 kbps Max. Recommended Baud Rate Min. Recommended Baud Rate
0x1 (16 MHz) 0.9 Mbps 0.300 kbps
The UPDI Baud Rate Generator utilizes fractional baud counting to minimize the transmission error. With the fixed
frame format used by the UPDI, the maximum and recommended receiver transmission error limits can be seen in
the following table:
Table 33-2. Receiver Baud Rate Error
Data + Parity Bits Rslow Rfast Max. Total Error [%] Recommended Max. RX Error [%]
9 96.39 104.76 +4.76/-3.61 +1.5/-1.5
2. It is used by the Baud Rate Generator to set the baud rate for the subsequent transmission. If an invalid
SYNCH character is sent, the next transmission will not be sampled correctly.
33.3.2 Operation
The UPDI must be enabled before the UART communication can start.
Figure 33-4. UPDI Enable Sequence with UPDI PAD Enabled By Fuse
1 Fuse read in. Pull-up enabled. Ready to receive init.
2 Drive low from the debugger to request the UPDI clock.
3 UPDI clock ready; Communication channel ready.
1
2
RESET Hi-Z St D0 D1 D2 D3 D4 D5 D6 D7 Sp
Handshake / BREAK
SYNC (0x55)
TRES
(Auto-baud)
UPDI.rxd (Ignore)
3
UPDI.txd Hi-Z Hi-Z
UPDI.txd = 0
TUPDI
debugger.
Hi-Z Hi-Z
UPDI.txd
Debugger.txd = 0 Debugger.txd = z
TDeb0 TDebZ
To avoid the UPDI from staying enabled if an accidental trigger of the edge detector happens, the UPDI will
automatically disable itself and lower its clock request. See the Disable During Start-up section for more details.
RESET Hi-Z St D0 D1 D2 D3 D4 D5 D6 D7 Sp
Handshake / BREAK
SYNC (0x55)
TRES
(Auto-baud)
UPDI.rxd (Ignore)
3
UPDI.txd Hi-Z Hi-Z
UPDI.txd = 0
TUPDI
debugger.
Hi-Z Hi-Z
UPDI.txd
Debugger.txd = 0 Debugger.txd = z
TDeb0 TDebZ
When the pull-up is detected, the debugger initiates the enable sequence by driving the line low for a duration of
TDeb0.
The negative edge is detected by the UPDI, which starts the UPDI clock. The UPDI will continue to drive the line low
until the clock is stable and ready for the UPDI to use. The duration of TUPDI will vary, depending on the status of the
oscillator when the UPDI is enabled. After this duration, the data line will be released by the UPDI and pulled high.
When the debugger detects that the line is high, the initial SYNCH character (0x55) must be transmitted to
synchronize the UPDI communication data rate. If the Start bit of the SYNCH character is not sent within maximum
TDebZ, the UPDI will disable itself, and the UPDI enabling sequence must be reinitiated. The UPDI is disabled if the
timing is violated to avoid the UPDI being enabled unintentionally.
After successful SYNCH character transmission, the first instruction frame can be transmitted.
(Ignore)
Hi-Z St D0 D1 D2 D3 D4 D5 D6 D7 Sp
UPDIPAD
HV ramp Handshake/BREAK
Debugger.txd = z SYNC (0x55)
THV_ramp TRES
TDebZ (Auto-baud)
Min. is 10 ns
Min. is 1 μs Min. is 10 μs
Max. is 4 ms
Max. is 10 μs Max. is 200 μs
(Ignore)
UPDI.rxd
Hi-Z 2 Hi-Z
UPDI.txd
UPDI.txd = 0
TUPDI
Min. is 10 μs
Max. is 200 μs
debugger Hi-Z Hi-Z
UPDI.txd
Debugger.txd = 0 Debugger.txd = z
TDeb0 TDebZ
HV Min. is 200 ns Min. is 200 μs
debugger Max. is 1 μs Max. is 14 ms
UPDI HV Vdd
When enabled by an HV pulse, only a POR will disable the UPDI configuration on the RESET pin and restore the
default setting. If issuing a UPDI Disable command through the UPDIDIS bit in UPDI.CTRLB, the UPDI will be reset,
and the clock request will be canceled, but the RESET pin will remain in UPDI configuration.
Note: If insufficient external protection is added to the UPDI pin, an ESD pulse can be interpreted by the device as a
high-voltage override and enable the UPDI.
Note: The actual threshold voltage for the UPDI HV activation depends on VDD. See the Electrical Characteristics
for details.
It is always recommended to issue a System Reset before entering the HV programming sequence.
Time-Out Disable
When the start-up negative edge detector releases the pin after the UPDI has received its clock, or when the
regulator is stable and the system has power in a Multi-Voltage system, the default pull-up drives the UPDI pin high. If
the programmer does not detect that the pin is high, and does not initiate a transmission of the SYNCH character
within 16.4 ms at 4 MHz UPDI clock after the UPDI has released the pin, the UPDI will disable itself.
Note: Start-up oscillator frequency is device-dependent. The UPDI will count for 65536 cycles on the UPDI clock
before issuing the time-out.
The UPDI guard time is the minimum Idle time that the connected debugger will experience when waiting for data
from the UPDI. The maximum Idle time is the same as time-out. The Idle time before a transmission will be more than
the expected guard time when the synchronization time plus the data bus accessing time is longer than the guard
time.
It is recommended to always use the insertion of minimum two Guard Time bits on the UPDI side, and one guard time
cycle insertion from the debugger side.
LD 0 0 1 0
Size A - Address Size
0 0 Byte - can address 0-255 B
0 1 Word (2 Bytes) - for memories up to 64 KB in size
ST 0 1 1 0
1 0 3 Bytes - for memories above 64 KB in size
1 1 Reserved
CS Address
Ptr - Pointer Access
0 0 * (ptr)
LDCS 1 0 0 0
0 1 * (ptr++)
1 0 ptr
1 1 Reserved
STCS 1 1 0 0
33.3.3.1 LDS - Load Data from Data Space Using Direct Addressing
The LDS instruction is used to load data from the system bus into the PHY layer shift register for serial readout. The
LDS instruction is based on direct addressing, and the address must be given as an operand to the instruction for the
data transfer to start. The maximum supported size for the address and data is 32 bits. The LDS instruction supports
repeated memory access when combined with the REPEAT instruction.
After issuing the LDS instruction, the number of desired address bytes, as indicated by the Size A field followed by
the output data size, which is selected by the Size B field, must be transmitted. The output data is issued after the
specified Guard Time (GT). When combined with the REPEAT instruction, the address must be sent in for each
iteration of the repeat, meaning after each time the output data sampling is done. There is no automatic address
increment when using REPEAT with LDS, as it uses a direct addressing protocol.
Figure 33-9. LDS Instruction Operation
ADDRESS_SIZE
Synch RX
LDS Adr_0 Adr_n
(0x55)
Data_0 Data_n TX
ΔGT
When the instruction is decoded, and the address byte(s) are received as dictated by the decoded instruction, the DL
layer will synchronize all required information to the ACC layer, which will handle the bus request and synchronize
data buffered from the bus back again to the DL layer. This will create a synchronization delay that must be taken into
consideration upon receiving the data from the UPDI.
ADDRESS_SIZE DATA_SIZE
Synch RX
STS Adr_0 Adr_n Data_0 Data_n
(0x55)
ACK ACK TX
ΔGT ΔGT
The transfer protocol for an STS instruction is depicted in the above figure, following this sequence:
1. The address is sent.
2. An Acknowledge (ACK) is sent back from the UPDI if the transfer was successful.
3. The number of bytes, as specified in the STS instruction, is sent.
4. A new ACK is received after the data have been successfully transferred.
Synch
LD
(0x55) DATA_SIZE RX
Data_0 Data_n
TX
ΔGT
The figure above shows an example of a typical LD sequence, where the data are received after the Guard Time
(GT) period. Loading data from the UPDI Pointer register follows the same transmission protocol.
For the LD instruction from the data space, the pointer register must be set up by using an ST instruction to the UPDI
Pointer register. After the ACK has been received on a successful Pointer register write, the LD instruction must be
set up with the desired DATA SIZE operands. An LD to the UPDI Pointer register is done directly with the LD
instruction.
33.3.3.4 ST - Store Data from UPDI to Data Space Using Indirect Addressing
The ST instruction is used to store data from the UPDI PHY shift register to the data space. The ST instruction is
used to store data that are shifted serially into the PHY layer. The ST instruction is based on indirect addressing,
which means that the Address Pointer in the UPDI needs to be written before the data space. The automatic pointer
post-increment operation is supported and is useful when the ST instruction is utilized with the REPEAT instruction.
The ST instruction is also used to store the UPDI Address Pointer into the Pointer register. The maximum supported
size for storing address and data is 32 bits.
ADDRESS_SIZE
Synch
ST ADR_0 ADR_n RX
(0x55)
ACK TX
ΔGT
BLOCK_SIZE
Synch RX
ST Data_0 Data_n
(0x55)
ACK TX
ΔGT
The figure above gives an example of an ST instruction to the UPDI Pointer register and the storage of regular data.
A SYNCH character is sent before each instruction. In both cases, an Acknowledge (ACK) is sent back by the UPDI if
the ST instruction was successful.
To write the UPDI Pointer register, the following procedure has to be followed:
1. Set the PTR field in the ST instruction to signature 0x2.
2. Set the address size (Size A) field to the desired address size.
3. After issuing the ST instruction, send Size A bytes of address data.
4. Wait for the ACK character, which signifies a successful write to the Address register.
After the Address register is written, sending data is done in a similarly:
1. Set the PTR field in the ST instruction to signature 0x0 to write to the address specified by the UPDI Pointer
register. If the PTR field is set to 0x1, the UPDI pointer is automatically updated to the next address according
to the data size Size B field of the instruction after the write is executed.
2. Set the Size B field in the instruction to the desired data size.
3. After sending the ST instruction, send Size B bytes of data.
4. Wait for the ACK character, which signifies a successful write to the bus matrix.
When used with the REPEAT instruction, it is recommended to set up the Address register with the start address for
the block to be written and use the Pointer Post Increment register to automatically increase the address for each
repeat cycle. When using the REPEAT instruction, the data frame of Size B data bytes can be sent after each
received ACK.
33.3.3.5 LDCS - Load Data from Control and Status Register Space
The LDCS instruction is used to load serial readout data from the UPDI Control and the Status register space located
in the DL layer into the PHY layer shift register. The LDCS instruction is based on direct addressing, where the
address is part of the instruction operands. The LDCS instruction can access only the UPDI CS register space. This
instruction supports only byte access, and the data size is not configurable.
Figure 33-13. LDCS Instruction Operation
OPCODE CS Address
Synch
(0x55)
LDCS RX
Data TX
Δgt
The figure above shows a typical example of LDCS data transmission. A data byte from the LDCS is transmitted from
the UPDI after the guard time is completed.
OPCODE CS Address
Synch
STCS Data
(0x55) RX
TX
The figure above shows the data frame transmitted after the SYNCH character and the instruction frames. The STCS
instruction byte can be immediately followed by the data byte. There is no response generated from the STCS
instruction, as is the case for the ST and STS instructions.
OPCODE Size B
Size B - Data Size
0 0 1 Byte
REPEAT 1 0 1 0 0 0
0 1 Word (2 Bytes)
1 0 Reserved
1 1 Reserved
REPEAT_SIZE
Synch
REPEAT RPT_0
(0x55) Repeat Number of Blocks of Data_SIZE
Synch ST RX
Data_0 Data_n DataB_1 DataB_n
(0x55) (ptr++)
ACK ACK TX
Δd Δd Δd Δd Δd
The figure above gives an example of repeat operation with an ST instruction using pointer post-increment operation.
After the REPEAT instruction is sent with RPT_0 = n, the first ST instruction is issued with SYNCH and instruction
frame, while the next n ST instructions are executed by only sending data bytes according to the ST operand
DATA_SIZE, and maintaining the Acknowledge (ACK) handshake protocol.
Synch
REPEAT RPT_0 RPT_1
(0x55)
Synch LD
(0x55) (ptr++) RX
DATA_SIZE TX
DATA_SIZE
DataB_1 DataB_n
ΔGT
For LD, data will come out continuously after the LD instruction. Note the guard time on the first data block.
If using indirect addressing instructions (LD/ST), it is recommended to always use the pointer post-increment option
when combined with REPEAT. The ST/LD instruction is necessary only before the first data block (number of data
bytes determined by DATA_SIZE). Otherwise, the same address will be accessed in all repeated access operations.
For direct addressing instructions (LDS/STS), the address must always be transmitted as specified in the instruction
protocol, before data can be received (LDS) or sent (STS).
SIB Size C
Size C - Key Size
0 0 64 bits (8 Bytes)
KEY 1 1 1 0 0
0 1 128 bits (16 Bytes) (SIB only)
1 0 Reserved
1 1 Reserved
KEY_SIZE
Synch
KEY KEY_0 KEY_n RX
(0x55)
TX
Synch RX
KEY
(0x55)
TX
SIB_0 SIB_n
Δgt
SIB_SIZE
The figure above shows the transmission of a key and the reception of a SIB. In both cases, the Size C (SIZE_C)
field in the operand determines the number of frames being sent or received. There is no response after sending a
KEY to the UPDI. When requesting the SIB, data will be transmitted from the UPDI according to the current guard
time setting.
should be ignored. The second captured value based on the input event should be used for the measurement.
See the figure below for an example using 10 kbps UPDI SYNCH character pulses, giving a capture window of
200 µs for the timer.
• It is possible to read out the captured value directly after the SYNCH character by reading the TCBn.CCMP
register or the value can be written to memory by the CPU once the capture is done.
Figure 33-18. UPDI System Clock Measurement Events
Ignore the first
capture event
200 μs
UPDI_
Input
RX
Debugger
Data
RPT CNT LD*(ptr) GT D0 SB D1 SB D2 SB D3 SB D4 SB D5 SB
TX
Debugger D1 lost D3 lost
D0 D2 D4
Processing
RX
Debugger
RPT CNT LD*(ptr) GT D0 SB IB D1 SB IB D2 SB IB D3 SB
Data
TX
Debugger
D0 D1 D2 D3
Processing
Notes:
1. GT denotes the guard time insertion.
2. SB is for Stop bit.
3. IB is the inserted inter-byte delay.
4. The rest of the frames are data and instructions.
The table below gives an overview of the available key signatures that must be shifted in to activate the interfaces.
Table 33-5. Key Activation Signatures
2. Optional: Read the Chip Erase (CHIPERASE) bit in the ASI Key Status (UPDI.ASI_KEY_STATUS) register to
see that the key is successfully activated.
3. Write the signature to the Reset Request (RSTREQ) bit in the ASI Reset Request (UPDI.ASI_RESET_REQ)
register. This will issue a System Reset.
4. Write 0x00 to the ASI Reset Request (UPDI.ASI_RESET_REQ) register to clear the System Reset.
5. Read the NVM Lock Status (LOCKSTATUS) bit from the ASI System Status (UPDI.ASI_SYS_STATUS)
register.
6. The chip erase is done when LOCKSTATUS bit is ‘0’. If the LOCKSTATUS bit is ‘1’, return to step 5.
7. Check the Chip Erase Key Failed (ERASE_FAILED) bit in the ASI System Status (UPDI.ASI_SYS_STATUS)
register to verify if the chip erase was successful.
8. If the ERASE_FAILED bit is ‘0’, the chip erase was successful.
After a successful chip erase, the lock bits will be cleared, and the UPDI will have full access to the system. Until the
lock bits are cleared, the UPDI cannot access the system bus, and only CS-space operations can be performed.
During chip erase, the BOD is forced in ON state by writing to the Active (ACTIVE) bit field from the
CAUTION
Control A (BOD.CTRLA) register and uses the BOD Level (LVL) bit field from the BOD Configuration
(FUSE.BODCFG) fuse and the BOD Level (LVL) bit field from the Control B (BOD.CTRLB) register. If the
supply voltage VDD is below that threshold level, the device is unavailable until VDD is increased
adequately. See the BOD section for more details.
5. Read the Start User Row Programming (UROWPROG) bit from the ASI System Status
(UPDI.ASI_SYS_STATUS) register.
6. User Row Programming can start when the UROWPROG bit is ‘1’. If UROWPROG is ‘0’, return to step 5.
7. The data to be written to the User Row must first be written to a buffer in the RAM. The writable area in the
RAM has a size of 32 bytes, and it is only possible to write user row data to the first 32 byte addresses of the
RAM. Addressing outside this memory range will result in a nonexecuted write. The data will map 1:1 with the
user row space when the data is copied into the user row upon completion of the Programming sequence.
8. When all user row data has been written to the RAM, write the User Row Programming Done (UROWDONE)
bit in the ASI System Control A (UPDI.ASI_SYS_CTRLA) register.
9. Read the Start User Row Programming (UROWPROG) bit from the ASI System Status
(UPDI.ASI_SYS_STATUS) register.
10. The User Row Programming is completed when UROWPROG bit is ‘0’. If UROWPROG bit is ‘1’, return to step
9.
11. Write to the User Row Write Key Status (UROWWRITE) bit in the ASI Key Status (UPDI.ASI_KEY_STATUS)
register.
12. Write the signature to the Reset Request (RSTREQ) bit in the ASI Reset Request (UPDI.ASI_RESET_REQ)
register. This will issue a System Reset.
13. Write 0x00 to the ASI Reset Request (UPDI.ASI_RESET_REQ) register to clear the System Reset.
14. The User Row Programming is complete.
It is not possible to read back data from the RAM in this mode. Only writes to the first 32 bytes of the RAM are
allowed.
33.3.9 Events
The UPDI can generate the following events:
Table 33-6. Event Generators in UPDI
This event is set on the UPDI clock for each detected positive edge in the SYNCH character, and it is not possible to
disable this event from the UPDI.
The UPDI has no event users.
Refer to the Event System section for more details regarding event types and Event System configuration.
33.5.1 Status A
Name: STATUSA
Offset: 0x00
Reset: 0x10
Property: -
Bit 7 6 5 4 3 2 1 0
UPDIREV[3:0]
Access R R R R
Reset 0 0 0 1
33.5.2 Status B
Name: STATUSB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
PESIG[2:0]
Access R R R
Reset 0 0 0
33.5.3 Control A
Name: CTRLA
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
IBDLY PARD DTD RSD GTVAL[2:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
33.5.4 Control B
Name: CTRLB
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
NACKDIS CCDETDIS UPDIDIS
Access R/W R/W R/W
Reset 0 0 0
Name: ASI_KEY_STATUS
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
UROWWRITE NVMPROG CHIPERASE
Access R/W R R
Reset 0 0 0
Name: ASI_RESET_REQ
Offset: 0x08
Reset: 0x00
Property: -
A Reset is signalized to the System when writing the Reset signature to this register.
Bit 7 6 5 4 3 2 1 0
RSTREQ[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: ASI_CTRLA
Offset: 0x09
Reset: 0x03
Property: -
Bit 7 6 5 4 3 2 1 0
UPDICLKSEL[1:0]
Access R/W R/W
Reset 1 1
Name: ASI_SYS_CTRLA
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
UROWWRITE_ CLKREQ
FINAL
Access R R R R R R R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: ASI_SYS_STATUS
Offset: 0x0B
Reset: 0x01
Property: -
Bit 7 6 5 4 3 2 1 0
RSTSYS INSLEEP NVMPROG UROWPROG LOCKSTATUS
Access R R R R R
Reset 0 0 0 0 1
Name: ASI_CRC_STATUS
Offset: 0x0C
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CRC_STATUS[2:0]
Access R R R
Reset 0 0 0
35. Conventions
Symbol Description
165 Decimal number
0b0101 Binary number
‘0101’ Binary numbers are given without prefix if unambiguous
Symbol Description
KB kilobyte (210B = 1024B)
MB megabyte (220B = 1024 KB)
GB gigabyte (230B = 1024 MB)
b bit (binary ‘0’ or ‘1’)
B byte (8 bits)
1 kbit/s 1,000 bit/s rate
1 Mbit/s 1,000,000 bit/s rate
1 Gbit/s 1,000,000,000 bit/s rate
word 16-bit
Symbol Description
kHz 1 kHz = 103 Hz = 1,000 Hz
MHz 1 MHz = 106 Hz = 1,000,000 Hz
GHz 1 GHz = 109 Hz = 1,000,000,000 Hz
ms 1 ms = 10-3s = 0.001s
µs 1 µs = 10-6s = 0.000001s
ns 1 ns = 10-9s = 0.000000001s
Symbol Description
R/W Read/Write accessible register bit. The user can read from and write to this bit.
R Read-only accessible register bit. The user can only read this bit. Writes will be ignored.
W Write-only accessible register bit. The user can only write this bit. Reading this bit will return an
undefined value.
BITFIELD Bitfield names are shown in uppercase. Example: INTMODE.
BITFIELD[n:m] A set of bits from bit n down to m. Example: PINA[3:0] = {PINA3, PINA2, PINA1, PINA0}.
Reserved Reserved bits, bit fields, and bit field values are unused and reserved for future use. For
compatibility with future devices, always write reserved bits to ‘0’ when the register is written.
Reserved bits will always return zero when read.
PERIPHERALn If several instances of the peripheral exist, the peripheral name is followed by a single number to
identify one instance. Example: USARTn is the collection of all instances of the USART module,
while USART3 is one specific instance of the USART module.
PERIPHERALx If several instances of the peripheral exist, the peripheral name is followed by a single capital
letter (A-Z) to identify one instance. Example: PORTx is the collection of all instances of the
PORT module, while PORTB is one specific instance of the PORT module.
Reset Value of a register after a Power-on Reset. This is also the value of registers in a peripheral after
performing a software Reset of the peripheral, except for the Debug Control registers.
SET/CLR/TGL Registers with SET/CLR/TGL suffix allow the user to clear and set bits in a register without doing
a read-modify-write operation.
Each SET/CLR/TGL register is paired with the register it is affecting. Both registers in a register
pair return the same value when read.
Example: In the PORT peripheral, the OUT and OUTSET registers form such a register pair. The
contents of OUT will be modified by a write to OUTSET. Reading OUT and OUTSET will return
the same value.
Writing a ‘1’ to a bit in the CLR register will clear the corresponding bit in both registers.
Writing a ‘1’ to a bit in the SET register will set the corresponding bit in both registers.
Writing a ‘1’ to a bit in the TGL register will toggle the corresponding bit in both registers.
Note: For peripherals with different register sets in different modes, <peripheral_instance_name> and
<peripheral_name> must be followed by a mode name, for example:
// TCA0 in Normal Mode (SINGLE) uses waveform generator in frequency mode
TCA0.SINGLE.CTRL=TCA_SINGLE_WGMODE_FRQ_gc;
Offset Error The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5
LSb). Ideal value: 0 LSb.
Figure 35-1. Offset Error
Output Code
Ideal ADC
Actual ADC
Offset
Error
VREF Input Voltage
Gain Error After adjusting for offset, the gain error is found as the deviation of the last transition (e.g.,
0x3FE to 0x3FF for a 10-bit ADC) compared to the ideal transition (at 1.5 LSb below
maximum). Ideal value: 0 LSb.
Ideal ADC
Actual ADC
Integral After adjusting for offset and gain error, the INL is the maximum deviation of an actual
Nonlinearity (INL) transition compared to an ideal transition for any code. Ideal value: 0 LSb.
Figure 35-3. Integral Nonlinearity
Output Code
INL
Ideal ADC
Actual ADC
Differential The maximum deviation of the actual code width (the interval between two adjacent
Nonlinearity (DNL) transitions) from the ideal code width (1 LSb). Ideal value: 0 LSb.
Figure 35-4. Differential Nonlinearity
Output Code
0x3FF
1 LSb
DNL
0x000
Quantization Error Due to the quantization of the input voltage into a finite number of codes, a range of input
voltages (1 LSb wide) will code to the same value. Always ±0.5 LSb.
Absolute Accuracy The maximum deviation of an actual (unadjusted) transition compared to an ideal transition
for any code. This is the compound effect of all errors mentioned before. Ideal value: ±0.5
LSb.
36.1 Disclaimer
All typical values are measured at T = 25°C and VDD = 3V unless otherwise specified. All minimum and maximum
values are valid across operating temperature and voltage unless otherwise specified.
Note:
1. – If the VPIN is lower than GND – 0.6V, then a current limiting resistor is required. The negative DC injection
current limiting resistor is calculated as R = (GND – 0.6V – VPIN)/ICn.
– If the VPIN is greater than VDD+0.6V, then a current limiting resistor is required. The positive DC injection
current limiting resistor is calculated as R = (VPIN – (VDD + 0.6))/ICn.
VRSTMAX = 13V
CAUTION
Care should be taken to avoid overshoot (overvoltage) when connecting the RESET pin to a 12V source.
Exposing the pin to a voltage above the rated absolute maximum can activate the pin’s ESD protection
circuitry, which will remain activated until the voltage has been brought below approximately 10V. A 12V
driver can keep the ESD protection in an activated state (if activated by an overvoltage condition) while
driving currents through it, potentially causing permanent damage to the part.
Notes:
1. Refer to the device ordering codes for the device temperature range.
2. Operation is ensured down to 2.7V or BOD triggering level, VBOD. VBOD may be below the minimum Operating
Supply Voltage for some devices. Where this is the case, the device is tested down to VDD = VBOD during
production.
– During Chip Erase, the BOD is forced ON. If the supply voltage VDD is below the configured VBOD, the
Chip Erase will fail. See Chip Erase.
Table 36-3. Operating Voltage and Frequency
Notes:
1. Operation ensured down to BOD triggering level, VBOD with BODLEVEL2.
2. Operation ensured down to BOD triggering level, VBOD with BODLEVEL7.
The maximum CPU clock frequency depends on VDD. As shown in the following figure, the maximum frequency vs.
VDD is linear between 2.7V < VDD < 4.5V.
Figure 36-1. Maximum Frequency vs. VDD for [-40, 125]°C
16 MHz
8 MHz
• VDD = 3V
• T = 25°C
• OSC20M (16 MHz setting) used as the system clock source, except where otherwise specified
• System power consumption measured with peripherals disabled and without I/O drive
Table 36-4. Power Consumption in Active and Idle Mode
Note:
1. These values are based on characterization and not covered by production test limits.
Table 36-5. Power Consumption in Power-Down, Standby and Reset mode
Note:
1. These values are based on characterization and not covered by production test limits.
• VDD = 3V
• T = 25°C
• OSC20M as the system clock source, unless otherwise specified
Table 36-6. Start-Up, Reset, and Wake-Up Time from OSC20M
...........continued
Peripheral Conditions Typ.(1) Unit
Flash programming Erase Operation 1.5 mA
Write Operation 3.0
Notes:
1. The Current consumption of the module only. To calculate the total power consumption of the system, add this
value to the base power consumption as listed in Power Consumption.
2. The CPU in Standby sleep mode.
VPOR POR threshold voltage on VDD falling VDD falls/rises at 0.5 V/ms or slower 0.8 - 1.6 V
BOD.VLMLVL = 0x1 - 13 -
BOD.VLMLVL = 0x2 - 25 -
BODLEVEL2 - 40 -
Sampled, 1 kHz - 1 - ms
Sampled, 125 Hz - 8 -
fOSC20M Accuracy with 16 MHz frequency selection Factory calibrated T = 25°C, 3.0V -3.0 - 3.0 %
DC Duty cycle - 50 - %
Notes:
1. Oscillator frequencies above speed specification must be divided so that the CPU clock always is within
specification.
2. These values are based on characterization and not covered by production test limits.
Table 36-13. 32.768 kHz Internal Oscillator (OSCULP32K) Characteristics
Note:
1. These values are based on characterization and not covered by production test limits.
CL = 12.5 pF - - 40
V IH1
V IL1
Symbol Description Condition VDD = [2.7, 5.5]V VDD = [4.5, 5.5]V Unit
36.10 I/O Pin Characteristics
Table 36-16. I/O Pin Characteristics (TA = [-40, 105]°C, VDD = [2.7, 5.5]V Unless Otherwise Stated)
Symbol Description Condition Min. Typ. Max. Unit
VIL Input low-voltage, except RESET pin as I/O -0.2 - 0.3 × VDD V
VIH Input high-voltage, except RESET pin as I/O 0.7 × VDD - VDD + 0.2V V
IIH / IIL I/O pin input leakage current, except RESET pin as I/O VDD = 5.5V, pin high - < 0.05 - µA
VOL I/O pin drive strength VDD = 3.0V, IOL = 7.5 mA - - 0.6 V
VOH I/O pin drive strength VDD = 3.0V, IOH = 7.5 mA 2.4 - - V
...........continued
Symbol Description Condition Min. Typ. Max. Unit
Itotal Maximum combined I/O sink current per pin group(1) - - 100 mA
VIH2 Input high-voltage on RESET pin as I/O 0.7 × VDD - VDD + 0.2V V
VOL2 I/O pin drive strength on RESET pin as I/O VDD = 3.0V, IOL = 0.25 mA - - 0.6 V
VOH2 I/O pin drive strength on RESET pin as I/O VDD = 3.0V, IOH = 0.25 mA 2.4 - - V
RP Pull-up resistor 20 35 50 kΩ
Note:
1. Pin group x (Px[7:0]). The combined continuous sink/source current for all I/O ports should not exceed the
limits.
36.11 USART
Figure 36-3. USART in SPI Mode - Timing Requirements in Master Mode
SS
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS tMIH tSCK
MISO
MSb LSb
(Data Input)
tMOH tMOH
MOSI
(Data Output) MSb LSb
...........continued
Symbol Description Condition Min. Typ. Max. Unit
tSCK SCK period Master 100 - - ns
tSCKW SCK high/low width Master - 0.5 × tSCK - ns
tSCKR SCK rise time Master - 2.7 - ns
tSCKF SCK fall time Master - 2.7 - ns
tMIS MISO setup to SCK Master - 10 - ns
tMIH MISO hold after SCK Master - 10 - ns
tMOS MOSI setup to SCK Master - 0.5 × tSCK - ns
tMOH MOSI hold after SCK Master - 1.0 - ns
36.12 SPI
Figure 36-4. SPI - Timing Requirements in Master Mode
SS
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS tMIH tSCK
MISO
MSb LSb
(Data Input)
tMOH tMOH
MOSI
(Data Output) MSb LSb
SS
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS tSIH tSSCK
MOSI
MSb LSb
(Data Input)
MISO
(Data Output) MSb LSb
36.13 TWI
Figure 36-6. TWI - Timing Requirements
tHIGH tLOW
tOF tSP tR
SCL tSU;STA tHD ;STA tSU ;DAT tHD ;DAT tSU ;STO tBUF
SDA
S P S
...........continued
Symbol Description Condition Min. Typ. Max. Unit
tLOW Low period of SCL fSCL ≤ 100 kHz 4.7 - - µs
Clock
fSCL ≤ 400 kHz 1.3 - -
fSCL ≤ 1 MHz 0.5 - -
tHIGH High period of SCL fSCL ≤ 100 kHz 4.0 - - µs
Clock
fSCL ≤ 400 kHz 0.6 - -
fSCL ≤ 1 MHz 0.26 - -
tSU;STA Setup time for a fSCL ≤ 100 kHz 4.7 - - µs
repeated Start
fSCL ≤ 400 kHz 0.6 - -
condition
fSCL ≤ 1 MHz 0.26 - -
tHD;DAT Data hold time fSCL ≤ 100 kHz 0 - 3.45 µs
fSCL ≤ 400 kHz 0 - 0.9
fSCL ≤ 1 MHz 0 - 0.45
tSU;DAT Data setup time fSCL ≤ 100 kHz 250 - - ns
fSCL ≤ 400 kHz 100 - -
fSCL ≤ 1 MHz 50 - -
tSU;STO Setup time for Stop fSCL ≤ 100 kHz 4 - - µs
condition
fSCL ≤ 400 kHz 0.6 - -
fSCL ≤ 1 MHz 0.26 - -
tBUF Bus free time fSCL ≤ 100 kHz 4.7 - - µs
between a Stop and
fSCL ≤ 400 kHz 1.3 - -
Start condition
fSCL ≤ 1 MHz 0.5 - -
...........continued
Symbol Description Condition Min. Typ. Max. Unit
tHD;DAT Data hold time Slave(4) All Frequencies SDAHOLD = 0x00 90 150 220 ns
Notes:
1. These parameters are for design guidance only and are not covered by production test limits.
2. SDAHOLD is the data hold time after the SCL signal is detected as low. The actual hold time is, therefore,
higher than the configured hold time.
3. For Master mode, the data hold time is whatever is largest of the following:
– 4 × tCLK_PER + 50 ns (typical)
– SDAHOLD configuration + SCL filter delay
4. For Slave mode, the hold time is given by:
– SDAHOLD configuration + SCL filter delay
36.14 VREF
Table 36-21. Internal Voltage Reference Characteristics
Notes:
1. These values are based on characterization and not covered by production test limits.
2. The symbols INTxxV refer to the respective values of the ADC0REFSEL and DAC0REFSEL bit fields in the
VREF.CTRLA register.
Notes:
1. These values are based on characterization and not covered by production test limits.
2. The symbols INTxxV refer to the respective values of the ADC0REFSEL and DAC0REFSEL bit fields in the
VREF.CTRLA register.
36.15 ADC
Operating conditions:
• VDD = 2.7V to 5.5V
• Temperature = -40°C to 125°C
• DUTYCYC = 25%
• CLKADC = 13 × fADC
• SAMPCAP is 10 pF for 0.55V reference, while it is set to 5 pF for VREF ≥ 1.1V
• Applies for all allowed combinations of VREF selections and Sample Rates unless otherwise stated
Table 36-24. Power Supply, Reference, and Input Range
...........continued
Symbol Description Conditions Min. Typ. Max. Unit
CLKADC Clock frequency VREF = 0.55V (10 bits) 100 - 260 kHz
1.1V ≤ VREF (10 bits) 200 - 1500
1.1V ≤ VREF (8-bit resolution) 200 - 2000(1)
Ts Sampling time 2 2 33 CLKADC cycles
TCONV Conversion time (latency) Sampling time = 2 CLKADC 8.7 - 50 µs
TSTART Start-up time Internal VREF - 22 - µs
Note:
1. 50% duty cycle is required for clock frequencies above 1500 kHz.
Table 36-26. Accuracy Characteristics Internal Reference(2)
...........continued
Symbol Description Conditions Min. Typ. Max. Unit
EABS Absolute REFSEL = T = [0, 105]°C - 3 30 LSb
accuracy INTERNAL
VDD = [2.7V, 3.6V]
VREF = 1.1V
VDD = [2.7V, 3.6V] - 3 40
REFSEL = VDD - 2 5
REFSEL = - - 65
INTERNAL
EGAIN Gain error REFSEL = T = [0, 105]°C -25 3 25 LSb
INTERNAL
VDD = [2.7V, 3.6V]
VREF = 1.1V
VDD = [2.7V, 3.6V] -35 3 35
REFSEL = VDD -1 2 4
REFSEL = -60 - 60
INTERNAL
EOFF Offset error REFSEL = -5 -0.5 2 LSb
INTERNAL
VREF = 0.55V
REFSEL = -4 -0.5 2 LSb
INTERNAL
1.1V ≤ VREF
Notes:
1. A DNL error of ≤ 1 LSb ensures a monotonic transfer function with no missing codes.
2. These values are based on characterization and not covered by production test limits.
36.16 DAC
VDD = 3V, unless stated otherwise.
Accuracy characteristics calculated based on 5% to 95% range of the DAC.
Table 36-27. Power Supply, Reference, and Input Range
Note:
1. Supply voltage must meet the VDD specification for the VREF level used as DAC reference.
1. Offset including the DAC output buffer offset, this measured at DAC output pin.
2. VREF accuracy is included in the Gain accuracy specification.
3. These values are based on characterization and not covered by production test limits.
36.17 AC
Table 36-30. Analog Comparator Characteristics, Low-Power Mode Disabled
HYSMODE = 0x1 0 10 30
HYSMODE = 0x2 10 30 90
HYSMODE = 0x1 0 10 30
HYSMODE = 0x2 5 30 90
RESET Hi-Z St D0 D1 D2 D3 D4 D5 D6 D7 Sp
Handshake / BREAK
SYNC (0x55)
TRES
(Auto-baud)
UPDI.rxd (Ignore)
3
UPDI.txd Hi-Z Hi-Z
UPDI.txd = 0
TUPDI
debugger.
Hi-Z Hi-Z
UPDI.txd
Debugger.txd = 0 Debugger.txd = z
TDeb0 TDebZ
Note:
1. These parameters are for design guidance only and are not covered by production test limits.
Table 36-33. UPDI Max. Bit Rates vs. VDD(1)
Note:
1. These parameters are for design guidance only and are not covered by production test limits.
6.0
IDD [mA]
5.0
4.0
3.0
2.0
1.0
0.0
0 2 4 6 8 10 12 14 16
Frequency [MHz]
Figure 37-2. Active Supply Current vs. Frequency [0.1, 1.0] MHz at T = 25°C
600 VDD [V]
2.7
550 3
500 3.6
4.2
450 5
5.5
400
350
IDD [μA]
300
250
200
150
100
50
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency [MHz]
7.0
6.0
IDD [mA]
5.0
4.0
3.0
2.0
1.0
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 37-4. Active Supply Current vs. VDD (f=[1, 16] MHz OSC20M) at T = 25°C
10.0 Frequency [MHz]
1
9.0 2
4
8.0 8
16
7.0
6.0
IDD [mA]
5.0
4.0
3.0
2.0
1.0
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 37-5. Active Supply Current vs. VDD (f = 32.768 kHz OSCULP32K)
32 Temperature [°C]
-40
-20
28
0
25
24 70
85
105
20
125
IDD [μA]
16
12
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
3.0
IDD [mA]
2.5
2.0
1.5
1.0
0.5
0.0
0 2 4 6 8 10 12 14 16
Frequency [MHz]
Figure 37-7. Idle Supply Current vs. Low Frequency (0.1-1.0 MHz) at T = 25°C
250 VDD [V]
2.7
225 3
3.6
200 4.2
5
175 5.5
150
IDD [μA]
125
100
75
50
25
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency [MHz]
3.5
3.0
IDD [mA]
2.5
2.0
1.5
1.0
0.5
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 37-9. Idle Supply Current vs. VDD (f = 32.768 kHz OSCULP32K)
20 Temperature [°C]
-40
18 -20
0
16 25
70
14 85
105
12 125
IDD [μA]
10
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
5.0
4.0
3.0
2.0
1.0
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 37-11. Standby Mode Supply Current vs. VDD (RTC Running with Internal OSCULP32K)
10.0 Temperature [°C]
-40
9.0 -20
0
8.0 25
70
7.0 85
105
6.0 125
IDD [μA]
5.0
4.0
3.0
2.0
1.0
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 37-12. Standby Mode Supply Current vs. VDD (Sampled BOD Running at 125 Hz)
10.0 Temperature [°C]
-40
9.0 -20
0
8.0 25
70
7.0 85
105
6.0 125
IDD [μA]
5.0
4.0
3.0
2.0
1.0
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 37-13. Standby Mode Supply Current vs. VDD (Sampled BOD Running at 1 kHz)
10.0 Temperature [°C]
-40
9.0 -20
0
8.0 25
70
7.0 85
105
6.0 125
IDD [μA]
5.0
4.0
3.0
2.0
1.0
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
3.0
IDD [μA]
2.5
2.0
1.5
1.0
0.5
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 37-15. Power-Down Mode Supply Current vs. VDD (All Functions Disabled)
5.0 Temperature [°C]
-40
4.5 -20
0
4.0 25
70
3.5 85
105
3.0 125
IDD [μA]
2.5
2.0
1.5
1.0
0.5
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
37.2 GPIO
1.0
0.8
0.6
0.4
0.2
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 37-17. I/O Pin Input Threshold Voltage vs. VDD (T = 25°C)
75 Threshold
VIH
70 VIL
65
60
55
50
45
40
35
30
25
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 37-18. I/O Pin Input Threshold Voltage vs. VDD (VIH)
75 Temperature [°C]
-40
70 0
25
65 70
85
60 105
125
55
50
45
40
35
30
25
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 37-19. I/O Pin Input Threshold Voltage vs. VDD (VIL)
75 Temperature [°C]
-40
70 0
25
65 70
85
60 105
125
55
50
45
40
35
30
25
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
0.25
0.20
0.15
0.10
0.05
0.00
0 1 2 3 4 5 6 7 8 9 10
Sink current [mA]
Figure 37-21. I/O Pin Output Voltage vs. Sink Current (VDD = 5.0V)
0.5
VOutput [V]
0.4
0.3
0.2
0.1
0.0
0 2 4 6 8 10 12 14 16 18 20
Sink current [mA]
Figure 37-22. I/O Pin Output Voltage vs. Sink Current (T = 25°C)
0.7
0.6
VOutput [V]
0.5
0.4
0.3
0.2
0.1
0.0
0 2 4 6 8 10 12 14 16 18 20
Sink current [mA]
Figure 37-23. I/O Pin Output Voltage vs. Source Current (VDD = 3.0V)
2.5
2.4
2.3
2.2
2.1
2.0
0 1 2 3 4 5 6 7 8 9 10
Source current [mA]
Figure 37-24. I/O Pin Output Voltage vs. Source Current (VDD = 5.0V)
4.5
4.4
4.3
4.2
4.1
4.0
0 2 4 6 8 10 12 14 16 18 20
Source current [mA]
Figure 37-25. I/O Pin Output Voltage vs. Source Current (T = 25°C)
3.5
3.0
2.5
VOutput [V]
2.0
1.5
1.0
0.5
0.0
0 2 4 6 8 10 12 14 16 18 20
Source current [mA]
2.0
1.8
1.5
1.3
1.0
0 5 10 15 20 25 30 35 40 45 50
Pull-up resistor current [µA]
Figure 37-27. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VDD = 5.0V)
4.0
3.8
3.5
3.3
3.0
0 5 10 15 20 25 30 35 40 45 50
Pull-up resistor current [µA]
0.6
0.4
VREF error [%]
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
1.0
VDD [V]
3
0.8 5
0.6
0.4
0.2
VREF error [%]
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
0.6
0.4
0.2
VREF error [%]
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
0.6
0.4
0.2
VREF error [%]
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
50 Temperature [°C]
-40
45 0
25
40 70
85
35 105
125
30
IDD [µA]
25
20
15
10
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 37-33. BOD Current vs. VDD (Sampled BOD at 125 Hz)
2.5
2.0
1.5
1.0
0.5
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
2.5
2.0
1.5
1.0
0.5
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
2.70
2.68
BOD level [V]
2.66
2.64
2.62
2.60
2.58
2.56
4.30
4.28
BOD level [V]
4.26
4.24
4.22
4.20
4.18
4.16
6.0
5.0
4.0
3.0
2.0
1.0
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 37-38. Absolute Accuracy vs. VREF (VDD = 5.0V, fADC = 115 ksps), REFSEL = Internal Reference
7.0
Absolute Accuracy [LSb]
6.0
5.0
4.0
3.0
2.0
1.0
0.0
1.1 1.5 2.5 4.3 VDD
VREF [V]
Figure 37-39. DNL Error vs. VDD (fADC = 115 ksps) at T = 25°C, REFSEL = Internal Reference
1.2
DNL [LSb]
1.0
0.8
0.6
0.4
0.2
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 37-40. DNL vs. VREF (VDD = 5.0V, fADC = 115 ksps), REFSEL = Internal Reference
1.4
1.2
DNL [LSb]
1.0
0.8
0.6
0.4
0.2
0.0
1.1 1.5 2.5 4.3 VDD
VREF [V]
Figure 37-41. Gain Error vs. VDD (fADC = 115 ksps) at T = 25°C, REFSEL = Internal Reference
4.0
Gain [LSb]
3.0
2.0
1.0
0.0
-1.0
-2.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 37-42. Gain Error vs. VREF (VDD = 5.0V, fADC = 115 ksps), REFSEL = Internal Reference
5.0
Gain [LSb]
4.0
3.0
2.0
1.0
0.0
1.1 1.5 2.5 4.3 VDD
VREF [V]
Figure 37-43. INL vs. VDD (fADC = 115 ksps) at T = 25°C, REFSEL = Internal Reference
1.2
INL [LSb]
1.0
0.8
0.6
0.4
0.2
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 37-44. INL vs. VREF (VDD = 5.0V, fADC = 115 ksps), REFSEL = Internal Reference
1.4
1.2
INL [LSb]
1.0
0.8
0.6
0.4
0.2
0.0
1.1 1.5 2.5 4.3 VDD
VREF [V]
Figure 37-45. Offset Error vs. VDD (fADC = 115 ksps) at T = 25°C, REFSEL = Internal Reference
0.4
Offset [LSb]
0.0
-0.4
-0.8
-1.2
-1.6
-2.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 37-46. Offset Error vs. VREF (VDD = 5.0V, fADC = 115 ksps), REFSEL = Internal Reference
0.8
0.4
Offset [LSb]
0.0
-0.4
-0.8
-1.2
-1.6
-2.0
1.1 1.5 2.5 4.3 VDD
VREF [V]
37.6 AC Characteristics
Figure 37-47. Hysteresis vs. VCM - 10 mV (VDD = 5V)
20 Temperature [°C]
-40
18 -20
0
16 25
55
14
85
105
Hysteresis [mV]
12
125
10
0
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VCommon Mode [V]
80 HYSMODE
10 mV
72 25 mV
50 mV
64
56
Hysteresis [mV]
48
40
32
24
16
0
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VCommon Mode [V]
125
5.0
4.0
3.0
2.0
1.0
0.0
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VCommon Mode [V]
10 HYSMODE
10 mV
9 25 mV
50 mV
8
6
Offset [mV]
0
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VCommon Mode [V]
Figure 37-51. Propagation Delay vs. VCM LPMODE Enabled, Falling Positive Input, VOD = 25 mV (T = 25°C)
400
Propagation delay [ns]
300
200
100
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VCommon Mode [V]
Figure 37-52. Propagation Delay vs. VCM LPMODE Enabled, Rising Positive Input, VOD = 30 mV (T = 25°C)
400
Propagation delay [ns]
300
200
100
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VCommon Mode [V]
Figure 37-53. Propagation Delay vs. VCM LPMODE Disabled, Falling Positive Input, VOD = 30 mV (T = 25°C)
80
Propagation delay [ns]
60
40
20
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VCommon Mode [V]
Figure 37-54. Propagation Delay vs. VCM LPMODE Disabled, Rising Positive Input, VOD = 30 mV (T = 25°C)
100
VDD [V]
3
5
80
Propagation delay [ns]
60
40
20
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VCommon Mode [V]
85
1.5 105
125
1.3
1.0
0.8
0.5
0.3
0.0
0 8 16 24 32 40 48 56 64
OSCCAL [x1]
Figure 37-56. OSC20M Internal Oscillator: Frequency vs. Calibration Value (VDD = 3V)
30 Temperature [°C]
-40
28 -20
0
26 25
70
24
85
Frequency [MHz]
22 105
125
20
18
16
14
12
10
0 8 16 24 32 40 48 56 64
OSCCAL [x1]
16.1
16.0
15.9
15.8
15.7
15.6
15.5
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
16.0
15.9
15.8
15.7
15.6
15.5
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
36.0
35.0
34.0
33.0
32.0
31.0
30.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
35.0
34.0
33.0
32.0
31.0
30.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
700
600
500
400
300
200
100
0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Notes:
1. Pb-free packaging complies with the European Directive for Restriction of Hazardous Substances (RoHS
directive). Also, Halide-free and fully Green.
2. Available in Tape & Reel, Tube or Tray packing media.
3. Package outline drawings can be found in the Package Drawings chapter.
ATtiny212/214/412/414 Automotive
Package Drawings
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A D
NOTE 5
N
E
2
E1
2
E1 E
2X
0.10 C A–B
2X
0.10 C A–B
NOTE 1 1 2
e NX b
B 0.25 C A–B D
NOTE 5
TOP VIEW
0.10 C
C A A2
SEATING
PLANE 8X
0.10 C
A1 SIDE VIEW
h
R0.13
h
R0.13
H 0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A - - 1.75
Molded Package Thickness A2 1.25 - -
Standoff § A1 0.10 - 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (Optional) h 0.25 - 0.50
Foot Length L 0.40 - 1.27
Footprint L1 1.04 REF
Foot Angle 0° - 8°
Lead Thickness c 0.17 - 0.25
Lead Width b 0.31 - 0.51
Mold Draft Angle Top 5° - 15°
Mold Draft Angle Bottom 5° - 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
Y1
X1
E
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 1.27 BSC
Contact Pad Spacing C 5.40
Contact Pad Width (X8) X1 0.60
Contact Pad Length (X8) Y1 1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Package Drawings
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A NOTE 5 D
N
E
2
E2
2
E1 E
2X
0.10 C D
2X N/2 TIPS
NOTE 1 1 2 3 0.20 C
e NX b
B NOTE 5 0.25 C A–B D
TOP VIEW
0.10 C
C A A2
SEATING
PLANE 14X
A1 SIDE VIEW 0.10 C
h h
H R0.13
R0.13
SEE VIEW C
L
VIEW A–A (L1)
VIEW C
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e 1.27 BSC
Overall Height A - - 1.75
Molded Package Thickness A2 1.25 - -
Standoff § A1 0.10 - 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 8.65 BSC
Chamfer (Optional) h 0.25 - 0.50
Foot Length L 0.40 - 1.27
Footprint L1 1.04 REF
Lead Angle 0° - -
Foot Angle 0° - 8°
Lead Thickness c 0.10 - 0.25
Lead Width b 0.31 - 0.51
Mold Draft Angle Top 5° - 15°
Mold Draft Angle Bottom 5° - 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14
SILK SCREEN
1 2
X
E
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 1.27 BSC
Contact Pad Spacing C 5.40
Contact Pad Width (X14) X 0.60
Contact Pad Length (X14) Y 1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
40. Errata
Customer Support
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Embedded Solutions Engineer (ESE)
• Technical Support
Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to
help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the website at: www.microchip.com/support
Note: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for
ordering purposes. Check with your Microchip Sales Office for package availability with the Tape and Reel option.
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for your
convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with
your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER
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BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,
KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST,
MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer,
QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
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All other trademarks mentioned herein are property of their respective companies.
© 2020, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-6141-8