STM8S903K3
STM8S903K3
STM8S903K3
Features
Core
• 16 MHz advanced STM8 core with Harvard LQFP32 UFQFPN32 SDIP32
7 x 7 mm 5 x 5 mm 400 mils
architecture and 3-stage pipeline
• Extended instruction set
Memories
• Program memory: 8 Kbyte Flash; data
retention 20 years at 55 °C after 10 kcycle TSSOP20 SO20 UFQFPN20
4.40 mm body 300 mils 3 x 3 mm
MSv36414V1
• Data memory: 640 byte true data EEPROM;
endurance 300 kcycle • 16-bit general purpose timer, with 3 CAPCOM
• RAM: 1 Kbyte channels (IC, OC or PWM)
• 8-bit basic timer with 8-bit prescaler
Clock, reset and supply management • Auto wake-up timer
• 2.95 to 5.5 V operating voltage • Window watchdog and independent watchdog
• Flexible clock control, 4 master clock sources timers
– Low power crystal resonator oscillator
– External clock input
Communication interfaces
– Internal, user-trimmable 16 MHz RC • UART with clock output for synchronous
– Internal low-power 128 kHz RC operation, SmartCard, IrDA, LIN master mode
• Clock security system with clock monitor • SPI interface up to 8 Mbit/s
• Power management: • I2C interface up to 400 kbit/s
– Low-power modes (wait, active-halt, halt)
Analog to digital converter (ADC)
– Switch-off peripheral clocks individually
• 10-bit, ±1 LSB ADC with up to 7 multiplexed
• Permanently active, low-consumption power-
channels + 1 internal channel, scan mode and
on and power-down reset
analog watchdog
Interrupt management • Internal reference voltage measurement
• Nested interrupt controller with 32 interrupts I/Os
• Up to 28 external interrupts on 7 vectors
• Up to 28 I/Os on a 32-pin package including
21 high sink outputs
Timers
• Highly robust I/O design, immune against
• Advanced control timer: 16-bit, 4 CAPCOM current injection
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization Unique ID
• 96-bit unique key for each device
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 13
4.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.8 Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.9 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.11 TIM5 - 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.12 TIM6 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.13 Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14.1 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14.3 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8 Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.1 Alternate function remapping bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 65
10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 68
10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.3.8 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.9 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.1 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
List of tables
List of figures
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 49. UFQFPN32 - 32-pin, 5 x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 50. UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 51. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 52. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 53. UFQFPN20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 54. SDIP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 55. SDIP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 56. TSSOP20 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 57. TSSOP20 recommended package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 58. TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 59. SO20 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 60. SO20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 61. UFQFPN recommended footprint for on-board emulation . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 62. UFQFPN recommended footprint without on-board emulation. . . . . . . . . . . . . . . . . . . . . 106
Figure 63. STM8S903K3/F3 access line ordering information scheme(1) . . . . . . . . . . . . . . . . . . . . 109
1 Introduction
This datasheet contains the description of the device features, pinout, electrical
characteristics, mechanical data and ordering information.
• For complete information on the STM8S microcontroller memory, registers and
peripherals, please refer to the STM8S microcontroller family reference manual
(RM0016).
• For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051).
• For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
• For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
2 Description
The STM8S903K3/F3 access line 8-bit microcontrollers offer 8 Kbyte Flash program
memory, plus integrated true data EEPROM. The STM8S microcontroller family reference
manual (RM0016) refers to devices in this family as low-density. They provide the following
benefits: performance, robustness, and reduced system cost.
Device performance and robustness are ensured by advanced core and peripherals made
in a state-of-the art technology, a 16 MHz clock frequency, robust I/Os, independent
watchdogs with separate clock source, and a clock security system.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k
write/erase cycles and a high system integration level with internal clock oscillators,
watchdog and brown-out reset.
Full documentation is offered as well as a wide choice of development tools.
Pin count 32 20
Maximum number of GPIOs
28(1) 16(2)
(I/Os)
Ext. interrupt pins 28 16
Timer CAPCOM channels 7
Timer complementary outputs 3 2
A/D converter channels 7 5
High sink I/Os 21 12
Low density Flash program
8K
memory (bytes)
Data EEPROM (bytes) 640(3)
RAM (bytes) 1K
Multipurpose timer (TIM1), SPI, I2C, UART window WDG,
Peripheral set
independent WDG, ADC, PWM timer (TIM5), 8-bit timer (TIM6)
1. Including 21 high-sink outputs
2. Including 12 high-sink outputs
3. No read-while-write (RWW) capability.
3 Block diagram
Detector
POR BOR
RC int. 128 kHz
Window
STM8 WDG
core
Independent WDG
640 bytes
data EEPROM
Address and data bus
8 Mbit/s SPI
Up to 4 CAPCOM
16-bit advanced channels + 3
LIN master
UART1 control timer (TM1) complementary
SPI emul.
outputs
MSv37453V1
4 Product overview
The following section provides an overview of the basic features of the device functional
modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
Addressing
• 20 addressing modes,
• Indexed indirect addressing mode for look-up tables located anywhere in the address
space,
• Stack pointer relative addressing mode for local variables and parameter passing.
Instruction set
• 80 instructions with 2-byte average instruction size,
• Standard data movement and logic/arithmetic functions,
• 8-bit by 8-bit multiplication,
• 16-bit by 8-bit and 16-bit by 16-bit division,
• Bit manipulation,
• Data transfer between stack and accumulator (push/pop) with direct stack access,
• Data transfer using the X and Y registers or direct memory-to-memory transfers.
4.2 Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in-
circuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in real-
time by means of shadow registers.
• R/W to RAM and peripheral registers in real-time
• R/W access to all resources by stalling the CPU
• Breakpoints on all program-memory instructions (software breakpoints)
• Two advanced breakpoints, 23 predefined configurations
Programmable area
UBC area from 64 bytes
Remains write protected during IAP (1 page) up to 8 Kbytes
(in 1 page steps)
Low density
Flash program
memory (8
Kbytes) Program memory area
Write access possible for IAP
MSv36479V1
Features
• Clock prescaler: to get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• Master clock sources: four different clock sources can be used to drive the master
clock:
– 1-16 MHz high-speed external crystal (HSE)
– Up to 16 MHz high-speed user-external clock (HSE user-ext)
– 16 MHz high-speed internal RC oscillator (HSI)
– 128 kHz low-speed internal RC (LSI)
• Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz
clock (HSI/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
• Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
and an interrupt can optionally be generated.
• Configurable main clock output (CCO): This outputs an external clock for use by the
application.
4.9 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit
AFR7.
Any integer
TIM1 16 from 1 to Up/down 4 3 Yes
65536
Any power of
TIM5 16 2 from 1 to Up 3 0 No Yes
32768
Any power of
TIM6 8 2 from 1 to Up 0 0 No
128
4.14.1 UART1
Main features
• 1 Mbit/s full duplex SCI
• SPI emulation
• High precision baud rate generator
• Smartcard emulation
• IrDA SIR encoder decoder
• LIN master mode
• Single wire half duplex mode
Synchronous communication
• Full duplex synchronous transfers
• SPI master operation
• 8-bit data communication
• Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)
4.14.2 SPI
• Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
• Full duplex synchronous transfers
• Simplex synchronous transfers on two lines with a possible bidirectional data line
• Master or slave operation - selectable by hardware or software
• CRC calculation
• 1 byte Tx and Rx buffer
• Slave/master selection input pin
4.14.3 I2C
• I²C master features:
– Clock generation
– Start and stop generation
• I²C slave features:
– Programmable I2C address detection
– Stop bit detection
• Generation and detection of 7-bit/10-bit addressing and general call
• Supports different communication speeds:
– Standard speed (up to 100 kHz)
– Fast speed (up to 400 kHz)
Input CM = CMOS
Level
Output HS = High sink
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
Output speed
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
float = floating,
Input
wpu = weak pull-up
Port and control
configuration T = True open drain,
Output OD = Open drain,
PP = Push pull
Bold X (pin state after internal reset release).
Reset state Unless otherwise specified, the pin state is the same during the reset
phase and after the internal reset release.
TIM5_CH1[UART1_CK]BEEP/PD4(HS) 1 20 PD3(HS)/AIN4/TIM2_CH2/ADC_ETR
AIN5/UART1_TX/ PD5(HS) 2 19 PD2(HS)/AIN3 [TIM2_CH3]
AIN6/UART1_RX/PD6(HS) 3 18 PD1(HS)/SWIM
NRST 4 17 PC7(HS)/SPI_MISO [TIM1_CH2]
OSCIN/PA1 5 16 PC6(HS)/SPI_MOSI [TIM1_CH1]
OSCOUT/PA2 6 15 PC5(HS)/SPI_SCK [TIM2_CH1]
VSS 7 14 PC4(HS)/TIM1_CH4/CLK_CCO/AIN2 [TIM1_CH2N]
VCAP 8 13 PC3(HS)/TIM1_CH3 [TLI] [TIM1_CH1N]
VDD 9 12 PB4(T)/I2C_SCL[ADC_ETR]
[SPI_NSS]/ TIM5_CH3/PA3(HS) 10 11 PB5(T)/TIM1_BKIN]I2C_SDA
MSv37454V1
PD3 (HS)/AIN4/TIM5_CH2/ADC_ETR
20 19 18 17 16
NRST 1 15
PD1(HS)/SWIM
OSCIN/PA1 2 14 PC7 (HS)/SPI_MISO [TIM1_CH2]
OSCOUT/PA2 3 13 PC6 (HS)/SPI_MOSI [TIM1_CH1]
VSS 4 12 PC5 (HS)/SPI_SCK [TIM5_CH1]
VCAP 5 11 PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2 [TIM1_CH2N]
6 7 8 9 10
[TIM1_BKIN] I2C_SDA/(T) PB5
V DD
MSv37455V1
Default alternate
Input Output
Main function
(after reset)
after remap
UFQFPN20
[option bit]
TSSOP20
Pin name
Alternate
function
function
High sink(1)
Type
floating
Speed
wpu
Ext.
OD
PP
4 1 NRST I/O - X - - - - - Reset -
Port Resonator/
5 2 PA1/ OSCIN(2) I/O X X X - O1 X X -
A1 crystal in
Port Resonator/
6 3 PA2/ OSCOUT I/O X X X - O1 X X -
A2 crystal out
7 4 VSS S - - - - - - - Digital ground -
1.8 V regulator
8 5 VCAP S - - - - - - - -
capacitor
9 6 VDD S - - - - - - - Digital power supply -
SPI master/
PA3/ TIM5_CH3 slave select
Port Timer 52
10 7 [SPI_NSS] I/O X X X HS O3 X X [AFR1]/ UART1
A3 channel 3
[UART1_TX] data transmit
[AFR1:0]
PB5/ I2C_SDA Port Timer 1 - break
11 8 I/O X - X - O1 T(3) I2C data
[TIM1_BKIN] B5 input [AFR4]
PB4/ I2C_SCL Port ADC external
12 9 I/O X - X - O1 T(3) I2C clock
[ADC_ETR] B4 trigger [AFR4]
Top level
PC3/ interrupt [AFR3]
Port Timer 1 -
13 10 TIM1_CH3/TLI/ I/O X X X HS O3 X X Timer 1 inverted
C3 channel 3
[TIM1_CH1N] channel 1
[AFR7]
Analog input 2
Timer 1 -
PC4/ TIM1_CH4/ [AFR2]Timer 1
Port channel 4
14 11 CLK_CCO/AIN2/ I/O X X X HS O3 X X inverted
C4 /configurable
[TIM1_CH2N] channel 2
clock output
[AFR7]
Timer 5
PC5/SPI_SCK Port
15 12 I/O X X X HS O3 X X SPI clock channel 1
[TIM5_CH1] C5
[AFR0]
PC6/ SPI_MOSI Port PI master Timer 1 channel
16 13 I/O X X X HS O3 X X
[TIM1_CH1] C6 out/slave in 1 [AFR0]
PC7/ SPI_MISO Port SPI master Timer 1 channel
17 14 I/O X X X HS O3 X X
[TIM1_CH2] C7 in/ slave out 2[AFR0]
Port SWIM data
18 15 PD1/ SWIM(4) I/O X X X HS O4 X X -
D1 interface
Default alternate
Input Output
Main function
(after reset)
after remap
[option bit]
UFQFPN20
TSSOP20
Pin name
Alternate
function
function
High sink(1)
Type
floating
Speed
wpu
Ext.
OD
PP
Analog input 3
PD2/AIN3/ Port [AFR2] Timer
19 16 I/O X X X HS O3 X X -
[TIM5_CH3] D2 52 - channel 3
[AFR1]
Analog input
4 Timer 52 -
PD3/ AIN4/
Port channel
20 17 TIM5_CH2/ I/O X X X HS O3 X X -
D3 2/ADC
ADC_ETR
external
trigger
Timer 5 -
PD4/ TIM5_CH1/
Port channel UART clock
1 18 BEEP I/O X X X HS O3 X X
D4 1/BEEP [AFR2]
[UART1_CK]
output
Analog input
PD5/ AIN5/ Port
2 19 I/O X X X HS O3 X X 5/ UART1 -
UART1_TX D5
data transmit
Analog input
PD6/ AIN6/ Port
3 20 I/O X X X HS O3 X X 6/ UART1 -
UART1_RX D6
data receive
1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the
total driven current must respect the absolute maximum ratings (see Section 10.2: Absolute maximum ratings).
2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for
waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode
if Halt/Active-halt is used in the application.
3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are
not implemented)
4. The PD1 pin is in input pull-up during the reset phase and after internal reset release.
PD1 (HS)/SWIM
32 31 30 29 28 27 26 25
NRST 1 24 PC7 (HS)/SPI_MISO [TIM1_CH2]
OSCIN/PA1 2 23 PC6 (HS)/SPI_MOSI [TIM1_CH1]
OSCOUT/PA2 3 22 PC5 (HS)/SPI_SCK [TIM5_CH1]
VSS 4 21 PC4 (HS)/TIM1_CH4/CLK_CCO [AIN2] [TIM1_CH2N]
VCAP 5 20 PC3 (HS)/TIM1_CH3 [TU] [TIM1_CH1N]
VDD 6 19 PC2 (HS)/TIM1_CH2 [TIM1_CH3N]
[UART1_TX] [SPI_NSS] TIM2_CH3(HS) PA3 7 18 PC1 (HS)/TIM1_CH1/UART1_CK
UART1_CK [TIM1_CH2N]
[UART1_RX] PF4 8 17 PE5/SPI_NSS [TIM1_CH1N]
9 10 11 12 13 14 15 16
[TIM1_BKIN] I2C_SDA/ (T) PB5
[ADC_ETR] I2C_SCL/(T) PB4
TIM1_ETR/AIN3/(HS) PB3
TIM1_CH1N/AIN0/(HS) PB0
TIM1_CH2N/ AIN1/(HS) PB1
MSv37456V1
MSv37457V1
Default alternate
Main function
(after reset)
after remap
[option bit]
function
Ext. interrupt
SDIP32
High sink(1)
Type
floating
Pin name
Speed
wpu
OD
PP
6 1 NRST - X - - - - - Reset -
I/O
Resonator/
7 2 PA1/ OSCIN(2) I/O X X X - O1 X X Port A1 -
crystal in
Resonator/
8 3 PA2/ OSCOUT I/O X X X - O1 X X Port A2 -
crystal out
9 4 VSS S - - - - - - - Digital ground -
10 5 VCAP S - - - - - - 1.8 V regulator capacitor -
11 6 VDD S - - - - - - - Digital power supply -
Alternate function
LQFP/ UFQFP32
Default alternate
Main function
(after reset)
after remap
[option bit]
function
Ext. interrupt
SDIP32
High sink(1)
Type
floating
Pin name
Speed
wpu
OD
PP
SPI master/
PA3/ TIM5_CH3 slave select
Timer 5 channel
12 7 [SPI_NSS] I/O X X X HS O3 X X Port A3 [AFR1] /UART1
3
[UART1_TX] data transmit
[AFR 1:0]
PF4 UART1 data
13 8 X X - - O1 X X Port F4 -
[UART1_RX] I/O receive [AFR1:0]
14 9 PB7 X X X - X X Port B7 - -
I/O O1
15 10 PB6 X X X - X X Port B6 - -
I/O O1
Alternate function
LQFP/ UFQFP32
Default alternate
Main function
(after reset)
after remap
[option bit]
function
Ext. interrupt
SDIP32
High sink(1)
Type
floating
Pin name
Speed
wpu
OD
PP
Timer 1 -
PC2/ TIM1_CH2 Timer 1 -
24 19 I/O X X X HS O3 X X Port C2 inverted channel
[TIM1_CH3N] channel 2
3 [AFR1:0]
Top level
PC3/ interrupt [AFR3]
Timer 1 -
25 20 TIM1_CH3/TLI/ I/O X X X HS O3 X X Port C3 Timer 1 inverted
channel 3
[TIM1_CH1N] channel 1
[AFR7]
PC4/ Timer 1 - Analog input 2
TIM1_CH4/ channel 4 [AFR2]Timer 1
26 21 I/O X X X HS O3 X X Port C4
CLK_CCO/AIN2/ /configurable inverted channel
[TIM1_CH2N] clock output 2 [AFR7]
PC5/SPI_SCK Timer 5 channel
27 22 I/O X X X HS O3 X X Port C5 SPI clock
[TIM5_CH1] 1 [AFR0]
PC6/ SPI_MOSI SPI master Timer 1 channel
28 23 I/O X X X HS O3 X X Port C6
[TIM1_CH1] out/slave in 1 [AFR0]
PC7/ SPI_MISO SPI master in/ Timer 1 channel
29 24 I/O X X X HS O3 X X Port C7
[TIM1_CH2] slave out 2[AFR0]
PD0/ Configurable
Timer 1 - break
30 25 TIM1_BKIN I/O X X X HS O3 X X Port D0 clock output
input
[CLK_CCO] [AFR5]
SWIM data
31 26 PD1/ SWIM(4) I/O X X X HS O4 X X Port D1 -
interface
Analog input 3
PD2/AIN3/ [AFR2] Timer 5 -
32 27 I/O X X X HS O3 X X Port D2 -
[TIM5_CH3] channel 3
[AFR1]
Analog input 4
PD3/ AIN4/
Timer 5 -
1 28 TIM5_CH2/ I/O X X X HS O3 X X Port D3 -
channel 2/ADC
ADC_ETR
external trigger
PD4/
Timer 5 -
TIM5_CH1/ UART clock
2 29 I/O X X X HS O3 X X Port D4 channel 1/BEEP
BEEP [AFR2]
output
[UART1_CK]
Analog input 5/
PD5/ AIN5/
3 30 I/O X X X HS O3 X X Port D5 UART1 data -
UART1_TX
transmit
Alternate function
LQFP/ UFQFP32
Default alternate
Main function
(after reset)
after remap
[option bit]
function
Ext. interrupt
SDIP32
High sink(1)
Type
floating
Pin name
Speed
wpu
OD
PP
Analog input 6/
PD6/ AIN6/
4 31 I/O X X X HS O3 X X Port D6 UART1 data -
UART1_RX
receive
Timer 1 -
PD7/ TLI Top level
5 32 I/O X X X HS O3 X X Port D7 channel 4
[TIM1_CH4] interrupt
[AFR6]
1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the
total driven current must respect the absolute maximum ratings (see Section 10: Electrical characteristics).
2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for
waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode
if Halt/Active-halt is used in the application.
3. In the open-drain output column, “T” defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are
not implemented).
4. The PD1 pin is in input pull-up during the reset phase and after internal reset release.
0x00 03FF
513 bytes stack
0x00 0800
Reserved
0x00 3FFF
0x00 4000
640 bytes data EEPROM
0x00 427F
0x00 4280
Reserved
0x00 47FF
0x00 4800 Option bytes
0x00 480A
0x00 480B Reserved
0x00 4864
0x00 4865
0x00 4870
Unique ID
0x00 4871
Reserved
0x00 4FFF
0x00 5000
GPIO and periph. reg.
0x00 57FF
0x00 5800
Reserved
0x00 7EFF
0x00 7F00
CPU/SWIM/debug/ITC
registers
0x00 7FFF
0x00 8000
32 interrupt vectors
0x00 807F
0x00 8080 Flash program memory
0x00 9FFF
(8 Kbytes)
0x00 A000
Reserved
0x02 7FFF
MSv36419V1
TIM1 capture/compare
0x00 526A TIM1_CCR3L 0x00
register 3 low
TIM1 capture/compare
0x00 526B TIM1_CCR4H 0x00
register 4 high
DM breakpoint 1 register
0x00 7F90 DM_BK1RE 0xFF
extended byte
DM breakpoint 1 register
0x00 7F91 DM_BK1RH 0xFF
high byte
DM breakpoint 1 register
0x00 7F92 DM_BK1RL 0xFF
low byte
DM breakpoint 2 register
0x00 7F93 DM_BK2RE 0xFF
extended byte
DM breakpoint 2 register
0x00 7F94 DM_BK2RH 0xFF
high byte
DM DM breakpoint 2 register
0x00 7F95 DM_BK2RL 0xFF
low byte
DM debug module control
0x00 7F96 DM_CR1 0x00
register 1
DM debug module control
0x00 7F97 DM_CR2 0x00
register 2
DM debug module
0x00 7F98 DM_CSR1 0x10
control/status register 1
DM debug module
0x00 7F99 DM_CSR2 0x00
control/status register 2
0x00 7F9A DM_ENFCTR DM enable function register 0xFF
0x00 7F9B to 0x00 7F9F Reserved area (5 byte)
1. Accessible by debug module only.
8 Option byte
Option byte contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option byte can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option byte can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Read-out
0x4800 protection OPT0 ROP [7:0] 0x00
(ROP)
0x4803 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 0x00
function
0x4804 remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF
(AFR)
CKAWU
0x4807 OPT4 Reserved EXT CLK PRS C1 PRS C0 0x00
SEL
Clock option
NEXT NCKA
0x4808 NOPT4 Reserved NPRSC1 NPR SC0 0xFF
CLK WUSEL
Table 14. STM8S903F3 alternate function remapping bits [7:2] for 20-pin packages
Table 15. STM8S903K3 alternate function remapping bits [1:0] for 32-pin packages
Alternate function
AFR1 option bit value AFR0 option bit value I/O port
mapping
Table 15. STM8S903K3 alternate function remapping bits [1:0] for 32-pin packages
(continued)
Alternate function
AFR1 option bit value AFR0 option bit value I/O port
mapping
PD2 TIM5_CH3
PC5 TIM5_CH1
PC6 TIM1_CH1
PC7 TIM1_CH2
1 1 PC2 TIM1_CH3N
PC1 TIM1_CH2N
PE5 TIM1_CH1N
PA3 UART1_TX
PF4 UART1_RX
1. Refer to STM8S903K3 pin description.
Table 16. STM8S903F3 alternate function remapping bits [1:0] for 20-pin packages
Alternate function
AFR1 option bit value AFR0 option bit value I/O port
mapping
9 Unique ID
The devices feature a 96-bit unique device identifier which provides a reference number that
is unique for any device and in any context. The 96 bits of the identifier can never be altered
by the user.
The unique device identifier can be read in single byte and may then be concatenated using
a custom algorithm.
The unique device identifier is ideally suited:
• For use as serial numbers
• For use as security keys to increase the code security in the program memory while
using and combining this unique ID with software cryptographic primitives and
protocols before programming the internal memory.
• To activate secure boot processes
7 6 5 4 3 2 1 0
10 Electrical characteristics
STM8S PIN
50 pF
MSv36480V1
STM8S PIN
VIN
MSv36481V1
VDDx - VSS Supply voltage (including VDDA and VDDIO)(1) -0.3 6.5 V
Input voltage on true open drain pins(2) VSS - 0.3 6.5
VIN V
Input voltage on any other pin(2) VSS - 0.3 VDD + 0.3
TSSOP20 - 45
SO20W - 250
fCPU (MHz)
Functionality
not
guaranteed in
this area
16
12 Functionality guaranteed
@TA -40 to 125 °C
8
4
0
2.95 4.0 5.0 5.5
Supply voltage
MSv36469V1
ESR
RLeak
MSv36488V1
1. ESR is the equivalent series resistance and ESL is the equivalent inductance.
Table 23. Total current consumption with code execution in run mode at VDD = 5 V
Symbol Parameter Conditions Typ Max(1) Unit
Table 23. Total current consumption with code execution in run mode at VDD = 5 V (continued)
Symbol Parameter Conditions Typ Max(1) Unit
Table 24. Total current consumption with code execution in run mode at VDD = 3.3 V
Symbol Parameter Conditions Typ Max(1) Unit
Table 28. Total current consumption in active halt mode at VDD = 3.3 V
Conditions
Table 32. Total current consumption and timing in forced reset state
Symbol Parameter Conditions Typ Max(1) Unit
Figure 12. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz
Figure 13. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V
Figure 14. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz
Figure 15. Typ IDD(WFI) vs. VDD HSE external clock, fCPU = 16 MHz
Figure 16. Typ IDD(WFI) vs. fCPU HSE external clock, VDD = 5 V
Figure 17. Typ IDD(WFI) vs. VDD HSI RC osc., fCPU = 16 MHz
VHSEH
V HSEL
fHSE
External clock
source
OSCIN
STM8
MS36489V2
Rm
fHSE to core
CO RF
Lm
CL1
Cm OSCIN gm
Resonator
Consumption
control
Resonator
OSCOUT
CL2
STM8
MS36490V3
Operating voltage
VDD fCPU≤ 16 MHz 2.95 - 5.5 V
(all modes, execution/write/erase)
Standard programming time (including
erase) for byte/word/block - - 6 6.6
tprog (1 byte/4 byte/64 byte)
ms
Fast programming time for 1 block
- - 3 3.33
(64 byte)
terase Erase time for 1 block (64 byte) - - 3 3.33
Data retention (program and data
memory) after 10k erase/write cycles TRET = 55 °C 20 - -
at TA= +55 °C
tRET year
Data retention (data memory) after
300k erase/write cycles at TRET = 85 °C 1 - -
TA= +125°C
Supply current (Flash programming or
IDD - - 2 - mA
erasing for 1 to 128 byte)
1. Guaranteed by characterization results.
Figure 22. Typical VIL and VIH vs VDD @ 4 Figure 23. Typical pull-up current vs VDD @ 4
temperatures temperatures
-ÛC
60 ÛC
ÛC
55 ÛC
Pull-up resistance [ W]
50
45
40
35
30
2.5 3 3.5 4 4.5 5 5.5 6
VDD [V] MS37434V1
Figure 25. Typ. VOL @ VDD = 3.3 V (standard Figure 26. Typ. VOL @ VDD = 5.0 V (standard
ports) ports)
Figure 27. Typ. VOL @ VDD = 3.3 V (true open Figure 28. Typ. VOL @ VDD = 5.0 V (true open
drain ports) drain ports)
Figure 29. Typ. VOL @ VDD = 3.3 V (high sink Figure 30. Typ. VOL @ VDD = 5.0 V (high sink
ports) ports)
Figure 31. Typ. VDD - VOH @ VDD = 3.3 V Figure 32. Typ. VDD - VOH @ VDD = 5.0 V
(standard ports) (standard ports)
Figure 33. Typ. VDD - VOH @ VDD = 3.3 V (high Figure 34. Typ. VDD - VOH @ VDD = 5.0 V (high
sink ports) sink ports)
VIH(NRST) NRST input high level voltage(1) IOL= 2 mA 0.7 x VDD - VDD+ 0.3 V
The reset network shown in Figure 38 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below VIL(NRST) max (see Table 44:
NRST pin characteristics), otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external
circuitry, attention must be taken to the charge/discharge time of the external capacitor to
fulfill the external devices reset timing conditions. Minimum recommended capacity is
100 nF.
VDD STM8
RPU
External
reset NRST )LOWHU
circuit
ȝ)
(Optional)
MSv36491V1
Figure 39. SPI timing diagram where slave mode and CPHA = 0
NSS input
SCK input
MOSI
MSB IN BIT1 IN LSB IN
INPUT
(SI)
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
Figure 40. SPI timing diagram where slave mode and CPHA = 1
NSS input
CPHA=1
CPOL=0 tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1
tr(SCK)
tv(SO) th(SO) tdis(SO)
ta(SO) tf(SCK)
MISO
MSB OUT BIT6 OUT LSB OUT
OUTPUT
tsu(SI) th(SI)
MOSI
INPUT MSB IN BIT 1 IN LSB IN
ai14135b
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
High
NSS input
tc(SCK)
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(MO) th(MO)
ai14136c
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
Figure 42. Typical application with I2C bus and timing diagram
VDD VDD
STM8
4.7 k 4.7 k 100
SDA
I2C bus 100 SCL
Repeated
start
START
tsu(STA) tw(STO:STA)
START
SDA
SCL
0 1 2 3 4 5 6 7 1021102210231024
VSSA VDDA
VDD STM8
VT
VAIN RAIN 0.6 V
AINx 10-bit A/D
conversion
VT
CAIN IL CADC
0.6 V ± 1 μA
MSv38300V1
1. Legend: RAIN = external resistance, CAIN = capacitors, Csamp = internal sample and hold capacitor.
1. Data obtained with HSI clock configuration, after applying the hardware recommendations described in
AN2860 (EMC guidelines for STM8S microcontrollers).
Max fCPU(1)
Symbol Parameter Unit
Monitored
General conditions
frequency band 16 MHz/ 16 MHz/
8 MHz 16 MHz
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up
performance.
• A supply overvoltage (applied to each power supply pin), and
• A current injection (applied to each input, output and configurable I/O pin) are
performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
TA = 25 °C
LU Static latch-up class TA = 85 °C A
TA = 125 °C
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).
11 Package information
SEATING
PLANE
C
A2
A
c
A1
0.25 mm
GAUGE PLANE
ccc C
K
D
L
A1
D1
L1
D3
24 17
25 16
b
E1
E3
32 9
PIN 1
IDENTIFICATION 1 8
e 5V_ME_V2
Table 54. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.600 - - 0.2205 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.600 - - 0.2205 -
e - 0.800 - - 0.0315 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
1.20
24 17
25 16 0.50
0.30
7.30
6.10
9.70
7.30
32 9
1 8
1.20
6.10
9.70
5V_FP_V2
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Product (1)
identification
STM8S
903K3T3C
Date code
Standard ST logo
Y WW
Revision code
Pin 1 identifier
MS37474V1
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
ddd C
e A1
C
A2
SEATING
PLANE
D1
b
E2 b
E1 E
1
L
32
D2 L
PIN 1 Identifier
A0B8_ME_V2
Table 55. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
Figure 49. UFQFPN32 - 32-pin, 5 x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package recommended footprint
5.30
3.80
0.60
32 25
1 24
3.45
5.30 3.80
3.45
0.50
0.30 8 17
9 16 0.75
3.80
A0B8_FP_V2
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Product
(1)
identification
8S903K3
Date code
Y WW Revision code
Standard ST logo R
Dot (pin 1)
MS37475V1
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
Pin 1 E
TOP VIEW
L1
D
ddd
L3 D1
e 10 L2 A3
5
e
b
E1 E
1
15
20 16
L5 A1
A
Table 56. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
Table 56. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data (continued)
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
Section 11.7: UFQFPN recommended footprint shows the recommended footprints for
UFQFPN with and without on-board emulation.
Figure 52. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint
A0A5_FP_V2
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Product
(1)
identification
S903
Y WW R
Dot (pin 1)
MS37476V1
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
E1
A2 A
A1 L
B1 B e
C eA
eB
32 17
1 16
76_ME
eB - - 12.700 - - 0.5000
L 2.540 3.048 3.810 0.1000 0.1200 0.1500
1. Values in inches are converted from mm and rounded to 4 decimal digits
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Product (1)
identification Revision code
STM8S903K3B6
Pin 1 identifier Date code
Standard ST logo
R
Y WW
MS37473V1
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
20 11
c
E1 E
SEATING 0.25 mm
PLANE GAUGE PLANE
C
1 10
PIN 1
IDENTIFICATION
k
aaa C A1 L
A A2
L1
b e
YA_ME_V3
A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079
(2)
D 6.400 6.500 6.600 0.2520 0.2559 0.2598
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
E1(3) 4.300 4.400 4.500 0.1693 0.1732 0.1772
e - 0.650 - - 0.0256 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0.0° - 8.0° 0.0° - 8.0°
aaa - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25mm per side.
1.35
0.25
7.10 4.40
1.35
1 10
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Standard ST logo
Product (1)
identification
8S903F3P3
Date code Revision code
Pin 1 identifier
Y WW R
MS37472V1
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
D
h x 45°
E H
0.25 mm
GAUGE PLANE
A1 L
A
ddd
B e A1
Z7_ME_V2
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Standard ST logo
Revision code
Product R
(1)
identification
8S903F3M3
Date code
Pin 1 identifier
Y WW
MS37471V1
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
2.30
0.50
20 16
1 15
2.20
3.30 2.30
0.55
2.20
0.30 5 11
0.50
6 10
0.50
3.30
MS36498V1
12 Thermal characteristics
The maximum junction temperature (TJmax) of the device must never exceed the values
specified in Table 21: General operating conditions, otherwise the functionality of the device
cannot be guaranteed.
The maximum junction temperature TJmax, in degrees Celsius, may be calculated using the
following equation:
TJmax = TAmax + (PDmax x ΘJA)
Where:
• TAmax is the maximum ambient temperature in ° C
• ΘJA is the package junction-to-ambient thermal resistance in ° C/W
• PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
• PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
• PI/Omax represents the maximum power dissipation on output pins
Where:
PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*IOH),
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in
the application.
13 Ordering information
Family type
S = Standard
Sub-family type
903 = 903 sub-family
Pin count
K = 32 pins
F= 20 pins
Program memory size
3 = 8 Kbytes
Package type
B = SDIP
T = LQFP
U = UFQFPN
P = TSSOP
M = SO
Temperature range
3 = -40 to 125 °C
6 = -40 to 85 °C
Package pitch
Blank = 0.5 to 0.65 mm(2)
C = 0.8 mm(3)
Packing
No character = Tray or tube
TR = Tape and reel
1. A dedicated ordering information scheme will be released if, in the future, memory programming service
(FastROM) is required The letter “P” will be added after STM8S. Three unique letters identifying the
customer application code will also be visible in the codification. Example: STM8SP903K3MACTR.
2. UFQFPN, TSSOP, and SO packages.
3. LQFP package.
For a list of available options (for example memory size, package) and orderable part
numbers or for further information on any aspect of this device, please go to www.st.com or
contact the ST Sales Office nearest to you.
Temperature range
[ ] -40°C to +85°C or [ ] -40°C to +125°C
Padding value for unused program memory (check only one option)
[ ] 0xFF Fixed value
[ ] 0x83 TRAP instruction code
[ ] 0x75 Illegal opcode (causes a reset when executed)
[ ] 0: Reset
UBC, bit0
[ ] 1: Set
[ ] 0: Reset
UBC, bit1
[ ] 1: Set
[ ] 0: Reset
UBC, bit2
[ ] 1: Set
[ ] 0: Reset
UBC, bit3
[ ] 1: Set
[ ] 0: Reset
UBC, bit4
[ ] 1: Set
[ ] 0: Reset
UBC, bit5
[ ] 1: Set
[ ] 0: Reset
UBC, bit6
[ ] 1: Set
[ ] 0: Reset
UBC, bit7
[ ] 1: Set
Note: If the UBC area is not used, please select all bits at reset states.
OPT3 watchdog
OPT4 watchdog
[ ] for 16 MHz to 128 kHz prescaler
PRSC
[ ] for 8 MHz to 128 kHz prescaler
(check only one option)
[ ] for 4 MHz to 128 kHz prescaler
CKAWUSEL [ ] LSI clock source selected for AWU
(check only one option) [ ] HSE clock with prescaler selected as clock source for AWU
EXTCLK [ ] External crystal connected to OSCIN/OSCOUT
(check only one option) [ ] External signal on OSCIN
OTP6 is reserved
Comments: .........................................................................................
Supply operating range in the application: .........................................................................................
Notes: .........................................................................................
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation
boards and a low-cost in-circuit debugger/programmer.
ST visual develop
Full-featured integrated development environment from STMicroelectronics, featuring:
• Seamless integration of C and ASM toolsets
• Full-featured debugger
• Project management
• Syntax highlighting editor
• Integrated programming interface
• Support of advanced emulation features for STice such as code profiling and coverage
The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
16 Revision history
Updated:
– Section 11.5: TSSOP20 package information
– Section 11.3: UFQFPN20 package information.
Added:
– Figure 46: LQFP32 recommended footprint
– Figure 47: LQFP32 marking example (package top
view)
– Figure 50: UFQFPN32 marking example (package top
23-Feb-2015 9 view)
– Figure 53: UFQFPN20 marking example (package top
view)
– Figure 55: SDIP32 marking example (package top
view)
– Figure 57: TSSOP20 recommended package footprint
– Figure 58: TSSOP20 marking example (package top
view)
– Figure 60: SO20 marking example (package top view)
Corrected the values for “b” dimensions in Table 55:
26-Mar-2015 10 UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin
fine pitch quad flat package mechanical data.
Updated:
– Analog to digital converter (ADC) features on Section :
Features
– Section 10.2: Absolute maximum ratings
– Table 5: TSSOP20/SO20/UFQFPN20 pin descriptions
– Table 19: Current characteristics
– Table 33: Peripheral current consumption
– Table 47: ADC characteristics
– Table 56: UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm
pitch, ultra thin fine pitch quad flat package
mechanical data
– Figure 18: HSE external clock source
– Figure 19: HSE oscillator circuit diagram
– Figure 40: SPI timing diagram where slave mode and
CPHA = 1
– Figure 41: SPI timing diagram - master mode
– Figure 44: Typical application with ADC
– Section : Electromagnetic interference (EMI)
13-Feb-2017 11 – All “Device marking” sections on Section 11: Package
information
– Footnotes on the tables of Section 10: Electrical
characteristics and of Figure 48: UFQFPN32 - 32-pin,
5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline
– Title of Table 54: LQFP32 - 32-pin, 7 x 7 mm low-
profile quad flat package mechanical data and
Table 56: UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm
pitch, ultra thin fine pitch quad flat package
mechanical data
– Title of Figure 45: LQFP32 - 32-pin, 7 x 7 mm low-
profile quad flat package outline, Figure 46: LQFP32 -
32-pin, 7 x 7 mm low-profile quad flat package
recommended footprint, Figure 51: UFQFPN20 - 20-
lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad
flat package outline
Added:
– Figure 52: UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm
pitch, ultra thin fine pitch quad flat package
recommended footprint
Updated:
– Figure 51: UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm
pitch, ultra thin fine pitch quad flat package outline
12-May-2017 12
– Table 56: UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm
pitch, ultra thin fine pitch quad flat package
mechanical data
Updated Figure 63: STM8S903K3/F3 access line
03-Apr-2023 13 ordering information scheme(1)
Added the Chapter 15: Important security notice
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.