Dpco1&2 Notes
Dpco1&2 Notes
Dpco1&2 Notes
COMBINATIONAL LOGIC
Combinational Circuits – Karnaugh Map - Analysis and Design Procedures – Binary Adder –
Subtractor – Decimal Adder - Magnitude Comparator – Decoder – Encoder – Multiplexers -
UNIT II COMBINATIONAL
Demultiplexers CIRCUITS:
INTRODUCTION:
The digital system consists of two types of circuits, namely
(i) Combinational circuits
(ii) Sequential circuits
Sequential logic circuit comprises both logic gates and the state of storage
elements such as flip-flops. As a consequence, the output of a sequential circuit depends
not only on present value of inputs but also on the past state of inputs.
In the previous chapter, we have discussed binary numbers, codes, Boolean
algebra and simplification of Boolean function and logic gates. In this chapter,
formulation and analysis of various systematic designs of combinational circuits will be
discussed.
The following guidelines should be followed while choosing the preferred form
for hardware implementation:
1. The implementation should have the minimum number of gates, with the
gates used having the minimum number of inputs.
2. There should be a minimum number of interconnections.
3. Limitation on the driving capability of the gates should not be ignored.
Half-Adder:
A half-adder is a combinational circuit that can be used to add two binary bits. It
has two inputs that represent the two bits to be added and two outputs, with one
producing the SUM output and the other producing the CARRY.
Block schematic of half-adder
The truth table of a half-adder, showing all possible input combinations and
the corresponding outputs are shown below.
Inputs Outputs
A B Carry (C) Sum (S)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Truth table of half-adder
The Boolean expressions for the SUM and CARRY outputs are given by the
equations,
Sum, S = A’B+ AB’= A†B
Carry, C = A . B
The first one representing the SUM output is that of an EX-OR gate, the second
one representing the CARRY output is that of an AND gate.
The logic diagram of the half adder is,
The full adder circuit overcomes the limitation of the half-adder, which can be
used to add two bits only. As there are three input variables, eight different input
combinations are possible. The truth table is shown below,
Truth Table:
Inputs Outputs
A B Cin Sum (S) Carry (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
To derive the simplified Boolean expression from the truth table, the Karnaugh map
method is adopted as,
The Boolean expressions for the SUM and CARRY outputs are given by the
equations,
Sum, S = A’B’Cin+ A’BC’in + AB’C’in + ABCin
Carry, Cout = AB+ ACin + BCin .
The logic diagram of the full adder can also be implemented with two half-
adders and one OR gate. The S output from the second half adder is the exclusive-OR of
Cin and the output of the first half-adder, giving
Half -Subtractor:
A half-subtractor is a combinational circuit that can be used to subtract one binary
digit from another to produce a DIFFERENCE output and a BORROW output. The
BORROW output here specifies whether a ‗1‘ has been borrowed to perform the
subtraction.
The Boolean expressions for the DIFFERENCE and BORROW outputs are given
by the equations,
Difference, D = A’B+ AB’= A † B
Borrow, Bout = A’ . B
The Boolean expressions for the DIFFERENCE and BORROW outputs are given
by the equations,
Difference, D = A’B’Bin+ A’BB’in + AB’B’in + ABBin
Borrow, Bout = A’B+ A’Cin + BBin .
The logic diagram for the above functions is shown as,
Implementation of full-adder in Sum of Products
The logic diagram of the full-subtractor can also be implemented with two half-
subtractors and one OR gate. The difference,D output from the second half subtractor
is the exclusive-OR of Bin and the output of the first half-subtractor, giving
Difference,D= Bin † (A † B) [x † y = x‘y+ xy‘]
= Bin † (A‘B+AB‘)
= B‘in (A‘B+AB‘) + Bin (A‘B+AB‘)‘ [(x‘y+xy‘)‘= (xy+x‘y‘)]
= B‘in (A‘B+AB‘) + Bin (AB+A‘B‘)
= A‘BB‘in + AB‘B‘in + ABBin + A‘B‘Bin
. and the borrow output is,
Therefore,
we can implement full-subtractor using two half-subtractors and OR gate as,
Since all the bits of augend and addend are fed into the adder circuits
simultaneously and the additions in each position are taking place at the same time, this
circuit is known as parallel adder.
The bits are added with full adders, starting from the least significant position, to
form the sum it and carry bit. The input carry C0 in the least significant position must be
0. The carry output of the lower order stage is connected to the carry input of the next
higher order stage. Hence this type of adder is called ripple-carry adder.
In the least significant stage, A0, B0 and C0 (which is 0) are added resulting in
sum S0 and carry C1. This carry C1 becomes the carry input to the second stage.
Similarly in the second stage, A1, B1 and C1 are added resulting in sum S1 and carry C2,
in the third stage, A2, B2 and C2 are added resulting in sum S2 and carry C3, in the third
stage, A3, B3 and C3 are added resulting in sum S3 and C4, which is the output carry.
Thus the circuit results in a sum (S3S2S1S0) and a carry output (Cout).
Though the parallel binary adder is said to generate its output immediately after
the inputs are applied, its speed of operation is limited by the carry propagation delay
through all stages. However, there are several methods to reduce this delay.
One of the methods of speeding up this process is look-ahead carry addition
which eliminates the ripple-carry delay.
Using a Look-ahead Generator we can easily construct a 4-bit parallel adder with
a Look-ahead carry scheme. Each sum output requires two exclusive-OR gates. The
output of the first exclusive-OR gate generates the Pi variable, and the AND gate
generates the Gi variable. The carries are propagated through the carry look-ahead
generator and applied as inputs to the second exclusive-OR gate. All output carries are
generated after a delay through two levels of gates. Thus, outputs S1 through S3 have
equal propagation delay times.
4-Bit Adder with Carry Look-ahead
The mode input M controls the operation. When M= 0, the circuit is an adder and
when M=1, the circuit becomes a Subtractor. Each exclusive-OR gate receives input M
and one of the inputs of B. When M=0, we have B 0= B. The full adders receive the
value of B, the input carry is 0, and the circuit performs A plus B. When M=1, we have B
1= B‘ and C0=1. The B inputs are all complemented and a 1 is added through the input
carry. The circuit performs the operation A plus the 2‘s complement of B. The exclusive-
OR with output V is for detecting an overflow.
In examining the contents of the table, it is apparent that when the binary sum is
equal to or less than 1001, the corresponding BCD number is identical, and therefore no
conversion is needed. When the binary sum is greater than 9 (1001), we obtain a non-
valid BCD representation. The addition of binary 6 (0110) to the binary sum converts it
to the correct BCD representation and also produces an output carry as required.
The logic circuit to detect sum greater than 9 can be determined by simplifying
the boolean expression of the given truth table.
To implement BCD adder we require:
x 4-bit binary adder for initial addition
x Logic circuit to detect sum greater than 9 and
x One more 4-bit adder to add 01102 in the sum if the sum is greater than 9 or
carry is 1.
The two decimal digits, together with the input carry, are first added in the top4-
bit binary adder to provide the binary sum. When the output carry is equal to zero,
nothing is added to the binary sum. When it is equal to one, binary 0110 is added to
the binary sum through the bottom 4-bit adder. The output carry generated from the
bottom adder can be ignored, since it supplies information already available at the
output carry terminal. The output carry from one stage must be connected to the
input carry of the next higher-order stage.
Binary Multiplier:
Multiplication of binary numbers is performed in the same way as in decimal
numbers. The multiplicand is multiplied by each bit of the multiplier starting from the
least significant bit. Each such multiplication forms a partial product. Such partial
products are shifted one position to the left. The final product is obtained from the sum
of partial products.
Consider the multiplication of two 2-bit numbers. The multiplicand bits are B1
and B0, the multiplier bits are A1 and A0, and the product is C3, C2, C1 and C0. The first
partial product is formed by multiplying A0 by B1B0. The multiplication of two bits such
as A0 and B0 produces a 1 if both bits are 1; otherwise, it produces a 0. This is identical
to an AND operation. Therefore the partial product can be implemented with AND
gates as shown in the diagram below.
The second partial product is formed by multiplying A1 by B1B0 and shifted one
position to the left. The two partial products are added with two half adder (HA)
circuits.
Usually there are more bits in the partial products and it is necessary to use full
adders to produce the sum of the partial products. The least significant bit of the
product does not have to go through an adder since it is formed by the output of the
first AND gate.
A combinational circuit binary multiplier with more bits can be constructed in a
similar fashion. A bit of the multiplier is ANDed with each bit of the multiplicand in as
many levels as there are bits in the multiplier. The binary output in each level of AND
gates are added with the partial product of the previous level to form a new partial
product. The last level produces the product. For J multiplier bits and K multiplicand
bits we need (J x K) AND gates and (J-1) k-bit adders to produce a product of J+K bits.
Consider a multiplier circuit that multiplies a binary number of four bits by a
number of three bits. Let the multiplicand be represented by B3, B2, B1, B0 and the
multiplier by A2, A1, and A0. Since K= 4 and J= 3, we need 12 AND gates and two 4-bit
adders to produce a product of seven bits. The logic diagram of the multiplier is shown
below.
4-bit by 3-bit Binary multiplier
Parity Generator:
A parity generator is a combination logic system to generate the parity bit at the
transmitting side. A table illustrates even parity as well as odd parity for a message
consisting of three bits.
If the message bit combination is designated as A, B, C and Pe, Po are the even
and odd parity respectively, then it is obvious from table that the boolean expressions
of even parity and odd parity are
Pe = A†
B†C) and
Po = (A†B†C)′.
K-map Simplification:
Parity Checker:
The message bits with the parity bit are transmitted to their destination, where
they are applied to a parity checker circuit. The circuit that checks the parity at the
receiver side is called the parity checker. The parity checker circuit produces a check bit
and is very similar to the parity generator circuit. If the check bit is 1, then it is assumed
that the received data is incorrect. The check bit will be 0 if the received data is correct.
The table shows the truth table for the even parity checker.
PEC= A’B’ (C’D+ CD’) + A’B (C’D’+ CD) + AB (C’D+ CD’) + AB’ (C’D’+ CD)
= A’B’ (C†D) + A’B (C†D)’ + AB (C†D) + AB’ (C†D)’
= (A’B’+ AB) (C†D) + (A’B+ AB’) (C†D)’
= (A†B)’ (C†D) + (A†B) (C†D)’
= (A†B) † (C†D)
Logic Diagram:
MAGNITUDE COMPARATOR:
Inputs Outputs
A3 A2 A1 A0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
K-map Simplification:
Logic Diagram:
2- bit Magnitude Comparator
4-bit Magnitude Comparator:
Let us consider the two binary numbers A and B with four digits each. Write
the coefficient of the numbers in descending order as,
A = A3A2A1A0
B = B3 B2 B1 B0,
Each subscripted letter represents one of the digits in the number. It is observed from
the bit contents of two numbers that A = B when A3 = B3, A2 = B2, A1 = B1 and A0 = B0.
When the numbers are binary they possess the value of either 1 or 0, the equality
relation of each pair can be expressed logically by the equivalence function as
Xi = AiBi + Ai′Bi′ for i = 1, 2, 3, 4.
Or, Xi = (A † B)′. or, Xi ′ = A † B
Or, Xi = (AiBi′ + Ai′Bi)′.
where,
Xi =1 only if the pair of bits in position i are equal (ie., if both are 1 or both are 0).
To satisfy the equality condition of two numbers A and B, it is necessary that all
Xi must be equal to logic 1. This indicates the AND operation of all Xi variables. In other
words, we can write the Boolean expression for two equal 4-bit numbers.
(A = B) = X3X2X1 X0.
The binary variable (A=B) is equal to 1 only if all pairs of digits of the two numbers
are equal.
To determine if A is greater than or less than B, we inspect the relative
magnitudes of pairs of significant bits starting from the most significant bit. If the two
digits of the most significant position are equal, the next significant pair of digits is
compared. The comparison process is continued until a pair of unequal digits is found.
It may be concluded that A>B, if the corresponding digit of A is 1 and B is 0. If the
corresponding digit of A is 0 and B is 1, we conclude that A<B. Therefore, we can derive
the logical expression of such sequential comparison by the following two Boolean
functions,
The symbols (A>B) and (A<B) are binary output variables that are equal to 1 when
A>B or A<B, respectively.
The gate implementation of the three output variables just derived is simpler
than it seems because it involves a certain amount of repetition. The unequal outputs
can use the same gates that are needed to generate the equal output. The logic
diagram of the 4-bit magnitude comparator is shown below,
4-bit Magnitude Comparator
The four x outputs are generated with exclusive-NOR circuits and applied to
an AND gate to give the binary output variable (A=B). The other two outputs use the
x variables to generate the Boolean functions listed above. This is a multilevel
implementation and has a regular pattern.
CODE CONVERTERS:
A code converter is a logic circuit that changes data presented in one type of
binary code to another code of binary code. The following are some of the most
commonly used code converters:
i. Binary-to-Gray code
ii. Gray-to-Binary code
iii. BCD-to-Excess-3
iv. Excess-3-to-BCD
v. Binary-to-BCD
vi. BCD-to-binary
vii. Gray-to-BCD
viii. BCD-to-Gray
ix. 8 4 -2 -1 to BCD converter
Truth table:
Binary code Gray code
Decimal
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
K-map simplification:
Now, the above expressions can be implemented using EX-OR gates as,
Logic Diagram:
Truth table:
Gray code Binary code
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0
From the truth table, the logic expression for the binary code outputs can be written as,
G3= ∑m (8, 9, 10, 11, 12, 13, 14, 15)
G2= ∑m (4, 5, 6, 7, 8, 9, 10, 11)
G1= ∑m (2, 3, 4, 5, 8, 9, 14, 15)
G0= ∑m (1, 2, 4, 7, 8, 11, 13, 14)
K-map Simplification:
Truth Table:
BCD code Excess-3 code
Decimal
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
From the truth table, the logic expression for the Excess-3 code outputs can be
written as,
E3= ∑m (5, 6, 7, 8, 9) + ∑d (10, 11, 12, 13, 14, 15)
E2= ∑m (1, 2, 3, 4, 9) + ∑d (10, 11, 12, 13, 14, 15)
E1= ∑m (0, 3, 4, 7, 8) + ∑d (10, 11, 12, 13, 14, 15)
E0= ∑m (0, 2, 4, 6, 8) + ∑d (10, 11, 12, 13, 14, 15)
K-map Simplification:
Logic Diagram:
4. Excess-3 to BCD
K-map Simplification:
Now, the above expressions the logic diagram can be implemented as,
Logic Diagram:
The left-most four-bit group represents 10 and right-most four-bit group represents 9.
The binary representation for decimal 19 is 1910 = 110012.
BCD Code Binary
B4 B3 B2 B1 B0 E D C B A
0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 1 1
0 0 1 0 0 0 0 1 0 0
0 0 1 0 1 0 0 1 0 1
0 0 1 1 0 0 0 1 1 0
0 0 1 1 1 0 0 1 1 1
0 1 0 0 0 0 1 0 0 0
0 1 0 0 1 0 1 0 0 1
1 0 0 0 0 0 1 0 1 0
1 0 0 0 1 0 1 0 1 1
1 0 0 1 0 0 1 1 0 0
1 0 0 1 1 0 1 1 0 1
1 0 1 0 0 0 1 1 1 0
1 0 1 0 1 0 1 1 1 1
1 0 1 1 0 1 0 0 0 0
1 0 1 1 1 1 0 0 0 1
1 1 0 0 0 1 0 0 1 0
1 1 0 0 1 1 0 0 1 1
K-map Simplification:
From the above K-map,
A= B0
B= B1B4‘+ B1’B4
= B1†B4
E= B4B3 + B4B2B1
Now, from the above expressions the logic diagram can be implemented as,
Logic Diagram:
6. Binary to BCD Converter:
The truth table for binary to BCD converter can be written as,
Truth Table:
Binary Code BCD Code
Decimal
D C B A B4 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 0 1
2 0 0 1 0 0 0 0 1 0
3 0 0 1 1 0 0 0 1 1
4 0 1 0 0 0 0 1 0 0
5 0 1 0 1 0 0 1 0 1
6 0 1 1 0 0 0 1 1 0
7 0 1 1 1 0 0 1 1 1
8 1 0 0 0 0 1 0 0 0
9 1 0 0 1 0 1 0 0 1
10 1 0 1 0 1 0 0 0 0
11 1 0 1 1 1 0 0 0 1
12 1 1 0 0 1 0 0 1 0
13 1 1 0 1 1 0 0 1 1
14 1 1 1 0 1 0 1 0 0
15 1 1 1 1 1 0 1 0 1
From the truth table, the logic expression for the BCD code outputs can be written as,
B0= ∑m (1, 3, 5, 7, 9, 11, 13, 15)
B1= ∑m (2, 3, 6, 7, 12, 13)
B2= ∑m (4, 5, 6, 7, 14, 15)
B3= ∑m (8, 9)
B4= ∑m (10, 11, 12, 13, 14, 15)
K-map Simplification:
From the above K-map, the logical expression can be obtained
as, B0= A
B1= DCB’+ D’B
B2= D’C+ CB
B3= DC’B’
B4= DC+ DB
Now, from the above expressions the logic diagram can be implemented as,
Logic Diagram:
7. Gray to BCD Converter:
The truth table for gray to BCD converter can be written as,
Truth Table:
K-map Simplification:
From the above K-map, the logical expression can be obtained as,
B0= (G0†G1) † (G2†G3)
B1= G’2G1+ G’3G2G’1
B2= G’3G2+ G3G’2G’1
B3= G3G2G’1
B4= G3G’2+ G3G1
Now, from the above expressions the logic diagram can be implemented as,
Logic Diagram:
8. BCD to Gray Converter:
The truth table for gray to BCD converter can be written as,
Truth table:
BCD Code (8421) Gray code
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
K-map Simplification:
Now, from the above expressions the logic diagram can be implemented as,
Logic Diagram:
9. 8 4 -2 -1 to BCD Converter:
The truth table for 8 4 -2 -1 to BCD converter can be written as,
Truth Table:
Gray Code BCD Code
D C B A B4 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0
0 1 1 1 0 0 0 0 1
0 1 1 0 0 0 0 1 0
0 1 0 1 0 0 0 1 1
0 1 0 0 0 0 1 0 0
1 0 1 1 0 0 1 0 1
1 0 1 0 0 0 1 1 0
1 0 0 1 0 0 1 1 1
1 0 0 0 0 1 0 0 0
1 1 1 1 0 1 0 0 1
1 1 1 0 1 0 0 0 0
1 1 0 1 1 0 0 0 1
1 1 0 0 1 0 0 1 0
K-map Simplification:
From the above K-map, the logical expression can be obtained as,
B0 = A
B1= A’B’CD+ (A†B) (C’+D’)
B2= D’CB’A’+ C’ (A+B)
B3= D (ABC+ A’B’C’)
B4= CD ( A’+B’)
Logic Diagram:
DECODERS:
A decoder is a combinational circuit that converts binary information from ‗n‘
input lines to a maximum of ‗2n‘ unique output lines. The general structure of
decoder circuit is –
Here the 2 inputs are decoded into 4 outputs, each output representing one of the
minterms of the two input variables.
Inputs Outputs
Enable A B Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
As shown in the truth table, if enable input is 1 (EN= 1) only one of the outputs
(Y0 – Y3), is active for a given input.
The output Y0 is active, ie., Y0= 1 when inputs A= B= 0,
Y1 is active when inputs, A= 0 and B= 1,
Y2 is active, when input A= 1 and B= 0,
Y3 is active, when inputs A= B= 1.
Inputs Outputs
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
3-to-8 line decoder
0 a, b, c, d, e, f
1 b, c
2 a, b, d, e, g
3 a, b, c, d, g
4 b, c, f, g
5 a, c, d, f, g
6 a, c, d, e, f, g
7 a, b, c
8 a, b, c, d, e, f, g
9 a, b, c, d, f, g
Truth table:
Applications of decoders:
1. Decoders are used in counter system.
2. They are used in analog to digital converter.
3. Decoder outputs can be used to drive a display system.
ENCODERS:
An encoder is a digital circuit that performs the inverse operation of a decoder.
Hence, the opposite of the decoding process is called encoding. An encoder is a
combinational circuit that converts binary information from 2n input lines to a
maximum of ‗n‘ unique output lines.
The general structure of encoder circuit is –
It has 2n input lines, only one which 1 is active at any time and ‗n‘ output lines. It
encodes one of the active inputs to a coded binary output with ‗n‘ bits. In an encoder,
the number of outputs is less than the number of inputs.
Octal-to-Binary Encoder:
It has eight inputs (one for each of the octal digits) and the three outputs that
generate the corresponding binary number. It is assumed that only one input has a
value of 1 at any given time.
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
The encoder can be implemented with OR gates whose inputs are determined
directly from the truth table. Output z is equal to 1, when the input octal digit is 1 or 3
or 5 or 7. Output y is 1 for octal digits 2, 3, 6, or 7 and the output is 1 for digits 4, 5, 6 or
7. These conditions can be expressed by the following output Boolean
Octal-to-Binary Encoder
Another problem in the octal-to-binary encoder is that an output with all 0‘s is
generated when all the inputs are 0; this output is same as when D0 is equal to 1. The
discrepancy can be resolved by providing one more output to indicate that atleast one
input is equal to 1.
Priority Encoder:
A priority encoder is an encoder circuit that includes the priority function. In
priority encoder, if two or more inputs are equal to 1 at the same time, the input having
the highest priority will take precedence.
In addition to the two outputs x and y, the circuit has a third output, V (valid bit
indicator). It is set to 1 when one or more inputs are equal to 1. If all inputs are 0, there
is no valid input and V is equal to 0.
The higher the subscript number, higher the priority of the input. Input D3, has
the highest priority. So, regardless of the values of the other inputs, when D 3 is 1, the
output for xy is 11.
D2 has the next priority level. The output is 10, if D2= 1 provided D3= 0. The
output for D1 is generated only if higher priority inputs are 0, and so on down the
priority levels.
Truth table:
Inputs Outputs
D0 D1 D2 D3 x y V
0 0 0 0 x x 0
1 0 0 0 0 0 1
x 1 0 0 0 1 1
x x 1 0 1 0 1
x x x 1 1 1 1
Although the above table has only five rows, when each don‘t care condition is
replaced first by 0 and then by 1, we obtain all 16 possible input combinations. For
example, the third row in the table with X100 represents minterms 0100 and 1100. The
don‘t care condition is replaced by 0 and 1 as shown in the table below.
Inputs Outputs
D0 D1 D2 D3 x y V
0 0 0 0 x x 0
1 0 0 0 0 0 1
0 1 0 0
0 1 1
1 1 0 0
0 0 1 0
0 1 1 0
1 0 1
1 0 1 0
1 1 1 0
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
K-map Simplification:
A multiplexer or MUX, is a combinational circuit with more than one input line,
one output line and more than one selection line. A multiplexer selects binary
information present from one of many input lines, depending upon the logic status of
the selection inputs, and routes it to the output line. Normally, there are 2 n input lines
and n selection lines whose bit combinations determine which input is selected. The
multiplexer is often labeled as MUX in block diagrams.
A multiplexer is also called a data selector, since it selects one of many inputs
and steers the binary information to the output line.
Logic diagram
The multiplexer acts like an electronic switch that selects one of the two sources.
Truth table:
S Y
0 I0
1 I1
4-to-1-line Multiplexer:
A 4-to-1-line multiplexer has four (2n) input lines, two (n) select lines and one
output line. It is the multiplexer consisting of four input channels and information of
one of the channels can be selected and transmitted to an output line according to the
select inputs combinations. Selection of one of the four input channel is possible by two
selection inputs.
Each of the four inputs I0 through I3, is applied to one input of AND gate.
Selection lines S1 and S0 are decoded to select a particular AND gate. The outputs of the
AND gate are applied to a single OR gate that provides the 1-line output.
4-to-1-Line Multiplexer
Function table:
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
To demonstrate the circuit operation, consider the case when S 1S0= 10. The AND
gate associated with input I2 has two of its inputs equal to 1 and the third input
connected to I2. The other three AND gates have atleast one input equal to 0, which
makes their outputs equal to 0. The OR output is now equal to the value of I 2, providing
a path from the selected input to the output.
The data output is equal to I0 only if S1= 0 and S0= 0; Y= I0S1‘S0‘.
The data output is equal to I1 only if S1= 0 and S0= 1; Y= I1S1‘S0.
The data output is equal to I2 only if S1= 1 and S0= 0; Y= I2S1S0‘.
The data output is equal to I3 only if S1= 1 and S0= 1; Y= I3S1S0.
When these terms are ORed, the total expression for the data output is,
Y= I0S1’S0’+ I1S1’S0 +I2S1S0’+ I3S1S0.
As in decoder, multiplexers may have an enable input to control the operation of
the unit. When the enable input is in the inactive state, the outputs are disabled, and
when it is in the active state, the circuit functions as a normal multiplexer.
Application:
The multiplexer is a very useful MSI function and has various ranges of
applications in data communication. Signal routing and data communication are the
important applications of a multiplexer. It is used for connecting two or more sources to
guide to a single destination among computer units and it is useful for constructing a
common bus system. One of the general properties of a multiplexer is that Boolean
functions can be implemented by this device.
Implementation table:
Apply variables A and B to the select lines. The procedures for implementing the
function are:
i. List the input of the multiplexer
ii. List under them all the minterms in two rows as shown below.
The first half of the minterms is associated with A‘ and the second half with A. The
given function is implemented by circling the minterms of the function and applying
the following rules to find the values for the inputs of the multiplexer.
1. If both the minterms in the column are not circled, apply 0 to the corresponding
input.
2. If both the minterms in the column are circled, apply 1 to the
corresponding input.
3. If the bottom minterm is circled and the top is not circled, apply C to the input.
4. If the top minterm is circled and the bottom is not circled, apply C‘ to the input.
Multiplexer Implementation:
2. F (x, y, z) = ∑m (1, 2, 6, 7)
Solution:
Implementation table:
Multiplexer Implementation:
3. F ( A, B, C) = ∑m (1, 2, 4, 5)
Solution:
Variables, n= 3 (A, B, C)
Select lines= n-1 = 2 (S1, S0)
2n-1 to MUX i.e., 22 to 1 = 4 to 1 MUX
Input lines= 2n-1 = 22 = 4 (D0, D1, D2, D3)
Implementation table:
Multiplexer Implementation:
Solution:
Variables, n= 4 (P, Q, R, S)
Select lines= n-1 = 3 (S2, S1, S0)
2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
Implementation table:
Multiplexer Implementation:
5. Implement the Boolean function using 8: 1 and also using 4:1 multiplexer
F (A, B, C, D) = ∑m (0, 1, 2, 4, 6, 9, 12, 14)
Solution:
Variables, n= 4 (A, B, C, D)
Select lines= n-1 = 3 (S2, S1, S0)
2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
Implementation table:
Multiplexer Implementation (Using 8: 1 MUX):
Using 4: 1 MUX:
Implementation table:
Multiplexer Implementation:
Implementation table:
Multiplexer Implementation:
Multiplexer Implementation:
9. Implement the Boolean function using 8: 1 and also using 4:1 multiplexer
F (w, x, y, z) = ∑m (1, 2, 3, 6, 7, 8, 11, 12, 14)
Solution:
Variables, n= 4 (w, x, y, z)
Select lines= n-1 = 3 (S2, S1, S0)
2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
Implementation table:
Implementation table:
Multiplexer Implementation:
12. An 8×1 multiplexer has inputs A, B and C connected to the selection inputs S2,
S1, and S0 respectively. The data inputs I0 to I7 are as follows
I1=I2=I7= 0; I3=I5= 1; I0=I4= D and I6= D'.
Determine the Boolean function that the multiplexer implements.
Multiplexer Implementation:
Implementation table:
DEMULTIPLEXER:
Demultiplex means one into many. Demultiplexing is the process of taking
information from one input and transmitting the same over one of several outputs.
A demultiplexer is a combinational logic circuit that receives information on a
single input and transmits the same information over one of several (2n) output lines.
Logic Symbol
The input variable Din has a path to all four outputs, but the input information
is directed to only one of the output lines. The truth table of the 1-to-4 demultiplexer is
shown below.
Enable S1 S0 Din Y0 Y1 Y2 Y3
0 x x x 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 1 1 0 0 0
1 0 1 0 0 0 0 0
1 0 1 1 0 1 0 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 0
1 1 1 0 0 0 0 0
1 1 1 1 0 0 0 1
From the truth table, it is clear that the data input, Din is connected to the
output Y0, when S1= 0 and S0= 0 and the data input is connected to output Y1 when S1=
0 and S0= 1. Similarly, the data input is connected to output Y2 and Y3 when S1= 1 and
S0= 0 and when S1= 1 and S0= 1, respectively. Also, from the truth table, the expression
for outputs can be written as follows,
Y0= S1’S0’Din
Y1= S1’S0Din
Y2= S1S0’Din
Y3= S1S0Din
1-to-8 Demultiplexer:
A 1-to-8 demultiplexer has a single input, Din, eight outputs (Y0 to Y7) and
three select inputs (S2, S1 and S0). It distributes one input line to eight output lines
based on the select inputs. The truth table of 1-to-8 demultiplexer is shown below.
Din S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 x x x 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
Truth table of 1-to-8 demultiplexer
From the above truth table, it is clear that the data input is connected with one of
the eight outputs based on the select inputs. Now from this truth table, the expression
for eight outputs can be written as follows:
Y0= S2‘S1‘S0‘Din Y4= S2 S1‘S0‘Din
Y1= S2‘S1‘S0Din Y5= S2 S1‘S0Din
Y2= S2‘S1S0‘Din Y6= S2 S1S0‘Din
Y3= S2‘S1S0Din Y7= S2S1S0Din
Now using the above expressions, the logic diagram of a 1-to-8 demultiplexer can be
drawn as shown below. Here, the single data line, Din is connected to all the eight AND
gates, but only one of the eight AND gates will be enabled by the select input lines. For
example, if S2S1S0= 000, then only AND gate-0 will be enabled and thereby the data
input, Din will appear at Y0. Similarly, the different combinations of the select inputs, the
input Din will appear at the respective output.
Logic diagram of 1-to-8 demultiplexer
1. Design 1:8 demultiplexer using two 1:4 DEMUX.
2. Implement full subtractor using demultiplexer.
Inputs Outputs
A B Bin Difference(D) Borrow(Bout)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1