Infineon IR35201MTRPBF DS v01 - 00 EN

8+0/7+1/6+2 Dual Output Digital Multi-Phase Controller IR35201
FEATURES DESCRIPTION
 Ultra Low Quiescent Power Dual output 8 phase The IR35201 is a dual-loop digital multi-phase
(8+0/7+1/ 6+2) PWM Controller buck controller designed for CPU voltage
®
 VR12 Rev 1.7, VR12.5 Rev 1.5, IMVP8 Rev 1.2, AMD regulation, and is fully compliant with Intel , VR12
2
SVI2, and Memory VR modes Rev 1.7, VR12.5 Rev 1.5, IMVP8 Rev 1.2, and
AMD SVI2 REV 1.06 specifications.
 Switching frequency from 194KHz to 2MHz per phase
in 56 steps The IR35201 includes IR’s Efficiency Shaping
 IR Efficiency Shaping Features including Dynamic Technology to deliver exceptional efficiency at
Phase Control and Automatic Power State Switching minimum cost across the entire load range. IR’s
Dynamic Phase Control adds/drops phases based
 Programmable 1-phase or 2-phase operation for Light
Loads and Active Diode Emulation for very Light upon load current. The IR35201 can be configured
Loads to enter 1 or 2-phase PS1 operation and active
diode emulation mode automatically or by
 IR Adaptive Transient Algorithm (ATA) on both loops command.
minimizes output bulk capacitors and system cost
 Auto-Phase Detection with PID Coefficient auto- IR’s unique Adaptive Transient Algorithm (ATA),
scaling based on proprietary non-linear digital PWM
algorithms, minimizes output bulk capacitors.
 Fault Protection: OVP, UVP, OCP, OTP, CAT_FLT
 I2C/SMBus/PMBus system interface for reporting of IR35201 has 127 possible address values for both
Temperature, Voltage, Current & Power telemetry for the PMBus and I2C bus interfaces. The device
both loops configuration can be easily defined using the IR
 Multiple Time Programming (MTP) with integrated PowIRCenter GUI, and is stored in the on-chip
charge pump for easy non-volatile programming Non-Volatile Memory (NVM). This reduces external
components and minimizes the package size.
 Compatible with 3.3V tri-state drivers

o o
+3.3V supply voltage; -40 C to 85 C ambient The IR35201 provides extensive OVP, UVP, OCP,
o o OTP & CAT_FLT fault protection, and includes
operation; -40 C to 125 C junction
thermistor based temperature sensing or per
 Pb-Free, RoHS, 7x7mm 56-pin, 0.4mm pitch QFN phase temperature reporting when using the IR
powIRstage. The controller is designed to work
APPLICATIONS with either Rdson current sense PowIRstages or
with DCR current sense.
 VR12, VR12.5 and IMVP8 (overclocking only), AMD
SVI2 based systems The IR35201 also includes numerous VR design
 Servers and High End Desktop CPU VRs simplifying and differentiating features, like register
 High Performance Graphics Processors, Memory VR diagnostics, which enable fast time-to-market.
ORDERING INFORMATION
Base Part Standard Pack Orderable
Package Type
Number Form Quantity Part Number
IR35201 56-pin, QFN 7 mm x 7 mm Tape and Reel 3000 IR35201MxxyyTRP1
IR35201 56-pin, QFN 7 mm x 7 mm Tape and Reel 3000 IR35201MTRPBF
IR35201 56-pin, QFN 7 mm x 7 mm Tray 4900 IR35201MTYPBF

Notes:
1. Customer Specific Configuration File, where xx = Customer ID and yy = Configuration File (Codes assigned by IR Marketing).
2. IR35201 is not intended for application where ultra low power PS4 shutdown functionality is required.
1 www.irf.com | © 2016 International Rectifier February 8, 2015 | V1.6

ORDERING INFORMATION
IR35201M         
P/PBF – Lead Free
TR – Tape & Reel / TY - Tray
yy – Configuration File ID
xx – Customer ID
Package Type (QFN)
Figure 1: IR35201 Pin Diagram

FUNCTIONAL BLOCK DIAGRAM
Figure 2: IR35201 Block Diagram

TYPICAL APPLICATION DIAGRAM
V
V
V
V
VV
Figure 3: VR using IR35201 Controller and IR3555 PowIR Stage in 6+2 Configuration

PIN DESCRIPTIONS
PIN# PIN NAME TYPE PIN DESCRIPTION
1 ISEN6 A [I] Phase 6 Current Sense Input. Phase 6 sensed current input (+).Short to GND if not used.
Resistor Current Sense Positive. This pin is connected to an external network to set the load
2 RCSP A [O]
line slope, bandwidth and temperature compensation for Loop 1.
Resistor Current Sense Minus. This pin is connected to an external network to set the load line
3 RCSM A [O]
slope, bandwidth and temperature compensation for Loop 1.
Voltage Regulator Ready Output (Loop #2). Open-drain output that asserts high when the VR
4 VRDY2 D [O] has completed soft-start to Loop #2 boot voltage. Pull-up to an external voltage through a
resistor.
Voltage Sense Input. This pin is connected directly to the VR output voltage of Loop #1 at the
5 VSEN A [I]
load and should be routed differentially with VRTN.
Voltage Sense Return Input. This pin is connected directly to Loop#1 ground at the load and
6 VRTN A [I]
should be routed differentially with VSEN.
7 NC Do Not Connect
I in. Input current signal that ranges from 0 to 1.25Vdc indicating a maximum input current of
8 I_IN A [I]
62.5 Amps.
Temperature Sense Input Loop 1. An NTC network or the temperature reporting output from an
IR PowIRstage can be connected to this pin to measure temperature for VRHOT and OTP
shutdown. When connected to the IR PowIRstage’s temperature output; the scaled input voltage
9 TSEN1 A [I]
to the controller needs to be at a gain of 4.88mV per degC and an offset of 0.365 Vdc so the
controller can correctly report temperature. Typically a 10kohm and 6.49kohm resistive divider is
used to accomplish the scaling between the power stage and the controller.
10 CFILT A [O] 1.8V Decoupling. A 1F capacitor on this pin provides decoupling for the internal 1.8V supply.
Voltage Regulator Ready Output (Loop #1). Open-drain output that asserts high when the VR
11 VRDY1 D [O] has completed soft-start to Loop #1 boot voltage. Pull-up to an external voltage through a
resistor.
Enable Input for Loop #2. This pin may be configured as an Enable input for loop #2.
EN_L2 D[I] Power OK Input (AMD). An input that when low indicates to return to the Boot voltage and when
12 PWROK D[I] high indicates to use the SVI bus.
CAT_FLT D[O]
Catastrophic Fault Output Pin. This pin may be used as a Catastrophic Fault CMOS Output Pin
that is driven to VCC under output OVP, NVM CRC errors or a TSEN fault input.
13 NC Do Not Connect
Voltage Sense Input. This is used to detect and measure a valid input supply voltage (typically
14 VINSEN A [I]
4.5V-13.2V) to the VR.
Serial VID Address. If present, a resistor to ground sets the offset to the SVID address set in
SV_ADDR A[I] NVM. If not, the value stored in NVM is used. Requires a 0.01µF to ground for noise filtering.
16
VDDIO A[P] VDDIO Input (AMD). This pin provides the voltage to which the SVT line and the SVD
Acknowledge are driven high.
Serial VID ALERT# (INTEL). SVID ALERT# is pulled low by the controller to alert the CPU of
SV_ALERT# new IMVP8/VR12/VR12.5 Status. Pull-up to an external voltage through a resistor.
17 D [O]
SVT
SVI Telemetry Output (AMD). Telemetry and VOTF information output by the IR35201
18 SV_CLK D [I] Serial VID Clock Input. Clock input driven by the CPU Master.
Serial VID Data I/O. Is a bi-directional serial line over which the CPU Master issues commands to
19 SV_DIO D [B]
slave/s and receives data back.
VRHOT_ICRIT# Output. Active low alert pin that can be programmed to assert if temperature or
20 VRHOT_ICRIT# D [O] average load current exceeds user-definable thresholds. Pull-up to an external voltage through a
resistor.


VR Enable Input. ENABLE is used to power-on the regulator, provided Vin and Vcc are present.
ENABLE is not pulled up in the controller. The polarity of the chip enable function is bit-settable to
21 EN D [I] either an active high or an active low configuration. When the controller is disabled, the controller
de-asserts VR READY and shuts down the regulator. ENABLE pin cannot be left
floating. ENABLE pin must be pulled high or low.
Bus Address & I2C Bus Protection. A resistor to ground on this pin sets the offset to the NVM
D [B]/ value of the I2C address if configured to do so. Subsequently, this pin becomes a logic input to
22 ADDR_PROT
enable or disable communication on the I2C bus when protection is enabled. Requires a 0.01µF
to ground for noise filtering.
SMBus/PMBus Alert Line. Active low alert pin to indicate that the regulator status has changed.
23 SM_ALERT# D [O]
Requires a pull-up. Ground if not used.
24 SM_DIO D [B] Serial Data Line I/O. I2C/SMBus/PMBus bi-directional serial data line. Ground if not used.
Serial Clock Line Input. I2C/SMBus/PMBus clock input. The interface is rated to 1 MHz. Ground
25 SM_CLK D [I]
if not used.
PIN_ALERT# Output. Active low alert pin that can be programmed to assert if the input power
26 PIN_ALERT# D [O]
exceeds user-defined threshold. Pull-up to an external voltage through a resistor.
Temperature Sense Input Loop #2. An NTC network or the temperature reporting output from
an IR PowIRstage can be connected to this pin to measure temperature for VRHOT. Float if not
TSEN2 A [O] used.
27
/VAUXSEN A [I]
Auxiliary Voltage Sense Input. Monitors an additional power supply to ensure that both the
IR35201 Vcc and other voltages (such as VCC to the driver) are operational. Float if not used.
Phase 1-6 Pulse Width Modulation Outputs. PWM signal pin which is connected to the input of
28 - 33 PWM1 – PWM6 A [O] an external MOSFET gate driver. The power-up state is high-impedance until ENABLE goes
active. Float if not used.
Phase 7 Pulse Width Modulation Outputs. PWM signal pin which is connected to the input of
an external MOSFET gate driver. The power-up state is high-impedance until ENABLE goes
PWM7/ active. Float if not used.
34 A [O]
PWM2_L2
Loop 2 Phase 2 Pulse Width Modulation Outputs. PWM signal pin which is connected to the input of
an external MOSFET gate driver. The power-up state is high-impedance until ENABLE goes active.
Phase 8 Pulse Width Modulation Outputs. PWM signal pin which is connected to the input of
an external MOSFET gate driver. The power-up state is high-impedance until ENABLE goes
PWM8/ active. Float if not used.
35 A [O]
PWM1_L2
Loop 2 Phase 1 Pulse Width Modulation Outputs. PWM signal pin which is connected to the input of
an external MOSFET gate driver. The power-up state is high-impedance until ENABLE goes active.
Voltage Sense Return Input Loop#2. This pin is connected directly to Loop 2 ground at the load and
36 VRTN_L2 A [I]
should be routed differentially with VSEN_L2. Short to GND if not used
Voltage Sense Input Loop#2. This pin is connected directly to the VR output voltage of Loop 2 at the
37 VSEN_L2 A [I]
load and should be routed differentially with VRTN_L2. Short to GND if not used
38 VCC A [P] Input Supply Voltage. 3.3V supply to power the device.
Resistor Current Sense Minus Loop#2. This pin is connected to an external network to set the load
39 RCSM_L2 A [I] line slope, bandwidth and temperature compensation for Loop 2. Connect to RCSP_L2 with 10K resistor
if not used
Resistor Current Sense Positive Loop#2. This pin is connected to an external network to set the load
40 RCSP_L2 A [I]
line slope, bandwidth and temperature compensation for Loop 2.
Loop 2 Phase 1 Current Sense Input. Loop 2 Phase 1 sensed current input (+).Short to GND if not
ISEN 1_L2/ used.
42 A [I]
ISEN8
Phase 8 Current Sense Input. Phase 8 sensed current input (+).Short to GND if not used.
Loop 2 Phase 1 Current Sense Return Input. Loop 2 Phase 1 sensed current input return (-).Short to
IRTN 1_L2/ GND if not used.
43 A [I]
IRTN8 Phase 8 Current Sense Return Input. Phase 8 sensed current input return (-).Short to GND if
not used.

Loop 2 Phase 2 Current Sense Input. Loop 2 Phase 2 sensed current input (+).Short to GND if not
ISEN 2_L2/ used.
44 A [I]
ISEN7
Phase 7 Current Sense Input. Phase 7 sensed current input (+).Short to GND if not used.
Loop 2 Phase 2 Current Sense Return Input. Loop 2 Phase 2 sensed current input return (-).Short to
IRTN 2_L2/ GND if not used.
45 A [I]
IRTN7 Phase 7 Current Sense Return Input. Phase 7 sensed current input return (-).Short to GND if
not used.
46 ISEN 5 A [I] Phase 5 Current Sense Input. Phase 5 sensed current input (+).Short to GND if not used.
Phase 5 Current Sense Return Input. Phase 5 sensed current input return (-). Short to GND if
47 IRTN 5 A [I]
not used..
48 ISEN 4 A [I] Phase 4 Current Sense Input. Phase 4 sensed current input (+).Short to GND if not used..
Phase 4 Current Sense Return Input. Phase 4 sensed current input return (-).Short to GND if
49 IRTN 4 A [I]
not used.
51 IRTN 3 A [I]
not used..
53 IRTN 2 A [I]
not used.
55 IRTN 1 A [I]
not used.
56 IRTN6 A [I]
not used..
57 Ground. Ground reference for the IC. The large metal pad on the bottom must be connected to
GND Ground.
(PAD)
Note 1: A - Analog; D – Digital; [I] – Input; [O] – Output; [B] – Bi-directional; [P] - Power

ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) GND-0.3V to 4.0V
RCSPx, RCSMx 0 to 2.2V
VSEN, VRTN, ISENx, IRTNx GND-0.2V to VCC + 0.3V
CFILT, VINSEN, I_IN GND-0.2V to 2.2V
TSENx GND-0.3V to VCC
SV_CLK, SV_DIO, SV_ALERT#, SV_ADDR GND-0.3V to VCC
VRDYx, ENx, ADDR_PROT, VRHOT_ICRIT#, PIN_ALERT# GND-0.3V to VCC
PWMx, GND-0.3V to 4.1V
SM_DIO, SM_CLK, SM_ALERT# GND-0.3V to 5.5V
ESD Rating
Human Body Model 2000V
Machine Model 200V
Charge Device Model 1000V
Thermal Information
1
Thermal Resistance (θJA & θJC) 29°C/W & 3°C/W
Maximum Operating Junction Temperature -40°C to +125°C
Maximum Storage Temperature Range -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) 300°C
Note: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications are not implied.

ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
Recommended Operating Ambient Temperature Range -40°C to 85°C

Supply Voltage Range +2.90V to +3.63V
The electrical characteristics table lists the spread of values guaranteed within the recommended operating
conditions. Typical values represent the median values, which are related to 25°C.
ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

Supply VCC/GND
Supply Voltage Vcc 2.90 3.3 3.63 V
Supply Current Ivcc No PWM switching - 48 - mA
3.3V UVLO Turn-on Threshold - 2.80 2.90 V
3.3V UVLO Turn-off Threshold 2.60 2.70 - V
Input Voltage (4.5V-13.2V) Sense Input VINSEN
Input Impedance 1 - - MΩ
Input Range V12 With 14:1 divider 0 0.857 1.1 V
UVLO Turn-on Programmable Range1 With 14:1 divider - 4.5 –13.2 - V
1
UVLO Turn-off Programmable Range With 14:1 divider - 4.5 –13.2 - V
1
OVP Threshold (if enabled) 14.3 14.6 14.9 V
AUX Voltage Sense Input VAUXSEN
Input Impedance1 - 1 - MΩ
1
UVLO Turn-on Threshold VAUXSEN_on 0.642 0.664 0.686 mV
1
UVLO Turn-off Threshold VAUXSEN_off 0.564 0.586 0.608 mV
Reference Voltage and DAC
VBoot Voltage Range Intel®, VR12.5,VR12and
IMVP8 mode, and AMD Meets spec V
SVI2
System Accuracy VID = 2.005–3.04V -1.1 - 1.1 %VID
(0 to 85°C ambient) VID = 1.0V–2.0V -0.5 - 0.5 %VID
VID = 0.8 – 0.995V -5 - 5 mV
VID = 0.25 –0.795V -8 - 8 mV
System Accuracy VID = 2.005–3.04V -1.65 - 1.65 %VID
(-40°C to 125°C junction) VID = 1.0V–2.0V -0.75 - 0.75 %VID
VID = 0.8 – 0.995V -7.5 - 7.5 mV
VID = 0.25 –0.795V -12 - 12 mV
Oscillator & PWM Generator
Internal Oscillator1 - 96 - MHz
Frequency Accuracy 0°C to 85°C -2.5 - 2.5 %
Frequency Accuracy -40°C to 125°C -5 +5 %
1
PWM Frequency Range 194 - 2000 kHz

1
PWM Resolution - 163 - ps
NTC Temperature Sense TSEN_NTC
Output Current For TSEN = 0 to 1.2V 96 100 104 µA
1
Accuracy at 100°C (ideal NTC) 96 - 104 °C
Tout Temperature Sense TSEN_IR3555
Input Voltage For TSEN = 0 to 1.2V - 4.88 - mV/°C
Offset Voltage - 0.365 - Vdc
Fault Threshold 1.45 Vdc
Divider Ratio to interface IR3555 to
- 1:1.64 -
IR35201
Digital Inputs – Low Vth Type 1 EN(_L2) (Intel), VRHOT_ICRIT# (during PoR),
Input High Voltage 0.7 - - V

Input Low Voltage - - 0.35 V
Input Leakage Current Vpad = 0 to 2V - - ±5 µA
Digital Inputs – Low Vth Type 2 SV_CLK, SV_DIO

Hysteresis - 95 - mV
Input Leakage Current Vpad = 0 to 2V - - ±1 µA
Digital Inputs – LVTTL SM_DIO, SM_CLK, EN(_L2), ADDR_PROT

Input Leakage Vpad = 0 to 3.6V - - ±1 µA
Remote Voltage Sense Inputs VSENx, VRTNx
VSEN Input Current -25 to
VCPU = 0.5V to 3.04V - - µA
+100
VRTN Input Current - -50 - µA
1
Differential Input Voltage Range VRTN = ±100mV - 0 to 3.04 - V
1
VRTN Input CM Voltage - -100 to - mV
100
Remote Current Sense Inputs ISENx/IRTNx
1
Voltage Range -0.1 to
- - V
VCC - 0.65
Input Current Sense Input I_IN
Voltage Range - 0 to 1.25 - V
Analog Address/Level Inputs ADDR_PROT,SV_ADDR,
1
Output Current Vpad = 0 to 1.2V 96 100 104 µA
CMOS Outputs ― 3.3V CAT_FLT
VCC –
Output High Voltage loh = -20mA 0.4 - - V
Output Low Voltage lol = 20mA - - 0.4 V
Open-Drain Outputs – 4mA Drive VRDY, SM_DIO, SM_ALERT#
Output Low Voltage 4mA - - 0.3 V

Output Leakage Vpad = 0 to 3.6V - - ±5 µA
Open-Drain Outputs – 20mA Drive VR_HOT_ICRIT#, SV_DIO, SV_ALERT#, PIN_ALERT#

1
Output Low Voltage I = 20mA - - 0.26 V
1
On Resistance I = 20mA 7 9 13 Ω
Tri-State Leakage Ileak Vpad = 0 to 3.6V - - ±5 µA
PWM I/O PWMx
Output Low Voltage (Tri-state mode) I = -4mA - - 0.4 V
Output High Voltage (Tri-State mode) I =+4mA 2.9 - - V
Tri-State Leakage loop_x_pwm_en_ats = 0,
- - ±1 µA
Vpad = 0 to Vcc
PWM Auto-Detect Inputs (when 3.3V Vcc is applied) – if enabled
Input Voltage High 0.7 - - V
Input Voltage Low - - 0.35 V
AMD SVI2 Bus
Tperiod (SVC Period)1 SVC 47.6 10,000 nSec
SVI2 SVC Frequency1 SVC 0.1 20.0 21.0 MHz
I2C/PMBus & Reporting
Bus Speed1 Normal - 100 - kHz
Fast - 400 - kHz
Maximum - 1000 - kHz
Iout , Vout , Iin, Vin, Pin and Temperature Selectable 0.69, 1.39,
Filter Rate1 2.78, 5.55,
(Selected Frequency applies - - Hz
11.1, 22.2,
to all parameters) 44.6, 89.5
Iout Update Rate1 - 250 - kHz
Vout Update Rate1 - 35.7 - kHz
Vin & Temperature Update Rate1 - 35.7 - kHz
1
Vin Range Reporting With 14:1 divider - 0 to 13.2 - V
Vin Accuracy Reporting With 1% resistors -2 - +2 %
Vin Resolution Reporting -PMBUS1 - 31.25 - mV
1
Vin Resolution Reporting –I2C - 125 - mV
1
Vout Range Reporting - - 4 V
1
Vout Accuracy Reporting No load-line ±0.5 %
Vout Resolution Reporting-PMBUS1 Vout < 2V - 1.95 - mV
Vout Resolution Reporting-I2C1 Vout < 4V - 15.6 - mV
1
Iout Per Phase Range Reporting 0 - 62 A
Iout Accuracy Reporting1 Maximum load, all phase
active (based on DCR, - ±2 - %
NTC and # active phases)
1
Loop1 Iout Resolution Reporting-PMBUS *0.5A if >255.75A - 0.25* - A
1
Loop2 Iout Resolution Reporting-PMBUS - 0.25 - A
1
Loop1 Iout Resolution Reporting-I2C - 1 - A
Loop2 Iout Resolution Reporting-I2C 1 - 0.5 - A
1
Loop1 Iin Resolution Reporting-PMBUS - 31.25 - mA

1
Loop2 Iin Resolution Reporting-PMBUS - 31.25 - mA
Loop1 Iin Resolution Reporting-I2C1 - 0.125 - A
Loop2 Iin Resolution Reporting-I2C1 - 0.0625 - A
1
P_in Resolution Reporting-PMBUS - 0.5 - W
1
P_out Resolution Reporting-PMBUS - 0.5 - W
Temperature Range Reporting1 IR3555 mode 0 - 158 °C
Temperature Accuracy Reporting1 IR3555 mode 3.5 - 3.5 %
1
Temperature Range Reporting 0 - 134 °C
1
Temperature Accuracy Reporting At 100°C, with ideal NTC -4 - 4 %
Temperature Resolution Reporting1 - 1 - °C
Fault Protection
OVP Threshold During Start-up 1.2, 1.275,
Selectable - - V
(until output reaches 1V) 1.35, 2.5
1
OVP Operating Threshold (programmable) Relative to VID - 50 to 400 - mV
1
OVP Filter Delay - 160 - ns
Output UVP Threshold1 (programmable) Relative to VID - 50 to 400 - mV
Fast OCP Range (per phase)1 - 0 to 62 - A
1
Fast OCP Filter Bandwidth - 60 - kHz
Slow OCP Filter Bandwidth1 0.69, 1.39,
2.78, 5.55,
Selectable - - Hz
11.1, 22.2,
44.6, 89.5
OCP System Accuracy1 System excluding DCR/sense
- ±2 - %
resistor
PIN_ALERT# Bandwidth 2000 Hz
1
VR_HOT Range - 64 to 127 - °C
1, 2
OTP Range OTP Range (added to
- 0 to 31 - °C
VR_HOT level)
Dynamic Phase Control
Current Filter Bandwidth1 For Phase drop - 4 - kHz
Timing Information
Automatic Configuration from MTP1 3.3V ready to end of
t3-t2 - 0.4 ms
configuration
Automatic Trim Time1 t4-t3 - 2 ms
1
EN Delay (to ramp start) - 3 - µs
VID Delay (to ramp start) 1 Loop bandwidth dependent - 5 - µs
1
VRDY Delay After reaching Boot voltage - 20 - µs
Notes:
1
Guaranteed by design.
2
OTP max setting with NTC TEMP SENSE is 134°C.

GENERAL DESCRIPTION ADAPTIVE TRANSIENT ALGORITHM (ATA)
Dynamic load step-up and load step-down transients
require fast system response to maintain the output
The IR35201 is a flexible, dual-loop, digital multiphase voltage within specification limits. This is achieved by
PWM buck controller optimized to convert a 12V input a unique adaptive non-linear digital transient control
supply to the core voltage required by Intel high loop based on a proprietary algorithm.
performance microprocessors and DDR memory. It is
easily configurable for 1 to 8 phases of operation on
Loop #1 and 0 to 2 phase operation on Loop #2.
MULTIPLE TIME PROGRAMMING MEMORY
However, at a single time, a total of only 8 phases can The multiple time programming memory (MTP) stores
be in operation. the device configuration. At power-up, MTP contents
are transferred to operating registers for access
The unique partitioning of analog and digital circuits during device operation. MTP allows customization
within the IR35201 provides the user with easy during both design and high-volume manufacturing.
configuration capability while maintaining the required MTP integrity is verified by Cyclic Redundancy Code
accuracy and performance. Access to on-chip Multiple (CRC) checking on each power up. The controller will
Time Programming memory (MTP) to store the not start up in the event of a CRC error.
IR35201 configuration parameters enables power
supply designers to optimize their designs without The IR35201 offers up to 6 writes to configure basic
changing external components. device parameters such as frequency, fault operation
characteristics, and boot voltage. This represents a
OPERATING MODES significant size and component saving compared to
®
traditional analog methods. The following pseudo-
The IR35201 can be used for Intel VR12, VR12.5, code illustrates how to write the MTP:
IMVP8 designs, AMD SVI2, and DDR Memory
# write data
designs without significant changes to the external Set MTP Command Register = WRITE,
components (Bill of Materials). The required mode is Line Pointer = An unused line
selected in MTP and the pin-out, VID table and Poll MTP Command Register until Operation = IDLE.
relevant functions are automatically configured. This # verify data was written correctly
Issue a READ Command; then poll OTP Operation Register
greatly reduces time-to-market and eliminates the till Operation = IDLE
need to manage and inventory different PWM Verify that the Read Succeeded
controllers.
INTERNAL OSCILLATOR
DIGITAL CONTROLLER & PWM
The IR35201 has a single 96MHz internal oscillator
A linear Proportional-Integral-Derivative (PID) that generates all the internal system clock
digital controller provides the loop compensation for frequencies required for proper device function. The
system regulation. The digitized error voltage from oscillator frequency is factory trimmed for precision,
the high-speed voltage error ADC is processed by the and has extremely low jitter (Figure 4) even in light-
digital compensator. The digital PWM generator uses load mode (Figure 5). A single internal oscillator is
the outputs of the PID and the phase current balance used to set the switching frequency on each loop
control signals to determine the pulse width for independently.
each phase on each loop. The PWM generator has
enough resolution to ensure that there are no limit
cycles. The compensator coefficients are user
configurable to enable optimized system response.
The compensation algorithm uses a PID with two
additional programmable poles. This provides the
digital equivalent of a Type III analog compensator.

Vdd
Lossless inductor DCR or precision resistor current
VCORE sensing is used to accurately measure individual
phase currents. Using a simple off-chip thermistor,
resistor and capacitor network for each loop, a
thermally compensated load line is generated to meet
PWM3 the given power system requirement. A filtered
voltage, which is a function of the total load current
PWM2 and the target load line resistance, is summed into
each voltage sense path to accomplish the Active
PWM1
Voltage Positioning (AVP) function.
The IR35201 can also be used with Rdson current

sensing PowIRstages. This algorithm helps reduce
Figure 4: Persistence plot of a 3Φ, 50A system component by eliminating the need for the R-C sense
components. Also, the thermistor used for thermal
compensation would no longer be required, as this
VCORE function is inherently designed into the Rdson sensing
PowIRstages. The R-C network across the pins would
still be required.
VID DECODER
The VID decoder receives a VID code from the CPU

that is converted to an internal code representing the
VID voltage. This block also outputs the signal for VR
PWM1
disable if a VID shutdown code has been received.
®
The 8 bit VID code supports Intel VR12 & VR12.5
modes and VID settings are selectable as either
Figure 5: Persistence plot in 1Φ, 10A 5mV/code or 10mV/code on each loop independently.
When AMD SVI2 mode is choosen, both loops will be
HIGH-PRECISION VOLTAGE REFERENCE set to 6.25mV/code
The internal high-precision voltage reference supplies

MOSFET DRIVER, POWER STAGE AND
the required reference voltages to the VID DACs,
ADCs and other analog circuits. This factory trimmed DRMOS COMPATIBILITY
reference is guaranteed over temperature and The PWM output signals of the IR35201 are designed
manufacturing variations. for compatibility with industry standard +3.3V Tri-State
MOSFET drivers
VOLTAGE SENSE
An error voltage is generated from the difference I2C & PMBUS INTERFACE
between the target voltage, defined by the VID and An I2C or PMBus interface is used to communicate
load line (if implemented), and the differential, with the IR35201. This two-wire serial interface
remotely sensed, output voltage. For each loop, the consists of clock and data signals, and operates as
error voltage is digitized by a high-speed, high- fast as 1MHz. The bus provides read and write access
precision ADC. An anti-alias filter provides the to the internal registers for configuration, and for
necessary high frequency noise rejection. monitoring of operating parameters. The bus is also
The gain and offset of the voltage sense circuitry for used to program on-chip non-volatile memory (MTP)
each loop is factory trimmed to deliver the required to store operating parameters.
accuracy.
To ensure operation with multiple devices on the bus,
CURRENT SENSE an exclusive address for the IR35201 is programmed

into MTP. The IR35201, additionally, supports pin- The configuration file can be re-coded into an
programming of the address. I2C/PMBus master (e.g. a Test System) and loaded
into the IR35201 using the bus protocols described on
To protect customer configuration and information, page 48.
the I2C interface can be configured for either limited
access with a 16-bit software password, or completely REAL-TIME MONITORING
locked. Limited access includes both write and read
protection options. In addition, there is a telemetry- The IR35201 can be accessed through the use of
only mode which only allows reads from the telemetry PMBus Command codes (described in Table 56), to
registers. read the real time status of the VR system including
input voltage, output voltage, input and output current,
The IR35201 provides a hardware pin security option input and output power, efficiency, and temperature.
to provide extra protection. The protect pin is shared
with the ADDR pin and is automatically engaged once
the address is read. The pin must be driven high to
disable protection. The pin can be enabled or disabled
by a configuration setting in MTP.
The IR35201 supports the Packet Error Checking

(PEC) protocol and a number of PMBus commands to
monitor voltages and currents. For more information,
refer to the PMBus Command Codes in Table 56.
IR POWIRCENTER GUI
The IR PowIRCenter GUI provides the designer with a
comprehensive design environment that includes
interactive tools to calculate VR efficiency and DC
error budget, design the thermal compensation and
feedback loop networks, and produce calculated Bode
plots and output impedance plots. The PowIRCenter
GUI environment is a key utility for design
optimization, debug, and validation of designs that
saves the designer significant time, allowing faster
time-to-market (TTM).
The PowIRCenter GUI allows real-time design

optimization and monitoring of key parameters such
as output current and power, input current and power,
efficiency, phase currents, temperature, and faults.
The IR PowIRCenter GUI also allows access to the

system configuration settings for switching frequency,
MOSFET driver compatibility, soft start rate, VID table,
PSI, loop compensation, transient control system
parameters, input under-voltage, output over-voltage,
output under-voltage, output over-current and over-
temperature.
PROGRAMMING
Once a design is complete, the PowIRcenter
produces a complete configuration file.

THEORY OF OPERATION
OPERATING MODE
The IR35201 changes its functionality based on the
user-selected operating mode, allowing one device to
be used for multiple applications without significant
BoM changes. This greatly reduces the user’s design
cycles and Time-to-Market (TTM).
The functionality for each operating mode is

completely configurable by simple selections in MTP.
The mode configuration is shown in Table 1.
TABLE 1: MODE SELECTION

Figure 6: Controller Startup and Initialization
Mode Description
VR12 Intel® VR12 (Selected via MTP). Once the registers are loaded from MTP, the designer
VR12.5 Intel® VR12.5 (Selected via MTP).
can use I2C to re-configure the registers to suit the
specific VR design requirements if desired.
IMVP8 Intel® IMVP8 (Selected via MTP).
SVI2 AMD SVI2 (Selected via MTP).
TEST MODE
Memory Mode, with Loop 2 output voltage = ½
MPoL
Loop 1 output voltage.
Having the ADDR_PROT pin high as the IC goes
through 3.3V POR engages a special test mode in
which the I2C address changes to 0Ah. This allows
DEVICE POWER-ON AND INITIALIZATION individual in-circuit programming of the controller. This
The IR35201 is powered from a 3.3V DC supply. is specifically useful in multi-controller systems that
Figure 6 shows the timing diagram during device use a single I2C bus. Note that MTP will not load to
initialization. An internal LDO generates a 1.8V rail to the working registers until the ADDR_PROT pin goes
power the control logic within the device. During initial low.
startup, the 1.8V rail follows the rising 3.3V supply
voltage, proportional to an internal resistor tree. The SUPPLY VOLTAGE
internal oscillator becomes active at t1 as the 1.8V rail
is ramping up. Until soft-start begins, the IR35201 The controller is powered by the 3.3V supply rail.
PWM outputs are disabled in a high impedance state Once initialization of the device is complete, steady
to ensure that the system comes up in a known state. and stable supply voltage rails and a VR Enable
signal (EN) are required to change the controller into
The controller comes out of power-on reset (POR) at an active state. The Enable signal is used to enable
t2 when the 3.3V supply is high enough for the internal the PWM signals and begin the soft start sequence
bias control to generate 1.8V. The contents of the after the 3.3V and VIN supply rails are determined to
MTP are transferred to the registers by time t3 and the be within the defined operating bands. The polarity of
automatic trim routines are complete by time t4. At this the chip enable function is bit-settable to either an
time, if enabled in MTP and when the VINSEN voltage active high or an active low configuration. When the
is valid, the controller will detect the populated phases controller is disabled by deactivating the Enable
by sensing the voltage on the PWM pins. If the signal, it de-asserts VR READY and shuts down the
voltage is less than the Auto Phase Detect threshold regulator.
(unused PWMs are grounded), the controller assumes
the phase is unpopulated. The register settings and The recommended decoupling for the 3.3V is shown
number of phases define the controller performance in Figure 7. The Vcc pin should have a 0.1µF and
specific to the VR configuration, including trim 1µF X5R-type ceramic capacitors placed as close as
settings, soft start ramp rate and boot voltage. possible to the package.

Figure 7: Vcc 3.3V decoupling
The CFILT pin must have a 1µF, X5R type decoupling

capacitor connected close to the package as shown in Figure 9: VINSEN resistor divider network
Figure 8.
If enabled, VAUXSEN can be used to sense an
auxiliary voltage like a 5V driver VCC, for
example. The on and off thresholds are adjusted by
selecting the correct divider network, R1 and R2.
Figure 8: CFILT decoupling
The IR35201 is designed to accommodate a wide

variety of input power supplies and applications and
offers programmability of the VINSEN turn-on/off
voltages, Figure 10: VAUXSEN resistor divider network
VAUX on and off thresholds are defined as:
TABLE 2: VINSEN TURN-ON/OFF VOLTAGE RANGE VAUX_on = VAUXSEN_on*(1+R1/R2)

VAUX_off = VAUXSEN_off*(1+R1/R2)
Threshold Range
Turn-on 4.5V to 13.1875V in 1/16V steps
1
With R2 set to 1KΩ, Table 3 shows the on and off
1 thresholds for various values of R1.
Turn-off 4.5V to 13.1875V in 1/16V steps
1
Must not be programmed below 4.5V
TABLE 3: VAUXSEN TURN-ON/OFF VOLTAGES
R1 VAUX_on VAUX_off
The supply voltage on the VINSEN pin is compared KΩ Volt Volt
against a programmable threshold. Once the rising 5.77 4.50 3.97
VINSEN voltage crosses the turn-on threshold and EN 8.78 6.50 5.74
is asserted, all PWM outputs become active. The 11.80 8.50 7.50
VINSEN supply voltage is valid until it declines below 14.81 10.50 9.27
its programmed turn-off level.
A 14:1 attenuation network is connected to the Telemetry for VAUX is provided with 8 bit read only
VINSEN pin as shown in Figure 9. Recommended register, vaux_supply. VAUX_reported can be
values for a 12V system are RVIN_1 = 13kΩ and RVIN_2 calculated with the following formula:
= 1kΩ, with a 1% tolerance or better. CVINSEN is
VAUX_reported = vaux_supply(dec)*4.883E-
required to have a minimum 1nF for noise
3*(1+R1/R2)
suppression, with a maximum value of 10nF.

POWER-ON SEQUENCING INTEL MODE
The VR power-on sequence is initiated when all of the When the power-on sequence is initiated, and with
following conditions are satisfied: VBOOT set to > 0V, the output voltage will ramp to its
configured boot voltage and assert VRDY. The slew
 IR35201 Vcc (+3.3V rail) > VCC UVLO rate to VBOOT is programmed per Table 21.
 Input Voltage (VINSEN rail) > Vin UVLO
If Vboot = 0V, the VR will stay at 0V and will not soft-
 Aux Voltage (VAUXSEN rail) > VAUXSEN
start until the CPU issues a VID command to the loop.
UVLO
(if configured)ENABLE is HIGH In VR 13 mode, as soon as the IC is ready for SVID
communication, VR_READY will be asserted with
 VR has no Over-current, Over-voltage, Over- Vboot = 0V.
temperature or Under-voltage faults
 MTP transfer to configuration registers Intel Boot Voltage
occurred without parity error
The IR35201 Vboot voltage is fully programmable in
Once the above conditions are cleared, start-up MTP to the range specified in the Intel VID tables.
behavior is controlled by the operating mode. Table 14 and Table 15 show the Intel VID tables for
for 5mV and 10mV VID steps respectively.
TABLE 8: VBOOT RANGE
Loop Boot Voltage

VCORE Per Intel VR12 and VR12.5 VID
Loop 1
table
Per Intel VR12 and VR12.5 VID
VRRDY Loop 2
table
ENABLE
Intel SVID Interface
®
The IR35201 implements a fully compliant Intel VR12
Figure 11: Enable-based Startup & VR12.5 Serial VID (SVID) interface. This is a three-
®
wire interface between an Intel VR12 ,VR12.5 &
POWER-OFF SEQUENCING IMVP8 compliant processor and a VR that consists of
clock, data and alert# signals.
When +12Vdc goes below controller turn-off
threshold, the controller tristates all PWM’s. When The IR35201 architecture is based upon a digital core
enable goes low the controller ramps down Vout on and hence lends itself very well to digital
both loops as shown in Figure12. communications. As such, the IR35201 implements all
the required SVID registers and commands. The
IR35201 also implements many of the optional
VCORE
commands and registers with very few exceptions.
The Intel CPU is able to detect and recognize the
extra functionality that the IR35201 provides and thus
®
gives the Intel VR 13/12/12.5/IMVP8 CPU
unparalleled ability to monitor and optimize its power.
The SVID address of the IR35201 defaults to 0. This

VRRDY address may be re-programmed in MTP. An address
lock function prevents accidental overwrites of the
ENABLE address.
Figure 12: Enable-based Shutdown

The pseudo-code below illustrates the MTP address VR12.5 Operation
programming:
VR12.5 mode is selectable via MTP bit. The boot
# unlock the address register to write, then lock voltage in VR12.5 is also selectable and can be taken
Set Address_lock_bit=0 from the boot registers.
Write new SVID address
Set Address_lock_bit=1 IMVP8 Operation
IMVP8 mode is selectable via MTP bit. The boot

Intel VID Offset voltage in IMVP8 mode is configured in the boot
The output voltage can be offset instead of setting a register in 5mV steps compatible to VR12 mode VID
manual VID value, according to Table 9. This is table i.e. Table 14 or in 10mV steps compatible to
especially useful for memory applications where VR12.5 mode VID table i.e. Table 15. In IMVP8 mode,
voltages higher than the standard VID table may be bit 3 of SVID register “Status 1” (10h) is defined as
“VID DAC high”. This bit when set is an indicator to
required.
the CPU that the VR VID DAC is greater than 30mV
above a new VID recently set by an SetVID
TABLE 9: VID OFFSET command.
Parameter Memory Range Step Size In IMVP8 mode, IR35201 does support PS4
command, however, it does not shut down the
Output -128 to circuitry to reduce quiescent power consumption to
R/W 1 VID code
Voltage +127 <1mW. Thus, IR35201 is meant to be operated in
IMVP8 mode for overclocking applications only where
Maximum allowed voltage is 3.04V (VR12.5) it is not expected for VR to shut down its circuitry to
reduce quiescent power consumption.
Note that the Vmax register must be set appropriately
to allow the required output voltage offset.
Intel Reporting Offsets Loop Start-Up Sequence and Delay

IR35201 can be configured to enable both loops in
In addition to the mandatory features of the SVID bus, one of the following possible sequences:
the IR35201 provides optional volatile SVID registers
which allow the user to offset the reporting on the  Both loops start together.
SVID interface as detailed in Table 10.  Loop 2 follows Loop 1.
 Loop1 follows Loop 2.
TABLE 10: SVID OFFSET REGISTERS
If IR35201 is configured such that one loop follows the
Parameter Memory Range Step size other, the delay between the two loops can be
adjusted for following pre-defined intervals:
Output Current NVM -4A to +3.75A 0.25A  0 mS, 0.25 mS, 0.5 mS, 1 mS, 2.5 mS, 5 mS,
10 mS.
Temperature R/W -32°C to +31°C 1°C Memory (MPoL) Mode
In MPoL mode the IR35201 configures Loop 2 VID to
All Call SUPPORT 50% of Loop 1. Communication with and control of the
All Call for each loop of IR35201 can be configured in IR35201 may occur either through the SVID interface
following ways: when an Intel SVID Master is present, or alternatively
through the I2C/SMBus/PMBus interface for non-Intel
 0E and 0F. applications.
 0E only.
The IR35201 follows startup and timing requirements
 0F only. as shown in Figure 13. When the power-on sequence
is initiated, and with VBOOT set to > 0V, both rails will
 No All Call ramp to their configured voltages and assert
VR_READY_L1 and VR_READY_L2. The slew rates
IR35201 can be configured to be used as VR for CPU for both loops are set independently per Table 21. If
which is All Call 0F or Memory which is All Call 0E. tracking is required during the slew, then care must be

taken to ensure that the Loop 2 slew rate is set to ½ of
the Loop 1 slew rate. Typical MPoL start-up and shut-
down waveforms are shown in Figure 14 and Figure Vout 1
15.
Vout 2
Figure 13: MPoL Startup

Figure 15: MPoL Tracking Shutdown
TABLE 12: MPOL START-UP TIMING
In MPoL mode, Loop 2 start-up can be delayed
Time Description Min Typ Max relative to Loop 1 according to 2.
TA VR_EN to Loop 1 start 3µs
TB Loop 2 delay Table TABLE 13: MPOL LOOP 2 START-UP DELAY
Voltage ramp complete Loop 2 Delay
TC 1µs
to VR_RDY_L1/L2
0 – 678.3usec in 2.66usec Steps
Vout 1
Vout 2
Figure 14: MPoL Tracking Startup

Table 14: Intel VR12 VID Table – 5mV VID Step
VID Voltage VID Voltage VID Voltage VID Voltage VID Voltage
(Hex) (V) (Hex) (V) (Hex) (V) (Hex) (V) (Hex) (V)
FF 1.52 DA 1.335 B5 1.15 90 0.965 6B 0.78
FE 1.515 D9 1.33 B4 1.145 8F 0.96 6A 0.775
FD 1.51 D8 1.325 B3 1.14 8E 0.955 69 0.77
FC 1.505 D7 1.32 B2 1.135 8D 0.95 68 0.765
FB 1.5 D6 1.315 B1 1.13 8C 0.945 67 0.76
FA 1.495 D5 1.31 B0 1.125 8B 0.94 66 0.755
F9 1.49 D4 1.305 AF 1.12 8A 0.935 65 0.75
F8 1.485 D3 1.3 AE 1.115 89 0.93 64 0.745
F7 1.48 D2 1.295 AD 1.11 88 0.925 63 0.74
F6 1.475 D1 1.29 AC 1.105 87 0.92 62 0.735
F5 1.47 D0 1.285 AB 1.1 86 0.915 61 0.73
F4 1.465 CF 1.28 AA 1.095 85 0.91 60 0.725
F3 1.46 CE 1.275 A9 1.09 84 0.905 5F 0.72
F2 1.455 CD 1.27 A8 1.085 83 0.9 5E 0.715
F1 1.45 CC 1.265 A7 1.08 82 0.895 5D 0.71
F0 1.445 CB 1.26 A6 1.075 81 0.89 5C 0.705
EF 1.44 CA 1.255 A5 1.07 80 0.885 5B 0.7
EE 1.435 C9 1.25 A4 1.065 7F 0.88 5A 0.695
ED 1.43 C8 1.245 A3 1.06 7E 0.875 59 0.69
EC 1.425 C7 1.24 A2 1.055 7D 0.87 58 0.685
EB 1.42 C6 1.235 A1 1.05 7C 0.865 57 0.68
EA 1.415 C5 1.23 A0 1.045 7B 0.86 56 0.675
E9 1.41 C4 1.225 9F 1.04 7A 0.855 55 0.67
E8 1.405 C3 1.22 9E 1.035 79 0.85 54 0.665
E7 1.4 C2 1.215 9D 1.03 78 0.845 53 0.66
E6 1.395 C1 1.21 9C 1.025 77 0.84 52 0.655
E5 1.39 C0 1.205 9B 1.02 76 0.835 51 0.65
E4 1.385 BF 1.2 9A 1.015 75 0.83 50 0.645
E3 1.38 BE 1.195 99 1.01 74 0.825 4F 0.64
E2 1.375 BD 1.19 98 1.005 73 0.82 4E 0.635
E1 1.37 BC 1.185 97 1 72 0.815 4D 0.63
E0 1.365 BB 1.18 96 0.995 71 0.81 4C 0.625
DF 1.36 BA 1.175 95 0.99 70 0.805 4B 0.62
DE 1.355 B9 1.17 94 0.985 6F 0.8 4A 0.615
DD 1.35 B8 1.165 93 0.98 6E 0.795 49 0.61
DC 1.345 B7 1.16 92 0.975 6D 0.79 48 0.605
DB 1.34 B6 1.155 91 0.97 6C 0.785 47 0.6

46 0.595 37 0.52 28 0.445 19 0.37 0A 0.295
45 0.59 36 0.515 27 0.44 18 0.365 09 0.29
44 0.585 35 0.51 26 0.435 17 0.36 08 0.285
43 0.58 34 0.505 25 0.43 16 0.355 07 0.28
42 0.575 33 0.5 24 0.425 15 0.35 06 0.275
41 0.57 32 0.495 23 0.42 14 0.345 05 0.27
40 0.565 31 0.49 22 0.415 13 0.34 04 0.265
3F 0.56 30 0.485 21 0.41 12 0.335 03 0.26
3E 0.555 2F 0.48 20 0.405 11 0.33 02 0.255
3D 0.55 2E 0.475 1F 0.4 10 0.325 01 0.25
3C 0.545 2D 0.47 1E 0.395 0F 0.32 00 0
3B 0.54 2C 0.465 1D 0.39 0E 0.315
3A 0.535 2B 0.46 1C 0.385 0D 0.31
39 0.53 2A 0.455 1B 0.38 0C 0.305
38 0.525 29 0.45 1A 0.375 0B 0.3

Table 15: Intel VR12.5 VID Table – 10mV VID Step
VID VOLTAGE VID VOLTAGE VID VOLTAGE VID VOLTAGE VID VOLTAGE
(HEX) (V) (HEX) (V) (HEX) (V) (HEX) (V) (HEX) (V)
FF 3.04 E1 2.74 C3 2.44 A5 2.14 87 1.84
FE 3.03 E0 2.73 C2 2.43 A4 2.13 86 1.83
FD 3.02 DF 2.72 C1 2.42 A3 2.12 85 1.82
FC 3.01 DE 2.71 C0 2.41 A2 2.11 84 1.81
FB 3.00 DD 2.70 BF 2.40 A1 2.10 83 1.80
FA 2.99 DC 2.69 BE 2.39 A0 2.09 82 1.79
F9 2.98 DB 2.68 BD 2.38 9F 2.08 81 1.78
F8 2.97 DA 2.67 BC 2.37 9E 2.07 80 1.77
F7 2.96 D9 2.66 BB 2.36 9D 2.06 7F 1.76
F6 2.95 D8 2.65 BA 2.35 9C 2.05 7E 1.75
F5 2.94 D7 2.64 B9 2.34 9B 2.04 7D 1.74
F4 2.93 D6 2.63 B8 2.33 9A 2.03 7C 1.73
F3 2.92 D5 2.62 B7 2.32 99 2.02 7B 1.72
F2 2.91 D4 2.61 B6 2.31 98 2.01 7A 1.71
F1 2.90 D3 2.60 B5 2.30 97 2.00 79 1.70
F0 2.89 D2 2.59 B4 2.29 96 1.99 78 1.69
EF 2.88 D1 2.58 B3 2.28 95 1.98 77 1.68
EE 2.87 D0 2.57 B2 2.27 94 1.97 76 1.67
ED 2.86 CF 2.56 B1 2.26 93 1.96 75 1.66
EC 2.85 CE 2.55 B0 2.25 92 1.95 74 1.65
EB 2.84 CD 2.54 AF 2.24 91 1.94 73 1.64
EA 2.83 CC 2.53 AE 2.23 90 1.93 72 1.63
E9 2.82 CB 2.52 AD 2.22 8F 1.92 71 1.62
E8 2.81 CA 2.51 AC 2.21 8E 1.91 70 1.61
E7 2.80 C9 2.50 AB 2.20 8D 1.90 6F 1.60
E6 2.79 C8 2.49 AA 2.19 8C 1.89 6E 1.59
E5 2.78 C7 2.48 A9 2.18 8B 1.88 6D 1.58
E4 2.77 C6 2.47 A8 2.17 8A 1.87 6C 1.57
E3 2.76 C5 2.46 A7 2.16 89 1.86 6B 1.56
E2 2.75 C4 2.45 A6 2.15 88 1.85 6A 1.55

VID VOLTAGE VID VOLTAGE VID VOLTAGE VID VOLTAGE VID VOLTAGE
(HEX) (V) (HEX) (V) (HEX) (V) (HEX) (V) (HEX) (V)
69 1.54 53 1.32 3D 1.10 27 0.88 11 0.66
68 1.53 52 1.31 3C 1.09 26 0.87 10 0.65
67 1.52 51 1.30 3B 1.08 25 0.86 F 0.64
66 1.51 50 1.29 3A 1.07 24 0.85 E 0.63
65 1.50 4F 1.28 39 1.06 23 0.84 D 0.62
64 1.49 4E 1.27 38 1.05 22 0.83 C 0.61
63 1.48 4D 1.26 37 1.04 21 0.82 B 0.60
62 1.47 4C 1.25 36 1.03 20 0.81 A 0.59
61 1.46 4B 1.24 35 1.02 1F 0.80 9 0.58
60 1.45 4A 1.23 34 1.01 1E 0.79 8 0.57
5F 1.44 49 1.22 33 1.00 1D 0.78 7 0.56
5E 1.43 48 1.21 32 0.99 1C 0.77 6 0.55
5D 1.42 47 1.20 31 0.98 1B 0.76 5 0.54
5C 1.41 46 1.19 30 0.97 1A 0.75 4 0.53
5B 1.40 45 1.18 2F 0.96 19 0.74 3 0.52
5A 1.39 44 1.17 2E 0.95 18 0.73 2 0.51
59 1.38 43 1.16 2D 0.94 17 0.72 1 0.50
58 1.37 42 1.15 2C 0.93 16 0.71 0 0.00
57 1.36 41 1.14 2B 0.92 15 0.70
56 1.35 40 1.13 2A 0.91 14 0.69
55 1.34 3F 1.12 29 0.90 13 0.68
54 1.33 3E 1.11 28 0.89 12 0.67

PHASING the phase configuration to operate with the populated
phases (up to the configuration allowed by the
The number of phases enabled on each loop of the settings in Table 16).
IR35201 is shown in Table 16. The phase of the PWM
outputs is automatically adjusted to optimize phase In addition, the IR35201 detects the number of
interleaving for minimum output ripple. Phase populated phases at start-up by comparing the
interleaving results in a ripple frequency that is the voltage on the PWM pin against the phase detection
product of the switching frequency and the number of threshold. In order for populated phases to be
phases. A high ripple frequency results in reduced detected, the MOSFET drivers need to be powered up
ripple voltage, thereby minimizing the output filter before the VCC, +12Vin and Vaux to the IR35201
capacitance requirements, resulting in significant total exceeds its POR threshold.
BOM cost reduction.
Typical PWM pulse phase relationships are shown in
TABLE 16: LOOP CONFIGURATION Table 17 and Figure 16.
Configuration Loop 1 Loop 2
8+0 8-phases - TABLE 17: PHASE RELATIONSHIP
7+0 7-phases - Phases Phasing
6+0 6-phases - 1 -
5+0 5-phases - 2 180º
4+0 4-phases - 3 120º
3+0 3-phases - 4 90º
5 72º
2+0 2-phases -
6 60º
1+0 1-phase -
7 51.42º
7+1 7-phases 1-phase
8 45º
1+1 1-phase 1-phase
1+2 1-phase 2-phase
UNUSED PHASES
Figure 16: 4-phase PWM interleaved operation
Phases are disabled based upon the configuration
shown in Table 16. Disabled PWM outputs should
be left floating unless the auto-populate phase SWITCHING FREQUENCY
detection feature is used. Unused phases should be The phase switching frequency (Fsw) of the IR35201
disconnected in reverse order to ensure a correct is set by a user configurable register. The switching
phase relationship. E.g. a 4+0 configuration must frequency can be set indepently on each loop. The
have PWMs on phases 3 and 4 disconnected in order switching frequency variation with register setting has
to operate in 2+0 mode. If phases 1 or 2 were been plotted in Figure 17.
disconnected instead, the remaining phases would not
have a symmetrical relationship, leading to unreliable The IR35201 oscillator is factory trimmed to guarantee
performance. If the auto-populate phase detection high accuracy and very low jitter compared to analog
feature is used, unused PWM outputs should be controllers.
grounded so that their voltage is below the threshold
(phase is disabled). IR35201 automatically adjusts

As shown in Figure 19, the Vsen and Vrtn inputs have
a 20kΩ pull-up to an internal 1V rail. This causes
some current flow in the Vsen and Vrtn lines. To
minimize the offset created by this current flow, the
external series impedance on these lines needs to be
kept to a minimum.
Figure 17: Switching Frequency Variation with Register Setting
MOSFET DRIVER AND POWERSTAGE

SELECTION
The PWM signals from the active phases of the
Figure 19: Output Voltage sensing impedance
IR35201 are designed to operate with industry
standard tri-state type drivers or PowIRstage devices.
The logic operation for these types of tri-state drivers INPUT CURRENT SENSING
is depicted in Figure 18. The IR35201 provides input current sensing to
measure the power drawn by the load from the
When in tri-state, the IR35201 floats the outputs so source. A precision current sense resistor is
that the voltage level is determined by an external connected in series with the input path as shown in
voltage divider which is typically inside the MOSFET Figure 21. The voltage across the current sense
driver. Sometimes external resistors are added to resistor is differentially amplified by a current sense
improve the speed of the PWM signal going into tri- amplifier and fed to I_IN pin of IR35201. An internal
state. ADC converts the sensed voltage into its digital
equivalent. The I_IN pin input voltage range is 0 to
Note that the PWM outputs are tri-stated whenever 1.25Vdc.
the controller is disabled (EN = low), the shut-down
ramp has completed or before the soft-start ramp is
initiated. _ ( )= ∗ ∗
The IR35201 offers four full-scale ranges for input
current.
1. 0 – 62.5A.
2. 0 – 31.25A.
3. 0 – 15.625A.
4. 0 – 7.8125A.
Figure 18: 3.3V Tri-state Driver Logic Levels
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The IR35201 VSEN and VRTN pins for each loop are
connected to the load sense pins of the output voltage
to provide true differential remote voltage sensing with
high common-mode rejection. Each loop has a high
bandwidth error amplifier that generates the error
voltage between this remote sense voltage and the
target voltage. The error voltage is digitized by a fast,
high-precision ADC. Figure 20 Input Current Sensing

PIN_ALERT current is also summed with the VID DAC output to
implement the AVP function.
The IR35201 has a PIN_ALERT# pin to alert the
system when the input power has exceeded a preset The recommended value for Csen is 220nF, with an
threshold. The pin is an open drain output that is high NPO type dielectric. To prevent undershooting of the
until the input power threshold is exceeded at which output voltage during load transients, the Rsen resistor
point it pulls low. The output stays low until the input can be calculated by:
power drops below 90% of the Pin_Alert
threshold. The PIN_ALERT# pin will de-assert 1.05 * L _ out
100mS after the input power drops below 90% of the Rsen 
C sen  DCR
PIN_ALERT threshold. In an Intel system the
Pin_alert pin is pulled up with a 4.99kohm resistor to
Note: Use thick film resistor (0603) for Rsen.
3.3 Vdc. The PIN is filtered by a 2KHz BW filter. The
PIN_ALERT# pin assertion will be belayed by up to
VCC_Core
300uS.
12V
OUTPUT CURRENT SENSING V cc BOOT

V in
PWM
The IR35201 provides per-phase output current P WM
sensing to support accurate Adaptive Voltage L_out

I Iphase
Positioning (AVP), current balancing, and over-current R1 IR3555
S witch
ISEN 10K
protection. The differential current sense scheme + IO UT
2.49K
supports both lossless inductor DCR and RDS (ON) (or IRTN R2
-
per-phase series precision resistor) current sensing REF IN
techniques.
For DCR sensing, a suitable resistor-capacitor

network of Rsen and Csen is connected across the Figure 22 RDS (ON) Current Sense
inductor in each phase as shown in Figure 21 below.
The time constant of this RC network is set to equal Additionally, the current sense inputs to the IR35201
the inductor time constant (L/DCR) such that the can also be directly fed the current information from a
voltage across the capacitor Csen is equal to the PowIRstage having RDS (ON) sensing capability, thereby
voltage across the inductor DCR. eliminating the need for the R-C sense components,
RSEN and CSEN as shown in Figure 22. The IR3555
has an IOUT gain of 5mV/A. A divider of 5:1 should
be used to match the ISENSE amp input dynamic
range. The recommended values are 10K and 2.49K.
The REFIN pin is offset above 0V by connecting it to
the 1.8V CFILT pin.
CURRENT BALANCING & OFFSET

The IR35201 provides accurate digital phase current
balancing in any phase configuration. Current
balancing equalizes the current across all the phases.
This improves efficiency, prevents hotspots and
reduces the possibility of inductor saturation.
Figure 21: DCR Current Sensing
The sensed currents for each phase are converted to

A current proportional to the inductor current in each
a voltage and are multiplexed into the monitoring
phase is generated and used for per-phase current
ADC. The digitized currents are low-pass filtered and
balancing. The individual phase current signals are
passed through a proprietary current balance
summed to arrive at the total current.
algorithm to enable the equalization of the phase
currents as shown in Figure 23.
The phase currents and total current are quantized by
the monitoring ADC and used to implement the
current monitoring and OCP features. The total

Table 43 for output current calibration registers.
LOAD LINE
The IR35201 enables the implementation of an
accurate, temperature compensated load line.
The nominal load line is set by an external resistor

RCS, as shown in Figure 25. This load line value also
needs to be stored in MTP. The stored values for load
line, scaling and gain provide the scaling factors
Figure 23: Typical Phase Current Balance required for digital computation of the total current, in
(3-phases enabled) order to determine the true current, OCP threshold,
and output voltage telemetry registers.
The proprietary high-speed active phase current
balance operates during load transients to eliminate For each loop, the sensed current from all the active
current imbalance that can result from a load current phases is summed and applied differentially to a
oscillating near the switching frequency. The order in resistor network across the RSCP and RCSM pins as
which the phases output PWM pulses is decided shown in Figure 25. This generates a precise
based on an adaptive High Speed Phase Balance proportional voltage, which is summed with the
(HSPB) to ensure that the phases remain balanced sensed output voltage and VID DAC reference to form
during high frequency load transients. Once the VR the error voltage.
returns to steady-state operation, the phases return to
the normal phase firing order. IR35201 supports two types of current sense
techniques.
In addition, the IR35201 allows the user to offset
phase currents to optimize the thermal solution. 1. DCR Current Sense.
Figure 24 shows Phase 1 current gain offset to a
value of 6. This scales the current in phase 1 to have 2. RDS (ON) Current Sense.
approximately 30% more current than the other
phases.
DCR Current Sense
DCR current sense technique measures the voltage

drop across DCR of the inductor as shown in Figure
21. DCR of the inductor has a positive temperature
coefficient of resistance. Hence, to compensate for
increase in DCR with respect to temperature and
thermistor RTh having negative temperature coefficient
of resistance is also part of the network. For proper
Figure 24: Phase 1 Current Offset load line temperature compensation, the thermistor is
placed near the phase one inductor to accurately
sense the inductor temperature.
CURRENT CALIBRATION
For optimizing the current measurement accuracy of a
design, the IR35201 contains a register in MTP, which
can store a user-programmed per phase Current
Offset, to zero out the no-load current reading. Refer
to

Murata NCP18XH103F03RB
Panasonic ERTJ1VG103FA
TDK NTCG163JF103F
3. Calculate RCS using the following equation:
1
RCS 
1 1

RCS effective  2  Rseries RTh
Rseries is selected to achieve minimum load line error
Figure 25: Load Line & Thermal Compensation for DCR Sense over temperature. The IR PowIRCenter GUI provides
a graphical tool that allows the user to easily calculate
the resistor values for minimum error.
The capacitor CCS is defined by the following equation:
1
CCS 
2    RCS effective  f AVP
where fAVP is the user selectable current sense AVP

bandwidth. The recommended bandwidth is typically
in the range of 200kHz to 300kHz.
RDS (ON) Current Sense

Figure 26 Load Line for RDS (ON) Current Sense
IR35201 reads the current value from individual power
The resistor RCS is calculated using the following stages as shown in Figure 22. The power stage
procedure: measures the output current by sensing the voltage
drop across lower side MOSFET. The current sensed
1. Calculate the RCSeffective or the total effective by the power stage is thermally compensated hence
parallel resistance across the RSCP and there is no need of an external thermistor for
RCSM pins as defined by: temperature compensation. Thus, RDS (ON) current
sense reduces the component count required for
loadline measurement as shown in Figure 26.
R LL
RCS effective  8  R _ ISEN 
DCR The resistor Rcs for RDS ON current sense is calculated
where RLL is the desired load line, DCR is DC by using the following procedure.
resistance of the phase inductor, and R_ISEN is the
internal series resistor = 1000. = 8∗ ∗ /( ∗ )
2. Select a suitable NTC thermistor, Rth. This is Where IRDS ON Scale = current scale of Power Stage in
typically selected to have the lowest thermal V/A
coefficient and tightest tolerance in a standard
available package. A typical NTC used in Divider Ratio = .Refer to Figure 22
these applications is a 10kΩ, 1% tolerance
device. Recommended thermistors are shown The capacitor CCS is defined by the following equation:
in Table 18.
1
CCS 
2    RCS  f AVP
TABLE 18: 10K 1% NTC THERMISTORS

where fAVP is the user selectable current sense AVP The IR35201 uses a digital feedback loop to minimize
bandwidth. The recommended bandwidth is typically the requirement for output decoupling, and to maintain
in the range of 200kHz to 300kHz. a tightly regulated output voltage. The error between
the target and the output voltage is digitized and
Setting a 0mΩ Load Line passed through a low pass filter. This filtered signal is
then passed through an initial single-pole filter stage,
The load line is turned off by setting the Loadline followed by the PID (Proportional Integral Derivative)
Enable bit low. This is a separate bit from the load line compensator, and an additional single-pole filter
settings for each loop. stage. The loop compensation parameters Kp
(proportional coefficient), Ki (integral coefficient), and
Even though the load line is disabled digitally, the Kd (derivative coefficient), as well as the low-pass filter
load-line resistors and scaling registers should be set pole locations are user-configurable to optimize the
such that the load line is at least 3 times the value of VR design for the chosen external components.
low ohmic DCR inductors (<0.5mΩ) or equal to the
DCR value for high ohmic inductors (>0.5mΩ). For The adaptive PID control used in IR35201 intelligently
example, if the inductor(s) DCR is 0.3mΩ, a nominal scales the coefficients and the low-pass filters in real-
0.9 mΩ load line should be set. For accurate current time, to maintain optimum stability, as phases are
measurement and OCP threshold with the load line added and dropped dynamically in the application.
disabled, the output current gain and scaling registers This auto-scaling feature significantly reduces design
must be set to the same value as the load line set with time by virtue of having to design the PID coefficients
the external resistor network. With load line disabled, design only for one loop combination. (Figure 28).
the thermistor and Ccs capacitor must still be installed
to insure accuracy of the current measurement.
Figure 27 shows a typical 1.05mΩ load line

measurement with minimum and maximum error
ranges. The controller accuracy lies well within
common processor requirements.
Figure 28: Stability with Phase Add/Drop
Each of the proportional, integral and derivative terms

is a 6-bit value stored in MTP that is decoded by the
IC’s digital core. This allows the designer to set the
converter bandwidth and phase margin to the desired
Figure 27: Load Line Measurements
values.
The load line range for IR35201 is shown in Table 19.
The compensator transfer function is defined as:
TABLE 19: LOAD LINE SETTINGS
   
Loop #1 Loop #2 Ki  1   1 
Minimum 0.0 mΩ 0.0 mΩ
( Kp   Kd  s)     
s  1  s p   1  s p 
Maximum 6.375 mΩ 12.75 mΩ  1   2 
Resolution 0.025 mΩ 0.050 mΩ
where ωp1 and ωp2 are the two configurable poles,
typically positioned to filter noise, and to roll off the
high-frequency gain that the Kd term creates.
DIGITAL FEEDBACK LOOP & PWM

The outputs of the compensator and the phase
current balance block are fed into a digital PWM pulse
generator to generate the PWM pulses for the active
phases. The digital PWM generator has a native time VCORE
resolution of 1.3ns which is combined with digital
dithering to provide an effective PWM resolution of
163ps. This ensures that there is no limit cycling when
operating at the highest switching frequency.
ADAPTIVE TRANSIENT ALGORITHM (ATA)
The IR35201 Adaptive Transient Algorithm (ATA) is a

high speed non-linear control technique that allows
compliance with CPU voltage transient load regulation
requirements, with minimum output bulk capacitance Figure 30: ATA feature – zoomed-in
for reduced system cost.
In addition, during a load transient overshoot, the ATA
A high-speed digitizer measures both the magnitude may also be programmed to turn off the low-side
and slope of the error signal to predict the load current MOSFETS instead of leaving them on. This forces the
transient. This prediction is used to control the pulse load current to flow through the larger FET body
widths and the phase relationships of the PWM diode, and helps to reduce the overshoot created
pulses. The ATA bypasses the PID control during a load release, as showing in Figure 31 below.
momentarily during load transients to achieve very
wideband closed loop control and smoothly transitions
back to PID control during steady state load Diode Emulation:
conditions. Figure 29 illustrates the transient Disabled
Enabled
performance improvement provided by the ATA
showing the clear reduction in undershoot and
overshoot. Figure 30 is a zoomed-in scope capture of
a load step, illustrating the fast reaction time of the
ATA, and how the algorithm changes the pulse phase
relationships. IR35201 provides the option to enable
or disable this feature, using a digitally programmable
bit.
ATA Enabled
Figure 31: Diode Emulation during a load release
HIGH-SPEED PHASE BALANCE

The IR35201 provides phase balance during high
frequency load oscillations. The balance is provided
through phase skipping. Whenever a set error voltage
threshold and load oscillation frequency threshold are
ATA Disabled
exceeded for a particular phase, that phase is
skipped, resulting in a lowering of current in the
skipped phase and a corresponding increase in
current in the other phases. Both these thresholds,
Figure 29: ATA Enable/Disable Comparison listed in Table 20, are user programmable, to provide
flexibility in high-speed phase balance for a wide
variety of systems. In addition, the IR35201 allows the
user to disable HSPB by resetting a bit in MTP.

DYNAMIC VID COMPENSATION
TABLE 20: HIGH-SPEED THRESHOLDS
The IR35201 can compensate for the error produced
Register Function
by the current feedback in a system with AVP (Active
Voltage Positioning) when the output voltage is
Hspb_enable Dedicated bit to enable/disable HSPB. ramping to a higher voltage. An output capacitance
Resetting this bit will result in the HSPB
function not being activated, regardless of the term and an AVP bandwidth term are provided in the
error voltage or load oscillation frequency MTP registers to help model the effects of variation in
settings. output voltage during a voltage ramp, due to the
Hspb_hth Error Voltage threshold. inrush current seen by the output bulk capacitors.
Activates HSPB when the threshold is Once properly modeled, the output voltage will follow
exceeded.
the DAC more closely during a positive dynamic VID,
0mV – 60mV, 4mV resolution
and provide better dynamic VID alert timing, as
Hspb_fth Load Oscillation Frequency Threshold. ®
required by Intel processors. Figure 32 shows the
Activates HSPB when the load oscillation effects that Dynamic VID Compensation has on the
frequency is above threshold.
0kHz – 703.5kHz, 46.9kHz resolution.
output voltage and the alert timing.
DYNAMIC VID SLEW RATE

DVID COMP ON;
The IR35201 provides the VR designer 16 fast slew 3000uF
rates each of which can be further configured to 4
different slow slew rates by selecting a slew rate
setting as shown . These slew rates can be further DVID COMP OFF
reduced ½, 1/4, 1/8, and 1/16
TABLE 21: SLEW RATES
Fast x 1/2 x 1/4 x 1/8 x 1/16

Rate Factor Factor Factor Factor
10 5.0 2.50 1.25 0.0625
15 7.5 3.75 1.875 0.94
20 10 5.00 2.50 1.25
25 12.5 6.25 3.125 1.56 Figure 32: Dynamic VID Compensation
30 15 7.5 3.75 1.88
35 17.5 8.75 4.375 2.19
mV/ 40 20 10 5.0 2.5

µs 45 22.5 11.25 5.625 2.81
50 25 12.5 6.25 3.125
EFFICIENCY SHAPING
55 27.5 13.75 6.875 3.4375
60 30 15 7.5 3.75 In addition to CPU-specified Power States, the
65 32.5 16.25 8.125 4.0625
IR35201 features Efficiency Shaping Technology that
enables VR designers to cost-effectively maximize
70 35 17.5 8.75 4.375
system efficiency. Efficiency Shaping Technology
80 40 20 10 5 consists of Dynamic Phase Control to achieve the
85 42.5 21.25 10.625 5.3125 best VR efficiency at a given cost point.
95 47.5 23.75 11.875 5.9375
POWER-SAVING STATES
Note: The maximum DVID rate is limited by the inductor The IR35201 uses Power States to set the power-
current available to charge the output capacitors. High savings mode. These are summarized in Table 22.
DVID rates may not be possible if the output capacitor and
inductor combination does not allow the output voltage to
change at the selected rate. TABLE 22: POWER STATES
Power Recommended
Mode
State Current

PS0 Full Power Maximum Exit SVID Clock Toggle.
b) In Multi Mode – Any
PS1 Light Load 1-2Φ <20A
SetVID Command
1Φ Active Discontinuous
PS2
(Diode Emulation)
<5A .
1Φ Passive Discontinuous DYNAMIC PHASE CONTROL (DPC) IN PS0
PS3 <1A
(Diode Emulation)
Output Voltage DVID or IR35201 optionally supports the ability to
Decay Down to zero autonomously adjust the number of phases with load
depending upon
PS4 configuration in Near OFF current, thus optimizing efficiency over a wide range
“ps4_dvid_or_decay” of loads.
registor. PWM signals of The output current level at which a phase is added
all phases are tristated.
can be programmed individually for each phase for
optimum results (Table 24).
The Power States may be commanded through
I2C/PMBus, the SVID interface, or the IR35201 can TABLE 24: DPC THRESHOLDS
autonomously step through the Power States based Register (2A steps) Function
upon the regulator conditions as summarized in Table
Phase1_thresh 2Φ when I > Phase1_thresh
23. PS4 can only be commanded with an SVID
command Phase2_delta 3Φ when I > Phase1_thresh +
Phase2_delta
Phase3_delta 4Φ when I > Phase1_thresh +
IVID REGISTER Phase2_delta+Phase3_delta
Phase4_delta 5Φ when I > Phase1_thresh +
IVID efficiency registers are new additions to the Phase2_delta+Phase3_delta+
family of SVID registers of the IMVP8 specification. Phase4_delta
When sent an SVID command associated with IVID Phase5_delta 6Φ when I > Phase1_thresh +
registers, IR35201 acknowledges the command and Phase2_delta+Phase3_delta+
stores the received information into the IVID registers. Phase4_delta+Phase5_delta
However, IR35201 does not use the information Phase6_delta 7Φ and 8Φ when I > Phase1_thresh +
Phase2_delta + Phase3_delta +
received in IVID registers for any purpose. Instead, it Phase4_delta + Phase5_delta +
uses the user set-up phase shed function to optimize Phase6_delta
the VR’s efficiency across the entire operating current
range.
As shown in Figure 33 (loop one, 8-phase example
Table 23: Power State Entry/Exit shown), the designer can configure the VR to
dynamically add or shed phases as the load current
Command Mode Auto Mode varies. Both control loops of the IR35201 have the
PS1 a) Command n/a if Phase Shed enabled DPC feature.
Entry
a) Command to PS0 n/a if Phase Shed enabled Per -phase
PS1 Programmable
b) DVID to PS0 Programmable
Exit Threshold for
c) Current limit to PS0 Threshold for Auto
Auto DCM
Phase Shed
PS2 a) Command Current level in 1Φ
Entry
a) Command to PS1/0 Fsw > Fsw_desired
PS2
b) DVID to PS0 to PS0, DVID to PS0,
Exit
c) Current limit to PS0 Current limit to PS0
Efficiency
PS3 a) Command Current level in 1Φ

yDCM
1Ø 2Ø 3Ø 8Ø
Entry
a) Command to PS2/1/0 Fsw > Fsw_desired
PS3
b) DVID to PS0 to PS0, DVID to PS0,
Exit
c) Current limit to PS0 Current limit to PS0
PS4
a) Command n/a
Entry
Load Current
PS4 a) In Single Mode- Any n/a
Figure 33: Dynamic Phase Control Regions

The IR35201 Dynamic Phase Control reduces the
number of phases (Figure 34) based upon monitoring
both the filtered total current and the error voltage VCORE
over the DPC filter window. Monitoring the error
voltage insures that the VR does not drop phases
during large load oscillations.
VCORE
Figure 36: Zoomed-out view of Phase Shed/Add

PWM1
PWM2
Current limit and current balancing circuits remain
PWM3 active during ATA events to prevent inductor
PWM4
PWM5 saturation and maintain even distribution of current
across the active phases.
Figure 34: Phase Shed 5Φ1Φ The add/drop points for each phase can be set in 2A
increments from 0 to 62A per phase, with a fixed 4A
During a large load step, and based on the error hysteresis. This results in a uniform per-phase current
voltage, the controller instantly goes to the maximum density as the load increases or decreases.
programmed number of phases. It remains at this
level for a period equivalent to the DPC filter delay, Having DPC enabled optimizes the number of phases
after which phases get dropped depending on the used in real time, Resulting in significant light and
load current. The Dynamic Phase Control (DPC) medium-load efficiency improvements, as shown in
algorithm is designed to meet customer specifications Figure 37.
even if the VR experiences a large load transient
when operating with a lower number of phases. The
ATA circuitry ensures that the idle phases are
activated with optimum timing during a load step as
shown in Figure 35 and Figure 36 below.
VCORE
PWM1
Figure 37: Light Load Efficiency Improvement with DPC
PWM2
PWM3
PWM4
PWM5 VARIABLE FREQUENCY WITH LOAD ON LOOP1
In addition, the controller can be made to operate at a
Figure 35: Phase Add 1Φ5Φ high frequency when only a few phases are running,
and lower the frequency as more phases are added.
This skew feature is based on monitoring the per-
phase current. The different skews of the switching
frequency available are:

Sets the duration of the ON time pulse in
de_pw
40ns steps during diode emulation.
TABLE 25: SWITCHING PERIOD SKEW FACTOR OPTIONS
Reduces the calculated low-side FET
Per-Phase Starting ON time during diode emulation in 60ns
Switching Period Skew Range off_time_adj steps. Useful for compensating for DrMOS
Current (A)
or other drivers’ tri-state delay for better
Fsw to 2 x Fsw 8 zero-crossing prediction.
Fsw to 2 x Fsw 12
Fsw to 2 x Fsw 16
Fsw to 0.5 x Fsw 8
In PS2 mode (Active Diode Emulation Mode), the
internal circuitry estimates when the inductor current
Fsw to 0.5 x Fsw 12
declines to zero on a cycle-by-cycle basis, and shuts
Fsw to 0.5 x Fsw 16 off the low-side MOSFET at an appropriate time in
Note: Per Phase Current is limited to 62A in normal each cycle (Figure 39). This effectively lowers the
mode, 124A in doubler mode. switching frequency, resulting in lowered switching
Using the above feature, the switching frequency can losses and improved efficiency.
be skewed based on the different register settings and
per-phase currents – the switching frequency skew Industry standard tri-state drivers typically have delays
factor versus per-phase currents have been plotted in when entering tri-state, typically 150ns to 300ns,
Figure 38 below for 3 of the register settings for which allows negative current to build up, causing
reference. switch node ringing and reducing efficiency.
The off_time_adj variable allows for compensation of

the tri-state delay by reducing the low-side FET on-
time by an equivalent amount.
VOUT
Zero-crossing prediction
at the correct time
IΦ1
Programmed
on-time Calculated low-side
FET on-time
Figure 38: Normalized Switching Frequency PWM(Φ1)
DISCONTINUOUS MODE OPERATION - PS2, PS3

Under very light loads, the VR efficiency is dominated
Figure 39: PS2 Active Diode Emulation Mode
by MOSFET switching losses. In PS2 mode, the
IR35201 operates as a constant on-time controller
where the user sets the desired peak-to-peak ripple PS4 MODE
by programming an error threshold and an on-time
duration (Table 26). PS3 operation is identical to PS2, The IR35201 controller supports the PS4 command
with the additional ability to disable the internal current but does not reduce controller power consumption .
sense amplifiers within the controller for further
reduction in power consumption. When a valid PS4 command is received by the
controller, the IR35201 does the following:
TABLE 26: PS2/PS3 MODE CONSTANT ON-TIME CONTROL  Acknowledge the command.
 Output voltage is DVID or Decay down to 0
MTP Register Function
Vdc depending upon the configuration in
Sets the current level below which “ps4_dvid_or_decay” register.
ni_thresh
PS2/PS3 is entered.
 PWM signals of all phases are tristated.
Sets the error threshold to start a pulse
de_thresh
during diode emulation, in 3mV resolution.

The controller does not shutdown the circuitry for voltage condition. This release mode reduces the
lowest power consumption. undershoot of the output voltage during recovery from
an OVP condition. If the output voltage rises above
PS4 wake up can be set to wake on any SVID clock the OVP threshold during recovery, the low side
or alternatively on any SVID Set_VID or SetPS0/1/2/3 MOSFET’s will again be turned on until Vout drops
command. below the release threshold level. Note that OVP is
disabled during a DVID-down event to prevent false
PS4 REGISTER SUPPORT triggering.
IR35201 controller supports SVID register “PS4 Exit
Latency” (2B). This register holds the encoded value for PS4 During soft-start, OVP is triggered at a user-selectable
exit latency calculated as level from one of the thresholds listed in Table 29
( )= ∗2 below.
16
Where x =bits[3:0], y = bits[7:4]
TABLE 29: OVP THRESHOLDS DURING START-UP
Value Threshold
FAULTS & PROTECTION
0 2.5V
The comprehensive fault coverage of the IR35201 1 1.2V

protects the VR against a variety of fault conditions. 2 1.275V
Faults can be configured and monitored through the 3 1.35V
IR PowIRCenter GUI. There are two types of fault
monitoring registers. In addition to real-time fault
registers, there are “sticky” fault registers that can only The IR35201 also provides the option to allow OVP to
be cleared with an I2C command or 3.3V power cycle. remain active when the device is disabled, in order to
These will indicate if any fault has occurred since the prevent system leakage from causing over-voltage on
last power cycle, even if the fault has cleared itself the output (Table 30).
and the VR has resumed normal operation.Table 27
lists the available faults. Note: OVP functionality is only available when both
the controller and drivers or power stages have Vcc
TABLE 27: STICKY & NON-STICKY FAULTS
power.
Register Type Faults

TABLE 30: OVP OPTIONS
Sticky OTP, OCP, OVP, UVP,
VIN UVLO, 3.3V UVLO, OVP_when-disabled setting When active
Non-Sticky phase-fault, slow-OCP On IC disabled & IC enabled
Off IC enabled
Output Over-voltage Protection (OVP)

If the output voltage exceeds a user-programmable
threshold (Table 32) above the VID set-point, the
IR35201 detects an output over-voltage fault and
latches ON the low-side MOSFETS to limit the output
voltage rise.
TABLE 28: OVP ACTION
OVP Action
Low-side MOSFET latched on
Low-side MOSFET on until
Output<0.248V
Per Table 28 above, the low-side MOSFETs may be

configured to either latch ON indefinitely (Figure 40) or Figure 40: OVP - MOSFET latched on
stay ON until the output voltage falls below the
release threshold (Figure 41), in case of an over-

The controller action during an OCP event can be
configured as shown in TABLE 33. Note that the OCP
protection is disabled during start up and during VID
transitions. Also, the threshold scales by a factor of 2x
in the doubler mode and 4x in the quad mode.
TABLE 33: OCP & UVP MODE SELECTION
OCP/UVP Behavior Mode

Per phase OCP Threshold (0 to 62A)
Shutdown immediately
(cycle power or enable to restart)
Hiccup 2X before Shutdown
Hiccup indefinitely
Figure 41: OVP - MOSFET released when output<0.3V

Slow Current Limit
Output Under-voltage Protection (UVP) In addition to the (fast) OCP, a Slow Current Limit can
be programmed to monitor and protect against the
The IR35201 detects an output under-voltage thermal effects of the average current over time. This
condition if the sensed voltage at the CPU is below allows the system designer to operate close to the
the user-programmable UVP threshold (Table 32) or a TDP level of the system. The slow current limit
fixed 248mV (if the ADC detection is used instead of bandwidth is set by the telemetry bandwidth to one of
the comparator), as shown inTable 31. the following options:
TABLE 31: UVP THRESHOLD OPTIONS TABLE 34: TELEMETRY BANDWIDTH SETTING OPTIONS
Use the common comparator Value Bandwidth (Hz)
Use the ADC 0 0.69
1 1.39
The user also has the option to choose if the threshold 2 2.78
needs to factor in the load line or not. Upon detecting 3 5.55
an output under-voltage condition, the IR35201 4 11.1
responds in the same manner as the OCP, according 5 22.2
to the setting selected inTable 33. 6 44.6
7 89.5
TABLE 32: OVP & UVP THRESHOLDS
Value Threshold
0 50mV When the slow OCP threshold is exceeded, the VR
1 100mV will shut down based upon the OCP mode
2 150mV programmed in the MTP.
3 200mV Note that the slow OCP protection is disabled during
4 250mV start up and during VID transitions.
5 300mV
6 350mV VR_HOT and Over Temperature Protection (OTP)
7 400mV The IR35201 provides a temperature measurement
capability at the TSEN pin that is used for over
temperature protection, VR_HOT flag and
Over-current Protection (OCP) temperature monitoring. The temperature is measured
The IR35201 provides a programmable output over- with either an NTC network or by monitoring IR
current protection threshold of up to 62A per phase. PowIRstage temperature reporting outputs. Sense
This would translate to an overall maximum system devices need to be placed close to the thermal hot
OCP threshold of 62A times the number of phases. spot for optimal performance. The thresholds are

programmable in 1°C increments within the range over voltage condition. The controller will shut down
shown in Table 35. If the measured temperature and assert the CAT_FLT pin (high) upon receiving the
exceeds the OTP threshold, the IR35201 will latch off power stage fault.
the VR, requiring a system power recycle or an
To controller
ENABLE recycle to resume operation. TSEN
6.49KOhm
TABLE 35: VR_HOT & OTP
TOUT
Function From IR3555 100pF 10KOhm
VR_HOT threshold (64°C to 127°C)

OTP threshold (VR_HOT + 0°C to 32°C) max 135°C
MAX 158C with IR3555 temp sense
Figure 43: Temperature Sense IR Power Stage Network
NTC Temperature Sense

VR_HOT_ICRIT Pin Functionality Options
The IR35201 includes a pre-programmed look-up
The functionality of the VR_HOT_ICRIT pin can be set
table that is optimized for the recommended NTC
to assert when levels of Temp_max, Icc_max, and/or
options shown in Table 36. The NTC network is
OCP levels are exceeded. Table 37 shows the
connected to the TSEN pin as shown in Figure 42.
multiple configurations of the VR_HOT_ICRIT pin.
A 0.01µF capacitor is recommended for filtering when
TABLE 37: VR_HOT_ICRIT PIN OPTIONS
used with the NTC sense network.
Temp_max Only
TABLE 36: NTC TEMPERATURE SENSE RANGE Temp_max or Icc_max
NTC Value Rparallel Temp_max or OCP
Murata NCP15WB473F03RC or Icc_max Only
47KΩ 13KΩ
Panasonic ERT-J0EP473J
Icritical Flag
The IR35201 VR_HOT_ICRIT pin can optionally be
programmed to assert when a user programmable
output current level is exceeded. The assertion is not
a fault, and the VR continues to regulate. I_CRITICAL
monitors a long term averaged output current, which
is a useful indicator of average operating current and
thermal condition. The user can select between the
Figure 42: Temperature Sense NTC Network I_CRITICAL filters bandwidths shown in Table 38.
TABLE 38: I_CRITICAL OVER-CURRENT OPTIONS
Value Bandwidth (Hz)

IR Power Stage Temperature Sense 0 0.69
1 1.39
The controller is designed to interface to the IR3555 2 2.78
power stage to receive temperature and fault
3 5.55
information from the IR3555 power stage. The power
stage temperature output is scaled to 8mV/C and a 4 11.1
1:1.64 divider is required to scale this down to the 5 22.2
4.88mV/C gain of the controller input as shown in 6 44.6
Figure 43. Fault communication from the IR3555 is a 7 89.5
3.3Vdc high. The 3.3Vdc high from the power stage
indicates either 1) a power stage phase fault, 2) an
over temperature, 3) a persistent overcurrent or 4) an

I_CRITICAL has a 5% hysteresis level and the (note that a 0.01µF capacitor is required across the
VR_HOT_ICRIT pin will de-assert when the average resistor per Figure 44), with the offsets shown in
output current level drops below 95% of the programmed Table 42.
current level threshold.
As an example, setting a base 7-bit I2C address of 28h
Input Over-voltage Protection with a resistor offset of +15 sets the 7-bit I2C address to
37h. Similarly setting a base 7-bit PMBus address of 40h
The IR35201 offers protection against input supply over- with a resistor offset of +15 sets the 7-bit PMBus address
voltage. When enabled (Table 39), the VINSEN pin is to 4Fh.
compared to a fixed threshold of 14.5V with a 14:1
divider, and shuts down the IC if the threshold is The IR35201 can also set the I2C address indepen-
exceeded. dently from the PMBus address. By using a 7-bit address
the user can configure the device to any one of 127
TABLE 39: INPUT OVER-VOLTAGE OPTIONS different I2C addresses.
disabled
Once the address of the IR35201 is set, it is locked to
enabled
protect it from being overridden.
Phase Faults For default programmed devices, the I2C/PMBus

The IR35201 can detect and declare a phase fault when address can be temporarily forced to address 0Ah for
the current in one or more phases is too high or too low. I2C and 0Dh for PMBus by setting EN=VR_HOT=low.
It detects the fault when the duty cycle of a particular
phase is 5% higher or lower than the average duty cycle TABLE 41: I2C OFFSET OPTIONS
of all the phases. This feature helps detect severe
imbalances in the phase currents, an unpowered or Enable_I2C
I2C Address Offset
Addr_Offset MTP bit
damaged MOSFET driver, or a phase that is
0 disabled
disconnected from Vin. The phase fault feature can be
1 enabled
enabled or disabled through an MTP bit. When a phase
fault occurs, the controller shuts down the loop where the
fault occurred, and sets register bits to display which TABLE 42: ADDR RESISTOR OFFSET
phase had the fault and whether it faulted high or low.
I2C Address
The phase fault registers are cleared via a register bit ADDR Resistor
Offset
and the VR will restart once ENABLE or Vcc is cycled. 0.845kΩ +0
1.30kΩ +1
TABLE 40: PHASE CURRENT FAULT REGISTERS
1.78kΩ +2
Register Function 2.32kΩ +3
2.87kΩ +4
pi_fault_en Enables phase current fault
shutdown. 3.48kΩ +5
4.12kΩ +6
clear_phase_faults Clears all phase faults for each loop.
4.75kΩ +7
pi_fault Indicates which phase has a phase
current fault. 0 – phase1, 1 – phase2, 5.49kΩ +8
2 – phase3, 3 – phase4…7-phase 8 6.19kΩ +9
max_cond Indicates one or more phase currents 6.98kΩ +10
are too high. 7.87kΩ +11
min_cond Indicates one or more phase currents 8.87kΩ +12
are too low.
10.00kΩ +13
11.00kΩ +14
12.10kΩ +15
I2C/PMBUS COMMUNICATION
Note: Extends the range of PMBus addresses.
The IR35201 simultaneously supports I2C and PMBus
through the use of exclusive addressing. This means that
a motherboard PMBus master may communicate with as
many as 127 IR35201-based VRs. Optionally, a resistor
offset can be enabled as shown in Table 41

20%
15% Iout Error
10% CPU spec with 7% inductors
5%
Error
0%
Figure 44: ADDR pin components 0 10 20 30 40 50 60 70 80 90 100
-5%
-10%
-15%
REAL-TIME I2C MONITORING FUNCTIONS -20%
E-Load (A)
IR35201 provides real-time accurate measurement of
input voltage, input current, output voltage, output Figure 45: I2C IOUT Error using 10% DCR Inductors
current and temperature over the I2C interface.
Output voltage is calculated based upon the VID 12.3 1.0%
setting and load line, and the result is reported 12.2

0.5%
through the I2C. 12.1
Vin (V)
Error
12 0.0%
Accuracy Optimization Registers

11.9 Vin (DMM)
-0.5%
The IR35201 provides excellent factory-trimmed chip 11.8
Vin (I2C)
Vin error (2nd axis)
accuracy. In addition, the designer has calibration
11.7 -1.0%
capability that can be used to optimize reporting 0 20 40 60 80 100
E-Load (A)
accuracy for a given design, with minimum component
changes. Once a design is optimized, the IR35201 Figure 46: I2C Input Voltage Measurements
provides excellent repeatability from board to board.
The IR35201 also provides capability for individual 1.050 1.00%
Vout (DMM)
board calibration and programming in production for 1.025 0.75%
Vout (I2C)
best accuracy. 1.000
Vout error (2nd axis)
0.50%
0.975 0.25%
Vout (V)
Error
Table 43 shows the MTP registers used to fine tune 0.950 0.00%
0.925 -0.25%
the accuracy of the reported measurements. Figure
0.900 -0.50%
45 to Figure 47 show the typical accuracy of the
0.875 -0.75%
output current, input voltage and output voltage 0.850 -1.00%
measurements using the IR35201. 0 20 40 60 80 100
E-Load (A)
TABLE 43: ACCURACY OPTIMIZATION REGISTERS Figure 47: I2C Output Voltage Measurements
NVM Register Function I2C SECURITY

IIN Fixed Offset Offsets the input current in 1/32A steps. The IR35201 provides robust and flexible security
options to meet a wide variety of customer applications.
Offsets the input current dependent upon the
number of active phases in 1/128A steps e.g. A combination of hardware pin and software passwords
IIN Per Phase
Offset
the drive current for the MOSFET’s. This prevent accidental overwrites, discourages hackers, and
current increases every time a new phase is secures custom configurations and operating data. The
added.
Read and Write Security can be in set in MTP (Table 44
IOUT Current Offsets the output current from and Table 45) with the protection methods shown in
Offset -2A to +1.875A per phase in 0.125A steps
Table 46.
Offsets the output voltage +40mV to -35mV in
Vout Offset 5mV steps (Intel® VR12 mode), or +80mV to TABLE 44: READ SECURITY
-70mV in 10mV steps (Intel® VR12.5 mode).
No Protection
Offsets the temperature +31°C to -32°C in
Temperature 1°C steps to compensate for offset between Configuration Registers Only
Offset the hottest component and the NTC sensing Protect All Registers But Telemetry
location.
Protect All
Duty Cycle Adjusts the input current calculation to
Adjust compensate for a non-ideal driver.
TABLE 45: WRITE SECURITY

No Protection Min/Max Registers
Configuration Registers Only Min/Max registers for IOUT, IIN, VOUT, VIN, and
Protect All TEMPERATURE are available. The data is read by
setting a pointer and reading the value from a register
that contains the minimum and maximum data. These
TABLE 46: READ OR WRITE UNLOCK OPTIONS registers store high and low values from startup or the
last read, whichever was the latest to occur. The
Password Only registers are automatically cleared when the data is read
Pin Only back from the controller
Pin & Password
The minmax_sel[4:0] register is the pointer used to select
Lock Forever the appropriate signal and the minmax_val[7:0] register
will show the min or max value of what has been
selected. The list of available min/max values,
Password Protection
bandwidth, and resolutions are shown in Table 50.
The system designer can set any 16-bit password (other
than 00h). This password is stored in MTP. To unlock, a TABLE 50: MIN/MAX REGISTER SETTINGS
user must write the correct password into the “Password
Resolution
Try” register, which is a volatile read/write register. After Pointer Signal
Reading of reading
Value bandwidth
four incorrect tries, the IC will lock up to prevent value
unauthorized access. 0 loop_1_current_min
62 KHz/ 3.93 2A
1 loop_1_current_max KHz (based
TABLE 47: PASSWORD REGISTERS on minmax
2 loop_2_current_min
_output_i_bw) 0.5A
Register Length Location 3 loop_2_current_max
Password 16 bit (2 bytes) MTP loop_1_input
4
_current_min
Try 16 bit (2 bytes) R/W 0.125A
loop_1_input
The following pseudo-code illustrates how to change 5
_current_max
a password: 102Hz
loop_2_input
# first unlock the IC 6
_current_min
Write old password high Byte to R/W high Byte Try register 0.0625A
Write old password low Byte to R/W low Byte Try register loop_2_input
7
# now write new password into MTP _current_max
Write new password high Byte to high Byte Password register loop_1_output_
8
voltage_min
loop_1_output_
9
# password has changed! Must unlock to change the low byte voltage_max
Telemetry_bw 0.0625V
Write new password high Byte to R/W high Byte Try register loop_2_output_
Write new password low Byte to low Byte Password register 10
voltage_min
# password change complete, status is locked loop_2_output_
11
# Need to write new low byte to Try register to unlock voltage_max
12 input_voltage_min
Pin Protection 760Hz 0.125V
13 input_voltage_max
The ADDR/PROTECT pin is a dual function pin. 14 temp1_min 1C
When the IC is enabled, the resistor value is latched and Telemetry_bw
15 temp1_max 1C
stored for use in the I2C address offset function.
16 temp2_min 1C
Thereafter, the pin acts entirely as a PROTECT pin. Telemetry_bw
17 temp2_max 1C
If enabled, the PROTECT pin must be driven high to
unlock and low to lock. If the resistor address offset
function is being used, care must be taken to allow the IC
to read the resistor value before driving the pin high or
AMD SVI2 MODE
low to set the security state. Failure to follow this When the power-on sequence is initiated, both rails
precaution may result in an erroneous address offset will ramp to the configured Vboot voltage and assert
value being latched in. The user should at least wait until the PWRGD on each loop. The soft-start occurs at the
the completion of the auto-trim time t4 in Figure 6. ½ or ¼ multiplier slew rate as selected in Table 51.

TABLE 51: SLEW RATES
FAST rate ½ Multiplier ¼ Multiplier

10 5.0 2.50
mV/µs 15 7.5 3.75
20 10 5.00
25 12.5 6.25
PWROK
The boot voltage is decoded from the SVC and SVD

levels when the EN pin is asserted high as shown in
Table 52. This value is latched and will be re-used in
the event of a soft reset (de-assertion and re-assertion
of PwrOK).
Note: VCC and VDDIO must be stable for a Figure 49: PWROK De-assertion
minimum 5ms before the IC is enabled to ensure
that the Boot voltage is decoded from the SVC, SVI2 Interface
SVD pins correctly.
The IR35201 implements a fully compliant AMD SVI2
TABLE 52: AMD SVI BOOT TABLE Serial VID interface (SVI). SVI2 is a three-wire
interface between a SVI2 compliant processor and a
Boot Voltage SVC SVD VR. It consists of clock, data, and telemetry/alert
1.1V 0 0 signals. The processor will send a data packet with
1.0V 0 1 the clock (SVC) and data (SVD) lines. This packet has
0.9V 1 0 SVI commands to change VID, go to a low power
state, enable and configure telemetry, change load
0.8V 1 1
line slope and change VID offset. The VR, when
configured to do so, will send telemetry to the
Alternatively, the AMD Boot voltage can be set by an processor. The telemetry data consists of voltage
MTP register instead of decoding the SVC, SVD pins only, or voltage and current of each output rail (VDD,
as shown in Table 53. Boot values are shown in Table VDDNB). The telemetry line (SVT) is also used as an
54. alert signal (VOTF complete) to alert the processor
when a positive going VID change in complete, or an
offset or load line scale change has occurred.
VID Change
TABLE 53: AMD BOOT OPTIONS The IR35201 accepts an 8-bit VID within the SVD
packet and will change the output voltage at the FAST
MTP Boot Register Boot Location
rate specified in Table 51 of one or both of the loops
Bit[7] = low Decode from SVC, SVD pins per Table 52 based on the VID in Table 54. This is a VID-on-the-fly-
Bit[7] = high Use MTP boot register bits [6:0] request (VOTF Request).
PWROK De-assertion
The IR35201 responds to SVI commands on the SVI
bus interface when PWROK is high. In the event that
PWROK is de-asserted the controller resets the SVI
state machine, drives the SVT pin high and returns to
the Boot voltage, initial load line slope and offset.

TABLE 54: SVI2 VID TABLE
0 1.55000 32 1.23750 64 0.92500 96 0.61250 C8 0.30000
1 1.54375 33 1.23125 65 0.91875 97 0.60625 C9 0.29375
2 1.53750 34 1.22500 66 0.91250 98 0.60000 CA 0.28750
3 1.53125 35 1.21875 67 0.90625 99 0.59375 CB 0.28125
4 1.52500 36 1.21250 68 0.90000 9A 0.58750 CC 0.27500
5 1.51875 37 1.20625 69 0.89375 9B 0.58125 CD 0.26875
6 1.51250 38 1.20000 6A 0.88750 9C 0.57500 CE 0.26250
7 1.50625 39 1.19375 6B 0.88125 9D 0.56875 CF 0.25625
8 1.50000 3A 1.18750 6C 0.87500 9E 0.56250 D0 0.25000
9 1.49375 3B 1.18125 6D 0.86875 9F 0.55625 D1 0.24375
A 1.48750 3C 1.17500 6E 0.86250 A0 0.55000 D2 0.23750
B 1.48125 3D 1.16875 6F 0.85625 A1 0.54375 D3 0.23125
C 1.47500 3E 1.16250 70 0.85000 A2 0.53750 D4 0.22500
D 1.46875 3F 1.15625 71 0.84375 A3 0.53125 D5 0.21875
E 1.46250 40 1.15000 72 0.83750 A4 0.52500 D6 0.21250
F 1.45625 41 1.14375 73 0.83125 A5 0.51875 D7 0.20625
10 1.45000 42 1.13750 74 0.82500 A6 0.51250 D8 0.20000
11 1.44375 43 1.13125 75 0.81875 A7 0.50625 D9 0.19375
12 1.43750 44 1.12500 76 0.81250 A8 0.50000 DA 0.18750
13 1.43125 45 1.11875 77 0.80625 A9 0.49375 DB 0.18125
14 1.42500 46 1.11250 78 0.80000 AA 0.48750 DC 0.17500
15 1.41875 47 1.10625 79 0.79375 AB 0.48125 DD 0.16875
16 1.41250 48 1.10000 7A 0.78750 AC 0.47500 DE 0.16250
17 1.40625 49 1.09375 7B 0.78125 AD 0.46875 DF 0.15625
18 1.40000 4A 1.08750 7C 0.77500 AE 0.46250 E0 0.15000
19 1.39375 4B 1.08125 7D 0.76875 AF 0.45625 E1 0.14375
1A 1.38750 4C 1.07500 7E 0.76250 B0 0.45000 E2 0.13750
1B 1.38125 4D 1.06875 7F 0.75625 B1 0.44375 E3 0.13125
1C 1.37500 4E 1.06250 80 0.75000 B2 0.43750 E4 0.12500
1D 1.36875 4F 1.05625 81 0.74375 B3 0.43125 E5 0.11875
1E 1.36250 50 1.05000 82 0.73750 B4 0.42500 E6 0.11250
1F 1.35625 51 1.04375 83 0.73125 B5 0.41875 E7 0.10625
20 1.35000 52 1.03750 84 0.72500 B6 0.41250 E8 0.10000
21 1.34375 53 1.03125 85 0.71875 B7 0.40625 E9 0.09375
22 1.33750 54 1.02500 86 0.71250 B8 0.40000 EA 0.08750
23 1.33125 55 1.01875 87 0.70625 B9 0.39375 EB 0.08125
24 1.32500 56 1.01250 88 0.70000 BA 0.38750 EC 0.07500
25 1.31875 57 1.00625 89 0.69375 BB 0.38125 ED 0.06875

26 1.31250 58 1.00000 8A 0.68750 BC 0.37500 EE 0.06250
27 1.30625 59 0.99375 8B 0.68125 BD 0.36875 EF 0.05625
28 1.30000 5A 0.98750 8C 0.67500 BE 0.36250 F0 0.05000
29 1.29375 5B 0.98125 8D 0.66875 BF 0.35625 F1 0.04375
2A 1.28750 5C 0.97500 8E 0.66250 C0 0.35000 F2 0.03750
2B 1.28125 5D 0.96875 8F 0.65625 C1 0.34375 F3 0.03125
2C 1.27500 5E 0.96250 90 0.65000 C2 0.33750 F4 0.02500
2D 1.26875 5F 0.95625 91 0.64375 C3 0.33125 F5 0.01875
2E 1.26250 60 0.95000 92 0.63750 C4 0.32500 F6 0.01250
2F 1.25625 61 0.94375 93 0.63125 C5 0.31875 F7 0.00625
30 1.25000 62 0.93750 94 0.62500 C6 0.31250 F6-FF OFF
31 1.24375 63 0.93125 95 0.61875 C7 0.30625

PSI[x]_L and TFN Load Line Slope Trim
PSI0_L is Power State Indicator Level 0. When this bit
The IR35201 has the ability for the processor to
is asserted the IR35201 will drop to 1 phase
depending on configuration. This will only occur if the change the load line slope of each loop independently
output current is low enough (typically <20A) to enter through the SVI2 bus while ENABLE and PWROK are
PSI0, else the VR will remain in full phase operation. asserted via the serial VID interface. The slope
change applies to initial load line slope as set by the
PSI1_L is Power State Indicator Level 1. When this bit external RCSP/RCSM resistor network. The load line
is asserted along with the PSI0_L bit, the IR35201 will slope can be disabled or adjusted by -40%, -20%, 0%,
enter diode emulation mode. This will only occur if the +20%, +40%, +60%, or +80%.
output current is low enough (typically <5A) to enter
PSI1, else the VR will enter PSI0_L mode of Offset Trim
operation.
The IR35201 has the ability for the processor to
change the offset of each loop independently while
TFN is an active high signal that allows the processor
ENABLE and PWROK are asserted via the serial VID
to control the telemetry functionality of the VR. If
interface. The offset can be left unchanged, disabled,
TFN=1, then the VR telemetry will be configured per
or changed +25mV or -25mV.
Table 55.
TABLE 55: TFN TRUTH TABLE Ispike/Dual OCP Support
VDD, VDDNB Domain The IR35201 has two current limit thresholds. One
Meaning threshold is for short duration current spikes (Fast
Selector bit
0, 0 Telemetry is in voltage only mode. OCP). When this threshold, typically a percentage
Telemetry is in voltage
above the peak processor current, is exceeded, the
0, 1 VR quickly shuts down. The other threshold, typically
& current mode.
1, 0 Telemetry is disabled. a percentage above the thermal design current (TDC),
1, 1 Reserved.
is heavily filtered (Slow OCP) and shuts down the VR
when the average current exceeds it. To meet AMD
specifications, exceeding both thresholds will assert
SVT Telemetry
the OCP_L (VR_HOT) pin and delay the over-current
shut down by 10usec for FAST threshold and 20usec
The IR35201 has the ability to sample and report
for the SLOW threshold, typically. Figure 50 and
voltage and current for the VDD and VDDNB
domains. The IR35201 reports this telemetry serially Figure 51 show the delay action of the OCP shutdown
over the SVT wire which is clocked by the processor with the OCP_L (VR_HOT) and PWRGD pins.
driven SVC. If in voltage-only telemetry mode then the
sampled voltage for VDD and VDDNB are sent Over-current
together in every SVT telemetry packet at a rate of detected
20kHz. If in voltage and current mode then the Vdd
sampled voltage and current for VDD is sent out in

one SVT telemetry packet followed by the sampled Idd
voltage and current for VDDNB in the next SVT
OCP Delay
telemetry packet at a rate of 40kHz. The voltage and (fast)
current are moving averages based on the filters and OCP_L
update rates specified in the Electrical Specification
Table. The voltage is reported as a function of the Set VR shuts
PG
VID minus Iout times the Load Line Resistance. The down
current is reported as a percentage of the Icc_max
register, where a value of FFh represents 100% and
00h represents 0% of the Icc_max setting. Resolution
of the current reporting is 0.39% (1/256).
Figure 50: OCP_L (VR_HOT) assertion with
OCP_spike (Fast) threshold. OCP delay action (11usec)

Over-current
detected
Vdd
Idd
OCP Delay
(slow)
OCP_L
PG VR shuts
down
Figure 51: OCP_L (VR_HOT) assertion with

OCP_TDC (Slow) threshold. OCP delay action (22usec)
Thermal Based Protection

The IR35201 can also assert the PROC_HOT_L
(VR_HOT) pin when the temperature of the VR
exceeds a configurable temp_max threshold (typically
100⁰ C). If the temperature continues to rise and
exceeds a second configurable threshold
(OTP_thresh) then the VR will shut down and latch
off. The VR can only be restarted if ENABLE or VCC
is cycled.
AMD SVI Address Programming

By default, loop 1 is addressed as the VDD rail and
loop 2 is addressed as the VDDNB rail which is
sufficient for most applications. The IR35201 however,
can also be configured with a single bit change to
swap this addressing scheme so that loop 1 can be
addressed as the VDDNB rail and loop 2 can be
addressed as the VDD rail. This is for application
where the VDDNB requires more than two phases
and VDD only requires two.

I2C PROTOCOLS
All registers may be accessed using either I2C or PMBus protocols. I2C allows the use of a simple format
whereas PMBus provides error checking capability. Figure 52 shows the I2C format employed by the IR35201.
Figure 52: I2C Format
PMBUS PROTOCOLS
To access IR’s configuration and monitoring registers, 4 different protocols are required:
 the PMBus Send Byte protocol with/without PEC (for CLEAR_FAULTS only)
 the PMBus Read/Write Byte/Word protocol with/without PEC (for status and monitoring)
 the PMBus Block Read and Block Write protocols with Byte Count = 1 and Byte Count = 2
 the PMBus Block Read Process call (for accessing Configuration Registers)
An explanation of which command codes and protocols are required to access them is given in Table 6.
In addition, the IR35201 supports:
 Alert Response Address (ARA)
 Bus timeout (30ms)
 Group Command for writing to many VRs within one command

LEGEND:
Figure 53: PMBus Send Byte
Figure 54: PMBus Write Byte/Word
Figure 55: PMBus Read Byte/Word

Figure 56: PMBus Block Read with Byte Count=1
Figure 57: PMBus Block Read with Byte Count=2
Figure 58: PMBus Block Write with Byte Count=1
Figure 59: PMBus Block Write with Byte Count=2
Figure 60: MFR_WRITE_REG
PMBus Command Register

S Address
W A D0h
A Address
A
...
PMBus Address+1
Sr Address
R A Data Byte A Data Byte
A* PEC* N P
Figure 61: MFR_READ_REG
PMBus
S Address
W A Command A 1 A Command A ...
PMBus
Sr Address R A 1 A Data Byte A* PEC* N P
Figure 62: Block Read Process Call

Figure 63: Group Command
TABLE 56: PMBUS COMMANDS
PMBUS COMMAND
COMMAND DESCRIPTION
PROTOCOL CODE
Enables or disables the output and controls margining.

OPERATION Read/Write Byte 01h
Ignores OVP on Margin High, UVP on Margin Low.
Configures the combination of CONTROL pin and
ON_OFF_CONFIG Read/Write Byte 02h
OPERATION command needed to turn the unit on and off.
CLEAR FAULTS Send Byte 03h Clear contents of Fault registers
WRITE_PROTECT Read/Write Byte 10h Provides protection from accidental changes
RESTORE_DEFAULT_ALL Send Byte 12h Reloads the OTP

Returns 1010xxxx to indicate Packet Error Checking is
CAPABILITY Read Byte 19h
supported and Maximum bus speed is 400kHz
Set to prevent warning or fault conditions from asserting the
Block Write/ Block SMBALERT# signal. Write command code for STATUS
SMBALERT_MASK 1Bh register to be masked in the low byte, the bit to be masked
Read Process Call
in the High byte.
Sets the format for VOUT related commands.

VOUT_MODE Read/Write Byte 20h
Linear mode, -8 and -9 exponents supported.
Sets the voltage to which the device should set the output.
VOUT_COMMAND Read/Write Word 21h
Format according to VOUT_MODE.
Applies a fixed offset to the output voltage command value.
VOUT_TRIM Read/Write Word 22h
Sets an upper limit on the output voltage the unit can
VOUT_MAX Read/Write Word 24h
command. Format according to VOUT_MODE.
Sets the margin high voltage when commanded by
VOUT_MARGIN_HIGH Read/Write Word 25h OPERATION. Must be in format determined by
VOUT_MODE.
Sets the margin low voltage when commanded by
VOUT_MARGIN_LOW Read/Write Word 26h OPERATION. Must be in format determined by
VOUT_MODE.
Sets the rate at which the output changes voltage due to

VOUT_TRANSITION_RATE Read/Write Word 27h VOUT_COMMAND or OPERATION commands.
mV/s; exp = [0.-1,-2,-3,-4]
Sets the rate at which the output voltage decreases or
increases with increasing or decreasing output current for
VOUT_DROOP Read/Write Word 28h
use with Adaptive Voltage Positioning.
VOUT_SCALE_LOOP Read/Write Word 29h Sets the gain of the output voltage sensing circuitry to take

PMBUS COMMAND
COMMAND DESCRIPTION
PROTOCOL CODE
into account an external resistor divider.
Fixed to E8 08h
Sets the switching frequency in KHz per table found in user
FREQUENCY_SWITCH Read/Write Word 33h
note UN00044. Exp = 0, 1
Sets the value of the input voltage at which the unit should
VIN_ON Read/Write Word 35h
begin power conversion. Exp = -1.
Sets the value of the input voltage that the unit, once
VIN_OFF Read/Write Word 36h operation has started, should stop power conversion.
Exp = -1.
Used to null out any offsets in the output current sensing
IOUT_CAL_OFFSET Read/Write Word 39h
circuitry. Exp = -2.
Returns the value of the output voltage, measured at the
VOUT_OV_FAULT_LIMIT Read Only 40h sense or output pins, that causes an output overvoltage
fault.
Instructs the device on what action to take in response to an
VOUT_OV_FAULT_RESPONSE Read/Write Byte 41h output overvoltage fault. Only shutdown and ignore are
supported.
Sets the value of the output voltage, measured at the sense
VOUT_OV_WARN_LIMIT Read/Write Word 42h or output pins, that causes an output overvoltage warning.
Format as determined by VOUT_MODE.
Sets the value of the output voltage, measured at the
VOUT_UV_WARN_LIMIT Read/Write Word 43h sense or output pins, that causes an output voltage low
warning. Format as determined by VOUT_MODE.
Returns the value of the output voltage, measured at the

VOUT_UV_FAULT_LIMIT Read Only 44h sense or output pins, that causes an output undervoltage
fault.
Instructs the device on what action to
VOUT_UV_FAULT_RESPONSE Read/Write Byte 45h take in response to an output undervoltage fault.
Only shutdown and ignore are supported.
Sets the value of the output current, in amperes, that causes
the overcurrent detector to indicate an overcurrent fault
IOUT_OC_FAULT_LIMIT Read/Write Word 46h
condition. Set by writing this command in Linear format with
a -1 exponent.
output overcurrent fault.
IOUT_OC_FAULT_RESPONSE Read/Write Byte 47h
Only C0h (shutdown immediately), F8h (hiccup forever), and
D8 (hiccup 3 times) are supported.
Sets the value of the output current that causes an output

IOUT_OC_WARN_LIMIT Read/Write Word 4Ah overcurrent warning. Set by writing this command in Linear
format with a -1 exponent.
Sets the temperature, in degrees Celsius, of the unit at
OT_FAULT_LIMIT Read/Write Word 4Fh which it should indicate an overtemperature fault.
Exp = 0.

OT_FAULT_RESPONSE Read/Write Byte 50h overtemperature fault. Only shutdown and ignore are
supported.
Sets the temperature, in degrees Celsius, of the unit at
OT_WARN_LIMIT Read/Write Word 51h which it should indicate an Overtemperature Warning alarm.
Exp = 0.
Sets the value of the input voltage that causes an input
VIN_OV_FAULT_LIMIT Read/Write Word 55h
overvoltage fault. Exp = -4.

PMBUS COMMAND
COMMAND DESCRIPTION
PROTOCOL CODE
VIN_OV_FAULT_RESPONSE Read/Write Byte 56h input overvoltage fault. Only shutdown and ignore are
supported.
Sets the value of the input voltage that causes an input
VIN_UV_WARN_LIMIT Read/Write Word 58h
voltage low warning. Exp = -4.
Sets the value of the input current, in amperes,
IIN_OC_WARN_LIMIT Read/Write Word 5Dh that causes a warning that the input current is high.
Exp = -1.
Sets the output voltage at which an optional
POWER_GOOD_ON Read/Write Word 5Eh POWER_GOOD signal should be asserted.
Sets the output voltage at which an optional
POWER_GOOD_OFF Read/Write Word 5Fh POWER_GOOD signal should be negated.
Sets the time, in milliseconds, from when a start condition is
TON_DELAY Read/Write Word 60h received (as programmed by the ON_OFF_CONFIG
command) until the output voltage starts to rise. Exp = 0.
Sets the time, in milliseconds, from when the output starts to
TON_RISE Read/Write Word 61h rise until the voltage has entered the regulation band.
Exp = 0.
Sets an upper limit, in milliseconds, on how
TON_MAX_FAULT_LIMIT Read/Write Word 62h long the unit can attempt to power up the output without
reaching the output undervoltage fault limit. Exp = 0.
Instructs the device on what action to take in response to a
TON_MAX_FAULT_RESPONSE Read/Write Byte 63h
TON_MAX fault. Only shutdown and ignore are supported.
Sets the time, in milliseconds, from when a stop condition is
received (as programmed by the ON_OFF_CONFIG
TOFF_DELAY Read/Write Word 64h
command) until the unit stops transferring energy to the
output. Exp = 0.
Sets the time, in milliseconds, from the end of the turn-off
TOFF_FALL Read/Write Word 65h
delay time until the voltage is commanded to zero. Exp = 0.
Returns 1 byte where the bit meanings are:
Bit <7> Reserved
Bit <6> Output off (due to fault or enable)
Bit <5> Output over-voltage fault
STATUS_BYTE Read/Write Byte 78h Bit <4> Output over-current fault
Bit <3> Input Under-voltage fault
Bit <2> Temperature fault
Bit <1> Communication/Memory/Logic fault
Bit <0>: Reserved
Returns 2 bytes where the Low byte is the same as the
STATUS_BYTE data. The High byte has bit meanings are:
Bit <7> Output high or low fault
Bit <6> Output over-current fault
STATUS_WORD Read/Write Word 79h
Bit <5> Input under-voltage fault
Bit <4> MFR_SPECIFIC
Bit <3> POWER_GOOD#
Bit <2:0> Reserved
Bit <7> Output Overvoltage Fault
STATUS_VOUT Read/Write Byte 7Ah Bit <6> Output Overvoltage Warning
Bit <5> Output Undervoltage Warning

PMBUS COMMAND
COMMAND DESCRIPTION
PROTOCOL CODE
Bit <4> Output Undervoltage Fault
Bit <3> VOUT_MAX Warning
Bit <2> TON_MAX_FAULT
Bit <1> Reserved
Bit <0> Reserved
Bit <7> Output Overcurrent Fault
Bit <6> Reserved
Bit <5> Output Overcurrent Warning
STATUS_IOUT Read/Write Byte 7Bh
Bit <4> Reserved
Bit <3> Current Share Fault
Bit <2:0> Reserved
Bit <7> Input Overvoltage Fault
Bit <6> Reserved
Bit <5> Input Undervoltage Warning
Bit <4> Input Undervoltage Fault
STATUS_INPUT Read/Write Byte 7Ch
Bit <3> Unit Off For Insufficient Input Voltage
Bit <2> Reserved
Bit <1> Input Overcurrent Warning
Bit <0> Reserved
Bit <7> Over Temperature Fault
STATUS_TEMPERATURE Read/Write Byte 7Dh Bit <6> Over Temperature Warning
Bit <5:0> Reserved
Bit <7> Invalid or unsupported command
Bit <6> Invalid or unsupported data
STATUS_CML Read/Write Byte 7Eh Bit <5> PEC fault
Bit <4:2> Reserved
Bit <1> Other communication fault not listed here
Bit <0> Reserved
Bit <7:4> Reserved
Bit <3> Loss of SYNC
STATUS_MFR_SPECIFIC Read/Write Byte 80h
Bit <2> Driver Fault
Bit <1> Unpopulated Phase
Bit <0> External Overtemperature Fault
READ_VIN Read Word 88h Returns the input voltage in Volts
READ_IIN Read Word 89h Returns the input current in Amperes
Returns the output voltage in the format set by
READ_VOUT Read Word 8Bh
VOUT_MODE
READ_IOUT Read Word 8Ch Returns the output current in Amperes
Returns the addressed loop NTC temperature in degrees
READ_TEMPERATURE_1 Read Word 8Dh
Celsius
READ_TEMPERATURE_2 Read Word 8Eh Returns the other loop NTC temperature in degrees Celsius
Returns the duty cycle of the PMBus device’s main
READ_DUTY_CYCLE Read Word 94h
power converter in percent.
READ_POUT Read Word 96h Returns the output power in Watts
READ_PIN Read Word 97h Returns the input power in Watts
Reports PMBus Part I rev 1.1 & PMBUs
PMBUS_REVISION Read Byte 98h
Part II rev 1.2(draft)
MFR_ID Block Read/Write 99h The MFR_ID is set to IR (ASCII 52 49) unless programmed

PMBUS COMMAND
COMMAND DESCRIPTION
PROTOCOL CODE
Byte count = 2 different in the USER registers of the controller.
The MFR_Model is the same as the device ID if the USER
Block Read, register for Manufacturer model is 00. Otherwise
MFR_MODEL 9Ah
byte count = 1 MFR_Model command returns the value in the USER
register for MFR_Model.
The MFR_Revision is the same as the device revision if the
Block Read, USER register for Manufacturer revision is 00. Otherwise
MFR_REVISION 9Bh
byte count = 2 MFR_Revision command returns the value in the USER
register for MFR_Revison.
Block Read/Write The MFR_DATE command returns the value in the USER
MFR_DATE 9Dh register called MFR_DATE
Byte count = 2
Returns a 1 byte code with the following values:
IC_DEVICE_ID Block Read ADh
4D = IR35201
IC_DEVICE_REV Block Read AEh The IC revision that is stored inside the IC
Custom MFR Read I2C registers
MFR_READ_REG D0h
protocol
MFR_WRITE_REG Write Word D1h Write to I2C registers, High Byte is reg, low byte is data

11-BIT LINEAR DATA FORMAT
Monitored parameters use the Linear Data Format (Figure 64) encoding into 1 Word (2 bytes), where:
Value Y  2N
Note: N and Y are “signed” values.
Databyte High Databyte Low
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
N Y
Figure 64: 11-bit Linear Data Format
16-BIT LINEAR DATA FORMAT

This format is only used for VOUT related commands (READ_VOUT, VOUT_MARGIN_HIGH,
VOUT_MARGIN_LOW, VOUT_COMMAND):
Value Y  2N
Note: N is a “signed” value. If VOUT is set to linear format (by VOUT_MODE), then N is set by the VOUT_MODE
command and only Y is returned in the data-field as a 16-bit unsigned number.
Figure 65: 16-bit Linear Data Format

SVID REGISTERS
A list of all the SVID registers is given in Table 57. SVID registers supported by IR35201 in VR12.5 and IMVP8 mode conform
to VR12.5 and IMVP8 specifications respectively.
Table 57: SVID Registers
Register
Register Name Access VR12.5 Mode IMVP8 Mode
Address
00 Vendor ID RO Supported Supported
01 Product ID RO Supported Supported
02 Product Revision RO Supported Supported
03 Product Date Code - Not Supported Not Supported
04 Lot Code - Not Supported Not Supported
05 Protocol ID RO Supported Supported
06 Capability RO Supported Supported
07 Vendor-Timeout RW Supported Supported
08 Vendor Use RO Supported Supported
09 Vendor Use - Not Supported Not Supported
0A Vendor Use - Not Supported Not Supported
0B Vendor Use - Not Supported Not Supported
0C Vendor Use - Not Supported Not Supported
Supported, For Supported, For
0D Vendor Use RO
Factor Use Only Factor Use Only
0E Vendor Use RW
0F Vendor Use RW
10 Status_1 RO Supported Supported
11 Status_2 RO Supported Supported
12 Temperature Zone RO Supported Supported
13 Reserved - Not Supported Not Supported
14 Reserved - Not Supported Not Supported
15 Output Current RO Supported Supported
16 Output Voltage RO Supported Supported
17 VR Temperature RO Supported Supported
18 Output Power RO Supported Supported
19 Input Current RO Supported Supported
1A Input Voltage RO Supported Supported
1B Input Power RO Supported Supported
1C Status 2 Last Read RO Supported Supported
1D Future Command - Not Supported Not Supported
1E Future Command - Not Supported Not Supported
1F Future Command - Not Supported Not Supported
20 Future Command - Not Supported Not Supported
21 ICC Max RO Supported Supported
22 Temp Max RO Supported Supported
23 DC_LL RO Supported Supported
24 SR_Fast RO Supported Supported
25 SR_Slow RO Supported Supported
26 Vboot RO Supported Supported
27 VR Tolerance - Not Supported Not Supported
28 Current-Offset RO Supported Supported
29 Temperature Offset RO Supported Supported
2A Slow Slew Rate Select RO Not Supported Supported
2B PS4 Exit Latency RO Not Supported Supported
2C PS3 Exit Latency RO Not Supported Supported
2D Enable to Ready RO Not Supported Supported

Register
Register Name Access VR12.5 Mode IMVP8 Mode
Address
2E Pin Max RO Not Supported Supported
2F Pin Alert Threshold RW Not Supported Supported
30 VOUT Max RW Supported Supported
31 VID Setting RW Supported Supported
32 Pwr State RW Supported Supported
33 Offset RW Supported Supported
34 Multi VR Config RW Supported Supported
35 Set RegADR RW Supported Supported
3A Work Point 0 RW Not Supported Not Supported
3B Work Point 1 RW Not Supported Not Supported
3C Work Point 2 RW Not Supported Not Supported
3D Work Point 3 RW Not Supported Not Supported
3E Work Point 4 RW Not Supported Not Supported
3F Work Point 5 - Not Supported Not Supported
40 Work Point 6 - Not Supported Not Supported
41 Work Point 7 - Not Supported Not Supported
42 IVID1-VID RW Not Supported Supported
43 IVID1-I RW Not Supported Supported

MARKING INFORMATION
PIN 1
PART # 35201
ASSEMBLER (A)/DATE(YWW)/MARKING CODE(X) AYWWX
LOT CODE XXXXX
(ENG MODE - MIN. LAST 5 DIGITS OF EATI #)
(PROD MODE – 4 DIGIT SPN CODE)
Figure 66: Package Marking
PACKAGE INFORMATION
QFN 7x7mm, 56-pin
Figure 67: Package Dimensions

ENVIRONMENTAL QUALIFICATIONS
Qualification Level Industrial
Moisture Sensitivity Level QFN package MSL2
Machine Model JESD22-A115-A
Human Body Model JESD22-A114-E

ESD
Charged Device Model JESD22-C101-C
Latch-up JESD78
RoHS Compliant Yes
† Qualification standards can be found at International Rectifier web site: http://www.irf.com

†† Exceptions to AEC-Q101 requirements are noted in the qualification report.

Data and specifications subject to change without notice.

This product will be designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
www.irf.com

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8+0/7+1/6+2 Dual Output Digital Multi-Phase Controller IR35201

IR35201 56-pin, QFN 7 mm x 7 mm Tape and Reel 3000 IR35201MxxyyTRP1

IR35201 56-pin, QFN 7 mm x 7 mm Tape and Reel 3000 IR35201MTRPBF

IR35201 56-pin, QFN 7 mm x 7 mm Tray 4900 IR35201MTYPBF

1 www.irf.com | © 2016 International Rectifier February 8, 2015 | V1.6

P/PBF – Lead Free

TR – Tape & Reel / TY - Tray

Package Type (QFN)

Figure 1: IR35201 Pin Diagram

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Figure 2: IR35201 Block Diagram

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PIN# PIN NAME TYPE PIN DESCRIPTION

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PIN# PIN NAME TYPE PIN DESCRIPTION

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PIN# PIN NAME TYPE PIN DESCRIPTION

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RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN

Recommended Operating Ambient Temperature Range -40°C to 85°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

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Input High Voltage 0.7 - - V

Input High Voltage 0.65 - - V

Input High Voltage 2.1 - - V

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Open-Drain Outputs – 20mA Drive VR_HOT_ICRIT#, SV_DIO, SV_ALERT#, PIN_ALERT#

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The IR35201 can also be used with Rdson current

The VID decoder receives a VID code from the CPU

The internal high-precision voltage reference supplies

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The IR35201 supports the Packet Error Checking

The PowIRCenter GUI allows real-time design

The IR PowIRCenter GUI also allows access to the

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The functionality for each operating mode is

TABLE 1: MODE SELECTION

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Figure 7: Vcc 3.3V decoupling

The CFILT pin must have a 1µF, X5R type decoupling

Figure 8: CFILT decoupling

The IR35201 is designed to accommodate a wide

VAUX on and off thresholds are defined as:

TABLE 2: VINSEN TURN-ON/OFF VOLTAGE RANGE VAUX_on = VAUXSEN_on*(1+R1/R2)

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TABLE 8: VBOOT RANGE

Loop Boot Voltage

The SVID address of the IR35201 defaults to 0. This

Figure 12: Enable-based Shutdown

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IMVP8 mode is selectable via MTP bit. The boot

Intel Reporting Offsets Loop Start-Up Sequence and Delay

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Figure 13: MPoL Startup