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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY

COMPUTER SCIENCE & INFORMATION TECHNOLOGY DEPARTMENT
BS (Computer Science)

COURSE INFORMATION SHEET

(For Lab Based Course)
Session: Spring-2024
Course Title: Digital Logic Design
Course Code: CS-128L
Credit Hours: 1
Semester: 2nd
Pre-Requisites: None
Instructor Name: Faisal Rasheed Yazdanie, S.M Fazal-ul-Karim
[email protected]; HS-10 (Cubical – 02)
Email and Contact Information:
[email protected]; HT-14 (Cubical – 03)
WhatsApp Group -
Office Hours: Wednesday & Thursday (8:30 AM to 12:30 pm)
Mode of Teaching: Synchronous/Asynchronous/ Hybrid/Blended

LAB OBJECTIVE:

The laboratory objective is to introduce students with basic digital logic design concepts and to
implement them as well. The topics include number systems, codes, Boolean algebra,
combinational logic, arithmetic, MSI logic circuits, latches/flip flops, counters/registers,
sequential circuit design, memory devices and digital electronics.
This Lab course will be conducted both by practical implementation of circuits on breadboard as
well as on latest Trainers (Hardware based) along with circuit simulation using simulation
software such as Logic works 5 (Software Based) as an option.

COURSE OUTLINE:

Introduction to Digital Electronics and Equipment, Verifying the construction and working of
Basic Logic Gates (AND, OR, NOT), Verifying the construction and working of Universal Gates
(NAND, NOR) and also verifying the construction and working of Bubbled AND and Bubbled
OR Gates (Negative AND & Negative OR), Implementing Standard and Complex Boolean
Expression, Construction and working of Exclusive OR Gates (XOR Gates) and Exclusive NOR
Gates (X-NOR), Verifying the operational logic 4 bit and 8-bit binary Parallel Adder and Parity
Generator, S-R Latches, J-K Master Slave Flip Flop, Binary Ripple Counter.

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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
COMPUTER SCIENCE & INFORMATION TECHNOLOGY DEPARTMENT
BS (Computer Science)
COURSE LEARNING OUTCOMES:

CLO # Course Learning Outcomes (CLOs) Bloom’s Taxonomy

Follow the instructions to develop comprehensive understanding P3
1
of the basic concepts of digital circuits (Guided Response)

2 Integrate a team to develop a technical project which will be A3 (Organization)

assessed through demonstration and viva

RELATIONSHIP BETWEEN ASSESSMENT TOOLS AND CLOS:

Assessment Tools CLO-1 (40) CLO-2 (10)

Lab Manual 37.5% (15) -
Subject Project 25% (10) 50% (05)
Lab Exam 37.5% (15) 50% (05)

GRADING POLICY:

Assessment Tools Percentage Marks

Lab Manual 30% 15
Viva/ Project Demonstration 30% 15
Lab Exam 40% 20
TOTAL 100% 50

Recommended Books:

 Thomas L Floyd, Digital Fundamentals, Pearson, Latest Edition.

Reference Books:

 M. Morris Mano, Digital Logic and Computer Design, Published by Prentice Hall, Latest
Edition.

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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
COMPUTER SCIENCE & INFORMATION TECHNOLOGY DEPARTMENT
BS (Computer Science)
COURSE BREAKDOWN WITH LAB SYNCHRONIZATION:

- Both sides same Colours: Lab is synchronized with the topic

- Red Color: Lab is not synchronized (conducted before theory)
- No Color: Lab is to introduce new hardware or software skill /
Open Ended Lab / Lab is relevant to a topic taught in
pre-requisite and required for upcoming labs.

Week Topics Laboratory Synchronization

No.
Week 1 Introduction to Digital Electronics,
& Equipment.

Basic Logic Gates

a. 2-input AND gate, OR gate,
Introductory Digital Concepts, Digital NAND gate, NOR gate.
and Analog quantities, Binary Digits, b. Bubbled AND, and Bubbled
Logic Levels, Basic logic gates, Boolean OR
function, truth tables. c. 2 input XOR, XNOR and
design gates with AND, OR and NOT
gate.
d. Verify NOT gate and also
implement NOT gate with XOR gate.

Week 2 Digital waveforms, Two and three input Combinational Logic Circuits with
NAND and NOR gates. Number systems NAND and NOR Gates
and operations, Decimal Numbers, Binary
Numbers, Decimal to binary conversion
& vice versa. Octal Numbers, Octal
number conversions, Practice Questions
and Examples
Week 3 Hexadecimal Numbers, Hexadecimal Implementing Boolean Function
number conversions, Practice Questions using Logic Gates
and Examples. Binary Arithmetic
Operations, 1’s and 2’s complements of
Binary Numbers, Practice Questions and
Examples.
Week 4 Octal Arithmetic Operations, Practice Boolean Algebra
Questions and Examples, Hexadecimal
Arithmetic Operations, Practice Questions
and Examples. Two and three input
NAND and NOR gates, Bubbled AND &
OR gates.
Week 5 Exclusive OR and Exclusive NOR gates. Binary Adder
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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
COMPUTER SCIENCE & INFORMATION TECHNOLOGY DEPARTMENT
BS (Computer Science)
Truth Tables and waveform analysis of
different gates.
Practice Questions related to constructing
Truth Tables and Analyzing Waveforms
Week 6 Boolean operations, Boolean Laws, Scenario Based Circuit Design
Verification of Boolean Laws. Boolean
Rules and their verification.
Standard forms of Boolean expressions,
De Morgan’s Theorems.

Week 7 Simplification of Boolean Expressions Comparator and Parity Generator

using Boolean Algebra and Verification
Using truth tables, Basic Combinational
logic circuits.
Implementing Combinational Logic, The
Universal property of NAND Gates
Week 8 MID TERM EXAMINATION MID TERM EXAMINATION
Week 9 The Universal property of NOR Gates, Multiplexers
SOP & POS expressions.
Standard and Non-Standard SOP and
POS, Converting Non-Standard SOP
standard forms.
Week 10 Constructing Truth Tables of SOP and Encoder and Decoder
POS expressions.
Converting SOP to POS and vice versa,
Practice Questions and Examples related
to SOP and POS.Half and Full adder
circuits.
Week 11 Half and Full subractor circuits S-R Latches, Gated S-R Latches and
Karnaugh’s Map, Plotting Karnaugh’s D Latches
Map for 2, 3, and 4 Variables, 2&3
variable Karnaugh map, Simplification of
SOP & POS using K-map
4 variable Karnaugh’s Map,
Simplification of Standard Boolean
expressions SOP and POS using
Karnaugh’s Map, Related problems
Week 12 Converting SOP to POS and vice versa Initialization of the Flip-Flop using
using Karnaugh’s Map, Practice Asynchronous Inputs
Questions related to K-map.
Week 13 , Comparators Encoders, Decoders JK Master Slave Flip Flop
Multiplexers, De-Multiplexers,
Introduction to Sequential Circuits.

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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
COMPUTER SCIENCE & INFORMATION TECHNOLOGY DEPARTMENT
BS (Computer Science)
Difference between Combinational and
Sequential Logic.

Week 14 Flip-Flops and related devices, Latches, MOD-10 COUNTER

Active-High Input S-R Latch, Active- Binary Ripple Counter
Low Input Latch.
Operation, Working, Truth Table,
Waveform Analysis of S-R Latch, Gated
S-R Latch, Operation, Working, Truth
Table, Waveform Analysis
Week 15 Gated-D latch, Operation, Working, Truth 4 Bit Serial-In/Serial Out Shift
Table, Waveform Analysis. Flip-Flop Register
Applications.
Serial-in/Serial-out Shift Registers,
Serial-in/Parallel-out Shift Registers.
Parallel-in/Serial-out Shift Registers,
Shift Register applications
Week 16 2-Bit Asynchronous Binary Counter Final Lab / VIVA
Asynchronous Decade counter
3-Bit Synchronous Binary Counter
4-Bit Synchronous Decade Counter

LAB PLAN
Course Title: Digital Logic Design Lab
Course Code: CS-128L
Week Required
Lab Date Objective
No. Reading
12-03-2024 to Introduction to Digital Electronics & Equipment.
1 Lab Manual
17-03-2024 Basic Logic Gates
18-03-2024 to Combinational Logic Circuits with NAND and NOR
2 Lab Manual
24-03-2024 Gates
25-03-2024 to
3 Implementing Boolean Function using Logic Gates Lab Manual
31-03-2024
01-04-2024 to Boolean Algebra
4 Lab Manual
07-04-2024
08-04-2024 to
5 Binary Adder Lab Manual
14-04-2024

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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
COMPUTER SCIENCE & INFORMATION TECHNOLOGY DEPARTMENT
BS (Computer Science)
6 15-04-2024 to
Scenario Based Circuit Design Lab Manual
21-04-2022
22-04-2024 to
7 Comparator and Parity Generator Lab Manual
28-04-2024
29-04-2024 to
8 Multiplexers Lab Manual
05-04-2024
Midterm Examination
10
(05-05-2024 to 11-05-2024)
13-05-2024 to
9 Encoder and Decoder Lab Manual
19-05-2024
20-05-2024 to
11 S-R Latches, Gated S-R Latches and D Latches Lab Manual
26-05-2024
27-05-2024 to Initialization of the Flip-Flop using Asynchronous
12 Lab Manual
02-06-2024 Inputs
03-06-2024 to
13 JK Master Slave Flip Flop Lab Manual
09-06-2024
10-06-2024 to MOD-10 COUNTER
14 Lab Manual
16-06-2024 Binary Ripple Counter
17-06-2024 to 4 Bit Serial-In/Serial Out Shift Register
15
23-06-2024 Lab Manual
24-06-2024 to Open Ended Lab
16 Lab Manual
30-06-2024
01-07-2024 to Project Demonstrations
17
07-07-2024
Final Lab Examination
18
(08-07-2024 to 12-07-2024)

Teacher’s Name __________________________________ Date: ___________________

and Signature:

Chairperson’s Name _______________________________ Date: ___________________

and Signature:

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