Sequential Circuits

 Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements

 Synchronous
Inputs Outputs
Combinational
Circuit
Flip-flops
Clock

0
 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0

R
0 0
Q

S Q
0 1

Initial Value

4
 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

R
0 1
Q

S Q
0 0

5
 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 0
Q

S Q
0 1

6
 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 1 0 1 1 0 1 Q=0
Q

S Q
0 0

7
 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 0 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1

S Q
1 1

8
 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 1 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1
1 0 1 1 0 Q=1

S Q
1 0

9
 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 0 0 1 1 0 1
Q=0
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 10

10
 Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 10 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’
S Q
1 0

11
 Latches

 SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S R Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set
1 0 0 Reset
R Q
1 1 Q0 No change
12
 Latches

 SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S’ R’ Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set
Q 1 0 0 Reset
R Q0 No change
1 1
13
 Controlled Latches

 SR Latch with Control Input

R R S S
Q Q
C C
S Q R Q
S R

C S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q’ Invalid
15
 Controlled Latches

 D Latch (D = Data) Timing Diagram

S
C
D
Q
C D
R Q
Q

t
C D Q
Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set

16
 Controlled Latches

 D Latch (D = Data) Timing Diagram

S
C
D
Q
C D
R Q
Q

C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set

17
Advantages of edge triggering:
FF change states only once for a clock cycle
 Flip-Flops

 Controlled latches are level-triggered

 Flip-Flops are edge-triggered

CLK Positive Edge

CLK Negative Edge

22
 J-K Flip-Flop

S S
Q
C
R Q
R

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Mesra
 Flip-Flops

 JK Flip-Flop

J
D Q Q
K
CLK Q Q

J Q
D = JQ’ + K’Q
K Q
24
 Flip-Flops

 T Flip-Flop

T J Q T D Q

Q
K Q

T Q
D = JQ’ + K’Q
D = TQ’ + T’Q = T  Q Q

25
Y=1
Y’=0
Master Slave J-K Flip-Flop

33
 Flip-Flops

 Master-Slave D Flip-Flop
D D Q D Q Q
D Latch D Latch
(Master) (Slave)
C C

Master Slave
CLK
CLK

D
Looks like it is negative
edge-triggered QMaster

QSlave
34
Flip-Flop Characteristic Tables

D Q D Q(t+1)
0 0 Reset
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle

T Q T Q(t+1)
0 Q(t) No change
Q
1 Q’(t) Toggle
35
Flip-Flop Characteristic Equations

D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t) Q(t+1) = T  Q
Q
1 Q’(t)
36
 Flip-Flop Characteristic Equations

 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 Reset
0 1 1
K Q
1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1

37
 Flip-Flop Characteristic Equations

 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1

38
 Flip-Flop Characteristic Equations

 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 1 Set
1 0 1 1
1 1 0 Toggle
1 1 1

39
 Flip-Flop Characteristic Equations

 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 1 Set
1 0 1 1
1 1 0 1 Toggle
1 1 1 0

40
 Flip-Flop Characteristic Equations

 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
J Q 0 0 1 1 K
0 1 0 0 0 1 0 0
0 1 1 0 J 1 1 0 1
K Q Q
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Q(t+1) = JQ’ + K’Q

41
 Flip-Flops with Direct Inputs

 Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 x x 0
Q
R
Reset

42
 Flip-Flops with Direct Inputs

 Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 x x 0
Q 1 0 ↑ 0
R 1 1 ↑ 1
Reset

Eastern Mediterranean 43
 Flip-Flops with Direct Inputs

 Asynchronous Preset and Clear

Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0

Q
CLR
Reset

44
 Flip-Flops with Direct Inputs

 Asynchronous Preset and Clear

Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0
0 1 x x 1
Q
CLR
Reset

45
 Flip-Flops with Direct Inputs

 Asynchronous Preset and Clear

Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0
0 1 x x 1
Q 1 1 0 ↑ 0
CLR 1 1 1 ↑ 1
Reset

46
 Register

Buffer Register

Shift Register
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Din 1 1 1 1

Q3 1 1 1 1

Q2 0 1 1 1

Q1 0 0 1 1

Q0 0 0 0 1
Application of Shift registers:

(1) Ring Counter

(2) Sequence generator
(3) Johnson Counter

[will be discussed later]

 Basic Application of Counters
• A Counter is a device which stores (and sometimes displays) the number of
times a particular event or process has occurred, often in relationship to a clock
signal.

• Counters are used in digital electronics for counting purpose.

• For example, in UP counter a counter increases count for every rising/ falling
edge of clock.

• A counter can follow the certain sequence based on our design like any random
sequence 0,1,3,2… .

• They are used as frequency dividers where the frequency of given pulse
waveform is divided.

• The main properties of a counter are timing , sequencing , and counting.

Counters are broadly divided into two categories

1. Asynchronous counter

1. Synchronous counter
 Asynchronous counter

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 Synchronous counter

3-bit Synchronous Register

BIT, Mesra
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1. Asynchronous Counter/ Ripple counter

In asynchronous counter we don’t use universal clock, only

first flip flop is driven by main clock and the clock input of rest of the
following flip flop is driven by output of previous flip flops.
or asynchronous counter

Counter pu
or
clock puls

[All FFs are –ve edge triggered]

Counting
sequence
 Sequential Circuits

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Mesra
Application of Shift registers:

(1) Ring Counter

(2) Sequence generator
(3) Johnson Counter

[will be discussed later]

1. Asynchronous Counter/ Ripple counter

In asynchronous counter we don’t use universal clock, only

first flip flop is driven by main clock and the clock input of rest of the
following flip flop is driven by output of previous flip flops.
or asynchronous counter

Counter pu
or
clock puls

[All FFs are –ve edge triggered]

Counting
sequence
 [All FFs are –ve edge triggered, i.e. o/p changes at the –ve edge of
Clock
No. of clock pulse
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

A2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

A3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

A4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0

Timing diagram of UP counter

Down counter
The previous counter was up-counter that counts in increasing order. For reverse
counting a down-counter is used [i.e. 15, 14, 13, 12,….]

Solution:
(1) Either, use +ve edge triggered FF and apply
normal output of the FF to clock input of nex
[if normal output is not available]

(2) Or, keeping the –ve edge triggered FF as its,

apply the complemented output of the FF to
input of next FF
As per the second solution:
Timing diagram of DOWN counter
 Design of MOD-N asynchronous counter

1) Modulus-N, N<2n, n= No. of FFs, counts from decimal 0-to-(N-1)

2) Connect as ripple counter
3) Find the binary of decimal-N
4) Connect all FF outputs that are 1 at the state of the number N as inputs to
an NAND gate
1) Connect the NAND gate output to the ‘clear’ input of all FFs
 MOD-10 counter or BCD counter (asynchronous)

State of FFs:
Q3 Q2 Q1 Q0

Counter counts from 0-to-9, so total no. of count is 10, hence MOD-10
When the state after 1001 i.e. 1010 is about to come all FFs are
cleared so 1010 will not come
Hence, When Q3=1 and Q1=1, FFs are cleared
 Circuit Diagram of MOD-10 counter or BCD counter (asynchronous)

Q3 Q2 Q1 Q0
Timing Diagram

glitches
(asynchronous)
Excitation table
(also
discussed later)
 TA3

A3 A2

A’3
Propagation delay in synchronous counter
Design of sequential Circuits
Using
State Diagram
1
1
An example: state assignment
Unused-states
 Analysis of Clocked Sequential Circuits

 The State
● State = Values of all Flip-Flops

x
A
Example D Q

Q
AB=00

D Q B

CLK Q

118
 Analysis of Clocked Sequential Circuits

 State Equations
x
A
A(t+1) = DA D Q

= A(t) x(t)+B(t) x(t) Q

=Ax+Bx
D Q B
B(t+1) = DB
CLK Q
= A’(t) x(t)
y
= A’ x
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’
119
 Analysis of Clocked Sequential Circuits

 State Table (Transition Table)

x
Present Next D Q A
Input Output
State State
Q
A B x A B y
0 0 0 0 0 0 D Q B
0 0 1 0 1 0
CLK Q
0 1 0 0 0 1
0 1 1 1 1 0 y

1 0 0 0 0 1
1 0 1 1 0 0
A(t+1) = A x + B x
1 1 0 0 0 1
1 1 1 1 0 0 B(t+1) = A’ x
y(t) = (A + B) x’
t t+1 t 120
 Analysis of Clocked Sequential Circuits

 State Table (Transition Table)

x
Present Next State Output D Q A

State x=0 x=1 x=0 x=1 Q

A B A B A B y y
0 0 0 0 0 1 0 0 D Q B
0 1 0 0 1 1 1 0
CLK Q
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0 y

t t+1 t A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
121
 Analysis of Clocked Sequential Circuits

 State Diagram Present Next State Output

State x=0 x=1 x=0 x=1
A B A B A B y y
AB input/output
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
0/0 1/0
1 0 0 0 1 0 1 0
0/1 1 1 0 0 1 0 1 0
00 10
x
D Q A
0/1
Q
1/0 0/1 1/0
D Q B

CLK Q
01 11
y

1/0 122
 Analysis of Clocked Sequential Circuits

 D Flip-Flops
Example: x D Q A
Present Next
y
Input
State State CLK Q
A x y A
0 0 0 0
0 0 1 1 A(t+1) = DA = A  x  y
0 1 0 1
0 1 1 0
1 0 0 1 01,10
1 0 1 0
00,11 0 1 00,11
1 1 0 0
1 1 1 1 01,10
123
 Analysis of Clocked Sequential Circuits

 JK Flip-Flops J Q A

Example: x K Q

Present Next Flip-Flop

I/P J Q B
State State Inputs
A B x A B JA KA JB KB K Q
0 0 0 0 1 0 0 1 0 CLK
0 0 1 0 0 0 0 0 1
JA = B KA = B x’
0 1 0 1 1 1 1 1 0
JB = x’ KB = A  x
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1 A(t+1) = JA Q’A + K’A QA
1 0 1 1 0 0 0 0 0 = A’B + AB’ + Ax
1 1 0 0 0 1 1 1 1 B(t+1) = JB Q’B + K’B QB
1 1 1 1 1 1 0 0 0 = B’x’ + ABx + A’Bx’
124
 Analysis of Clocked Sequential Circuits

 JK Flip-Flops J Q A

x K Q
Example:
Present Next Flip-Flop J Q B
I/P
State State Inputs
A B x A B JA KA JB KB K Q

0 0 0 0 1 0 0 1 0 CLK

0 0 1 0 0 0 0 0 1 1 0 1
0 1 0 1 1 1 1 1 0 00 11
0 1 1 1 0 1 0 0 1
0
1 0 0 1 1 0 0 1 1 0 0
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1 01 10
1
1 1 1 1 1 1 0 0 0 1
125
 Analysis of Clocked Sequential Circuits
x A
 T Flip-Flops T Q y

R Q
Example:
Present Next F.F
I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0
TA = B x TB = x
0 1 1 1 0 1 1 0
y =AB
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0
A(t+1) = TA Q’A + T’A QA
= AB’ + Ax’ + A’Bx
1 1 0 1 1 0 0 1
1 1
B(t+1) = TB Q’B + T’B QB
1 1 1 0 0 1
=xB 126
 Analysis of Clocked Sequential Circuits
x A
 T Flip-Flops T Q y

R Q
Example:
Present Next F.F
I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0 0/0 0/0
0 1 1 1 0 1 1 0 00 1/0 01
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0 1/1 1/0
1 1 0 1 1 0 0 1 11 10
0/1 0/0
1 1 1 0 0 1 1 1 1/0
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