Snoa 998

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Analog Engineer's Circuit

Relaxation Oscillator Circuit
Design Goals
Supply Oscillator Frequency
Vcc Vee f
5V 0V 1 MHz
Design Description
The oscillator circuit generates a square wave at a selected frequency. This is done by charging and discharging
the capacitor, C1 through the resistor, R1. The oscillation frequency is determined by the RC time constant of R1
and C1, and the threshold levels set by the resistor network of R2, R3, and R4. The maximum frequency of the
oscillator is limited by the toggle rate of the comparator and the capacitance load at the output. This oscillator
circuit is commonly used as a time reference or a supervisor clock source.
V+
R2 20k
R4 20k
R3 20k
V+
+ Vo
+V
V+ - TLV3201
Vcc 5
Vc R1 6.8k
C1 100p
Design Notes
1. Comparator toggle rate and output capacitance are critical considerations when designing a high-speed
oscillator.
2. Select C1 to be large enough to minimize the errors caused by stray capacitance.
3. If using a ceramic capacitor, select a COG or NPO type for best stability over temperature.
4. Select lower value resistors for the R2, R3, R4 resistor network to minimize the effects of stray capacitance.
5. R2, R3, and R4 can be adjusted in order to create a duty cycle other than 50%.
SNOA998 – JUNE 2018 Relaxation Oscillator Circuit 1

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Design Steps
1. When R2 = R3 = R4, the resistor network sets the oscillator trip points of the non-inverting input at one-third
and two-thirds of the supply.
2. When the output is high, the upper trip point will be set at two-thirds of the supply to bring the output back
low.
R
Vo = Vs (R ∥R 3)+R = 23 Vs = 3.33V
2 4 3
3. When the output is low, the lower trip point will be set at one-third of the supply in order to bring the output
back high.
3 4R ∥R
Vo = Vs (R ∥R = 13 Vs = 1.67V
3 4)+R2
4. The timing of the oscillation is controlled by the charging and discharging rate of the capacitor C1 through
the resistor R1. This capacitor sets the voltage of the inverting input of the comparator. Calculate the time to
discharge the capacitor.
‐ t
Vc = Vie R1C1
1.67 ‐ R tC
3.33 = e 1 1
t = 0.69R1C1
5. Calculate the time to charge the capacitor.

t
Vi = Vc 1‐e‐ RC
t
1.67 = 3.33 1‐e‐ RC
1.67 ‐ t
3.33 = e RC
t = 0.69R1C1
6. The time for the capacitor to charge or discharge is given by 0.69R1C1. With a target oscillator frequency of
1 MHz, the time to charge or discharge should be 500 ns.
0.69R1C1 = 500ns
R1C1 = 724ns
7. Select C1 as 100 pF and R1 as 6.8 kΩ (the closest real world value).
2 Relaxation Oscillator Circuit SNOA998 – JUNE 2018

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Design Simulations
Transient Simulation Results
T 5.00
4.00
3.00
Output
2.00
1.00
0.00
0.00 1.00u 2.00u 3.00u 4.00u 5.00u
Time (s)
Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
See circuit spice simulation file, SBOMAO3.
For more information on many comparator topics including hysteresis, propagation delay and input common
mode range please see, TI Precision Labs.
Design Featured Comparator
TLV3201
Vss 2.7 V to 5.5 V
VinCM Rail-to-rail
tpd 40 ns
Vos 1 mV
VHYS 1.2 mV
Iq 40 µA
Output Type Push-Pull
#Channels 1
TLV3201
SNOA998 – JUNE 2018 Relaxation Oscillator Circuit 3

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Design Alternate Comparator

TLV7011
Vss 1.6 V to 5.5 V
VinCM Rail-to-rail
tpd 260 ns
Vos 0.5 V
VHYS 4 mV
Iq 5 µA
Output Type Push-Pull
#Channels 1
TLV7011
4 Relaxation Oscillator Circuit SNOA998 – JUNE 2018

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Analog Engineer's Circuit

SNOA998 – JUNE 2018 Relaxation Oscillator Circuit 1

5. Calculate the time to charge the capacitor.

7. Select C1 as 100 pF and R1 as 6.8 kΩ (the closest real world value).

2 Relaxation Oscillator Circuit SNOA998 – JUNE 2018

SNOA998 – JUNE 2018 Relaxation Oscillator Circuit 3

Design Alternate Comparator

4 Relaxation Oscillator Circuit SNOA998 – JUNE 2018

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